ATPL100SK-99

Atmel ATPL100A FSK Power Line Communications SoC SUMMARY DATASHEET Features • Core • ADD8051C3A enhanced 8051 core • Speedups up to x5 vs. standard 8051 microcontroller • • • • 128Kbytes internal SRAM In-circuit serial flash programming Auto boot-loading program from serial flash Media Access Control • Convolutional and block (FEC) channel coding, Viterbi decoding • Hardware CRC error detection and FEC error correction • By-pass mode to support earlier no-MAC FSK modem software • Modem • • • • • • Power Line Carrier Modem for 50 and 60 Hz mains 8 Programmable Carrier Frequencies from 60 to 132.5KHz Baud rate Selectable: 600 to 4800 bps Half Duplex communication Receiver Sensitivity: Up to 44dBμVrms Peripherals • Three 2-wire UARTs • Two SPI. SPI to serial flash and External RTC. Buffered SPI to external metering • • • • • IC Programmable Watchdog Quad dimmer in/out 24x8/28x4 segments LCD driver Up to 20 I/O lines Package • 144-lead LQFP, 16 x 16 mm, pitch 0.4 mm • Pb-free and RoHS compliant • Typical Applications • Automated Meter Reading (AMR) & Advanced Meter Management (AMM) • Street lighting • Home Automation 43002A-ATPL-03/12 Description The ATPL100A is a Power Line Communications System on Chip. It implements a full PLC node using FSK modulations and includes a hardwired Medium Access Controller (ADD1210). It has been developed to reduce the CPU computational load in PLC systems. Thus, the microcontroller is free to be used in the applications tasks. MAC functional capabilities of ATPL100A (performed in ADD1210 Medium Access Controller) involve the construction of message packets, adding convolutional or FEC (Forward Error Correction) codes to bytes and FCS (Frame Check Sequence) to packets. In reception, the MAC provides frame detection and Viterbi decoding or FCS and FEC correction. ATPL100A MAC design is versatile and allows users to create a wide range of datagram structures. The MAC can be set in a bypass mode allowing direct connection between the microcontroller and the modem to support old FSK software that doesn’t include the MAC. ATPL100A PLC modem (ADD1310) can use a single power supply of 3.3V and a few external components. It supports several Analog Front End (AFE) configurations suitable for Automatic Meter Reading (AMR) or Home Automation. It can replace the traditional analog PLC modem and can use the same software libraries or a simplified version if the hardwired MAC is used. ATPL100A core (ADD8051C3A) includes all features of the standard 8051, with an average speed up x5 and some additional features. The microcontroller includes some specific peripherals as a 4 input / 4 output dimmer for power regulation (phase angle control), also being able to generate a PWM (Pulse-Width Modulation) control. A flash program loader allows to store the microcontroller program in a standard SPI serial flash memory and to execute it from internal SRAM. In the start-up process the program is uploaded from serial flash to the internal 128Kbytes of SRAM before start execution, after start-up the free space in the serial flash can be used to store application data. ATPL100A includes an encryption engine for code protection. Using a larger flash, several programs can be stored at the same time and the microcontroller can switch from one program to another, this feature could be used to reprogram the SoC using PLC downloading. Atmel ATPL100A [Summary datasheet] 43002A-ATPL-03/12 2 1. Block Diagram Figure 1-1. ATPL100A 144-pin Block Diagram DEBUG D_INIT RSTA Reset Interface RESET 11.059.200Hz CLKA Clock VDD Power Management DEBUG VSSO LDO_PD VDEO Clock Interface CLKB 8051C3A Core IDATA INT1 TDI TDO TCK TRST TMS JTAG Bscan 128KB SRAM CODE SRAM XDATA SRAM P1.7 P3(1,2), P3(3:5) P4(0:7) P5(0:5) GENERAL PURPOSE I/O TRIAC_(3:0) VNR INTA(3:0) INTB(3:0) INTC(3:0) INTD(3:0) SEGM(23:20) SEGM(19:0) BCKP(7:4) BCKP(3:0) DIMMER PERIPHERAL M U X LCD DRIVER MEDIUM ACCESS CONTROL VSENSE PSENSE EMIT(12:0) ENABLE DC_COMP D_IN D_NIN REC(8:1) VIN VRH VRL /PROG BOOT LOADER SECURED SSN SPI0 MISO, MOSI, CLK, SS SPI1 MISO1, MOSI1, CLK1, SS1 UART0 Rx0, Tx0 UART1 Rx1, Tx1 UART2 Rx2, Tx2 TIMER0 T0 TIMER1 T1 T2 TIMER2 PLC MODEM AVD T2EX T11, T12, T14 WATCHDOG /EWDG AVS Atmel ATPL100A [Summary datasheet] 43002A-ATPL-03/12 3 2. Package and Pinout 2.1 144-Lead LQFP Package Outline Figure 2-1. Orientation of the 144-Lead Package 108 73 109 72 144 37 1 36 Atmel ATPL100A [Summary datasheet] 43002A-ATPL-03/12 4 2.2 144-Lead LQFP Pinout Table 2-1. ATPL100A 144-Lead LQFP pinout 1 P3.3/INT1 37 TRIAC_0 73 P4.0/RXD2 109 BCKP_3 2 VCC 38 P5.5/TXD1/INTA1 74 VCC 110 BCKP_2 3 GND 39 P5.4/RXD1/INTA0 75 GND 111 BCKP_1 4 GND 40 P4.7/T2EX/INTA3 76 SEGM_23/INTC3 112 BCKP_0 5 GND 41 P4.6/T2/INTA2 77 SEGM_22/INTC2 113 GND 6 TDI 42 P1.7/SSN 78 SEGM_21/INTC1 114 DC_COMP 7 TDO 43 VCC 79 SEGM_20/INTC0 115 VCC 8 TCK 44 GND 80 SEGM_19 116 ENABLE 9 TMS 45 EMIT.0 81 SEGM_18 117 GND 10 TRST 46 EMIT.1 82 SEGM_17 118 DNIN 11 D_INIT 47 EMIT.2 83 SEGM_16 119 DIN 12 RSTA 48 VCC 84 SEGM_15 120 REC_1 13 /PROG 49 GND 85 SEGM_14 121 REC_2 14 SECURED 50 EMIT.3 86 SEGM_13 122 REC_3 15 /EWDG 51 EMIT.4 87 SEGM_12 123 REC_4 16 DEBUG 52 EMIT.5 88 SEGM_11 124 REC_5 17 VCC 53 EMIT.6 89 VDD 125 REC_6 18 CLKEB 54 VCC 90 VCC 126 REC_7 19 GND 55 GND 91 GND 127 REC_8 20 CLKEA 56 EMIT.7 92 SEGM_10 128 VCC 21 VCC 57 EMIT.8 93 SEGM_9 129 GND 22 GND 58 EMIT.9 94 SEGM_8 130 VRL 23 GND 59 EMIT.10 95 SEGM_7 131 VIN 24 VDEO 60 VCC 96 SEGM_6 132 VRH 25 VDEO 61 GND 97 SEGM_5 133 AVD1 26 VSSO 62 EMIT.11 98 SEGM_4 134 AVS1 27 LDO_PD 63 EMIT.12 99 SEGM_3 135 AVD2 28 VDD 64 VCC 100 SEGM_2 136 AVS2 29 GND 65 GND 101 SEGM_1 137 VCC 30 VCC 66 P3.1/TXD0 102 SEGM_0 138 GND 31 VSENSE 67 P3.0/RXD0 103 VCC 139 P5.3/MISO0 32 PSENSE 68 P4.5/MISO1/INTB3 104 GND 140 P5.2/MOSI0 33 VNR 69 P4.4/MOSI1/INTB2 105 BCKP_7/SEGM_27/INTD3 141 P5.1/SPICLK0 34 TRIAC_3 70 P4.3/SPICLK1/INTB1 106 BCKP_6/SEGM_26/INTD2 142 P5.0/SS0 35 TRIAC_2 71 P4.2/SS1/INTB0 107 BCKP_5/SEGM_25/INTD1 143 P3.5/T1 36 TRIAC_1 72 P4.1/TXD2 108 BCKP_4/SEGM_24/INTD0 144 P3.4/T0 Atmel ATPL100A [Summary datasheet] 43002A-ATPL-03/12 5 3. Mechanical Characteristics Figure 3-1. 144-lead LQFP Package Mechanical Drawing Lead pitch 0.40 mm Pa ck age width ⋅ pack age length 16.0 ⋅ 16.0 mm Lead shape Gullwing Sealing method Plastic mold Mounting height 1.70 mm MAX We ight 0.88 g Note 1) * : These dimensions include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder. 18.00±0.20(.709±.008)SQ +0.40 +.016 * 16.00 –0.10 .630 –.004 SQ 73 108 72 109 0.08(.003) Details of "A" part 1.50 +0.20 –0.10 .059 +.008 –.004 (Mounting height) INDEX 0~8 ˚ 37 144 LEAD No. 1 0.60±0.15 (.024±.006) 36 0.40(.016) C "A" 2003 FUJITSU LIMITED F144024S-c-3-3 0.18±0.035 .007±.001 0.07(.003) M 0.145 +0.05 –0.03 .006 +.002 –.001 0.10±0.05 (.004±.002) (Stand off) 0.25(.010) Dimensions in mm (inches). Note: The values in parentheses are reference values. Atmel ATPL100A [Summary datasheet] 43002A-ATPL-03/12 6 4. Recommended mounting conditions 4.1 Conditions of Standard Reflow Table 4-1. Conditions of standard Reflow Items Contents Method IR(Infrared Reflow)/Convection Times 2 Before unpacking Please use within 2 years after production From unpacking to second reflow Within 8 days In case over period of floor life Baking with 125ºC +/- 3ºC for 24hrs +2hrs/-0hrs is required. Then please use within 8 days. (please remember baking is up to 2 times) Floor Life Floor Life Condition Between 5ºC and 30ºC and also below 70%RH required. (It is preferred lower humidity in the required temp range.) Figure 4-1. Temperature Profile Temperature 260ºC 255ºC Liquidous Temperature 170-190ºC RT b c a Note: d d’ e Time H rank: 260ºC Max a: Average ramp-up rate: 1ºC/s to 4ºC/s b: Preheat & Soak: 170ºC to 190ºC, 60s to 180s c: Average ramp-up rate: 1ºC/s to 4ºC d: Peak temperature: 260ºC Max, up to 255ºC within 10s d’: Liquidous temperature: Up to 230ºC within 40s or Up to 225ºC within 60s or Up to 220ºC within 80s e: Cooling: Natural cooling or forced cooling Atmel ATPL100A [Summary datasheet] 43002A-ATPL-03/12 7 5. Ordering Information Table 5-1. Atmel ATPL100A Ordering Codes Atmel Ordering Code Package Package Type Temperature Range ATPL100A-AZU-Y 144 LQFP Pb-Free Industrial (-40ºC to 85º) A T P L 1 0 0 A - A Z U - Y x x Atmel Designator Customer marking AT=Atmel Product Family PL=Power Line Communications Device Designator Device Revision Shipping Carrier Option Y = Tray Package Device Grade or Wafer/Die Thickness U = Lead free (Pb-free) Industrial temperature range (-40°C to +85°C) Package Option AZ = 144LQFP Atmel ATPL100A [Summary datasheet] 43002A-ATPL-03/12 8 6. Revision History Doc. Rev. Date Comments 1.00 30/03/2012 Initial release Atmel ATPL100A [Summary datasheet] 43002A-ATPL-03/12 9 Atmel Corporation Atmel Asia Limited Atmel Munich GmbH Atmel Japan G.K. 2325 Orchard Parkway Unit 01-5 & 16, 19F Business Campus 16F Shin-Osaki Kangyo Building San Jose, CA 95131 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki USA 418 Kwun Tong Road D-85748 Garching b. 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