ATSAMA5D44B-CU

32-BIT ARM-BASED MICROPROCESSORS SAMA5D4 Series SAMA5D41 /42 /43 /44 Description The SAMA5D4 Series is a high-performance, power-efficient Arm® Cortex®-A5 processor-based MPU capable of running at up to 600 MHz. It integrates the Arm NEON™ SIMD engine for accelerated signal processing, multimedia and graphics, as well as a 128 KB L2-Cache for high system performance. The device features the Arm TrustZone® enabling a strong security perimeter for critical software, as well as several hardware security features. The device also features advanced user interface and connectivity peripherals. The SAMA5D4 devices have three software-selectable low-power modes: Idle, Ultra-low-power, and Backup. In Idle mode, the processor is stopped while all other functions can be kept running at normal operating bus frequency. In Ultralow-power mode, the processor is stopped while all other functions can be kept running at minimum operating bus frequency. In Backup mode, only the real-time clock, real-time timer, backup SRAM, backup registers, and wakeup logic are running. The SAMA5D4 features an internal multi-layer bus architecture associated with 32 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device supports DDR2/LPDDR/LPDDR2 and SLC/MLC NAND Flash memory with 24-bit ECC. The comprehensive peripheral set includes a 720p hardware video decoder, an LCD controller with overlays for hardware-accelerated image composition, a resistive touchscreen function, and a CMOS sensor interface. Connectivity peripherals include a dual 10/100 Ethernet MAC with IEEE1588, three HS USB ports, UARTs, SPIs and I2Cs. Security features include an “on-the-fly” encryption-decryption process from the external DDR memory, tamper detection pins, secure storage of critical data, an integrity check monitor (ICM) to detect modification of the memory contents and a secure boot. The product also includes a dedicated coprocessor for public key cryptography such as RSA and elliptic curves algorithms (ECC), as well as AES, 3DES, SHA function and TRNG. These features protect the system against counterfeiting, safeguard sensitive data, authenticate safe programs and secure external data transfers. The SAMA5D4 series is optimized for control panel/HMI applications needing video playback and applications that require high levels of connectivity in the industrial and consumer market. Its security features make the SAMA5D4 well suited for secure gateways or for the IoT. Features • Arm Cortex-A5 Core - Armv7-A Thumb2® instruction set - Arm TrustZone - NEON Media Processing Engine - 945 MIPS @ 600 MHz in worst conditions • Memory Architecture - Memory Management Unit - 32 Kbyte Data Cache, 32 Kbyte Instruction Cache - 128 Kbyte L2 Cache - One 128 Kbyte scrambled internal ROM single-cycle access at system speed, embedding Microchip boot loader/Microchip Secure boot loader - One 128 Kbyte scrambled internal SRAM, single-cycle access at system speed - High-bandwidth scramblable 16-bit or 32-bit Double Data Rate Multi-port Dynamic RAM Controller supporting 512 Mbyte 8-bank DDR2/LPDDR/LPDDR2, including partial areas “on-the-fly” AES encryption/decryption  2017 Microchip Technology Inc. DS60001525A-page 1 SAMA5D4 SERIES - EBI (External Bus interface) supporting:  16-bit NAND Flash controller, including 24-bit error correction code (PMECC) for 8-bit NAND Flash  Independent Static Memory Controller (SMC) with datapath scrambling • System running up to 200 MHz in worst conditions - Power-on Reset Cells, Reset Controller, Shutdown Controller, Periodic Interval Timer, Watchdog Timer and secure Real-time Clock - Internal regulator - One 600–1200 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed - Internal Low-power 12 MHz RC Oscillator - Low-power 32 kHz RC Oscillator - Selectable 32.768 KHz Low-power oscillator and 12 MHz Oscillator - Two 64-bit, 16-channel DMA Controllers - 64-bit Advanced Interrupt Controller - 64-bit Secure Advanced Interrupt Controller - Three Programmable External Clock Signals - Programmable fuse box with 512 fuse bits available for customer, including JTAG protection • Three Low-power Modes: Idle, Ultra-low-power, and Backup • Peripherals - Video Decoder (VDEC) supporting formats MPEG-4, H.264, H.263, VP8 and JPEG, and image postprocessing - LCD TFT Controller with 4 overlays up to 2048x2048 or up to 720p in video format, with rotation and alpha blending - ITU-R BT. 601/656 Image Sensor Interface (ISI) - One High-Speed USB Device, Three High-Speed USB Host with On-chip Transceiver - Two 10/100 Mbps Ethernet MAC Controllers with IEEE 1588 v2 support - Software Modem Interface (SMD) - Two high-speed memory card hosts (eMMC 4.3 and SD 2.0) - Three Master/Slave Serial Peripheral Interfaces (SPI) - Five USARTs, two UARTs, one DBGU - Two Synchronous Serial Controllers (SSC) - Four Two-wire Interfaces up to 400 Kbits/s supporting I2C protocol and SMBUS (TWI) - Three 3-channel 32-bit Timer/Counters (TC) - One 4-channel 16-bit PWM Controller - One 5-channel 10-bit Analog-to-Digital Converter with Resistive Touchscreen function • Safety - Internal and external memory integrity monitoring, with Integrity Check Monitor (ICM) based on SHA256 - Power-on Reset Cells - Main Crystal Clock Failure Detector - Independent Watchdog - Register Write Protection - Memory Management Unit • Security - 512 bits of scrambled and erasable registers(1) - 8 Kbytes of internal scrambled RAM with non-imprinting support, 6 Kbytes are erasable(1) - 8 PIOBU tamper pins for static or dynamic intrusion detections(1) - Microchip secure boot(2) ______________________________ Note: 1: This feature is described in the document “Secure Box Module (SBM)”, Literature No. 11254. This document is available under Non-Disclosure Agreement (NDA). Contact a Microchip Sales Representative for further details. 2: For secure boot strategies, refer to the application note “SAMA5D4x Secure Boot Strategy”, Literature No. 11295. This document is available under Non-Disclosure Agreement (NDA). Contact a Microchip Sales Representative for further details. DS60001525A-page 2  2017 Microchip Technology Inc. SAMA5D4 SERIES • Cryptography - True Random Number Generator (TRNG), compliant with NIST special publication 800-22 test suite and FIPS PBUs 140-2 and 140-3 - SHA: Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512) compliant with FIPS publications 180-2 - AES: 256-bit, 192-bit, 128-bit Key Algorithm, compliant with FIPS PUB 197 specifications - Advanced Encryption Standard Bridge (AESB): AES 128 that includes Automatic Bridge Mode for automatic DDR port Encryption/ Decryption - TDES: Two-key or Three-key Algorithms, compliant with FIPS PUB 46-3 specifications - Public Key Coprocessor (CPKCC) and associated Classical Public Key Cryptography Library (CPKCL) for RSA, DSA, ECC GF(2n), ECC GF(p)(1) • Up to 152 I/Os - Five Parallel Input/Output Controllers with slew rate control on high-speed I/Os - Input Change Interrupt capability on each I/O Line, selectable Schmitt Trigger input - Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering • Packages - 361-ball stubless TFBGA, 16x16 mm body, pitch 0.8 mm - 289-ball stubless LFBGA, 14x14 mm body, pitch 0.8 mm • SAMA5D4 Series Devices Device Package Video Decoder DDR Datapath SAMA5D44 TFBGA361 X 32 bits SAMA5D43 LFBGA289 X 16 bits SAMA5D42 TFBGA361 – 32 bits SAMA5D41 LFBGA289 – 16 bits ______________________________ Note 1: CPKCC and CPKCL are described in the application note “Using CPKCL Version 02.05.01.xx on SAMA5D4”, Literature No. 11247. This document is available under Non-Disclosure Agreement (NDA). Contact a Microchip Sales Representative for further details.  2017 Microchip Technology Inc. DS60001525A-page 3 Block Diagram PLLUTMI HS Trans PIO FIQ VDDBU XIN32 XOUT32 AIC PIOBU[7..0] HS EHCI USB HOST HS USB Device GMAC0 GMAC1 10/100 32 KB DCache DMA DMA DMA DMA LCD ISI DMA DMA LN CA R_ DD Fuse Box Scrambling Backup Area ROM 128 KB RTC SMD 4-ch. PWM TC0 TC1 TC2 SRAM 128 KB TWI0 TWI1 TWI2 TWI3 16-ch. DMA0 USART0 USART1 USART2 USART3 USART4 TRNG CPKCC SPI0 SPI1 SPI2 UART0 UART1 PIO SHA AES TDES ICM (SHA) SSC0 SSC1 Peripheral Bridge 0 Peripheral Bridge 1 A0/NBS0 A1–A20 A23–A25 NWR1/NBS1 NCS0, NCS1, NCS2 NWAIT Reduced Static Memory Controller Scrambling 32.768 kHz 64 KHz RC Crystal Osc SHDWC D0–D15 A21/NANDALE A22/NANDCLE NRD/NANDOE NWE/NWR0/NANDWE NCS3/NANDCS NANDRDY NAND Flash Controller MCL/SLC ECC (4 KB SRAM) TrustZone Secured Multi-Layer Matrix SECURAM 8 KB + 512 bits DDR2 LPDDR LPDDR2 512 MB Secured EBI RSTC POR DDR_DQM[3..0] DDR_DQS[3..0] DDR_DQSN[3..0] DDR_CS DDR_CLK, DDR_CLKN DDR_CKE DDR_RAS, DDR_CAS DDR_WE DDR_BA[2..0] Scrambling 128 KB L2 Cache I/D POR DD R_ CA LP LC D LC DA D T[ LC _VS 0:23 D Y ] LC _PC NC D_ K , L DE , LC CD N, D_ _H LC D SY IS D_ ISP NC I_ PW IS D[0 I_V :11 M IS SY ] I_P N C CK , I , IS SI_ I_M HS CK YNC Video Decoder DBGU SHDN WKUP MMU NEON FPU 16-ch. DMA1 5-ch. 10-bit ADC Touchscreen MCI0/MCI1 SD/SDIO eMMC PIO PIO DI B PW DI P B M PW H N [ PW ML 3:0] M [3:0 FI ] TI [1:0 O ] TI A[5 O :0 TC B[5 ] LK :0] [5 TW :0] TW D[ CK 3:0 [3 ] : CT 0] S RT [4:0 ] SCS[4 :0 RX K[4 ] : 0 D ] TX [4: D[ 0] UR 4:0 ] X UT D[1 XD :0] NP [1:0 CS ] [3 SP :0] C M K O M SI IS O  2017 Microchip Technology Inc. Key TrustZone Access Right Management SPI0_, SPI1_, SPI2_ VR AD EF T AD RIG [0: 4] NRST Cortex-A5 32 KB ICache PA xxx Always Secured xxx Programmable Secured xxx Secured and Non-Secured xxx Always Non-Secured AD VDDCORE DDR_A0–DDR_A13 DDR_D0–DDR_D31 PIO TK TF[1:0 TD[1: ] 0 RD[1:0] [1 ] RF :0 [ ] RK 1:0 [1 ] :0 M ] CI x_ M M C CI C DA M 0_ Ix_ CI D C 0_ A[ K D 7. M MC B[3 .0] CI I0 .. 1_ _C 0] DA D [3 B ..0 ] DTXD PIT Scrambling DRXD Trust Zone SAIC PIO IRQ PC PB In-Circuit Emulator PMC WDT HS Trans PIO PIO 12 MHz RC Osc PCK0–PCK2 HS Trans JTAG / SWD 12 MHz Osc AESB PLLA XIN XOUT DH S DH DP SD /HH M/ SD HH PA Gx SD _T MA Gx XC _T K– Gx XE G _ N x_ Gx CR –G RX _ S– x_ CK Gx RXD Gx TX _ V _C ER Gx RX[ , Gx OL _T 0:3 _R Gx X[ ] XE 0 R Gx_MD :3] _M C DI O TST HH S HH DPC SD HH MC HHSDP S B VB DMB G Block Diagram NT RS TD T I TD O TM TC S/SW K/S D WC IO LK JTA GS EL Figure 1-1: SAMA5D4 SERIES DS60001525A-page 4 1. SAMA5D4 SERIES 2. Signal Description Table 2-1 gives details on signal names classified by peripheral. Table 2-1: Signal Description List Signal Name Function Type Active Level Input – Output – Input – Clocks, Oscillators and PLLs XIN Main Oscillator Input XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output Output – VBG Bias Voltage Reference for USB Analog – PCK0–PCK2 Programmable Clock Output Output – Output – Input – Shutdown, Wakeup Logic SHDN Shutdown Control WKUP Wakeup Input ICE and JTAG TCK/SWCLK Test Clock/Serial Wire Clock Input – TDI Test Data In Input – TDO Test Data Out Output – TMS/SWDIO Test Mode Select/Serial Wire Input/Output I/O – JTAGSEL JTAG Selection Input – Reset/Test NRST Microprocessor Reset Input Low TST Test Mode Select Input – NTRST Test Reset Signal Input – Debug Unit - DBGU DRXD Debug Receive Data Input – DTXD Debug Transmit Data Output – Input – Input – Advanced Interrupt Controller - AIC IRQ External Interrupt Input Secured Advanced Interrupt Controller - SAIC FIQ Fast Interrupt Input PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE PA0–PAxx Parallel IO Controller A I/O – PB0–PBxx Parallel IO Controller B I/O – PC0–PCxx Parallel IO Controller C I/O – PD8–PDxx Parallel IO Controller D I/O – PE0–PExx Parallel IO Controller E I/O –  2017 Microchip Technology Inc. DS60001525A-page 5 SAMA5D4 SERIES Table 2-1: Signal Description List (Continued) Signal Name Function Type Active Level I/O – Output – Input Low External Bus Interface - EBI D0–D15 Data Bus A0–A25 Address Bus NWAIT External Wait Signal Static Memory Controller - SMC NCS0–NCS3 Chip Select Lines Output Low NWR0–NWR1 Write Signal Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0–NBS1 Byte Mask Signal Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low DDR2/LPDDR2 Controller DDR_CK,DDR_CKN DDR2 Differential Clock Output – DDR_CKE DDR2 Clock Enable Output High DDR_CS DDR2 Controller Chip Select Output Low DDR_BA[2..0] Bank Select Output Low DDR_WE DDR2 Write Enable Output Low DDR_RAS, DDR_CAS Row and Column Signal Output Low DDR_A[13..0] DDR2 Address Bus Output – DDR_D[31..0] DDR2 Data Bus I/O/-PD – DDR_DQS[3..0], DDR_DQSN[3..0] Differential Data Strobe I/O-PD – DDR_DQM[3..0] Write Data Mask Output – DDR_CALP, DDR_CALN DDR2/LPDDR2 Calibration Input – DDR_VREF DDR2/LPDDR2 Reference Input – High Speed Multimedia Card Interface - HSMCIx [1..0] MCI0_CK, MCI1_CK Multimedia Card Clock I/O – MCI0_CDA, MCI0_CDB, MCI1_CDA Multimedia Card Command I/O – MCI0_DA[7..0] Multimedia Card 0 Data slot A I/O – MCI0_DB[3..0] Multimedia Card 0 Data slot B I/O – MCI1_DA[3..0] Multimedia Card 1 Data I/O – Universal Synchronous Asynchronous Receiver Transmitter - USARTx [4..0] SCKx USARTx Serial Clock I/O – TXDx USARTx Transmit Data Output – RXDx USARTx Receive Data Input – RTSx USARTx Request To Send Output – DS60001525A-page 6  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 2-1: Signal Description List (Continued) Signal Name CTSx Function USARTx Clear To Send Type Active Level Input – Universal Asynchronous Receiver Transmitter - UARTx [1..0] UTXDx UARTx Transmit Data Output – URXDx UARTx Receive Data Input – Synchronous Serial Controller - SSCx [1..0] TDx SSC Transmit Data Output – RDx SSC Receive Data Input – TKx SSC Transmit Clock I/O – RKx SSC Receive Clock I/O – TFx SSC Transmit Frame Sync I/O – RFx SSC Receive Frame Sync I/O – Input – Timer/Counter - TCx [8..0] TCLKx TC Channel x External Clock Input TIOAx TC Channel x I/O Line A I/O – TIOBx TC Channel x I/O Line B I/O – Serial Peripheral Interface - SPIx [2..0] SPIx_MISO Master In Slave Out I/O – SPIx_MOSI Master Out Slave In I/O – SPIx_SPCK SPI Serial Clock I/O – SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPIx_NPCS[3..1] SPI Peripheral Chip Select Output Low Two-wire Interface - TWIx [3..0] TWDx Two-wire Serial Data I/O – TWCKx Two-wire Serial Clock I/O – Pulse Width Modulation Controller - PWM PWMH0–3 PWM Waveform Output High – Output PWML0–3 PWM Waveform Output Low – Output PWMFI0–1 PWM Fault Inputs – Input USB Host High Speed Port - UHPHS HHSDPA USB Host Port A High Speed Data + Analog – HHSDMA USB Host Port A High Speed Data - Analog – HHSDPB USB Host Port B High Speed Data + Analog – HHSDMB USB Host Port B High Speed Data - Analog – HHSDPC USB Host Port C High Speed Data + Analog – HHSDMC USB Host Port C High Speed Data - Analog – USB Device High Speed Port - UDPHS  2017 Microchip Technology Inc. DS60001525A-page 7 SAMA5D4 SERIES Table 2-1: Signal Description List (Continued) Signal Name Function Type Active Level DHSDP USB Device High Speed Data + Analog – DHSDM USB Device High Speed Data - Analog – Ethernet 10/100 - GMACx [1..0] GxTXCK Transmit Clock or Reference Clock Input – GxRXCK Receive Clock Input – GxTXEN Transmit Enable Output – GxTX0–3 Transmit Data Output – GxTXER Transmit Coding Error Output – GxRXDV Receive Data Valid Input – GxRX0–3 Receive Data Input – GxRXER Receive Error Input – GxCRS Carrier Sense and Data Valid Input – GxCOL Collision Detect Input – GxMDC Management Data Clock Output – GxMDIO Management Data Input/Output I/O – LCD Controller - LCDC LCDDAT0–23 LCD Data Bus Output – LCDVSYNC LCD Vertical Synchronization Output – LCDHSYNC LCD Horizontal Synchronization Output – LCDPCK LCD Pixel Clock Output – LCDDEN LCD Data Enable Output – LCDPWM LCDPWM for Contrast Control Output – LCDDISP LCD Display ON/OFF Output – Analog – Input – Analog – I/O – Touchscreen Analog-to-Digital Converter - ADC AD0–4 4 Analog Inputs ADTRG ADC Trigger ADVREF ADC Reference Secure Box Module - SBM PIOBU0–7 Secured I/Os Image Sensor Interface - ISI ISI_D0–ISI_D11 Image Sensor Data Input – ISI_HSYNC Image Sensor Horizontal Synchro Input – ISI_VSYNC Image Sensor Vertical Synchro Input – ISI_PCK Image Sensor Data clock Input – I/O – Software Modem Device - SMD DIBN DS60001525A-page 8 Software Modem Signal  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 2-1: Signal Description List (Continued) Signal Name DIBP  2017 Microchip Technology Inc. Function Software Modem Signal Type Active Level I/O – DS60001525A-page 9 SAMA5D4 SERIES 3. Package and Pinout The SAMA5D4 product is available in two packages: • 361-ball TFBGA • 289-ball LFBGA The pinouts are provided in the following Section 3.1 “361-ball TFBGA Package Pinout” and Section 3.2 “289-ball LFBGA Package Pinout”. The package mechanical characteristics are described in Section 57. “Mechanical Characteristics”. DS60001525A-page 10  2017 Microchip Technology Inc. SAMA5D4 SERIES 3.1 361-ball TFBGA Package Pinout Table 3-1: TFBGA361 Pin Description Primary Pin Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST A7 VDDIOP GPIO PA0 I/O – – LCDDAT0 O – – TMS I TMS, PU, ST F6 VDDIOP GPIO PA1 I/O – – LCDDAT1 O – – – – PIO, I, PU, ST E6 VDDIOP GPIO_CLK PA2 I/O – – LCDDAT2 O G1_TXCK I – – PIO, I, PU, ST C6 VDDIOP GPIO_CLK PA3 I/O – – LCDDAT3 O G1_RXCK I – – PIO, I, PU, ST D6 VDDIOP GPIO PA4 I/O – – LCDDAT4 O G1_TXEN O – – PIO, I, PU, ST B6 VDDIOP GPIO PA5 I/O – – LCDDAT5 O G1_TXER O – – PIO, I, PU, ST A6 VDDIOP GPIO PA6 I/O – – LCDDAT6 O G1_CRS I – – PIO, I, PU, ST E5 VDDIOP GPIO PA7 I/O – – LCDDAT7 O – – – – PIO, I, PU, ST A5 VDDIOP GPIO PA8 I/O – – LCDDAT8 O – – TCK I TCK, PU F4 VDDIOP GPIO PA9 I/O – – LCDDAT9 O G1_COL I – – PIO, I, PU, ST F5 VDDIOP GPIO PA10 I/O – – LCDDAT10 O G1_RXDV I – – PIO, I, PU, ST D5 VDDIOP GPIO PA11 I/O – – LCDDAT11 O G1_RXER I – – PIO, I, PU, ST G5 VDDIOP GPIO PA12 I/O – – LCDDAT12 O G1_RX0 I – – PIO, I, PU, ST C5 VDDIOP GPIO PA13 I/O – – LCDDAT13 O G1_RX1 I – – PIO, I, PU, ST E4 VDDIOP GPIO PA14 I/O – – LCDDAT14 O G1_TX0 O – – PIO, I, PU, ST B5 VDDIOP GPIO PA15 I/O – – LCDDAT15 O G1_TX1 O – – PIO, I, PU, ST H6 VDDIOP GPIO PA16 I/O – – LCDDAT16 O – – NTRST D4 VDDIOP GPIO PA17 I/O – – LCDDAT17 O – – – – PIO, O, LOW G4 VDDIOP GPIO PA18 I/O – – LCDDAT18 O G1_RX2 I – – PIO, O, LOW C4 VDDIOP GPIO PA19 I/O – – LCDDAT19 O G1_RX3 I – – PIO, O, LOW A3 VDDIOP GPIO PA20 I/O – – LCDDAT20 O G1_TX2 O – – PIO, I, PU, ST B4 VDDIOP GPIO PA21 I/O – – LCDDAT21 O G1_TX3 O – – PIO, I, PU, ST B3 VDDIOP GPIO PA22 I/O – – LCDDAT22 O G1_MDC O – – PIO, I, PU, ST A4 VDDIOP GPIO PA23 I/O – – LCDDAT23 O G1_MDIO I/O – – PIO, I, PU, ST H5 VDDIOP GPIO_CLK PA24 I/O – – LCDPWM O PCK0 O – – PIO, I, PU, ST F3 VDDIOP GPIO PA25 I/O – – LCDDISP O TD0 O – – PIO, I, PU, ST E3 VDDIOP GPIO PA26 I/O – – LCDVSYNC O PWMH0 O SPI1_NPCS1 O PIO, I, PU, ST H4 VDDIOP GPIO PA27 I/O – – LCDHSYNC O PWML0 O SPI1_NPCS2 O PIO, I, PU, ST G3 VDDIOP GPIO_CLK2 PA28 I/O – – LCDPCK O PWMH1 O SPI1_NPCS3 O PIO, I, PU, ST J5 VDDIOP GPIO PA29 I/O – – LCDDEN O PWML1 O – – PIO, I, PU, ST D3 VDDIOP GPIO PA30 I/O – – TWD0 I/O – – – – PIO, I, PU, ST J4 VDDIOP GPIO PA31 I/O – – TWCK0 O – – – – PIO, I, PU, ST C3 VDDIOP GPIO_CLK PB0 I/O – – G0_TXCK I – – – – PIO, I, PU, ST A2 VDDIOP GPIO_CLK PB1 I/O – – G0_RXCK I SCK2 I/O ISI_PCK I PIO, I, PU, ST B2 VDDIOP GPIO PB2 I/O – – G0_TXEN O – – – – PIO, I, PU, ST C2 VDDIOP GPIO PB3 I/O – – G0_TXER O CTS2 I ISI_VSYNC I PIO, I, PU, ST  2017 Microchip Technology Inc. I NTRST, PU, ST DS60001525A-page 11 SAMA5D4 SERIES Table 3-1: TFBGA361 Pin Description (Continued) Primary Pin Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST I PIO, I, PU, ST J3 VDDIOP GPIO PB4 I/O – – G0_CRS I RXD2 I ISI_HSYNC H2 VDDIOP GPIO PB5 I/O – – G0_COL I TXD2 O PCK2 G2 VDDIOP GPIO PB6 I/O – – G0_RXDV I – – – – PIO, I, PU, ST H3 VDDIOP GPIO PB7 I/O – – G0_RXER I – – – – PIO, I, PU, ST F2 VDDIOP GPIO PB8 I/O – – G0_RX0 I – – – – PIO, I, PU, ST J2 VDDIOP GPIO PB9 I/O – – G0_RX1 I – – – – PIO, I, PU, ST F1 VDDIOP GPIO_CLK PB10 I/O – – G0_RX2 I PCK2 O PWML1 O PIO, I, PU, ST K4 VDDIOP GPIO PB11 I/O – – G0_RX3 I RTS2 O PWMH1 O PIO, I, PU, ST D2 VDDIOP GPIO PB12 I/O – – G0_TX0 O – – – – PIO, I, PU, ST K3 VDDIOP GPIO PB13 I/O – – G0_TX1 O – – – – PIO, I, PU, ST A1 VDDIOP GPIO PB14 I/O – – G0_TX2 O SPI2_NPCS1 O PWMH0 O PIO, I, PU, ST E2 VDDIOP GPIO PB15 I/O – – G0_TX3 O SPI2_NPCS2 O PWML0 O PIO, I, PU, ST B1 VDDIOP GPIO PB16 I/O – – G0_MDC O – – – – PIO, I, PU, ST K5 VDDIOP GPIO PB17 I/O – – G0_MDIO I/O – – – – PIO, I, PU, ST K2 VDDIOP GPIO PB18 I/O – – SPI1_MISO I/O D8 I/O – – PIO, I, PU, ST C1 VDDIOP GPIO PB19 I/O – – SPI1_MOSI I/O D9 I/O – – PIO, I, PU, ST D1 VDDIOP GPIO_CLK PB20 I/O – – SPI1_SPCK I/O D10 I/O – – PIO, I, PU, ST L3 VDDIOP GPIO PB21 I/O – – SPI1_NPCS0 I/O D11 I/O – – PIO, I, PU, ST G1 VDDIOP GPIO PB22 I/O – – SPI1_NPCS1 O D12 I/O – – PIO, I, PU, ST H1 VDDIOP GPIO PB23 I/O – – SPI1_NPCS2 O D13 I/O – – PIO, I, PU, ST E1 VDDIOP GPIO PB24 I/O – – DRXD I D14 I/O TDI I TDI, PU, ST J1 VDDIOP GPIO PB25 I/O – – DTXD O D15 I/O TDO O TDO, ST M5 VDDIOP GPIO_CLK PB26 I/O – – PCK0 O RK0 I/O PWMH0 O PIO, I, PU, ST L2 VDDIOP GPIO PB27 I/O – – SPI1_NPCS3 O TK0 I/O PWML0 O PIO, I, PU, ST K1 VDDIOP GPIO PB28 I/O – – SPI2_NPCS3 O TD0 O PWMH1 O PIO, I, PU, ST M3 VDDIOP GPIO PB29 I/O – – TWD2 I/O RD0 I PWML1 O PIO, O, LOW M4 VDDIOP GPIO PB30 I/O – – TWCK2 O RF0 I/O – – PIO, O, LOW L1 VDDIOP GPIO PB31 I/O – – – – TF0 I/O – – PIO, I, PU, ST V4 VDDIOM GPIO PC0 I/O – – SPI0_MISO I/O PWMH2 O ISI_D8 I PIO, I, PU, ST P8 VDDIOM GPIO PC1 I/O – – SPI0_MOSI I/O PWML2 O ISI_D9 I PIO, I, PU, ST V5 VDDIOM GPIO_CLK PC2 I/O – – SPI0_SPCK I/O PWMH3 O ISI_D10 I PIO, I, PU, ST R8 VDDIOM GPIO PC3 I/O – – SPI0_NPCS0 I/O PWML3 O ISI_D11 I PIO, I, PU, ST W5 VDDIOM MCI_CLK PC4 I/O – – SPI0_NPCS1 O MCI0_CK I/O PCK1 T8 VDDIOM GPIO PC5 I/O – – D0 I/O MCI0_CDA I/O – – PIO, I, PU, ST W6 VDDIOM GPIO PC6 I/O – – D1 I/O MCI0_DA0 I/O – – PIO, I, PU, ST R19 VDDIOM GPIO PC7 I/O – – D2 I/O MCI0_DA1 I/O – – PIO, I, PU, ST N15 VDDIOM GPIO PC8 I/O – – D3 I/O MCI0_DA2 I/O – – PIO, I, PU, ST DS60001525A-page 12 O PIO, I, PU, ST O PIO, I, PU, ST  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 3-1: TFBGA361 Pin Description (Continued) Primary Pin Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST U8 VDDIOM GPIO PC9 I/O – – D4 I/O MCI0_DA3 I/O – – PIO, I, PU, ST V6 VDDIOM GPIO PC10 I/O – – D5 I/O MCI0_DA4 I/O – – PIO, I, PU, ST V7 VDDIOM GPIO PC11 I/O – – D6 I/O MCI0_DA5 I/O – – PIO, I, PU, ST W7 VDDIOM GPIO PC12 I/O – – D7 I/O MCI0_DA6 I/O – – PIO, I, PU, ST V8 VDDIOM GPIO PC13 I/O – – NRD/NANDOE O MCI0_DA7 I/O – – PIO, I, PU, ST U9 VDDIOM GPIO PC14 I/O – – NWE/NANDWE O – – – – PIO, I, PU, ST W8 VDDIOM GPIO PC15 I/O – – NCS3 O – – – – PIO, I, PU, ST V9 VDDIOM GPIO PC16 I/O – – NANDRDY I – – – – PIO, I, PU, ST W9 VDDIOM GPIO PC17 I/O – – A21/NANDALE O – – – – A21 V10 VDDIOM GPIO PC18 I/O – – A22/NANDCLE O – – – – A22 U14 VDDIOM GPIO PC19 I/O – – ISI_D0 I TK1 I/O – – PIO, I, PU, ST V11 VDDIOM GPIO PC20 I/O – – ISI_D1 I TF1 I/O – – PIO, I, PU, ST U15 VDDIOM GPIO PC21 I/O – – ISI_D2 I TD1 O – – PIO, I, PU, ST T15 VDDIOM GPIO PC22 I/O – – ISI_D3 I RF1 I/O – – PIO, I, PU, ST U16 VDDIOM GPIO PC23 I/O – – ISI_D4 I RD1 I – – PIO, I, PU, ST T16 VDDIOM GPIO PC24 I/O – – ISI_D5 I RK1 I PCK1 V17 VDDIOM GPIO PC25 I/O – – ISI_D6 I TWD3 I/O URXD1 I R16 VDDIOM GPIO PC26 I/O – – ISI_D7 I TWCK3 O UTXD1 O PIO, I, PU, ST U12 VDDANA GPIO_ANA PC27 I/O AD0 – – I SPI0_NPCS1 O PWML0 O PIO, I, PU, ST T11 VDDANA GPIO_ANA PC28 I/O AD1 – – I SPI0_NPCS2 O PWML1 O PIO, I, PU, ST R13 VDDANA GPIO_ANA PC29 I/O AD2 – – I SPI0_NPCS3 O PWMFI0 O PIO, I, PU, ST T12 VDDANA GPIO_ANA PC30 I/O AD3 – – I – – PWMH0 O PIO, I, PU, ST T13 VDDANA GPIO_ANA PC31 I/O AD4 – – I – – PWMH1 I PIO, I, PU, ST M1 VDDIOP GPIO_CLK PD8 I/O – – PCK0 O – – – – PIO, I, PU, ST M2 VDDIOP GPIO PD9 I/O – – FIQ I – – – – PIO, I, PU, ST N2 VDDIOP GPIO PD10 I/O – – CTS0 I – – – – PIO, I, PU, ST N3 VDDIOP GPIO PD11 I/O – – RTS0 O SPI2_MISO I/O – – PIO, I, PU, ST N1 VDDIOP GPIO PD12 I/O – – RXD0 I – – – – PIO, O, PD P3 VDDIOP GPIO PD13 I/O – – TXD0 O SPI2_MOSI I/O – – PIO, I, PU, ST P2 VDDIOP GPIO PD14 I/O – – CTS1 I – – – – PIO, I, PU, ST N4 VDDIOP GPIO PD15 I/O – – RTS1 O SPI2_SPCK I/O – – PIO, I, PU, ST R2 VDDIOP GPIO PD16 I/O – – RXD1 I – – – – PIO, O, PD R3 VDDIOP GPIO PD17 I/O – – TXD1 O – – PIO, I, PU, ST T9 VDDANA GPIO PD18 I/O – – – – – – – – PIO, I, PU, ST P11 VDDANA GPIO PD19 I/O – – – – – – – – PIO, I, PU, ST T10 VDDANA GPIO PD20 I/O – – – – – – – – PIO, I, PU, ST P10 VDDANA GPIO PD21 I/O – – – – – – – – PIO, I, PU, ST  2017 Microchip Technology Inc. SPI2_NPCS0 I/O O PIO, I, PU, ST PIO, I, PU, ST DS60001525A-page 13 SAMA5D4 SERIES Table 3-1: TFBGA361 Pin Description (Continued) Primary Pin Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST U11 VDDANA GPIO PD22 I/O – – – – – – – – PIO, I, PU, ST R10 VDDANA GPIO PD23 I/O – – – – – – – – PIO, I, PU, ST U10 VDDANA GPIO PD24 I/O – – – – – – – – PIO, I, PU, ST R11 VDDANA GPIO PD25 I/O – – – – – – – – PIO, I, PU, ST U13 VDDANA GPIO PD26 I/O – – – – – – – – PIO, I, PU, ST T14 VDDANA GPIO PD27 I/O – – – – – – – – PIO, I, PU, ST R1 VDDIOP GPIO_CLK PD28 I/O – – SCK0 I/O – – – – PIO, I, PU, ST P1 VDDIOP GPIO_CLK PD29 I/O – – SCK1 I/O – – – – PIO, I, PU, ST N5 VDDIOP GPIO PD30 I/O – – – – – – – – PIO, I, PU, ST P5 VDDIOP GPIO_CLK PD31 I/O – – SPI0_NPCS2 O PCK1 O – – PIO, I, PU, ST W19 VDDIOM MCI_CLK PE0 I/O – – A0/NBS0 O MCI0_CDB I/O CTS4 I O, High U17 VDDIOM EBI PE1 I/O – – A1 O MCI0_DB0 I/O – – O, High T17 VDDIOM EBI PE2 I/O – – A2 O MCI0_DB1 I/O – – A2, LOW P16 VDDIOM EBI PE3 I/O – – A3 O MCI0_DB2 I/O – – A3, LOW U18 VDDIOM EBI PE4 I/O – – A4 O MCI0_DB3 I/O – – A4, LOW R17 VDDIOM EBI PE5 I/O – – A5 O CTS3 I – – A5, LOW V19 VDDIOM EBI PE6 I/O – – A6 O TIOA3 I/O – – PIO, O, LOW U19 VDDIOM EBI PE7 I/O – – A7 O TIOB3 I/O PWMFI1 I A7, LOW T19 VDDIOM EBI PE8 I/O – – A8 O TCLK3 I PWML3 O A8, LOW T18 VDDIOM EBI PE9 I/O – – A9 O TIOA2 I/O – – A9, LOW N14 VDDIOM EBI PE10 I/O – – A10 O TIOB2 I/O – – A10, LOW R18 VDDIOM EBI PE11 I/O – – A11 O TCLK2 I – – A11, LOW P17 VDDIOM EBI PE12 I/O – – A12 O TIOA1 I/O PWMH2 O A12, LOW P18 VDDIOM EBI PE13 I/O – – A13 O TIOB1 I/O PWML2 O A13, LOW N17 VDDIOM EBI PE14 I/O – – A14 O TCLK1 I PWMH3 O A14, LOW N18 VDDIOM EBI PE15 I/O – – A15 O SCK3 I/O TIOA0 I/O A15, LOW M15 VDDIOM EBI PE16 I/O – – A16 O RXD3 I TIOB0 I/O A16, LOW N19 VDDIOM EBI PE17 I/O – – A17 O TXD3 O TCLK0 I A17, LOW P19 VDDIOM EBI PE18 I/O – – A18 O TIOA5 I/O MCI1_CK I/O A18, LOW N16 VDDIOM EBI PE19 I/O – – A19 O TIOB5 I/O MCI1_CDA I/O A19, LOW M14 VDDIOM EBI PE20 I/O – – A20 O TCLK5 I MCI1_DA0 I/O A20, LOW M18 VDDIOM EBI PE21 I/O – – A23 O TIOA4 I/O MCI1_DA1 I/O A23, LOW M19 VDDIOM EBI PE22 I/O – – A24 O TIOB4 I/O MCI1_DA2 I/O A24, LOW L18 VDDIOM EBI PE23 I/O – – A25 O TCLK4 I MCI1_DA3 I/O A25, LOW L19 VDDIOM EBI PE24 I/O – – NCS0 O RTS3 O – – NCS0, HIGH M17 VDDIOM EBI PE25 I/O – – NCS1 O SCK4 I/O IRQ I NCS1, HIGH L15 VDDIOM EBI PE26 I/O – – NCS2 O RXD4 I A18 O NCS2, HIGH DS60001525A-page 14  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 3-1: TFBGA361 Pin Description (Continued) Primary Pin Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST M16 VDDIOM EBI PE27 I/O – – NWR1/NBS1 O TXD4 O – – PIO, I, PD L17 VDDIOM EBI PE28 I/O – – NWAIT I RTS4 O A19 O PIO, I, PD V1 VDDIOP DIB PE29 I/O – – DIBP O URXD0 I TWD1 U2 VDDIOP DIB PE30 I/O – – DIBN O UTXD0 O TWCK1 O PIO, O, LOW L4 VDDIOP GPIO PE31 I/O – – ADTRG I – – – – PIO, O, LOW H10 G10 K10 J10 K9 J9 H9 G9 E7 A8 D7 B7 C7 E9 A10 B9 D8 A9 – Not connected – – – – – – – – – – – P4 VDDBU SYSC TST I – – – – – – – – I, PD, ST W12 VDDIOP CLOCK XIN I – – – – – – – – I V12 VDDIOP CLOCK XOUT O – – – – – – – – O W2 VDDBU CLOCK XIN32 I – – – – – – – – I W3 VDDBU CLOCK XOUT32 O – – – – – – – – O T2 VDDBU SYSC SHDN O – – – – – – – – O, PU V3 VDDBU SYSC WKUP I – – – – – – – – I, ST U3 VDDBU PIOBU PIOBU0 I – – – – – – – – I, PU T3 VDDBU PIOBU PIOBU1 I – – – – – – – – I, PU T4 VDDBU PIOBU PIOBU2 I – – – – – – – – I, PU U4 VDDBU PIOBU PIOBU3 I – – – – – – – – I, PU P6 VDDBU PIOBU PIOBU4 I – – – – – – – – I, PU T5 VDDBU PIOBU PIOBU5 I – – – – – – – – I, PU R4 VDDBU PIOBU PIOBU6 I – – – – – – – – I, PU U5 VDDBU PIOBU PIOBU7 I – – – – – – – – I, PU R5 U6 R6 T6 R7 U7 P7 T7 – Not connected – – – – – – – – – – –  2017 Microchip Technology Inc. I/O PIO, O, LOW DS60001525A-page 15 SAMA5D4 SERIES Table 3-1: TFBGA361 Pin Description (Continued) Primary Pin Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST T1 VDDBU RST NRST I – – – – – – – – I V2 VDDBU SYSC JTAGSEL I – – – – – – – – I, PD F15 VDDIODDR DDR_IO DDR_A0 O – – – – – – – – O, LOW F16 VDDIODDR DDR_IO DDR_A1 O – – – – – – – – O, LOW E17 VDDIODDR DDR_IO DDR_A2 O – – – – – – – – O, LOW G15 VDDIODDR DDR_IO DDR_A3 O – – – – – – – – O, LOW B18 VDDIODDR DDR_IO DDR_A4 O – – – – – – – – O, LOW C16 VDDIODDR DDR_IO DDR_A5 O – – – – – – – – O, LOW E15 VDDIODDR DDR_IO DDR_A6 O – – – – – – – – O, LOW F17 VDDIODDR DDR_IO DDR_A7 O – – – – – – – – O, LOW F18 VDDIODDR DDR_IO DDR_A8 O – – – – – – – – O, LOW D19 VDDIODDR DDR_IO DDR_A9 O – – – – – – – – O, LOW E18 VDDIODDR DDR_IO DDR_A10 O – – – – – – – – O, LOW D18 VDDIODDR DDR_IO DDR_A11 O – – – – – – – – O, LOW C18 VDDIODDR DDR_IO DDR_A12 O – – – – – – – – O, LOW D16 VDDIODDR DDR_IO DDR_A13 O – – – – – – – – O, LOW L14 VDDIODDR DDR_IO DDR_D0 I/O – – – – – – – – I, HiZ K16 VDDIODDR DDR_IO DDR_D1 I/O – – – – – – – – I, HiZ K15 VDDIODDR DDR_IO DDR_D2 I/O – – – – – – – – I, HiZ K14 VDDIODDR DDR_IO DDR_D3 I/O – – – – – – – – I, HiZ J18 VDDIODDR DDR_IO DDR_D4 I/O – – – – – – – – I, HiZ J17 VDDIODDR DDR_IO DDR_D5 I/O – – – – – – – – I, HiZ J15 VDDIODDR DDR_IO DDR_D6 I/O – – – – – – – – I, HiZ H19 VDDIODDR DDR_IO DDR_D7 I/O – – – – – – – – I, HiZ H18 VDDIODDR DDR_IO DDR_D8 I/O – – – – – – – – I, HiZ J14 VDDIODDR DDR_IO DDR_D9 I/O – – – – – – – – I, HiZ G18 VDDIODDR DDR_IO DDR_D10 I/O – – – – – – – – I, HiZ H17 VDDIODDR DDR_IO DDR_D11 I/O – – – – – – – – I, HiZ H15 VDDIODDR DDR_IO DDR_D12 I/O – – – – – – – – I, HiZ H14 VDDIODDR DDR_IO DDR_D13 I/O – – – – – – – – I, HiZ G16 VDDIODDR DDR_IO DDR_D14 I/O – – – – – – – – I, HiZ E19 VDDIODDR DDR_IO DDR_D15 I/O – – – – – – – – I, HiZ E14 VDDIODDR DDR_IO DDR_D16 I/O – – – – – – – – I, HiZ E13 VDDIODDR DDR_IO DDR_D17 I/O – – – – – – – – I, HiZ H13 VDDIODDR DDR_IO DDR_D18 I/O – – – – – – – – I, HiZ F13 VDDIODDR DDR_IO DDR_D19 I/O – – – – – – – – I, HiZ B15 VDDIODDR DDR_IO DDR_D20 I/O – – – – – – – – I, HiZ DS60001525A-page 16  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 3-1: TFBGA361 Pin Description (Continued) Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) Pin Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST A14 VDDIODDR DDR_IO DDR_D21 I/O – – – – – – – – I, HiZ D12 VDDIODDR DDR_IO DDR_D22 I/O – – – – – – – – I, HiZ B14 VDDIODDR DDR_IO DDR_D23 I/O – – – – – – – – I, HiZ B13 VDDIODDR DDR_IO DDR_D24 I/O – – – – – – – – I, HiZ G12 VDDIODDR DDR_IO DDR_D25 I/O – – – – – – – – I, HiZ B12 VDDIODDR DDR_IO DDR_D26 I/O – – – – – – – – I, HiZ C12 VDDIODDR DDR_IO DDR_D27 I/O – – – – – – – – I, HiZ F11 VDDIODDR DDR_IO DDR_D28 I/O – – – – – – – – I, HiZ C11 VDDIODDR DDR_IO DDR_D29 I/O – – – – – – – – I, HiZ D11 VDDIODDR DDR_IO DDR_D30 I/O – – – – – – – – I, HiZ B11 VDDIODDR DDR_IO DDR_D31 I/O – – – – – – – – I, HiZ L16 VDDIODDR DDR_IO DDR_DQM0 O – – – – – – – – O, LOW J16 VDDIODDR DDR_IO DDR_DQM1 O – – – – – – – – O, LOW D13 VDDIODDR DDR_IO DDR_DQM2 O – – – – – – – – O, LOW F12 VDDIODDR DDR_IO DDR_DQM3 O – – – – – – – – O, LOW J19 VDDIODDR DDR_IO DDR_DQS0 I/O – – – – – – – – O, LOW F19 VDDIODDR DDR_IO DDR_DQS1 I/O – – – – – – – – O, LOW A15 VDDIODDR DDR_IO DDR_DQS2 I/O – – – – – – – – O, LOW A12 VDDIODDR DDR_IO DDR_DQS3 I/O – – – – – – – – O, LOW K19 VDDIODDR DDR_IO DDR_DQSN0 I/O – – – – – – – – O, HIGH G19 VDDIODDR DDR_IO DDR_DQSN1 I/O – – – – – – – – O, HIGH A16 VDDIODDR DDR_IO DDR_DQSN2 I/O – – – – – – – – O, HIGH A13 VDDIODDR DDR_IO DDR_DQSN3 I/O – – – – – – – – O, HIGH B16 VDDIODDR DDR_IO DDR_CS O – – – – – – – – O, LOW A18 VDDIODDR DDR_IO DDR_CLK O – – – – – – – – O A19 VDDIODDR DDR_IO DDR_CLKN O – – – – – – – – O D15 VDDIODDR DDR_IO DDR_CKE O – – – – – – – – O, LOW B17 VDDIODDR DDR_IO DDR_RAS O – – – – – – – – O, LOW A17 VDDIODDR DDR_IO DDR_CAS O – – – – – – – – O, LOW E16 VDDIODDR DDR_IO DDR_WE O – – – – – – – – O, LOW C15 VDDIODDR DDR_IO DDR_BA0 O – – – – – – – – O, LOW D14 VDDIODDR DDR_IO DDR_BA1 O – – – – – – – – O, LOW G13 VDDIODDR DDR_IO DDR_BA2 O – – – – – – – – O, LOW C19 VDDIODDR Reference DDR_CALN I – – – – – – – – I B19 GNDIODDR Reference DDR_CALP I – – – – – – – – I K12 VDDIODDR/2 Reference DDR_VREF I – – – – – – – – I VBG VBG I – – – – – – – – I W11 VBG  2017 Microchip Technology Inc. DS60001525A-page 17 SAMA5D4 SERIES Table 3-1: TFBGA361 Pin Description (Continued) Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST Reference ADCVREF I – – – – – – – – I W16 VDDUTMII USBHS HHSDPC I/O – – – – – – – – O, PD V16 VDDUTMII USBHS HHSDMC I/O – – – – – – – – O, PD W15 VDDUTMII USBHS HHSDPB I/O – – – – – – – – O, PD V15 VDDUTMII USBHS HHSDMB I/O – – – – – – – – O, PD W14 VDDUTMII USBHS HHSDPA I/O DHSDP I/O – – – – – – O, PD V14 VDDUTMII USBHS HHSDMA I/O DHSDM I/O – – – – – – O, PD Pin Power Rail R12 VDDANA W4 VDDBU Power supply VDDBU I – – – – – – – – I W1 GNDBU Ground GNDBU I – – – – – – – – I VDDCORE I – – – – – – – – I GNDCORE I – – – – – – – – I J7 J11 K7 K8 VCCCORE Power supply L9 L11 N10 VCCCORE I – – – – – – – – I C14 D17 E10 E12 F14 VDDIODDR Power supply H12 H16 K13 K17 M13 VDDIODDR I – – – – – – – – I G8 N9 VDDCORE Power supply B10 D9 D10 F9 H8 J8 J12 K11 GNDCORE L8 L10 L12 M9 M10 M11 V18 W18 Ground DS60001525A-page 18  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 3-1: TFBGA361 Pin Description (Continued) Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) Pin Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST C13 C17 E11 F10 G11 GNDIODDR G14 G17 J13 K18 L13 Ground GNDIODDR I – – – – – – – – I M8 N7 P15 R9 VDDIOM Power supply VDDIOM I – – – – – – – – I M7 M12 N8 P9 GNDIOM Ground GNDIOM I – – – – – – – – I B8 C8 E8 F8 GNDIOP Ground GNDIOP I – – – – – – – – I H7 K6 L5 M6 VDDIOP Power supply VDDIOP I – – – – – – – – I F7 G6 G7 J6 L6 N6 GNDIOP Ground GNDIOP I – – – – – – – – I V13 VDDUTMIC Power supply VDDUTMIC I – – – – – – – – I W13 VDDUTMII W17 Power supply VDDUTMII I – – – – – – – – I P13 GNDUTMI Ground GNDUTMI I – – – – – – – – I W10 VDDPLLA Power supply VDDPLLA I – – – – – – – – I L7 GNDPLL Ground GNDPLL I – – – – – – – – I P14 VDDOSC Power supply VDDOSC I – – – – – – – – I N13 GNDOSC Ground GNDOSC I – – – – – – – – I A11 GNDIOP Ground GNDIOP I – – – – – – – – I C9 N11 P12 VDDANA Power supply VDDANA I – – – – – – – – I C10 H11 N12 GNDANA Ground GNDANA I – – – – – – – – I R14 VDDFUSE Power supply VDDFUSE I – – – – – – – – I R15 GNDFUSE Ground GNDFUSE I – – – – – – – – I  2017 Microchip Technology Inc. DS60001525A-page 19 SAMA5D4 SERIES Table 3-1: TFBGA361 Pin Description (Continued) Primary Pin Power Rail U1 – Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST Not connected – – – – – – – – – – – Note 1: The GPIOs’ reset state is not guaranteed during the powerup phase. During this phase, the GPIOs are in input pullup mode and they take their reset value only after VDDCORE POR reset has been released. If a GPIO must be at level zero at powerup, it is recommended to connect an external pulldown to guarantee this state. 3.2 289-ball LFBGA Package Pinout In this package, the DDRC datapath is reduced to 16 bits. Table 3-2: LFBGA289 Pin Description Primary Pin Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST C5 VDDIOP GPIO PA0 I/O – – LCDDAT0 O – – TMS I TMS, PU, ST F6 VDDIOP GPIO PA1 I/O – – LCDDAT1 O – – – – PIO, I, PU, ST F5 VDDIOP GPIO_CLK PA2 I/O – – LCDDAT2 O G1_TXCK I – – PIO, I, PU, ST B5 VDDIOP GPIO_CLK PA3 I/O – – LCDDAT3 O G1_RXCK I – – PIO, I, PU, ST E5 VDDIOP GPIO PA4 I/O – – LCDDAT4 O G1_TXEN O – – PIO, I, PU, ST A5 VDDIOP GPIO PA5 I/O – – LCDDAT5 O G1_TXER O – – PIO, I, PU, ST A4 VDDIOP GPIO PA6 I/O – – LCDDAT6 O G1_CRS I – – PIO, I, PU, ST E4 VDDIOP GPIO PA7 I/O – – LCDDAT7 O – – – – PIO, I, PU, ST B4 VDDIOP GPIO PA8 I/O – – LCDDAT8 O – – TCK I TCK, PU D4 VDDIOP GPIO PA9 I/O – – LCDDAT9 O G1_COL I – – PIO, I, PU, ST C4 VDDIOP GPIO PA10 I/O – – LCDDAT10 O G1_RXDV I – – PIO, I, PU, ST A3 VDDIOP GPIO PA11 I/O – – LCDDAT11 O G1_RXER I – – PIO, I, PU, ST F4 VDDIOP GPIO PA12 I/O – – LCDDAT12 O G1_RX0 I – – PIO, I, PU, ST F3 VDDIOP GPIO PA13 I/O – – LCDDAT13 O G1_RX1 I – – PIO, I, PU, ST D3 VDDIOP GPIO PA14 I/O – – LCDDAT14 O G1_TX0 O – – PIO, I, PU, ST B3 VDDIOP GPIO PA15 I/O – – LCDDAT15 O G1_TX1 O – – PIO, I, PU, ST G3 VDDIOP GPIO PA16 I/O – – LCDDAT16 O – – NTRST I NTRST, PU, ST E3 VDDIOP GPIO PA17 I/O – – LCDDAT17 O – – – – PIO, O, LOW C3 VDDIOP GPIO PA18 I/O – – LCDDAT18 O G1_RX2 I – – PIO, O, LOW A2 VDDIOP GPIO PA19 I/O – – LCDDAT19 O G1_RX3 I – – PIO, O, LOW G5 VDDIOP GPIO PA20 I/O – – LCDDAT20 O G1_TX2 O – – PIO, I, PU, ST A1 VDDIOP GPIO PA21 I/O – – LCDDAT21 O G1_TX3 O – – PIO, I, PU, ST D2 VDDIOP GPIO PA22 I/O – – LCDDAT22 O G1_MDC O – – PIO, I, PU, ST E2 VDDIOP GPIO PA23 I/O – – LCDDAT23 O G1_MDIO I/O – – PIO, I, PU, ST G4 VDDIOP GPIO_CLK PA24 I/O – – LCDPWM O PCK0 O – – PIO, I, PU, ST C2 VDDIOP GPIO PA25 I/O – – LCDDISP O TD0 O – – PIO, I, PU, ST B2 VDDIOP GPIO PA26 I/O – – LCDVSYNC O PWMH0 O SPI1_NPCS1 O PIO, I, PU, ST DS60001525A-page 20  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 3-2: LFBGA289 Pin Description (Continued) Primary Pin Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST H3 VDDIOP GPIO PA27 I/O – – LCDHSYNC O PWML0 O SPI1_NPCS2 O PIO, I, PU, ST F2 VDDIOP GPIO_CLK2 PA28 I/O – – LCDPCK O PWMH1 O SPI1_NPCS3 O PIO, I, PU, ST B1 VDDIOP GPIO PA29 I/O – – LCDDEN O PWML1 O – – PIO, I, PU, ST C1 VDDIOP GPIO PA30 I/O – – TWD0 I/O – – – – PIO, I, PU, ST H5 VDDIOP GPIO PA31 I/O – – TWCK0 O – – – – PIO, I, PU, ST D1 VDDIOP GPIO_CLK PB0 I/O – – G0_TXCK I – – – – PIO, I, PU, ST H4 VDDIOP GPIO_CLK PB1 I/O – – G0_RXCK I SCK2 I/O ISI_PCK I PIO, I, PU, ST G2 VDDIOP GPIO PB2 I/O – – G0_TXEN O – – – – PIO, I, PU, ST E1 VDDIOP GPIO PB3 I/O – – G0_TXER O CTS2 I ISI_VSYNC I PIO, I, PU, ST F1 VDDIOP GPIO PB4 I/O – – G0_CRS I RXD2 I ISI_HSYNC I PIO, I, PU, ST J3 VDDIOP GPIO PB5 I/O – – G0_COL I TXD2 O PCK2 O PIO, I, PU, ST H2 VDDIOP GPIO PB6 I/O – – G0_RXDV I – – – – PIO, I, PU, ST J5 VDDIOP GPIO PB7 I/O – – G0_RXER I – – – – PIO, I, PU, ST J2 VDDIOP GPIO PB8 I/O – – G0_RX0 I – – – – PIO, I, PU, ST G1 VDDIOP GPIO PB9 I/O – – G0_RX1 I – – – – PIO, I, PU, ST H1 VDDIOP GPIO_CLK PB10 I/O – – G0_RX2 I PCK2 O PWML1 O PIO, I, PU, ST J4 VDDIOP GPIO PB11 I/O – – G0_RX3 I RTS2 O PWMH1 O PIO, I, PU, ST J1 VDDIOP GPIO PB12 I/O – – G0_TX0 O – – – – PIO, I, PU, ST K6 VDDIOP GPIO PB13 I/O – – G0_TX1 O – – – – PIO, I, PU, ST K1 VDDIOP GPIO PB14 I/O – – G0_TX2 O SPI2_NPCS1 O PWMH0 O PIO, I, PU, ST K2 VDDIOP GPIO PB15 I/O – – G0_TX3 O SPI2_NPCS2 O PWML0 O PIO, I, PU, ST L1 VDDIOP GPIO PB16 I/O – – G0_MDC O – – – – PIO, I, PU, ST K3 VDDIOP GPIO PB17 I/O – – G0_MDIO I/O – – – – PIO, I, PU, ST L2 VDDIOP GPIO PB18 I/O – – SPI1_MISO I/O D8 I/O – – PIO, I, PU, ST M1 VDDIOP GPIO PB19 I/O – – SPI1_MOSI I/O D9 I/O – – PIO, I, PU, ST N1 VDDIOP GPIO_CLK PB20 I/O – – SPI1_SPCK I/O D10 I/O – – PIO, I, PU, ST K4 VDDIOP GPIO PB21 I/O – – SPI1_NPCS0 I/O D11 I/O – – PIO, I, PU, ST P1 VDDIOP GPIO PB22 I/O – – SPI1_NPCS1 O D12 I/O – – PIO, I, PU, ST M2 VDDIOP GPIO PB23 I/O – – SPI1_NPCS2 O D13 I/O – – PIO, I, PU, ST R1 VDDIOP GPIO PB24 I/O – – DRXD I D14 I/O TDI I TDI, PU, ST T1 VDDIOP GPIO PB25 I/O – – DTXD O D15 I/O TDO O TDO, ST K5 VDDIOP GPIO_CLK PB26 I/O – – PCK0 O RK0 I/O PWMH0 O PIO, I, PU, ST U1 VDDIOP GPIO PB27 I/O – – SPI1_NPCS3 O TK0 I/O PWML0 O PIO, I, PU, ST K7 VDDIOP GPIO PB28 I/O – – SPI2_NPCS3 O TD0 O PWMH1 O PIO, I, PU, ST L3 VDDIOP GPIO PB29 I/O – – TWD2 I/O RD0 I PWML1 O PIO, O, LOW L4 VDDIOP GPIO PB30 I/O – – TWCK2 O RF0 I/O – – PIO, O, LOW U2 VDDIOP GPIO PB31 I/O – – – – TF0 I/O – – PIO, I, PU, ST  2017 Microchip Technology Inc. DS60001525A-page 21 SAMA5D4 SERIES Table 3-2: LFBGA289 Pin Description (Continued) Primary Pin Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST U7 VDDIOM GPIO PC0 I/O – – SPI0_MISO I/O PWMH2 O ISI_D8 I PIO, I, PU, ST U9 VDDIOM GPIO PC1 I/O – – SPI0_MOSI I/O PWML2 O ISI_D9 I PIO, I, PU, ST U8 VDDIOM GPIO_CLK PC2 I/O – – SPI0_SPCK I/O PWMH3 O ISI_D10 I PIO, I, PU, ST M8 VDDIOM GPIO PC3 I/O – – SPI0_NPCS0 I/O PWML3 O ISI_D11 I PIO, I, PU, ST U10 VDDIOM MCI_CLK PC4 I/O – – SPI0_NPCS1 O MCI0_CK I/O PCK1 O PIO, I, PU, ST N7 VDDIOM GPIO PC5 I/O – – D0 I/O MCI0_CDA I/O – – PIO, I, PU, ST T7 VDDIOM GPIO PC6 I/O – – D1 I/O MCI0_DA0 I/O – – PIO, I, PU, ST G17 VDDIOM GPIO PC7 I/O – – D2 I/O MCI0_DA1 I/O – – PIO, I, PU, ST J13 VDDIOM GPIO PC8 I/O – – D3 I/O MCI0_DA2 I/O – – PIO, I, PU, ST P7 VDDIOM GPIO PC9 I/O – – D4 I/O MCI0_DA3 I/O – – PIO, I, PU, ST R7 VDDIOM GPIO PC10 I/O – – D5 I/O MCI0_DA4 I/O – – PIO, I, PU, ST U11 VDDIOM GPIO PC11 I/O – – D6 I/O MCI0_DA5 I/O – – PIO, I, PU, ST T8 VDDIOM GPIO PC12 I/O – – D7 I/O MCI0_DA6 I/O – – PIO, I, PU, ST U12 VDDIOM GPIO PC13 I/O – – NRD/NANDOE O MCI0_DA7 I/O – – PIO, I, PU, ST R8 VDDIOM GPIO PC14 I/O – – NWE/NANDWE O – – – – PIO, I, PU, ST U13 VDDIOM GPIO PC15 I/O – – NCS3 O – – – – PIO, I, PU, ST P8 VDDIOM GPIO PC16 I/O – – NANDRDY I – – – – PIO, I, PU, ST T9 VDDIOM GPIO PC17 I/O – – A21/NANDALE O – – – – A21 T11 VDDIOM GPIO PC18 I/O – – A22/NANDCLE O – – – – A22 T10 VDDIOM GPIO PC19 I/O – – ISI_D0 I TK1 I/O – – PIO, I, PU, ST N8 VDDIOM GPIO PC20 I/O – – ISI_D1 I TF1 I/O – – PIO, I, PU, ST P15 VDDIOM GPIO PC21 I/O – – ISI_D2 I TD1 O – – PIO, I, PU, ST N16 VDDIOM GPIO PC22 I/O – – ISI_D3 I RF1 I/O – – PIO, I, PU, ST P16 VDDIOM GPIO PC23 I/O – – ISI_D4 I RD1 I – – PIO, I, PU, ST N17 VDDIOM GPIO PC24 I/O – – ISI_D5 I RK1 I PCK1 O PIO, I, PU, ST P17 VDDIOM GPIO PC25 I/O – – ISI_D6 I TWD3 I/O URXD1 I PIO, I, PU, ST M17 VDDIOM GPIO PC26 I/O – – ISI_D7 I TWCK3 O UTXD1 O PIO, I, PU, ST T12 VDDANA GPIO_ANA PC27 I/O AD0 – – I SPI0_NPCS1 O PWML0 O PIO, I, PU, ST R13 VDDANA GPIO_ANA PC28 I/O AD1 – – I SPI0_NPCS2 O PWML1 O PIO, I, PU, ST T13 VDDANA GPIO_ANA PC29 I/O AD2 – – I SPI0_NPCS3 O PWMFI0 O PIO, I, PU, ST R14 VDDANA GPIO_ANA PC30 I/O AD3 – – I – – PWMH0 O PIO, I, PU, ST R15 VDDANA GPIO_ANA PC31 I/O AD4 – – I – – PWMH1 I PIO, I, PU, ST L7 VDDIOP GPIO_CLK PD8 I/O – – PCK0 O – – – – PIO, I, PU, ST P2 VDDIOP GPIO PD9 I/O – – FIQ I – – – – PIO, I, PU, ST T2 VDDIOP GPIO PD10 I/O – – CTS0 I – – – – PIO, I, PU, ST M3 VDDIOP GPIO PD11 I/O – – RTS0 O SPI2_MISO I/O – – PIO, I, PU, ST N2 VDDIOP GPIO PD12 I/O – – RXD0 I – – – – PIO, O, PD DS60001525A-page 22  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 3-2: LFBGA289 Pin Description (Continued) Primary Pin Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST M4 VDDIOP GPIO PD13 I/O – – TXD0 O SPI2_MOSI I/O – – PIO, I, PU, ST K8 VDDIOP GPIO PD14 I/O – – CTS1 I – – – – PIO, I, PU, ST N3 VDDIOP GPIO PD15 I/O – – RTS1 O SPI2_SPCK I/O – – PIO, I, PU, ST L8 VDDIOP GPIO PD16 I/O – – RXD1 I – – – – PIO, I, PU, ST P3 VDDIOP GPIO PD17 I/O – – TXD1 O – – PIO, I, PU, ST P9 VDDANA GPIO PD18 I/O – – – – – – – – PIO, I, PU, ST M10 VDDANA GPIO PD19 I/O – – – – – – – – PIO, I, PU, ST R9 VDDANA GPIO PD20 I/O – – – – – – – – PIO, I, PU, ST R10 VDDANA GPIO PD21 I/O – – – – – – – – PIO, I, PU, ST P10 VDDANA GPIO PD22 I/O – – – – – – – – PIO, I, PU, ST L11 VDDANA GPIO PD23 I/O – – – – – – – – PIO, I, PU, ST R11 VDDANA GPIO PD24 I/O – – – – – – – – PIO, I, PU, ST M11 VDDANA GPIO PD25 I/O – – – – – – – – PIO, I, PU, ST P11 VDDANA GPIO PD26 I/O – – – – – – – – PIO, I, PU, ST L12 VDDANA GPIO PD27 I/O – – – – – – – – PIO, I, PU, ST L9 VDDIOP GPIO_CLK PD28 I/O – – SCK0 I/O – – – – PIO, I, PU, ST R2 VDDIOP GPIO_CLK PD29 I/O – – SCK1 I/O – – – – PIO, I, PU, ST L5 VDDIOP GPIO PD30 I/O – – – – – – – – PIO, I, PU, ST L6 VDDIOP GPIO_CLK PD31 I/O – – SPI0_NPCS2 O PCK1 O – – PIO, I, PU, ST N14 VDDIOM MCI_CLK PE0 I/O – – A0/NBS0 O MCI0_CDB I/O CTS4 I O, HIGH N13 VDDIOM EBI PE1 I/O – – A1 O MCI0_DB0 I/O – – O, HIGH M16 VDDIOM EBI PE2 I/O – – A2 O MCI0_DB1 I/O – – A2, LOW M15 VDDIOM EBI PE3 I/O – – A3 O MCI0_DB2 I/O – – A3, LOW J16 VDDIOM EBI PE4 I/O – – A4 O MCI0_DB3 I/O – – A4, LOW L17 VDDIOM EBI PE5 I/O – – A5 O CTS3 I – – A5, LOW J17 VDDIOM EBI PE6 I/O – – A6 O TIOA3 I/O – – PIO, O, LOW K17 VDDIOM EBI PE7 I/O – – A7 O TIOB3 I/O PWMFI1 I A7, LOW H16 VDDIOM EBI PE8 I/O – – A8 O TCLK3 I PWML3 O A8, LOW L16 VDDIOM EBI PE9 I/O – – A9 O TIOA2 I/O – – A9, LOW L14 VDDIOM EBI PE10 I/O – – A10 O TIOB2 I/O – – A10, LOW H17 VDDIOM EBI PE11 I/O – – A11 O TCLK2 I – – A11, LOW L15 VDDIOM EBI PE12 I/O – – A12 O TIOA1 I/O PWMH2 O A12, LOW G16 VDDIOM EBI PE13 I/O – – A13 O TIOB1 I/O PWML2 O A13, LOW K12 VDDIOM EBI PE14 I/O – – A14 O TCLK1 I PWMH3 O A14, LOW F16 VDDIOM EBI PE15 I/O – – A15 O SCK3 I/O TIOA0 I/O A15, LOW K16 VDDIOM EBI PE16 I/O – – A16 O RXD3 I TIOB0 I/O A16, LOW F17 VDDIOM EBI PE17 I/O – – A17 O TXD3 O TCLK0 I A17, LOW  2017 Microchip Technology Inc. SPI2_NPCS0 I/O DS60001525A-page 23 SAMA5D4 SERIES Table 3-2: LFBGA289 Pin Description (Continued) Primary Pin Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST E16 VDDIOM EBI PE18 I/O – – A18 O TIOA5 I/O MCI1_CK I/O A18, LOW D16 VDDIOM EBI PE19 I/O – – A19 O TIOB5 I/O MCI1_CDA I/O A19, LOW E17 VDDIOM EBI PE20 I/O – – A20 O TCLK5 I MCI1_DA0 I/O A20, LOW D17 VDDIOM EBI PE21 I/O – – A23 O TIOA4 I/O MCI1_DA1 I/O A23, LOW C16 VDDIOM EBI PE22 I/O – – A24 O TIOB4 I/O MCI1_DA2 I/O A24, LOW C17 VDDIOM EBI PE23 I/O – – A25 O TCLK4 I MCI1_DA3 I/O A25, LOW K13 VDDIOM EBI PE24 I/O – – NCS0 O RTS3 O – – NCS0, HIGH B17 VDDIOM EBI PE25 I/O – – NCS1 O SCK4 I/O IRQ I NCS1, HIGH K14 VDDIOM EBI PE26 I/O – – NCS2 O RXD4 I A18 O NCS2, HIGH K15 VDDIOM EBI PE27 I/O – – NWR1/NBS1 O TXD4 O – – PIO, I, PU, ST J10 VDDIOM EBI PE28 I/O – – NWAIT I RTS4 O A19 O PIO, I, PU, ST P6 VDDIOP DIB PE29 I/O – – DIBP O URXD0 I TWD1 I/O PIO, O, LOW N6 VDDIOP DIB PE30 I/O – – DIBN O UTXD0 O TWCK1 O PIO, O, LOW K9 VDDIOP GPIO PE31 I/O – – ADTRG I – – – – PIO, O, LOW R3 VDDBU SYSC TST I – – – – – – – – I, PD, ST T15 VDDIOP CLOCK XIN I – – – – – – – – I U15 VDDIOP CLOCK XOUT O – – – – – – – – O U5 VDDBU CLOCK XIN32 I – – – – – – – – I T5 VDDBU CLOCK XOUT32 O – – – – – – – – O U4 VDDBU SYSC SHDN O – – – – – – – – O, PU T4 VDDBU SYSC WKUP I – – – – – – – – I, ST M5 VDDBU PIOBU PIOBU0 I – – – – – – – – I, PU R4 VDDBU PIOBU PIOBU1 I – – – – – – – – I, PU P4 VDDBU PIOBU PIOBU2 I – – – – – – – – I, PU R5 VDDBU PIOBU PIOBU3 I – – – – – – – – I, PU N5 VDDBU PIOBU PIOBU4 I – – – – – – – – I, PU P5 VDDBU PIOBU PIOBU5 I – – – – – – – – I, PU N4 VDDBU PIOBU PIOBU6 I – – – – – – – – I, PU R6 VDDBU PIOBU PIOBU7 I – – – – – – – – I, PU U3 VDDBU PIOBU NRST I – – – – – – – – I T3 VDDBU SYSC JTAGSEL I – – – – – – – – I, PD B12 VDDIODDR DDR_IO DDR_A0 O – – – – – – – – O, LOW A12 VDDIODDR DDR_IO DDR_A1 O – – – – – – – – O, LOW E15 VDDIODDR DDR_IO DDR_A2 O – – – – – – – – O, LOW G11 VDDIODDR DDR_IO DDR_A3 O – – – – – – – – O, LOW C13 VDDIODDR DDR_IO DDR_A4 O – – – – – – – – O, LOW D12 VDDIODDR DDR_IO DDR_A5 O – – – – – – – – O, LOW DS60001525A-page 24  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 3-2: LFBGA289 Pin Description (Continued) Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) Pin Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST C11 VDDIODDR DDR_IO DDR_A6 O – – – – – – – – O, LOW A14 VDDIODDR DDR_IO DDR_A7 O – – – – – – – – O, LOW F12 VDDIODDR DDR_IO DDR_A8 O – – – – – – – – O, LOW C14 VDDIODDR DDR_IO DDR_A9 O – – – – – – – – O, LOW G12 VDDIODDR DDR_IO DDR_A10 O – – – – – – – – O, LOW A13 VDDIODDR DDR_IO DDR_A11 O – – – – – – – – O, LOW B13 VDDIODDR DDR_IO DDR_A12 O – – – – – – – – O, LOW C10 VDDIODDR DDR_IO DDR_A13 O – – – – – – – – O, LOW J14 VDDIODDR DDR_IO DDR_D0 I/O – – – – – – – – I, HiZ B16 VDDIODDR DDR_IO DDR_D1 I/O – – – – – – – – I, HiZ J9 VDDIODDR DDR_IO DDR_D2 I/O – – – – – – – – I, HiZ J12 VDDIODDR DDR_IO DDR_D3 I/O – – – – – – – – I, HiZ A16 VDDIODDR DDR_IO DDR_D4 I/O – – – – – – – – I, HiZ A15 VDDIODDR DDR_IO DDR_D5 I/O – – – – – – – – I, HiZ H10 VDDIODDR DDR_IO DDR_D6 I/O – – – – – – – – I, HiZ B15 VDDIODDR DDR_IO DDR_D7 I/O – – – – – – – – I, HiZ G15 VDDIODDR DDR_IO DDR_D8 I/O – – – – – – – – I, HiZ H13 VDDIODDR DDR_IO DDR_D9 I/O – – – – – – – – I, HiZ C15 VDDIODDR DDR_IO DDR_D10 I/O – – – – – – – – I, HiZ D15 VDDIODDR DDR_IO DDR_D11 I/O – – – – – – – – I, HiZ H12 VDDIODDR DDR_IO DDR_D12 I/O – – – – – – – – I, HiZ H11 VDDIODDR DDR_IO DDR_D13 I/O – – – – – – – – I, HiZ B14 VDDIODDR DDR_IO DDR_D14 I/O – – – – – – – – I, HiZ H9 VDDIODDR DDR_IO DDR_D15 I/O – – – – – – – – I, HiZ A17 VDDIODDR DDR_IO DDR_DQM0 O – – – – – – – – O, LOW H14 VDDIODDR DDR_IO DDR_DQM1 O – – – – – – – – O, LOW H15 VDDIODDR DDR_IO DDR_DQS0 I/O – – – – – – – – O, LOW F15 VDDIODDR DDR_IO DDR_DQS1 I/O – – – – – – – – O, LOW J15 VDDIODDR DDR_IO DDR_DQSN0 I/O – – – – – – – – O, HIGH F14 VDDIODDR DDR_IO DDR_DQSN1 I/O – – – – – – – – O, HIGH C9 VDDIODDR DDR_IO DDR_CS O – – – – – – – – O, LOW B10 VDDIODDR DDR_IO DDR_CLK O – – – – – – – – O B11 VDDIODDR DDR_IO DDR_CLKN O – – – – – – – – O D9 VDDIODDR DDR_IO DDR_CKE O – – – – – – – – O, LOW A10 VDDIODDR DDR_IO DDR_RAS O – – – – – – – – O, LOW A11 VDDIODDR DDR_IO DDR_CAS O – – – – – – – – O, LOW C12 VDDIODDR DDR_IO DDR_WE O – – – – – – – – O, LOW  2017 Microchip Technology Inc. DS60001525A-page 25 SAMA5D4 SERIES Table 3-2: LFBGA289 Pin Description (Continued) Primary Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) Pin Power Rail I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST D11 VDDIODDR DDR_IO DDR_BA0 O – – – – – – – – O, LOW D10 VDDIODDR DDR_IO DDR_BA1 O – – – – – – – – O, LOW E10 VDDIODDR DDR_IO DDR_BA2 O – – – – – – – – O, LOW G10 VDDIODDR Reference DDR_CALN I – – – – – – – – I E14 GNDIODDR Reference DDR_CALP I – – – – – – – – I G14 VDDIODDR/2 Reference DDR_VREF I – – – – – – – – I P14 VBG VBG VBG I – – – – – – – – I R12 VDDANA Reference ADCVREF I – – – – – – – – I R16 VDDUTMII USBHS HHSDPC I/O – – – – – – – – O, PD R17 VDDUTMII USBHS HHSDMC I/O – – – – – – – – O, PD U17 VDDUTMII USBHS HHSDPB I/O – – – – – – – – O, PD T17 VDDUTMII USBHS HHSDMB I/O – – – – – – – – O, PD U16 VDDUTMII USBHS HHSDPA I/O DHSDP – – – – – – – O, PD T16 VDDUTMII USBHS HHSDMA I/O DHSDM – – – – – – – O, PD T6 VDDBU Power Supply VDDBU I – – – – – – – – I U6 GNDBU Ground GNDBU I – – – – – – – – I VDDCORE I – – – – – – – – I GNDCORE I – – – – – – – – I VCCCORE I – – – – – – – – I D13 E11 VDDIODDR Power Supply VDDIODDR F11 G13 I – – – – – – – – I D14 E12 GNDIODDR E13 F13 J6 VDDCORE Power Supply E9 F9 F10 GNDCORE J7 K11 Ground H6 H7 VCCCORE Power Supply J11 N9 Ground GNDIODDR I – – – – – – – – I M6 M7 VDDIOM Power Supply VDDIOM I – – – – – – – – I M9 N11 GNDIOM Ground GNDIOM I – – – – – – – – I B9 D6 D7 E6 E8 GNDIOP Ground GNDIOP I – – – – – – – – I DS60001525A-page 26  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 3-2: LFBGA289 Pin Description (Continued) Primary Pin Power Rail Alternate PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State(1) I/O Type Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir Signal, Dir, PU, PD, HiZ, ST G8 H8 J8 VDDIOP Power Supply VDDIOP I – – – – – – – – I A6 A7 A8 A9 B6 B7 B8 C6 C7 C8 D5 D8 E7 F7 F8 G6 G7 GNDIOP Ground GNDIOP I – – – – – – – – I P13 VDDUTMIC Power Supply VDDUTMIC I – – – – – – – – I L13 VDDUTMII Power Supply M13 VDDUTMII I – – – – – – – – I N12 GNDUTMI GNDUTMI I – – – – – – – – I U14 VDDPLLA Power Supply VDDPLLA I – – – – – – – – I T14 GNDPLL Ground GNDPLL I – – – – – – – – I P12 VDDOSC Power Supply VDDOSC I – – – – – – – – I M12 GNDOSC Ground GNDOSC I – – – – – – – – I G9 L10 VDDANA Power Supply VDDANA I – – – – – – – – I N10 GNDANA Ground GNDANA I – – – – – – – – I N15 VDDFUSE Power Supply VDDFUSE I – – – – – – – – I M14 GNDFUSE Ground GNDFUSE I – – – – – – – – I Not connected – – – – – – – – – – – K10 – Ground Note 1: The GPIOs’ reset state is not guaranteed during the powerup phase. During this phase, the GPIOs are in input pullup mode and they take their reset value only after VDDCORE POR reset has been released. If a GPIO must be at level zero at powerup, it is recommended to connect an external pulldown to guarantee this state.  2017 Microchip Technology Inc. DS60001525A-page 27 SAMA5D4 SERIES 3.3 Input/Output Description Table 3-3: SAMA5D4 I/O Type Description Pull-up I/O Type Pull-down Schmitt Trigger (2) Voltage Range Analog Type (2) Typ Value (Ω) Type (2) Typ Value (Ω) 3.0–3.6V — Switchable (1) Switchable (1) Switchable Switchable (1) Switchable (1) Switchable Switchable (1) Switchable — (1) Switchable — GPIO GPIO_CLK 3.0–3.6V — GPIO_CLK2 3.0–3.6V — Switchable (1) GPIO_ANA 3.0–3.6V I Switchable (1) Switchable (1) EBI 1.65–1.95V, 3.0–3.6V — Switchable (1) RST 3.0–3.6V — Reset State 100K Reset State 100K Reset State SYSC 1.65–3.6V — Reset State 100K Reset State 15K Reset State USBHS 3.0–3.6V I/O — — — — — CLOCK 1.65–3.6V I/O — — — — — PIOBU 1.88–2.12V — Switchable 150K Switchable 150K Switchable — (1) — (1) — DIB 3.0–3.6V I/O Note 1: Refer to Section 56.2 “DC Characteristics”. 2: When “Reset State” is indicated, the configuration is defined by the “Reset State” column of the pin description tables (refer to Table 3-1 and Table 3-2). Table 3-4: I/O Type SAMA5D4 I/O Type Assignment and Frequency I/O Frequency (MHz) Load (pF) Fan-out Drive Control Signal Name GPIO — — — High/Medium/Low All PIO lines except the lines indicated further on in this table MCI_CLK — — — High/Medium/Low MCI0CK, MCI1CK GPIO_CLK — — — High/Medium/Low SPI0CK, SPI1CK, ETXCLK, ERXCLK GPIO_CLK2 — — — High/Medium/Low LCDPCK GPIO_ANA — — — Fixed to Medium EBI — — — High/Medium/Low 1.8V/3.3V All EBI signals DDR_IO — — — High/Medium/Low All DDR signals RST — — — Fixed to Low NRST, NTRST, RST JTAG — — — Fixed to Medium TCK, TDI, TMS, TDO SYSC — — — No WKUP, SHDN, JTAGSEL, TST VBG — — — No VBG USBHS 480 20 — No HHSDPC, HHSDPB, HHSDPA/DHSDP, HHSDMC, HHSDMB, HHSDMA/DHSDM CLOCK 50 50 — No XIN, XOUT, XIN32, XOUT32 PIOBU — — — No PIOBUx DS60001525A-page 28 ADx  2017 Microchip Technology Inc. SAMA5D4 SERIES 4. Power Considerations 4.1 Power Supplies Table 4-1 defines the different power supplies rails and the estimated power consumption at typical voltage. All 3.3V power rails are to be established prior to VDDCORE and must always be present. Specific power sequences ensure reliable operation of the device and avoid unwanted security events. Table 4-1: Power Supplies Name Voltage Range, Nominal Associated Ground VDDCORE 1.62–1.98V, 1.8V GNDCORE Powers Regulator that generates core power supply on VCCCORE 10 µF decoupling capacitor is to be connected to VCCCORE MUST BE ESTABLISHED AFTER VDDIOP OR AT THE SAME TIME VCCCORE 1.1–1.32V, 1.2V GNDCORE 1.70–1.90V, 1.8V VDDIODDR DDR2 Interface I/O lines GNDIODDR 1.14–1.30V, 1.2V VDDIOM Core 1.65–1.95V, 1.8V 3.0–3.6V, 3.3V LP-DDR2 Interface I/O lines GNDIOM VDDIOP (1) 3.0–3.6V, 3.3V GNDIOP VDDBU 1.8V–2.6V, 2V GNDBU NAND and HSMC Interface I/O lines Peripherals I/O lines MUST BE ESTABLISHED PRIOR TO VDDCORE Slow Clock oscillator, the internal 64 kHz RC and a part of the System Controller MUST BE ESTABLISHED FIRST VDDUTMIC 1.1–1.32V, 1.2V GNDUTMI VDDUTMII 3.0–3.6V, 3.3V GNDUTMI VDDPLLA 1.1–1.32V, 1.2V GNDPLL VDDOSC 3.0V–3.6V, 3.3V GNDOSC (1) 3.0–3.6V, 3.3V GNDANA VDDFUSE 2.25–2.75V, 2.5V GNDFUSE VDDANA USB device and host UTMI+ core and the UTMI PLL MUST be connected to VCCCORE USB device and host UTMI+ interface PLLA cell MUST be connected to VCCCORE Main Oscillator cell Analog parts MUST be connected to VDDIOP with filtering Fuse box for programming VDDFUSE must be 2.5V or 0V and must not be left floating Note 1: VDDIOP and VDDANA must rise at the same time. 4.2 Powerup Considerations VDDBU must be set first and for a permanent duration. The user must maintain NRST at ‘L’ prior to switching on the power supplies. Then VDDIOP and VDDANA are to be switched on, followed by VDDCORE. Afterward, other power supplies can be switched on. After a delay of five SLCK periods, the user can assert NRST to ‘H’ and make the system start. Figure 4-1 illustrates the SAMA5D4 powerup sequence.  2017 Microchip Technology Inc. DS60001525A-page 29 SAMA5D4 SERIES Figure 4-1: Recommended Powerup Sequence VDDBU VDDIOP0 VDDIOP1 VDDANA VDDCORE VDDOSC VDDIOM VDDUTMII VDDIODDR VDDFUSE NRST 5 x tSLCK time 4.3 Shutdown Considerations When the SHDN pin is asserted, NRST must be maintained at ‘L’ prior to switching off the power supplies. After a delay of five SLCK periods, VDDPLL, then VDDCORE, then VDDIOP and VDDANA can be switched off. Afterward, other power supplies can be switched off. VDDBU must never be switched off when other supplies are on. 4.4 Wakeup Considerations When SHDN is rising, NRST is to be maintained at ‘L’ prior to switching on the power supplies. Then VDDIOP and VDDANA are to be switched on, followed by VDDCORE and VDDPLL. Afterward, other power supplies can be switched on. After a delay of five SLCK periods, the user can assert NRST to ‘H’ and make the system wakeup. 4.5 Powerdown Considerations The user must maintain NRST at ‘L’ prior to switching off the power supplies. After a delay of five SLCK periods, the user can switch off VDDCORE, then VDDIOP and VDDANA. Afterward, other power supplies can be switched off. VDDBU must never be switched when other supplies are on. Figure 4-2 illustrates the SAMA5D4 powerdown sequence. DS60001525A-page 30  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 4-2: Recommended Powerdown Sequence 5 x tSLCK NRST VDDCORE VDDIOP0 VDDIOP1 VDDANA VDDOSC VDDIOM VDDUTMII VDDIODDR VDDFUSE VDDBU time 4.6 Power-on Reset The SAMA5D4 embeds several Power-On Resets (POR) to ensure that the power supply is switched on when the reset is released. These PORs are dedicated to VDDBU, VDDIOP and VDDCORE respectively. 4.7 4.7.1 Programmable I/O Lines and Current Drive DDR2 Bus interface 16-bit or 32-bit wide interface, supporting: • 16-bit or 32-bit DDR2/LPDDR/LPDDR2 The DDR2/LPDDR/LPDDR2 I/Os embeds an automatic impedance matching control to avoid overshoots and to reach the best performances according to the bus load and external memories. Two specific analog inputs, DDR_CALP and DDR_CALN are used to calibrate all the DDR I/Os. 4.7.2 LP-DDR2 Power Fail Management The DDR controller (MPDDRC) allows to manage the LPDDR memory when an uncontrolled power off occurs. The DDR power rail must be monitored externally and generate an interrupt when a power fail condition is triggered. The interrupt handler must apply the sequence defined in the MPDDRC Low-power Register by setting the bit LPDDR2_PWOFF (LPDDR2 Power Off Bit). 4.7.3 External Bus Interface 16-bit wide interface, working at MCK/2, supporting: • Static Memories • NAND Flash with Multi-bit ECC The EBI I/Os accept three drive level (LOW, MEDIUM, HIGH) allowing to avoid overshoots and give the best performances according to the bus load and external memories voltage. The drive levels are configured line by line with the LINEx field in the PIO I/O Drive Register x (PIO_DRIVER1 and PIODRIVER2). At reset, the selected drive is low. The user must make sure to program the correct drive according to the device load.  2017 Microchip Technology Inc. DS60001525A-page 31 SAMA5D4 SERIES 4.8 I/O Drive Selection The aim of this control is to adapt the signal drive to the frequency. The general purpose I/O lines can drive high speed or low speed signals depending on the PIO multiplexing. To reduce the overshoots and improve the EMI behavior, the I/Os feature a drive control which can be enabled in the PIO user interface. The PIO controller embeds drive control registers. Two bits per I/O allow to select one drive from [High, Medium, Low] list. DS60001525A-page 32  2017 Microchip Technology Inc. SAMA5D4 SERIES 5. Memories Figure 5-1: Memory Mapping Internal Memory Mapping Address Memory Space 0x0000 0000 0x0000 0000 Internal Memories 256 Mbytes 16 Kbytes SRAM 128 Kbytes Peripheral Mapping DMAC1 512 Mbytes ISI 0x00A0 0000 0x3FFF FFFF 0x4000 0000 Undefined (Abort) 0x00B0 0000 0xF800 0000 0x0FFF FFFF HSMCI0 16 Kbytes UART0 16 Kbytes SSC0 16 Kbytes 0xF000 C000 0xF800 4000 512 Mbytes 0xF800 8000 0x5FFF FFFF 0x6000 0000 256 Mbytes PWMC 16 Kbytes SPI0 16 Kbytes 1 Mbyte Undefined (Abort) 1 Mbyte TWI0 16 Kbytes 0xF801 4000 16 Kbytes TC0, TC1, TC2 16 Kbytes GMAC0 16 Kbytes 16 Kbytes DMAC0 16 Kbytes PMC 16 Kbytes H64MX 16 Kbytes AESB 16 Kbytes SFR 16 Kbytes 0xF802 8000 0xF802 C000 0xF802 4000 TWI2 16 Kbytes USART0 16 Kbytes USART1 16 Kbytes 0xF803 0000 0xF802 8000 Undefined (Abort) MPDDRC 0xF002 4000 0xF802 0000 128 Mbytes 16 Kbytes 0xF002 0000 TWI1 0x8800 0000 CPKCC 0xF001 C000 0xF801 C000 256 Mbytes Always Secure Mapping 0xF001 8000 0xF801 8000 0x6FFF FFFF 0x7000 0000 NFC Command Registers 1 Mbyte L2CC 0xF001 4000 0xF801 0000 0x8FFF FFFF 0x9000 0000 1 Mbyte SMD 0xF001 0000 0xF800 C000 EBI Chip Select 3 1 Mbyte DAP 0x0090 0000 0xF001 8000 0x7FFF FFFF 0x8000 0000 1 Mbyte AXIMX 0x0080 0000 0xF000 8000 0xF000 C000 EBI Chip Select 2 1 Mbyte UHP EHCI 0x0070 0000 0xF000 4000 EBI Chip Select 1 1 Mbyte UHP OHCI 0x0060 0000 LCDC DDR CS/AES 1 Mbyte UDPHS RAM 0x0050 0000 0xF000 0000 DDR CS VDEC 0x0040 0000 256 Mbytes 0x1FFF FFFF 0x2000 0000 0xF803 4000 0xFC00 0000 HSMCI1 16 Kbytes UART1 16 Kbytes USART2 16 Kbytes USART3 16 Kbytes USART4 16 Kbytes SSC1 16 Kbytes 0xFC00 4000 256 Mbytes Reserved 0xFC00 8000 0x9FFF FFFF CATB 0xFC00 C000 0xFC03 9000 0xFC01 0000 Reserved 0xFC01 4000 0xFC01 8000 Undefined (Abort) SPI1 16 Kbytes SPI2 16 Kbytes 0xFC04 0000 TC3, TC4, TC5 16 Kbytes TC6, TC7, TC8 16 Kbytes GMAC1 16 Kbytes Reserved 16 Kbytes SHA 16 Kbytes 0xFC05 4000 H32MX 16 Kbytes SECURAM 16 Kbytes SMC 16 Kbytes SFC 16 Kbytes 0xFC05 8000 16 Kbytes 0xFC05 C000 TRNG 16 Kbytes 0xFC06 0000 ADC 16 Kbytes 0xFC06 4000 0xFC03 0000 0xFC03 4000 0xFC03 8000 16 Kbytes TDES 0xFC05 0000 UDPHS TWI3 16 Kbytes 0xFC04 C000 0xFC02 C000 Reserved 0xFC06 8000 0xFC03 9000 0xEFFF FFFF 0xF000 0000 16 Kbytes 0xFC04 8000 0xFC02 4000 0xFC02 8000 ICM AES 0xFC04 4000 0xFC01 C000 0xFC02 0000 PIOD 512 bytes SBM 512 bytes SAIC 512 bytes RSTC 16 bytes SHDWC 16 bytes 0xFC06 8200 0xFC06 9000 Internal Peripheral 256 Mbytes DBGU 4 Kbytes 0xFC06 8400 0xFC06 A000 PIOA 4 Kbytes PIOB 4 Kbytes PIOC 4 Kbytes PIOE 4 Kbytes 0xFC06 8650 AIC 4 Kbytes 0xFC06 86B0 0xFC06 8600 0xFC06 B000 0xFFFF FFFF 0xFC06 C000 Key Always Secured 0xFC06 E000 Programmable Secured 0xFC06 F000 Undefined (Abort) Secured and Non-Secured  2017 Microchip Technology Inc. 0xFC06 8610 0xFC06 8630 0xFC06 8640 0xFC06 D000 xxx NFC SRAM 0x0030 0000 EBI Chip Select 0 xxx 128 Kbytes 0x0020 0000 0x0FFF FFFF 0x1000 0000 xxx ROM 0x0010 0000 0xFC06 88B0 PIT 16 bytes WDT 16 bytes SCKCR 16 bytes RTC 512 bytes Undefined (Abort) DS60001525A-page 33 SAMA5D4 SERIES 5.1 5.1.1 Embedded Memory Scrambled Internal SRAM The SAMA5D4 product embeds a total of 128 Kbytes of scrambled high-speed SRAM. After reset and until the Remap command is performed, SRAM is accessible at the address: 0x0020 0000. After remap of AXI Bus Matrix, SRAM is also available at the address 0x0. 5.1.2 Secured Backup SRAM The device embeds secure memories (8 Kbytes of SRAM) which are dedicated to the storage of sensitive data. The secure backup SRAM is described in the document “Secure Box Module (SBM)”. This document is available under Non-Disclosure Agreement (NDA). Contact a Microchip Sales Representative for further details. 5.1.3 Scrambled Internal ROM The product embeds one 128-Kbyte secured scrambled internal ROM mapped at address 0 after reset. The ROM contains a standard and a secure bootloader as well as the BCH (Bose, Chaudhuri and Hocquenghem) code tables for NAND Flash ECC correction. The standard bootloader supports booting from: • • • • • 8-bit NAND Flash with ECC management SPI Serial Flash SDCARD EMMC TWI EEPROM The boot sequence can be selected using the boot order facility (Boot Select Control Register). The internal ROM embeds Galois field tables that are used to compute NAND Flash ECC. Refer to Figure 12-9 “Galois Field Table Mapping” in Section 12. “Standard Boot Strategies”. 5.1.4 Boot Strategies For standard boot strategies, refer to Section 12. “Standard Boot Strategies”. For secure boot strategies, refer to the application note “SAMA5D4x Secure Boot Strategy” (NDA required). 5.2 External Memory The SAMA5D4 offers connection to a wide range of external memories or to parallel peripherals. 5.2.1 Supported Memories on DDR2/LPDDR/LPDDR2 Interface • • • • • • • • 16-bit or 32-bit external interface 512 Mbytes of address space on DDR CS and DDR/AES CS in 32-bit mode 256 Mbytes of address space on DDR CS and DDR/AES CS in 16-bit mode Supports 16-bit or 32-bit 8-banks DDR2, LPDDR and LPDDR2 memories Automatic drive level control Multi-port Dynamic scrambling The port 0 of this interface has an embedded automatic AES encryption and decryption mechanism (refer to Section 53. “Advanced Encryption Standard Bridge (AESB)”). Writing to or reading from the address 0x40000000 may trigger the encryption or decryption mechanism depending on the AESB on External Memories configuration. • TrustZone: The multi-port feature of this interface implies TrustZone configuration constraints. Refer to Section 15.12 “TrustZone Extension to AHB and APB” for more details. 5.2.2 Supported Memories on Static Memories and NAND Flash Interfaces The Static Memory Controller is dedicated to interfacing external memory devices: • Asynchronous SRAM-like memories and parallel peripherals • NAND Flash (MLC and SLC) 8-bit data path The Static Memory Controller is able to drive up to four chip selects. NCS3 is dedicated to the NAND Flash control. The HSMC embeds the NAND Flash Controller (NFC). The NFC can handle automatic transfers, sending the commands and address cycles to the NAND Flash and transferring the content of the page (for read and write) to the NFC SRAM. It minimizes the CPU overhead. DS60001525A-page 34  2017 Microchip Technology Inc. SAMA5D4 SERIES In order to improve overall system performance, the DATA phase of the transfer can be DMA assisted. The static memory embeds the NAND Flash Error Correcting Code Controller with the following features: • Algorithm based on BCH codes • Supports also SLC 1-bit (BCH 2-bit), SLC 4-bit (BCH 4-bit) • Programmable Error Correcting Capability - 2-bit, 4-bit, 8-bit and 16-bit errors for 512 bytes/sector (4 Kbyte page) - 24-bit error for 1024 bytes/sector (8 Kbyte page) • Programmable sector size: 512 bytes or 1024 bytes • Programmable number of sector per page: 1, 2, 4 or 8 blocks of data per page • Programmable spare area size • Supports spare area ECC protection • Supports 8-Kbyte page size using 1024 bytes/sector and 4-Kbyte page size using 512 bytes/sector • Error detection is interrupt driven • Provides hardware acceleration for error location • Finds roots of error-locator polynomial • Programmable number of roots • Dynamic scrambling  2017 Microchip Technology Inc. DS60001525A-page 35 SAMA5D4 SERIES 6. Real-time Event Management The events generated by peripherals are designed to be directly routed to peripherals managing/using these events without processor intervention. Peripherals receiving events contain logic by which to select the one required. 6.1 Embedded Characteristics • Timers, PWM, IO peripherals generate event triggers which are directly routed to event managers such as ADC, for example, to start measurement/conversion without processor intervention. • UART, USART, SPI, TWI, PWM, HSMCI, AES, ADC, PIO, Timer (capture mode) also generate event triggers directly connected to DMA Controller (XDMAC0 or XDMAC1) for data transfer without processor intervention. • PWM safety events (faults) are in combinational form and directly routed from event generators (ADC, PMC, Timer) to PWM module. • PMC safety event (clock failure detection) can be programmed to switch the MCK on reliable main RC internal clock without processor intervention. Table 6-1: Function Safety Measurement trigger Real-time Event Mapping List Application(s) Description Event Source Event Destination General-purpose Automatic switch to reliable main RC oscillator in case of main crystal clock failure(1) Power Management Controller (PMC) PMC General-purpose, motor control Puts the PWM outputs in Safe mode (main crystal clock failure detection)(1)(2) Power Management Controller (PMC) Motor control Puts the PWM outputs in Safe mode (Overspeed, Overcurrent detection, etc.)(2)(3) Analog-to-Digital-Converter (ADC) Motor control Puts the PWM Outputs in Safe mode (Overspeed, Overcurrent detection, etc.)(2)(4) Timer Counter Block 0 (channels TC0,TC1,TC2) General-purpose, motor control Puts the PWM outputs in Safe mode (general purpose fault inputs)(2) Two IOs (PWM_FI0 and PWM_FI1) General-purpose Trigger source selection in ADC(5) Timer Counter Block 0 (TIOA0,TIOA1,TIOA2) Motor control General-purpose ADC-PWM synchronization(6)(7) Trigger source selection in ADC(5) Trigger source selection in ADC(5) Pulse Width Modulation (PWM) PWM Event Line 0 and 1 ADC ADTRG Note 1: Refer to “Main Crystal Oscillator Failure Detection” in Section 27. “Power Management Controller (PMC)”. 2: Refer to “Fault Inputs” and “Fault Protection” in Section 47. “Pulse Width Modulation Controller (PWM)”. 3: Refer to “Fault Output” in Section 48. “Analog-to-Digital Converter (ADC)”. 4: Refer to “Fault Mode” in Section 46. “Timer Counter (TC)”. 5: Refer to “Conversion Triggers” and the “ADC Mode Register” (ADC_MR) in Section 48. “Analog-to-Digital Converter (ADC)”. 6: Refer to “PWM Comparison x Value Register” (PWM_CMPVx) in Section 47. “Pulse Width Modulation Controller (PWM)”. 7: Refer to “PWM Comparison Units” and “PWM Event Lines” in Section 47. “Pulse Width Modulation Controller (PWM)”. DS60001525A-page 36  2017 Microchip Technology Inc. SAMA5D4 SERIES 7. System Controller The System Controller is a set of peripherals handling key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller’s peripherals are all mapped between addresses 0xFC06 0000 and 0xFC06 F000. Figure 7-1 shows the System Controller block diagram.  2017 Microchip Technology Inc. DS60001525A-page 37 SAMA5D4 SERIES Figure 7-1: System Controller Block Diagram System Controller VDDCORE Powered Secured Advanced Interrupt Controller fiq secured_periph_irq[] irq[23] pmc_irq nfiq fiq_vect ptc_wakeup irq nirq irq_vect Advanced Interrupt Controller nonsecured_periph_irq[] pit_irq wdt_irq dbgu_irq por_ntrst Cortex-A5 ntrst proc_nreset PCK MCK periph_nreset dbgu_irq Debug Unit dbgu_rxd MCK Debug periph_nreset SLCK Debug Idle proc_nreset debug dbgu_txd Periodic Interval Timer pit_irq Watchdog Timer wdt_irq jtag_nreset Boundary Scan TAP Controller MCK periph_nreset Bus Matrix wdt_fault NRST por_ntrst jtag_nreset VDDCORE POR Reset Controller periph_nreset proc_nreset backup_nreset UPLLCK VDDBU VDDBU POR VDDBU Powered UHP48M UHP12M SLCK SLCK backup_nreset Real-Time Clock Secure Box Module rtc_irq periph_nreset rtc_alarm periph_irq[50] USB High Speed Host Port ntrst irq[20] UPLLCK irq[23] wkup PIOBU[7..0] periph_nreset MCK USB High Speed Device Port periph_irq[49] Erase Automaton 12M PLL 32K RC SECURAM 8 KB + 512 bits SLCK SHDN WKUP backup_nreset rtc_alarm Shutdown Controller 32K RC Oscillator XIN32 XOUT32 Slow Clock Oscillator SCKC_CR 12 MHz RC Oscillator XIN XOUT SLCK int MAINCK 12 MHz Main Oscillator PLLA UPLL PLLACK Power Management Controller UPLLCK periph_clk[2..59] pck[0-2] UHP48M UHP12M PCK MCK DDR sysclk LCD Pixel clock pmc_irq Idle periph_clk[2..59] periph_nreset periph_nreset periph_nreset periph_clk[29..26] dbgu_rxd PA0–PA31 PB0–PB31 PIO Controllers PC0–PC31 periph_irq[29..26] irq fiq dbgu_txd periph_irq[2..59] Embedded Peripherals In Out Enable PD8–PD31 PE0–PE31 Fuse Box Key DS60001525A-page 38 xxx Always Secured xxx Programmable Secured xxx Secured and Non-Secured  2017 Microchip Technology Inc. SAMA5D4 SERIES 7.1 • • • • • • • • Chip Identification Chip ID: 0x8A5C07Cx SAMA5D41 Ext ID: 0x1 SAMA5D42 Ext ID: 0x2 SAMA5D43 Ext ID: 0x3 SAMA5D44 Ext ID: 0x4 Boundary JTAG ID: 0x05B3903F Debug Port JTAG IDCODE: 0x4BA00477 Debug Port Serial Wire IDCODE: 0x2BA01477  2017 Microchip Technology Inc. DS60001525A-page 39 SAMA5D4 SERIES 8. Peripherals 8.1 Peripheral Mapping As shown in Figure 5-1 “Memory Mapping”, the peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xF000 0000 and 0xFFFF FFFF. Each user peripheral is allocated 16 Kbytes of the address space. 8.2 Peripheral Identifiers In the following table, AS stands for “Always Secured” and PS stands for “Programmable Secured”. Table 8-1: Peripheral Identifiers Instance ID Instance Name External Interrupt Wired-OR Interrupt Clock Type Security Type In Matrix 0 SAIC FIQ Interrupt ID FIQ – MCK2 AS H32MX 1 SYS System Controller – PMC, RSTC, RTC, SHDWC MCK2 AS H32MX 2 ARM Performance Monitor Unit (PMU) – – PCK AS H64MX 3 PIT Periodic Interval Timer – – MCK2 AS H32MX 4 WDT Watchdog Timer – – MCK2 AS H32MX 5 PIOD Parallel I/O Controller D – – PCLOCK_LS AS H32MX 6 USART0 Universal Synchronous Asynchronous Receiver Transceiver 0 – – PCLOCK_LS AS H32MX 7 USART1 Universal Synchronous Asynchronous Receiver Transceiver 1 – – PCLOCK_LS AS H32MX 8 XDMAC0 DMA Controller 0 – – HCLOCK_HS + PCLOCK_HS AS H64MX 9 ICM Integrity Check Monitor – – PCLOCK_LS AS H32MX 10 CPKCC Classic Public Key Crypto Controller – – PCLOCK_HS AS H64MX 12 AES Advanced Encryption Standard – – PCLOCK_LS AS H32MX 13 AESB AES Bridge – – PCLOCK_HS AS H64MX 14 TDES Triple Data Encryption Standard – – PCLOCK_LS AS H32MX 15 SHA SHA Signature – – PCLOCK_LS AS H32MX 16 MPDDRC MPDDR Controller – – HCLOCK_HS AS H64MX 17 MATRIX1 H32MXMX, 32-bit AHB Matrix – – PCLOCK_LS AS H32MX 18 MATRIX0 H64MX, 64-bit AHB Matrix – – PCLOCK_HS AS H64MX 19 VDEC Video Decoder – – PCLOCK_HS PS H64MX 20 SBM Secure Box Module – – MCK2 AS H32MX 22 HSMC Multi-bit ECC Interrupt – – PCLOCK_LS PS H32MX 23 PIOA Parallel I/O Controller A – – PCLOCK_LS PS H32MX 24 PIOB Parallel I/O Controller B – – PCLOCK_LS PS H32MX DS60001525A-page 40 Instance Description  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 8-1: Peripheral Identifiers (Continued) Instance ID Instance Name External Interrupt Wired-OR Interrupt Clock Type Security Type In Matrix 25 PIOC Parallel I/O Controller C – – PCLOCK_LS PS H32MX 26 PIOE Parallel I/O Controller E – – PCLOCK_LS PS H32MX 27 UART0 Universal Asynchronous Receiver Transmitter 0 – – PCLOCK_LS PS H32MX 28 UART1 Universal Asynchronous Receiver Transmitter 1 – – PCLOCK_LS PS H32MX 29 USART2 Universal Synchronous Asynchronous Receiver Transceiver 2 – – PCLOCK_LS PS H32MX 30 USART3 Universal Synchronous Asynchronous Receiver Transceiver3 – – PCLOCK_LS PS H32MX 31 USART4 Universal Synchronous Asynchronous Receiver Transceiver 4 – – PCLOCK_LS PS H32MX 32 TWI0 Two-wire Interface 0 – – PCLOCK_LS PS H32MX 33 TWI1 Two-wire Interface 1 – – PCLOCK_LS PS H32MX 34 TWI2 Two-wire Interface 2 – – PCLOCK_LS PS H32MX 35 HSMCI0 High Speed Multimedia Card Interface 0 – – PCLOCK_LS PS H32MX 36 HSMCI1 High Speed Multimedia Card Interface 1 – – PCLOCK_LS PS H32MX 37 SPI0 Serial Peripheral Interface 0 – – PCLOCK_LS PS H32MX 38 SPI1 Serial Peripheral Interface 1 – – PCLOCK_LS PS H32MX 39 SPI2 Serial Peripheral Interface 2 – – PCLOCK_LS PS H32MX 40 TC0 Timer Counter 0 (ch. 0, 1, 2) – – PCLOCK_LS PS H32MX 41 TC1 Timer Counter 1 (ch. 3, 4, 5) – – PCLOCK_LS PS H32MX 42 TC2 Timer Counter 2 (ch. 6, 7, 8) – – PCLOCK_LS PS H32MX 43 PWM Pulse Width Modulation Controller – – PCLOCK_LS PS H32MX 44 ADC Touchscreen ADC Controller – – PCLOCK_LS PS H32MX 45 DBGU Debug Unit – – PCLOCK_LS PS H32MX 46 UHPHS USB Host High Speed – – HCLOCK_LS PS H32MX 47 UDPHS USB Device High Speed – – HCLOCK_LS + PCLOCK_LS PS H32MX 48 SSC0 Synchronous Serial Controller 0 – – PCLOCK_LS PS H32MX 49 SSC1 Synchronous Serial Controller 1 – – PCLOCK_LS PS H32MX 50 XDMAC1 DMA Controller 1 – – HCLOCK_HS + PCLOCK_HS NonSecured H64MX 51 LCDC LCD Controller – – HCLOCK_HS PS H64MX 52 ISI Camera Interface – – PCLOCK_HS PS H64MX Instance Description  2017 Microchip Technology Inc. DS60001525A-page 41 SAMA5D4 SERIES Table 8-1: Peripheral Identifiers (Continued) Instance ID Instance Name External Interrupt Wired-OR Interrupt Clock Type Security Type In Matrix 53 TRNG True Random Number Generator – – PCLOCK_LS PS H32MX 54 GMAC0 Ethernet MAC 0 – – HCLOCK_LS + PCLOCK_LS PS H32MX 55 GMAC1 Ethernet MAC 1 – – HCLOCK_LS + PCLOCK_LS PS H32MX 56 AIC IRQ Interrupt ID IRQ – MCK2 NonSecured H32MX 57 SFC Fuse Controller – – PCLOCK_LS AS H32MX 58 – Reserved – – – – – 59 SECURAM Secured RAM – – PCLOCK_LS AS H32MX 61 SMD SMD Soft Modem – – SMDCK PS H32MX 62 TWI3 Two-Wire Interface 3 – – PCLOCK_LS PS H32MX 63 – – – – – – – AS H32MX Instance Description Reserved (1) 64 SFR Special Function Register 65 AIC Advanced Interrupt Controller (1) – – – NonSecured H32MX 66 SAIC Secured Advanced Interrupt Controller (1) – – – AS H32MX 67 L2CC L2 Cache Controller (1) – – – PS H64MX Note 1: For security purposes, there is no matching clock but a peripheral ID only. 8.3 Peripheral Signal Multiplexing on I/O Lines The SAMA5D4 product features five PIO controllers: PIOA, PIOB, PIOC, PIOD, and PIOE, that multiplex the I/O lines of the peripheral set. Each line can be assigned to one of three peripheral functions: A, B, or C. The multiplexing tables in the pin description paragraphs define how the I/O lines of the peripherals A, B and C are multiplexed on the PIO Controllers. Note that some peripheral functions which are output only, might be duplicated within the both tables. The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is mentioned, the PIO line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO line in PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 8.4 Peripheral Clock Type The SAMA5D4 series embeds peripherals with the following clock types: • HCLOCK_HS, HCLOCK_LS: AHB Clocks, managed with the PMC_SCER, PMC_SCDR and PMC_SCSR registers of PMC System Clock • PCLOCK_HS, PCLOCK_LS: APB Clocks, managed with the PMC_PCER, PMC_PCDR, PMC_PCSR and PMC_PCR registers of Peripheral Clock • MCK2: This clock cannot be disabled. • PCK: The Processor Clock is managed with the PMC_SCDR and PMC_SCSR registers of PMC System Clock. Refer to Table 8-1 “Peripheral Identifiers” for details. In the table, clock type suffixes _HS and _LS refer to H64MX and H32MX, respectively. DS60001525A-page 42  2017 Microchip Technology Inc. SAMA5D4 SERIES 9. Arm Cortex-A5 9.1 Description The Arm Cortex-A5 processor is a high-performance, low-power, Arm macrocell with an L1 cache subsystem that provides full virtual memory capabilities. The Cortex-A5 processor implements the Armv7 architecture and runs 32-bit Arm instructions, 16-bit and 32-bit Thumb instructions, and 8-bit Java® byte codes in Jazelle® state. The Cortex-A5 NEON Media Processing Engine (MPE) extends the Cortex-A5 functionality to provide support for the Armv7 Advanced SIMD v2 and Vector Floating-Point v4 (VFPv4) instruction sets. The Cortex-A5 NEON MPE provides flexible and powerful acceleration for signal processing algorithms including multimedia such as image processing, video decode/encode, 2D/3D graphics, and audio. Refer to the Cortex-A5 NEON Media Processing Engine Technical Reference Manual. The Cortex-A5 processor includes TrustZone technology to enhance security by partitioning the SoC’s hardware and software resources in a Secure world for the security subsystem and a Normal world for the rest, enabling a strong security perimeter to be built between the two. Refer to Security Extensions overview in the Cortex-A5 Technical Reference Manual. Refer to the Arm Architecture Reference Manual for details on how TrustZone works in the architecture. Note: 9.1.1 All Arm publications referenced in this datasheet can be found at www.arm.com. Power Management The Cortex-A5 design supports the following main levels of power management: • Run Mode • Standby Mode 9.1.1.1 Run Mode Run mode is the normal mode of operation where all of the processor functionality is available. Everything, including core logic and embedded RAM arrays, is clocked and powered up. 9.1.1.2 Standby Mode Standby mode disables most of the clocks of the processor, while keeping it powered up. This reduces the power drawn to the static leakage current, plus a small clock power overhead required to enable the processor to wake up from Standby mode. The transition from Standby mode to Run mode is caused by one of the following: • • • • the arrival of an interrupt, either masked or unmasked the arrival of an event, if standby mode was initiated by a Wait for Event (WFE) instruction a debug request, when either debug is enabled or disabled a reset. 9.2 • • • • • • • • • • Embedded Characteristics In-order pipeline with dynamic branch prediction Arm, Thumb, and ThumbEE instruction set support TrustZone security extensions Harvard level 1 memory system with a Memory Management Unit (MMU) 32 Kbytes Data Cache 32 Kbytes Instruction Cache 64-bit AXI master interface Armv7 debug architecture Media Processing Engine (MPE) with NEON technology Jazelle hardware acceleration  2017 Microchip Technology Inc. DS60001525A-page 43 SAMA5D4 SERIES 9.3 Block Diagram Figure 9-1: Cortex-A5 Processor Top-level Diagram *'   '   *   %    #$%&                  ' $!           "   ' $!       ! "        " UDPHS_CTRL &= ~AT91C_UDPHS_EN_UDPHS; AT91C_BASE_UDPHS->UDPHS_CTRL |= AT91C_UDPHS_EN_UDPHS; // With OR without DMA !!! for( i=1; iUDPHS_IPFEATURES & AT91C_UDPHS_DMA_CHANNEL_NBR)>>4); i++ ) { // RESET endpoint canal DMA: // DMA stop channel command AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command // Disable endpoint AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLDIS |= 0XFFFFFFFF; // Reset endpoint config AT91C_BASE_UDPHS->UDPHS_EPT[i].UDPHS_EPTCTLCFG = 0; // Reset DMA channel (Buff count and Control field) AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0x02; // NON STOP command // Reset DMA channel 0 (STOP) AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0; // STOP command // Clear DMA channel status (read the register for clear it) AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS = AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS; }  2017 Microchip Technology Inc. DS60001525A-page 855 SAMA5D4 SERIES 35.6.10 Handling Transactions with USB V2.0 Device Peripheral 35.6.10.1 Setup Transaction The setup packet is valid in the DPR while RX_SETUP is set. Once RX_SETUP is cleared by the application, the UDPHS accepts the next packets sent over the device endpoint. When a valid setup packet is accepted by the UDPHS: • • • • The UDPHS device automatically acknowledges the setup packet (sends an ACK response) Payload data is written in the endpoint Sets the RX_SETUP interrupt The BYTE_COUNT field in the UDPHS_EPTSTAx register is updated An endpoint interrupt is generated while RX_SETUP in the UDPHS_EPTSTAx register is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect RX_SETUP polling UDPHS_EPTSTAx or catching an interrupt, read the setup packet in the FIFO, then clear the RX_SETUP bit in the UDPHS_EPTCLRSTA register to acknowledge the setup stage. If STALL_SNT was set to 1, then this bit is automatically reset when a setup token is detected by the device. Then, the device still accepts the setup stage. (Refer to Section 35.6.10.5 “STALL”). 35.6.10.2 NYET NYET is a High Speed only handshake. It is returned by a High Speed endpoint as part of the PING protocol. High Speed devices must support an improved NAK mechanism for Bulk OUT and control endpoints (except setup stage). This mechanism allows the device to tell the host whether it has sufficient endpoint space for the next OUT transfer (refer to USB 2.0 spec 8.5.1 NAK Limiting via Ping Flow Control). The NYET/ACK response to a High Speed Bulk OUT transfer and the PING response are automatically handled by hardware in the UDPHS_EPTCTLx register (except when the user wants to force a NAK response by using the NYET_DIS bit). If the endpoint responds instead to the OUT/DATA transaction with an NYET handshake, this means that the endpoint accepted the data but does not have room for another data payload. The host controller must return to using a PING token until the endpoint indicates it has space available. Figure 35-8: NYET Example with Two Endpoint Banks data 0 ACK data 1 NYET t = 125 μs t=0 Bank 1 E Bank 0 F 35.6.10.3 PING t = 250 μs Bank 1 F Bank 1 F Bank 0 E' Bank 0 E ACK data 0 NYET t = 375 μs Bank 1 F Bank 0 E PING t = 500 μs Bank 1 F Bank 0 F NACK PING t = 625 μs Bank 1 E' Bank 0 F ACK E: empty E': begin to empty F: full Bank 1 E Bank 0 F Data IN Bulk IN or Interrupt IN Data IN packets are sent by the device during the data or the status stage of a control transfer or during an (interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel. There are three ways for an application to transfer a buffer in several packets over the USB: • packet by packet (refer to ”Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)” ) • 64 KB (refer to ”Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host)” ) • DMA (refer to ”Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host)” ) Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host) The application can write one or several banks. DS60001525A-page 856  2017 Microchip Technology Inc. SAMA5D4 SERIES A simple algorithm can be used by the application to send packets regardless of the number of banks associated to the endpoint. Algorithm Description for Each Packet: • The application waits for TXRDY flag to be cleared in the UDPHS_EPTSTAx register before it can perform a write access to the DPR. • The application writes one USB packet of data in the DPR through the 64 KB endpoint logical memory window. • The application sets TXRDY flag in the UDPHS_EPTSETSTAx register. The application is notified that it is possible to write a new packet to the DPR by the TXRDY interrupt. This interrupt can be enabled or masked by setting the TXRDY bit in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register. Algorithm Description to Fill Several Packets: Using the previous algorithm, the application is interrupted for each packet. It is possible to reduce the application overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must be set by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register. The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the intervention of the CPU. This means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware. • The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The application must wait that at least one bank is free. • The application writes a number of bytes inferior to the number of free DPR banks for the endpoint. Each time the application writes the last byte of a bank, the TXRDY signal is automatically set by the UDPHS. • If the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set the TXRDY bit in the UDPHS_EPTSETSTAx register. The application is notified that all banks are free, so that it is possible to write another burst of packets by the BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers. This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism does not operate. A Zero Length Packet can be sent by setting just the TXRDY flag in the UDPHS_EPTSETSTAx register. Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buffer from the memory to the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all transfer types except control transfer. Example DMA configuration: 1. 2. 3. - - Program UDPHS_DMAADDRESS x with the address of the buffer that should be transferred. Enable the interrupt of the DMA in UDPHS_IEN Program UDPHS_ DMACONTROLx: Size of buffer to send: size of the buffer to be sent to the host. END_B_EN: The endpoint can validate the packet (according to the values programmed in the AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.) (Refer to Section 35.7.12 “UDPHS Endpoint Control Disable Register (Isochronous Endpoint)” and Figure 35-13) END_BUFFIT: generate an interrupt when the BUFF_COUNT in UDPHS_DMASTATUSx reaches 0. CHANN_ENB: Run and stop at end of buffer The auto-valid-bank mechanism allows the transfer of data (IN & OUT) without the intervention of the CPU. This means that bank validation (set TXRDY or clear the RXRDY_TXKL bit) is done by hardware. A transfer descriptor can be used. Instead of programming the register directly, a descriptor should be programmed and the address of this descriptor is then given to UDPHS_DMANXTDSC to be processed after setting the LDNXT_DSC field (Load Next Descriptor Now) in UDPHS_DMACONTROLx register. The structure that defines this transfer descriptor must be aligned. Each buffer to be transferred must be described by a DMA Transfer descriptor (refer to Section 35.7.21 “UDPHS DMA Channel Transfer Descriptor”). Transfer descriptors are chained. Before executing transfer of the buffer, the UDPHS may fetch a new transfer descriptor from the memory address pointed by the UDPHS_DMANXTDSCx register. Once the transfer is complete, the transfer status is updated in the UDPHS_DMASTATUSx register. To chain a new transfer descriptor with the current DMA transfer, the DMA channel must be stopped. To do so, INTDIS_DMA and TXRDY may be set in the UDPHS_EPTCTLENBx register. It is also possible for the application to wait for the completion of all transfers. In this case the LDNXT_DSC bit in the last transfer descriptor UDPHS_DMACONTROLx register must be set to 0 and the CHANN_ENB bit set to 1.  2017 Microchip Technology Inc. DS60001525A-page 857 SAMA5D4 SERIES Then the application can chain a new transfer descriptor. The INTDIS_DMA can be used to stop the current DMA transfer if an enabled interrupt is triggered. This can be used to stop DMA transfers in case of errors. The application can be notified at the end of any buffer transfer (ENB_BUFFIT bit in the UDPHS_DMACONTROLx register). Figure 35-9: Data IN Transfer for Endpoint with One Bank Prevous Data IN TX USB Bus Packets Token IN Data IN 1 TXRDY Flag (UDPHS_EPTSTAx) Set by firmware Microcontroller Loads Data in FIFO ACK Token IN NAK Cleared by hardware Data is Sent on USB Bus Token IN Data IN 2 Set by the firmware ACK Cleared by hardware Interrupt Pending TX_COMPLT Flag (UDPHS_EPTSTAx) Payload in FIFO Set by hardware DPR access by firmware FIFO Content DS60001525A-page 858 Interrupt Pending Data IN 1 Load in progress Cleared by firmware Cleared by firmware DPR access by hardware Data IN 2  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 35-10: Data IN Transfer for Endpoint with Two Banks Microcontroller Load Data IN Bank 0 USB Bus Packets Microcontroller Load Data IN Bank 1 UDPHS Device Send Bank 0 Token IN Data IN Microcontroller Load Data IN Bank 0 UDPHS Device Send Bank 1 ACK Token IN Data IN ACK Set by Firmware, Cleared by Hardware Data Payload Written switch to next bank in FIFO Bank 0 Virtual TXRDY bank 0 (UDPHS_EPTSTAx) Cleared by Hardware Data Payload Fully Transmitted Virtual TXRDY bank 1 (UDPHS_EPTSTAx) Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending TX_COMPLT Flag (UDPHS_EPTSTAx) FIFO (DPR) Bank 0 Set by Hardware Interrupt Cleared by Firmware Written by Microcontroller Written by Microcontroller Read by UDPHS Device Data IN Followed By Status OUT Transfer at the End of a Control Transfer Device Sends the Last Data Payload to Host USB Bus Packets Written by Microcontroller Read by USB Device FIFO (DPR) Bank1 Figure 35-11: Set by Hardware Token IN Data IN Device Sends a Status OUT to Host ACK Token OUT Data OUT (ZLP) ACK Token OUT Data OUT (ZLP) ACK Interrupt Pending RXRDY (UDPHS_EPTSTAx) Set by Hardware Cleared by Firmware TX_COMPLT (UDPHS_EPTSTAx) Set by Hardware Note: Cleared by Firmware A NAK handshake is always generated at the first status stage token.  2017 Microchip Technology Inc. DS60001525A-page 859 SAMA5D4 SERIES Figure 35-12: Data OUT Followed by Status IN Transfer Host Sends the Last Data Payload to the Device USB Bus Packets Token OUT Data OUT Device Sends a Status IN to the Host ACK Token IN Data IN ACK Interrupt Pending RXRDY (UDPHS_EPTSTAx) Cleared by Firmware Set by Hardware TXRDY (UDPHS_EPTSTAx) Set by Firmware Note: Clear by Hardware Before proceeding to the status stage, the software should determine that there is no risk of extra data from the host (data stage). If not certain (non-predictable data stage length), then the software should wait for a NAK-IN interrupt before proceeding to the status stage. This precaution should be taken to avoid collision in the FIFO. Figure 35-13: Autovalid with DMA Bank (system) Write Bank 0 Bank 1 write bank 0 write bank 1 bank 0 is full Bank 1 Bank 0 Bank 1 write bank 0 bank 1 is full bank 0 is full Bank 0 IN data 0 Bank (usb) Bank 0 IN data 1 Bank 1 IN data 0 Bank 0 Bank 1 Virtual TXRDY Bank 0 Virtual TXRDY Bank 1 TXRDY (Virtual 0 & Virtual 1) Note: In the illustration above Autovalid validates a bank as full, although this might not be the case, in order to continue processing data and to send to DMA. DS60001525A-page 860  2017 Microchip Technology Inc. SAMA5D4 SERIES Isochronous IN Isochronous-IN is used to transmit a stream of data whose timing is implied by the delivery rate. Isochronous transfer provides periodic, continuous communication between host and device. It guarantees bandwidth and low latencies appropriate for telephony, audio, video, etc. If the endpoint is not available (TXRDY_TRER = 0), then the device does not answer to the host. An ERR_FL_ISO interrupt is generated in the UDPHS_EPTSTAx register and once enabled, then sent to the CPU. The STALL_SNT command bit is not used for an ISO-IN endpoint. High Bandwidth Isochronous Endpoint Handling: IN Example For high bandwidth isochronous endpoints, the DMA can be programmed with the number of transactions (BUFF_LENGTH field in UDPHS_DMACONTROLx) and the system should provide the required number of packets per microframe, otherwise, the host will notice a sequencing problem. A response should be made to the first token IN recognized inside a microframe under the following conditions: • If at least one bank has been validated, the correct DATAx corresponding to the programmed Number Of Transactions per Microframe (NB_TRANS) should be answered. In case of a subsequent missed or corrupted token IN inside the microframe, the USB 2.0 Core available data bank(s) that should normally have been transmitted during that microframe shall be flushed at its end. If this flush occurs, an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx). • If no bank is validated yet, the default DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). Then, no data bank is flushed at microframe end. • If no data bank has been validated at the time when a response should be made for the second transaction of NB_TRANS = 3 transactions microframe, a DATA1 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). If and only if remaining untransmitted banks for that microframe are available at its end, they are flushed and an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx). • If no data bank has been validated at the time when a response should be made for the last programmed transaction of a microframe, a DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). If and only if the remaining untransmitted data bank for that microframe is available at its end, it is flushed and an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx). • If at the end of a microframe no valid token IN has been recognized, no data bank is flushed and no error condition is reported. At the end of a microframe in which at least one data bank has been transmitted, if less than NB_TRANS banks have been validated for that microframe, an error condition is flagged (ERR_TRANS is set in UDPHS_EPTSTAx). Cases of Error (in UDPHS_EPTSTAx) • ERR_FL_ISO: There was no data to transmit inside a microframe, so a ZLP is answered by default. • ERR_FLUSH: At least one packet has been sent inside the microframe, but the number of token INs received is less than the number of transactions actually validated (TXRDY_TRER) and likewise with the NB_TRANS programmed. • ERR_TRANS: At least one packet has been sent inside the microframe, but the number of token INs received is less than the number of programmed NB_TRANS transactions and the packets not requested were not validated. • ERR_FL_ISO + ERR_FLUSH: At least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token INs. • ERR_FL_ISO + ERR_TRANS: At least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token INs and the data can be discarded at the microframe end. • ERR_FLUSH + ERR_TRANS: The first token IN has been answered and it was the only one received, a second bank has been validated but not the third, whereas NB_TRANS was waiting for three transactions. • ERR_FL_ISO + ERR_FLUSH + ERR_TRANS: The first token IN has been treated, the data for the second Token IN was not available in time, but the second bank has been validated before the end of the microframe. The third bank has not been validated, but three transactions have been set in NB_TRANS. 35.6.10.4 Data OUT Bulk OUT or Interrupt OUT Like data IN, data OUT packets are sent by the host during the data or the status stage of control transfer or during an interrupt/bulk/isochronous OUT transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel. Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device)  2017 Microchip Technology Inc. DS60001525A-page 861 SAMA5D4 SERIES Algorithm Description for Each Packet: • The application enables an interrupt on RXRDY_TXKL. • When an interrupt on RXRDY_TXKL is received, the application knows that UDPHS_EPTSTAx register BYTE_COUNT bytes have been received. • The application reads the BYTE_COUNT bytes from the endpoint. • The application clears RXRDY_TXKL. Note: If the application does not know the size of the transfer, it may not be a good option to use AUTO_VALID. Because if a zerolength-packet is received, the RXRDY_TXKL is automatically cleared by the AUTO_VALID hardware and if the endpoint interrupt is triggered, the software will not find its originating flag when reading the UDPHS_EPTSTAx register. Algorithm to Fill Several Packets: • The application enables the interrupts of BUSY_BANK and AUTO_VALID. • When a BUSY_BANK interrupt is received, the application knows that all banks available for the endpoint have been filled. Thus, the application can read all banks available. If the application does not know the size of the receive buffer, instead of using the BUSY_BANK interrupt, the application must use RXRDY_TXKL. Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device) To use the DMA setting, the AUTO_VALID field is mandatory. Refer to Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) for more information. DMA Configuration Example: 1. 2. 3. - First program UDPHS_DMAADDRESSx with the address of the buffer that should be transferred. Enable the interrupt of the DMA in UDPHS_IEN Program the DMA Channelx Control Register: Size of buffer to be sent. END_B_EN: Can be used for OUT packet truncation (discarding of unbuffered packet data) at the end of DMA buffer. END_BUFFIT: Generate an interrupt when BUFF_COUNT in the UDPHS_DMASTATUSx register reaches 0. END_TR_EN: End of transfer enable, the UDPHS device can put an end to the current DMA transfer, in case of a short packet. END_TR_IT: End of transfer interrupt enable, an interrupt is sent after the last USB packet has been transferred by the DMA, if the USB transfer ended with a short packet. (Beneficial when the receive size is unknown.) CHANN_ENB: Run and stop at end of buffer. For OUT transfer, the bank will be automatically cleared by hardware when the application has read all the bytes in the bank (the bank is empty). Note 1: When a zero-length-packet is received, RXRDY_TXKL bit in UDPHS_EPTSTAx is cleared automatically by AUTO_VALID, and the application knows of the end of buffer by the presence of the END_TR_IT. 2: If the host sends a zero-length packet, and the endpoint is free, then the device sends an ACK. No data is written in the endpoint, the RXRDY_TXKL interrupt is generated, and the BYTE_COUNT field in UDPHS_EPTSTAx is null. DS60001525A-page 862  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 35-14: Data OUT Transfer for Endpoint with One Bank Host Sends Data Payload USB Bus Packets Token OUT Data OUT 1 ACK Token OUT Data OUT 1 Written by UDPHS Device NAK Data OUT 2 Token OUT ACK Cleared by Firmware, Data Payload Written in FIFO Data OUT 1 Data OUT 2 Microcontroller Read Written by UDPHS Device Data OUT Transfer for an Endpoint with Two Banks Microcontroller reads Data 1 in bank 0, Host sends second data payload Host sends first data payload Virtual RXRDY Bank 0 Data OUT 2 Set by Hardware FIFO (DPR) Content USB Bus Packets Host Resends the Next Data Payload Interrupt Pending RXRDY (UDPHS_EPTSTAx) Figure 35-15: Microcontroller Transfers Data Host Sends the Next Data Payload Token OUT Data OUT 1 ACK Token OUT Data OUT 2 Virtual RXRDY Bank 1 Token OUT Data OUT 3 Cleared by Firmware Interrupt pending Set by Hardware, Data payload written in FIFO endpoint bank 0 ACK Microcontroller reads Data 2 in bank 1, Host sends third data payload Set by Hardware Data Payload written in FIFO endpoint bank 1 Cleared by Firmware Interrupt pending RXRDY = (virtual bank 0 | virtual bank 1) (UDPHS_EPTSTAx) FIFO (DPR) Bank 0 Data OUT 1 Data OUT 3 Read by Microcontroller Write in progress Data OUT 1 Write by UDPHS Device FIFO (DPR) Bank 1 Data OUT 2 Write by Hardware Data OUT 2 Read by Microcontroller High Bandwidth Isochronous Endpoint OUT USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192 Mb/s (24 MB/s): 3x1024 data bytes per microframe. To support such a rate, two or three banks may be used to buffer the three consecutive data packets. The microcontroller (or the DMA) should be able to empty the banks very rapidly (at least 24 MB/s on average). NB_TRANS field in UDPHS_EPTCFGx register = Number Of Transactions per Microframe. If NB_TRANS > 1 then it is High Bandwidth.  2017 Microchip Technology Inc. DS60001525A-page 863 SAMA5D4 SERIES Example: • If NB_TRANS = 3, the sequence should be either - MData0 - MData0/Data1 - MData0/Data1/Data2 • If NB_TRANS = 2, the sequence should be either - MData0 - MData0/Data1 • If NB_TRANS = 1, the sequence should be - Data0 Figure 35-16: USB bus Transactions Bank Management, Example of Three Transactions per Microframe MDATA0 MDATA1 DATA2 t = 52.5 μs (40% of 125 μs) t=0 RXRDY Microcontroller FIFO (DPR) Access MDATA0 Read Bank 1 Read Bank 2 MDATA1 DATA2 USB line t = 125 μs RXRDY Read Bank 3 Read Bank 1 Isochronous Endpoint Handling: OUT Example The user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank with the UDPHS_EPTSTAx register in the three fields as follows: • TOGGLESQ_STA: PID of the data stored in the current bank • CURBK: Number of the bank currently being accessed by the microcontroller. • BUSY_BANK_STA: Number of busy bank This is particularly useful in case of a missing data packet. If the inter-packet delay between the OUT token and the Data is greater than the USB standard, then the ISO-OUT transaction is ignored. (Payload data is not written, no interrupt is generated to the CPU.) If there is a data CRC (Cyclic Redundancy Check) error, the payload is, none the less, written in the endpoint. The ERR_CRC_NTR flag is set in UDPHS_EPTSTAx register. If the endpoint is already full, the packet is not written in the DPRAM. The ERR_FL_ISO flag is set in UDPHS_EPTSTAx. If the payload data is greater than the maximum size of the endpoint, then the ERR_OVFLW flag is set. It is the task of the CPU to manage this error. The data packet is written in the endpoint (except the extra data). If the host sends a Zero Length Packet, and the endpoint is free, no data is written in the endpoint, the RXRDY_TXKL flag is set, and the BYTE_COUNT field in UDPHS_EPTSTAx register is null. The FRCESTALL command bit is unused for an isochronous endpoint. Otherwise, payload data is written in the endpoint, the RXRDY_TXKL interrupt is generated and the BYTE_COUNT in UDPHS_EPTSTAx register is updated. 35.6.10.5 STALL STALL is returned by a function in response to an IN token or after the data phase of an OUT or in response to a PING transaction. STALL indicates that a function is unable to transmit or receive data, or that a control pipe request is not supported. • OUT To stall an endpoint, set the FRCESTALL bit in UDPHS_EPTSETSTAx register and after the STALL_SNT flag has been set, set the TOGGLE_SEG bit in the UDPHS_EPTCLRSTAx register. • IN Set the FRCESTALL bit in UDPHS_EPTSETSTAx register. DS60001525A-page 864  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 35-17: Stall Handshake Data OUT Transfer USB Bus Packets Data OUT Token OUT Stall PID FRCESTALL Set by Firmware Cleared by Firmware Interrupt Pending STALL_SNT Set by Hardware Figure 35-18: Cleared by Firmware Stall Handshake Data IN Transfer USB Bus Packets Token IN Stall PID FRCESTALL Cleared by Firmware Set by Firmware Interrupt Pending STALL_SNT Set by Hardware 35.6.11 Cleared by Firmware Speed Identification The high speed reset is managed by hardware. At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset. At the end of the reset process (full or high), the ENDRESET interrupt is generated. Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of the device. 35.6.12 USB V2.0 High Speed Global Interrupt Interrupts are defined in Section 35.7.3 “UDPHS Interrupt Enable Register” (UDPHS_IEN) and in Section 35.7.4 “UDPHS Interrupt Status Register” (UDPHS_INTSTA). 35.6.13 Endpoint Interrupts Interrupts are enabled in UDPHS_IEN (refer to Section 35.7.3 “UDPHS Interrupt Enable Register”) and individually masked in UDPHS_EPTCTLENBx (refer to Section 35.7.9 “UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)”). Table 35-5: Endpoint Interrupt Source Masks SHRT_PCKT Short Packet Interrupt BUSY_BANK Busy Bank Interrupt NAK_OUT NAKOUT Interrupt NAK_IN/ERR_FLUSH NAKIN/Error Flush Interrupt STALL_SNT/ERR_CRC_NTR Stall Sent/CRC error/Number of Transaction Error Interrupt RX_SETUP/ERR_FL_ISO Received SETUP/Error Flow Interrupt TXRDY_TRER TX Packet Read/Transaction Error Interrupt  2017 Microchip Technology Inc. DS60001525A-page 865 SAMA5D4 SERIES Table 35-5: Endpoint Interrupt Source Masks (Continued) TX_COMPLT Transmitted IN Data Complete Interrupt RXRDY_TXKL Received OUT Data Interrupt ERR_OVFLW Overflow Error Interrupt MDATA_RX MDATA Interrupt DATAX_RX DATAx Interrupt DS60001525A-page 866  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 35-19: UDPHS Interrupt Control Interface (UDPHS_IEN) Global IT mask Global IT sources DET_SUSPD MICRO_SOF USB Global IT Sources INT_SOF ENDRESET WAKE_UP ENDOFRSM UPSTR_RES (UDPHS_EPTCTLENBx) SHRT_PCKT EP mask BUSY_BANK EP sources NAK_OUT (UDPHS_IEN) EPT_0 husb2dev interrupt NAK_IN/ERR_FLUSH STALL_SNT/ER_CRC_NTR EPT0 IT Sources RX_SETUP/ERR_FL_ISO TXRDY_TRER TX_COMPLT RXRDY_TXKL ERR_OVFLW MDATA_RX DATAX_RX (UDPHS_IEN) EPT_x EP mask EP sources (UDPHS_EPTCTLx) INTDIS_DMA EPT1-6 IT Sources disable DMA channelx request (UDPHS_DMACONTROLx) mask (UDPHS_IEN) DMA_x EN_BUFFIT mask DMA CH x END_TR_IT mask DESC_LD_IT  2017 Microchip Technology Inc. DS60001525A-page 867 SAMA5D4 SERIES 35.6.14 35.6.14.1 Power Modes Controlling Device States A USB device has several possible states. Refer to Chapter 9 (USB Device Framework) of the Universal Serial Bus Specification, Rev 2.0. Figure 35-20: UDPHS Device State Diagram Attached Hub Reset Hub or Configured Deconfigured Bus Inactive Powered Suspended Bus Activity Power Interruption Reset Bus Inactive Suspended Default Bus Activity Reset Address Assigned Bus Inactive Suspended Address Bus Activity Device Deconfigured Device Configured Bus Inactive Configured Suspended Bus Activity Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the USB device enters Suspend mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend mode are very strict for bus-powered applications; devices may not consume more than 500 µA on the USB bus. While in Suspend mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wakeup request to the host, e.g., waking up a PC by moving a USB mouse. The wakeup feature is not mandatory for all devices and must be negotiated with the host. 35.6.14.2 Not Powered State Self powered devices can detect 5V VBUS using a PIO. When the device is not connected to a host, device power consumption can be reduced by the DETACH bit in UDPHS_CTRL. Disabling the transceiver is automatically done. HSDM, HSDP, FSDP and FSDP lines are tied to GND pull-downs integrated in the hub downstream ports. DS60001525A-page 868  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.6.14.3 Entering Attached State When no device is connected, the USB FSDP and FSDM signals are tied to GND by 15 KΩ pull-downs integrated in the hub downstream ports. When a device is attached to an hub downstream port, the device connects a 1.5 KΩ pull-up on FSDP. The USB bus line goes into IDLE state, FSDP is pulled-up by the device 1.5 KΩ resistor to 3.3V and FSDM is pulled-down by the 15 KΩ resistor to GND of the host. After pull-up connection, the device enters the powered state. The transceiver remains disabled until bus activity is detected. In case of low power consumption need, the device can be stopped. When the device detects the VBUS, the software must enable the USB transceiver by enabling the EN_UDPHS bit in UDPHS_CTRL register. The software can detach the pull-up by setting DETACH bit in UDPHS_CTRL register. 35.6.14.4 From Powered State to Default State (Reset) After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmasked flag ENDRESET is set in the UDPHS_IEN register and an interrupt is triggered. Once the ENDRESET interrupt has been triggered, the device enters Default State. In this state, the UDPHS software must: • Enable the default endpoint, setting the EPT_ENABL flag in the UDPHS_EPTCTLENB[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 in EPT_0 of the UDPHS_IEN register. The enumeration then begins by a control transfer. • Configure the Interrupt Mask Register which has been reset by the USB reset detection • Enable the transceiver. In this state, the EN_UDPHS bit in UDPHS_CTRL register must be enabled. 35.6.14.5 From Default State to Address State (Address Assigned) After a Set Address standard device request, the USB host peripheral enters the address state. Warning: before the device enters address state, it must achieve the Status IN transaction of the control transfer, i.e., the UDPHS device sets its new address once the TX_COMPLT flag in the UDPHS_EPTCTL[0] register has been received and cleared. To move to address state, the driver software sets the DEV_ADDR field and the FADDR_EN flag in the UDPHS_CTRL register. 35.6.14.6 From Address State to Configured State (Device Configured) Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the BK_NUMBER, EPT_TYPE, EPT_DIR and EPT_SIZE fields in the UDPHS_EPTCFGx registers and enabling them by setting the EPT_ENABL flag in the UDPHS_EPTCTLENBx registers, and, optionally, enabling corresponding interrupts in the UDPHS_IEN register. 35.6.14.7 Entering Suspend State (Bus Activity) When a Suspend (no bus activity on the USB bus) is detected, the DET_SUSPD signal in the UDPHS_STA register is set. This triggers an interrupt if the corresponding bit is set in the UDPHS_IEN register. This flag is cleared by writing to the UDPHS_CLRINT register. Then the device enters Suspend mode. In this state bus powered devices must drain less than 500 µA from the 5V VBUS. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle mode. It may also switch off other devices on the board. The UDPHS device peripheral clocks can be switched off. Resume event is asynchronously detected. 35.6.14.8 Receiving a Host Resume In Suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks disabled (however the pull-up should not be removed). Once the resume is detected on the bus, the signal WAKE_UP in the UDPHS_INTSTA is set. It may generate an interrupt if the corresponding bit in the UDPHS_IEN register is set. This interrupt may be used to wake up the core, enable PLL and main oscillators and configure clocks. 35.6.14.9 Sending an External Resume In Suspend State it is possible to wake up the host by sending an external resume. The device waits at least 5 ms after being entered in Suspend State before sending an external resume. The device must force a K state from 1 to 15 ms to resume the host.  2017 Microchip Technology Inc. DS60001525A-page 869 SAMA5D4 SERIES 35.6.15 Test Mode A device must support the TEST_MODE feature when in the Default, Address or Configured High Speed device states. TEST_MODE can be: • • • • Test_J Test_K Test_Packet Test_SEO_NAK (Refer to Section 35.7.7 “UDPHS Test Register” for definitions of each test mode.) const char test_packet_buffer[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, 0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, 0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, 0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD, 0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E }; DS60001525A-page 870 // // // // // // JKJKJKJK * 9 JJKKJJKK * 8 JJKKJJKK * 8 JJJJJJJKKKKKKK * 8 JJJJJJJK * 8 {JKKKKKKK * 10}, JK  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7 USB High Speed Device Port (UDPHS) User Interface Table 35-6: Register Mapping Offset Register Name 0x00 UDPHS Control Register UDPHS_CTRL Read/Write 0x0000_0200 0x04 UDPHS Frame Number Register UDPHS_FNUM Read-only 0x0000_0000 0x08–0x0C Reserved – – – 0x10 UDPHS Interrupt Enable Register UDPHS_IEN Read/Write 0x0000_0010 0x14 UDPHS Interrupt Status Register UDPHS_INTSTA Read-only 0x0000_0000 0x18 UDPHS Clear Interrupt Register UDPHS_CLRINT Write-only – 0x1C UDPHS Endpoints Reset Register UDPHS_EPTRST Write-only – 0x20–0xCC Reserved – – – 0xE0 UDPHS Test Register UDPHS_TST Read/Write 0x0000_0000 0xE4–0xFC Reserved – – – 0x100 + endpoint * 0x20 + 0x00 UDPHS Endpoint Configuration Register UDPHS_EPTCFG Read/Write 0x0000_0000 0x100 + endpoint * 0x20 + 0x04 UDPHS Endpoint Control Enable Register UDPHS_EPTCTLENB Write-only – 0x100 + endpoint * 0x20 + 0x08 UDPHS Endpoint Control Disable Register UDPHS_EPTCTLDIS Write-only – 0x100 + endpoint * 0x20 + 0x0C UDPHS Endpoint Control Register UDPHS_EPTCTL Read-only ) 0x100 + endpoint * 0x20 + 0x10 Reserved (for endpoint) – – – 0x100 + endpoint * 0x20 + 0x14 UDPHS Endpoint Set Status Register UDPHS_EPTSETSTA Write-only – 0x100 + endpoint * 0x20 + 0x18 UDPHS Endpoint Clear Status Register UDPHS_EPTCLRSTA Write-only – 0x100 + endpoint * 0x20 + 0x1C UDPHS Endpoint Status Register Access Reset 0x0000_0000(1 UDPHS_EPTSTA Read-only 0x0000_0040 0x120–0x2FC UDPHS Endpoint1 to 15 (2) Registers – – – 0x300 + channel * 0x10 + 0x00 UDPHS DMA Next Descriptor Address Register UDPHS_DMANXTDSC Read/Write 0x0000_0000 0x300 + channel * 0x10 + 0x04 UDPHS DMA Channel Address Register UDPHS_DMAADDRESS Read/Write 0x0000_0000 0x300 + channel * 0x10 + 0x08 UDPHS DMA Channel Control Register UDPHS_DMACONTRO L Read/Write 0x0000_0000 0x300 + channel * 0x10 + 0x0C UDPHS DMA Channel Status Register UDPHS_DMASTATUS Read/Write 0x0000_0000 – – – 0x310–0x36C DMA Channel1 to 6 (3) Registers Note 1: The reset value for UDPHS_EPTCTL0 is 0x0000_0001. 2: The addresses for the UDPHS Endpoint registers shown here are for UDPHS Endpoint0. The structure of this group of registers is repeated successively for each endpoint according to the sequence of endpoint registers located between 0x120 and 0x2FC. 3: The DMA channel index refers to the corresponding EP number. When no DMA channel is assigned to one EP, the associated registers are reserved. This is the case for EP0, so DMA Channel 0 registers are reserved.  2017 Microchip Technology Inc. DS60001525A-page 871 SAMA5D4 SERIES 35.7.1 UDPHS Control Register Name: UDPHS_CTRL Address:0xFC02C000 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 PULLD_DIS 10 REWAKEUP 9 DETACH 8 EN_UDPHS 7 FADDR_EN 6 5 4 3 DEV_ADDR 2 1 0 DEV_ADDR: UDPHS Address (cleared upon USB reset) This field contains the default address (0) after powerup or UDPHS bus reset (read), or it is written with the value set by a SET_ADDRESS request received by the device firmware (write). FADDR_EN: Function Address Enable (cleared upon USB reset) 0: Device is not in address state (read), or only the default function address is used (write). 1: Device is in address state (read), or this bit is set by the device firmware after a successful status phase of a SET_ADDRESS transaction (write). When set, the only address accepted by the UDPHS controller is the one stored in the UDPHS Address field. It will not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset, or when UDPHS bus reset is received. EN_UDPHS: UDPHS Enable 0: UDPHS is disabled (read), or this bit disables and resets the UDPHS controller (write). Switch the host to UTMI. 1: UDPHS is enabled (read), or this bit enables the UDPHS controller (write). Switch the host to UTMI. DETACH: Detach Command 0: UDPHS is attached (read), or this bit pulls up the DP line (attach command) (write). 1: UDPHS is detached, UTMI transceiver is suspended (read), or this bit simulates a detach on the UDPHS line and forces the UTMI transceiver into suspend state (Suspend M = 0) (write). Refer to “PULLD_DIS: Pull-Down Disable (cleared upon USB reset)”. REWAKEUP: Send Remote Wakeup (cleared upon USB reset) 0: Remote Wakeup is disabled (read), or this bit has no effect (write). 1: Remote Wakeup is enabled (read), or this bit forces an external interrupt on the UDPHS controller for Remote Wakeup purposes. An Upstream Resume is sent only after the UDPHS bus has been in SUSPEND state for at least 5 ms. This bit is automatically cleared by hardware at the end of the Upstream Resume. PULLD_DIS: Pull-Down Disable (cleared upon USB reset) When set, there is no pull-down on DP & DM. (DM Pull-Down = DP Pull-Down = 0). Note: If the DETACH bit is also set, device DP & DM are left in high impedance state. DS60001525A-page 872  2017 Microchip Technology Inc. SAMA5D4 SERIES (Refer to “DETACH: Detach Command”.) DETACH PULLD_DIS DP DM Condition 0 0 Pull up Pull down Not recommended 0 1 Pull up High impedance state VBUS present 1 0 Pull down Pull down No VBUS 1 1 High impedance state High impedance state VBUS present & software disconnect  2017 Microchip Technology Inc. DS60001525A-page 873 SAMA5D4 SERIES 35.7.2 UDPHS Frame Number Register Name: UDPHS_FNUM Address:0xFC02C004 Access: Read-only 31 FNUM_ERR 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 10 FRAME_NUMBER 9 8 7 6 5 FRAME_NUMBER 4 3 1 MICRO_FRAME_NUM 0 2 MICRO_FRAME_NUM: Microframe Number (cleared upon USB reset) Number of the received microframe (0 to 7) in one frame.This field is reset at the beginning of each new frame (1 ms). One microframe is received each 125 microseconds (1 ms/8). FRAME_NUMBER: Frame Number as defined in the Packet Field Formats (cleared upon USB reset) This field is provided in the last received SOF packet (refer to INT_SOF in the UDPHS Interrupt Status Register). FNUM_ERR: Frame Number CRC Error (cleared upon USB reset) This bit is set by hardware when a corrupted Frame Number in Start of Frame packet (or Micro SOF) is received. This bit and the INT_SOF (or MICRO_SOF) interrupt are updated at the same time. DS60001525A-page 874  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.3 UDPHS Interrupt Enable Register Name: UDPHS_IEN Address:0xFC02C010 Access: Read/Write 31 DMA_7 30 DMA_6 29 DMA_5 28 DMA_4 27 DMA_3 26 DMA_2 25 DMA_1 24 – 23 EPT_15 22 EPT_14 21 EPT_13 20 EPT_12 19 EPT_11 18 EPT_10 17 EPT_9 16 EPT_8 15 EPT_7 14 EPT_6 13 EPT_5 12 EPT_4 11 EPT_3 10 EPT_2 9 EPT_1 8 EPT_0 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 – DET_SUSPD: Suspend Interrupt Enable (cleared upon USB reset) 0: Disable Suspend Interrupt. 1: Enable Suspend Interrupt. MICRO_SOF: Micro-SOF Interrupt Enable (cleared upon USB reset) 0: Disable Micro-SOF Interrupt. 1: Enable Micro-SOF Interrupt. INT_SOF: SOF Interrupt Enable (cleared upon USB reset) 0: Disable SOF Interrupt. 1: Enable SOF Interrupt. ENDRESET: End Of Reset Interrupt Enable (cleared upon USB reset) 0: Disable End Of Reset Interrupt. 1: Enable End Of Reset Interrupt. Automatically enabled after USB reset. WAKE_UP: Wakeup CPU Interrupt Enable (cleared upon USB reset) 0: Disable Wakeup CPU Interrupt. 1: Enable Wakeup CPU Interrupt. ENDOFRSM: End Of Resume Interrupt Enable (cleared upon USB reset) 0: Disable Resume Interrupt. 1: Enable Resume Interrupt. UPSTR_RES: Upstream Resume Interrupt Enable (cleared upon USB reset) 0: Disable Upstream Resume Interrupt. 1: Enable Upstream Resume Interrupt. EPT_x: Endpoint x Interrupt Enable (cleared upon USB reset) 0: Disable the interrupts for this endpoint. 1: Enable the interrupts for this endpoint. DMA_x: DMA Channel x Interrupt Enable (cleared upon USB reset) 0: Disable the interrupts for this channel. 1: Enable the interrupts for this channel.  2017 Microchip Technology Inc. DS60001525A-page 875 SAMA5D4 SERIES 35.7.4 UDPHS Interrupt Status Register Name: UDPHS_INTSTA Address:0xFC02C014 Access: Read-only 31 DMA_7 30 DMA_6 29 DMA_5 28 DMA_4 27 DMA_3 26 DMA_2 25 DMA_1 24 – 23 EPT_15 22 EPT_14 21 EPT_13 20 EPT_12 19 EPT_11 18 EPT_10 17 EPT_9 16 EPT_8 15 EPT_7 14 EPT_6 13 EPT_5 12 EPT_4 11 EPT_3 10 EPT_2 9 EPT_1 8 EPT_0 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 SPEED SPEED: Speed Status 0: Reset by hardware when the hardware is in Full Speed mode. 1: Set by hardware when the hardware is in High Speed mode. DET_SUSPD: Suspend Interrupt 0: Cleared by setting the DET_SUSPD bit in UDPHS_CLRINT register. 1: Set by hardware when a UDPHS Suspend (Idle bus for three frame periods, a J state for 3 ms) is detected. This triggers a UDPHS interrupt when the DET_SUSPD bit is set in UDPHS_IEN register. MICRO_SOF: Micro Start Of Frame Interrupt 0: Cleared by setting the MICRO_SOF bit in UDPHS_CLRINT register. 1: Set by hardware when an UDPHS micro start of frame PID (SOF) has been detected (every 125 us) or synthesized by the macro. This triggers a UDPHS interrupt when the MICRO_SOF bit is set in UDPHS_IEN. In case of detected SOF, the MICRO_FRAME_NUM field in UDPHS_FNUM register is incremented and the FRAME_NUMBER field does not change. Note: The Micro Start Of Frame Interrupt (MICRO_SOF), and the Start Of Frame Interrupt (INT_SOF) are not generated at the same time. INT_SOF: Start Of Frame Interrupt 0: Cleared by setting the INT_SOF bit in UDPHS_CLRINT. 1: Set by hardware when an UDPHS Start Of Frame PID (SOF) has been detected (every 1 ms) or synthesized by the macro. This triggers a UDPHS interrupt when the INT_SOF bit is set in UDPHS_IEN register. In case of detected SOF, in High Speed mode, the MICRO_FRAME_NUMBER field is cleared in UDPHS_FNUM register and the FRAME_NUMBER field is updated. ENDRESET: End Of Reset Interrupt 0: Cleared by setting the ENDRESET bit in UDPHS_CLRINT. 1: Set by hardware when an End Of Reset has been detected by the UDPHS controller. This triggers a UDPHS interrupt when the ENDRESET bit is set in UDPHS_IEN. WAKE_UP: Wakeup CPU Interrupt 0: Cleared by setting the WAKE_UP bit in UDPHS_CLRINT. 1: Set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from the UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN register. When receiving this interrupt, the user has to enable the device controller clock prior to operation. Note: this interrupt is generated even if the device controller clock is disabled. DS60001525A-page 876  2017 Microchip Technology Inc. SAMA5D4 SERIES ENDOFRSM: End Of Resume Interrupt 0: Cleared by setting the ENDOFRSM bit in UDPHS_CLRINT. 1: Set by hardware when the UDPHS controller detects a good end of resume signal initiated by the host. This triggers a UDPHS interrupt when the ENDOFRSM bit is set in UDPHS_IEN. UPSTR_RES: Upstream Resume Interrupt 0: Cleared by setting the UPSTR_RES bit in UDPHS_CLRINT. 1: Set by hardware when the UDPHS controller is sending a resume signal called “upstream resume”. This triggers a UDPHS interrupt when the UPSTR_RES bit is set in UDPHS_IEN. EPT_x: Endpoint x Interrupt (cleared upon USB reset) 0: Reset when the UDPHS_EPTSTAx interrupt source is cleared. 1: Set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_x bit in UDPHS_IEN. DMA_x: DMA Channel x Interrupt 0: Reset when the UDPHS_DMASTATUSx interrupt source is cleared. 1: Set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_x bit in UDPHS_IEN.  2017 Microchip Technology Inc. DS60001525A-page 877 SAMA5D4 SERIES 35.7.5 UDPHS Clear Interrupt Register Name: UDPHS_CLRINT Address:0xFC02C018 Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 UPSTR_RES 6 ENDOFRSM 5 WAKE_UP 4 ENDRESET 3 INT_SOF 2 MICRO_SOF 1 DET_SUSPD 0 – DET_SUSPD: Suspend Interrupt Clear 0: No effect. 1: Clear the DET_SUSPD bit in UDPHS_INTSTA. MICRO_SOF: Micro Start Of Frame Interrupt Clear 0: No effect. 1: Clear the MICRO_SOF bit in UDPHS_INTSTA. INT_SOF: Start Of Frame Interrupt Clear 0: No effect. 1: Clear the INT_SOF bit in UDPHS_INTSTA. ENDRESET: End Of Reset Interrupt Clear 0: No effect. 1: Clear the ENDRESET bit in UDPHS_INTSTA. WAKE_UP: Wakeup CPU Interrupt Clear 0: No effect. 1: Clear the WAKE_UP bit in UDPHS_INTSTA. ENDOFRSM: End Of Resume Interrupt Clear 0: No effect. 1: Clear the ENDOFRSM bit in UDPHS_INTSTA. UPSTR_RES: Upstream Resume Interrupt Clear 0: No effect. 1: Clear the UPSTR_RES bit in UDPHS_INTSTA. DS60001525A-page 878  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.6 UDPHS Endpoints Reset Register Name: UDPHS_EPTRST Address:0xFC02C01C Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 EPT_15 14 EPT_14 13 EPT_13 12 EPT_12 11 EPT_11 10 EPT_10 9 EPT_9 8 EPT_8 7 EPT_7 6 EPT_6 5 EPT_5 4 EPT_4 3 EPT_3 2 EPT_2 1 EPT_1 0 EPT_0 EPT_x: Endpoint x Reset 0: No effect. 1: Reset the Endpointx state. Setting this bit clears all bits in the Endpoint status UDPHS_EPTSTAx register except the TOGGLESQ_STA field.  2017 Microchip Technology Inc. DS60001525A-page 879 SAMA5D4 SERIES 35.7.7 UDPHS Test Register Name: UDPHS_TST Address:0xFC02C0E0 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 OPMODE2 4 TST_PKT 3 TST_K 2 TST_J 1 0 SPEED_CFG SPEED_CFG: Speed Configuration Value Name Description 0 NORMAL Normal mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode. 1 – Reserved 2 HIGH_SPEED Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. 3 FULL_SPEED Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake. TST_J: Test J Mode 0: No effect. 1: Set to send the J state on the UDPHS line. This enables the testing of the high output drive level on the D+ line. TST_K: Test K Mode 0: No effect. 1: Set to send the K state on the UDPHS line. This enables the testing of the high output drive level on the D- line. TST_PKT: Test Packet Mode 0: No effect. 1: Set to repetitively transmit the packet stored in the current bank. This enables the testing of rise and fall times, eye patterns, jitter, and any other dynamic waveform specifications. OPMODE2: OpMode2 0: No effect. 1: Set to force the OpMode signal (UTMI interface) to “10”, to disable the bit-stuffing and the NRZI encoding. Note: For the Test mode, Test_SE0_NAK (refer to Universal Serial Bus Specification, Revision 2.0: 7.1.20, Test Mode Support). Force the device in High Speed mode, and configure a bulk-type endpoint. Do not fill this endpoint for sending NAK to the host. Upon command, a port’s transceiver must enter the High Speed Receive mode and remain in that mode until the exit action is taken. This enables the testing of output impedance, low level output voltage and loading characteristics. In addition, while in this mode, upstream facing ports (and only upstream facing ports) must respond to any IN token packet with a NAK handshake (only if the packet CRC is determined to be correct) within the normal allowed device response time. This enables testing of the device squelch level circuitry and, additionally, provides a general purpose stimulus/response test for basic functional testing. DS60001525A-page 880  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.8 UDPHS Endpoint Configuration Register Name: UDPHS_EPTCFGx [x=0..15] Address:0xFC02C100 [0], 0xFC02C120 [1], 0xFC02C140 [2], 0xFC02C160 [3], 0xFC02C180 [4], 0xFC02C1A0 [5], 0xFC02C1C0 [6], 0xFC02C1E0 [7], 0xFC02C200 [8], 0xFC02C220 [9], 0xFC02C240 [10], 0xFC02C260 [11], 0xFC02C280 [12], 0xFC02C2A0 [13], 0xFC02C2C0 [14], 0xFC02C2E0 [15] Access: Read/Write 31 EPT_MAPD 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 6 5 4 3 EPT_DIR 2 1 EPT_SIZE 7 BK_NUMBER EPT_TYPE 8 NB_TRANS 0 EPT_SIZE: Endpoint Size (cleared upon USB reset) Set this field according to the endpoint size(1) in bytes (refer to Section 35.6.6 “Endpoint Configuration”). Value Name Description 0 8 8 bytes 1 16 16 bytes 2 32 32 bytes 3 64 64 bytes 4 128 128 bytes 5 256 256 bytes 6 512 512 bytes 7 1024 1024 bytes Note 1: 1024 bytes is only for isochronous endpoint. EPT_DIR: Endpoint Direction (cleared upon USB reset) 0: Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. 1: Set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. For Control endpoints this bit has no effect and should be left at zero. EPT_TYPE: Endpoint Type (cleared upon USB reset) Set this field according to the endpoint type (refer to Section 35.6.6 “Endpoint Configuration”). (Endpoint 0 should always be configured as control) Value Name Description 0 CTRL8 Control endpoint 1 ISO Isochronous endpoint 2 BULK Bulk endpoint 3 INT Interrupt endpoint  2017 Microchip Technology Inc. DS60001525A-page 881 SAMA5D4 SERIES BK_NUMBER: Number of Banks (cleared upon USB reset) Set this field according to the endpoint’s number of banks (refer to Section 35.6.6 “Endpoint Configuration”). Value Name Description 0 0 Zero bank, the endpoint is not mapped in memory 1 1 One bank (bank 0) 2 2 Double bank (Ping-Pong: bank0/bank1) 3 3 Triple bank (bank0/bank1/bank2) NB_TRANS: Number Of Transaction per Microframe (cleared upon USB reset) The Number of transactions per microframe is set by software. Note: Meaningful for high bandwidth isochronous endpoint only. EPT_MAPD: Endpoint Mapped (cleared upon USB reset) 0: The user should reprogram the register with correct values. 1: Set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding: – The FIFO max capacity (FIFO_MAX_SIZE in UDPHS_IPFEATURES register) – The number of endpoints/banks already allocated – The number of allowed banks for this endpoint DS60001525A-page 882  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.9 UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCTLENBx [x=0..15] Address:0xFC02C104 [0], 0xFC02C124 [1], 0xFC02C144 [2], 0xFC02C164 [3], 0xFC02C184 [4], 0xFC02C1A4 [5], 0xFC02C1C4 [6], 0xFC02C1E4 [7], 0xFC02C204 [8], 0xFC02C224 [9], 0xFC02C244 [10], 0xFC02C264 [11], 0xFC02C284 [12], 0xFC02C2A4 [13], 0xFC02C2C4 [14], 0xFC02C2E4 [15] Access: Write-only 31 SHRT_PCKT 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 BUSY_BANK 17 – 16 – 15 NAK_OUT 14 NAK_IN 13 STALL_SNT 12 RX_SETUP 11 TXRDY 10 TX_COMPLT 9 RXRDY_TXKL 8 ERR_OVFLW 7 – 6 – 5 – 4 NYET_DIS 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_ENABL This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register”. For additional information, refer to “UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints)”. EPT_ENABL: Endpoint Enable 0: No effect. 1: Enable endpoint according to the device configuration. AUTO_VALID: Packet Auto-Valid Enable 0: No effect. 1: Enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. INTDIS_DMA: Interrupts Disable DMA 0: No effect. 1: If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints) 0: No effect. 1: Forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. ERR_OVFLW: Overflow Error Interrupt Enable 0: No effect. 1: Enable Overflow Error Interrupt. RXRDY_TXKL: Received OUT Data Interrupt Enable 0: No effect. 1: Enable Received OUT Data Interrupt. TX_COMPLT: Transmitted IN Data Complete Interrupt Enable 0: No effect. 1: Enable Transmitted IN Data Complete Interrupt. TXRDY: TX Packet Ready Interrupt Enable 0: No effect. 1: Enable TX Packet Ready/Transaction Error Interrupt.  2017 Microchip Technology Inc. DS60001525A-page 883 SAMA5D4 SERIES RX_SETUP: Received SETUP 0: No effect. 1: Enable RX_SETUP Interrupt. STALL_SNT: Stall Sent Interrupt Enable 0: No effect. 1: Enable Stall Sent Interrupt. NAK_IN: NAKIN Interrupt Enable 0: No effect. 1: Enable NAKIN Interrupt. NAK_OUT: NAKOUT Interrupt Enable 0: No effect. 1: Enable NAKOUT Interrupt. BUSY_BANK: Busy Bank Interrupt Enable 0: No effect. 1: Enable Busy Bank Interrupt. SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable For OUT endpoints: 0: No effect. 1: Enable Short Packet Interrupt. For IN endpoints: Guarantees short packet at end of DMA Transfer if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTOVALID bits are also set. DS60001525A-page 884  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.10 UDPHS Endpoint Control Enable Register (Isochronous Endpoints) Name: UDPHS_EPTCTLENBx [x=0..15] (ISOENDPT) Address:0xFC02C104 [0], 0xFC02C124 [1], 0xFC02C144 [2], 0xFC02C164 [3], 0xFC02C184 [4], 0xFC02C1A4 [5], 0xFC02C1C4 [6], 0xFC02C1E4 [7], 0xFC02C204 [8], 0xFC02C224 [9], 0xFC02C244 [10], 0xFC02C264 [11], 0xFC02C284 [12], 0xFC02C2A4 [13], 0xFC02C2C4 [14], 0xFC02C2E4 [15] Access: Write-only 31 SHRT_PCKT 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 BUSY_BANK 17 – 16 – 11 TXRDY_TRER 10 TX_COMPLT 9 RXRDY_TXKL 8 ERR_OVFLW 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_ENABL 15 – 7 MDATA_RX 14 13 12 ERR_FLUSH ERR_CRC_NTR ERR_FL_ISO 6 DATAX_RX 5 – 4 – This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register”. For additional information, refer to “UDPHS Endpoint Control Register (Isochronous Endpoint)”. EPT_ENABL: Endpoint Enable 0: No effect. 1: Enable endpoint according to the device configuration. AUTO_VALID: Packet Auto-Valid Enable 0: No effect. 1: Enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. INTDIS_DMA: Interrupts Disable DMA 0: No effect. 1: If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. DATAX_RX: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 0: No effect. 1: Enable DATAx Interrupt. MDATA_RX: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 0: No effect. 1: Enable MDATA Interrupt. ERR_OVFLW: Overflow Error Interrupt Enable 0: No effect. 1: Enable Overflow Error Interrupt. RXRDY_TXKL: Received OUT Data Interrupt Enable 0: No effect. 1: Enable Received OUT Data Interrupt. TX_COMPLT: Transmitted IN Data Complete Interrupt Enable 0: No effect. 1: Enable Transmitted IN Data Complete Interrupt.  2017 Microchip Technology Inc. DS60001525A-page 885 SAMA5D4 SERIES TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Enable 0: No effect. 1: Enable TX Packet Ready/Transaction Error Interrupt. ERR_FL_ISO: Error Flow Interrupt Enable 0: No effect. 1: Enable Error Flow ISO Interrupt. ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Enable 0: No effect. 1: Enable Error CRC ISO/Error Number of Transaction Interrupt. ERR_FLUSH: Bank Flush Error Interrupt Enable 0: No effect. 1: Enable Bank Flush Error Interrupt. BUSY_BANK: Busy Bank Interrupt Enable 0: No effect. 1: Enable Busy Bank Interrupt. SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable For OUT endpoints: 0: No effect. 1: Enable Short Packet Interrupt. For IN endpoints: Guarantees short packet at end of DMA Transfer if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTOVALID bits are also set. DS60001525A-page 886  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.11 UDPHS Endpoint Control Disable Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCTLDISx [x=0..15] Address:0xFC02C108 [0], 0xFC02C128 [1], 0xFC02C148 [2], 0xFC02C168 [3], 0xFC02C188 [4], 0xFC02C1A8 [5], 0xFC02C1C8 [6], 0xFC02C1E8 [7], 0xFC02C208 [8], 0xFC02C228 [9], 0xFC02C248 [10], 0xFC02C268 [11], 0xFC02C288 [12], 0xFC02C2A8 [13], 0xFC02C2C8 [14], 0xFC02C2E8 [15] Access: Write-only 31 SHRT_PCKT 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 BUSY_BANK 17 – 16 – 15 NAK_OUT 14 NAK_IN 13 STALL_SNT 12 RX_SETUP 11 TXRDY 10 TX_COMPLT 9 RXRDY_TXKL 8 ERR_OVFLW 7 – 6 – 5 – 4 NYET_DIS 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_DISABL This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register”. For additional information, refer to “UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints)”. EPT_DISABL: Endpoint Disable 0: No effect. 1: Disable endpoint. AUTO_VALID: Packet Auto-Valid Disable 0: No effect. 1: Disable this bit to not automatically validate the current packet. INTDIS_DMA: Interrupts Disable DMA 0: No effect. 1: Disable the “Interrupts Disable DMA”. NYET_DIS: NYET Enable (Only for High Speed Bulk OUT endpoints) 0: No effect. 1: Let the hardware handle the handshake response for the High Speed Bulk OUT transfer. ERR_OVFLW: Overflow Error Interrupt Disable 0: No effect. 1: Disable Overflow Error Interrupt. RXRDY_TXKL: Received OUT Data Interrupt Disable 0: No effect. 1: Disable Received OUT Data Interrupt. TX_COMPLT: Transmitted IN Data Complete Interrupt Disable 0: No effect. 1: Disable Transmitted IN Data Complete Interrupt. TXRDY: TX Packet Ready Interrupt Disable 0: No effect. 1: Disable TX Packet Ready/Transaction Error Interrupt.  2017 Microchip Technology Inc. DS60001525A-page 887 SAMA5D4 SERIES RX_SETUP: Received SETUP Interrupt Disable 0: No effect. 1: Disable RX_SETUP Interrupt. STALL_SNT: Stall Sent Interrupt Disable 0: No effect. 1: Disable Stall Sent Interrupt. NAK_IN: NAKIN Interrupt Disable 0: No effect. 1: Disable NAKIN Interrupt. NAK_OUT: NAKOUT Interrupt Disable 0: No effect. 1: Disable NAKOUT Interrupt. BUSY_BANK: Busy Bank Interrupt Disable 0: No effect. 1: Disable Busy Bank Interrupt. SHRT_PCKT: Short Packet Interrupt Disable For OUT endpoints: 0: No effect. 1: Disable Short Packet Interrupt. For IN endpoints: Never automatically add a zero length packet at end of DMA transfer. DS60001525A-page 888  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.12 UDPHS Endpoint Control Disable Register (Isochronous Endpoint) Name: UDPHS_EPTCTLDISx [x=0..15] (ISOENDPT) Address:0xFC02C108 [0], 0xFC02C128 [1], 0xFC02C148 [2], 0xFC02C168 [3], 0xFC02C188 [4], 0xFC02C1A8 [5], 0xFC02C1C8 [6], 0xFC02C1E8 [7], 0xFC02C208 [8], 0xFC02C228 [9], 0xFC02C248 [10], 0xFC02C268 [11], 0xFC02C288 [12], 0xFC02C2A8 [13], 0xFC02C2C8 [14], 0xFC02C2E8 [15] Access: Write-only 31 SHRT_PCKT 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 BUSY_BANK 17 – 16 – 11 TXRDY_TRER 10 TX_COMPLT 9 RXRDY_TXKL 8 ERR_OVFLW 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_DISABL 15 – 7 MDATA_RX 14 13 12 ERR_FLUSH ERR_CRC_NTR ERR_FL_ISO 6 DATAX_RX 5 – 4 – This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register”. For additional information, refer to “UDPHS Endpoint Control Register (Isochronous Endpoint)”. EPT_DISABL: Endpoint Disable 0: No effect. 1: Disable endpoint. AUTO_VALID: Packet Auto-Valid Disable 0: No effect. 1: Disable this bit to not automatically validate the current packet. INTDIS_DMA: Interrupts Disable DMA 0: No effect. 1: Disable the “Interrupts Disable DMA”. DATAX_RX: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 0: No effect. 1: Disable DATAx Interrupt. MDATA_RX: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 0: No effect. 1: Disable MDATA Interrupt. ERR_OVFLW: Overflow Error Interrupt Disable 0: No effect. 1: Disable Overflow Error Interrupt. RXRDY_TXKL: Received OUT Data Interrupt Disable 0: No effect. 1: Disable Received OUT Data Interrupt. TX_COMPLT: Transmitted IN Data Complete Interrupt Disable 0: No effect. 1: Disable Transmitted IN Data Complete Interrupt.  2017 Microchip Technology Inc. DS60001525A-page 889 SAMA5D4 SERIES TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Disable 0: No effect. 1: Disable TX Packet Ready/Transaction Error Interrupt. ERR_FL_ISO: Error Flow Interrupt Disable 0: No effect. 1: Disable Error Flow ISO Interrupt. ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Disable 0: No effect. 1: Disable Error CRC ISO/Error Number of Transaction Interrupt. ERR_FLUSH: bank flush error Interrupt Disable 0: No effect. 1: Disable Bank Flush Error Interrupt. BUSY_BANK: Busy Bank Interrupt Disable 0: No effect. 1: Disable Busy Bank Interrupt. SHRT_PCKT: Short Packet Interrupt Disable For OUT endpoints: 0: No effect. 1: Disable Short Packet Interrupt. For IN endpoints: Never automatically add a zero length packet at end of DMA transfer. DS60001525A-page 890  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.13 UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCTLx [x=0..15] Address:0xFC02C10C [0], 0xFC02C12C [1], 0xFC02C14C [2], 0xFC02C16C [3], 0xFC02C18C [4], 0xFC02C1AC [5], 0xFC02C1CC [6], 0xFC02C1EC [7], 0xFC02C20C [8], 0xFC02C22C [9], 0xFC02C24C [10], 0xFC02C26C [11], 0xFC02C28C [12], 0xFC02C2AC [13], 0xFC02C2CC [14], 0xFC02C2EC [15] Access: Read-only 31 SHRT_PCKT 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 BUSY_BANK 17 – 16 – 15 NAK_OUT 14 NAK_IN 13 STALL_SNT 12 RX_SETUP 11 TXRDY 10 TX_COMPLT 9 RXRDY_TXKL 8 ERR_OVFLW 7 – 6 – 5 – 4 NYET_DIS 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_ENABL This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register”. EPT_ENABL: Endpoint Enable (cleared upon USB reset) 0: The endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration. 1: The endpoint is enabled according to the device configuration. AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints) (cleared upon USB reset) Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints. For IN Transfer: If this bit is set, the UDPHS_EPTSTAx register TXRDY bit is set automatically when the current bank is full and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. The user may still set the UDPHS_EPTSTAx register TXRDY bit if the current bank is not full, unless the user needs to send a Zero Length Packet by software. For OUT Transfer: If this bit is set, the UDPHS_EPTSTAx register RXRDY_TXKL bit is automatically reset for the current bank when the last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is reached. The user may still clear the UDPHS_EPTSTAx register RXRDY_TXKL bit, for example, after completing a DMA buffer by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the remaining data bank(s). INTDIS_DMA: Interrupt Disables DMA (cleared upon USB reset) If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the UDPHS_IEN register EPT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source or clear this bit if transfer completion is needed. If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is normally completed, but the new DMA packet transfer is not started (not requested). If the exception raised is not associated to a new system bank packet (NAK_IN, NAK_OUT, etc.), then the request cancellation may happen at any time and may immediately stop the current DMA transfer.  2017 Microchip Technology Inc. DS60001525A-page 891 SAMA5D4 SERIES This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA buffer by software after reception of a short packet. NYET_DIS: NYET Disable (Only for High Speed Bulk OUT Endpoints) (cleared upon USB reset) 0: Lets the hardware handle the handshake response for the High Speed Bulk OUT transfer. 1: Forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. Note: According to the Universal Serial Bus Specification, Rev 2.0 (8.5.1.1 NAK Responses to OUT/DATA During PING Protocol), a NAK response to an HS Bulk OUT transfer is expected to be an unusual occurrence. ERR_OVFLW: Overflow Error Interrupt Enabled (cleared upon USB reset) 0: Overflow Error Interrupt is masked. 1: Overflow Error Interrupt is enabled. RXRDY_TXKL: Received OUT Data Interrupt Enabled (cleared upon USB reset) 0: Received OUT Data Interrupt is masked. 1: Received OUT Data Interrupt is enabled. TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 0: Transmitted IN Data Complete Interrupt is masked. 1: Transmitted IN Data Complete Interrupt is enabled. TXRDY: TX Packet Ready Interrupt Enabled (cleared upon USB reset) 0: TX Packet Ready Interrupt is masked. 1: TX Packet Ready Interrupt is enabled. Caution: Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TXRDY flag remains low. If there are no more banks available for transmitting after the software has set UDPHS_EPTSTAx/TXRDY for the last transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit at UDPHS_EPTSTAx/TXRDY hardware clear. RX_SETUP: Received SETUP Interrupt Enabled (cleared upon USB reset) 0: Received SETUP is masked. 1: Received SETUP is enabled. STALL_SNT: Stall Sent Interrupt Enabled (cleared upon USB reset) 0: Stall Sent Interrupt is masked. 1: Stall Sent Interrupt is enabled. NAK_IN: NAKIN Interrupt Enabled (cleared upon USB reset) 0: NAKIN Interrupt is masked. 1: NAKIN Interrupt is enabled. NAK_OUT: NAKOUT Interrupt Enabled (cleared upon USB reset) 0: NAKOUT Interrupt is masked. 1: NAKOUT Interrupt is enabled. BUSY_BANK: Busy Bank Interrupt Enabled (cleared upon USB reset) 0: BUSY_BANK Interrupt is masked. 1: BUSY_BANK Interrupt is enabled. For OUT endpoints: an interrupt is sent when all banks are busy. For IN endpoints: an interrupt is sent when all banks are free. DS60001525A-page 892  2017 Microchip Technology Inc. SAMA5D4 SERIES SHRT_PCKT: Short Packet Interrupt Enabled (cleared upon USB reset) For OUT endpoints: send an Interrupt when a Short Packet has been received. 0: Short Packet Interrupt is masked. 1: Short Packet Interrupt is enabled. For IN endpoints: a Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling a BULK or INTERRUPT end of transfer, but only if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTO_VALID bits are also set.  2017 Microchip Technology Inc. DS60001525A-page 893 SAMA5D4 SERIES 35.7.14 UDPHS Endpoint Control Register (Isochronous Endpoint) Name: UDPHS_EPTCTLx [x=0..15] (ISOENDPT) Address:0xFC02C10C [0], 0xFC02C12C [1], 0xFC02C14C [2], 0xFC02C16C [3], 0xFC02C18C [4], 0xFC02C1AC [5], 0xFC02C1CC [6], 0xFC02C1EC [7], 0xFC02C20C [8], 0xFC02C22C [9], 0xFC02C24C [10], 0xFC02C26C [11], 0xFC02C28C [12], 0xFC02C2AC [13], 0xFC02C2CC [14], 0xFC02C2EC [15] Access: Read-only 31 SHRT_PCKT 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 BUSY_BANK 17 – 16 – 11 TXRDY_TRER 10 TX_COMPLT 9 RXRDY_TXKL 8 ERR_OVFLW 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_ENABL 15 – 7 MDATA_RX 14 13 12 ERR_FLUSH ERR_CRC_NTR ERR_FL_ISO 6 DATAX_RX 5 – 4 – This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register”. EPT_ENABL: Endpoint Enable (cleared upon USB reset) 0: The endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration. 1: The endpoint is enabled according to the device configuration. AUTO_VALID: Packet Auto-Valid Enabled (cleared upon USB reset) Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints. For IN Transfer: If this bit is set, the UDPHS_EPTSTAx register TXRDY_TRER bit is set automatically when the current bank is full and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. The user may still set the UDPHS_EPTSTAx register TXRDY_TRER bit if the current bank is not full, unless the user needs to send a Zero Length Packet by software. For OUT Transfer: If this bit is set, the UDPHS_EPTSTAx register RXRDY_TXKL bit is automatically reset for the current bank when the last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is reached. The user may still clear the UDPHS_EPTSTAx register RXRDY_TXKL bit, for example, after completing a DMA buffer by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the remaining data bank(s). INTDIS_DMA: Interrupt Disables DMA (cleared upon USB reset) If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the UDPHS_IEN register EPT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source or clear this bit if transfer completion is needed. If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is normally completed, but the new DMA packet transfer is not started (not requested). If the exception raised is not associated to a new system bank packet (ex: ERR_FL_ISO), then the request cancellation may happen at any time and may immediately stop the current DMA transfer. DS60001525A-page 894  2017 Microchip Technology Inc. SAMA5D4 SERIES This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO interrupt for adaptive rate. DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 0: No effect. 1: Send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received. MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) (cleared upon USB reset) 0: No effect. 1: Send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data payload has been received. ERR_OVFLW: Overflow Error Interrupt Enabled (cleared upon USB reset) 0: Overflow Error Interrupt is masked. 1: Overflow Error Interrupt is enabled. RXRDY_TXKL: Received OUT Data Interrupt Enabled (cleared upon USB reset) 0: Received OUT Data Interrupt is masked. 1: Received OUT Data Interrupt is enabled. TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled (cleared upon USB reset) 0: Transmitted IN Data Complete Interrupt is masked. 1: Transmitted IN Data Complete Interrupt is enabled. TXRDY_TRER: TX Packet Ready/Transaction Error Interrupt Enabled (cleared upon USB reset) 0: TX Packet Ready/Transaction Error Interrupt is masked. 1: TX Packet Ready/Transaction Error Interrupt is enabled. Caution: Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TXRDY_TRER flag remains low. If there are no more banks available for transmitting after the software has set UDPHS_EPTSTAx/ TXRDY_TRER for the last transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit at UDPHS_EPTSTAx/TXRDY_TRER hardware clear. ERR_FL_ISO: Error Flow Interrupt Enabled (cleared upon USB reset) 0: Error Flow Interrupt is masked. 1: Error Flow Interrupt is enabled. ERR_CRC_NTR: ISO CRC Error/Number of Transaction Error Interrupt Enabled (cleared upon USB reset) 0: ISO CRC error/number of Transaction Error Interrupt is masked. 1: ISO CRC error/number of Transaction Error Interrupt is enabled. ERR_FLUSH: Bank Flush Error Interrupt Enabled (cleared upon USB reset) 0: Bank Flush Error Interrupt is masked. 1: Bank Flush Error Interrupt is enabled. BUSY_BANK: Busy Bank Interrupt Enabled (cleared upon USB reset) 0: BUSY_BANK Interrupt is masked. 1: BUSY_BANK Interrupt is enabled. For OUT endpoints: An interrupt is sent when all banks are busy. For IN endpoints: An interrupt is sent when all banks are free.  2017 Microchip Technology Inc. DS60001525A-page 895 SAMA5D4 SERIES SHRT_PCKT: Short Packet Interrupt Enabled (cleared upon USB reset) For OUT endpoints: send an Interrupt when a Short Packet has been received. 0: Short Packet Interrupt is masked. 1: Short Packet Interrupt is enabled. For IN endpoints: A Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling an end of isochronous (micro)frame data, but only if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTO_VALID bits are also set. DS60001525A-page 896  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.15 UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTSETSTAx [x=0..15] Address:0xFC02C114 [0], 0xFC02C134 [1], 0xFC02C154 [2], 0xFC02C174 [3], 0xFC02C194 [4], 0xFC02C1B4 [5], 0xFC02C1D4 [6], 0xFC02C1F4 [7], 0xFC02C214 [8], 0xFC02C234 [9], 0xFC02C254 [10], 0xFC02C274 [11], 0xFC02C294 [12], 0xFC02C2B4 [13], 0xFC02C2D4 [14], 0xFC02C2F4 [15] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 TXRDY 10 – 9 RXRDY_TXKL 8 – 7 – 6 – 5 FRCESTALL 4 – 3 – 2 – 1 – 0 – This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register”. For additional information, refer to “UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)”. FRCESTALL: Stall Handshake Request Set 0: No effect. 1: Set this bit to request a STALL answer to the host for the next handshake Refer to chapters 8.4.5 (Handshake Packets) and 9.4.5 (Get Status) of the Universal Serial Bus Specification, Rev 2.0 for more information on the STALL handshake. RXRDY_TXKL: KILL Bank Set (for IN Endpoint) 0: No effect. 1: Kill the last written bank. TXRDY: TX Packet Ready Set 0: No effect. 1: Set this bit after a packet has been written into the endpoint FIFO for IN data transfers – This flag is used to generate a Data IN transaction (device to host). – Device firmware checks that it can write a data payload in the FIFO, checking that TXRDY is cleared. – Transfer to the FIFO is done by writing in the “Buffer Address” register. – Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device setting TXRDY to one. – UDPHS bus transactions can start. – TXCOMP is set once the data payload has been received by the host. – Data should be written into the endpoint FIFO only after this bit has been cleared. – Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet.  2017 Microchip Technology Inc. DS60001525A-page 897 SAMA5D4 SERIES 35.7.16 UDPHS Endpoint Set Status Register (Isochronous Endpoint) Name: UDPHS_EPTSETSTAx [x=0..15] (ISOENDPT) Address:0xFC02C114 [0], 0xFC02C134 [1], 0xFC02C154 [2], 0xFC02C174 [3], 0xFC02C194 [4], 0xFC02C1B4 [5], 0xFC02C1D4 [6], 0xFC02C1F4 [7], 0xFC02C214 [8], 0xFC02C234 [9], 0xFC02C254 [10], 0xFC02C274 [11], 0xFC02C294 [12], 0xFC02C2B4 [13], 0xFC02C2D4 [14], 0xFC02C2F4 [15] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 TXRDY_TRER 10 – 9 RXRDY_TXKL 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register”. For additional information, refer to “UDPHS Endpoint Status Register (Isochronous Endpoint)”. RXRDY_TXKL: KILL Bank Set (for IN Endpoint) 0: No effect. 1: Kill the last written bank. TXRDY_TRER: TX Packet Ready Set 0: No effect. 1: Set this bit after a packet has been written into the endpoint FIFO for IN data transfers – This flag is used to generate a Data IN transaction (device to host). – Device firmware checks that it can write a data payload in the FIFO, checking that TXRDY_TRER is cleared. – Transfer to the FIFO is done by writing in the “Buffer Address” register. – Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device setting TXRDY_TRER to one. – UDPHS bus transactions can start. – TXCOMP is set once the data payload has been sent. – Data should be written into the endpoint FIFO only after this bit has been cleared. – Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet. DS60001525A-page 898  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.17 UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTCLRSTAx [x=0..15] Address:0xFC02C118 [0], 0xFC02C138 [1], 0xFC02C158 [2], 0xFC02C178 [3], 0xFC02C198 [4], 0xFC02C1B8 [5], 0xFC02C1D8 [6], 0xFC02C1F8 [7], 0xFC02C218 [8], 0xFC02C238 [9], 0xFC02C258 [10], 0xFC02C278 [11], 0xFC02C298 [12], 0xFC02C2B8 [13], 0xFC02C2D8 [14], 0xFC02C2F8 [15] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 NAK_OUT 14 NAK_IN 13 STALL_SNT 12 RX_SETUP 11 – 10 TX_COMPLT 9 RXRDY_TXKL 8 – 7 – 6 TOGGLESQ 5 FRCESTALL 4 – 3 – 2 – 1 – 0 – This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register”. For additional information, refer to “UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)”. FRCESTALL: Stall Handshake Request Clear 0: No effect. 1: Clear the STALL request. The next packets from host will not be STALLed. TOGGLESQ: Data Toggle Clear 0: No effect. 1: Clear the PID data of the current bank For OUT endpoints, the next received packet should be a DATA0. For IN endpoints, the next packet will be sent with a DATA0 PID. RXRDY_TXKL: Received OUT Data Clear 0: No effect. 1: Clear the RXRDY_TXKL flag of UDPHS_EPTSTAx. TX_COMPLT: Transmitted IN Data Complete Clear 0: No effect. 1: Clear the TX_COMPLT flag of UDPHS_EPTSTAx. RX_SETUP: Received SETUP Clear 0: No effect. 1: Clear the RX_SETUP flags of UDPHS_EPTSTAx. STALL_SNT: Stall Sent Clear 0: No effect. 1: Clear the STALL_SNT flags of UDPHS_EPTSTAx. NAK_IN: NAKIN Clear 0: No effect. 1: Clear the NAK_IN flags of UDPHS_EPTSTAx.  2017 Microchip Technology Inc. DS60001525A-page 899 SAMA5D4 SERIES NAK_OUT: NAKOUT Clear 0: No effect. 1: Clear the NAK_OUT flag of UDPHS_EPTSTAx. DS60001525A-page 900  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.18 UDPHS Endpoint Clear Status Register (Isochronous Endpoint) Name: UDPHS_EPTCLRSTAx [x=0..15] (ISOENDPT) Address:0xFC02C118 [0], 0xFC02C138 [1], 0xFC02C158 [2], 0xFC02C178 [3], 0xFC02C198 [4], 0xFC02C1B8 [5], 0xFC02C1D8 [6], 0xFC02C1F8 [7], 0xFC02C218 [8], 0xFC02C238 [9], 0xFC02C258 [10], 0xFC02C278 [11], 0xFC02C298 [12], 0xFC02C2B8 [13], 0xFC02C2D8 [14], 0xFC02C2F8 [15] Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 13 12 ERR_FLUSH ERR_CRC_NTR ERR_FL_ISO 11 – 10 TX_COMPLT 9 RXRDY_TXKL 8 – 7 – 6 TOGGLESQ 3 – 2 – 1 – 0 – 5 – 4 – This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register”. For additional information, refer to “UDPHS Endpoint Status Register (Isochronous Endpoint)”. TOGGLESQ: Data Toggle Clear 0: No effect. 1: Clear the PID data of the current bank For OUT endpoints, the next received packet should be a DATA0. For IN endpoints, the next packet will be sent with a DATA0 PID. RXRDY_TXKL: Received OUT Data Clear 0: No effect. 1: Clear the RXRDY_TXKL flag of UDPHS_EPTSTAx. TX_COMPLT: Transmitted IN Data Complete Clear 0: No effect. 1: Clear the TX_COMPLT flag of UDPHS_EPTSTAx. ERR_FL_ISO: Error Flow Clear 0: No effect. 1: Clear the ERR_FL_ISO flags of UDPHS_EPTSTAx. ERR_CRC_NTR: Number of Transaction Error Clear 0: No effect. 1: Clear the ERR_CRC_NTR flags of UDPHS_EPTSTAx. ERR_FLUSH: Bank Flush Error Clear 0: No effect. 1: Clear the ERR_FLUSH flags of UDPHS_EPTSTAx.  2017 Microchip Technology Inc. DS60001525A-page 901 SAMA5D4 SERIES 35.7.19 UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints) Name: UDPHS_EPTSTAx [x=0..15] Address:0xFC02C11C [0], 0xFC02C13C [1], 0xFC02C15C [2], 0xFC02C17C [3], 0xFC02C19C [4], 0xFC02C1BC [5], 0xFC02C1DC [6], 0xFC02C1FC [7], 0xFC02C21C [8], 0xFC02C23C [9], 0xFC02C25C [10], 0xFC02C27C [11], 0xFC02C29C [12], 0xFC02C2BC [13], 0xFC02C2DC [14], 0xFC02C2FC [15] Access: Read-only 31 SHRT_PCKT 30 23 15 NAK_OUT 29 28 22 21 BYTE_COUNT 20 14 NAK_IN 7 6 TOGGLESQ_STA 27 BYTE_COUNT 26 19 18 BUSY_BANK_STA 25 24 17 16 CURBK_CTLDIR 13 STALL_SNT 12 RX_SETUP 11 TXRDY 10 TX_COMPLT 9 RXRDY_TXKL 8 ERR_OVFLW 5 FRCESTALL 4 – 3 – 2 – 1 – 0 – This register view is relevant only if EPT_TYPE = 0x0, 0x2 or 0x3 in “UDPHS Endpoint Configuration Register”. FRCESTALL: Stall Handshake Request (cleared upon USB reset) 0: No effect. 1: If set a STALL answer will be done to the host for the next handshake. This bit is reset by hardware upon received SETUP. TOGGLESQ_STA: Toggle Sequencing (cleared upon USB reset) Toggle Sequencing: – IN endpoint: It indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the current bank. – CONTROL and OUT endpoint: These bits are set by hardware to indicate the PID data of the current bank: Value Name Description 0 DATA0 DATA0 1 DATA1 DATA1 2 DATA2 Reserved for High Bandwidth Isochronous Endpoint 3 MDATA Reserved for High Bandwidth Isochronous Endpoint Note 1: In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1). 2: These bits are updated for OUT transfer: - A new data has been written into the current bank. - The user has just cleared the Received OUT Data bit to switch to the next bank. 3: This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx (disable endpoint). DS60001525A-page 902  2017 Microchip Technology Inc. SAMA5D4 SERIES ERR_OVFLW: Overflow Error (cleared upon USB reset) This bit is set by hardware when a new too-long packet is received. Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow Error bit is set. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). RXRDY_TXKL: Received OUT Data/KILL Bank (cleared upon USB reset) – Received OUT Data (for OUT endpoint or Control endpoint): This bit is set by hardware after a new packet has been stored in the endpoint FIFO. This bit is cleared by the device firmware after reading the OUT data from the endpoint. For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile. Hardware assertion of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register RXRDY_TXKL bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). – KILL Bank (for IN endpoint): – The bank is really cleared or the bank is sent, BUSY_BANK_STA is decremented. – The bank is not cleared but sent on the IN transfer, TX_COMPLT – The bank is not cleared because it was empty. The user should wait that this bit is cleared before trying to clear another packet. Note: “Kill a packet” may be refused if at the same time, an IN token is coming and the current packet is sent on the UDPHS line. In this case, the TX_COMPLT bit is set. Take notice however, that if at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. In fact, in that case, the current bank is sent (IN transfer) and the last bank is killed. TX_COMPLT: Transmitted IN Data Complete (cleared upon USB reset) This bit is set by hardware after an IN packet has been accepted (ACK’ed) by the host. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). TXRDY: TX Packet Ready (cleared upon USB reset) This bit is cleared by hardware after the host has acknowledged the packet. For Multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit. Hardware clear of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register TXRDY bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). RX_SETUP: Received SETUP (cleared upon USB reset) – (for Control endpoint only) This bit is set by hardware when a valid SETUP packet has been received from the host. It is cleared by the device firmware after reading the SETUP data from the endpoint FIFO. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). STALL_SNT: Stall Sent (cleared upon USB reset) – (for Control, Bulk and Interrupt endpoints) This bit is set by hardware after a STALL handshake has been sent as requested by the UDPHS_EPTSTAx register FRCESTALL bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). NAK_IN: NAK IN (cleared upon USB reset) This bit is set by hardware when a NAK handshake has been sent in response to an IN request from the Host. This bit is cleared by software.  2017 Microchip Technology Inc. DS60001525A-page 903 SAMA5D4 SERIES NAK_OUT: NAK OUT (cleared upon USB reset) This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint). CURBK_CTLDIR: Current Bank/Control Direction (cleared upon USB reset) – Current Bank (not relevant for Control endpoint): These bits are set by hardware to indicate the number of the current bank. Value Name Description 0 BANK0 Bank 0 (or single bank) 1 BANK1 Bank 1 2 BANK2 Bank 2 Note: The current bank is updated each time the user: - Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank. - Clears the received OUT data bit to access the next bank. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). – Control Direction (for Control endpoint only): 0: A Control Write is requested by the Host. 1: A Control Read is requested by the Host. Note 1: This bit corresponds with the 7th bit of the bmRequestType (Byte 0 of the Setup Data). 2: This bit is updated after receiving new setup data. BUSY_BANK_STA: Busy Bank Number (cleared upon USB reset) These bits are set by hardware to indicate the number of busy banks. IN endpoint: It indicates the number of busy banks filled by the user, ready for IN transfer. OUT endpoint: It indicates the number of busy banks filled by OUT transaction from the Host. Value Name Description 0 0BUSYBANK All banks are free 1 1BUSYBANK 1 busy bank 2 2BUSYBANKS 2 busy banks 3 3BUSYBANKS 3 busy banks BYTE_COUNT: UDPHS Byte Count (cleared upon USB reset) Byte count of a received data packet. This field is incremented after each write into the endpoint (to prepare an IN transfer). This field is decremented after each reading into the endpoint (OUT transfer). This field is also updated at RXRDY_TXKL flag clear with the next bank. This field is also updated at TXRDY flag set with the next bank. This field is reset by EPT_x of UDPHS_EPTRST register. SHRT_PCKT: Short Packet (cleared upon USB reset) An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). DS60001525A-page 904  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.20 UDPHS Endpoint Status Register (Isochronous Endpoint) Name: UDPHS_EPTSTAx [x=0..15] (ISOENDPT) Address:0xFC02C11C [0], 0xFC02C13C [1], 0xFC02C15C [2], 0xFC02C17C [3], 0xFC02C19C [4], 0xFC02C1BC [5], 0xFC02C1DC [6], 0xFC02C1FC [7], 0xFC02C21C [8], 0xFC02C23C [9], 0xFC02C25C [10], 0xFC02C27C [11], 0xFC02C29C [12], 0xFC02C2BC [13], 0xFC02C2DC [14], 0xFC02C2FC [15] Access: Read-only 31 SHRT_PCKT 30 23 15 – 29 28 22 21 BYTE_COUNT 20 14 13 12 ERR_FLUSH ERR_CRC_NTR ERR_FL_ISO 7 6 TOGGLESQ_STA 5 – 4 – 27 BYTE_COUNT 26 25 19 18 BUSY_BANK_STA 17 24 16 CURBK 11 TXRDY_TRER 10 TX_COMPLT 9 RXRDY_TXKL 8 ERR_OVFLW 3 – 2 – 1 – 0 – This register view is relevant only if EPT_TYPE = 0x1 in “UDPHS Endpoint Configuration Register”. TOGGLESQ_STA: Toggle Sequencing (cleared upon USB reset) Toggle Sequencing: – IN endpoint: It indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the current bank. – OUT endpoint: These bits are set by hardware to indicate the PID data of the current bank: Value Name Description 0 DATA0 DATA0 1 DATA1 DATA1 2 DATA2 Data2 (only for High Bandwidth Isochronous Endpoint) 3 MDATA MData (only for High Bandwidth Isochronous Endpoint) Note 1: In OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1). 2: These bits are updated for OUT transfer: - A new data has been written into the current bank. - The user has just cleared the Received OUT Data bit to switch to the next bank. 3: For High Bandwidth Isochronous Out endpoint, it is recommended to check the UDPHS_EPTSTAx/TXRDY_TRER bit to know if the toggle sequencing is correct or not. 4: This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx (disable endpoint). ERR_OVFLW: Overflow Error (cleared upon USB reset) This bit is set by hardware when a new too-long packet is received. Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow Error bit is set. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).  2017 Microchip Technology Inc. DS60001525A-page 905 SAMA5D4 SERIES RXRDY_TXKL: Received OUT Data/KILL Bank (cleared upon USB reset) – Received OUT Data (for OUT endpoint or Control endpoint): This bit is set by hardware after a new packet has been stored in the endpoint FIFO. This bit is cleared by the device firmware after reading the OUT data from the endpoint. For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile. Hardware assertion of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register RXRDY_TXKL bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). – KILL Bank (for IN endpoint): – The bank is really cleared or the bank is sent, BUSY_BANK_STA is decremented. – The bank is not cleared but sent on the IN transfer, TX_COMPLT – The bank is not cleared because it was empty. The user should wait that this bit is cleared before trying to clear another packet. Note: “Kill a packet” may be refused if at the same time, an IN token is coming and the current packet is sent on the UDPHS line. In this case, the TX_COMPLT bit is set. Take notice however, that if at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. In fact, in that case, the current bank is sent (IN transfer) and the last bank is killed. TX_COMPLT: Transmitted IN Data Complete (cleared upon USB reset) This bit is set by hardware after an IN packet has been sent. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). TXRDY_TRER: TX Packet Ready/Transaction Error (cleared upon USB reset) – TX Packet Ready: This bit is cleared by hardware, as soon as the packet has been sent. For Multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit. Hardware clear of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register TXRDY_TRER bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). – Transaction Error (for high bandwidth isochronous OUT endpoints) (Read-Only): This bit is set by hardware when a transaction error occurs inside one microframe. If one toggle sequencing problem occurs among the n-transactions (n = 1, 2 or 3) inside a microframe, then this bit is still set as long as the current bank contains one “bad” n-transaction (refer to “CURBK: Current Bank (cleared upon USB reset)”). As soon as the current bank is relative to a new “good” n-transactions, then this bit is reset. Note 1: A transaction error occurs when the toggle sequencing does not comply with the Universal Serial Bus Specification, Rev 2.0 (5.9.2 High Bandwidth Isochronous endpoints) (Bad PID, missing data, etc.) 2: When a transaction error occurs, the user may empty all the “bad” transactions by clearing the Received OUT Data flag (RXRDY_TXKL). If this bit is reset, then the user should consider that a new n-transaction is coming. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). ERR_FL_ISO: Error Flow (cleared upon USB reset) This bit is set by hardware when a transaction error occurs. – Isochronous IN transaction is missed, the micro has no time to fill the endpoint (underflow). – Isochronous OUT data is dropped because the bank is busy (overflow). This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). ERR_CRC_NTR: CRC ISO Error/Number of Transaction Error (cleared upon USB reset) – CRC ISO Error (for Isochronous OUT endpoints) (Read-only): This bit is set by hardware if the last received data is corrupted (CRC error on data). DS60001525A-page 906  2017 Microchip Technology Inc. SAMA5D4 SERIES This bit is updated by hardware when new data is received (Received OUT Data bit). – Number of Transaction Error (for High Bandwidth Isochronous IN endpoints): This bit is set at the end of a microframe in which at least one data bank has been transmitted, if less than the number of transactions per micro-frame banks (UDPHS_EPTCFGx register NB_TRANS) have been validated for transmission inside this microframe. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). ERR_FLUSH: Bank Flush Error (cleared upon USB reset) – (for High Bandwidth Isochronous IN endpoints) This bit is set when flushing unsent banks at the end of a microframe. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint). CURBK: Current Bank (cleared upon USB reset) – Current Bank: These bits are set by hardware to indicate the number of the current bank. Value Name Description 0 BANK0 Bank 0 (or single bank) 1 BANK1 Bank 1 2 BANK2 Bank 2 Note: The current bank is updated each time the user: - Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank. - Clears the received OUT data bit to access the next bank. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). BUSY_BANK_STA: Busy Bank Number (cleared upon USB reset) These bits are set by hardware to indicate the number of busy banks. – IN endpoint: It indicates the number of busy banks filled by the user, ready for IN transfer. – OUT endpoint: It indicates the number of busy banks filled by OUT transaction from the Host. Value Name Description 0 0BUSYBANK All banks are free 1 1BUSYBANK 1 busy bank 2 2BUSYBANKS 2 busy banks 3 3BUSYBANKS 3 busy banks BYTE_COUNT: UDPHS Byte Count (cleared upon USB reset) Byte count of a received data packet. This field is incremented after each write into the endpoint (to prepare an IN transfer). This field is decremented after each reading into the endpoint (OUT transfer). This field is also updated at RXRDY_TXKL flag clear with the next bank. This field is also updated at TXRDY_TRER flag set with the next bank. This field is reset by EPT_x of UDPHS_EPTRST register. SHRT_PCKT: Short Packet (cleared upon USB reset) An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).  2017 Microchip Technology Inc. DS60001525A-page 907 SAMA5D4 SERIES 35.7.21 UDPHS DMA Channel Transfer Descriptor The DMA channel transfer descriptor is loaded from the memory. Be careful with the alignment of this buffer. The structure of the DMA channel transfer descriptor is defined by three parameters as described below: Offset 0: The address must be aligned: 0xXXXX0 Next Descriptor Address Register: UDPHS_DMANXTDSCx Offset 4: The address must be aligned: 0xXXXX4 DMA Channelx Address Register: UDPHS_DMAADDRESSx Offset 8: The address must be aligned: 0xXXXX8 DMA Channelx Control Register: UDPHS_DMACONTROLx To use the DMA channel transfer descriptor, fill the structures with the correct value (as described in the following pages). Then write directly in UDPHS_DMANXTDSCx the address of the descriptor to be used first. Then write 1 in the LDNXT_DSC bit of UDPHS_DMACONTROLx (load next channel transfer descriptor). The descriptor is automatically loaded upon Endpointx request for packet transfer. DS60001525A-page 908  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.22 UDPHS DMA Next Descriptor Address Register Name: UDPHS_DMANXTDSCx [x = 0..6] Address:0xFC02C300 [0], 0xFC02C310 [1], 0xFC02C320 [2], 0xFC02C330 [3], 0xFC02C340 [4], 0xFC02C350 [5], 0xFC02C360 [6] Access: Read/Write 31 30 29 28 27 NXT_DSC_ADD 26 25 24 23 22 21 20 19 NXT_DSC_ADD 18 17 16 15 14 13 12 11 NXT_DSC_ADD 10 9 8 7 6 5 4 3 NXT_DSC_ADD 2 1 0 Note: Channel 0 is not used. NXT_DSC_ADD: Next Descriptor Address This field points to the next channel descriptor to be processed. This channel descriptor must be aligned, so bits 0 to 3 of the address must be equal to zero.  2017 Microchip Technology Inc. DS60001525A-page 909 SAMA5D4 SERIES 35.7.23 UDPHS DMA Channel Address Register Name: UDPHS_DMAADDRESSx [x = 0..6] Address:0xFC02C304 [0], 0xFC02C314 [1], 0xFC02C324 [2], 0xFC02C334 [3], 0xFC02C344 [4], 0xFC02C354 [5], 0xFC02C364 [6] Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BUFF_ADD 23 22 21 20 BUFF_ADD 15 14 13 12 BUFF_ADD 7 6 5 4 BUFF_ADD Note: Channel 0 is not used. BUFF_ADD: Buffer Address This field determines the AHB bus starting address of a DMA channel transfer. Channel start and end addresses may be aligned on any byte boundary. The firmware may write this field only when the UDPHS_DMASTATUS register CHANN_ENB bit is clear. This field is updated at the end of the address phase of the current access to the AHB bus. It is incrementing of the access byte width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not aligned on a word boundary. The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer. The packet end address is either the channel end address or the latest channel address accessed in the channel buffer. The channel start address is written by software or loaded from the descriptor, whereas the channel end address is either determined by the end of buffer or the UDPHS device, USB end of transfer if the UDPHS_DMACONTROLx register END_TR_EN bit is set. DS60001525A-page 910  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.24 UDPHS DMA Channel Control Register Name: UDPHS_DMACONTROLx [x = 0..6] Address:0xFC02C308 [0], 0xFC02C318 [1], 0xFC02C328 [2], 0xFC02C338 [3], 0xFC02C348 [4], 0xFC02C358 [5], 0xFC02C368 [6] Access: Read/Write 31 30 29 28 27 BUFF_LENGTH 26 25 24 23 22 21 20 19 BUFF_LENGTH 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 BURST_LCK 6 DESC_LD_IT 5 END_BUFFIT 4 END_TR_IT 3 END_B_EN 2 END_TR_EN 1 LDNXT_DSC 0 CHANN_ENB Note: Channel 0 is not used. CHANN_ENB: (Channel Enable Command) 0: DMA channel is disabled at and no transfer will occur upon request. This bit is also cleared by hardware when the channel source bus is disabled at end of buffer. If the UDPHS_DMACONTROL register LDNXT_DSC bit has been cleared by descriptor loading, the firmware will have to set the corresponding CHANN_ENB bit to start the described transfer, if needed. If the UDPHS_DMACONTROL register LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read and/ or written reliably as soon as both UDPHS_DMASTATUS register CHANN_ENB and CHANN_ACT flags read as 0. If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then the UDPHS_DMASTATUS register CHANN_ENB bit is cleared. If the LDNXT_DSC bit is set at or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer occurs) and the next descriptor is immediately loaded. 1: UDPHS_DMASTATUS register CHANN_ENB bit will be set, thus enabling DMA channel data transfer. Then any pending request will start the transfer. This may be used to start or resume any requested transfer. LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command) 0: No channel register is loaded after the end of the channel transfer. 1: The channel controller loads the next descriptor after the end of the current transfer, i.e., when the UDPHS_DMASTATUS/CHANN_ENB bit is reset. If the UDPHS_DMA CONTROL/CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer request. DMA Channel Control Command Summary LDNXT_DSC CHANN_ENB 0 0 Stop now 0 1 Run and stop at end of buffer 1 0 Load next descriptor now 1 1 Run and link at end of buffer  2017 Microchip Technology Inc. Description DS60001525A-page 911 SAMA5D4 SERIES END_TR_EN: End of Transfer Enable (Control) Used for OUT transfers only. 0: USB end of transfer is ignored. 1: UDPHS device can put an end to the current buffer transfer. When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) will close the current buffer and the UDPHS_DMASTATUSx register END_TR_ST flag will be raised. This is intended for UDPHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe data buffer closure. END_B_EN: End of Buffer Enable (Control) 0: DMA Buffer End has no impact on USB packet transfer. 1: Endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e., when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0. This is mainly for short packet IN validation initiated by the DMA reaching end of buffer, but could be used for OUT packet truncation (discarding of unwanted packet data) at the end of DMA buffer. END_TR_IT: End of Transfer Interrupt Enable 0: UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising. 1: An interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer. Use when the receive size is unknown. END_BUFFIT: End of Buffer Interrupt Enable 0: UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt. 1: An interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero. DESC_LD_IT: Descriptor Loaded Interrupt Enable 0: UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt. 1: An interrupt is generated when a descriptor has been loaded from the bus. BURST_LCK: Burst Lock Enable 0: The DMA never locks bus access. 1: USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration. BUFF_LENGTH: Buffer Byte Length (Write-only) This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size (64 KBytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0, but the transfer end may occur earlier under UDPHS device control. When this field is written, The UDPHS_DMASTATUSx register BUFF_COUNT field is updated with the write value. Note 1: Bits [31:2] are only writable when issuing a channel Control Command other than “Stop Now”. 2: For reliability it is highly recommended to wait for both UDPHS_DMASTATUSx register CHAN_ACT and CHAN_ENB flags are at 0, thus ensuring the channel has been stopped before issuing a command other than “Stop Now”. DS60001525A-page 912  2017 Microchip Technology Inc. SAMA5D4 SERIES 35.7.25 UDPHS DMA Channel Status Register Name: UDPHS_DMASTATUSx [x = 0..6] Address:0xFC02C30C [0], 0xFC02C31C [1], 0xFC02C32C [2], 0xFC02C33C [3], 0xFC02C34C [4], 0xFC02C35C [5], 0xFC02C36C [6] Access: Read/Write 31 30 29 28 27 BUFF_COUNT 26 25 24 23 22 21 20 19 BUFF_COUNT 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 DESC_LDST 5 END_BF_ST 4 END_TR_ST 3 – 2 – 1 CHANN_ACT 0 CHANN_ENB Note: Channel 0 is not used. CHANN_ENB: Channel Enable Status 0: The DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set. When any transfer is ended either due to an elapsed byte count or a UDPHS device initiated transfer end, this bit is automatically reset. 1: The DMA channel is currently enabled and transfers data upon request. This bit is normally set or cleared by writing into the UDPHS_DMACONTROLx register CHANN_ENB bit either by software or descriptor loading. If a channel request is currently serviced when the UDPHS_DMACONTROLx register CHANN_ENB bit is cleared, the DMA FIFO buffer is drained until it is empty, then this status bit is cleared. CHANN_ACT: Channel Active Status 0: The DMA channel is no longer trying to source the packet data. When a packet transfer is ended this bit is automatically reset. 1: The DMA channel is currently trying to source packet data, i.e., selected as the highest-priority requesting channel. When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor load (if any) and potentially until UDPHS packet transfer completion, if allowed by the new descriptor. END_TR_ST: End of Channel Transfer Status 0: Cleared automatically when read by software. 1: Set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. END_BF_ST: End of Channel Buffer Status 0: Cleared automatically when read by software. 1: Set by hardware when the BUFF_COUNT countdown reaches zero. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. DESC_LDST: Descriptor Loaded Status 0: Cleared automatically when read by software. 1: Set by hardware when a descriptor has been loaded from the system bus. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer.  2017 Microchip Technology Inc. DS60001525A-page 913 SAMA5D4 SERIES BUFF_COUNT: Buffer Byte Count This field determines the current number of bytes still to be transferred for this buffer. This field is decremented from the AHB source bus access byte width at the end of this bus address phase. The access byte width is 4 by default, or less, at DMA start or end, if the start or end address is not aligned on a word boundary. At the end of buffer, the DMA accesses the UDPHS device only for the number of bytes needed to complete it. This field value is reliable (stable) only if the channel has been stopped or frozen (UDPHS_EPTCTLx register NT_DIS_DMA bit is used to disable the channel request) and the channel is no longer active CHANN_ACT flag is 0. Note: For OUT endpoints, if the receive buffer byte length (BUFF_LENGTH) has been defaulted to zero because the USB transfer length is unknown, the actual buffer byte length received will be 0x10000-BUFF_COUNT. DS60001525A-page 914  2017 Microchip Technology Inc. SAMA5D4 SERIES 36. USB Host High Speed Port (UHPHS) 36.1 Description The USB Host High Speed Port (UHPHS) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as Enhanced HCI protocol (Enhanced Host Controller Interface). 36.2 Embedded Characteristics • Compliant with Enhanced HCI Rev 1.0 Specification - Compliant with USB V2.0 High-speed - Supports High-speed 480 Mbps • Compliant with Open HCI Rev 1.0 Specification - Compliant with USB V2.0 Full-speed and Low-speed Specification - Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices • Root Hub Integrated with 3 Downstream USB HS Ports • Embedded USB Transceivers • Supports Power Management • 3 Hosts (A, B, and C) High Speed (EHCI), Port A shared with UDPHS 36.3 Block Diagram Figure 36-1: Block Diagram HCI Slave Block AHB Slave OHCI Registers Root Hub Registers List Processor Block Control ED & TD Registers Embedded USB v2.0 Transceiver Root Hub and Host SIE Master AHB HCI Master Block Data HCI Slave Block Slave EHCI Registers USB High-speed Transceiver HFSDPC HFSDMC HHSDPC HHSDMC PORT S/M 1 USB High-speed Transceiver HFSDPB HFSDMB HHSDPB HHSDMB PORT S/M 0 USB High-speed Transceiver HFSDPA HFSDMA HHSDPA HHSDMA FIFO 64 x 8 SOF generator AHB PORT S/M 2 Packet Buffer FIFO Control List Processor Master AHB HCI Master Block  2017 Microchip Technology Inc. Data DS60001525A-page 915 SAMA5D4 SERIES Access to the USB host operational registers is achieved through the AHB bus slave interface. The Open HCI host controller and Enhanced HCI host controller initialize master DMA transfers through the AHB bus master interface as follows: • • • • Fetches endpoint descriptors and transfer descriptors Access to endpoint data from system memory Access to the HC communication area Write status and retire transfer descriptor Memory access errors (abort, misalignment) lead to an “Unrecoverable Error” indicated by the corresponding flag in the host controller operational registers. The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of downstream ports can be determined by the software driver reading the root hub’s operational registers. Device connection is automatically detected by the USB host port logic. USB physical transceivers are integrated in the product and driven by the root hub’s ports. Over current protection on ports can be activated by the USB host controller. Microchip’s standard product does not dedicate pads to external over current protection. 36.4 Typical Connection Figure 36-2: Board Schematic to Interface UHP High-speed Host Controller PIO (VBUS ENABLE) +5V "A" Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND HHSDM/HFSDM 3 4 Shell = Shield 1 2 HHSDP/HFSDP 5K62 ± 1% Ω VBG 10 pF GNDUTMI Note 1: 10 pF capacitor on VBG is a provision and may not be populated. 36.5 36.5.1 Product Dependencies I/O Lines HFSDPs, HFSDMs, HHSDPs and HHSDMs are not controlled by any PIO controllers. The embedded USB High Speed physical transceivers are controlled by the USB host controller. One transceiver is shared with the USB High Speed Device (port A). The selection between Host Port A and USB Device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL register. In the case the port A is driven by the USB High Speed Device, the output signals are DFSDP, DFSDM, DHSDP and DHSDM. The transceiver is automatically selected for Device operation once the USB High Speed Device is enabled. In the case the port A is driven by the USB High Speed Host, the output signals are HFSDPA, HFSDMA, HHSDPA and HHSDMA. DS60001525A-page 916  2017 Microchip Technology Inc. SAMA5D4 SERIES 36.5.2 Power Management The system embeds 3 transceivers. The USB Host High Speed requires a 480 MHz clock for the embedded High-speed transceivers. This clock (UPLLCK) is provided by the UTMI PLL. In case power consumption is saved by stopping the UTMI PLL, high-speed operations are not possible. Nevertheless, OHCI Full-speed operations remain possible by selecting PLLACK as the input clock of OHCI. The High-speed transceiver returns a 30 MHz clock to the USB Host controller. The USB Host controller requires 48 MHz and 12 MHz clocks for OHCI full-speed operations. These clocks must be generated by a PLL with a correct accuracy of ± 0.25% using the USBDIV field. Thus the USB Host peripheral receives three clocks from the Power Management Controller (PMC): the Peripheral Clock (MCK domain), the UHP48M and the UHP12M (built-in UHP48M divided by four) used by the OHCI to interface with the bus USB signals (recovered 12 MHz domain) in Full-speed operations. For High-speed operations, the user has to perform the following: • • • • • • • Enable UHP peripheral clock in PMC_PCER. Write PLLCOUNT field in CKGR_UCKR. Enable UPLL with UPLLEN bit in CKGR_UCKR. Wait until UTMI_PLL is locked (LOCKU bit in PMC_SR). Enable BIAS with BIASEN bit in CKGR_UCKR. Select UPLLCK as Input clock of OHCI part (USBS bit in PMC_USB register). Program OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register. USBDIV must be 9 (division by 10) if UPLLCK is selected. • Enable OHCI clocks with UHP bit in PMC_SCER. For OHCI Full-speed operations only, the user has to perform the following: • Enable UHP peripheral clock in PMC_PCER. • Select PLLACK as Input clock of OHCI part (USBS bit in PMC_USB register). • Program OHCI clocks (UHP48M and UHP12M) with USBDIV field in PMC_USB register. USBDIV value is to be calculated according to the PLLACK value and USB Full-speed accuracy. • Enable the OHCI clocks with UHP bit in PMC_SCER.  2017 Microchip Technology Inc. DS60001525A-page 917 SAMA5D4 SERIES Figure 36-3: UHP Clock Trees UPLL (480 MHz) AHB EHCI Master Interface 30 MHz USB 2.0 EHCI Host Controller Port Router EHCI User Interface 30 MHz 30 MHz UTMI transceiver UTMI transceiver UTMI transceiver MCK OHCI Master Interface Root Hub and Host SIE UHP48M UHP12M OHCI User Interface USB 1.1 OHCI Host Controller OHCI clocks 36.5.3 Interrupt Sources The USB host interface has an interrupt line connected to the interrupt controller. Handling USB host interrupts requires programming the interrupt controller before configuring the UHPHS. 36.6 36.6.1 Functional Description UTMI Transceivers Sharing The High Speed USB Host Port A is shared with the High Speed USB Device port and connected to the second UTMI transceiver. The selection between Host Port A and USB device is controlled by the UDPHS enable bit (EN_UDPHS) located in the UDPHS_CTRL register. Figure 36-4: USB Selection Other Transceivers HS Transceiver EN_UDPHS 0 Other Ports HS USB Host HS EHCI FS OHCI DMA DS60001525A-page 918 1 PA HS USB Device DMA  2017 Microchip Technology Inc. SAMA5D4 SERIES 36.6.2 EHCI The USB Host Port controller is fully compliant with the Enhanced HCI specification. The USB Host Port User Interface (registers description) can be found in the Enhanced HCI Rev 1.0 Specification available on www.usb.org. The standard EHCI USB stack driver can be easily ported to Microchip’s architecture in the same way all existing class drivers run, without hardware specialization. 36.6.3 OHCI The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several Full-speed half-duplex serial communication ports at a baud rate of 12 Mbps. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.) and the USB hub can be connected to the USB host in the USB “tiered star” topology. The USB Host Port controller is fully compliant with the Open HCI specification. The USB Host Port User Interface (registers description) can be found in the Open HCI Rev 1.0 Specification available on www.usb.org. The standard OHCI USB stack driver can be easily ported to Microchip’s architecture, in the same way all existing class drivers run without hardware specialization. This means that all standard class devices are automatically detected and available to the user’s application. As an example, integrating an HID (Human Interface Device) class driver provides a plug & play feature for all USB keyboards and mouses.  2017 Microchip Technology Inc. DS60001525A-page 919 SAMA5D4 SERIES 36.7 USB Host High Speed Port (UHPHS) User Interface The Enhanced USB Host Controller contains two sets of software-accessible hardware registers: memory-mapped Host Controller Registers and optional PCI configuration registers. Note that the PCI configuration registers are only needed for PCI devices that implement the Host Controller. • Memory-mapped USB Host Controller Registers—This block of registers is memory-mapped into non-cacheable memory. This memory space must begin on a DWord (32-bit) boundary. This register space is divided into two sections: a set of read-only capability registers and a set of read/write operational registers. Table 36-1 describes each register space. Note: Host controllers are not required to support exclusive-access mechanisms (such as PCI LOCK) for accesses to the memorymapped register space. Therefore, if software attempts exclusive-access mechanisms to the host controller memory-mapped register space, the results are undefined. • PCI Configuration Registers (for PCI devices)—In addition to the normal PCI header, power management, and device-specific registers, two registers are needed in the PCI configuration space to support USB. The normal PCI header and device-specific registers are beyond the scope of this document (the UHPHS_CLASSC register is shown in this document). Note that HCD does not interact with the PCI configuration space. This space is used only by the PCI enumerator to identify the USB Host Controller, and assign the appropriate system resources. Table 36-1: Offset Enhanced Interface Register Sets Register Set 0 to N-1 Capability Registers N to N+M-1 Operational Registers Table 36-2: Offset Explanation The capability registers specify the limits, restrictions, and capabilities of a host controller implementation. These values are used as parameters to the host controller driver. The operational registers are used by system software to control and monitor the operational state of the host controller. Register Mapping Register Name Access Reset Host Controller Capability Registers 0x00 UHPHS Host Controller Capability Register UHPHS_HCCAPBASE Read-only 0x0100 0010 0x04 UHPHS Host Controller Structural Parameters Register UHPHS_HCSPARAMS Read-only 0x0000 1116 0x08 UHPHS Host Controller Capability Parameters Register UHPHS_HCCPARAMS Read-only 0x0000 A010 0x0C Reserved – – – 0x0008 0000 or Host Controller Operational Registers 0x10 UHPHS USB Command Register UHPHS_USBCMD Read/ Write(1) 0x14 UHPHS USB Status Register UHPHS_USBSTS Read/ Write(1) 0x0000 1000 0x18 UHPHS USB Interrupt Enable Register UHPHS_USBINTR Read/Write 0x0000 0000 0x1C UHPHS USB Frame Index Register UHPHS_FRINDEX Read/Write 0x0000 0000 0x20 UHPHS Control Data Structure Segment Register UHPHS_CTRLDSSEGMENT Read/Write 0x0000 0000 0x24 UHPHS Periodic Frame List Base Address Register UHPHS_PERIODICLISTBASE Read/Write 0x0000 0000 DS60001525A-page 920 0x0008 0B00(2)  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 36-2: Register Mapping (Continued) Offset Register Name Access Reset 0x28 UHPHS Asynchronous List Address Register UHPHS_ASYNCLISTADDR Read/Write 0x0000 0000 0x2C–0x4F Reserved – – – 0x50 UHPHS Configured Flag Register UHPHS_CONFIGFLAG Read/Write 0x0000 0000 0x54 UHPHS Port Status and Control Register 0 UHPHS_PORTSC_0 Read/ Write(1) 0x0000 2000 or 0x58 UHPHS Port Status and Control Register 1 UHPHS_PORTSC_1 Read/ Write(1) 0x0000 2000 or 0x5C UHPHS Port Status and Control Register 2 UHPHS_PORTSC_2 Read/ Write(1) 0x0000 2000 or 0x90 EHCI Synopsys-Specific Registers 00 UHPHS_INSNREG00 Read/ Write(1) 0x0000 0000 0x94 EHCI Synopsys-Specific Registers 01 UHPHS_INSNREG01 Read/ Write(1) 0x0020 0020 0x98 EHCI Synopsys-Specific Registers 02 UHPHS_INSNREG02 Read/ Write(1) (5) 0x9C EHCI Synopsys-Specific Registers 03 UHPHS_INSNREG03 Read/ Write(1) 0x0000 0001 0xA0 EHCI Synopsys-Specific Registers 04 UHPHS_INSNREG04 Read/ Write(1) 0x0000 0000 0xA4 EHCI Synopsys-Specific Registers 05 UHPHS_INSNREG05 Read/ Write(1) 0x0000 1000 0xA8 EHCI Synopsys-Specific Registers 06 UHPHS_INSNREG06 Read/ Write(1) 0x0000 0000 0xAC EHCI Synopsys-Specific Registers 07 UHPHS_INSNREG07 Read/ Write(1) 0x0000 0000 0xB0 EHCI Synopsys-Specific Registers 08 UHPHS_INSNREG08 Read/ Write(1) 0x0000 0000 0x0000 3000(3) 0x0000 3000(3) 0x0000 3000(3) Note 1: Field-dependent. 2: The default value depends on whether the Asynchronous Schedule Park Capability (ASPC) field in the UHPHS_HCCPARAMS register is enabled: Disabled (set to 0) = 0x0008 0000h; Enabled (set to 1) = 0x0008 0B00h. 3: The default value depends on the value of the Port Power Control (PPC) field in the UHPHS_HCSPARAMS register: 0x0000 2000h (with PPC set to 1); 0x0000 3000h (with PPC set to 0). 4: Software should not assume reserved bits are always 0 and should preserve these bits when writing to modifiable registers. 5: This value is determined by coreConsultant.  2017 Microchip Technology Inc. DS60001525A-page 921 SAMA5D4 SERIES 36.7.1 UHPHS Host Controller Capability Register Name:UHPHS_HCCAPBASE Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 HCIVERSION 23 22 21 20 HCIVERSION 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 CAPLENGTH CAPLENGTH: Capability Registers Length 10h: Default value. This field is used as an offset to add to register base to find the beginning of the Operational Register Space. HCIVERSION: Host Controller Interface Version Number 0100h: Default value. This is a two-byte field containing a BCD encoding of the EHCI revision number supported by this host controller. The most significant byte of this field represents a major revision and the least significant byte is the minor revision. DS60001525A-page 922  2017 Microchip Technology Inc. SAMA5D4 SERIES 36.7.2 UHPHS Host Controller Structural Parameters Register Name:UHPHS_HCSPARAMS Access:Read-only 31 – 30 – 23 22 29 – 28 – 27 – 26 – 25 – 24 – 21 20 19 – 18 – 17 – 16 P_INDICATOR 13 12 11 10 9 8 1 0 N_DP 15 14 N_CC 7 – 6 – N_PCC 5 – 4 PPC 3 2 N_PORTS This is a set of fields that are structural parameters: number of downstream ports, etc. N_PORTS: Number of Ports This field specifies the number of physical downstream ports implemented on this host controller. The value of this field determines how many port registers are addressable in the Operational Register Space. Valid values are in the range of 1H to FH. A zero in this field is undefined. PPC: Port Power Control This field indicates whether the host controller implementation includes port power control. A one in this bit indicates the ports have port power switches. A zero in this bit indicates the ports do not have port power switches. The value of this field affects the functionality of the Port Power field in each port status and control register (refer to Section 36.7.12 “UHPHS Port Status and Control Register”). N_PCC: Number of Ports per Companion Controller This field indicates the number of ports supported per companion host controller. It is used to indicate the port routing configuration to system software. For example, if N_PORTS has a value of 6 and N_CC has a value of 2, then N_PCC could have a value of 3. The convention is that the first N_PCC ports are assumed to be routed to companion controller 1, the next N_PCC ports to companion controller 2, etc. In the previous example, the N_PCC could have been 4, where the first four are routed to companion controller 1 and the last two are routed to companion controller 2. The number in this field must be consistent with N_PORTS and N_CC. N_CC: Number of Companion Controllers This field indicates the number of companion controllers associated with this USB 2.0 host controller. A zero in this field indicates there are no companion host controllers. Port-ownership hand-off is not supported. Only high-speed devices are supported on the host controller root ports. A value larger than zero in this field indicates there are companion USB 1.1 host controller(s). Port-ownership hand-offs are supported. High, Full- and Low-speed devices are supported on the host controller root ports. P_INDICATOR: Port Indicators This bit indicates whether the ports support port indicator control. When this bit is a 1, the port status and control registers include a read/ writeable field for controlling the state of the port indicator. Refer to Section 36.7.12 “UHPHS Port Status and Control Register” for definition of the port indicator control field. N_DP: Debug Port Number Optional. This register identifies which of the host controller ports is the debug port. The value is the port number (1-based) of the debug port. A non-zero value in this field indicates the presence of a debug port. The value in this register must not be greater than N_PORTS (refer to ”N_PORTS: Number of Ports”).  2017 Microchip Technology Inc. DS60001525A-page 923 SAMA5D4 SERIES 36.7.3 UHPHS Host Controller Capability Parameters Register Name:UHPHS_HCCPARAMS Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 ASPC 1 PFLF 0 AC EECP 7 6 5 IST 4 This is a set of fields that are capability parameters: Multiple Mode control (time-base bit functionality), addressing capability, etc. AC: 64-bit Addressing Capability This field documents the addressing range capability of this implementation. The value of this field determines whether software should use 32-bit or 64-bit data structures. Values for this field have the following interpretation: 0: Data structures using 32-bit address memory pointers 1: Data structures using 64-bit address memory pointers Note: This is not tightly coupled with the UHPHS_USBBASE address register mapping control. The 64-bit Addressing Capability bit indicates whether the host controller can generate 64-bit addresses as a master. The UHPHS_USBBASE register indicates the host controller only needs to decode 32-bit addresses as a slave. PFLF: Programmable Frame List Flag The default value is implementation-dependent. If this bit is set to 0, then system software must use a frame list length of 1024 elements with this host controller. The UHPHS_USBCMD register Frame List Size field is a read-only register and should be set to 0. If set to 1, then system software can specify and use a smaller frame list and configure the host controller via the UHPHS_USBCMD register Frame List Size field. The frame list must always be aligned on a 4-Kbyte page boundary. This requirement ensures that the frame list is always physically contiguous. ASPC: Asynchronous Schedule Park Capability The default value is Implementation dependent. If this bit is set to 1, then the host controller supports the park feature for high-speed queue heads in the Asynchronous Schedule. The feature can be disabled or enabled and set to a specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous Schedule Park Mode Count fields in the UHPHS_USBCMD register. IST: Isochronous Scheduling Threshold The default value is Implementation dependent. This field indicates, relative to the current position of the executing host controller, where software can reliably update the isochronous schedule. When bit [7] is 0, the value of the least significant 3 bits indicates the number of microframes a host controller can hold a set of isochronous data structures (one or more) before flushing the state. When bit [7] is set to 1, then host software assumes the host controller may cache an isochronous data structure for an entire frame. DS60001525A-page 924  2017 Microchip Technology Inc. SAMA5D4 SERIES EECP: EHCI Extended Capabilities Pointer The default value is Implementation dependent. This optional field indicates the existence of a capabilities list. A value of 00h indicates no extended capabilities are implemented. A nonzero value in this register indicates the offset in PCI configuration space of the first EHCI extended capability. The pointer value must be 40h or greater if implemented to maintain the consistency of the PCI header defined for this class of device.  2017 Microchip Technology Inc. DS60001525A-page 925 SAMA5D4 SERIES 36.7.4 UHPHS USB Command Register Name:UHPHS_USBCMD Access:Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 ITC 15 – 14 – 13 – 12 – 11 ASPME 10 – 9 7 LHCR 6 IAAD 5 ASE 4 PSE 3 2 1 HCRESET FLS 8 ASPMC 0 RS The Command Register indicates the command to be executed by the serial bus host controller. Writing to the register causes a command to be executed. RS: Run/Stop (read/write) 0: Stop (default value). 1: Run. When set to 1, the Host Controller proceeds with execution of the schedule. The Host Controller continues execution as long as this bit is set to 1. When this bit is set to 0, the Host Controller completes the current and any actively pipelined transactions on the USB and then halts. The Host Controller must halt within 16 microframes after software clears the Run bit. The HC Halted bit in the status register indicates when the Host Controller has finished its pending pipelined transactions and has entered the stopped state. Software must not write 1 to this field unless the host controller is in the Halted state (i.e., HCHalted in the UHPHS_USBSTS register is 1). Doing so will yield undefined results. HCRESET: Host Controller Reset (read/write) This control bit is used by software to reset the host controller. The effects of this on Root Hub registers are similar to a Chip Hardware Reset. When software writes a 1 to this bit, the Host Controller resets its internal pipelines, timers, counters, state machines, etc. to their initial value. Any transaction currently in progress on USB is immediately terminated. A USB reset is not driven on downstream ports. PCI Configuration registers are not affected by this reset. All operational registers, including port registers and port state machines, are set to their initial values. Port ownership reverts to the companion host controller(s) with side effects. Software must reinitialize the host controller in order to return the host controller to an operational state. This bit is set to 0 by the Host Controller when the reset process is complete. Software cannot terminate the reset process early by writing a 0 to this register. Software should not set this bit to 1 when the HCHalted bit in the UHPHS_USBSTS register is 0. Attempting to reset an actively running host controller will result in undefined behavior. FLS: Frame List Size (read/write or read-only) This field is R/W only if Programmable Frame List Flag in the UHPHS_HCCPARAMS registers is set to 1. This field specifies the size of the frame list. The size of the frame list controls which bits in the Frame Index Register should be used for the Frame List Current index. 00b: 1024 elements (4096 bytes) (default value). 01b: 512 elements (2048 bytes). 10b: 256 elements (1024 bytes), for resource-constrained environments. 11b: Reserved. DS60001525A-page 926  2017 Microchip Technology Inc. SAMA5D4 SERIES PSE: Periodic Schedule Enable (read/write) This bit controls whether the host controller skips processing the Periodic Schedule. 0: Do not process the Periodic Schedule (default value). 1: Use the UHPHS_PERIODICLISTBASE register to access the Periodic Schedule. ASE: Asynchronous Schedule Enable (read/write) This bit controls whether the host controller skips processing the Asynchronous Schedule. 0: Do not process the Asynchronous Schedule (default value). 1: Use the UHPHS_ASYNCLISTADDR register to access the Asynchronous Schedule. IAAD: Interrupt on Async Advance Doorbell (read/write) This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule. Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the UHPHS_USBSTS register. If the Interrupt on Async Advance Enable bit in the UHPHS_USBINTR register is set to 1, then the host controller will assert an interrupt at the next interrupt threshold. The host controller sets this bit to 0 after it has set the Interrupt on Async Advance status bit in the UHPHS_USBSTS register to 1. Software should not write a 1 to this bit when the asynchronous schedule is disabled. Doing so will yield undefined results. LHCR: Light Host Controller Reset (optional) (read/write) This control bit is not required. If implemented, it allows the driver to reset the EHCI controller without affecting the state of the ports or the relationship to the companion host controllers. For example, the UHPHS_PORTSC registers should not be reset to their default values and the CF bit setting should not go to 0 (retaining port ownership relationships). A host software read of this bit as 0 indicates the Light Host Controller Reset has completed and it is safe for host software to re-initialize the host controller. A host software read of this bit as 1 indicates the Light Host Controller Reset has not yet completed. If not implemented, a read of this field will always return a 0. ASPMC: Asynchronous Schedule Park Mode Count (optional) (read/write or read-only) If the Asynchronous Park Capability bit in the UHPHS_HCCPARAMS register is set to 1, then this field defaults to 3h and is R/W. Otherwise it defaults to 0 and is RO. It contains a count of the number of successive transactions the host controller is allowed to execute from a high-speed queue head on the Asynchronous schedule before continuing traversal of the Asynchronous schedule. Valid values are 1h to 3h. Software must not write a 0 to this bit when Park Mode Enable is set to 1 as this will result in undefined behavior. ASPME: Asynchronous Schedule Park Mode Enable (optional) (read/write or read-only) If the Asynchronous Park Capability bit in the UHPHS_HCCPARAMS register is set to 1, then this bit defaults to a 1h and is R/W. Otherwise the bit must be a 0 and is RO. Software uses this bit to enable or disable Park mode. When this bit is set to 1, Park mode is enabled. When this bit is set to 0, Park mode is disabled. ITC: Interrupt Threshold Control (read/write) This field is used by system software to select the maximum rate at which the host controller will issue interrupts. The only valid values are defined below. If software writes an invalid value to this register, the results are undefined. Value Maximum Interrupt Interval 00h Reserved 01h 1 microframe 02h 2 microframes 04h 4 microframes 08h 8 microframes (default, equates to 1 ms) 10h 16 microframes (2 ms) 20h 32 microframes (4 ms) 40h 64 microframes (8 ms)  2017 Microchip Technology Inc. DS60001525A-page 927 SAMA5D4 SERIES Any other value in this register yields undefined results. Software modifications to this bit while HCHalted bit is equal to 0 results in undefined behavior. DS60001525A-page 928  2017 Microchip Technology Inc. SAMA5D4 SERIES 36.7.5 UHPHS USB Status Register Name:UHPHS_USBSTS Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 ASS 14 PSS 13 RCM 12 HCHLT 11 – 10 – 9 – 8 – 7 – 6 – 5 IAA 4 HSE 3 FLR 2 PCD 1 USBERRINT 0 USBINT This register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software sets a bit to 0 in this register by writing a 1 to it. USBINT: USB Interrupt (read/write clear) The Host Controller sets this bit to 1 on the completion of a USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC bit set. The Host Controller also sets this bit to 1 when a short packet is detected (the actual number of bytes received was less than the expected number of bytes). USBERRINT: USB Error Interrupt (read/write clear) The Host Controller sets this bit to 1 when completion of a USB transaction results in an error condition (e.g., error counter underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both this bit and USBINT bit are set. PCD: Port Change Detect (read/write clear) The Host Controller sets this bit to 1 when any port for which the Port Owner bit is set to 0 (refer to Section 36.7.12 “UHPHS Port Status and Control Register”) has a change bit transition from 0 to 1 or a Force Port Resume bit transition from 0 to 1 as a result of a J-K transition detected on a suspended port. This bit will also be set as a result of the Connect Status Change being set to 1 after system software has relinquished ownership of a connected port by writing 1 to a port's Port Owner bit. This bit is allowed to be maintained in the Auxiliary power well. Alternatively, it is also acceptable that on a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of the PORTSC change bits (including: Force Port Resume, Over-Current Change, Enable/ Disable Change and Connect Status Change). FLR: Frame List Rollover (read/write clear) The Host Controller sets this bit to 1 when the Frame List Index (refer to Section 36.7.7 “UHPHS USB Frame Index Register”) rolls over from its maximum value to 0. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list size (as programmed in the Frame List Size field of the UHPHS_USBCMD register) is 1024, the Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly, if the size is 512, the Host Controller sets this bit to 1 every time FRINDEX[12] toggles. HSE: Host System Error (read/write clear) The Host Controller sets this bit to 1 when a serious error occurs during a host system access involving the Host Controller module. In a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master Abort, and PCI Target Abort. When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to prevent further execution of the scheduled TDs. IAA: Interrupt on Async Advance (read/write clear) 0: Default. System software can force the host controller to issue an interrupt the next time the host controller advances the asynchronous schedule by writing 1 to the Interrupt on the Async Advance Doorbell bit in the UHPHS_USBCMD register. This status bit indicates the assertion of that interrupt source.  2017 Microchip Technology Inc. DS60001525A-page 929 SAMA5D4 SERIES HCHLT: HCHalted (read-only) 1: Default. This bit is 0 whenever the Run/Stop bit is 1. The Host Controller sets this bit to 1 after it has stopped executing as a result of the Run/Stop bit being set to 0, either by software or by the Host Controller hardware (e.g. internal error). RCM: Reclamation (read-only) 0: Default. This is a read-only status bit used to detect any empty asynchronous schedule. PSS: Periodic Schedule Status (read-only) 0: Default. The bit reports the current real status of the Periodic Schedule. If this bit is set to 0, then the status of the Periodic Schedule is disabled. If this bit is set to 1, then the status of the Periodic Schedule is enabled. The Host Controller is not required to immediately disable or enable the Periodic Schedule when software transitions the Periodic Schedule Enable bit in the UHPHS_USBCMD register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or disabled (0). ASS: Asynchronous Schedule Status (read-only) 0: Default. The bit reports the current real status of the Asynchronous Schedule. If this bit is set to 0, then the status of the Asynchronous Schedule is disabled. If this bit is set to 1, then the status of the Asynchronous Schedule is enabled. The Host Controller is not required to immediately disable or enable the Asynchronous Schedule when software transitions the Asynchronous Schedule Enable bit in the UHPHS_USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or disabled (0). DS60001525A-page 930  2017 Microchip Technology Inc. SAMA5D4 SERIES 36.7.6 UHPHS USB Interrupt Enable Register Name:UHPHS_USBINTR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 IAAE 4 HSEE 3 FLRE 2 PCIE 1 USBEIE 0 USBIE This register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that are disabled in this register still appear in the UHPHS_USBSTS to allow the software to poll for events. Each interrupt enable bit description indicates whether it is dependent on the interrupt threshold mechanism. For all enable register bits, 1= Enabled, 0= Disabled. USBIE: USB Interrupt Enable When this bit is set to 1, and the USBINT bit in the UHPHS_USBSTS register is 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit. USBEIE: USB Error Interrupt Enable When this bit is set to 1, and the USBERRINT bit in the UHPHS_USBSTS register is 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the USBERRINT bit. PCIE: Port Change Interrupt Enable When this bit is set to 1, and the Port Change Detect bit in the UHPHS_USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Port Change Detect bit. FLRE: Frame List Rollover Enable When this bit is set to 1, and the Frame List Rollover bit in the UHPHS_USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Frame List Rollover bit. HSEE: Host System Error Enable When this bit is set to 1, and the Host System Error Status bit in the UHPHS_USBSTS register is 1, the host controller will issue an interrupt. The interrupt is acknowledged by software clearing the Host System Error bit. IAAE: Interrupt on Async Advance Enable When this bit is set to 1, and the Interrupt on Async Advance bit in the UHPHS_USBSTS register is 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async Advance bit.  2017 Microchip Technology Inc. DS60001525A-page 931 SAMA5D4 SERIES 36.7.7 UHPHS USB Frame Index Register Name:UHPHS_FRINDEX Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 10 9 8 7 6 5 2 1 0 FI 4 3 FI This register is used by the host controller to index into the periodic frame list. The register updates every 125 µs (once each microframe). Bits [N:3] are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by system software in the Frame List Size field in the UHPHS_USBCMD register (refer to Section 36.7.4 “UHPHS USB Command Register”). This register must be written as a DWord. Byte writes produce undefined results. This register cannot be written unless the Host Controller is in the Halted state as indicated by the HCHalted bit (UHPHS_USBSTS register, Section 36.7.5 “UHPHS USB Status Register”). A write to this register while the Run/Stop bit is set to 1 (UHPHS_USBCMD register, Section 36.7.4 “UHPHS USB Command Register”) produces undefined results. Writes to this register also affect the SOF value. FI: Frame Index The value in this register increments at the end of each time frame (e.g., microframe). Bits [N:3] are used for the Frame List current index. This means that each location of the frame list is accessed eight times (frames or microframes) before moving to the next index. The following illustrates values of N based on the value of the Frame List Size field in the UHPHS_USBCMD register. USBCMD [Frame List Size] Number Elements N 00b (1024) 12 01b (512) 11 10b (256) 10 11b Reserved – The SOF frame number value for the bus SOF token is derived or alternatively managed from this register. The value of FRINDEX must be 125 µs (1 microframe) ahead of the SOF token value. The SOF value may be implemented as an 11-bit shadow register. For this discussion, this shadow register is 11 bits and is named SOFV. SOFV updates every eight microframes (1 millisecond). An example implementation to achieve this behavior is to increment SOFV each time the FRINDEX[2:0] increments from 0 to 1. Software must use the value of FRINDEX to derive the current microframe number, both for high-speed isochronous scheduling purposes and to provide the “get microframe number” function required for client drivers. Therefore, the value of FRINDEX and the value of SOFV must be kept consistent if chip is reset or software writes to FRINDEX. Writes to FRINDEX must also write-through FRINDEX[13:3] to SOFV[10:0]. In order to keep the update as simple as possible, software should never write a FRINDEX value where the three least significant bits are 111b or 000b. DS60001525A-page 932  2017 Microchip Technology Inc. SAMA5D4 SERIES 36.7.8 UHPHS Control Data Structure Segment Register Name:UHPHS_CTRLDSSEGMENT Access:Read/Write This 32-bit register corresponds to the most significant address bits [63:32] for all EHCI data structures. If the 64-bit Addressing Capability field in UHPHS_HCCPARAMS is set to 0, then this register is not used. Software cannot write to it and a read from this register will return zeros. If the 64-bit Addressing Capability field in UHPHS_HCCPARAMS is 1, then this register is used with the link pointers to construct 64-bit addresses to EHCI control data structures. This register is concatenated with the link pointer from either the UHPHS_PERIODICLISTBASE, UHPHS_ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address. This register must be written as a DWord. Byte writes produce undefined results. This register allows the host software to locate all control data structures within the same 4-Gigabyte memory segment.  2017 Microchip Technology Inc. DS60001525A-page 933 SAMA5D4 SERIES 36.7.9 UHPHS Periodic Frame List Base Address Register Name:UHPHS_PERIODICLISTBASE Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 BA 23 22 21 20 BA 15 14 13 12 11 – 10 – 9 – 8 – 5 – 4 – 3 – 2 – 1 – 0 – BA 7 – 6 – This 32-bit register contains the beginning address of the Periodic Frame List in the system memory. If the host controller is in 64-bit mode (as indicated by a 1 in the 64-bit Addressing Capability field in the UHPHS_HCCSPARAMS register), then the most significant 32 bits of every control data structure address comes from the UHPHS_CTRLDSSEGMENT register (refer to Section 36.7.8 “UHPHS Control Data Structure Segment Register”). System software loads this register prior to starting the schedule execution by the Host Controller. The memory structure referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register are combined with the Frame Index Register (UHPHS_FRINDEX) to enable the Host Controller to step through the Periodic Frame List in sequence. This register must be written as a DWord. Byte writes produce undefined results. BA: Base Address (Low) These bits correspond to memory address signals [31:12], respectively. DS60001525A-page 934  2017 Microchip Technology Inc. SAMA5D4 SERIES 36.7.10 UHPHS Asynchronous List Address Register Name:UHPHS_ASYNCLISTADDR Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 – LPL 23 22 21 20 LPL 15 14 13 12 LPL 7 6 LPL 5 4 – This 32-bit register contains the address of the next asynchronous queue head to be executed. If the host controller is in 64-bit mode (as indicated by a 1 in the 64-bit Addressing Capability field in the UHPHS_HCCPARAMS register), then the most significant 32 bits of every control data structure address comes from the UHPHS_CTRLDSSEGMENT register (refer to Section 36.7.8 “UHPHS Control Data Structure Segment Register”). Bits [4:0] of this register cannot be modified by system software and will always return a zero when read. The memory structure referenced by this physical memory pointer is assumed to be 32-byte (cache line) aligned. This register must be written as a DWord. Byte writes produce undefined results. LPL: Link Pointer Low These bits correspond to memory address signals [31:5], respectively. This field may only reference a Queue Head (QH).  2017 Microchip Technology Inc. DS60001525A-page 935 SAMA5D4 SERIES 36.7.11 UHPHS Configure Flag Register Name:UHPHS_CONFIGFLAG Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CF This register is in the auxiliary power well. It is only reset by hardware when the auxiliary power is initially applied or in response to a host controller reset. CF: Configure Flag (read/write) Host software sets this bit as the last action in its process of configuring the Host Controller. This bit controls the default port-routing control logic. Bit values and side-effects are listed below. 0: Port routing control logic default-routes each port to an implementation-dependent classic host controller (default value). 1: Port routing control logic default-routes all ports to this host controller. DS60001525A-page 936  2017 Microchip Technology Inc. SAMA5D4 SERIES 36.7.12 UHPHS Port Status and Control Register Name:UHPHS_PORTSC_x[x = 0..2] Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 WKOC_E 21 WKDSCNNT_E 20 WKCNNT_E 19 18 14 13 PO 12 PP 11 5 OCC 4 OCA 3 PEDC 15 PIC 7 SUS 6 FPR 25 – 24 – 17 16 10 9 – 8 PR 2 PED 1 CSC 0 CCS PTC LS A host controller must implement one or more port registers. The number of port registers implemented by a particular instantiation of a host controller is documented in the UHPHS_HCSPARAMS register (Section 36.7.2 “UHPHS Host Controller Structural Parameters Register”). Software uses this information as an input parameter to determine how many ports need to be serviced. All ports have the structure defined below. This register is in the auxiliary power well. It is only reset by hardware when the auxiliary power is initially applied or in response to a host controller reset. The initial conditions of a port are: • No device connected • Port disabled If the port has port power control, software cannot change the state of the port until after it applies power to the port by setting port power to a 1. Software must not attempt to change the state of the port until after power is stable on the port. The host is required to have power stable to the port within 20 milliseconds of the 0 to 1 transition. Note 1: When a device is attached, the port state transitions to the connected state and system software will process this as with any status change notification. 2: If a port is being used as the Debug Port, then the port may report device connected and enabled when the Configured Flag is set to 0. CCS: Current Connect Status (read-only) 0: No device is present (default value). 1: Device is present on port. This value reflects the current state of the port, and may not correspond directly to the event that caused the Connect Status Change bit (Bit 1) to be set. This field is 0 if Port Power is 0. CSC: Connect Status Change (read/write clear) 0: No change (default value). 1: Change in Current Connect Status. Indicates a change has occurred in the port’s Current Connect Status. The host controller sets this bit for all changes to the port device connect status, even if system software has not cleared an existing connect status change. For example, the insertion status changes twice before system software has cleared the changed condition, hub hardware will be “setting” an already-set bit (i.e., the bit will remain set). Software sets this bit to 0 by writing a 1 to it. This field is 0 if Port Power is 0. PED: Port Enabled/Disabled (read/write) 0: Disable (default value). 1: Enable.  2017 Microchip Technology Inc. DS60001525A-page 937 SAMA5D4 SERIES Ports can only be enabled by the host controller as a part of the reset and enable. Software cannot enable a port by writing a 1 to this field. The host controller will only set this bit to 1 when the reset sequence determines that the attached device is a high-speed device. Ports can be disabled by either a fault condition (disconnect event or other fault condition) or by host software. Note that the bit status does not change until the port state actually changes. There may be a delay in disabling or enabling a port due to other host controller and bus events. When the port is disabled (0b), downstream propagation of data is blocked on this port, except for reset. This field is 0 if Port Power is 0. PEDC: Port Enable/Disable Change (read/write clear) 0: No change (default value). 1: Port enabled/disabled status has changed. For the root hub, this bit gets set to 1 only when a port is disabled due to the appropriate conditions existing at the EOF2 point (refer to Chapter 11 of the USB Specification for the definition of a Port Error). Software clears this bit by writing a 1 to it. This field is 0 if Port Power is 0. OCA: Over-current Active (read-only) 0: This port does not have an over-current condition (default value). 1: This port currently has an over-current condition. This bit will automatically transition from 1 to 0 when the over current condition is removed. OCC: Over-current Change (read/write clear) 0: Default value. 1: This bit gets set to 1 when there is a change to Over-current Active. Software clears this bit by writing 1 to this bit position. FPR: Force Port Resume (read/write) 0: No resume (K-state) detected/driven on port (default value). 1: Resume detected/driven on port. This functionality defined for manipulating this bit depends on the value of the Suspend bit. For example, if the port is not suspended (Suspend and Enabled bits are set to 1) and software transitions this bit to 1, then the effects on the bus are undefined. Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit to 1 if a J-to-K transition is detected while the port is in the Suspend state. When this bit transitions to 1 because a J-to-K transition is detected, the Port Change Detect bit in the UHPHS_USBSTS register is also set to 1. If software sets this bit to 1, the host controller must not set the Port Change Detect bit. Note that when the EHCI controller owns the port, the resume sequence follows the defined sequence documented in the USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the port as long as this bit remains set to 1. Software must appropriately time the Resume and set this bit to 0 when the appropriate amount of time has elapsed. Writing a 0 (from 1) causes the port to return to High-Speed mode (forcing the bus below the port into a high-speed idle). This bit will remain set to 1 until the port has switched to the high-speed idle. The host controller must complete this transition within 2 milliseconds of software setting this bit to 0. This field is 0 if Port Power is 0. SUS: Suspend (read/write) 0: Port not in suspend state (default value). 1: Port in suspend state. Port Enabled Bit and Suspend bit of this register define the port states as follows: Bits [Port Enabled, Suspend] Port State 0X Disable 10 Enable 11 Suspend DS60001525A-page 938  2017 Microchip Technology Inc. SAMA5D4 SERIES When in suspend state, downstream propagation of data is blocked on this port, except for port reset. The blocking occurs at the end of the current transaction, if a transaction was in progress when this bit was written to 1. In the suspend state, the port is sensitive to resume detection. Note that the bit status does not change until the port is suspended and that there may be a delay in suspending a port if there is a transaction currently in progress on the USB. A write of 0 to this bit is ignored by the host controller. The host controller will unconditionally set this bit to 0 when: • Software sets the Force Port Resume bit to 0 (from 1). • Software sets the Port Reset bit to 1 (from 0). If host software sets this bit to 1 when the port is not enabled (i.e., Port Enabled bit set to 0), the results are undefined. This field is 0 if Port Power is set to 0. PR: Port Reset (read/write) 0: Port is not in Reset (default value). 1: Port is in Reset. When software writes a 1 to this bit (from 0), the bus reset sequence as defined in the USB Specification Revision 2.0 is started. Software writes a 0 to this bit to terminate the bus reset sequence. Software must keep this bit set to 1 long enough to ensure the reset sequence, as specified in the USB Specification Revision 2.0, completes. Note: When software writes this bit to 1, it must also write 0 to the Port Enable bit. When software writes a 0 to this bit, there may be a delay before the bit status changes to 0. The bit status will not read as 0 until after the reset has completed. If the port is in High-Speed mode after reset is complete, the host controller will automatically enable this port (e.g., set the Port Enable bit to 1). A host controller must terminate the reset and stabilize the state of the port within 2 milliseconds of software transitioning this bit from 1 to 0. For example: if the port detects that the attached device is high-speed during reset, then the host controller must have the port in the enabled state within 2 ms of software writing this bit to 0. The HCHalted bit in the UHPHS_USBSTS register should be set to 0 before software attempts to use this bit. The host controller may hold Port Reset asserted to 1 when the HCHalted bit is 1. This field is 0 if Port Power is 0. LS: Line Status (read-only) These bits reflect the current logical levels of the D+ (bit 11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB devices prior to the port reset and enable sequence. This field is valid only when the port enable bit is 0 and the current connect status bit is set to 1. Bits are encoded as follows: Value USB State Interpretation 00b SE0 Not a low-speed device, perform EHCI reset 10b J-state Not a low-speed device, perform EHCI reset 01b K-state Low-speed device, release ownership of port 11b Undefined Not a low-speed device, perform EHCI reset This value of this field is undefined if Port Power is 0. PP: Port Power (read/write or read-only) The function of this bit depends on the value of the Port Power Control (PPC) field in the UHPHS_HCSPARAMS register. The behavior is as follows: PPC PP 0b 1b Operation Read-only. Host controller does not have port power control switches. Each port is hard-wired to power. Read/write. 1b 1b/0b Host controller has port power control switches. This bit represents the current setting of the switch (0 = off, 1 = on). When power is not available on a port (i.e., PP at 0), the port is non-functional and will not report attaches, detaches, etc.  2017 Microchip Technology Inc. DS60001525A-page 939 SAMA5D4 SERIES When an overcurrent condition is detected on a powered port and PPC is set to 1, the PP bit in each affected port may be transitioned by the host controller from 1 to 0 (removing power from the port). PO: Port Owner (read/write) 0: This bit unconditionally goes to a 0 when the Configured bit in the UHPHS_CONFIGFLAG register makes a 0 to 1 transition. 1: This bit unconditionally goes to 1 whenever the Configured bit is 0 (default value). System software uses this field to release ownership of the port to a selected host controller (in the event that the attached device is not a high-speed device). Software writes 1 to this bit when the attached device is not a high-speed device. A 1 in this bit means that a companion host controller owns and controls the port. PIC: Port Indicator Control (read/write) 00b: Default value. Writing to these bits has no effect if the P_INDICATOR bit in the UHPHS_HCSPARAMS register is set to 0. If the P_INDICATOR bit is set to 1, then the bits are encoded as follows: Value Meaning 00b Port indicators are off 01b Amber 10b Green 11b Undefined Refer to the USB Specification Revision 2.0 for a description on how these bits are to be used. This field is 0 if Port Power is 0. PTC: Port Test Control (read/write) 0000b: Default value. When this field is set to 0, the port is NOT operating in a test mode. A non-zero value indicates that it is operating in test mode and the specific test mode is indicated by the specific value. Test mode bits are encoded as follows (0110b - 1111b are reserved): Value Test Mode 0000b Test mode not enabled 0001b Test J_STATE 0010b Test K_STATE 0011b Test SE0_NAK 0100b Test Packet 0101b Test FORCE_ENABLE Refer to the USB Specification Revision 2.0, Chapter 7, for details on each test mode. WKCNNT_E: Wake on Connect Enable (read/write) 0: Default value. Writing this bit to 1 enables the port to be sensitive to device connects as wakeup events. This field is 0 if Port Power is 0. WKDSCNNT_E: Wake on Disconnect Enable (read/write) 0: Default value. Writing this bit to 1 enables the port to be sensitive to device disconnects as wakeup events. This field is 0 if Port Power is 0. DS60001525A-page 940  2017 Microchip Technology Inc. SAMA5D4 SERIES WKOC_E: Wake on Over-current Enable (read/write) 0: Default value. Writing this bit to 1 enables the port to be sensitive to over-current conditions as wakeup events. This field is 0 if Port Power is 0.  2017 Microchip Technology Inc. DS60001525A-page 941 SAMA5D4 SERIES 36.7.13 EHCI: REG00 - Programmable Microframe Base Value Name:UHPHS_INSNREG00 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 14 13 12 11 15 7 6 5 24 – 17 16 9 8 1 0 En Debug 10 MFC_8 Debug 25 – MFC_16 4 MFC_16 3 2 The Programmable Microframe Base Value is used to change the microframe length value (default is microframe SOF = 125 µs) in order to reduce simulation time. En: Enable this Register 0: Register disabled (default value). 1: Register enabled. Note: Do not enable this register for the gate-level netlist. MFC_16: Microframe Counter with Word Byte Interface This value is used as the 1-microframe counter with 16-bit interface. MFC_8: Microframe Counter with Byte Interface This value is used as the 1-microframe counter with 8-bit interface. Debug: Debug Purposes This field is used for debug purposes only. In Heterogeneous mode, if the per port clock gets out of sync (but still within the ppm limits) of the phy_clk, then the per port SOF counter needs some correction relative to the global SOF counter. The RTL corrects itself if this happens. This field controls the SOF correction, in case some debugging is required for the correction. If bit 14 is set to 1, then it enables the RTL to use the value in bits 19:15 to perform the correction. In normal operating mode, these bits should not be written. Note: The “value” in bits [31:1] must be programmed as follows: (value + 32/64) * Clock Period = microframe timer duration Factor 32 is used for a 16-bit interface and factor 64 is used for an 8-bit interface. For example, for the full (125 µs) microframe duration: - In 8-bit, 60 MHz mode, the value is h1D0C (=7436), so (7436 + 64) * 16.67 ns = 125 µs - In 16-bit, 30 MHz mode, the value is hE86 (=3718), so (3718 + 32) * 33.33 ns = 125 µs For a 50 µs microframe duration: - In 8-bit, 60 MHz mode, the value is hB77 (=2395), so (2395 + 64) * 16.67 ns = 50 µs - In 16-bit, 30 MHz mode, the value is h5BC (=1468), so (1468 + 32) * 33.33 ns = 50 µs DS60001525A-page 942  2017 Microchip Technology Inc. SAMA5D4 SERIES 36.7.14 EHCI: REG01 - Programmable Packet Buffer OUT/IN Thresholds Name:UHPHS_INSNREG01 Access:Read/Write 31 30 29 28 27 Out_Threshold 26 25 24 23 22 21 20 19 Out_Threshold 18 17 16 15 14 13 12 11 10 9 8 3 2 1 0 In_Threshold 7 6 5 4 In_Threshold Programmable Packet Buffer OUT/IN thresholds (in CONFIG1 mode only, not applicable in Config2 mode). The value specified here is the number of DWORDs (32-bit entries). In_Threshold: Amount of Data Available in the IN Packet Buffer The IN threshold is used to start the memory transfer as soon as the IN threshold amount of data is available in the Packet Buffer. It is also used to disconnect the data write, if the threshold amount of data is not available in the Packet Buffer. Out_Threshold: Amount of Data Available in the OUT Packet Buffer The OUT threshold is used to start the USB transfer as soon as the OUT threshold amount of data is fetched from system memory. It is also used to disconnect the data fetch, if the threshold amount of space is not available in the Packet Buffer. The minimum OUT and IN threshold amount that can be programmed through INSN registers is 16 bytes. For INCRX configurations, the minimum threshold amount that can be programmed is the highest possible INCRX burst value. For example, if the value of the strap signals {ss_ena_incr16_i, ss_ena_incr8_i, ss_ena_incr4_i} is 3'b011 (for example, INCR16 burst is disabled, INCR8/INCR4 bursts are enabled), then the minimum OUT and IN threshold values should be 32 bytes (8 DWords). OUT and IN threshold values can be equal to the packet buffer depth only when one of the following conditions is met: • The packet buffer depth is equal to 512 bytes and isochronous/interrupt transactions are not initiated by the host controller. • The packet buffer depth is equal to 1024 bytes. The threshold default value depends on one of the following packet buffer configurations: • 1024 bytes depth, 256 bytes IN and OUT thresholds • 512 bytes depth, 128 bytes IN and OUT thresholds • 256 bytes depth, 64 bytes IN and OUT thresholds • 128 bytes depth, 64 bytes IN and OUT thresholds • 64 bytes depth, 60 bytes IN and OUT thresholds For INCRX configurations, the Break Memory Transfer bit is always enabled. Depending on the different packet buffer settings, not all MSB bits are used.  2017 Microchip Technology Inc. DS60001525A-page 943 SAMA5D4 SERIES 36.7.15 EHCI: REG02 - Programmable Packet Buffer Depth Name:UHPHS_INSNREG02 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 Dwords 3 2 Dwords Programmable Packet Buffer Depth (in CONFIG1 mode only, not applicable in Config2 mode). The value specified here is the number of DWORDs (32-bit entries). Dwords: Number of Entries For a maximum 256 entries for 1-Kbyte packet buffer, bits [8:0] are sufficient. DS60001525A-page 944  2017 Microchip Technology Inc. SAMA5D4 SERIES 36.7.16 EHCI: REG03 Name:UHPHS_INSNREG03 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 EN_CK256 13 Ignore_LS 12 11 Tx_Tx 10 9 Per_Frame 8 TA_Offset 7 6 5 4 TA_Offset 3 2 1 0 Break_Mem The default value for INSNREG03[0] depends on the host core configuration. So, if INCRx support is enabled, this bit is 1 after reset. Otherwise, it should stay at 0. Break_Mem: Break Memory Transfer (in CONFIG1 mode only, not applicable in CONFIG2 mode) 0: Disables this function. 1: Enables this function. Used in conjunction with INSNREG01 to enable breaking memory transactions into chunks once the OUT/IN threshold value is reached. TA_Offset: Time-Available Offset This value indicates the additional number of bytes to be accommodated for the time-available calculation. The USB traffic on the bus can be started only when sufficient time is available to complete the packet within the EOF1 point. Refer to the USB 2.0 specification for details of the EOF1 point. This time-available calculation is done in the hardware, and can be further offset by programming a value in this location. Note: Time-available calculation is added for future flexibility. The application is not required to program this field by default. Per_Frame: Periodic Frame List Fetch In CONFIG1 mode only (“EHCI Descriptor/Data Prefetching” is disabled in core configuration), setting this bit forces the host controller to fetch the periodic frame list in every microframe of a frame. If not set, then the periodic frame list is fetched only in microframe 0 of every frame. The default is 0 (not set). This bit can be changed only during core initialization and should not be changed afterwards. Tx_Tx: Tx-Tx Turnaround Delay Add-on This field specifies the extra delays in phy_clks to be added to the “Transmit to Transmit turnaround delay” value maintained in the core. The default value of this register field is 0. This default value of 0 is sufficient for most PHYs. But for some PHYs which enter wait states during the token packet, it may be required to program a value greater than 0 to meet the transmit-to-transmit minimum turnaround time. It is recommended to use default value 0 and to change it only if there is an issue with minimum transmit-to-transmit turnaround time. This value should be programmed during core initialization and should not be changed afterwards. Ignore_LS: Ignore Linestate During TestSE0 Nak When set to 1 (default), the core ignores the linestate checking when transmitting SOF in SE0_NAK Test mode. When set to 0, the port state machine disables the port if it does not find the linestate to be in SE0 when transmitting SOF during the SE0_NAK test. While performing impedance measurement during the SE0_NAK test, the linestate could go to non SE0 forcing the core to disable the port. This bit is used to control the port behavior during this operation.  2017 Microchip Technology Inc. DS60001525A-page 945 SAMA5D4 SERIES EN_CK256: Enable 256 Clock Checking This bit controls the End of Resume sequence of the EHCI host controller. By default, the value of this bit is 0 and during the End of Resume sequence, the host controller waits for SE0 on the linestate before switching the PHY to High-Speed. When set to 1, during the End of Resume sequence, the controller waits for SE0 or 256 clocks before switching the PHY to High-Speed. Setting this bit to 1 enables the 256-clock check. Some of the UTMI PHYs do not present SE0 on the linestate during the End of Resume sequence. For such PHYs, this bit should be set, so that the core does not wait forever for SE0. This bit should be set only during initialization. DS60001525A-page 946  2017 Microchip Technology Inc. SAMA5D4 SERIES 36.7.17 EHCI: REG04 Name:UHPHS_INSNREG04 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 – – EN_AutoFunc NAK_RF – SDPE_TIME 1 0 HCSPARAMS_ HCCPARAMS_ W BW Bits [2:0] are used for debug purposes. Bits [(5+UHC2_N_PORTS):4] are functional bits where UHC2_N_PORTS indicates the number of physical USB ports. HCSPARAMS_W: HCSPARAMS Write When set, the HCSPARAMS register becomes writable. Upon system reset, this bit is 0. HCCPARAMS_BW: HCCPARAMS Bits Write When set, the HCCPARAMS register's bits 17, 15:4, and 2:0 become writable. Upon system reset, these bits are 0. SDPE_TIME: Scales Down Port Enumeration Time When set, Scales Down Port Enumeration Time is enabled. Reset value is 1’b0. Note: This bit can be used for both RTL and Gate level simulations. NAK_RF: NAK Reload Fix (Read/Write) 0: Enables this function. 1: Disables this function Incorrect NAK reload transition at the end of a microframe for backward compatibility with Release 2.40c. For more information, refer to the USB 2.0 Host-AHB Release Notes. Reset value is 1’b0. EN_AutoFunc: Enable Automatic Feature 0: Enables the automatic feature. The Suspend signal is deasserted (logic level 1'b1) when run/stop is reset by software, but the hchalted bit is not set yet. 1: Disables the automatic feature, which takes all ports out of suspend when software clears the run/stop bit. This is for backward compatibility. Bit [5] has an added functionality in release 2.80a and later. For systems where the host is halted without waking up all ports out of suspend, the port can remain suspended because the PHYCLK is not running when the halt is programmed. To avoid this, the DWC H20AHB host core automatically pulls ports out of suspend when the host is halted by software. This bit is used to disable this automatic function. Reset value is 0.  2017 Microchip Technology Inc. DS60001525A-page 947 SAMA5D4 SERIES 36.7.18 EHCI: REG05 - UTMI Configuration Name:UHPHS_INSNREG05 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 VBusy 16 VPort 15 14 VPort 13 12 VControlLoadM 11 10 9 8 6 5 4 3 1 0 7 VControl 2 VStatus Control and Status Register, used to read the UTMI registers from the following signals: VStatus: Vendor Status (Software RO) VControl: Vendor Control (Software R/W) VControlLoadM: Vendor Control Load Microframe 0: Load. 1: NOP (software R/W) VPort: Vendor Port (Software R/W) Valid values range from 1 to 15 depending on coreConsultant configuration. For example, if the number of ports is 3, then software should only write values 1, 2, and 3 to this field and not any other values in the range, that is, 0 or 4 to 15. For example, if the software writes value 4 to VPort, from that write onwards, any write to this register is ignored and the read value will always be 4. VBusy: Vendor Busy (Software RO) Hardware indicator that a write to this register has occurred and the hardware is currently processing the operation defined by the data written. When processing is finished, this bit is cleared. DS60001525A-page 948  2017 Microchip Technology Inc. SAMA5D4 SERIES 36.7.19 EHCI: REG06 - AHB Error Status Name:UHPHS_INSNREG06 Access:Read/Write 31 AHB_ERR 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 HBURST 9 8 Nb_Burst 7 6 5 4 3 Nb_Burst 2 1 Nb_Success_Burst 0 Control and Status Register, used to read the UTMI registers from the following signals: Nb_Success_Burst: Number of Successful Bursts (read-only)(1) Number of successfully completed beats in the current burst before the AHB error occurred. Nb_Burst: Number of Bursts (read-only)(1) Number of beats expected in the burst at which the AHB error occurred. Valid values are 0 to 16. 5'b10001–5b11111: Reserved 5'b00000–5b10000: Valid HBURST: Burst Value (read-only)(1) Value of the control phase at which the AHB error occurred. Note 1: This field applies to AHB INCRX-enabled configurations only. AHB_ERR: AHB Error AHB Error Captured Indicator that an AHB error was encountered and values were captured. To clear this field the application must write a 0 to it. EHCI: – When no error, 0 is written to INSNREG06[8:4]. – When INCR4 and an error occur, 4 is written to INSNREG06[8:4]. – When INCR8 and an error occur, 8 is written to INSNREG06[8:4]. – When INCR16 and an error occur, 16 is written to INSNREG06[8:4]. – Other values except 4, 8, and 16 are not written to INSNREG06[8:4]. OHCI: – When no error, 0 is written to INSNREG06[8:4]. – When INCR4 and error occur, 4 is written to INSNREG06[8:4]. – Other values except 4 are not written to INSNREG06[8:4].  2017 Microchip Technology Inc. DS60001525A-page 949 SAMA5D4 SERIES 36.7.20 EHCI: REG07 - AHB Master Error Address Name:UHPHS_INSNREG07 Access:Read Only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 AHB_ADDR 23 22 21 20 AHB_ADDR 15 14 13 12 AHB_ADDR 7 6 5 4 AHB_ADDR AHB_ADDR: AHB Address (read only) AHB address of the control phase at which the AHB error occurred. DS60001525A-page 950  2017 Microchip Technology Inc. SAMA5D4 SERIES 37. Ethernet MAC (GMAC) 37.1 Description The Ethernet MAC (GMAC) module implements a 10/100 Mbps Ethernet MAC compatible with the IEEE 802.3 standard. The GMAC can operate in either half or full duplex mode at all supported speeds. The GMAC Network Configuration Register is used to select the speed, duplex mode and interface type (MII, RMII). 37.2 • • • • • • • • • • • • • • • • • • • • • • • Embedded Characteristics Compatible with IEEE Standard 802.3 10, 100 Mbps Operation Full and Half Duplex Operation at all Supported Speeds of Operation Statistics Counter Registers for RMON/MIB MII/RMII Interface to the Physical Layer Integrated Physical Coding Direct Memory Access (DMA) Interface to External Memory Programmable Burst Length and Endianism for DMA Interrupt Generation to Signal Receive and Transmit Completion, Errors or Other Events Automatic Pad and Cyclic Redundancy Check (CRC) Generation on Transmitted Frames Automatic Discard of Frames Received with Errors Receive and Transmit IP, TCP and UDP Checksum Offload. Both IPv4 and IPv6 Packet Types Supported Address Checking Logic for Four Specific 48-bit Addresses, Four Type IDs, Promiscuous Mode, Hash Matching of Unicast and Multicast Destination Addresses and Wake-on-LAN Management Data Input/Output (MDIO) Interface for Physical Layer Management Support for Jumbo Frames up to 10240 Bytes Full Duplex Flow Control with Recognition of Incoming Pause Frames and Hardware Generation of Transmitted Pause Frames Half Duplex Flow Control by Forcing Collisions on Incoming Frames Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and Priority Tagged Frames Support for 802.1Qbb Priority-based Flow Control Programmable Inter Packet Gap (IPG) Stretch Recognition of IEEE 1588 PTP Frames IEEE 1588 Time Stamp Unit (TSU) Support for 802.1AS Timing and Synchronization  2017 Microchip Technology Inc. DS60001525A-page 951 SAMA5D4 SERIES 37.3 Block Diagram Figure 37-1: Block Diagram Status & Statistic Registers Register Interface APB MDIO Control Registers MAC Transmitter AHB DMA Interface AHB FIFO Interface Media Interface MAC Receiver Frame Filtering 37.4 Signal Interfaces The GMAC includes the following signal interfaces: • • • • MII, RMII to an external PHY MDIO interface for external PHY management Slave APB interface for accessing GMAC registers Master AHB interface for memory access Table 37-1: GMAC Connections in Different Modes Signal Name Function MII RMII Transmit Clock or Reference Clock TXCK REFCK GTXEN Transmit Enable TXEN TXEN GTX[3..0] Transmit Data TXD[3:0] TXD[1:0] GTXER Transmit Coding Error TXER Not Used GRXCK Receive Clock RXCK Not Used GRXDV Receive Data Valid RXDV CRSDV GRX[3..0] Receive Data RXD[3:0] RXD[1:0] GRXER Receive Error RXER RXER GCRS Carrier Sense and Data Valid CRS Not Used GTXCK (1) DS60001525A-page 952  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 37-1: GMAC Connections in Different Modes (Continued) Signal Name Function MII RMII GCOL Collision Detect COL Not Used GMDC Management Data Clock MDC MDC GMDIO Management Data Input/Output MDIO MDIO Note 1: Input only. GTXCK must be provided with a 25 MHz / 50 MHz external crystal oscillator for MII / RMII interfaces, respectively. 37.5 Product Dependencies 37.5.1 I/O Lines The pins used for interfacing the GMAC may be multiplexed with PIO lines. The programmer must first program the PIO Controller to assign the pins to their peripheral function. If I/O lines of the GMAC are not used by the application, they can be used for other purposes by the PIO Controller. Table 37-2: I/O Lines Instance Signal I/O Line Peripheral GMAC0 G0_COL PB5 A GMAC0 G0_CRS PB4 A GMAC0 G0_MDC PB16 A GMAC0 G0_MDIO PB17 A GMAC0 G0_RXCK PB1 A GMAC0 G0_RXDV PB6 A GMAC0 G0_RXER PB7 A GMAC0 G0_RX0 PB8 A GMAC0 G0_RX1 PB9 A GMAC0 G0_RX2 PB10 A GMAC0 G0_RX3 PB11 A GMAC0 G0_TXCK PB0 A GMAC0 G0_TXEN PB2 A GMAC0 G0_TXER PB3 A GMAC0 G0_TX0 PB12 A GMAC0 G0_TX1 PB13 A GMAC0 G0_TX2 PB14 A GMAC0 G0_TX3 PB15 A GMAC1 G1_COL PA9 B GMAC1 G1_CRS PA6 B GMAC1 G1_MDC PA22 B GMAC1 G1_MDIO PA23 B GMAC1 G1_RXCK PA3 B GMAC1 G1_RXDV PA10 B GMAC1 G1_RXER PA11 B  2017 Microchip Technology Inc. DS60001525A-page 953 SAMA5D4 SERIES Table 37-2: I/O Lines (Continued) GMAC1 G1_RX0 PA12 B GMAC1 G1_RX1 PA13 B GMAC1 G1_RX2 PA18 B GMAC1 G1_RX3 PA19 B GMAC1 G1_TXCK PA2 B GMAC1 G1_TXEN PA4 B GMAC1 G1_TXER PA5 B GMAC1 G1_TX0 PA14 B GMAC1 G1_TX1 PA15 B GMAC1 G1_TX2 PA20 B GMAC1 G1_TX3 PA21 B 37.5.2 Power Management The GMAC is not continuously clocked. The user must first enable the GMAC clock in the Power Management Controller before using it. 37.5.3 Interrupt Sources The GMAC interrupt line is connected to one of the internal sources of the interrupt controller. Using the GMAC interrupt requires prior programming of the interrupt controller. The GMAC features 1 interrupt sources. Refer to Section 8.2 “Peripheral Identifiers” for the interrupt numbers for GMAC priority queues. Table 37-3: Peripheral IDs Instance ID GMAC0 54 GMAC1 55 37.6 37.6.1 Functional Description Media Access Controller The Media Access Controller (MAC) transmit block takes data from FIFO, adds preamble and, if necessary, pad and frame check sequence (FCS). Both half duplex and full duplex Ethernet modes of operation are supported. When operating in half duplex mode, the MAC transmit block generates data according to the carrier sense multiple access with collision detect (CSMA/CD) protocol. The start of transmission is deferred if carrier sense (CRS) is active. If collision (COL) becomes active during transmission, a jam sequence is asserted and the transmission is retried after a random backoff. The CRS and COL signals have no effect in full duplex mode. The MAC receive block checks for valid preamble, FCS, alignment and length, and presents received frames to the MAC address checking block and FIFO. Software can configure the GMAC to receive jumbo frames up to 10240 bytes. It can optionally strip CRC from the received frame prior to transfer to FIFO. The address checker recognizes four specific 48-bit addresses, can recognize four different type ID values, and contains a 64-bit Hash register for matching multicast and unicast addresses as required. It can recognize the broadcast address of all ones and copy all frames. The MAC can also reject all frames that are not VLAN tagged and recognize Wake on LAN events. The MAC receive block supports offloading of IP, TCP and UDP checksum calculations (both IPv4 and IPv6 packet types supported), and can automatically discard bad checksum frames. 37.6.2 1588 Time Stamp Unit The 1588 time stamp unit (TSU) is implemented as a 94-bit timer. The 48 upper bits [93:46] of the timer count seconds and are accessible in the “GMAC 1588 Timer Seconds High Register” (GMAC_TSH) and “GMAC 1588 Timer Seconds Low Register” (GMAC_TSL). The 30 lower bits [45:16] of the timer count nanoseconds and are accessible in the “GMAC 1588 Timer Nanoseconds Register” (GMAC_TN). The lowest 16 bits [15:0] of the timer count sub-nanoseconds. DS60001525A-page 954  2017 Microchip Technology Inc. SAMA5D4 SERIES The 46 lower bits roll over when they have counted to one second. The timer increments by a programmable period (to approximately 15.2 femtoseconds resolution) with each MCK period and can also be adjusted in 1ns resolution (incremented or decremented) through APB register accesses. 37.6.3 AHB Direct Memory Access Interface The GMAC DMA controller performs six types of operations on the AHB bus. The order of priority of these operations is: 1. 2. 3. 4. 5. 6. Receive buffer manager write Receive buffer manager read Transmit buffer manager write Transmit buffer manager read Receive data DMA write Transmit data DMA read 37.6.3.1 Receive AHB Buffers Received frames, optionally including FCS, are written to receive AHB buffers stored in memory. The receive buffer depth is programmable in the range of 64 bytes to 16 Kbytes through the DMA Configuration register, with the default being 128 bytes. The start location for each receive AHB buffer is stored in memory in a list of receive buffer descriptors at an address location pointed to by the receive buffer queue pointer. The base address for the receive buffer queue pointer is configured in software using the Receive Buffer Queue Base Address register. Each list entry consists of two words. The first is the address of the receive AHB buffer and the second the receive status. If the length of a receive frame exceeds the AHB buffer length, the status word for the used buffer is written with zeroes except for the “start of frame” bit, which is always set for the first buffer in a frame. Bit zero of the address field is written to 1 to show the buffer has been used. The receive buffer manager then reads the location of the next receive AHB buffer and fills that with the next part of the received frame data. AHB buffers are filled until the frame is complete and the final buffer descriptor status word contains the complete frame status. Refer to Table 37-4 for details of the receive buffer descriptor list. Each receive AHB buffer start location is a word address. The start of the first AHB buffer in a frame can be offset by up to three bytes, depending on the value written to bits 14 and 15 of the Network Configuration register. If the start location of the AHB buffer is offset, the available length of the first AHB buffer is reduced by the corresponding number of bytes. Table 37-4: Bit Receive Buffer Descriptor Entry Function Word 0 31:2 Address of beginning of buffer 1 Wrap—marks last descriptor in receive buffer descriptor list. 0 Ownership—needs to be zero for the GMAC to write data to the receive buffer. The GMAC sets this to one once it has successfully written a frame to memory. Software has to clear this bit before the buffer can be used again. Word 1 31 Global all ones broadcast address detected 30 Multicast hash match 29 Unicast hash match 28 – 27 Specific Address Register match found, bit 25 and bit 26 indicate which Specific Address Register causes the match.  2017 Microchip Technology Inc. DS60001525A-page 955 SAMA5D4 SERIES Table 37-4: Bit Receive Buffer Descriptor Entry (Continued) Function Specific Address Register match. Encoded as follows: 00: Specific Address Register 1 match 26:25 01: Specific Address Register 2 match 10: Specific Address Register 3 match 11: Specific Address Register 4 match If more than one specific address is matched only one is indicated with priority 4 down to 1. This bit has a different meaning depending on whether RX checksum offloading is enabled. With RX checksum offloading disabled: (bit 24 clear in Network Configuration Register) 24 Type ID register match found, bit 22 and bit 23 indicate which type ID register causes the match. With RX checksum offloading enabled: (bit 24 set in Network Configuration Register) 0: The frame was not SNAP encoded and/or had a VLAN tag with the Canonical Format Indicator (CFI) bit set. 1: The frame was SNAP encoded and had either no VLAN tag or a VLAN tag with the CFI bit not set. This bit has a different meaning depending on whether RX checksum offloading is enabled. With RX checksum offloading disabled: (bit 24 clear in Network Configuration) Type ID register match. Encoded as follows: 00: Type ID register 1 match 01: Type ID register 2 match 10: Type ID register 3 match 23:22 11: Type ID register 4 match If more than one Type ID is matched only one is indicated with priority 4 down to 1. With RX checksum offloading enabled: (bit 24 set in Network Configuration Register) 00: Neither the IP header checksum nor the TCP/UDP checksum was checked. 01: The IP header checksum was checked and was correct. Neither the TCP nor UDP checksum was checked. 10: Both the IP header and TCP checksum were checked and were correct. 11: Both the IP header and UDP checksum were checked and were correct. 21 VLAN tag detected—type ID of 0x8100. For packets incorporating the stacked VLAN processing feature, this bit will be set if the second VLAN tag has a type ID of 0x8100 20 Priority tag detected—type ID of 0x8100 and null VLAN identifier. For packets incorporating the stacked VLAN processing feature, this bit will be set if the second VLAN tag has a type ID of 0x8100 and a null VLAN identifier. 19:17 VLAN priority—only valid if bit 21 is set. 16 Canonical format indicator (CFI) bit (only valid if bit 21 is set). 15 End of frame—when set the buffer contains the end of a frame. If end of frame is not set, then the only valid status bit is start of frame (bit 14). 14 Start of frame—when set the buffer contains the start of a frame. If both bits 15 and 14 are set, the buffer contains a whole frame. DS60001525A-page 956  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 37-4: Bit Receive Buffer Descriptor Entry (Continued) Function This bit has a different meaning depending on whether jumbo frames and ignore FCS modes are enabled. If neither mode is enabled this bit will be zero. With jumbo frame mode enabled: (bit 3 set in Network Configuration Register) Additional bit for length of frame (bit[13]), that is concatenated with bits[12:0] 13 With ignore FCS mode enabled and jumbo frames disabled: (bit 26 set in Network Configuration Register and bit 3 clear in Network Configuration Register) This indicates per frame FCS status as follows: 0: Frame had good FCS 1: Frame had bad FCS, but was copied to memory as ignore FCS enabled. These bits represent the length of the received frame which may or may not include FCS depending on whether FCS discard mode is enabled. With FCS discard mode disabled: (bit 17 clear in Network Configuration Register) 12:0 Least significant 12 bits for length of frame including FCS. If jumbo frames are enabled, these 12 bits are concatenated with bit[13] of the descriptor above. With FCS discard mode enabled: (bit 17 set in Network Configuration Register) Least significant 12 bits for length of frame excluding FCS. If jumbo frames are enabled, these 12 bits are concatenated with bit[13] of the descriptor above. To receive frames, the AHB buffer descriptors must be initialized by writing an appropriate address to bits 31:2 in the first word of each list entry. Bit 0 must be written with zero. Bit 1 is the wrap bit and indicates the last entry in the buffer descriptor list. The start location of the receive buffer descriptor list must be written with the receive buffer queue base address before reception is enabled (receive enable in the Network Control register). Once reception is enabled, any writes to the Receive Buffer Queue Base Address register are ignored. When read, it will return the current pointer position in the descriptor list, though this is only valid and stable when receive is disabled. If the filter block indicates that a frame should be copied to memory, the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered. An internal counter within the GMAC represents the receive buffer queue pointer and it is not visible through the CPU interface. The receive buffer queue pointer increments by two words after each buffer has been used. It re-initializes to the receive buffer queue base address if any descriptor has its wrap bit set. As receive AHB buffers are used, the receive AHB buffer manager sets bit zero of the first word of the descriptor to logic one indicating the AHB buffer has been used. Software should search through the “used” bits in the AHB buffer descriptors to find out how many frames have been received, checking the start of frame and end of frame bits. To function properly, a 10/100 Ethernet system should have no excessive length frames or frames greater than 128 bytes with CRC errors. Collision fragments will be less than 128 bytes long, therefore it will be a rare occurrence to find a frame fragment in a receive AHB buffer, when using the default value of 128 bytes for the receive buffers size. If bit zero of the receive buffer descriptor is already set when the receive buffer manager reads the location of the receive AHB buffer, then the buffer has been already used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the “buffer not available” bit in the Receive Status register is set and an interrupt triggered. The Receive Resource Error statistics register is also incremented. 37.6.3.2 Transmit AHB Buffers Frames to transmit are stored in one or more transmit AHB buffers. Transmit frames can be between 1 and 16384 bytes long, so it is possible to transmit frames longer than the maximum length specified in the IEEE 802.3 standard. It should be noted that zero length AHB buffers are allowed and that the maximum number of buffers permitted for each transmit frame is 128.  2017 Microchip Technology Inc. DS60001525A-page 957 SAMA5D4 SERIES The start location for each transmit AHB buffer is stored in memory in a list of transmit buffer descriptors at a location pointed to by the transmit buffer queue pointer. The base address for this queue pointer is set in software using the Transmit Buffer Queue Base Address register. Each list entry consists of two words. The first is the byte address of the transmit buffer and the second containing the transmit control and status. For the FIFO-based DMA configured with a 32-bit data path the address of the buffer is a byte address. Frames can be transmitted with or without automatic CRC generation. If CRC is automatically generated, pad will also be automatically generated to take frames to a minimum length of 64 bytes. When CRC is not automatically generated (as defined in word 1 of the transmit buffer descriptor), the frame is assumed to be at least 64 bytes long and pad is not generated. An entry in the transmit buffer descriptor list is described in Table 37-5. To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits [31:0] in the first word of each descriptor list entry. The second word of the transmit buffer descriptor is initialized with control information that indicates the length of the frame, whether or not the MAC is to append CRC and whether the buffer is the last buffer in the frame. After transmission the status bits are written back to the second word of the first buffer along with the used bit. Bit 31 is the used bit which must be zero when the control word is read if transmission is to take place. It is written to one once the frame has been transmitted. Bits[29:20] indicate various transmit error conditions. Bit 30 is the wrap bit which can be set for any buffer within a frame. If no wrap bit is encountered the queue pointer continues to increment. The Transmit Buffer Queue Base Address register can only be updated while transmission is disabled or halted; otherwise any attempted write will be ignored. When transmission is halted the transmit buffer queue pointer will maintain its value. Therefore when transmission is restarted the next descriptor read from the queue will be from immediately after the last successfully transmitted frame. while transmit is disabled (bit 3 of the Network Control register set low), the transmit buffer queue pointer resets to point to the address indicated by the Transmit Buffer Queue Base Address register. Note that disabling receive does not have the same effect on the receive buffer queue pointer. Once the transmit queue is initialized, transmit is activated by writing to the transmit start bit (bit 9) of the Network Control register. Transmit is halted when a buffer descriptor with its used bit set is read, a transmit error occurs, or by writing to the transmit halt bit of the Network Control register. Transmission is suspended if a pause frame is received while the pause enable bit is set in the Network Configuration register. Rewriting the start bit while transmission is active is allowed. This is implemented with TXGO variable which is readable in the Transmit Status register at bit location 3. The TXGO variable is reset when: • • • • Transmit is disabled. A buffer descriptor with its ownership bit set is read. Bit 10, THALT, of the Network Control register is written. There is a transmit error such as too many retries or a transmit underrun. To set TXGO, write TSTART to the bit 9 of the Network Control register. Transmit halt does not take effect until any ongoing transmit finishes. The DMA transmission will automatically restart from the first buffer of the frame. If a used bit is read midway through transmission of a multi-buffer frame, this is treated as a transmit error. Transmission stops, GTXER is asserted and the FCS will be bad. If transmission stops due to a transmit error or a used bit being read, transmission restarts from the first buffer descriptor of the frame being transmitted when the transmit start bit is rewritten. Table 37-5: Bit Transmit Buffer Descriptor Entry Function Word 0 31:0 Byte address of buffer Word 1 31 Used—must be zero for the GMAC to read data to the transmit buffer. The GMAC sets this to one for the first buffer of a frame once it has been successfully transmitted. Software must clear this bit before the buffer can be used again. 30 Wrap—marks last descriptor in transmit buffer descriptor list. This can be set for any buffer within the frame. 29 Retry limit exceeded, transmit error detected 28 Transmit underrun—occurs when the start of packet data has been written into the FIFO and either HRESP is not OK, or the transmit data could not be fetched in time, or when buffers are exhausted. DS60001525A-page 958  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 37-5: Transmit Buffer Descriptor Entry (Continued) Bit Function 27 Transmit frame corruption due to AHB error—set if an error occurs while midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and GTXER asserted). 26 Late collision, transmit error detected. 25:23 Reserved Transmit IP/TCP/UDP checksum generation offload errors: 000: No Error. 001: The Packet was identified as a VLAN type, but the header was not fully complete, or had an error in it. 010: The Packet was identified as a SNAP type, but the header was not fully complete, or had an error in it. 22:20 011: The Packet was not of an IP type, or the IP packet was invalidly short, or the IP was not of type IPv4/IPv6. 100: The Packet was not identified as VLAN, SNAP or IP. 101: Non supported packet fragmentation occurred. For IPv4 packets, the IP checksum was generated and inserted. 110: Packet type detected was not TCP or UDP. TCP/UDP checksum was therefore not generated. For IPv4 packets, the IP checksum was generated and inserted. 111: A premature end of packet was detected and the TCP/UDP checksum could not be generated. 19:17 Reserved No CRC to be appended by MAC. When set, this implies that the data in the buffers already contains a valid CRC, hence no CRC or padding is to be appended to the current frame by the MAC. 16 This control bit must be set for the first buffer in a frame and will be ignored for the subsequent buffers of a frame. Note that this bit must be clear when using the transmit IP/TCP/UDP checksum generation offload, otherwise checksum generation and substitution will not occur. 15 Last buffer, when set this bit will indicate the last buffer in the current frame has been reached. 14 Reserved 13:0 37.6.3.3 Length of buffer DMA Bursting on the AHB The DMA will always use SINGLE, or INCR type AHB accesses for buffer management operations. When performing data transfers, the AHB burst length used can be programmed using bits 4:0 of the DMA Configuration register so that either SINGLE, INCR or fixed length incrementing bursts (INCR4, INCR8 or INCR16) are used where possible. When there is enough space and enough data to be transferred, the programmed fixed length bursts will be used. If there is not enough data or space available, for example when at the beginning or the end of a buffer, SINGLE type accesses are used. Also SINGLE type accesses are used at 1024 byte boundaries, so that the 1 Kbyte boundaries are not burst over as per AHB requirements. The DMA will not terminate a fixed length burst early, unless an error condition occurs on the AHB or if receive or transmit are disabled in the Network Control register. 37.6.4 MAC Transmit Block The MAC transmitter can operate in either half duplex or full duplex mode and transmits frames in accordance with the Ethernet IEEE 802.3 standard. In half duplex mode, the CSMA/CD protocol of the IEEE 802.3 specification is followed. A small input buffer receives data through the FIFO interface which will extract data in 32-bit form. All subsequent processing prior to the final output is performed in bytes. Transmit data can be output using the MII interface. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO interface a word at a time. If necessary, padding is added to take the frame length to 60 bytes. CRC is calculated using an order 32-bit polynomial. This is inverted and appended to the end of the frame taking the frame length to a minimum of 64 bytes. If the no CRC bit is set in the second word of the last buffer descriptor of a transmit frame, neither pad nor CRC are appended. The no CRC bit can also be set through the FIFO interface.  2017 Microchip Technology Inc. DS60001525A-page 959 SAMA5D4 SERIES In full duplex mode (at all data rates), frames are transmitted immediately. Back to back frames are transmitted at least 96 bit times apart to guarantee the interframe gap. In half duplex mode, the transmitter checks carrier sense. If asserted, the transmitter waits for the signal to become inactive, and then starts transmission after the interframe gap of 96 bit times. If the collision signal is asserted during transmission, the transmitter will transmit a jam sequence of 32 bits taken from the data register and then retry transmission after the backoff time has elapsed. If the collision occurs during either the preamble or Start Frame Delimiter (SFD), then these fields will be completed prior to generation of the jam sequence. The backoff time is based on an XOR of the 10 least significant bits of the data coming from the transmit FIFO interface and a 10-bit pseudo random number generator. The number of bits used depends on the number of collisions seen. After the first collision 1 bit is used, then the second 2 bits and so on up to the maximum of 10 bits. All 10 bits are used above ten collisions. An error will be indicated and no further attempts will be made if 16 consecutive attempts cause collision. This operation is compliant with the description in Clause 4.2.3.2.5 of the IEEE 802.3 standard which refers to the truncated binary exponential backoff algorithm. In 10/100 mode, both collisions and late collisions are treated identically, and backoff and retry will be performed up to 16 times. This condition is reported in the transmit buffer descriptor word 1 (late collision, bit 26) and also in the Transmit Status register (late collision, bit 7). An interrupt can also be generated (if enabled) when this exception occurs, and bit 5 in the Interrupt Status register will be set. In all modes of operation, if the transmit DMA underruns, a bad CRC is automatically appended using the same mechanism as jam insertion and the GTXER signal is asserted. For a properly configured system this should never happen. By setting when bit 28 is set in the Network Configuration register, the Inter Packet Gap (IPG) may be stretched beyond 96 bits depending on the length of the previously transmitted frame and the value written to the IPG Stretch register (GMAC_IPGS). The least significant 8 bits of the IPG Stretch register multiply the previous frame length (including preamble). The next significant 8 bits (+1 so as not to get a divide by zero) divide the frame length to generate the IPG. IPG stretch only works in full duplex mode and when bit 28 is set in the Network Configuration register. The IPG Stretch register cannot be used to shrink the IPG below 96 bits. If the back pressure bit is set in the Network Control register, or if the HDFC configuration bit is set in the GMAC_UR register (10M or 100M half duplex mode), the transmit block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit rate mode 64 1s, whenever it sees an incoming frame to force a collision. This provides a way of implementing flow control in half duplex mode. 37.6.5 MAC Receive Block All processing within the MAC receive block is implemented using a 16-bit data path. The MAC receive block checks for valid preamble, FCS, alignment and length, presents received frames to the FIFO interface and stores the frame destination address for use by the address checking block. If, during the frame reception, the frame is found to be too long, a bad frame indication is sent to the FIFO interface. The receiver logic ceases to send data to memory as soon as this condition occurs. At end of frame reception the receive block indicates to the DMA block whether the frame is good or bad. The DMA block will recover the current receive buffer if the frame was bad. Ethernet frames are normally stored in DMA memory complete with the FCS. Setting the FCS remove bit in the network configuration (bit 17) causes frames to be stored without their corresponding FCS. The reported frame length field is reduced by four bytes to reflect this operation. The receive block signals to the register block to increment the alignment, CRC (FCS), short frame, long frame, jabber or receive symbol errors when any of these exception conditions occur. If bit 26 is set in the network configuration, CRC errors will be ignored and CRC errored frames will not be discarded, though the Frame Check Sequence Errors statistic register will still be incremented. Additionally, if not enabled for jumbo frames mode, then bit[13] of the receiver descriptor word 1 will be updated to indicate the FCS validity for the particular frame. This is useful for applications such as EtherCAT whereby individual frames with FCS errors must be identified. Received frames can be checked for length field error by setting the length field error frame discard bit of the Network Configuration register (bit-16). When this bit is set, the receiver compares a frame's measured length with the length field (bytes 13 and 14) extracted from the frame. The frame is discarded if the measured length is shorter. This checking procedure is for received frames between 64 bytes and 1518 bytes in length. Each discarded frame is counted in the 10-bit Length Field Frame Error statistics register. Frames where the length field is greater than or equal to 0x0600 hex will not be checked. DS60001525A-page 960  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.6.6 Checksum Offload for IP, TCP and UDP The GMAC can be programmed to perform IP, TCP and UDP checksum offloading in both receive and transmit directions, which is enabled by setting bit 24 in the Network Configuration register for receive. IPv4 packets contain a 16-bit checksum field, which is the 16-bit 1’s complement of the 1’s complement sum of all 16-bit words in the header. TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit 1’s complement of the 1’s complement sum of all 16bit words in the header, the data and a conceptual IP pseudo header. To calculate these checksums in software requires each byte of the packet to be processed. For TCP and UDP this can use a large amount of processing power. Offloading the checksum calculation to hardware can result in significant performance improvements. For IP, TCP or UDP checksum offload to be useful, the operating system containing the protocol stack must be aware that this offload is available so that it can make use of the fact that the hardware can either generate or verify the checksum. 37.6.6.1 Receiver Checksum Offload When receive checksum offloading is enabled in the GMAC, the IPv4 header checksum is checked as per RFC 791, where the packet meets the following criteria: • • • • If present, the VLAN header must be four octets long and the CFI bit must not be set. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP Encoding. IPv4 packet IP header is of a valid length The GMAC also checks the TCP checksum as per RFC 793, or the UDP checksum as per RFC 768, if the following criteria are met: • • • • IPv4 or IPv6 packet Good IP header checksum (if IPv4) No IP fragmentation TCP or UDP packet When an IP, TCP or UDP frame is received, the receive buffer descriptor gives an indication if the GMAC was able to verify the checksums. There is also an indication if the frame had SNAP encapsulation. These indication bits will replace the type ID match indication bits when the receive checksum offload is enabled. For details of these indication bits refer to Table 37-4 “Receive Buffer Descriptor Entry”. If any of the checksums are verified as incorrect by the GMAC, the packet is discarded and the appropriate statistics counter incremented. 37.6.7 MAC Filtering Block The filter block determines which frames should be written to the FIFO interface and on to the DMA. Whether a frame is passed depends on what is enabled in the Network Configuration register, the state of the external matching pins, the contents of the specific address, type and Hash registers and the frame's destination address and type field. If bit 25 of the Network Configuration register is not set, a frame will not be copied to memory if the GMAC is transmitting in half duplex mode at the time a destination address is received. Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes (48 bits) of an Ethernet frame make up the destination address. The first bit of the destination address, which is the LSB of the first byte of the frame, is the group or individual bit. This is one for multicast addresses and zero for unicast. The all ones address is the broadcast address and a special case of multicast. The GMAC supports recognition of four specific addresses. Each specific address requires two registers, Specific Address Bottom register and Specific Address Top register. Specific Address Bottom register stores the first four bytes of the destination address and Specific Address Top register contains the last two bytes. The addresses stored can be specific, group, local or universal. The destination address of received frames is compared against the data stored in the Specific Address registers once they have been activated. The addresses are deactivated at reset or when their corresponding Specific Address Bottom register is written. They are activated when Specific Address Top register is written. If a receive frame address matches an active address, the frame is written to the FIFO interface and on to DMA memory. Frames may be filtered using the type ID field for matching. Four type ID registers exist in the register address space and each can be enabled for matching by writing a one to the MSB (bit 31) of the respective register. When a frame is received, the matching is implemented as an OR function of the various types of match. The contents of each type ID register (when enabled) are compared against the length/type ID of the frame being received (e.g., bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and copied to memory if a match is found. The encoded type ID match bits (Word 0, Bit 22 and Bit 23) in the receive buffer descriptor status are set indicating which type ID register generated the match, if the receive checksum offload is disabled. The reset state of the type ID registers is zero, hence each is initially disabled.  2017 Microchip Technology Inc. DS60001525A-page 961 SAMA5D4 SERIES The following example illustrates the use of the address and type ID match registers for a MAC address of 21:43:65:87:A9:CB: Preamble 55 SFD D5 DA (Octet 0 - LSB) 21 DA (Octet 1) 43 DA (Octet 2) 65 DA (Octet 3) 87 DA (Octet 4) A9 DA (Octet 5 - MSB) CB SA (LSB) ) SA ) SA ) SA ) SA ) SA (MSB) ) Type ID (MSB) 43 Type ID (LSB) 21 00(1 00(1 00(1 00(1 00(1 00(1 Note 1: Contains the address of the transmitting device The sequence above shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom as shown. For a successful match to specific address 1, the following address matching registers must be set up: Specific Address 1 Bottom register (GMAC_SAB1) (Address 0x088) 0x87654321 Specific Address 1 Top register (GMAC_SAT1) (Address 0x08C) 0x0000CBA9 For a successful match to the type ID, the following Type ID Match 1 register must be set up: Type ID Match 1 register (GMAC_TIDM1) (Address 0x0A8) 37.6.8 0x80004321 Broadcast Address Frames with the broadcast address of 0xFFFFFFFFFFFF are stored to memory only if the 'no broadcast' bit in the Network Configuration register is set to zero. 37.6.9 Hash Addressing The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in Hash Register Bottom and the most significant bits in Hash Register Top. The unicast hash enable and the multicast hash enable bits in the Network Configuration register enable the reception of hash matched frames. The destination address is reduced to a 6-bit index into the 64-bit Hash register using the following hash function: The hash function is an XOR of every sixth bit of the destination address. DS60001525A-page 962  2017 Microchip Technology Inc. SAMA5D4 SERIES hash_index[05] hash_index[04] hash_index[03] hash_index[02] hash_index[01] hash_index[00] = = = = = = da[05] da[04] da[03] da[02] da[01] da[00] ^ ^ ^ ^ ^ ^ da[11] da[10] da[09] da[08] da[07] da[06] ^ ^ ^ ^ ^ ^ da[17] da[16] da[15] da[14] da[13] da[12] ^ ^ ^ ^ ^ ^ da[23] da[22] da[21] da[20] da[19] da[18] ^ ^ ^ ^ ^ ^ da[29] da[28] da[27] da[26] da[25] da[24] ^ ^ ^ ^ ^ ^ da[35] da[34] da[33] da[32] da[31] da[30] ^ ^ ^ ^ ^ ^ da[41] da[40] da[39] da[38] da[37] da[36] ^ ^ ^ ^ ^ ^ da[47] da[46] da[45] da[44] da[43] da[42] da[0] represents the least significant bit of the first byte received, that is, the multicast/unicast indicator, and da[47] represents the most significant bit of the last byte received. If the hash index points to a bit that is set in the Hash register then the frame will be matched according to whether the frame is multicast or unicast. A multicast match will be signalled if the multicast hash enable bit is set, da[0] is logic 1 and the hash index points to a bit set in the Hash register. A unicast match will be signalled if the unicast hash enable bit is set, da[0] is logic 0 and the hash index points to a bit set in the Hash register. To receive all multicast frames, the Hash register should be set with all ones and the multicast hash enable bit should be set in the Network Configuration register. 37.6.10 Copy all Frames (Promiscuous Mode) If the Copy All Frames bit is set in the Network Configuration register then all frames (except those that are too long, too short, have FCS errors or have GRXER asserted during reception) will be copied to memory. Frames with FCS errors will be copied if bit 26 is set in the Network Configuration register. 37.6.11 Disable Copy of Pause Frames Pause frames can be prevented from being written to memory by setting the disable copying of pause frames control bit 23 in the Network Configuration register. When set, pause frames are not copied to memory regardless of the Copy All Frames bit, whether a hash match is found, a type ID match is identified or if a destination address match is found. 37.6.12 VLAN Support The following table describes an Ethernet encoded 802.1Q VLAN tag. Table 37-6: 802.1Q VLAN Tag TPID (Tag Protocol Identifier) 16 bits TCI (Tag Control Information) 16 bits 0x8100 First 3 bits priority, then CFI bit, last 12 bits VID The VLAN tag is inserted at the 13th byte of the frame adding an extra four bytes to the frame. To support these extra four bytes, the GMAC can accept frame lengths up to 1536 bytes by setting bit 8 in the Network Configuration register. If the VID (VLAN identifier) is null (0x000) this indicates a priority-tagged frame. The following bits in the receive buffer descriptor status word give information about VLAN tagged frames:• • • • Bit 21 set if receive frame is VLAN tagged (i.e., type ID of 0x8100). Bit 20 set if receive frame is priority tagged (i.e., type ID of 0x8100 and null VID). (If bit 20 is set, bit 21 will be set also.) Bit 19, 18 and 17 set to priority if bit 21 is set. Bit 16 set to CFI if bit 21 is set. The GMAC can be configured to reject all frames except VLAN tagged frames by setting the discard non-VLAN frames bit in the Network Configuration register. 37.6.13 Wake on LAN Support The receive block supports Wake on LAN by detecting the following events on incoming receive frames: • • • • Magic packet Address Resolution Protocol (ARP) request to the device IP address Specific address 1 filter match Multicast hash filter match  2017 Microchip Technology Inc. DS60001525A-page 963 SAMA5D4 SERIES These events can be individually enabled through bits [19:16] of the Wake on LAN register. Also, for Wake on LAN detection to occur, receive enable must be set in the Network Control register, however a receive buffer does not have to be available. In case of an ARP request, specific address 1 or multicast filter events will occur even if the frame is errored. For magic packet events, the frame must be correctly formed and error free. A magic packet event is detected if all of the following are true: • • • • • Magic packet events are enabled through bit 16 of the Wake on LAN register The frame's destination address matches specific address 1 The frame is correctly formed with no errors The frame contains at least 6 bytes of 0xFF for synchronization There are 16 repetitions of the contents of Specific Address 1 register immediately following the synchronization An ARP request event is detected if all of the following are true: • • • • • • ARP request events are enabled through bit 17 of the Wake on LAN register Broadcasts are allowed by bit 5 in the Network Configuration register The frame has a broadcast destination address (bytes 1 to 6) The frame has a type ID field of 0x0806 (bytes 13 and 14) The frame has an ARP operation field of 0x0001 (bytes 21 and 22) The least significant 16 bits of the frame's ARP target protocol address (bytes 41 and 42) match the value programmed in bits[15:0] of the Wake on LAN register The decoding of the ARP fields adjusts automatically if a VLAN tag is detected within the frame. The reserved value of 0x0000 for the Wake on LAN target address value will not cause an ARP request event, even if matched by the frame. A specific address 1 filter match event will occur if all of the following are true: • Specific address 1 events are enabled through bit 18 of the Wake on LAN register • The frame's destination address matches the value programmed in the Specific Address 1 registers A multicast filter match event will occur if all of the following are true: • • • • Multicast hash events are enabled through bit 19 of the Wake on LAN register Multicast hash filtering is enabled through bit 6 of the Network Configuration register The frame destination address matches against the multicast hash filter The frame destination address is not a broadcast 37.6.14 IEEE 1588 Support IEEE 1588 is a standard for precision time synchronization in local area networks. It works with the exchange of special Precision Time Protocol (PTP) frames. The PTP messages can be transported over IEEE 802.3/Ethernet, over Internet Protocol Version 4 or over Internet Protocol Version 6 as described in the annex of IEEE P1588.D2.1. The GMAC indicates the message timestamp point (asserted on the start packet delimiter and de-asserted at end of frame) for all frames and the passage of PTP event frames (asserted when a PTP event frame is detected and de-asserted at end of frame). IEEE 802.1AS is a subset of IEEE 1588. One difference is that IEEE 802.1AS uses the Ethernet multicast address 0180C200000E for sync frame recognition whereas IEEE 1588 does not. GMAC is designed to recognize sync frames with both IEEE 802.1AS and IEEE 1588 addresses and so can support both 1588 and 802.1AS frame recognition simultaneously. Synchronization between master and slave clocks is a two stage process. First, the offset between the master and slave clocks is corrected by the master sending a sync frame to the slave with a follow up frame containing the exact time the sync frame was sent. Hardware assist modules at the master and slave side detect exactly when the sync frame was sent by the master and received by the slave. The slave then corrects its clock to match the master clock. Second, the transmission delay between the master and slave is corrected. The slave sends a delay request frame to the master which sends a delay response frame in reply. Hardware assist modules at the master and slave side detect exactly when the delay request frame was sent by the slave and received by the master. The slave will now have enough information to adjust its clock to account for delay. For example, if the slave was assuming zero delay, the actual delay will be half the difference between the transmit and receive time of the delay request frame (assuming equal transmit and receive times) because the slave clock will be lagging the master clock by the delay time already. The timestamp is taken when the message timestamp point passes the clock timestamp point. This can generate an interrupt if enabled (GMAC_IER). However, MAC Filtering configuration is needed to actually ‘copy’ the message to memory. For Ethernet, the message timestamp point is the SFD and the clock timestamp point is the MII interface. (The IEEE 1588 specification refers to sync and delay_req mes- DS60001525A-page 964  2017 Microchip Technology Inc. SAMA5D4 SERIES sages as event messages as these require timestamping. These events are captured in the registers GMAC_EFTx and GMAC_EFRx, respectively. Follow up, delay response and management messages do not require timestamping and are referred to as general messages.) 1588 version 2 defines two additional PTP event messages. These are the peer delay request (Pdelay_Req) and peer delay response (Pdelay_Resp) messages. These events are captured in the registers GMAC_PEFTx and GMAC_PEFRx, respectively. These messages are used to calculate the delay on a link. Nodes at both ends of a link send both types of frames (regardless of whether they contain a master or slave clock). The Pdelay_Resp message contains the time at which a Pdelay_Req was received and is itself an event message. The time at which a Pdelay_Resp message is received is returned in a Pdelay_Resp_Follow_Up message. 1588 version 2 introduces transparent clocks of which there are two kinds, peer-to-peer (P2P) and end-to-end (E2E). Transparent clocks measure the transit time of event messages through a bridge and amend a correction field within the message to allow for the transit time. P2P transparent clocks additionally correct for the delay in the receive path of the link using the information gathered from the peer delay frames. With P2P transparent clocks delay_req messages are not used to measure link delay. This simplifies the protocol and makes larger systems more stable. The GMAC recognizes four different encapsulations for PTP event messages: 1. 2. 3. 4. 1588 version 1 (UDP/IPv4 multicast) 1588 version 2 (UDP/IPv4 multicast) 1588 version 2 (UDP/IPv6 multicast) 1588 version 2 (Ethernet multicast) Table 37-7: Example of Sync Frame in 1588 Version 1 Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — Type (Octets 12–13) 0800 IP stuff (Octets 14–22) — UDP (Octet 23) 11 IP stuff (Octets 24–29) — IP DA (Octets 30–32) E00001 IP DA (Octet 33) 81 or 82 or 83 or 84 Source IP port (Octets 34–35) — Dest IP port (Octets 36–37) 013F Other stuff (Octets 38–42) — Version PTP (Octet 43) 01 Other stuff (Octets 44–73) — Control (Octet 74) 00 Other stuff (Octets 75–168) —  2017 Microchip Technology Inc. DS60001525A-page 965 SAMA5D4 SERIES Table 37-8: Example of Delay Request Frame in 1588 Version 1 Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — Type (Octets 12–13) 0800 IP stuff (Octets 14–22) — UDP (Octet 23) 11 IP stuff (Octets 24–29) — IP DA (Octets 30–32) E00001 IP DA (Octet 33) 81 or 82 or 83 or 84 Source IP port (Octets 34–35) — Dest IP port (Octets 36–37) 013F Other stuff (Octets 38–42) — Version PTP (Octet 43) 01 Other stuff (Octets 44–73) — Control (Octet 74) 01 Other stuff (Octets 75–168) — For 1588 version 1 messages, sync and delay request frames are indicated by the GMAC if the frame type field indicates TCP/IP, UDP protocol is indicated, the destination IP address is 224.0.1.129/130/131 or 132, the destination UDP port is 319 and the control field is correct. The control field is 0x00 for sync frames and 0x01 for delay request frames. For 1588 version 2 messages, the type of frame is determined by looking at the message type field in the first byte of the PTP frame. Whether a frame is version 1 or version 2 can be determined by looking at the version PTP field in the second byte of both version 1 and version 2 PTP frames. In version 2 messages sync frames have a message type value of 0x0, delay_req have 0x1, Pdelay_Req have 0x2 and Pdelay_Resp have 0x3. Table 37-9: Example of Sync Frame in 1588 Version 2 (UDP/IPv4) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — Type (Octets 12–13) 0800 IP stuff (Octets 14–22) — UDP (Octet 23) 11 IP stuff (Octets 24–29) — IP DA (Octets 30–33) E0000181 Source IP port (Octets 34–35) — Dest IP port (Octets 36–37) 013F DS60001525A-page 966  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 37-9: Example of Sync Frame in 1588 Version 2 (UDP/IPv4) Format (Continued) Frame Segment Value Other stuff (Octets 38–41) — Message type (Octet 42) 00 Version PTP (Octet 43) 02 Table 37-10: Example of Pdelay_Req Frame in 1588 Version 2 (UDP/IPv4) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — Type (Octets 12–13) 0800 IP stuff (Octets 14–22) — UDP (Octet 23) 11 IP stuff (Octets 24–29) — IP DA (Octets 30–33) E000006B Source IP port (Octets 34–35) — Dest IP port (Octets 36–37) 013F Other stuff (Octets 38–41) — Message type (Octet 42) 02 Version PTP (Octet 43) 02 Table 37-11: Example of Sync Frame in 1588 Version 2 (UDP/IPv6) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — Type (Octets 12–13) 86dd IP stuff (Octets 14–19) — UDP (Octet 20) 11 IP stuff (Octets 21–37) — IP DA (Octets 38–53) FF0X00000000018 Source IP port (Octets 54–55) — Dest IP port (Octets 56–57) 013F Other stuff (Octets 58–61) — Message type (Octet 62) 00 Other stuff (Octets 63–93) —  2017 Microchip Technology Inc. DS60001525A-page 967 SAMA5D4 SERIES Table 37-11: Example of Sync Frame in 1588 Version 2 (UDP/IPv6) Format (Continued) Frame Segment Value Version PTP (Octet 94) 02 Table 37-12: Example of Pdelay_Resp Frame in 1588 Version 2 (UDP/IPv6) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) — SA (Octets 6–11) — Type (Octets 12–13) 86dd IP stuff (Octets 14–19) — UDP (Octet 20) 11 IP stuff (Octets 21–37) — IP DA (Octets 38–53) FF0200000000006B Source IP port (Octets 54–55) — Dest IP port (Octets 56–57) 013F Other stuff (Octets 58–61) — Message type (Octet 62) 03 Other stuff (Octets 63–93) — Version PTP (Octet 94) 02 For the multicast address 011B19000000 sync and delay request frames are recognized depending on the message type field, 00 for sync and 01 for delay request. Table 37-13: Example of Sync Frame in 1588 Version 2 (Ethernet Multicast) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) 011B19000000 SA (Octets 6–11) — Type (Octets 12–13) 88F7 Message type (Octet 14) 00 Version PTP (Octet 15) 02 Pdelay request frames need a special multicast address so they can pass through ports blocked by the spanning tree protocol. For the multicast address 0180C200000E sync, Pdelay_Req and Pdelay_Resp frames are recognized depending on the message type field, 00 for sync, 02 for pdelay request and 03 for pdelay response. DS60001525A-page 968  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 37-14: Example of Pdelay_Req Frame in 1588 Version 2 (Ethernet Multicast) Format Frame Segment Value Preamble/SFD 55555555555555D5 DA (Octets 0–5) 0180C200000E SA (Octets 6–11) — Type (Octets 12–13) 88F7 Message type (Octet 14) 00 Version PTP (Octet 15) 02 37.6.15 Time Stamp Unit The TSU consists of a timer and registers to capture the time at which PTP event frames cross the message timestamp point. An interrupt is issued when a capture register is updated. The timer is implemented as a 94-bit register with the upper 48 bits counting seconds, the next 30 bits counting nanoseconds and the lowest 16 bits counting sub-nanoseconds. The lower 46 bits rolls over when they have counted to one second. An interrupt is generated when the seconds increment. The timer value can be read, written and adjusted through the APB interface. The timer is clocked by MCK. The amount by which the timer increments each clock cycle is controlled by the timer increment registers (GMAC_TI). Bits 7:0 are the default increment value in nanoseconds and an additional 16 bits of sub-nanosecond resolution are available using the Timer Increment Sub-nanoseconds register (GMAC_TISUBN). If the rest of the register is written with zero, the timer increments by the value in [7:0], plus the value of GMAC_TISUBN, each clock cycle. The GMAC_TISUBN register allows a resolution of approximately 15 femtoseconds. Bits 15:8 of the increment register are the alternative increment value in nanoseconds and bits 23:16 are the number of increments after which the alternative increment value is used. If 23:16 are zero then the alternative increment value will never be used. Taking the example of 10.2 MHz, there are 102 cycles every ten microseconds or 51 every five microseconds. So a timer with a 10.2 MHz clock source is constructed by incrementing by 98 ns for fifty cycles and then incrementing by 100 ns (98 × 50 + 100 = 5000). This is programmed by setting the 1588 Timer Increment register to 0x00326462. For a 49.8 MHz clock source it would be 20 ns for 248 cycles followed by an increment of 40 ns (20 × 248 + 40 = 5000) programmed as 0x00F82814. Having eight bits for the “number of increments” field allows frequencies up to 50 MHz to be supported with 200 kHz resolution. Without the alternative increment field the period of the clock would be limited to an integer number of nanoseconds, resulting in supported clock frequencies of 8, 10, 20, 25, 40, 50, 100, 125, 200 and 250 MHz. There are eight additional 80-bit registers that capture the time at which PTP event frames are transmitted and received. An interrupt is issued when these registers are updated. The TSU timer count value can be compared to a programmable comparison value. For the comparison, the 48 bits of the seconds value and the upper 22 bits of the nanoseconds value are used. An interrupt can also be generated (if enabled) when the TSU timer count value and comparison value are equal, mapped to bit 29 of the Interrupt Status register. 37.6.16 Note: MAC 802.3 Pause Frame Support Refer to Clause 31, and Annex 31A and 31B of the IEEE standard 802.3 for a full description of MAC 802.3 pause operation. The following table shows the start of a MAC 802.3 pause frame. Table 37-15: Start of an 802.3 Pause Frame Address Destination Source Type (MAC Control Frame) 0x0180C2000001 6 bytes 0x8808 Pause Opcode Time 0x0001 2 bytes The GMAC supports both hardware controlled pause of the transmitter, upon reception of a pause frame, and hardware generated pause frame transmission.  2017 Microchip Technology Inc. DS60001525A-page 969 SAMA5D4 SERIES 37.6.16.1 802.3 Pause Frame Reception Bit 13 of the Network Configuration register is the pause enable control for reception. If this bit is set, transmission pauses if a non zero pause quantum frame is received. If a valid pause frame is received, then the Pause Time register is updated with the new frame's pause time, regardless of whether a previous pause frame is active or not. An interrupt (either bit 12 or bit 13 of the Interrupt Status register) is triggered when a pause frame is received, but only if the interrupt has been enabled (bit 12 and bit 13 of the Interrupt Mask register). Pause frames received with non zero quantum are indicated through the interrupt bit 12 of the Interrupt Status register. Pause frames received with zero quantum are indicated on bit 13 of the Interrupt Status register. Once the Pause Time register is loaded and the frame currently being transmitted has been sent, no new frames are transmitted until the pause time reaches zero. The loading of a new pause time, and hence the pausing of transmission, only occurs when the GMAC is configured for full duplex operation. If the GMAC is configured for half duplex there will be no transmission pause, but the pause frame received interrupt will still be triggered. A valid pause frame is defined as having a destination address that matches either the address stored in Specific Address 1 register or if it matches the reserved address of 0x0180C2000001. It must also have the MAC control frame type ID of 0x8808 and have the pause opcode of 0x0001. Pause frames that have frame check sequence (FCS) or other errors will be treated as invalid and will be discarded. 802.3 Pause frames that are received after Priority-based Flow Control (PFC) has been negotiated will also be discarded. Valid pause frames received will increment the Pause Frames Received statistic register. The Pause Time register decrements every 512 bit times once transmission has stopped. For test purposes, the retry test bit can be set (bit 12 in the Network Configuration register) which causes the Pause Time register to decrement every GTXCK cycle once transmission has stopped. The interrupt (bit 13 in the Interrupt Status register) is asserted whenever the Pause Time register decrements to zero (assuming it has been enabled by bit 13 in the Interrupt Mask register). This interrupt is also set when a zero quantum pause frame is received. 37.6.16.2 802.3 Pause Frame Transmission Automatic transmission of pause frames is supported through the transmit pause frame bits of the Network Control register. If either bit 11 or bit 12 of the Network Control register is written with logic 1, an 802.3 pause frame will be transmitted, providing full duplex is selected in the Network Configuration register and the transmit block is enabled in the Network Control register. Pause frame transmission will happen immediately if transmit is inactive or if transmit is active between the current frame and the next frame due to be transmitted. Transmitted pause frames comprise the following: • • • • • • • A destination address of 01-80-C2-00-00-01 A source address taken from Specific Address 1 register A type ID of 88-08 (MAC control frame) A pause opcode of 00-01 A Pause Quantum register Fill of 00 to take the frame to minimum frame length Valid FCS The pause quantum used in the generated frame will depend on the trigger source for the frame as follows: • If bit 11 is written with a one, the pause quantum will be taken from the Transmit Pause Quantum register. The Transmit Pause Quantum register resets to a value of 0xFFFF giving maximum pause quantum as default. • If bit 12 is written with a one, the pause quantum will be zero. After transmission, a pause frame transmitted interrupt will be generated (bit 14 of the Interrupt Status register) and the only the statistics register Pause Frames Transmitted is incremented. Pause frames can also be transmitted by the MAC using normal frame transmission methods. 37.6.17 Note: MAC PFC Priority-based Pause Frame Support Refer to the 802.1Qbb standard for a full description of priority-based pause operation. The following table shows the start of a Priority-based Flow Control (PFC) pause frame. DS60001525A-page 970  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 37-16: Start of a PFC Pause Frame Address Destination Source Type (Mac Control Frame) Pause Opcode Priority Enable Vector Pause Time 0x0180C2000001 6 bytes 0x8808 0x1001 2 bytes 8 × 2 bytes The GMAC supports PFC priority-based pause transmission and reception. Before PFC pause frames can be received, bit 16 of the Network Control register must be set. 37.6.17.1 PFC Pause Frame Reception The ability to receive and decode priority-based pause frames is enabled by setting bit 16 of the Network Control register. When this bit is set, the GMAC will match either classic 802.3 pause frames or PFC priority-based pause frames. Once a priority-based pause frame has been received and matched, then from that moment on the GMAC will only match on priority-based pause frames (this is an 802.1Qbb requirement, known as PFC negotiation). Once priority-based pause has been negotiated, any received 802.3x format pause frames will not be acted upon. If a valid priority-based pause frame is received then the GMAC will decode the frame and determine which, if any, of the eight priorities require to be paused. Up to eight Pause Time registers are then updated with the eight pause times extracted from the frame regardless of whether a previous pause operation is active or not. An interrupt (either bit 12 or bit 13 of the Interrupt Status register) is triggered when a pause frame is received, but only if the interrupt has been enabled (bit 12 and bit 13 of the Interrupt Mask register). Pause frames received with non zero quantum are indicated through the interrupt bit 12 of the Interrupt Status register. Pause frames received with zero quantum are indicated on bit 13 of the Interrupt Status register. The loading of a new pause time only occurs when the GMAC is configured for full duplex operation. If the GMAC is configured for half duplex, the pause time counters will not be loaded, but the pause frame received interrupt will still be triggered. A valid pause frame is defined as having a destination address that matches either the address stored in Specific Address 1 register or if it matches the reserved address of 0x0180C2000001. It must also have the MAC control frame type ID of 0x8808 and have the pause opcode of 0x0101. Pause frames that have frame check sequence (FCS) or other errors will be treated as invalid and will be discarded. Valid pause frames received will increment the Pause Frames Received Statistic register. The Pause Time registers decrement every 512 bit times immediately following the PFC frame reception. For test purposes, the retry test bit can be set (bit 12 in the Network Configuration register) which causes the Pause Time register to decrement every GRXCK cycle once transmission has stopped. The interrupt (bit 13 in the Interrupt Status register) is asserted whenever the Pause Time register decrements to zero (assuming it has been enabled by bit 13 in the Interrupt Mask register). This interrupt is also set when a zero quantum pause frame is received. 37.6.17.2 PFC Pause Frame Transmission Automatic transmission of pause frames is supported through the transmit priority-based pause frame bit of the Network Control register. If bit 17 of the Network Control register is written with logic 1, a PFC pause frame will be transmitted providing full duplex is selected in the Network Configuration register and the transmit block is enabled in the Network Control register. When bit 17 of the Network Control register is set, the fields of the priority-based pause frame will be built using the values stored in the Transmit PFC Pause register. Pause frame transmission will happen immediately if transmit is inactive or if transmit is active between the current frame and the next frame due to be transmitted. Transmitted pause frames comprise the following: • • • • • • • • A destination address of 01-80-C2-00-00-01 A source address taken from Specific Address 1 register A type ID of 88-08 (MAC control frame) A pause opcode of 01-01 A priority enable vector taken from Transmit PFC Pause register 8 Pause Quantum registers Fill of 00 to take the frame to minimum frame length Valid FCS  2017 Microchip Technology Inc. DS60001525A-page 971 SAMA5D4 SERIES The Pause Quantum registers used in the generated frame will depend on the trigger source for the frame as follows: • If bit 17 of the Network Control register is written with a one, then the priority enable vector of the priority-based pause frame will be set equal to the value stored in the Transmit PFC Pause register [7:0]. For each entry equal to zero in the Transmit PFC Pause register [15:8], the pause quantum field of the pause frame associated with that entry will be taken from the Transmit Pause Quantum register. For each entry equal to one in the Transmit PFC Pause register [15:8], the pause quantum associated with that entry will be zero. • The Transmit Pause Quantum register resets to a value of 0xFFFF giving maximum pause quantum as default. After transmission, a pause frame transmitted interrupt will be generated (bit 14 of the Interrupt Status register) and the only statistics register that will be incremented will be the Pause Frames Transmitted register. PFC Pause frames can also be transmitted by the MAC using normal frame transmission methods. 37.6.18 Energy-efficient Ethernet Support IEEE 802.3az adds support for energy efficiency to Ethernet. These are the key features of 802.3az: • Allows a system’s transmit path to enter a low power mode if there is nothing to transmit. • Allows a PHY to detect whether its link partner’s transmit path is in low power mode, therefore allowing the system’s receive path to enter low power mode. • Link remains up during lower power mode and no frames are dropped. • Asymmetric, one direction can be in low power mode while the other is transmitting normally. • LPI (Low Power Idle) signaling is used to control entry and exit to and from low power modes. • LPI signaling can only take place if both sides have indicated support for it through auto-negotiation. These are the key features of 802.3az operation: • Low power control is done at the MII (reconciliation sublayer). • As an architectural convenience in writing the 802.3az it is assumed that transmission is deferred by asserting carrier sense, in practice it will not be done this way. This system will know when it has nothing to transmit and only enter low power mode when it is not transmitting. • LPI should not be requested unless the link has been up for at least one second. • LPI is signaled on the GMII transmit path by asserting 0x01 on txd with tx_en low and tx_er high. • A PHY on seeing LPI requested on the MII will send the sleep signal before going quiet. After going quiet it will periodically transmit refresh signals. • The sleep, quiet and refresh periods are defined in Table 78-2 of 802.3az. For 1000BASE-X the sleep period is 20 microseconds, the quiet period 2.5 milliseconds and the refresh period 20 microseconds. • 1000BASE-X is required to go quiet after sleep is signaled. The easiest way to do this is to write to a control register to disable transmit in the SerDes. • SGMII and XFI are not part of 802.3az and should not go quiet after sleep is signaled. • LPI mode ends by transmitting normal idle for the wake time. There is a default time for this but it can be adjusted in software using the Link Layer Discovery Protocol (LLDP) described in Clause 79 of 802.3az. • LPI is indicated at the receive side when sleep and refresh signaling has been detected. 37.6.19 LPI Operation in the GMAC It is best to use firmware to control LPI. LPI operation happens at the system level. Firmware gives maximum control and flexibility of operation. LPI operation is straightforward and firmware should be capable of responding within the required timeframes. Autonegotiation: 1. Indicate EEE capability using next page autonegotiation. For the transmit path: 1. 2. 3. 4. If the link has been up for 1 second and there is nothing being transmitted, write to the LPI bit in the Network Control register. If connected to 1000BASE-T PHY using SGMII or RGMII, there is nothing more to do. If connected to a backplane using a 1000BASE-KX PHY, use firmware to periodically disable the SerDes transmit path. (Write to bit 1.160.0 for 1000BASE-KX.) Wake up by clearing the LPI bit in the Network Control register. For the receive path: 1. 2. 3. Wait for an interrupt to indicate that LPI has been received. Disable relevant parts of the receive path if desired but keep the PCS and SerDes active. Wait for an interrupt to indicate that regular idle has been received and then re-enable the receive path. DS60001525A-page 972  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.6.20 PHY Interface Different PHY interfaces are supported by the Ethernet MAC: • MII • RMII The MII interface is provided for 10/100 operation and uses txd[3:0] and rxd[3:0]. The RMII interface is provided for 10/100 operation and uses txd[1:0] and rxd[1:0]. 37.6.21 10/100 Operation The 10/100 Mbps speed bit in the Network Configuration register is used to select between 10 Mbps and 100 Mbps. 37.6.22 Jumbo Frames The jumbo frames enable bit in the Network Configuration register allows the GMAC, in its default configuration, to receive jumbo frames up to 10240 bytes in size. This operation does not form part of the IEEE 802.3 specification and is normally disabled. When jumbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded. 37.7 37.7.1 37.7.1.1 Programming Interface Initialization Configuration Initialization of the GMAC configuration (e.g., loop back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. Refer to “GMAC Network Control Register” and “GMAC Network Configuration Register”. To change loop back mode, the following sequence of operations must be followed: 1. 2. 3. Write to Network Control register to disable transmit and receive circuits. Write to Network Control register to change loop back mode. Write to Network Control register to re-enable transmit or receive circuits. Note: 37.7.1.2 These writes to the Network Control register cannot be combined in any way. Receive Buffer List Receive data is written to areas of data (i.e., buffers) in system memory. These buffers are listed in another data structure that also resides in main memory. This data structure (receive buffer queue) is a sequence of descriptor entries as defined in Table 37-4 “Receive Buffer Descriptor Entry”. The Receive Buffer Queue Pointer register points to this data structure. Figure 37-2: Receive Buffer List Receive Buffer 0 Receive Buffer Queue Pointer (MAC Register) Receive Buffer 1 Receive Buffer N Receive Buffer Descriptor List (In memory)  2017 Microchip Technology Inc. (In memory) DS60001525A-page 973 SAMA5D4 SERIES To create the list of buffers: 1. 2. 3. 4. 5. Allocate a number (N) of buffers of X bytes in system memory, where X is the DMA buffer length programmed in the DMA Configuration register. Allocate an area 8N bytes for the receive buffer descriptor list in system memory and create N entries in this list. Mark all entries in this list as owned by GMAC, i.e., bit 0 of word 0 set to 0. Mark the last descriptor in the queue with the wrap bit (bit 1 in word 0 set to 1). Write address of receive buffer descriptor list and control information to GMAC register receive buffer queue pointer The receive circuits can then be enabled by writing to the address recognition registers and the Network Control register. Note: 37.7.1.3 The queue pointers must be initialized and point to USED descriptors for all queues including those not intended for use. Transmit Buffer List Transmit data is read from areas of data (the buffers) in system memory. These buffers are listed in another data structure that also resides in main memory. This data structure (Transmit Buffer Queue) is a sequence of descriptor entries as defined in Table 37-5 “Transmit Buffer Descriptor Entry”. The Transmit Buffer Queue Pointer register points to this data structure. To create this list of buffers: 1. 2. 3. 4. 5. Allocate a number (N) of buffers of between 1 and 2047 bytes of data to be transmitted in system memory. Up to 128 buffers per frame are allowed. Allocate an area 8N bytes for the transmit buffer descriptor list in system memory and create N entries in this list. Mark all entries in this list as owned by GMAC, i.e., bit 31 of word 1 set to 0. Mark the last descriptor in the queue with the wrap bit (bit 30 in word 1 set to 1). Write address of transmit buffer descriptor list and control information to GMAC register transmit buffer queue pointer. The transmit circuits can then be enabled by writing to the Network Control register. Note: 37.7.1.4 The queue pointers must be initialized and point to USED descriptors for all queues including those not intended for use. Address Matching The GMAC Hash register pair and the four Specific Address register pairs must be written with the required values. Each register pair comprises of a bottom register and top register, with the bottom register being written first. The address matching is disabled for a particular register pair after the bottom register has been written and re-enabled when the top register is written. Each register pair may be written at any time, regardless of whether the receive circuits are enabled or disabled. As an example, to set Specific Address 1 register to recognize destination address 21:43:65:87:A9:CB, the following values are written to Specific Address 1 Bottom register and Specific Address 1 Top register: • Specific Address 1 Bottom register bits 31:0 (0x98): 0x8765_4321. • Specific Address 1 Top register bits 31:0 (0x9C): 0x0000_CBA9. 37.7.1.5 PHY Maintenance The PHY Maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit two is set in the Network Status register (about 2000 MCK cycles later when bits 18:16 are set to 010 in the Network Configuration register). An interrupt is generated as this bit is set. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each Management Data Clock (MDC) cycle. This causes the transmission of a PHY management frame on MDIO. Refer to section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation will return the current contents of the shift register. At the end of the management operation the bits will have shifted back to their original locations. For a read operation the data bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The Management Data Clock (MDC) should not toggle faster than 2.5 MHz (minimum period of 400 ns), as defined by the IEEE 802.3 standard. MDC is generated by dividing down MCK. Three bits in the Network Configuration register determine by how much MCK should be divided to produce MDC. DS60001525A-page 974  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.7.1.6 Interrupts There are 18 interrupt conditions that are detected within the GMAC. The conditions are ORed to make a single interrupt. Depending on the overall system design this may be passed through a further level of interrupt collection (interrupt controller). On receipt of the interrupt signal, the CPU enters the interrupt handler. Refer to the device interrupt controller documentation to identify that it is the GMAC that is generating the interrupt. To ascertain which interrupt, read the Interrupt Status register. Note that in the default configuration this register will clear itself after being read, though this may be configured to be write-one-to-clear if desired. At reset all interrupts are disabled. To enable an interrupt, write to Interrupt Enable register with the pertinent interrupt bit set to 1. To disable an interrupt, write to Interrupt Disable register with the pertinent interrupt bit set to 1. To check whether an interrupt is enabled or disabled, read Interrupt Mask register. If the bit is set to 1, the interrupt is disabled. 37.7.1.7 Transmitting Frames The procedure to set up a frame for transmission is the following: 1. 2. 3. 4. 5. 6. 7. Enable transmit in the Network Control register. Allocate an area of system memory for transmit data. This does not have to be contiguous, varying byte lengths can be used if they conclude on byte borders. Set-up the transmit buffer list by writing buffer addresses to word zero of the transmit buffer descriptor entries and control and length to word one. Write data for transmission into the buffers pointed to by the descriptors. Write the address of the first buffer descriptor to transmit buffer descriptor queue pointer. Enable appropriate interrupts. Write to the transmit start bit (TSTART) in the Network Control register. 37.7.1.8 Receiving Frames When a frame is received and the receive circuits are enabled, the GMAC checks the address and, in the following cases, the frame is written to system memory: • • • • • If it matches one of the four Specific Address registers. If it matches one of the four Type ID registers. If it matches the hash address function. If it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed. If the GMAC is configured to “copy all frames”. The register receive buffer queue pointer points to the next entry in the receive buffer descriptor list and the GMAC uses this as the address in system memory to write the frame to. Once the frame has been completely and successfully received and written to system memory, the GMAC then updates the receive buffer descriptor entry (refer to Table 37-4 “Receive Buffer Descriptor Entry”) with the reason for the address match and marks the area as being owned by software. Once this is complete, a receive complete interrupt is set. Software is then responsible for copying the data to the application area and releasing the buffer (by writing the ownership bit back to 0). If the GMAC is unable to write the data at a rate to match the incoming frame, then a receive overrun interrupt is set. If there is no receive buffer available, i.e., the next buffer is still owned by software, a receive buffer not available interrupt is set. If the frame is not successfully received, a statistics register is incremented and the frame is discarded without informing software. 37.7.2 Statistics Registers Statistics registers are described in the User Interface beginning with Section 37.8.45 “GMAC Octets Transmitted Low Register” and ending with Section 37.8.89 “GMAC UDP Checksum Errors Register”. The statistics register block begins at 0x100 and runs to 0x1B0, and comprises the registers listed below. Octets Transmitted Low Register Broadcast Frames Received Register Octets Transmitted High Register Multicast Frames Received Register Frames Transmitted Register Pause Frames Received Register Broadcast Frames Transmitted Register 64 Byte Frames Received Register Multicast Frames Transmitted Register 65 to 127 Byte Frames Received Register Pause Frames Transmitted Register 128 to 255 Byte Frames Received Register  2017 Microchip Technology Inc. DS60001525A-page 975 SAMA5D4 SERIES 64 Byte Frames Transmitted Register 256 to 511 Byte Frames Received Register 65 to 127 Byte Frames Transmitted Register 512 to 1023 Byte Frames Received Register 128 to 255 Byte Frames Transmitted Register 1024 to 1518 Byte Frames Received Register 256 to 511 Byte Frames Transmitted Register 1519 to Maximum Byte Frames Received Register 512 to 1023 Byte Frames Transmitted Register Undersize Frames Received Register 1024 to 1518 Byte Frames Transmitted Register Oversize Frames Received Register Greater Than 1518 Byte Frames Transmitted Register Jabbers Received Register Transmit Underruns Register Frame Check Sequence Errors Register Single Collision Frames Register Length Field Frame Errors Register Multiple Collision Frames Register Receive Symbol Errors Register Excessive Collisions Register Alignment Errors Register Late Collisions Register Receive Resource Errors Register Deferred Transmission Frames Register Receive Overrun Register Carrier Sense Errors Register IP Header Checksum Errors Register Octets Received Low Register TCP Checksum Errors Register Octets Received High Register UDP Checksum Errors Register Frames Received Register These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit (RXEN) is set in the Network Control register. Once a statistics register has been read, it is automatically cleared. When reading the Octets Transmitted and Octets Received registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. DS60001525A-page 976  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8 Ethernet MAC (GMAC) User Interface Table 37-17: Offset (1) (2) Register Mapping Register Name Access Reset 0x000 Network Control Register GMAC_NCR Read/Write 0x0000_0000 0x004 Network Configuration Register GMAC_NCFGR Read/Write 0x0008_0000 0x008 Network Status Register GMAC_NSR Read-only 0b01x0 0x00C User Register GMAC_UR Read/Write 0x0000_0000 0x010 DMA Configuration Register GMAC_DCFGR Read/Write 0x0002_0004 0x014 Transmit Status Register GMAC_TSR Read/Write 0x0000_0000 0x018 Receive Buffer Queue Base Address Register GMAC_RBQB Read/Write 0x0000_0000 0x01C Transmit Buffer Queue Base Address Register GMAC_TBQB Read/Write 0x0000_0000 0x020 Receive Status Register GMAC_RSR Read/Write 0x0000_0000 0x024 Interrupt Status Register GMAC_ISR Read-only 0x0000_0000 0x028 Interrupt Enable Register GMAC_IER Write-only – 0x02C Interrupt Disable Register GMAC_IDR Write-only – 0x030 Interrupt Mask Register GMAC_IMR Read/Write 0x07FF_FFFF 0x034 PHY Maintenance Register GMAC_MAN Read/Write 0x0000_0000 0x038 Received Pause Quantum Register GMAC_RPQ Read-only 0x0000_0000 0x03C Transmit Pause Quantum Register GMAC_TPQ Read/Write 0x0000_FFFF 0x048 RX Jumbo Frame Max Length Register GMAC_RJFML Read/Write 0x0000_3FFF 0x040–0x07C Reserved – – – 0x080 Hash Register Bottom GMAC_HRB Read/Write 0x0000_0000 0x084 Hash Register Top GMAC_HRT Read/Write 0x0000_0000 0x088 Specific Address 1 Bottom Register GMAC_SAB1 Read/Write 0x0000_0000 0x08C Specific Address 1 Top Register GMAC_SAT1 Read/Write 0x0000_0000 0x090 Specific Address 2 Bottom Register GMAC_SAB2 Read/Write 0x0000_0000 0x094 Specific Address 2 Top Register GMAC_SAT2 Read/Write 0x0000_0000 0x098 Specific Address 3 Bottom Register GMAC_SAB3 Read/Write 0x0000_0000 0x09C Specific Address 3 Top Register GMAC_SAT3 Read/Write 0x0000_0000 0x0A0 Specific Address 4 Bottom Register GMAC_SAB4 Read/Write 0x0000_0000 0x0A4 Specific Address 4 Top Register GMAC_SAT4 Read/Write 0x0000_0000 0x0A8 Type ID Match 1 Register GMAC_TIDM1 Read/Write 0x0000_0000 0x0AC Type ID Match 2 Register GMAC_TIDM2 Read/Write 0x0000_0000 0x0B0 Type ID Match 3 Register GMAC_TIDM3 Read/Write 0x0000_0000 0x0B4 Type ID Match 4 Register GMAC_TIDM4 Read/Write 0x0000_0000 0x0B8 Wake on LAN Register GMAC_WOL Read/Write 0x0000_0000 0x0BC IPG Stretch Register GMAC_IPGS Read/Write 0x0000_0000 0x0C0 Stacked VLAN Register GMAC_SVLAN Read/Write 0x0000_0000  2017 Microchip Technology Inc. DS60001525A-page 977 SAMA5D4 SERIES Table 37-17: Register Mapping (Continued) Offset(1) (2) Register Name 0x0C4 Transmit PFC Pause Register 0x0C8 Access Reset GMAC_TPFCP Read/Write 0x0000_0000 Specific Address 1 Mask Bottom Register GMAC_SAMB1 Read/Write 0x0000_0000 0x0CC Specific Address 1 Mask Top Register GMAC_SAMT1 Read/Write 0x0000_0000 0x0D0–0x0D8 Reserved – – – 0x0DC 1588 Timer Nanosecond Comparison Register GMAC_NSC Read/Write 0x0000_0000 0x0E0 1588 Timer Second Comparison Low Register GMAC_SCL Read/Write 0x0000_0000 0x0E4 1588 Timer Second Comparison High Register GMAC_SCH Read/Write 0x0000_0000 0x0E8 PTP Event Frame Transmitted Seconds High Register GMAC_EFTSH Read-only 0x0000_0000 0x0EC PTP Event Frame Received Seconds High Register GMAC_EFRSH Read-only 0x0000_0000 0x0F0 PTP Peer Event Frame Transmitted Seconds High Register GMAC_PEFTSH Read-only 0x0000_0000 0x0F4 PTP Peer Event Frame Received Seconds High Register GMAC_PEFRSH Read-only 0x0000_0000 0x0F8–0x0FC Reserved – – – 0x100 Octets Transmitted Low Register GMAC_OTLO Read-only 0x0000_0000 0x104 Octets Transmitted High Register GMAC_OTHI Read-only 0x0000_0000 0x108 Frames Transmitted Register GMAC_FT Read-only 0x0000_0000 0x10C Broadcast Frames Transmitted Register GMAC_BCFT Read-only 0x0000_0000 0x110 Multicast Frames Transmitted Register GMAC_MFT Read-only 0x0000_0000 0x114 Pause Frames Transmitted Register GMAC_PFT Read-only 0x0000_0000 0x118 64 Byte Frames Transmitted Register GMAC_BFT64 Read-only 0x0000_0000 0x11C 65 to 127 Byte Frames Transmitted Register GMAC_TBFT127 Read-only 0x0000_0000 0x120 128 to 255 Byte Frames Transmitted Register GMAC_TBFT255 Read-only 0x0000_0000 0x124 256 to 511 Byte Frames Transmitted Register GMAC_TBFT511 Read-only 0x0000_0000 0x128 512 to 1023 Byte Frames Transmitted Register GMAC_TBFT1023 Read-only 0x0000_0000 0x12C 1024 to 1518 Byte Frames Transmitted Register GMAC_TBFT1518 Read-only 0x0000_0000 0x130 Greater Than 1518 Byte Frames Transmitted Register GMAC_GTBFT1518 Read-only 0x0000_0000 0x134 Transmit Underruns Register GMAC_TUR Read-only 0x0000_0000 0x138 Single Collision Frames Register GMAC_SCF Read-only 0x0000_0000 0x13C Multiple Collision Frames Register GMAC_MCF Read-only 0x0000_0000 0x140 Excessive Collisions Register GMAC_EC Read-only 0x0000_0000 0x144 Late Collisions Register GMAC_LC Read-only 0x0000_0000 0x148 Deferred Transmission Frames Register GMAC_DTF Read-only 0x0000_0000 0x14C Carrier Sense Errors Register GMAC_CSE Read-only 0x0000_0000 0x150 Octets Received Low Received Register GMAC_ORLO Read-only 0x0000_0000 0x154 Octets Received High Received Register GMAC_ORHI Read-only 0x0000_0000 DS60001525A-page 978  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 37-17: Register Mapping (Continued) Offset(1) (2) Register Name 0x158 Frames Received Register 0x15C Access Reset GMAC_FR Read-only 0x0000_0000 Broadcast Frames Received Register GMAC_BCFR Read-only 0x0000_0000 0x160 Multicast Frames Received Register GMAC_MFR Read-only 0x0000_0000 0x164 Pause Frames Received Register GMAC_PFR Read-only 0x0000_0000 0x168 64 Byte Frames Received Register GMAC_BFR64 Read-only 0x0000_0000 0x16C 65 to 127 Byte Frames Received Register GMAC_TBFR127 Read-only 0x0000_0000 0x170 128 to 255 Byte Frames Received Register GMAC_TBFR255 Read-only 0x0000_0000 0x174 256 to 511 Byte Frames Received Register GMAC_TBFR511 Read-only 0x0000_0000 0x178 512 to 1023 Byte Frames Received Register GMAC_TBFR1023 Read-only 0x0000_0000 0x17C 1024 to 1518 Byte Frames Received Register GMAC_TBFR1518 Read-only 0x0000_0000 0x180 1519 to Maximum Byte Frames Received Register GMAC_TMXBFR Read-only 0x0000_0000 0x184 Undersize Frames Received Register GMAC_UFR Read-only 0x0000_0000 0x188 Oversize Frames Received Register GMAC_OFR Read-only 0x0000_0000 0x18C Jabbers Received Register GMAC_JR Read-only 0x0000_0000 0x190 Frame Check Sequence Errors Register GMAC_FCSE Read-only 0x0000_0000 0x194 Length Field Frame Errors Register GMAC_LFFE Read-only 0x0000_0000 0x198 Receive Symbol Errors Register GMAC_RSE Read-only 0x0000_0000 0x19C Alignment Errors Register GMAC_AE Read-only 0x0000_0000 0x1A0 Receive Resource Errors Register GMAC_RRE Read-only 0x0000_0000 0x1A4 Receive Overrun Register GMAC_ROE Read-only 0x0000_0000 0x1A8 IP Header Checksum Errors Register GMAC_IHCE Read-only 0x0000_0000 0x1AC TCP Checksum Errors Register GMAC_TCE Read-only 0x0000_0000 0x1B0 UDP Checksum Errors Register GMAC_UCE Read-only 0x0000_0000 0x1B4–0x1B8 Reserved – – – 0x1BC 1588 Timer Increment Sub-nanoseconds Register GMAC_TISUBN Read/Write 0x0000_0000 0x1C0 1588 Timer Seconds High Register GMAC_TSH Read/Write 0x0000_0000 0x1C4–0x1CC Reserved – – – 0x1D0 1588 Timer Seconds Low Register GMAC_TSL Read/Write 0x0000_0000 0x1D4 1588 Timer Nanoseconds Register GMAC_TN Read/Write 0x0000_0000 0x1D8 1588 Timer Adjust Register GMAC_TA Write-only – 0x1DC 1588 Timer Increment Register GMAC_TI Read/Write 0x0000_0000 0x1E0 PTP Event Frame Transmitted Seconds Low Register GMAC_EFTSL Read-only 0x0000_0000 0x1E4 PTP Event Frame Transmitted Nanoseconds Register GMAC_EFTN Read-only 0x0000_0000 0x1E8 PTP Event Frame Received Seconds Low Register GMAC_EFRSL Read-only 0x0000_0000 0x1EC PTP Event Frame Received Nanoseconds Register GMAC_EFRN Read-only 0x0000_0000  2017 Microchip Technology Inc. DS60001525A-page 979 SAMA5D4 SERIES Table 37-17: Register Mapping (Continued) Offset(1) (2) Register Name 0x1F0 PTP Peer Event Frame Transmitted Seconds Low Register 0x1F4 Access Reset GMAC_PEFTSL Read-only 0x0000_0000 PTP Peer Event Frame Transmitted Nanoseconds Register GMAC_PEFTN Read-only 0x0000_0000 0x1F8 PTP Peer Event Frame Received Seconds Low Register GMAC_PEFRSL Read-only 0x0000_0000 0x1FC PTP Peer Event Frame Received Nanoseconds Register GMAC_PEFRN Read-only 0x0000_0000 0x200–0x26C Reserved – – – 0x270 Received LPI Transitions GMAC_RXLPI Read-only 0x0000_0000 0x274 Received LPI Time GMAC_RXLPITIME Read-only 0x0000_0000 0x278 Transmit LPI Transitions GMAC_TXLPI Read-only 0x0000_0000 0x27C Transmit LPI Time GMAC_TXLPITIME Read-only 0x0000_0000 0x280–0x7FC Reserved – – – Note 1: If an offset is not listed in the Register Mapping, it must be considered as ‘reserved’. 2: Some register groups are not continuous in memory. DS60001525A-page 980  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.1 GMAC Network Control Register Name:GMAC_NCR Address:0xF8020000 (0), 0xFC028000 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 TXLPIEN 18 FNP 17 TXPBPF 16 ENPBPR 15 SRTSM 14 – 13 – 12 TXZQPF 11 TXPF 10 THALT 9 TSTART 8 BP 7 WESTAT 6 INCSTAT 5 CLRSTAT 4 MPE 3 TXEN 2 RXEN 1 LBL 0 – LBL: Loop Back Local Connects GTX to GRX, GTXEN to GRXDV and forces full duplex mode. GRXCK and GTXCK may malfunction as the GMAC is switched into and out of internal loop back. It is important that receive and transmit circuits have already been disabled when making the switch into and out of internal loop back. RXEN: Receive Enable When set, RXEN enables the GMAC to receive data. When reset frame reception stops immediately and the receive pipeline will be cleared. The Receive Queue Pointer Register is unaffected. TXEN: Transmit Enable When set, TXEN enables the GMAC transmitter to send data. When reset transmission will stop immediately, the transmit pipeline and control registers will be cleared and the Transmit Queue Pointer Register will reset to point to the start of the transmit descriptor list. MPE: Management Port Enable Set to one to enable the management port. When zero, forces MDIO to high impedance state and MDC low. CLRSTAT: Clear Statistics Registers This bit is write-only. Writing a one clears the statistics registers. INCSTAT: Increment Statistics Registers This bit is write-only. Writing a one increments all the statistics registers by one for test purposes. WESTAT: Write Enable for Statistics Registers Setting this bit to one makes the statistics registers writable for functional test purposes. BP: Back pressure If set in 10M or 100M half duplex mode, forces collisions on all received frames. TSTART: Start Transmission Writing one to this bit starts transmission. THALT: Transmit Halt Writing one to this bit halts transmission as soon as any ongoing frame transmission ends. TXPF: Transmit Pause Frame Writing one to this bit causes a pause frame to be transmitted.  2017 Microchip Technology Inc. DS60001525A-page 981 SAMA5D4 SERIES TXZQPF: Transmit Zero Quantum Pause Frame Writing one to this bit causes a pause frame with zero quantum to be transmitted. SRTSM: Store Receive Time Stamp to Memory 0: Normal operation. 1: Causes the CRC of every received frame to be replaced with the value of the nanoseconds field of the 1588 timer that was captured as the receive frame passed the message timestamp point. ENPBPR: Enable PFC Priority-based Pause Reception Enables PFC Priority Based Pause Reception capabilities. Setting this bit enables PFC negotiation and recognition of priority-based pause frames. TXPBPF: Transmit PFC Priority-based Pause Frame Takes the values stored in the Transmit PFC Pause Register. FNP: Flush Next Packet Flush the next packet from the external RX DPRAM. Writing one to this bit will only have an effect if the DMA is not currently writing a packet already stored in the DPRAM to memory. TXLPIEN: Enable LPI Transmission When set, LPI (low power idle) is immediately transmitted. DS60001525A-page 982  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.2 GMAC Network Configuration Register Name:GMAC_NCFGR Address:0xF8020004 (0), 0xFC028004 (1) Access: Read/Write 31 – 30 IRXER 29 RXBP 28 IPGSEN 27 – 26 IRXFCS 25 EFRHD 24 RXCOEN 23 DCPF 22 21 20 19 CLK 18 17 RFCS 16 LFERD 15 14 13 PEN 12 RTY 11 – 10 – 9 – 8 MAXFS 6 MTI HEN 5 NBC 4 CAF 3 JFRAME 2 DNVLAN 1 FD 0 SPD DBW RXBUFO 7 UNIHEN SPD: Speed Set to logic one to indicate 100 Mbps operation, logic zero for 10 Mbps. FD: Full Duplex If set to logic one, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. DNVLAN: Discard Non-VLAN FRAMES When set only VLAN tagged frames will be passed to the address matching logic. JFRAME: Jumbo Frame Size Set to one to enable jumbo frames up to 10240 bytes to be accepted. The default length is 10240 bytes. CAF: Copy All Frames When set to logic one, all valid frames will be accepted. NBC: No Broadcast When set to logic one, frames addressed to the broadcast address of all ones will not be accepted. MTIHEN: Multicast Hash Enable When set, multicast frames will be accepted when the 6-bit hash function of the destination address points to a bit that is set in the Hash Register. UNIHEN: Unicast Hash Enable When set, unicast frames will be accepted when the 6-bit hash function of the destination address points to a bit that is set in the Hash Register. MAXFS: 1536 Maximum Frame Size Setting this bit means the GMAC will accept frames up to 1536 bytes in length. Normally the GMAC would reject any frame above 1518 bytes. RTY: Retry Test Must be set to zero for normal operation. If set to one the backoff between collisions will always be one slot time. Setting this bit to one helps test the too many retries condition. Also used in the pause frame tests to reduce the pause counter's decrement time from 512 bit times, to every GRXCK cycle. PEN: Pause Enable When set, transmission will pause if a non-zero 802.3 classic pause frame is received and PFC has not been negotiated.  2017 Microchip Technology Inc. DS60001525A-page 983 SAMA5D4 SERIES RXBUFO: Receive Buffer Offset Indicates the number of bytes by which the received data is offset from the start of the receive buffer LFERD: Length Field Error Frame Discard Setting this bit causes frames with a measured length shorter than the extracted length field (as indicated by bytes 13 and 14 in a nonVLAN tagged frame) to be discarded. This only applies to frames with a length field less than 0x0600. RFCS: Remove FCS Setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). The frame length indicated will be reduced by four bytes in this mode. CLK: MDC CLock Division Set according to MCK speed. These three bits determine the number MCK will be divided by to generate Management Data Clock (MDC). For conformance with the 802.3 specification, MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and write operations). Value Name Description 0 MCK_8 MCK divided by 8 (MCK up to 20 MHz) 1 MCK_16 MCK divided by 16 (MCK up to 40 MHz) 2 MCK_32 MCK divided by 32 (MCK up to 80 MHz) 3 MCK_48 MCK divided by 48 (MCK up to 120 MHz) 4 MCK_64 MCK divided by 64 (MCK up to 160 MHz) 5 MCK_96 MCK divided by 96 (MCK up to 240 MHz) DBW: Data Bus Width Should always be written to ‘0’. DCPF: Disable Copy of Pause Frames Set to one to prevent valid pause frames being copied to memory. When set, pause frames are not copied to memory regardless of the state of the Copy All Frames bit, whether a hash match is found or whether a type ID match is identified. If a destination address match is found, the pause frame will be copied to memory. Note that valid pause frames received will still increment pause statistics and pause the transmission of frames as required. RXCOEN: Receive Checksum Offload Enable When set, the receive checksum engine is enabled. Frames with bad IP, TCP or UDP checksums are discarded. EFRHD: Enable Frames Received in Half Duplex Enable frames to be received in half-duplex mode while transmitting. IRXFCS: Ignore RX FCS When set, frames with FCS/CRC errors will not be rejected. FCS error statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame’s DMA descriptor. For normal operation this bit must be set to zero. IPGSEN: IP Stretch Enable When set, the transmit IPG can be increased above 96 bit times depending on the previous frame length using the IPG Stretch Register. RXBP: Receive Bad Preamble When set, frames with non-standard preamble are not rejected. IRXER: Ignore IPG GRXER When set, GRXER has no effect on the GMAC's operation when GRXDV is low. DS60001525A-page 984  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.3 GMAC Network Status Register Name:GMAC_NSR Address:0xF8020008 (0), 0xFC028008 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 RXLPIS 6 – 5 – 4 – 3 – 2 IDLE 1 MDIO 0 – MDIO: MDIO Input Status Returns status of the MDIO pin. IDLE: PHY Management Logic Idle The PHY management logic is idle (i.e., has completed). RXLPIS: LPI Indication Low power idle has been detected on receive. This bit is set when LPI is detected and reset when normal idle is detected. An interrupt is generated when the state of this bit changes.  2017 Microchip Technology Inc. DS60001525A-page 985 SAMA5D4 SERIES 37.8.4 GMAC User Register Name:GMAC_UR Address:0xF802000C (0), 0xFC02800C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RMII RMII: Reduced MII Mode 0: MII mode is selected (default). 1: RMII mode is selected. DS60001525A-page 986  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.5 GMAC DMA Configuration Register Name:GMAC_DCFGR Address:0xF8020010 (0), 0xFC028010 (1) Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 DRBS 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ESPA 6 ESMA 5 – 4 3 2 FBLDO 1 0 FBLDO: Fixed Burst Length for DMA Data Operations: Selects the burst length to attempt to use on the AHB when transferring frame data. Not used for DMA management operations and only used where space and data size allow. Otherwise SINGLE type AHB transfers are used. Upper bits become non-writable if the configured DMA TX and RX FIFO sizes are smaller than required to support the selected burst size. One-hot priority encoding enforced automatically on register writes as follows, where ‘x’ represents don’t care: Value Name Description 0 – Reserved 1 SINGLE 00001: Always use SINGLE AHB bursts 2 – Reserved 4 INCR4 001xx: Attempt to use INCR4 AHB bursts (Default) 8 INCR8 01xxx: Attempt to use INCR8 AHB bursts 16 INCR16 1xxxx: Attempt to use INCR16 AHB bursts ESMA: Endian Swap Mode Enable for Management Descriptor Accesses When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode. ESPA: Endian Swap Mode Enable for Packet Data Accesses When set, selects swapped endianism for AHB transfers. When clear, selects little endian mode. DRBS: DMA Receive Buffer Size DMA receive buffer size in AHB system memory. The value defined by these bits determines the size of buffer to use in main AHB system memory when writing received data. The value is defined in multiples of 64 bytes, thus a value of 0x01 corresponds to buffers of 64 bytes, 0x02 corresponds to 128 bytes etc. For example: – 0x02: 128 bytes – 0x18: 1536 bytes (1 × max length frame/buffer) – 0xA0: 10240 bytes (1 × 10K jumbo frame/buffer) Note that this value should never be written as zero.  2017 Microchip Technology Inc. DS60001525A-page 987 SAMA5D4 SERIES 37.8.6 GMAC Transmit Status Register Name:GMAC_TSR Address:0xF8020014 (0), 0xFC028014 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 HRESP 7 – 6 UND 5 TXCOMP 4 TFC 3 TXGO 2 RLE 1 COL 0 UBR UBR: Used Bit Read Set when a transmit buffer descriptor is read with its used bit set. Writing a one clears this bit. COL: Collision Occurred Set by the assertion of collision. Writing a one clears this bit. When operating in 10/100 mode, this status indicates either a collision or a late collision. RLE: Retry Limit Exceeded Writing a one clears this bit. TXGO: Transmit Go Transmit go, if high transmit is active. When using the DMA interface this bit represents the TXGO variable as specified in the transmit buffer description. TFC: Transmit Frame Corruption Due to AHB Error Transmit frame corruption due to AHB error. Set if an error occurs while midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame (if the buffers run out during transmission of a frame then transmission stops, FCS shall be bad and GTXER asserted). Writing a one clears this bit. TXCOMP: Transmit Complete Set when a frame has been transmitted. Writing a one clears this bit. UND: Transmit Underrun This bit is set if the transmitter was forced to terminate a frame that it had already began transmitting due to further data being unavailable. This bit is set if a transmitter status write back has not completed when another status write back is attempted. When using the DMA interface configured for internal FIFO mode, this bit is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because a used bit was read. Writing a one clears this bit. HRESP: HRESP Not OK Set when the DMA block sees HRESP not OK. Writing a one clears this bit. DS60001525A-page 988  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.7 GMAC Receive Buffer Queue Base Address Register Name:GMAC_RBQB Address:0xF8020018 (0), 0xFC028018 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register holds the start address of the receive buffer queue (receive buffers descriptor list). The receive buffer queue base address must be initialized before receive is enabled through bit 2 of the Network Control Register. Once reception is enabled, any write to the Receive Buffer Queue Base Address Register is ignored. Reading this register returns the location of the descriptor currently being accessed. This value increments as buffers are used. Software should not use this register for determining where to remove received frames from the queue as it constantly changes as new frames are received. Software should instead work its way through the buffer descriptor queue checking the “used” bits. In terms of AMBA AHB operation, the descriptors are read from memory using a single 32-bit AHB access. The descriptors should be aligned at 32-bit boundaries and the descriptors are written to using two individual non sequential accesses. ADDR: Receive Buffer Queue Base Address Written with the address of the start of the receive queue.  2017 Microchip Technology Inc. DS60001525A-page 989 SAMA5D4 SERIES 37.8.8 GMAC Transmit Buffer Queue Base Address Register Name:GMAC_TBQB Address:0xF802001C (0), 0xFC02801C (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register holds the start address of the transmit buffer queue (transmit buffers descriptor list). The Transmit Buffer Queue Base Address Register must be initialized before transmit is started through bit 9 of the Network Control Register. Once transmission has started, any write to the Transmit Buffer Queue Base Address Register is illegal and therefore ignored. Note that due to clock boundary synchronization, it takes a maximum of four MCK cycles from the writing of the transmit start bit before the transmitter is active. Writing to the Transmit Buffer Queue Base Address Register during this time may produce unpredictable results. Reading this register returns the location of the descriptor currently being accessed. Since the DMA handles two frames at once, this may not necessarily be pointing to the current frame being transmitted. In terms of AMBA AHB operation, the descriptors are written to memory using a single 32-bit AHB access. The descriptors should be aligned at 32-bit boundaries and the descriptors are read from memory using two individual non sequential accesses. ADDR: Transmit Buffer Queue Base Address Written with the address of the start of the transmit queue. DS60001525A-page 990  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.9 GMAC Receive Status Register Name:GMAC_RSR Address:0xF8020020 (0), 0xFC028020 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 HNO 2 RXOVR 1 REC 0 BNA This register, when read, provides receive status details. Once read, individual bits may be cleared by writing a one to them. It is not possible to set a bit to 1 by writing to the register. BNA: Buffer Not Available An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA will re-read the pointer each time an end of frame is received until a valid pointer is found. This bit is set following each descriptor read attempt that fails, even if consecutive pointers are unsuccessful and software has in the mean time cleared the status flag. Writing a one clears this bit. REC: Frame Received One or more frames have been received and placed in memory. Writing a one clears this bit. RXOVR: Receive Overrun This bit is set if RX FIFO is not able to store the receive frame due to a FIFO overflow, or if the receive status was not taken at the end of the frame. The buffer will be recovered if an overrun occurs. Writing a one clears this bit. HNO: HRESP Not OK Set when the DMA block sees HRESP not OK. Writing a one clears this bit.  2017 Microchip Technology Inc. DS60001525A-page 991 SAMA5D4 SERIES 37.8.10 GMAC Interrupt Status Register Name:GMAC_ISR Address:0xF8020024 (0), 0xFC028024 (1) Access: Read-only 31 – 30 – 29 TSUTIMCOMP 28 WOL 27 RXLPISBC 26 SRI 25 PDRSFT 24 PDRQFT 23 PDRSFR 22 PDRQFR 21 SFT 20 DRQFT 19 SFR 18 DRQFR 17 – 16 – 15 – 14 PFTR 13 PTZ 12 PFNZ 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TFC 5 RLEX 4 TUR 3 TXUBR 2 RXUBR 1 RCOMP 0 MFS This register indicates the source of the interrupt. In order that the bits of this register read 1, the corresponding interrupt source must be enabled in the mask register. If any bit is set in this register, the GMAC interrupt signal will be asserted in the system. MFS: Management Frame Sent The PHY Maintenance Register has completed its operation. Cleared on read. RCOMP: Receive Complete A frame has been stored in memory. Cleared on read. RXUBR: RX Used Bit Read Set when a receive buffer descriptor is read with its used bit set. Cleared on read. TXUBR: TX Used Bit Read Set when a transmit buffer descriptor is read with its used bit set. Cleared on read. TUR: Transmit Underrun This interrupt is set if the transmitter was forced to terminate a frame that it has already began transmitting due to further data being unavailable. This interrupt is set if a transmitter status write back has not completed when another status write back is attempted. This interrupt is also set when the transmit DMA has written the SOP data into the FIFO and either the AHB bus was not granted in time for further data, or because an AHB not OK response was returned, or because the used bit was read. RLEX: Retry Limit Exceeded Transmit error. Cleared on read. TFC: Transmit Frame Corruption Due to AHB Error Transmit frame corruption due to AHB error. Set if an error occurs while midway through reading transmit frame from the AHB, including HRESP errors and buffers exhausted mid frame. TCOMP: Transmit Complete Set when a frame has been transmitted. Cleared on read. ROVR: Receive Overrun Set when the receive overrun status bit is set. Cleared on read. HRESP: HRESP Not OK Set when the DMA block sees HRESP not OK. Cleared on read. DS60001525A-page 992  2017 Microchip Technology Inc. SAMA5D4 SERIES PFNZ: Pause Frame with Non-zero Pause Quantum Received Indicates a valid pause has been received that has a non-zero pause quantum field. Cleared on read. PTZ: Pause Time Zero Set when either the Pause Time register at address 0x38 decrements to zero, or when a valid pause frame is received with a zero pause quantum field. Cleared on read. PFTR: Pause Frame Transmitted Indicates a pause frame has been successfully transmitted after being initiated from the Network Control register. Cleared on read. DRQFR: PTP Delay Request Frame Received Indicates a PTP delay_req frame has been received. Cleared on read. SFR: PTP Sync Frame Received Indicates a PTP sync frame has been received. Cleared on read. DRQFT: PTP Delay Request Frame Transmitted Indicates a PTP delay_req frame has been transmitted. Cleared on read. SFT: PTP Sync Frame Transmitted Indicates a PTP sync frame has been transmitted. Cleared on read. PDRQFR: PDelay Request Frame Received Indicates a PTP pdelay_req frame has been received. Cleared on read. PDRSFR: PDelay Response Frame Received Indicates a PTP pdelay_resp frame has been received. Cleared on read. PDRQFT: PDelay Request Frame Transmitted Indicates a PTP pdelay_req frame has been transmitted. Cleared on read. PDRSFT: PDelay Response Frame Transmitted Indicates a PTP pdelay_resp frame has been transmitted. Cleared on read. SRI: TSU Seconds Register Increment Indicates the register has incremented. Cleared on read. RXLPISBC: Receive LPI indication Status Bit Change Receive LPI indication status bit change. Cleared on read. WOL: Wake On LAN WOL interrupt. Indicates a WOL event has been received. TSUTIMCOMP: TSU Timer Comparison Indicates when TSU timer count value is equal to programmed value. Cleared on read.  2017 Microchip Technology Inc. DS60001525A-page 993 SAMA5D4 SERIES 37.8.11 GMAC Interrupt Enable Register Name:GMAC_IER Address:0xF8020028 (0), 0xFC028028 (1) Access: Write-only 31 – 30 – 29 TSUTIMCOMP 28 WOL 27 RXLPISBC 26 SRI 25 PDRSFT 24 PDRQFT 23 PDRSFR 22 PDRQFR 21 SFT 20 DRQFT 19 SFR 18 DRQFR 17 – 16 – 15 EXINT 14 PFTR 13 PTZ 12 PFNZ 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TFC 5 RLEX 4 TUR 3 TXUBR 2 RXUBR 1 RCOMP 0 MFS This register is write-only and when read will return zero. The following values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. MFS: Management Frame Sent RCOMP: Receive Complete RXUBR: RX Used Bit Read TXUBR: TX Used Bit Read TUR: Transmit Underrun RLEX: Retry Limit Exceeded or Late Collision TFC: Transmit Frame Corruption Due to AHB Error TCOMP: Transmit Complete ROVR: Receive Overrun HRESP: HRESP Not OK PFNZ: Pause Frame with Non-zero Pause Quantum Received PTZ: Pause Time Zero PFTR: Pause Frame Transmitted EXINT: External Interrupt DRQFR: PTP Delay Request Frame Received SFR: PTP Sync Frame Received DRQFT: PTP Delay Request Frame Transmitted SFT: PTP Sync Frame Transmitted PDRQFR: PDelay Request Frame Received PDRSFR: PDelay Response Frame Received DS60001525A-page 994  2017 Microchip Technology Inc. SAMA5D4 SERIES PDRQFT: PDelay Request Frame Transmitted PDRSFT: PDelay Response Frame Transmitted SRI: TSU Seconds Register Increment RXLPISBC: Enable RX LPI Indication WOL: Wake On LAN TSUTIMCOMP: TSU Timer Comparison  2017 Microchip Technology Inc. DS60001525A-page 995 SAMA5D4 SERIES 37.8.12 GMAC Interrupt Disable Register Name:GMAC_IDR Address:0xF802002C (0), 0xFC02802C (1) Access: Write-only 31 – 30 – 29 TSUTIMCOMP 28 WOL 27 RXLPISBC 26 SRI 25 PDRSFT 24 PDRQFT 23 PDRSFR 22 PDRQFR 21 SFT 20 DRQFT 19 SFR 18 DRQFR 17 – 16 – 15 EXINT 14 PFTR 13 PTZ 12 PFNZ 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TFC 5 RLEX 4 TUR 3 TXUBR 2 RXUBR 1 RCOMP 0 MFS This register is write-only and when read will return zero. The following values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. MFS: Management Frame Sent RCOMP: Receive Complete RXUBR: RX Used Bit Read TXUBR: TX Used Bit Read TUR: Transmit Underrun RLEX: Retry Limit Exceeded or Late Collision TFC: Transmit Frame Corruption Due to AHB Error TCOMP: Transmit Complete ROVR: Receive Overrun HRESP: HRESP Not OK PFNZ: Pause Frame with Non-zero Pause Quantum Received PTZ: Pause Time Zero PFTR: Pause Frame Transmitted EXINT: External Interrupt DRQFR: PTP Delay Request Frame Received SFR: PTP Sync Frame Received DRQFT: PTP Delay Request Frame Transmitted SFT: PTP Sync Frame Transmitted PDRQFR: PDelay Request Frame Received PDRSFR: PDelay Response Frame Received DS60001525A-page 996  2017 Microchip Technology Inc. SAMA5D4 SERIES PDRQFT: PDelay Request Frame Transmitted PDRSFT: PDelay Response Frame Transmitted SRI: TSU Seconds Register Increment RXLPISBC: Enable RX LPI Indication WOL: Wake On LAN TSUTIMCOMP: TSU Timer Comparison  2017 Microchip Technology Inc. DS60001525A-page 997 SAMA5D4 SERIES 37.8.13 GMAC Interrupt Mask Register Name:GMAC_IMR Address:0xF8020030 (0), 0xFC028030 (1) Access: Read/Write 31 – 30 – 29 TSUTIMCOMP 28 WOL 27 RXLPISBC 26 SRI 25 PDRSFT 24 PDRQFT 23 PDRSFR 22 PDRQFR 21 SFT 20 DRQFT 19 SFR 18 DRQFR 17 – 16 – 15 EXINT 14 PFTR 13 PTZ 12 PFNZ 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TFC 5 RLEX 4 TUR 3 TXUBR 2 RXUBR 1 RCOMP 0 MFS The Interrupt Mask Register is a read-only register indicating which interrupts are masked. All bits are set at reset and can be reset individually by writing to the Interrupt Enable Register or set individually by writing to the Interrupt Disable Register. Having separate address locations for enable and disable saves the need for performing a read modify write when updating the Interrupt Mask Register. For test purposes there is a write-only function to this register that allows the bits in the Interrupt Status Register to be set or cleared, regardless of the state of the mask register. A write to this register directly affects the state of the corresponding bit in the Interrupt Status Register, causing an interrupt to be generated if a 1 is written. The following values are valid for all listed bit names of this register when read: 0: The corresponding interrupt is enabled. 1: The corresponding interrupt is not enabled. MFS: Management Frame Sent RCOMP: Receive Complete RXUBR: RX Used Bit Read TXUBR: TX Used Bit Read TUR: Transmit Underrun RLEX: Retry Limit Exceeded TFC: Transmit Frame Corruption Due to AHB Error TCOMP: Transmit Complete ROVR: Receive Overrun HRESP: HRESP Not OK PFNZ: Pause Frame with Non-zero Pause Quantum Received PTZ: Pause Time Zero PFTR: Pause Frame Transmitted EXINT: External Interrupt DRQFR: PTP Delay Request Frame Received SFR: PTP Sync Frame Received DRQFT: PTP Delay Request Frame Transmitted DS60001525A-page 998  2017 Microchip Technology Inc. SAMA5D4 SERIES SFT: PTP Sync Frame Transmitted PDRQFR: PDelay Request Frame Received PDRSFR: PDelay Response Frame Received PDRQFT: PDelay Request Frame Transmitted PDRSFT: PDelay Response Frame Transmitted SRI: TSU Seconds Register Increment RXLPISBC: Enable RX LPI Indication WOL: Wake On LAN TSUTIMCOMP: TSU Timer Comparison  2017 Microchip Technology Inc. DS60001525A-page 999 SAMA5D4 SERIES 37.8.14 GMAC PHY Maintenance Register Name:GMAC_MAN Address:0xF8020034 (0), 0xFC028034 (1) Access: Read/Write 31 WZO 30 CLTTO 29 23 PHYA 22 21 15 14 28 27 26 OP 25 24 PHYA 20 REGA 19 12 11 10 9 8 3 2 1 0 13 18 17 16 WTN DATA 7 6 5 4 DATA The PHY Maintenance Register is implemented as a shift register. Writing to the register starts a shift operation which is signalled as complete when bit 2 is set in the Network Status Register. It takes about 2000 MCK cycles to complete, when MDC is set for MCK divide by 32 in the Network Configuration Register. An interrupt is generated upon completion. During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each MDC cycle. This causes transmission of a PHY management frame on MDIO. Refer to Section 22.2.4.5 of the IEEE 802.3 standard. Reading during the shift operation returns the current contents of the shift register. At the end of management operation, the bits will have shifted back to their original locations. For a read operation, the data bits are updated with data read from the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced. The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs, bit 30 should be written with a 0 rather than a 1. To write clause 45 PHYs, bits 31:28 should be written as 0x0001. Refer to Table 37-18. Table 37-18: Clause 22/Clause 45 PHYs Read/Write Access Configuration (GMAC_MAN Bits 31:28) Bit Value PHY Access WZO CLTTO OP[1] OP[0] Read 0 1 1 0 Write 0 1 0 1 Read 0 0 1 1 Write 0 0 0 1 Read + Address 0 0 1 0 Clause 22 Clause 45 For a description of MDC generation, refer to Section 37.8.2 “GMAC Network Configuration Register”. DATA: PHY Data For a write operation this field is written with the data to be written to the PHY. After a read operation this field contains the data read from the PHY. WTN: Write Ten Must be written to 10. REGA: Register Address Specifies the register in the PHY to access. PHYA: PHY Address DS60001525A-page 1000  2017 Microchip Technology Inc. SAMA5D4 SERIES OP: Operation 01: Write 10: Read CLTTO: Clause 22 Operation 0: Clause 45 operation 1: Clause 22 operation WZO: Write ZERO Must be written with 0.  2017 Microchip Technology Inc. DS60001525A-page 1001 SAMA5D4 SERIES 37.8.15 GMAC Receive Pause Quantum Register Name:GMAC_RPQ Address:0xF8020038 (0), 0xFC028038 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RPQ 7 6 5 4 RPQ RPQ: Received Pause Quantum Stores the current value of the Receive Pause Quantum Register which is decremented every 512 bit times. DS60001525A-page 1002  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.16 GMAC Transmit Pause Quantum Register Name:GMAC_TPQ Address:0xF802003C (0), 0xFC02803C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TPQ 7 6 5 4 TPQ TPQ: Transmit Pause Quantum Written with the pause quantum value for pause frame transmission.  2017 Microchip Technology Inc. DS60001525A-page 1003 SAMA5D4 SERIES 37.8.17 GMAC RX Jumbo Frame Max Length Register Name: GMAC_RJFML Address:0xF8020048 (0), 0xFC028048 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 10 9 8 7 6 5 2 1 0 FML 4 3 FML FML: Frame Max Length Rx jumbo frame maximum length. DS60001525A-page 1004  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.18 GMAC Hash Register Bottom Name:GMAC_HRB Address:0xF8020080 (0), 0xFC028080 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR The unicast hash enable (UNIHEN) and the multicast hash enable (MITIHEN) bits in the Network Configuration Register (Section 37.8.2 “GMAC Network Configuration Register”) enable the reception of hash matched frames. Refer to Section 37.6.9 “Hash Addressing”. ADDR: Hash Address The first 32 bits of the Hash Address Register.  2017 Microchip Technology Inc. DS60001525A-page 1005 SAMA5D4 SERIES 37.8.19 GMAC Hash Register Top Name:GMAC_HRT Address:0xF8020084 (0), 0xFC028084 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR The unicast hash enable (UNIHEN) and the multicast hash enable (MITIHEN) bits in the GMAC Network Configuration Register enable the reception of hash matched frames. Refer to Section 37.6.9 “Hash Addressing”. ADDR: Hash Address Bits 63 to 32 of the Hash Address Register. DS60001525A-page 1006  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.20 GMAC Specific Address 1 Bottom Register Name:GMAC_SAB1 Address:0xF8020088 (0), 0xFC028088 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written. ADDR: Specific Address 1 Least significant 32 bits of the destination address, that is, bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.  2017 Microchip Technology Inc. DS60001525A-page 1007 SAMA5D4 SERIES 37.8.21 GMAC Specific Address 1 Top Register Name:GMAC_SAT1 Address:0xF802008C (0), 0xFC02808C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written. ADDR: Specific Address 1 The most significant bits of the destination address, that is, bits 47:32. DS60001525A-page 1008  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.22 GMAC Specific Address 2 Bottom Register Name:GMAC_SAB2 Address:0xF8020090 (0), 0xFC028090 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written. ADDR: Specific Address 2 Least significant 32 bits of the destination address, that is, bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.  2017 Microchip Technology Inc. DS60001525A-page 1009 SAMA5D4 SERIES 37.8.23 GMAC Specific Address 2 Top Register Name:GMAC_SAT2 Address:0xF8020094 (0), 0xFC028094 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written. ADDR: Specific Address 2 The most significant bits of the destination address, that is, bits 47:32. DS60001525A-page 1010  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.24 GMAC Specific Address 3 Bottom Register Name:GMAC_SAB3 Address:0xF8020098 (0), 0xFC028098 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written. ADDR: Specific Address 3 Least significant 32 bits of the destination address, that is, bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.  2017 Microchip Technology Inc. DS60001525A-page 1011 SAMA5D4 SERIES 37.8.25 GMAC Specific Address 3 Top Register Name:GMAC_SAT3 Address:0xF802009C (0), 0xFC02809C (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written. ADDR: Specific Address 3 The most significant bits of the destination address, that is, bits 47:32. DS60001525A-page 1012  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.26 GMAC Specific Address 4 Bottom Register Name:GMAC_SAB4 Address:0xF80200A0 (0), 0xFC0280A0 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written. ADDR: Specific Address 4 Least significant 32 bits of the destination address, that is, bits 31:0. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received.  2017 Microchip Technology Inc. DS60001525A-page 1013 SAMA5D4 SERIES 37.8.27 GMAC Specific Address 4 Top Register Name:GMAC_SAT4 Address:0xF80200A4 (0), 0xFC0280A4 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR The addresses stored in the Specific Address Registers are deactivated at reset or when their corresponding Specific Address Register Bottom is written. They are activated when Specific Address Register Top is written. ADDR: Specific Address 4 The most significant bits of the destination address, that is, bits 47:32. DS60001525A-page 1014  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.28 GMAC Type ID Match 1 Register Name:GMAC_TIDM1 Address:0xF80200A8 (0), 0xFC0280A8 (1) Access: Read/Write 31 ENID1 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID TID: Type ID Match 1 For use in comparisons with received frames type ID/length frames. ENID1: Enable Copying of TID Matched Frames 0: TID is not part of the comparison match. 1: TID is processed for the comparison match.  2017 Microchip Technology Inc. DS60001525A-page 1015 SAMA5D4 SERIES 37.8.29 GMAC Type ID Match 2 Register Name:GMAC_TIDM2 Address:0xF80200AC (0), 0xFC0280AC (1) Access: Read/Write 31 ENID2 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID TID: Type ID Match 2 For use in comparisons with received frames type ID/length frames. ENID2: Enable Copying of TID Matched Frames 0: TID is not part of the comparison match. 1: TID is processed for the comparison match. DS60001525A-page 1016  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.30 GMAC Type ID Match 3 Register Name:GMAC_TIDM3 Address:0xF80200B0 (0), 0xFC0280B0 (1) Access: Read/Write 31 ENID3 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID TID: Type ID Match 3 For use in comparisons with received frames type ID/length frames. ENID3: Enable Copying of TID Matched Frames 0: TID is not part of the comparison match. 1: TID is processed for the comparison match.  2017 Microchip Technology Inc. DS60001525A-page 1017 SAMA5D4 SERIES 37.8.31 GMAC Type ID Match 4 Register Name:GMAC_TIDM4 Address:0xF80200B4 (0), 0xFC0280B4 (1) Access: Read/Write 31 ENID4 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID TID: Type ID Match 4 For use in comparisons with received frames type ID/length frames. ENID4: Enable Copying of TID Matched Frames 0: TID is not part of the comparison match. 1: TID is processed for the comparison match. DS60001525A-page 1018  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.32 GMAC Wake on LAN Register Name:GMAC_WOL Address:0xF80200B8 (0), 0xFC0280B8 (1) Access: Read/Write 31 30 29 28 27 26 25 24 – 23 22 21 20 19 MTI 18 SA1 17 ARP 16 MAG 13 12 11 10 9 8 3 2 1 0 – 15 14 IP 7 6 5 4 IP IP: ARP Request IP Address Wake on LAN ARP request IP address. Written to define the least significant 16 bits of the target IP address that is matched to generate a Wake on LAN event. A value of zero will not generate an event, even if this is matched by the received frame. MAG: Magic Packet Event Enable Wake on LAN magic packet event enable. ARP: ARP Request Event Enable Wake on LAN ARP request event enable. SA1: Specific Address Register 1 Event Enable Wake on LAN Specific Address Register 1 event enable. MTI: Multicast Hash Event Enable Wake on LAN multicast hash event enable.  2017 Microchip Technology Inc. DS60001525A-page 1019 SAMA5D4 SERIES 37.8.33 GMAC IPG Stretch Register Name:GMAC_IPGS Address:0xF80200BC (0), 0xFC0280BC (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 FL 7 6 5 4 FL FL: Frame Length Bits 7:0 are multiplied with the previously transmitted frame length (including preamble). Bits 15:8 +1 divide the frame length. If the resulting number is greater than 96 and bit 28 is set in the Network Configuration Register then the resulting number is used for the transmit interpacket-gap. 1 is added to bits 15:8 to prevent a divide by zero. Refer to Section 37.6.4 “MAC Transmit Block”. DS60001525A-page 1020  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.34 GMAC Stacked VLAN Register Name:GMAC_SVLAN Address:0xF80200C0 (0), 0xFC0280C0 (1) Access: Read/Write 31 ESVLAN 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 VLAN_TYPE 7 6 5 4 VLAN_TYPE VLAN_TYPE: User Defined VLAN_TYPE Field User defined VLAN_TYPE field. When Stacked VLAN is enabled, the first VLAN tag in a received frame will only be accepted if the VLAN type field is equal to this user defined VLAN_TYPE, OR equal to the standard VLAN type (0x8100). Note that the second VLAN tag of a Stacked VLAN packet will only be matched correctly if its VLAN_TYPE field equals 0x8100. ESVLAN: Enable Stacked VLAN Processing Mode 0: Disable the stacked VLAN processing mode 1: Enable the stacked VLAN processing mode  2017 Microchip Technology Inc. DS60001525A-page 1021 SAMA5D4 SERIES 37.8.35 GMAC Transmit PFC Pause Register Name:GMAC_TPFCP Address:0xF80200C4 (0), 0xFC0280C4 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PQ 7 6 5 4 PEV PEV: Priority Enable Vector If bit 17 of the Network Control Register is written with a one then the priority enable vector of the PFC priority based pause frame will be set equal to the value stored in this register [7:0]. PQ: Pause Quantum If bit 17 of the Network Control Register is written with a one then for each entry equal to zero in the Transmit PFC Pause Register[15:8], the PFC pause frame's pause quantum field associated with that entry will be taken from the Transmit Pause Quantum Register. For each entry equal to one in the Transmit PFC Pause Register [15:8], the pause quantum associated with that entry will be zero. DS60001525A-page 1022  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.36 GMAC Specific Address 1 Mask Bottom Register Name:GMAC_SAMB1 Address:0xF80200C8 (0), 0xFC0280C8 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR ADDR: Specific Address 1 Mask Setting a bit to one masks the corresponding bit in the Specific Address 1 Register.  2017 Microchip Technology Inc. DS60001525A-page 1023 SAMA5D4 SERIES 37.8.37 GMAC Specific Address Mask 1 Top Register Name:GMAC_SAMT1 Address:0xF80200CC (0), 0xFC0280CC (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR ADDR: Specific Address 1 Mask Setting a bit to one masks the corresponding bit in the Specific Address 1 Register. DS60001525A-page 1024  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.38 GMAC 1588 Timer Nanosecond Comparison Register Name:GMAC_NSC Address:0xF80200DC (0), 0xFC0280DC (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 20 19 18 17 16 15 14 13 11 10 9 8 3 2 1 0 NANOSEC 12 NANOSEC 7 6 5 4 NANOSEC NANOSEC: 1588 Timer Nanosecond Comparison Value Value is compared to the bits [45:24] of the TSU timer count value (upper 22 bits of nanosecond value).  2017 Microchip Technology Inc. DS60001525A-page 1025 SAMA5D4 SERIES 37.8.39 GMAC 1588 Timer Second Comparison Low Register Name:GMAC_SCL Address:0xF80200E0 (0), 0xFC0280E0 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SEC 23 22 21 20 SEC 15 14 13 12 SEC 7 6 5 4 SEC SEC: 1588 Timer Second Comparison Value Value is compared to seconds value bits [31:0] of the TSU timer count value. DS60001525A-page 1026  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.40 GMAC 1588 Timer Second Comparison High Register Name:GMAC_SCH Address:0xF80200E4 (0), 0xFC0280E4 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 SEC 7 6 5 4 SEC SEC: 1588 Timer Second Comparison Value Value is compared to the top 16 bits (most significant 16 bits [47:32] of seconds value) of the TSU timer count value.  2017 Microchip Technology Inc. DS60001525A-page 1027 SAMA5D4 SERIES 37.8.41 GMAC PTP Event Frame Transmitted Seconds High Register Name: GMAC_EFTSH Address:0xF80200E8 (0), 0xFC0280E8 (1) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. An interrupt is issued when the register is updated. DS60001525A-page 1028  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.42 GMAC PTP Event Frame Received Seconds High Register Name: GMAC_EFRSH Address:0xF80200EC (0), 0xFC0280EC (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit primary event crosses the MII interface. An interrupt is issued when the register is updated.  2017 Microchip Technology Inc. DS60001525A-page 1029 SAMA5D4 SERIES 37.8.43 GMAC PTP Peer Event Frame Transmitted Seconds High Register Name: GMAC_PEFTSH Address:0xF80200F0 (0), 0xFC0280F0 (1) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. An interrupt is issued when the register is updated. DS60001525A-page 1030  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.44 GMAC PTP Peer Event Frame Received Seconds High Register Name: GMAC_PEFRSH Address:0xF80200F4 (0), 0xFC0280F4 (1) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 timer seconds register held when the SFD of a PTP transmit peer event crosses the MII interface. An interrupt is issued when the register is updated.  2017 Microchip Technology Inc. DS60001525A-page 1031 SAMA5D4 SERIES 37.8.45 GMAC Octets Transmitted Low Register Name:GMAC_OTLO Address:0xF8020100 (0), 0xFC028100 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXO 23 22 21 20 TXO 15 14 13 12 TXO 7 6 5 4 TXO When reading the Octets Transmitted and Octets Received Registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. TXO: Transmitted Octets Transmitted octets in frame without errors [31:0]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames. DS60001525A-page 1032  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.46 GMAC Octets Transmitted High Register Name:GMAC_OTHI Address:0xF8020104 (0), 0xFC028104 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXO 7 6 5 4 TXO When reading the Octets Transmitted and Octets Received Registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. TXO: Transmitted Octets Transmitted octets in frame without errors [47:32]. The number of octets transmitted in valid frames of any type. This counter is 48-bits, and is read through two registers. This count does not include octets from automatically generated pause frames.  2017 Microchip Technology Inc. DS60001525A-page 1033 SAMA5D4 SERIES 37.8.47 GMAC Frames Transmitted Register Name:GMAC_FT Address:0xF8020108 (0), 0xFC028108 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FTX 23 22 21 20 FTX 15 14 13 12 FTX 7 6 5 4 FTX FTX: Frames Transmitted without Error Frames transmitted without error. This register counts the number of frames successfully transmitted, i.e., no underrun and not too many retries. Excludes pause frames. DS60001525A-page 1034  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.48 GMAC Broadcast Frames Transmitted Register Name:GMAC_BCFT Address:0xF802010C (0), 0xFC02810C (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BFTX 23 22 21 20 BFTX 15 14 13 12 BFTX 7 6 5 4 BFTX BFTX: Broadcast Frames Transmitted without Error Broadcast frames transmitted without error. This register counts the number of broadcast frames successfully transmitted without error, i.e., no underrun and not too many retries. Excludes pause frames.  2017 Microchip Technology Inc. DS60001525A-page 1035 SAMA5D4 SERIES 37.8.49 GMAC Multicast Frames Transmitted Register Name:GMAC_MFT Address:0xF8020110 (0), 0xFC028110 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MFTX 23 22 21 20 MFTX 15 14 13 12 MFTX 7 6 5 4 MFTX MFTX: Multicast Frames Transmitted without Error This register counts the number of multicast frames successfully transmitted without error, i.e., no underrun and not too many retries. Excludes pause frames. DS60001525A-page 1036  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.50 GMAC Pause Frames Transmitted Register Name:GMAC_PFT Address:0xF8020114 (0), 0xFC028114 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PFTX 7 6 5 4 PFTX PFTX: Pause Frames Transmitted Register This register counts the number of pause frames transmitted. Only pause frames triggered by the register interface or through the external pause pins are counted as pause frames. Pause frames received through the FIFO interface are counted in the frames transmitted counter.  2017 Microchip Technology Inc. DS60001525A-page 1037 SAMA5D4 SERIES 37.8.51 GMAC 64 Byte Frames Transmitted Register Name:GMAC_BFT64 Address:0xF8020118 (0), 0xFC028118 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: 64 Byte Frames Transmitted without Error This register counts the number of 64 byte frames successfully transmitted without error, i.e., no underrun and not too many retries. Excludes pause frames. DS60001525A-page 1038  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.52 GMAC 65 to 127 Byte Frames Transmitted Register Name:GMAC_TBFT127 Address:0xF802011C (0), 0xFC02811C (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: 65 to 127 Byte Frames Transmitted without Error This register counts the number of 65 to 127 byte frames successfully transmitted without error, i.e., no underrun and not too many retries. Excludes pause frames.  2017 Microchip Technology Inc. DS60001525A-page 1039 SAMA5D4 SERIES 37.8.53 GMAC 128 to 255 Byte Frames Transmitted Register Name:GMAC_TBFT255 Address:0xF8020120 (0), 0xFC028120 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: 128 to 255 Byte Frames Transmitted without Error This register counts the number of 128 to 255 byte frames successfully transmitted without error, i.e., no underrun and not too many retries. DS60001525A-page 1040  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.54 GMAC 256 to 511 Byte Frames Transmitted Register Name:GMAC_TBFT511 Address:0xF8020124 (0), 0xFC028124 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: 256 to 511 Byte Frames Transmitted without Error This register counts the number of 256 to 511 byte frames successfully transmitted without error, i.e., no underrun and not too many retries.  2017 Microchip Technology Inc. DS60001525A-page 1041 SAMA5D4 SERIES 37.8.55 GMAC 512 to 1023 Byte Frames Transmitted Register Name:GMAC_TBFT1023 Address:0xF8020128 (0), 0xFC028128 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: 512 to 1023 Byte Frames Transmitted without Error This register counts the number of 512 to 1023 byte frames successfully transmitted without error, i.e., no underrun and not too many retries. DS60001525A-page 1042  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.56 GMAC 1024 to 1518 Byte Frames Transmitted Register Name:GMAC_TBFT1518 Address:0xF802012C (0), 0xFC02812C (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: 1024 to 1518 Byte Frames Transmitted without Error This register counts the number of 1024 to 1518 byte frames successfully transmitted without error, i.e., no underrun and not too many retries.  2017 Microchip Technology Inc. DS60001525A-page 1043 SAMA5D4 SERIES 37.8.57 GMAC Greater Than 1518 Byte Frames Transmitted Register Name:GMAC_GTBFT1518 Address:0xF8020130 (0), 0xFC028130 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFTX 23 22 21 20 NFTX 15 14 13 12 NFTX 7 6 5 4 NFTX NFTX: Greater than 1518 Byte Frames Transmitted without Error This register counts the number of 1518 or above byte frames successfully transmitted without error i.e., no underrun and not too many retries. DS60001525A-page 1044  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.58 GMAC Transmit Underruns Register Name:GMAC_TUR Address:0xF8020134 (0), 0xFC028134 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 TXUNR 0 TXUNR TXUNR: Transmit Underruns This register counts the number of frames not transmitted due to a transmit underrun. If this register is incremented then no other statistics register is incremented.  2017 Microchip Technology Inc. DS60001525A-page 1045 SAMA5D4 SERIES 37.8.59 GMAC Single Collision Frames Register Name:GMAC_SCF Address:0xF8020138 (0), 0xFC028138 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 15 14 13 12 11 10 9 8 3 2 1 0 16 SCOL SCOL 7 6 5 4 SCOL SCOL: Single Collision This register counts the number of frames experiencing a single collision before being successfully transmitted i.e., no underrun. DS60001525A-page 1046  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.60 GMAC Multiple Collision Frames Register Name:GMAC_MCF Address:0xF802013C (0), 0xFC02813C (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 15 14 13 12 11 10 9 8 3 2 1 0 16 MCOL MCOL 7 6 5 4 MCOL MCOL: Multiple Collision This register counts the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no underrun and not too many retries.  2017 Microchip Technology Inc. DS60001525A-page 1047 SAMA5D4 SERIES 37.8.61 GMAC Excessive Collisions Register Name:GMAC_EC Address:0xF8020140 (0), 0xFC028140 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 XCOL 0 XCOL XCOL: Excessive Collisions This register counts the number of frames that failed to be transmitted because they experienced 16 collisions. DS60001525A-page 1048  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.62 GMAC Late Collisions Register Name:GMAC_LC Address:0xF8020144 (0), 0xFC028144 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 LCOL 0 LCOL LCOL: Late Collisions This register counts the number of late collisions occurring after the slot time (512 bits) has expired. In 10/100 mode, late collisions are counted twice i.e., both as a collision and a late collision.  2017 Microchip Technology Inc. DS60001525A-page 1049 SAMA5D4 SERIES 37.8.63 GMAC Deferred Transmission Frames Register Name:GMAC_DTF Address:0xF8020148 (0), 0xFC028148 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 15 14 13 12 11 10 9 8 3 2 1 0 16 DEFT DEFT 7 6 5 4 DEFT DEFT: Deferred Transmission This register counts the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission. Frames involved in any collision are not counted nor are frames that experienced a transmit underrun. DS60001525A-page 1050  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.64 GMAC Carrier Sense Errors Register Name:GMAC_CSE Address:0xF802014C (0), 0xFC02814C (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 CSR 0 CSR CSR: Carrier Sense Error This register counts the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no underrun). Only incremented in half duplex mode. The only effect of a carrier sense error is to increment this register. The behavior of the other statistics registers is unaffected by the detection of a carrier sense error.  2017 Microchip Technology Inc. DS60001525A-page 1051 SAMA5D4 SERIES 37.8.65 GMAC Octets Received Low Register Name:GMAC_ORLO Address:0xF8020150 (0), 0xFC028150 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXO 23 22 21 20 RXO 15 14 13 12 RXO 7 6 5 4 RXO When reading the Octets Transmitted and Octets Received Registers, bits [31:0] should be read prior to bits [47:32] to ensure reliable operation. RXO: Received Octets Received octets in frame without errors [31:0]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered and copied to memory. DS60001525A-page 1052  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.66 GMAC Octets Received High Register Name:GMAC_ORHI Address:0xF8020154 (0), 0xFC028154 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXO 7 6 5 4 RXO When reading the Octets Transmitted and Octets Received Registers, bits 31:0 should be read prior to bits 47:32 to ensure reliable operation. RXO: Received Octets Received octets in frame without errors [47:32]. The number of octets received in valid frames of any type. This counter is 48-bits and is read through two registers. This count does not include octets from pause frames, and is only incremented if the frame is successfully filtered and copied to memory.  2017 Microchip Technology Inc. DS60001525A-page 1053 SAMA5D4 SERIES 37.8.67 GMAC Frames Received Register Name:GMAC_FR Address:0xF8020158 (0), 0xFC028158 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FRX 23 22 21 20 FRX 15 14 13 12 FRX 7 6 5 4 FRX FRX: Frames Received without Error Frames received without error. This register counts the number of frames successfully received. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. DS60001525A-page 1054  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.68 GMAC Broadcast Frames Received Register Name:GMAC_BCFR Address:0xF802015C (0), 0xFC02815C (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BFRX 23 22 21 20 BFRX 15 14 13 12 BFRX 7 6 5 4 BFRX BFRX: Broadcast Frames Received without Error Broadcast frames received without error. This register counts the number of broadcast frames successfully received. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.  2017 Microchip Technology Inc. DS60001525A-page 1055 SAMA5D4 SERIES 37.8.69 GMAC Multicast Frames Received Register Name:GMAC_MFR Address:0xF8020160 (0), 0xFC028160 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MFRX 23 22 21 20 MFRX 15 14 13 12 MFRX 7 6 5 4 MFRX MFRX: Multicast Frames Received without Error This register counts the number of multicast frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. DS60001525A-page 1056  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.70 GMAC Pause Frames Received Register Name:GMAC_PFR Address:0xF8020164 (0), 0xFC028164 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PFRX 7 6 5 4 PFRX PFRX: Pause Frames Received Register This register counts the number of pause frames received without error.  2017 Microchip Technology Inc. DS60001525A-page 1057 SAMA5D4 SERIES 37.8.71 GMAC 64 Byte Frames Received Register Name:GMAC_BFR64 Address:0xF8020168 (0), 0xFC028168 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 64 Byte Frames Received without Error This register counts the number of 64 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. DS60001525A-page 1058  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.72 GMAC 65 to 127 Byte Frames Received Register Name:GMAC_TBFR127 Address:0xF802016C (0), 0xFC02816C (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 65 to 127 Byte Frames Received without Error This register counts the number of 65 to 127 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.  2017 Microchip Technology Inc. DS60001525A-page 1059 SAMA5D4 SERIES 37.8.73 GMAC 128 to 255 Byte Frames Received Register Name:GMAC_TBFR255 Address:0xF8020170 (0), 0xFC028170 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 128 to 255 Byte Frames Received without Error This register counts the number of 128 to 255 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. DS60001525A-page 1060  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.74 GMAC 256 to 511 Byte Frames Received Register Name:GMAC_TBFR511 Address:0xF8020174 (0), 0xFC028174 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 256 to 511 Byte Frames Received without Error This register counts the number of 256 to 511 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory.  2017 Microchip Technology Inc. DS60001525A-page 1061 SAMA5D4 SERIES 37.8.75 GMAC 512 to 1023 Byte Frames Received Register Name:GMAC_TBFR1023 Address:0xF8020178 (0), 0xFC028178 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 512 to 1023 Byte Frames Received without Error This register counts the number of 512 to 1023 byte frames successfully received without error. Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. DS60001525A-page 1062  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.76 GMAC 1024 to 1518 Byte Frames Received Register Name:GMAC_TBFR1518 Address:0xF802017C (0), 0xFC02817C (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 1024 to 1518 Byte Frames Received without Error This register counts the number of 1024 to 1518 byte frames successfully received without error, i.e., no underrun and not too many retries.  2017 Microchip Technology Inc. DS60001525A-page 1063 SAMA5D4 SERIES 37.8.77 GMAC 1519 to Maximum Byte Frames Received Register Name:GMAC_TMXBFR Address:0xF8020180 (0), 0xFC028180 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 NFRX 23 22 21 20 NFRX 15 14 13 12 NFRX 7 6 5 4 NFRX NFRX: 1519 to Maximum Byte Frames Received without Error This register counts the number of 1519 byte or above frames successfully received without error. Maximum frame size is determined by the Network Configuration Register bit 8 (1536 maximum frame size) or bit 3 (jumbo frame size). Excludes pause frames, and is only incremented if the frame is successfully filtered and copied to memory. Refer to Section 37.8.2 “GMAC Network Configuration Register”. DS60001525A-page 1064  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.78 GMAC Undersized Frames Received Register Name:GMAC_UFR Address:0xF8020184 (0), 0xFC028184 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 UFRX 0 UFRX UFRX: Undersize Frames Received This register counts the number of frames received less than 64 bytes in length (10/100 mode, full duplex) that do not have either a CRC error or an alignment error.  2017 Microchip Technology Inc. DS60001525A-page 1065 SAMA5D4 SERIES 37.8.79 GMAC Oversized Frames Received Register Name:GMAC_OFR Address:0xF8020188 (0), 0xFC028188 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 OFRX 0 OFRX OFRX: Oversized Frames Received This register counts the number of frames received exceeding 1518 bytes (1536 bytes if bit 8 is set in the Network Configuration Register) in length but do not have either a CRC error, an alignment error nor a receive symbol error. Refer to Section 37.8.2 “GMAC Network Configuration Register”. DS60001525A-page 1066  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.80 GMAC Jabbers Received Register Name:GMAC_JR Address:0xF802018C (0), 0xFC02818C (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 JRX 0 JRX JRX: Jabbers Received The register counts the number of frames received exceeding 1518 bytes in length (1536 if bit 8 is set in Network Configuration Register) and have either a CRC error, an alignment error or a receive symbol error. Refer to Section 37.8.2 “GMAC Network Configuration Register”.  2017 Microchip Technology Inc. DS60001525A-page 1067 SAMA5D4 SERIES 37.8.81 GMAC Frame Check Sequence Errors Register Name:GMAC_FCSE Address:0xF8020190 (0), 0xFC028190 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 FCKR 0 FCKR FCKR: Frame Check Sequence Errors The register counts frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 is set in Network Configuration Register). This register is also incremented if a symbol error is detected and the frame is of valid length and has an integral number of bytes. This register is incremented for a frame with bad FCS, regardless of whether it is copied to memory due to ignore FCS mode being enabled in bit 26 of the Network Configuration Register. Refer to Section 37.8.2 “GMAC Network Configuration Register”. DS60001525A-page 1068  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.82 GMAC Length Field Frame Errors Register Name:GMAC_LFFE Address:0xF8020194 (0), 0xFC028194 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 LFER 0 LFER LFER: Length Field Frame Errors This register counts the number of frames received that have a measured length shorter than that extracted from the length field (bytes 13 and 14). This condition is only counted if the value of the length field is less than 0x0600, the frame is not of excessive length and checking is enabled through bit 16 of the Network Configuration Register. Refer to Section 37.8.2 “GMAC Network Configuration Register”.  2017 Microchip Technology Inc. DS60001525A-page 1069 SAMA5D4 SERIES 37.8.83 GMAC Receive Symbol Errors Register Name:GMAC_RSE Address:0xF8020198 (0), 0xFC028198 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 RXSE 0 RXSE RXSE: Receive Symbol Errors This register counts the number of frames that had GRXER asserted during reception. For 10/100 mode symbol errors are counted regardless of frame length checks. Receive symbol errors will also be counted as an FCS or alignment error if the frame is between 64 and 1518 bytes (1536 bytes if bit 8 is set in the Network Configuration Register). If the frame is larger it will be recorded as a jabber error. Refer to Section 37.8.2 “GMAC Network Configuration Register”. DS60001525A-page 1070  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.84 GMAC Alignment Errors Register Name:GMAC_AE Address:0xF802019C (0), 0xFC02819C (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 AER 0 AER AER: Alignment Errors This register counts the frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 is set in Network Configuration Register). This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes. Refer to Section 37.8.2 “GMAC Network Configuration Register”.  2017 Microchip Technology Inc. DS60001525A-page 1071 SAMA5D4 SERIES 37.8.85 GMAC Receive Resource Errors Register Name:GMAC_RRE Address:0xF80201A0 (0), 0xFC0281A0 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 15 14 13 12 11 10 9 8 3 2 1 0 16 RXRER RXRER 7 6 5 4 RXRER RXRER: Receive Resource Errors This register counts frames that are not an integral number of bytes long and have bad CRC when their length is truncated to an integral number of bytes and are between 64 and 1518 bytes in length (1536 if bit 8 is set in Network Configuration Register). This register is also incremented if a symbol error is detected and the frame is of valid length and does not have an integral number of bytes. Refer to Section 37.8.2 “GMAC Network Configuration Register”. DS60001525A-page 1072  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.86 GMAC Receive Overruns Register Name:GMAC_ROE Address:0xF80201A4 (0), 0xFC0281A4 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 6 5 4 3 2 1 RXOVR 0 RXOVR RXOVR: Receive Overruns This register counts the number of frames that are address recognized but were not copied to memory due to a receive overrun.  2017 Microchip Technology Inc. DS60001525A-page 1073 SAMA5D4 SERIES 37.8.87 GMAC IP Header Checksum Errors Register Name:GMAC_IHCE Address:0xF80201A8 (0), 0xFC0281A8 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 HCKER HCKER: IP Header Checksum Errors This register counts the number of frames discarded due to an incorrect IP header checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the Network Configuration Register) and do not have a CRC error, an alignment error, nor a symbol error. DS60001525A-page 1074  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.88 GMAC TCP Checksum Errors Register Name:GMAC_TCE Address:0xF80201AC (0), 0xFC0281AC (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TCKER TCKER: TCP Checksum Errors This register counts the number of frames discarded due to an incorrect TCP checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the Network Configuration Register) and do not have a CRC error, an alignment error, nor a symbol error.  2017 Microchip Technology Inc. DS60001525A-page 1075 SAMA5D4 SERIES 37.8.89 GMAC UDP Checksum Errors Register Name:GMAC_UCE Address:0xF80201B0 (0), 0xFC0281B0 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 UCKER UCKER: UDP Checksum Errors This register counts the number of frames discarded due to an incorrect UDP checksum, but are between 64 and 1518 bytes (1536 bytes if bit 8 is set in the Network Configuration Register) and do not have a CRC error, an alignment error, nor a symbol error. DS60001525A-page 1076  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.90 GMAC 1588 Timer Increment Sub-nanoseconds Register Name:GMAC_TISUBN Address:0xF80201BC (0), 0xFC0281BC (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 LSBTIR 7 6 5 4 LSBTIR LSBTIR: Lower Significant Bits of Timer Increment Register Lower significant bits of Timer Increment Register[15:0] giving a 24-bit timer_increment counter. These bits are the sub-ns value which the 1588 timer will be incremented each clock cycle. Bit n = 2(n-16) nsec giving a resolution of approximately 15.2E-15 sec.  2017 Microchip Technology Inc. DS60001525A-page 1077 SAMA5D4 SERIES 37.8.91 GMAC 1588 Timer Seconds High Register Name:GMAC_TSH Address:0xF80201C0 (0), 0xFC0281C0 (1) Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TCS 7 6 5 4 TCS TCS: Timer Count in Seconds This register is writable. It increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented when the Timer Adjust Register is written. DS60001525A-page 1078  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.92 GMAC 1588 Timer Seconds Low Register Name:GMAC_TSL Address:0xF80201D0 (0), 0xFC0281D0 (1) Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TCS 23 22 21 20 TCS 15 14 13 12 TCS 7 6 5 4 TCS TCS: Timer Count in Seconds This register is writable. It increments by one when the 1588 nanoseconds counter counts to one second. It may also be incremented when the Timer Adjust Register is written.  2017 Microchip Technology Inc. DS60001525A-page 1079 SAMA5D4 SERIES 37.8.93 GMAC 1588 Timer Nanoseconds Register Name:GMAC_TN Address:0xF80201D4 (0), 0xFC0281D4 (1) Access: Read/Write 31 – 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TNS 20 TNS 15 14 13 12 TNS 7 6 5 4 TNS TNS: Timer Count in Nanoseconds This register is writable. It can also be adjusted by writes to the 1588 Timer Adjust Register. It increments by the value of the 1588 Timer Increment Register each clock cycle. DS60001525A-page 1080  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.94 GMAC 1588 Timer Adjust Register Name:GMAC_TA Address:0xF80201D8 (0), 0xFC0281D8 (1) Access: Write-only 31 ADJ 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ITDT 20 ITDT 15 14 13 12 ITDT 7 6 5 4 ITDT ITDT: Increment/Decrement The number of nanoseconds to increment or decrement the 1588 Timer Nanoseconds Register. If necessary, the 1588 Seconds Register will be incremented or decremented. ADJ: Adjust 1588 Timer Write as one to subtract from the 1588 timer. Write as zero to add to it.  2017 Microchip Technology Inc. DS60001525A-page 1081 SAMA5D4 SERIES 37.8.95 GMAC 1588 Timer Increment Register Name:GMAC_TI Address:0xF80201DC (0), 0xFC0281DC (1) Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 NIT 15 14 13 12 ACNS 7 6 5 4 CNS CNS: Count Nanoseconds A count of nanoseconds by which the 1588 Timer Nanoseconds Register will be incremented each clock cycle. ACNS: Alternative Count Nanoseconds Alternative count of nanoseconds by which the 1588 Timer Nanoseconds Register will be incremented each clock cycle. NIT: Number of Increments The number of increments after which the alternative increment is used. DS60001525A-page 1082  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.96 GMAC PTP Event Frame Transmitted Seconds Low Register Name:GMAC_EFTSL Address:0xF80201E0 (0), 0xFC0281E0 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 23 22 21 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Seconds Register holds when the SFD of a PTP transmit primary event crosses the MII interface. An interrupt is issued when the register is updated.  2017 Microchip Technology Inc. DS60001525A-page 1083 SAMA5D4 SERIES 37.8.97 GMAC PTP Event Frame Transmitted Nanoseconds Register Name:GMAC_EFTN Address:0xF80201E4 (0), 0xFC0281E4 (1) Access: Read-only 31 – 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Nanoseconds Register holds when the SFD of a PTP transmit primary event crosses the MII interface. An interrupt is issued when the register is updated. DS60001525A-page 1084  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.98 GMAC PTP Event Frame Received Seconds Low Register Name:GMAC_EFRSL Address:0xF80201E8 (0), 0xFC0281E8 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 23 22 21 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Seconds Register holds when the SFD of a PTP receive primary event crosses the MII interface. An interrupt is issued when the register is updated.  2017 Microchip Technology Inc. DS60001525A-page 1085 SAMA5D4 SERIES 37.8.99 GMAC PTP Event Frame Received Nanoseconds Register Name:GMAC_EFRN Address:0xF80201EC (0), 0xFC0281EC (1) Access: Read-only 31 – 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Nanoseconds Register holds when the SFD of a PTP receive primary event crosses the MII interface. An interrupt is issued when the register is updated. DS60001525A-page 1086  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.100 GMAC PTP Peer Event Frame Transmitted Seconds Low Register Name:GMAC_PEFTSL Address:0xF80201F0 (0), 0xFC0281F0 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 23 22 21 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Seconds Register holds when the SFD of a PTP transmit peer event crosses the MII interface. An interrupt is issued when the register is updated.  2017 Microchip Technology Inc. DS60001525A-page 1087 SAMA5D4 SERIES 37.8.101 GMAC PTP Peer Event Frame Transmitted Nanoseconds Register Name:GMAC_PEFTN Address:0xF80201F4 (0), 0xFC0281F4 (1) Access: Read-only 31 – 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Nanoseconds Register holds when the SFD of a PTP transmit peer event crosses the MII interface. An interrupt is issued when the register is updated. DS60001525A-page 1088  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.102 GMAC PTP Peer Event Frame Received Seconds Low Register Name:GMAC_PEFRSL Address:0xF80201F8 (0), 0xFC0281F8 (1) Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 23 22 21 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Seconds Register holds when the SFD of a PTP receive primary event crosses the MII interface. An interrupt is issued when the register is updated.  2017 Microchip Technology Inc. DS60001525A-page 1089 SAMA5D4 SERIES 37.8.103 GMAC PTP Peer Event Frame Received Nanoseconds Register Name:GMAC_PEFRN Address:0xF80201FC (0), 0xFC0281FC (1) Access: Read-only 31 – 30 – 29 23 22 21 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RUD 20 RUD 15 14 13 12 RUD 7 6 5 4 RUD RUD: Register Update The register is updated with the value that the 1588 Timer Nanoseconds Register holds when the SFD of a PTP receive primary event crosses the MII interface. An interrupt is issued when the register is updated. DS60001525A-page 1090  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.104 GMAC Received LPI Transitions Name:GMAC_RXLPI Address:0xF8020270 (0), 0xFC028270 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 COUNT 7 6 5 4 COUNT COUNT: Count of RX LPI transitions (cleared on read) A count of the number of times there is a transition from receiving normal idle to receiving low power idle.  2017 Microchip Technology Inc. DS60001525A-page 1091 SAMA5D4 SERIES 37.8.105 GMAC Received LPI Time Name:GMAC_RXLPITIME Address:0xF8020274 (0), 0xFC028274 (1) Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 LPITIME 15 14 13 12 LPITIME 7 6 5 4 LPITIME LPITIME: Time in LPI (cleared on read) This field increments once every 16 PCLK cycles when the bit LPI Indication (bit 7) is set in the Network Status register. DS60001525A-page 1092  2017 Microchip Technology Inc. SAMA5D4 SERIES 37.8.106 GMAC Transmit LPI Transitions Name:GMAC_TXLPI Address:0xF8020278 (0), 0xFC028278 (1) Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 COUNT 7 6 5 4 COUNT COUNT: Count of LPI transitions (cleared on read) A count of the number of times the bit Enable LPI Transmission (bit 19) goes from low to high in the Network Control register.  2017 Microchip Technology Inc. DS60001525A-page 1093 SAMA5D4 SERIES 37.8.107 GMAC Transmit LPI Time Name:GMAC_TXLPITIME Address:0xF802027C (0), 0xFC02827C (1) Access: Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 LPITIME 15 14 13 12 LPITIME 7 6 5 4 LPITIME LPITIME: Time in LPI (cleared on read) This field increments once every 16 PCLK cycles when the bit Enable LPI Transmission (bit 19) is set in the Network Control register. DS60001525A-page 1094  2017 Microchip Technology Inc. SAMA5D4 SERIES 38. High Speed Multimedia Card Interface (HSMCI) 38.1 Description The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD Memory Card Specification V2.0, the SDIO V2.0 specification and CE-ATA V1.1. The HSMCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The HSMCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 1 slot(s). Each slot may be used to interface with a High Speed MultiMedia Card bus (up to 30 Cards) or with an SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the High Speed MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports High Speed MultiMedia Card operations. The main differences between SD and High Speed MultiMedia Cards are the initialization process and the bus topology. HSMCI fully supports CE-ATA Revision 1.1, built on the MMC System Specification v4.0. The module includes dedicated hardware to issue the command completion signal and capture the host command completion signal disable. 38.2 • • • • • • • • • • • • • Embedded Characteristics Compatible with MultiMedia Card Specification Version 4.3 Compatible with SD Memory Card Specification Version 2.0 Compatible with SDIO Specification Version 2.0 Compatible with CE-ATA Specification 1.1 Cards Clock Rate Up to Master Clock Divided by 2 Boot Operation Mode Support High Speed Mode Support Embedded Power Management to Slow Down Clock Rate When Not Used Supports 1 Multiplexed Slot(s) - Each Slot for either a High Speed MultiMedia Card Bus (Up to 30 Cards) or an SD Memory Card Support for Stream, Block and Multi-block Data Read and Write - Minimizes Processor Intervention for Large Buffer Transfers Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental Access Support for CE-ATA Completion Signal Disable Command Protection Against Unexpected Modification On-the-Fly of the Configuration Registers  2017 Microchip Technology Inc. DS60001525A-page 1095 SAMA5D4 SERIES 38.3 Block Diagram Figure 38-1: Block Diagram APB Bridge DMAC APB MCCK(1) MCCDA(1) MCDA0(1) PMC MCK MCDA1(1) MCDA2(1) MCDA3(1) MCCDB(1) HSMCI Interface PIO MCDB0(1) MCDB1(1) MCDB2(1) MCDB3(1) MCDB4(1) MCDB5(1) MCDB6(1) Interrupt Control MCDB7(1) HSMCI Interrupt Note 1: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCCDB to HSMCIx_CDB, MCDAy to HSMCIx_DAy, MCDBy to HSMCIx_DBy. DS60001525A-page 1096  2017 Microchip Technology Inc. SAMA5D4 SERIES 38.4 Application Block Diagram Figure 38-2: Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer HSMCI Interface 1 2 3 4 5 6 7 1 2 3 4 5 6 78 9 9 10 11 1213 8 MMC 38.5 SDCard Pin Name List Table 38-1: I/O Lines Description for 8-bit Configuration Pin Name(1) Pin Description Type(2) Comments MCCDA/MCCDB Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0–MCDA7 Data 0..7 of Slot A I/O/PP MCDB0–MCDB7 Data 0..7 of Slot B I/O/PP DAT[0..7] of an MMC DAT[0..3] of an SD Card/SDIO DAT[0..7] of an MMC DAT[0..3] of an SD Card/SDIO Note 1: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCCDB to HSMCIx_CDB, MCCDC to HSMCIx_CDC, MCCDD to HSMCIx_CDD, MCDAy to HSMCIx_DAy, MCDBy to HSMCIx_DBy, MCDCy to HSMCIx_DCy, MCDDy to HSMCIx_DDy. 2: I: Input, O: Output, PP: Push/Pull, OD: Open Drain.  2017 Microchip Technology Inc. DS60001525A-page 1097 SAMA5D4 SERIES Table 38-2: I/O Lines Description for 4-bit Configuration (1) Pin Name Pin Description Type(2) Comments MCCDA/MCCDB Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0–MCDA3 Data 0..3 of Slot A I/O/PP DAT[0..3] of an MMC DAT[0..3] of an SD Card/SDIO Note 1: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy. 2: I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 38.6 Product Dependencies 38.6.1 I/O Lines The pins used for interfacing the High Speed MultiMedia Cards or SD Cards are multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to HSMCI pins. Table 38-3: I/O Lines Instance Signal I/O Line Peripheral HSMCI0 MCI0_CDA PC5 B HSMCI0 MCI0_CDB PE0 B HSMCI0 MCI0_CK PC4 B HSMCI0 MCI0_DA0 PC6 B HSMCI0 MCI0_DA1 PC7 B HSMCI0 MCI0_DA2 PC8 B HSMCI0 MCI0_DA3 PC9 B HSMCI0 MCI0_DA4 PC10 B HSMCI0 MCI0_DA5 PC11 B HSMCI0 MCI0_DA6 PC12 B HSMCI0 MCI0_DA7 PC13 B HSMCI0 MCI0_DB0 PE1 B HSMCI0 MCI0_DB1 PE2 B HSMCI0 MCI0_DB2 PE3 B HSMCI0 MCI0_DB3 PE4 B HSMCI1 MCI1_CDA PE19 C HSMCI1 MCI1_CK PE18 C HSMCI1 MCI1_DA0 PE20 C HSMCI1 MCI1_DA1 PE21 C HSMCI1 MCI1_DA2 PE22 C HSMCI1 MCI1_DA3 PE23 C DS60001525A-page 1098  2017 Microchip Technology Inc. SAMA5D4 SERIES 38.6.2 Power Management The HSMCI is clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the HSMCI clock. 38.6.3 Interrupt Sources The HSMCI has an interrupt line connected to the interrupt controller. Handling the HSMCI interrupt requires programming the interrupt controller before configuring the HSMCI. Table 38-4: 38.7 Peripheral IDs Instance ID HSMCI0 35 HSMCI1 36 Bus Topology Figure 38-3: High Speed MultiMedia Memory Card Bus Topology 1 2 3 4 5 6 7 9 10 11 1213 8 MMC The High Speed MultiMedia Card communication is based on a 13-pin serial bus interface. It has three communication lines and four supply lines. Table 38-5: Bus Topology Description HSMCI Pin Name(2) (Slot z) Pin Number Name Type(1) 1 DAT[3] I/O/PP Data MCDz3 2 CMD I/O/PP/OD Command/response MCCDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I/O Clock MCCK 6 VSS2 S Supply voltage ground VSS 7 DAT[0] I/O/PP Data 0 MCDz0 8 DAT[1] I/O/PP Data 1 MCDz1 9 DAT[2] I/O/PP Data 2 MCDz2  2017 Microchip Technology Inc. DS60001525A-page 1099 SAMA5D4 SERIES Table 38-5: Bus Topology (Continued) Pin Number Name Type Description HSMCI Pin Name(2) (Slot z) 10 DAT[4] I/O/PP Data 4 MCDz4 11 DAT[5] I/O/PP Data 5 MCDz5 12 DAT[6] I/O/PP Data 6 MCDz6 13 DAT[7] I/O/PP Data 7 MCDz7 (1) Note 1: I: Input, O: Output, PP: Push/Pull, OD: Open Drain, S: Supply 2: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCCDB to HSMCIx_CDB, MCDAy to HSMCIx_DAy, MCDBy to HSMCIx_DBy. Figure 38-4: MMC Bus Connections (One Slot) HSMCI MCDA0 MCCDA MCCK 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 9 10 11 9 10 11 9 10 11 1213 8 MMC1 Note: 1213 8 MMC2 1213 8 MMC3 When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. Figure 38-5: SD Memory Card Bus Topology 1 2 3 4 56 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 38-6. Table 38-6: SD Memory Card Bus Signals Pin Number Name Type Description HSMCI Pin Name(2) (Slot z) 1 CD/DAT[3] I/O/PP Card detect/ Data line Bit 3 MCDz3 2 CMD PP Command/response MCCDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I/O Clock MCCK 6 VSS2 S Supply voltage ground VSS DS60001525A-page 1100 (1)  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 38-6: SD Memory Card Bus Signals (Continued) Pin Number Name Type Description HSMCI Pin Name(2) (Slot z) 7 DAT[0] I/O/PP Data line Bit 0 MCDz0 8 DAT[1] I/O/PP Data line Bit 1 or Interrupt MCDz1 9 DAT[2] I/O/PP Data line Bit 2 MCDz2 (1) Note 1: I: input, O: output, PP: Push Pull, OD: Open Drain. 2: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCCDB to HSMCIx_CDB, MCDAy to HSMCIx_DAy, MCDBy to HSMCIx_DBy. SD Card Bus Connections with One Slot MCDA0 - MCDA3 MCCK SD CARD 9 MCCDA 1 2 3 4 5 6 78 Figure 38-6: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA MCDAy to HSMCIx_DAy. Figure 38-7: SD Card Bus Connections with Two Slots MCDA0 - MCDA3 MCCK SD CARD 1 MCDB0 - MCDB3 SD CARD 2 9 MCCDB 12 3 4 5 678 9 MCCDA 12 3 4 5 678 Note: Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK,MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy, MCCDB to HSMCIx_CDB, MCDBy to HSMCIx_DBy.  2017 Microchip Technology Inc. DS60001525A-page 1101 SAMA5D4 SERIES Figure 38-8: Mixing High Speed MultiMedia and SD Memory Cards with Two Slots MCDA0 - MCDA7 MCCDA MCCK 1 2 3 4 5 6 7 1 2 3 4 5 6 7 1 2 3 4 5 6 7 9 10 11 9 10 11 9 10 11 1213 8 MCDB0 - MCDB3 MMC2 1213 8 MMC3 SD CARD 9 MCCDB 1 2 3 4 5 6 78 MMC1 1213 8 Note: When several HSMCI (x HSMCI) are embedded in a product, MCCK refers to HSMCIx_CK, MCCDA to HSMCIx_CDA, MCDAy to HSMCIx_DAy, MCCDB to HSMCIx_CDB, MCDBy to HSMCIx_DBy. When the HSMCI is configured to operate with SD memory cards, the width of the data bus can be selected in the HSMCI_SDCR. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of High Speed MultiMedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs. 38.8 High Speed MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based High Speed MultiMedia Card bus protocol. Each message is represented by one of the following tokens: • Command—A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. • Response—A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line. • Data—Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the High Speed MultiMedia Card System Specification. Refer to Table 38-7. High Speed MultiMedia Card bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock HSMCI clock. Two types of data transfer commands are defined: • Sequential commands—These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. • Block-oriented commands—These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a predefined block count (refer to Section 38.8.2 “Data Transfer Operation”). The HSMCI provides a set of registers to perform the entire range of High Speed MultiMedia Card operations. DS60001525A-page 1102  2017 Microchip Technology Inc. SAMA5D4 SERIES 38.8.1 Command - Response Operation After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the HSMCI_CR. The PWSEN bit saves power by dividing the HSMCI clock by 2PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow stopping the HSMCI clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMedia Card System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the HSMCI Command Register (HSMCI_CMDR). The HSMCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: NID Cycles Host Command CMD S T Content CRC E Z ****** High Impedance State Response Z S T CID Content Z Z Z The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR are described in Table 38-7 and Table 38-8. Table 38-7: CMD Index CMD2 ALL_SEND_CID Command Description Type bcr(1 ) Argument Response Abbreviation Command Description [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line Note 1: bcr means broadcast command with response. Table 38-8: Fields and Values for HSMCI_CMDR Field Value CMDNB (command number) 2 (CMD2) RSPTYP (response type) 2 (R2: 136 bits response) SPCMD (special command) 0 (not a special command) OPCMD (open drain command) 1 MAXLAT (max latency for command to response) 0 (NID cycles ==> 5 cycles) TRCMD (transfer command) 0 (No transfer) TRDIR (transfer direction) X (available only in transfer command) TRTYP (transfer type) X (available only in transfer command) IOSPCMD (SDIO special command) 0 (not a special command) The HSMCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps: • Fill the argument register (HSMCI_ARGR) with the command argument. • Set the command register (HSMCI_CMDR) (refer to Table 38-8). The command is sent immediately after writing the command register. While the card maintains a busy indication (at the end of a STOP_TRANSMISSION command CMD12, for example), a new command shall not be sent. The NOTBUSY flag in the Status Register (HSMCI_SR) is asserted when the card releases the busy indication. If the command requires a response, it can be read in the HSMCI Response Register (HSMCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The HSMCI embeds an error detection to prevent any corrupted data during the transfer.  2017 Microchip Technology Inc. DS60001525A-page 1103 SAMA5D4 SERIES The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the HSMCI Interrupt Enable Register (HSMCI_IER) allows using an interrupt method. Figure 38-9: Command/Response Functional Flow Diagram Set the command argument HSMCI_ARGR = Argument(1) Set the command HSMCI_CMDR = Command Read HSMCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? RETURN ERROR(1) Read response if required Does the command involve a busy indication? No RETURN OK Read HSMCI_SR 0 NOTBUSY 1 RETURN OK Note: If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the High Speed MultiMedia Card specification). DS60001525A-page 1104  2017 Microchip Technology Inc. SAMA5D4 SERIES 38.8.2 Data Transfer Operation The High Speed MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kinds of transfer can be selected setting the Transfer Type (TRTYP) field in the HSMCI Command Register (HSMCI_CMDR). In all cases, the block length (BLKLEN field) must be defined either in the HSMCI Mode Register (HSMCI_MR) or in the HSMCI Block Register (HSMCI_BLKR). This field determines the size of the data block. Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): • Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received. • Multiple block read (or write) with predefined block count (since version 3.1 and higher): The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with predefined block count, the host must correctly program the HSMCI Block Register (HSMCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT field of the HSMCI_BLKR defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer. 38.8.3 Read Operation The following flowchart (Figure 38-10) shows how to read a single block with or without use of DMAC facilities. In this example, a polling method is used to wait for the end of read. Similarly, the user can configure the HSMCI Interrupt Enable Register (HSMCI_IER) to trigger an interrupt at the end of read.  2017 Microchip Technology Inc. DS60001525A-page 1105 SAMA5D4 SERIES Figure 38-10: Read Functional Flow Diagram Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command(1) No Yes Read with DMAC Reset the DMAEN bit HSMCI_DMA &= ~DMAEN Set the block length (in bytes) HSMCI_BLKR l= (BlockLength1 0 SYNC OVER Selected Clock 0 0 Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 Warning: When the value of US_BRGR.FP is greater than 0, the SCK (oversampling clock) generates nonconstant duty cycles. The SCK high duration is increased by “selected clock” period from time to time. The duty cycle depends on the value of USART_BRGR.CD. 44.6.1.3 Baud Rate in Synchronous Mode or SPI Mode If the USART is programmed to operate in Synchronous mode, the selected clock is divided by the value of US_BRGR.CD. Selected Clock Baud Rate = -----------------------------------CD In Synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 3 times lower than the system clock. In Master mode, Synchronous mode (USCLKS = 0 or 1, CLKO set to 1), the receive part limits the SCK maximum frequency to Selected Clock/3 in USART mode, or Selected Clock/6 in SPI mode. When either the external clock SCK or the internal clock divided (peripheral clock/DIV) is selected, the value of CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. When the peripheral clock is selected, the baud rate generator ensures a 50:50 duty cycle on the SCK pin, even if the value of CD is odd.  2017 Microchip Technology Inc. DS60001525A-page 1299 SAMA5D4 SERIES 44.6.1.4 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ------ × f Fi where: • • • • B is the bit rate Di is the bit-rate adjustment factor Fi is the clock frequency division factor f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 44-5. Table 44-5: Binary and Decimal Values for Di DI field 0001 0010 0011 0100 0101 0110 1000 1001 1 2 4 8 16 32 12 20 Di (decimal) Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 44-6. Table 44-6: Binary and Decimal Values for Fi FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 Fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 Table 44-7 shows the resulting Fi/Di ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 44-7: Possible Values for the Fi/Di Ratio Fi/Di 372 558 744 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4 If the USART is configured in ISO7816 mode, the clock selected by US_MR.USCLKS is first divided by the value programmed in US_BRGR.CD. The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the US_MR.CLKO bit can be written to ‘1’. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI DI Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 65535 in ISO7816 mode. The noninteger values of the Fi/Di ratio are not supported and the user must program FI_DI_RATIO to a value as close as possible to the expected value. FI_DI_RATIO resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 44-4 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. DS60001525A-page 1300  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 44-4: Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 44.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by writing a ‘1’ to US_CR.TXEN. However, the transmitter registers can be programmed before being enabled. The receiver and the transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by writing a ‘1’ to the corresponding bit US_CR.RSTRX and US_CR.RSTTX respectively. The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by writing a ‘1’ to US_CR.RXDIS and US_CR.TXDIS, respectively. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding register (US_THR). If a timeguard is programmed, it is handled normally. 44.6.3 44.6.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both Synchronous and Asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is configured in the US_MR.CHRL and the US_MR.MODE9. Nine bits are selected by writing a ‘1’ to US_MR.MODE9 regardless of the CHRL field. The parity is selected by US_MR.PAR. Even, odd, space, marked or none parity bit can be configured. US_MR.MSBF configures which data bit is sent first. If written to ‘1’, the most significant bit is sent first. If written to ‘0’, the less significant bit is sent first. The number of stop bits is selected by US_MR.NBSTOP. The 1.5 stop bit is supported in Asynchronous mode only. Figure 44-5: Character Transmit Example: 8-bit, Parity Enabled, One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in US_THR. The transmitter reports two status bits in the Channel Status register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty, and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift register of the transmitter and US_THR becomes empty, thus TXRDY rises.  2017 Microchip Technology Inc. DS60001525A-page 1301 SAMA5D4 SERIES Both TXRDY and TXEMPTY are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. Figure 44-6: Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 44.6.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, write a ‘1’ to USART_MR.MAN. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of a Manchester-encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. Figure 44-7 illustrates this coding scheme. Figure 44-7: NRZ to Manchester Encoding NRZ Encoded Data 1 0 1 1 0 0 0 1 Manchester Encoded TXD Data The Manchester-encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a predefined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE by configuring US_MAN.TX_PP. US_MAN.TX_PL is used to configure the preamble length. Figure 44-8 illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using US_MAN.TX_MPOL. If TX_MPOL is set to ‘0’ (default), a logic zero is encoded with a zero-toone transition and a logic one is encoded with a one-to-zero transition. If TX_MPOL is set to ‘1’, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. DS60001525A-page 1302  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 44-8: Preamble Patterns, Default Polarity Assumed Manchester Encoded Data TXD SFD DATA SFD DATA SFD DATA SFD DATA 8-bit "ALL_ONE" Preamble Manchester Encoded Data TXD 8-bit "ALL_ZERO" Preamble Manchester Encoded Data TXD 8-bit "ZERO_ONE" Preamble Manchester Encoded Data TXD 8-bit "ONE_ZERO" Preamble A start frame delimiter is configured using US_MR.ONEBIT. It consists of a user-defined pattern that indicates the beginning of a valid data. Figure 44-9 illustrates these patterns. If the start frame delimiter, also known as the start bit, is one bit, (ONEBIT = 1), a logic zero is Manchester-encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT = 0), a sequence of three bit times is sent serially on the line to indicate the start of a new character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If US_MR.MODSYNC is written to ‘1’, the next character is a command. If it is written to ‘0’, the next character is a data. When direct memory access is used, MODSYNC can be immediately updated with a modified character located in memory. To enable this mode, US_MR.VAR_SYNC must be written to ‘1’. In this case, MODSYNC is bypassed and the sync configuration is held in US_THR.TXSYNH. The USART character format is modified and includes sync information. Figure 44-9: Start Frame Delimiter Preamble Length is set to 0 SFD Manchester Encoded Data DATA TXD SFD Manchester Encoded Data DATA TXD SFD Manchester Encoded Data TXD One bit start frame delimiter Command Sync start frame delimiter DATA Data Sync start frame delimiter  2017 Microchip Technology Inc. DS60001525A-page 1303 SAMA5D4 SERIES • Drift Compensation Drift compensation is available only in 16X Oversampling mode. A hardware recovery system allows a larger clock drift. To enable the hardware system, USART_MAN.DRIFT must be written to ‘1’. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective action is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken. Figure 44-10: Bit Resynchronization Oversampling 16X Clock RXD Sampling point Expected edge Synchro Error 44.6.3.3 Synchro Jump Tolerance Synchro Jump Synchro Error Asynchronous Receiver If the USART is programmed in Asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the baud rate clock, depending on the value of US_MR.OVER. The receiver samples the RXD line. If the line is sampled during one-half of a bit time to 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16 (OVER = 0), a start is detected at the eighth sample to 0. Data bits, parity bit and stop bit are assumed to have a duration corresponding to 16 oversampling clock cycles. If the oversampling is 8 (OVER = 1), a start bit is detected at the fourth sample to 0. Data bits, parity bit and stop bit are assumed to have a duration corresponding to 8 oversampling clock cycles. The number of data bits, first bit sent and Parity mode are selected by the same fields and bits as the transmitter, i.e., respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 44-11 and Figure 44-12 illustrate start detection and character reception when USART operates in Asynchronous mode. DS60001525A-page 1304  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 44-11: Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 Figure 44-12: 2 3 4 5 6 7 0 1 Start Rejection Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 44.6.3.4 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit Manchester Decoder When US_MR.MAN is ‘1’, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester-encoded input data. An optional preamble sequence can be defined, and its length is user-defined and totally independent of the transmitter side. The length of the preamble sequence is configured using US_MAN.RX_PL. If RX_PL is ‘0’, no preamble is detected and the function is disabled. The polarity of the input stream is configured with US_MAN.RX_MPOL. Depending on the desired application, the preamble pattern matching is to be defined via the US_MAN. Refer to Figure 44-8 for available preamble patterns. Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. If US_MR.ONEBIT is written to ‘1’, only a zero-encoded Manchester can be detected as a valid start frame delimiter. If US_MR.ONEBIT is written to ‘0’, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time to zero, a start bit is detected. Refer to Figure 44-13. The sample pulse rejection mechanism applies.  2017 Microchip Technology Inc. DS60001525A-page 1305 SAMA5D4 SERIES Figure 44-13: Asynchronous Start Bit Detection Sampling Clock (16X) Manchester Encoded Data TXD Start Detection 1 2 3 4 The receiver is activated and starts preamble and frame delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver resynchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time. If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into NRZ data and passed to the USART for processing. Figure 44-14 illustrates Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, the US_CSR.MANERR flag is raised. It is cleared by writing a ‘1’ to US_CR.RSTSTA. Refer to Figure 44-15 for an example of Manchester error detection during data phase. Figure 44-14: Preamble Pattern Mismatch Preamble Mismatch Manchester coding error Manchester Encoded Data Preamble Mismatch invalid pattern SFD TXD DATA Preamble Length is set to 8 Figure 44-15: Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester Encoded Data TXD Entering USART character area Sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded Manchester Coding Error detected When the start frame delimiter is a sync pattern (US_MR.ONEBIT = 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written in RXCHR in the Receive Holding register (US_RHR) and RXSYNH is updated. RXSYNH is set to ‘1’ when the received character is a command, and to ‘0’ if the received character is a data. This alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. As the decoder is setup to be used in Unipolar mode, the first bit of the frame has to be a zero-to-one transition. DS60001525A-page 1306  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.6.3.5 Radio Interface: Manchester-Encoded USART Application This section describes low data rate RF transmission systems and their integration with a Manchester-encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes. The goal is to perform full duplex radio transmission of characters using two different frequency carriers. Refer to the configuration in Figure 44-16. Figure 44-16: Manchester-Encoded Characters RF Transmission fUP Frequency Carrier ASK/FSK Upstream Receiver Upstream Transmitter LNA VCO RF filter Demod Control fDOWN Frequency Carrier Serial Configuration Interface bi-dir line ASK/FSK Downstream Transmitter Downstream Receiver Manchester Decoder USART Receiver Manchester Encoder USART Transmitter PA RF filter Mod VCO Control The USART peripheral is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchesterencoded characters are serially sent to the RF transmitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. Refer to Figure 44-17 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic one is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a zero. Refer to Figure 44-18. From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver switches to Receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration. Figure 44-17: ASK Modulator Output 1 0 0 1 NRZ Stream Manchester Encoded Data Default Polarity Unipolar Output TXD ASK Modulator Output Upstream Frequency F0  2017 Microchip Technology Inc. DS60001525A-page 1307 SAMA5D4 SERIES Figure 44-18: FSK Modulator Output 1 0 0 1 NRZ Stream Manchester Encoded Data Default Polarity Unipolar Output TXD FSK Modulator Output Upstream Frequencies [F0, F0+offset] 44.6.3.6 Synchronous Receiver In Synchronous mode (US_MR.SYNC = 1), the receiver samples the RXD signal on each rising edge of the baud rate clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high-speed transfer capability. Configuration fields and bits are the same as in Asynchronous mode. Figure 44-19 illustrates a character reception in Synchronous mode. Figure 44-19: Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit Parity Bit 44.6.3.7 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding register (US_RHR) and US_CSR.RXRDY rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing a ‘1’ to US_CR.RSTSTA. DS60001525A-page 1308  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 44-20: Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 44.6.3.8 Parity The USART supports five Parity modes. The PAR field also enables Multidrop mode (refer to Section 44.6.3.9 “Multidrop Mode”). Even and odd parity bit generation and error detection are supported. The configuration is done in US_MR.PAR. If even parity is selected, the parity generator of the transmitter drives the parity bit to 0 if a number of 1s in the character data bit is even, and to 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit to 1 if a number of 1s in the character data bit is even, and to 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit to 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 0. If the space parity is used, the parity generator of the transmitter drives the parity bit to 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled to 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 44-8 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits set to 1 in the character value, the parity bit is set to ‘1’ when the parity is odd, or configured to ‘0’ when the parity is even. Table 44-8: Parity Bit Examples Character Hexadecimal Binary Parity Bit Parity Mode A 0x41 0100 0001 1 Odd A 0x41 0100 0001 0 Even A 0x41 0100 0001 1 Mark A 0x41 0100 0001 0 Space A 0x41 0100 0001 None None When the receiver detects a parity error, it sets US_CSR.PARE (Parity Error). PARE can be cleared by writing a ‘1’ to the RSTSTA bit the US_CR. Figure 44-21 illustrates the parity bit status setting and clearing.  2017 Microchip Technology Inc. DS60001525A-page 1309 SAMA5D4 SERIES Figure 44-21: Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE Parity Error Detect Time Flags Report Time RXRDY 44.6.3.9 Multidrop Mode If the value 0x6 or 0x07 is written to US_MR.PAR, the USART runs in Multidrop mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in Multidrop mode, the receiver sets PARE when the parity bit is high and the transmitter is able to send a character with the parity bit high when a ‘1’ is written to US_CR.SENTA. To handle parity error, PARE is cleared when a ‘1’ is written to US_CR.RSTSTA. The transmitter sends an address byte (parity bit set) when US_CR.SENDA = 1. In this case, the next byte written to US_THR is transmitted as an address. Any character written in the US_THR without having written SENDA is transmitted normally with the parity at 0. 44.6.3.10 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard register (US_TTGR). When this field is written to ‘0’, no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 44-22, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. DS60001525A-page 1310  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 44-22: Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Table 44-9 indicates the maximum length of a timeguard period that the transmitter can handle depending on the baud rate. Table 44-9: Maximum Timeguard Length Depending on Baud Rate Baud Rate (bit/s) Bit Time (µs) Timeguard (ms) 1,200 833 212.50 9,600 104 26.56 14,400 69.4 17.71 19,200 52.1 13.28 28,800 34.7 8.85 38,400 26 6.63 56,000 17.9 4.55 57,600 17.4 4.43 115,200 8.7 2.21 44.6.3.11 Receiver Timeout The Receiver Timeout provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a timeout is detected, US_CSR.TIMEOUT rises and can generate an interrupt, thus indicating to the driver an end of frame. The timeout delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Timeout register (US_RTOR). If TO is written to ‘0’, the Receiver Timeout is disabled and no timeout is detected. US_CSR.TIMEOUT remains at ‘0’. Otherwise, the receiver loads a 16-bit counter with the value programmed in US_RTOR.TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, TIMEOUT rises. Then, the user can either: • Stop the counter clock until a new character is received. This is performed by writing a ‘1’ to US_CR.STTTO. In this case, the idle state on RXD before a new character is received will not provide a timeout. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. • Obtain an interrupt while no character is received. This is performed by writing a ‘1’ to the RETTO (Reload and Start Timeout) bit in the US_CR. In this case, the counter starts counting down immediately from the value TO. This generates a periodic interrupt so that a user timeout can be handled, for example when no key is pressed on a keyboard. Figure 44-23 shows the block diagram of the Receiver Timeout feature.  2017 Microchip Technology Inc. DS60001525A-page 1311 SAMA5D4 SERIES Figure 44-23: Receiver Timeout Block Diagram TO Baud Rate Clock 1 D Clock Q 16-bit Value 16-bit Timeout Counter = STTTO Character Received RETTO Load Clear TIMEOUT 0 Table 44-10 gives the maximum timeout period for some standard baud rates. Table 44-10: Maximum Timeout Period Baud Rate (bit/s) Bit Time (µs) Timeout (ms) 600 1,667 109,225 1,200 833 54,613 2,400 417 27,306 4,800 208 13,653 9,600 104 6,827 14,400 69 4,551 19,200 52 3,413 28,800 35 2,276 38,400 26 1,704 56,000 18 1,170 57,600 17 1,138 200,000 5 328 44.6.3.12 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported in US_CSR.FRAME. FRAME is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing a ‘1’ to US_CR.RSTSTA. DS60001525A-page 1312  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 44-24: Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 44.6.3.13 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing a ‘1’ to US_CR.STTBRK. This can be performed at any time, either while the transmitter is empty (no character in either the Shift register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested, further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing a ‘1’ to US_CR.STPBRK. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. The transmitter considers the break as though it is a character, i.e., the STTBRK and STPBRK commands are processed only if US_CSR. TXRDY = 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with both STTBRK and STPBRK bits to ‘1’ can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into US_THR while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 44-25 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 44-25: Break Transmission Baud Rate Clock TXD Start D0 Bit Write US_CR D1 D2 D3 D4 D5 STTBRK = 1 D6 D7 Parity Stop Bit Bit Break Transmission End of Break STPBRK = 1 TXRDY TXEMPTY  2017 Microchip Technology Inc. DS60001525A-page 1313 SAMA5D4 SERIES 44.6.3.14 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data to 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts US_CSR.RXBRK. This bit may be cleared by writing a ‘1’ to US_CR.RSTSTA. An end of receive break is detected by a high level for at least 2/16 of a bit period in Asynchronous operating mode or one sample at high level in Synchronous operating mode. The end of break detection also asserts US_CSR.RXBRK bit. 44.6.3.15 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 44-26. Figure 44-26: Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the value 0x2 to US_MR.USART_MODE. When hardware handshaking is enabled, the USART displays similar behavior as in standard Synchronous or Asynchronous modes, with the difference that the receiver drives the RTS pin and the level on the CTS pin modifies the behavior of the transmitter, as shown in the figures below. The transmitter can handle hardware handshaking in any case. Figure 44-27: RTS Line Software Control when US_MR.USART_MODE = 2 RXD Write US_CR.RTSEN Write US_CR.RTSDIS RTS Figure 44-28 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processed, the transmitter is disabled only after the completion of the current character and transmission of the next character occurs as soon as the pin CTS falls. Figure 44-28: Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 44.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing US_MR.USART_MODE to the value 0x4 for protocol T = 0 and to the value 0x6 for protocol T = 1. DS60001525A-page 1314  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.6.4.1 Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (refer to Section 44-2 “Baud Rate Generator”). The USART connects to a smart card as shown in Figure 44-29. The TXD line becomes bidirectional and the baud rate generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 44-29: Connection of a Smart Card to the USART USART CLK SCK I/O TXD Smart Card When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the Mode register fields CHRL, MODE9, PAR and CHMODE. US_MR.MSBF can be used to transmit LSB or MSB first. US_MR.PAR can be used to transmit in Normal or Inverse mode. Refer to Section 44.7.3 “USART Mode Register” and “PAR: Parity Type”. The USART cannot operate concurrently in both Receiver and Transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. 44.6.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 44-30. If a parity error is detected by the receiver, it drives the I/O line to 0 during the guard time, as shown in Figure 44-31. This error bit, NACK, for Non Acknowledge. In this case, the character lasts one additional bit time, as the guard time does not change and is added to the error bit time, which lasts one bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in US_RHR. It sets US_SR.PARE so that the software can handle the error. Figure 44-30: T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit  2017 Microchip Technology Inc. D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit DS60001525A-page 1315 SAMA5D4 SERIES Figure 44-31: T = 0 Protocol with Parity Error Baud Rate Clock Error I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition • Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Errors (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. • Receive NACK Inhibit The USART can be configured to inhibit an error. This is done by writing a ‘1’ to US_MR.INACK. In this case, no error signal is driven on the I/O line even if a parity bit is detected. Moreover, if INACK = 1, the erroneous received character is stored in the Receive Holding register as if no error occurred, and the RXRDY bit rises. • Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing US_MR.MAX_ITERATION to a value greater than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. When the USART repetition number reaches MAX_ITERATION and the last repeated character is not acknowledged, the US_CSR.ITER is set. If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. US_CSR.ITER can be cleared by writing a ‘1’ to US_CR.RSTIT. • Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting US_MR.DSNACK. The maximum number of NACKs transmitted is configured in US_MR.MAX_ITERATION. As soon as MAX_ITERATION is reached, no error signal is driven on the I/O line and US_CSR.ITER is set. 44.6.4.3 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets US_CSR.PARE. 44.6.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 44-32. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 kbit/s to 115.2 kbit/s. The IrDA mode is enabled by writing the value 0x8 to US_MR.USART_MODE. The IrDA Filter register (US_IF) is used to configure the demodulator filter. The USART transmitter and receiver operate in a normal Asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. DS60001525A-page 1316  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 44-32: Connection to IrDA Transceivers USART Receiver IrDA Transceivers Demodulator RXD RX TX Transmitter Modulator TXD The receiver and the transmitter must be enabled or disabled depending on the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done: • Disable TX and Enable RX • Configure the TXD pin as PIO and set it as an output to 0 (to avoid LED transmission). Disable the internal pull-up (better for power consumption). • Receive data 44.6.5.1 IrDA Modulation For baud rates up to and including 115.2 kbit/s, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 44-11. Table 44-11: IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 kbit/s 78.13 µs 9.6 kbit/s 19.53 µs 19.2 kbit/s 9.77 µs 38.4 kbit/s 4.88 µs 57.6 kbit/s 3.26 µs 115.2 kbit/s 1.63 µs Figure 44-33 shows an example of character transmission. Figure 44-33: IrDA Modulation Start Bit Transmitter Output 0 Stop Bit Data Bits 1 0 1 0 0 1 1 0 1 TXD Bit Period  2017 Microchip Technology Inc. 3/16 Bit Period DS60001525A-page 1317 SAMA5D4 SERIES 44.6.5.2 IrDA Baud Rate Table 44-12 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 44-12: IrDA Baud Rate Error Peripheral Clock Baud Rate (bit/s) CD Baud Rate Error Pulse Time (µs) 3,686,400 115,200 2 0.00% 1.63 20,000,000 115,200 11 1.38% 1.63 32,768,000 115,200 18 1.25% 1.63 40,000,000 115,200 22 1.38% 1.63 3,686,400 57,600 4 0.00% 3.26 20,000,000 57,600 22 1.38% 3.26 32,768,000 57,600 36 1.25% 3.26 40,000,000 57,600 43 0.93% 3.26 3,686,400 38,400 6 0.00% 4.88 20,000,000 38,400 33 1.38% 4.88 32,768,000 38,400 53 0.63% 4.88 40,000,000 38,400 65 0.16% 4.88 3,686,400 19,200 12 0.00% 9.77 20,000,000 19,200 65 0.16% 9.77 32,768,000 19,200 107 0.31% 9.77 40,000,000 19,200 130 0.16% 9.77 3,686,400 9,600 24 0.00% 19.53 20,000,000 9,600 130 0.16% 19.53 32,768,000 9,600 213 0.16% 19.53 40,000,000 9,600 260 0.16% 19.53 3,686,400 2,400 96 0.00% 78.13 20,000,000 2,400 521 0.03% 78.13 32,768,000 2,400 853 0.04% 78.13 44.6.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the peripheral clock speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 44-34 illustrates the operations of the IrDA demodulator. Figure 44-34: IrDA Demodulator Operations MCK RXD Counter Value 6 Receiver Input DS60001525A-page 1318 5 4 3 Pulse rejected 2 6 6 5 4 3 2 1 0 Pulse accepted  2017 Microchip Technology Inc. SAMA5D4 SERIES The programmed value in the US_IF register must always meet the following criterion: tperipheral clock × (IRDA_FILTER + 3) < 1.41 µs As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to ensure IrDA communications operate correctly. 44.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in Asynchronous or Synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to an RS485 bus is shown in Figure 44-35. Figure 44-35: Typical Connection to a RS485 Bus USART RXD Differential Bus TXD RTS RS485 mode is enabled by writing the value 0x1 to the US_MR.USART_MODE. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 44-36 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 44-36: Example of RTS Drive with Timeguard TG = 4 1 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RTS Write US_THR TXRDY TXEMPTY 44.6.7 SPI Mode The Serial Peripheral Interface (SPI) mode is a synchronous serial data link that provides communication with external devices in Master or Slave mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turns being masters and one master may simultaneously shift data into multiple slaves. (Multiple master protocol is the opposite of single master protocol, where one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its output to write data back to the master at any given time.  2017 Microchip Technology Inc. DS60001525A-page 1319 SAMA5D4 SERIES A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can address only one SPI slave because it can generate only one NSS signal. The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of the slave. • Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. • Serial Clock (SCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates. The SCK line cycles once for each bit that is transmitted. • Slave Select (NSS): This control line allows the master to select or deselect the slave. 44.6.7.1 Modes of Operation The USART can operate in SPI Master mode or in SPI Slave mode. SPI Master mode is enabled by writing 0xE to US_MR.USART_MODE. In this case, the SPI lines must be connected as described below: • • • • The MOSI line is driven by the output pin TXD The MISO line drives the input pin RXD The SCK line is driven by the output pin SCK The NSS line is driven by the output pin RTS SPI Slave mode is enabled by writing to 0xF US_MR.USART_MODE. In this case, the SPI lines must be connected as described below: • • • • The MOSI line drives the input pin RXD The MISO line is driven by the output pin TXD The SCK line drives the input pin SCK The NSS line drives the input pin CTS In order to avoid unpredictable behavior, any change of the SPI mode must be followed by a software reset of the transmitter and of the receiver (except the initial configuration after a hardware reset). (Refer to Section 44.6.7.4 “Receiver and Transmitter Control”). 44.6.7.2 Baud Rate In SPI mode, the baud rate generator operates in the same way as in USART Synchronous mode. Refer to Section 44.6.1.3 “Baud Rate in Synchronous Mode or SPI Mode”. However, there are some restrictions: In SPI Master mode: • The external clock SCK must not be selected (USCLKS ≠ 0x3), and US_MR.CLKO must be written to ‘1’, in order to generate correctly the serial clock on the SCK pin. • To obtain correct behavior of the receiver and the transmitter, the value programmed in US_BRGR.CD must be greater than or equal to 6. • If the divided peripheral clock is selected, the value programmed in CD must be even to ensure a 50:50 mark/space ratio on the SCK pin. This value can be odd if the peripheral clock is selected. In SPI Slave mode: • The external clock (SCK) selection is forced regardless of the value of the US_MR.USCLKS. Likewise, the value written in US_BRGR has no effect, because the clock is provided directly by the signal on the USART SCK pin. • To obtain correct behavior of the receiver and the transmitter, the external clock (SCK) frequency must be at least 6 times lower than the system clock. 44.6.7.3 Data Transfer Up to nine data bits are successively shifted out on the TXD pin at each rising or falling edge (depending on CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit. The number of data bits is selected using US_MR.CHRL and US_MR.MODE9. The nine bits are selected by setting the MODE9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI mode (Master or Slave). DS60001525A-page 1320  2017 Microchip Technology Inc. SAMA5D4 SERIES Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed using US_MR.CPOL. The clock phase is programmed using US_MR.CPHA. These two parameters determine the edges of the clock signal upon which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 44-13: Figure 44-37: SPI Bus Protocol Mode SPI Bus Protocol Mode CPOL CPHA 0 0 1 1 0 0 2 1 1 3 1 0 SPI Transfer Format (CPHA = 1, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 6 5 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master ->TXD SPI Slave -> RXD MISO SPI Master -> RXD SPI Slave -> TXD MSB MSB 6 5 4 3 2 1 LSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS  2017 Microchip Technology Inc. DS60001525A-page 1321 SAMA5D4 SERIES Figure 44-38: SPI Transfer Format (CPHA = 0, 8 bits per transfer) SCK cycle (for reference) 1 2 3 4 5 7 6 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI SPI Master -> TXD SPI Slave -> RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master -> RXD SPI Slave -> TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS 44.6.7.4 Receiver and Transmitter Control Refer to Section 44.6.2 “Receiver and Transmitter Control”. 44.6.7.5 Character Transmission The characters are sent by writing in the US_THR. An additional condition for transmitting a character can be added when the USART is configured in SPI Master mode. In the USART_MR (SPI_MODE), the value of WRDBT can prevent any character transmission (even if US_THR has been written) while the receiver side is not ready (character not read). When WRDBT equals ‘0’, the character is transmitted whatever the receiver status. If WRDBT is set to ‘1’, the transmitter waits for US_RHR to be read before transmitting the character (RXRDY flag cleared), thus preventing any overflow (character loss) on the receiver side. The chip select line is deasserted for a period equivalent to three bits between the transmission of two data. The transmitter reports two status bits in US_CSR: TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. If the USART is in SPI Slave mode and if a character must be sent while the US_THR is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is cleared by writing a 1 to the RSTSTA (Reset Status) bit in US_CR. In SPI Master mode, the slave select line (NSS) is asserted at low level one tbit (tbit being the nominal time required to transmit a bit) before the transmission of the MSB bit and released at high level one tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always released between each character transmission and a minimum delay of three tbit always inserted. However, in order to address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can be forced at low level by writing a 1 to the RCS bit in the US_CR. The slave select line (NSS) can be released at high level only by writing a ‘1’ to US_CR.FCS (for example, when all data have been transferred to the slave device). In SPI Slave mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a character transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least one tbit before the first serial clock cycle corresponding to the MSB bit. 44.6.7.6 Character Reception When a character reception is completed, it is transferred to US_RHR and US_CSR.RXRDY rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing a ‘1’ to US_CR.RSTSTA. DS60001525A-page 1322  2017 Microchip Technology Inc. SAMA5D4 SERIES To ensure correct behavior of the receiver in SPI Slave mode, the master device sending the frame must ensure a minimum delay of one tbit between each character transmission. The receiver does not require a falling edge of the slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be present on the slave select line (NSS) at least one tbit before the first serial clock cycle corresponding to the MSB bit. 44.6.7.7 Receiver Timeout Because the receiver baud rate clock is active only during data transfers in SPI mode, a receiver timeout is impossible in this mode, whatever the value is in US_RTOR.TO. 44.6.8 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In Loopback mode, the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 44.6.8.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 44-39: 44.6.8.2 Normal Mode Configuration Receiver RXD Transmitter TXD Automatic Echo Mode Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 44-40. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 44-40: 44.6.8.3 Automatic Echo Mode Configuration Receiver RXD Transmitter TXD Local Loopback Mode Local Loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 44-41. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 44-41: Local Loopback Mode Configuration RXD Receiver Transmitter  2017 Microchip Technology Inc. 1 TXD DS60001525A-page 1323 SAMA5D4 SERIES 44.6.8.4 Remote Loopback Mode Remote Loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 44-42. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 44-42: Remote Loopback Mode Configuration Receiver Transmitter 44.6.9 1 RXD TXD Register Write Protection To prevent any single software error from corrupting USART behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the USART Write Protection Mode Register (US_WPMR). If a write access to a write-protected register is detected, the WPVS flag in the USART Write Protection Status Register (US_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS bit is automatically cleared after reading the US_WPSR. The following registers can be write-protected: • • • • USART Mode Register USART Baud Rate Generator Register USART Receiver Timeout Register USART Transmitter Timeguard Register • USART Manchester Configuration Register DS60001525A-page 1324  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 44-14: Register Mapping Offset Register Name Access Reset 0x0000 Control Register US_CR Write-only – 0x0004 Mode Register US_MR Read/Write 0x0 0x0008 Interrupt Enable Register US_IER Write-only – 0x000C Interrupt Disable Register US_IDR Write-only – 0x0010 Interrupt Mask Register US_IMR Read-only 0x0 0x0014 Channel Status Register US_CSR Read-only 0x0 0x0018 Receive Holding Register US_RHR Read-only 0x0 0x001C Transmit Holding Register US_THR Write-only – 0x0020 Baud Rate Generator Register US_BRGR Read/Write 0x0 0x0024 Receiver Timeout Register US_RTOR Read/Write 0x0 0x0028 Transmitter Timeguard Register US_TTGR Read/Write 0x0 Reserved – – – 0x0040 FI DI Ratio Register US_FIDI Read/Write 0x174 0x0044 Number of Errors Register US_NER Read-only 0x0 0x0048 Reserved – – – 0x004C IrDA Filter Register US_IF Read/Write 0x0 0x0050 Manchester Configuration Register US_MAN Read/Write 0x30011004 0x0054–0x005C Reserved – – – 0x0060–0x00E0 Reserved – – – 0x00E4 Write Protection Mode Register US_WPMR Read/Write 0x0 0x00E8 Write Protection Status Register US_WPSR Read-only 0x0 Reserved – – – 0x002C–0x003C 0x00EC–0x00FC  2017 Microchip Technology Inc. DS60001525A-page 1325 SAMA5D4 SERIES 44.7.1 USART Control Register Name:US_CR Address:0xF802C000 (0), 0xF8030000 (1), 0xFC008000 (2), 0xFC00C000 (3), 0xFC010000 (4) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 – 16 – 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – For SPI control, refer to Section 44.7.2 “USART Control Register (SPI_MODE)”. RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR. STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. DS60001525A-page 1326  2017 Microchip Technology Inc. SAMA5D4 SERIES STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. STTTO: Clear TIMEOUT Flag and Start Timeout After Next Character Received 0: No effect. 1: Starts waiting for a character before enabling the timeout counter. Immediately disables a timeout period in progress. Resets the status bit TIMEOUT in US_CSR. SENDA: Send Address 0: No effect. 1: In Multidrop mode only, the next character written to the US_THR is sent with the address bit set. RSTIT: Reset Iterations 0: No effect. 1: Resets ITER in US_CSR. No effect if the ISO7816 is not enabled. RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. RETTO: Start Timeout Immediately 0: No effect 1: Immediately restarts timeout period. RTSEN: Request to Send Pin Control 0: No effect. 1: Drives RTS pin to 1 if US_MR.USART_MODE field = 2, else drives RTS pin to 0 if US_MR.USART_MODE field = 0. RTSDIS: Request to Send Pin Control 0: No effect. 1: Drives RTS pin to 0 if US_MR.USART_MODE field = 2 (if PDC RX buffer is not full), else drives RTS pin to 1 if US_MR.USART_MODE field = 0.  2017 Microchip Technology Inc. DS60001525A-page 1327 SAMA5D4 SERIES 44.7.2 USART Control Register (SPI_MODE) Name:US_CR (SPI_MODE) Address:0xF802C000 (0), 0xF8030000 (1), 0xFC008000 (2), 0xFC00C000 (3), 0xFC010000 (4) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RCS 18 FCS 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits OVRE, UNRE in US_CSR. FCS: Force SPI Chip Select Applicable if USART operates in SPI Master mode (USART_MODE = 0xE): 0: No effect. 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is not transmitting, in order to address SPI slave devices supporting the CSAAT mode (Chip Select Active After Transfer). DS60001525A-page 1328  2017 Microchip Technology Inc. SAMA5D4 SERIES RCS: Release SPI Chip Select Applicable if USART operates in SPI Master mode (USART_MODE = 0xE): 0: No effect. 1: Releases the Slave Select Line NSS (RTS pin).  2017 Microchip Technology Inc. DS60001525A-page 1329 SAMA5D4 SERIES 44.7.3 USART Mode Register Name:US_MR Address:0xF802C004 (0), 0xF8030004 (1), 0xFC008004 (2), 0xFC00C004 (3), 0xFC010004 (4) Access:Read/Write 31 ONEBIT 30 MODSYNC 29 MAN 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 INVDATA 22 VAR_SYNC 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 15 14 13 12 11 10 PAR 9 8 SYNC 4 3 2 1 0 CHMODE 7 NBSTOP 6 5 CHRL USCLKS USART_MODE This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. For SPI configuration, refer to Section 44.7.4 “USART Mode Register (SPI_MODE)”. USART_MODE: USART Mode of Operation Value Name Description 0x0 NORMAL Normal mode 0x1 RS485 RS485 0x2 HW_HANDSHAKING Hardware Handshaking 0x3 — Reserved 0x4 IS07816_T_0 IS07816 Protocol: T = 0 0x6 IS07816_T_1 IS07816 Protocol: T = 1 0x8 IRDA IrDA 0xE SPI_MASTER SPI Master mode (CLKO must be written to 1 and USCLKS = 0, 1 or 2) 0xF SPI_SLAVE SPI Slave mode USCLKS: Clock Selection Value Name Description 0 MCK Peripheral clock is selected 1 DIV Peripheral clock divided (DIV=8) is selected 2 — Reserved 3 SCK Serial clock (SCK) is selected CHRL: Character Length Value Name Description 0 5_BIT Character length is 5 bits 1 6_BIT Character length is 6 bits 2 7_BIT Character length is 7 bits 3 8_BIT Character length is 8 bits DS60001525A-page 1330  2017 Microchip Technology Inc. SAMA5D4 SERIES SYNC: Synchronous Mode Select 0: USART operates in Asynchronous mode. 1: USART operates in Synchronous mode. PAR: Parity Type Value Name Description 0 EVEN Even parity 1 ODD Odd parity 2 SPACE Parity forced to 0 (Space) 3 MARK Parity forced to 1 (Mark) 4 NO No parity 6 MULTIDROP Multidrop mode NBSTOP: Number of Stop Bits Value Name Description 0 1_BIT 1 stop bit 1 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 2 2_BIT 2 stop bits CHMODE: Channel Mode Value Name Description 0 NORMAL Normal mode 1 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 2 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 3 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. MSBF: Bit Order 0: Least significant bit is sent/received first. 1: Most significant bit is sent/received first. MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. OVER: Oversampling Mode 0: 16X Oversampling 1: 8X Oversampling INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated.  2017 Microchip Technology Inc. DS60001525A-page 1331 SAMA5D4 SERIES DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITER is asserted. Note: MAX_ITERATION field must be set to 0 if DSNACK is cleared. INVDATA: Inverted Data 0: The data field transmitted on TXD line is the same as the one written in US_THR or the content read in US_RHR is the same as RXD line. Normal mode of operation. 1: The data field transmitted on TXD line is inverted (voltage polarity only) compared to the value written on US_THR or the content read in US_RHR is inverted compared to what is received on RXD line (or ISO7816 IO line). Inverted mode of operation, useful for contactless card application. To be used with configuration bit MSBF. VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter 0: User defined configuration of command or data sync field depending on MODSYNC value. 1: The sync field is updated when a character is written into US_THR. MAX_ITERATION: Maximum Number of Automatic Iteration 0–7: Defines the maximum number of iterations in ISO7816 mode, protocol T = 0. FILTER: Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). MAN: Manchester Encoder/Decoder Enable 0: Manchester encoder/decoder are disabled. 1: Manchester encoder/decoder are enabled. MODSYNC: Manchester Synchronization Mode 0:The Manchester start bit is a 0 to 1 transition 1: The Manchester start bit is a 1 to 0 transition. ONEBIT: Start Frame Delimiter Selector 0: Start frame delimiter is COMMAND or DATA SYNC. 1: Start frame delimiter is one bit. DS60001525A-page 1332  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.7.4 USART Mode Register (SPI_MODE) Name:US_MR (SPI_MODE) Address:0xF802C004 (0), 0xF8030004 (1), 0xFC008004 (2), 0xFC00C004 (3), 0xFC010004 (4) Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 WRDBT 19 – 18 CLKO 17 – 16 CPOL 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 CPHA 6 5 4 3 2 1 0 7 CHRL USCLKS USART_MODE This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. USART_MODE: USART Mode of Operation Value Name Description 0xE SPI_MASTER SPI master 0xF SPI_SLAVE SPI Slave USCLKS: Clock Selection Value Name Description 0 MCK Peripheral clock is selected 1 DIV Peripheral clock divided (DIV=8) is selected 3 SCK Serial Clock (SCK) is selected CHRL: Character Length Value Name Description 3 8_BIT Character length is 8 bits CPHA: SPI Clock Phase – Applicable if USART operates in SPI mode (USART_MODE = 0xE or 0xF): 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. CPOL: SPI Clock Polarity Applicable if USART operates in SPI mode (Slave or Master, USART_MODE = 0xE or 0xF): 0: The inactive state value of SPCK is logic level zero. 1: The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SCK). It is used with CPHA to produce the required clock/data relationship between master and slave devices.  2017 Microchip Technology Inc. DS60001525A-page 1333 SAMA5D4 SERIES CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. WRDBT: Wait Read Data Before Transfer 0: The character transmission starts as soon as a character is written into US_THR (assuming TXRDY was set). 1: The character transmission starts when a character is written and only if RXRDY flag is cleared (Receive Holding Register has been read). DS60001525A-page 1334  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.7.5 USART Interrupt Enable Register Name:US_IER Address:0xF802C008 (0), 0xF8030008 (1), 0xFC008008 (2), 0xFC00C008 (3), 0xFC010008 (4) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, refer to Section 44.7.6 “USART Interrupt Enable Register (SPI_MODE)”. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt. RXRDY: RXRDY Interrupt Enable TXRDY: TXRDY Interrupt Enable RXBRK: Receiver Break Interrupt Enable OVRE: Overrun Error Interrupt Enable FRAME: Framing Error Interrupt Enable PARE: Parity Error Interrupt Enable TIMEOUT: Timeout Interrupt Enable TXEMPTY: TXEMPTY Interrupt Enable ITER: Max number of Repetitions Reached Interrupt Enable NACK: Non Acknowledge Interrupt Enable CTSIC: Clear to Send Input Change Interrupt Enable MANE: Manchester Error Interrupt Enable  2017 Microchip Technology Inc. DS60001525A-page 1335 SAMA5D4 SERIES 44.7.6 USART Interrupt Enable Register (SPI_MODE) Name:US_IER (SPI_MODE) Address:0xF802C008 (0), 0xF8030008 (1), 0xFC008008 (2), 0xFC00C008 (3), 0xFC010008 (4) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 NSSE 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Enables the corresponding interrupt. RXRDY: RXRDY Interrupt Enable TXRDY: TXRDY Interrupt Enable OVRE: Overrun Error Interrupt Enable TXEMPTY: TXEMPTY Interrupt Enable UNRE: SPI Underrun Error Interrupt Enable NSSE: NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable DS60001525A-page 1336  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.7.7 USART Interrupt Disable Register Name:US_IDR Address:0xF802C00C (0), 0xF803000C (1), 0xFC00800C (2), 0xFC00C00C (3), 0xFC01000C (4) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, refer to Section 44.7.8 “USART Interrupt Disable Register (SPI_MODE)”. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt. RXRDY: RXRDY Interrupt Disable TXRDY: TXRDY Interrupt Disable RXBRK: Receiver Break Interrupt Disable OVRE: Overrun Error Interrupt Enable FRAME: Framing Error Interrupt Disable PARE: Parity Error Interrupt Disable TIMEOUT: Timeout Interrupt Disable TXEMPTY: TXEMPTY Interrupt Disable ITER: Max Number of Repetitions Reached Interrupt Disable NACK: Non Acknowledge Interrupt Disable CTSIC: Clear to Send Input Change Interrupt Disable MANE: Manchester Error Interrupt Disable  2017 Microchip Technology Inc. DS60001525A-page 1337 SAMA5D4 SERIES 44.7.8 USART Interrupt Disable Register (SPI_MODE) Name: US_IDR (SPI_MODE) Address:0xF802C00C (0), 0xF803000C (1), 0xFC00800C (2), 0xFC00C00C (3), 0xFC01000C (4) Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 NSSE 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: No effect 1: Disables the corresponding interrupt. RXRDY: RXRDY Interrupt Disable TXRDY: TXRDY Interrupt Disable OVRE: Overrun Error Interrupt Disable TXEMPTY: TXEMPTY Interrupt Disable UNRE: SPI Underrun Error Interrupt Disable NSSE: NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable DS60001525A-page 1338  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.7.9 USART Interrupt Mask Register Name:US_IMR Address:0xF802C010 (0), 0xF8030010 (1), 0xFC008010 (2), 0xFC00C010 (3), 0xFC010010 (4) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANE 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, refer to Section 44.7.10 “USART Interrupt Mask Register (SPI_MODE)”. The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. RXRDY: RXRDY Interrupt Mask TXRDY: TXRDY Interrupt Mask RXBRK: Receiver Break Interrupt Mask OVRE: Overrun Error Interrupt Mask FRAME: Framing Error Interrupt Mask PARE: Parity Error Interrupt Mask TIMEOUT: Timeout Interrupt Mask TXEMPTY: TXEMPTY Interrupt Mask ITER: Max Number of Repetitions Reached Interrupt Mask NACK: Non Acknowledge Interrupt Mask CTSIC: Clear to Send Input Change Interrupt Mask MANE: Manchester Error Interrupt Mask  2017 Microchip Technology Inc. DS60001525A-page 1339 SAMA5D4 SERIES 44.7.10 USART Interrupt Mask Register (SPI_MODE) Name:US_IMR (SPI_MODE) Address:0xF802C010 (0), 0xF8030010 (1), 0xFC008010 (2), 0xFC00C010 (3), 0xFC010010 (4) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 NSSE 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. RXRDY: RXRDY Interrupt Mask TXRDY: TXRDY Interrupt Mask OVRE: Overrun Error Interrupt Mask TXEMPTY: TXEMPTY Interrupt Mask UNRE: SPI Underrun Error Interrupt Mask NSSE: NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask DS60001525A-page 1340  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.7.11 USART Channel Status Register Name:US_CSR Address:0xF802C014 (0), 0xF8030014 (1), 0xFC008014 (2), 0xFC00C014 (3), 0xFC010014 (4) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANERR 23 CTS 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 – 14 – 13 NACK 12 – 11 – 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY For SPI specific configuration, refer to Section 44.7.12 “USART Channel Status Register (SPI_MODE)”. RXRDY: Receiver Ready (cleared by reading US_RHR) 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. TXRDY: Transmitter Ready (cleared by writing US_THR) 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. RXBRK: Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 0: No break received or end of break detected since the last RSTSTA. 1: Break received or end of break detected since the last RSTSTA. OVRE: Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. FRAME: Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. PARE: Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. TIMEOUT: Receiver Timeout (cleared by writing a one to bit US_CR.STTTO) 0: There has not been a timeout since the last Start Timeout command (STTTO in US_CR) or the Timeout Register is 0. 1: There has been a timeout since the last Start Timeout command (STTTO in US_CR). TXEMPTY: Transmitter Empty (cleared by writing US_THR) 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register.  2017 Microchip Technology Inc. DS60001525A-page 1341 SAMA5D4 SERIES ITER: Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 0: Maximum number of repetitions has not been reached since the last RSTIT. 1: Maximum number of repetitions has been reached since the last RSTIT. NACK: Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 0: Non acknowledge has not been detected since the last RSTNACK. 1: At least one non acknowledge has been detected since the last RSTNACK. CTSIC: Clear to Send Input Change Flag (cleared on read) 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. CTS: Image of CTS Input 0: CTS input is driven low. 1: CTS input is driven high. MANERR: Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA. DS60001525A-page 1342  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.7.12 USART Channel Status Register (SPI_MODE) Name:US_CSR (SPI_MODE) Address:0xF802C014 (0), 0xF8030014 (1), 0xFC008014 (2), 0xFC00C014 (3), 0xFC010014 (4) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 NSS 22 – 21 – 20 – 19 NSSE 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 UNRE 9 TXEMPTY 8 – 7 – 6 – 5 OVRE 4 – 3 – 2 – 1 TXRDY 0 RXRDY This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register. RXRDY: Receiver Ready (cleared by reading US_RHR) 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. TXRDY: Transmitter Ready (cleared by writing US_THR) 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. OVRE: Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. TXEMPTY: Transmitter Empty (cleared by writing US_THR) 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. UNRE: Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 0: No SPI underrun error has occurred since the last RSTSTA. 1: At least one SPI underrun error has occurred since the last RSTSTA. NSSE: NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 0: No NSS line event has been detected since the last read of US_CSR. 1: A rising or falling edge event has been detected on NSS line since the last read of US_CSR. NSS: Image of NSS Line 0: NSS line is driven low (if NSSE = 1, falling edge occurred on NSS line). 1: NSS line is driven high (if NSSE = 1, rising edge occurred on NSS line).  2017 Microchip Technology Inc. DS60001525A-page 1343 SAMA5D4 SERIES 44.7.13 USART Receive Holding Register Name:US_RHR Address:0xF802C018 (0), 0xF8030018 (1), 0xFC008018 (2), 0xFC00C018 (3), 0xFC010018 (4) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR RXCHR: Received Character Last character received if RXRDY is set. RXSYNH: Received Sync 0: Last character received is a data. 1: Last character received is a command. DS60001525A-page 1344  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.7.14 USART Transmit Holding Register Name:US_THR Address:0xF802C01C (0), 0xF803001C (1), 0xFC00801C (2), 0xFC00C01C (3), 0xFC01001C (4) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. TXSYNH: Sync Field to be Transmitted 0: The next character sent is encoded as a data. Start frame delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start frame delimiter is COMMAND SYNC.  2017 Microchip Technology Inc. DS60001525A-page 1345 SAMA5D4 SERIES 44.7.15 USART Baud Rate Generator Register Name:US_BRGR Address:0xF802C020 (0), 0xF8030020 (1), 0xFC008020 (2), 0xFC00C020 (3), 0xFC010020 (4) Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. CD: Clock Divider USART_MODE ≠ ISO7816 SYNC = 0 OVER = 0 CD OVER = 1 0 1 to 65535 SYNC = 1 or USART_MODE = SPI (Master or Slave) USART_MODE = ISO7816 Baud Rate Clock Disabled CD = Selected Clock / (16 × Baud Rate) CD = Selected Clock / (8 × Baud Rate) CD = Selected Clock / Baud Rate CD = Selected Clock / (FI_DI_RATIO × Baud Rate) FP: Fractional Part 0: Fractional divider is disabled. 1–7: Baud rate resolution, defined by FP × 1/8. Warning: When the value of field FP is greater than 0, the SCK (oversampling clock) generates nonconstant duty cycles. The SCK high duration is increased by “selected clock” period from time to time. The duty cycle depends on the value of the CD field. DS60001525A-page 1346  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.7.16 USART Receiver Timeout Register Name:US_RTOR Address:0xF802C024 (0), 0xF8030024 (1), 0xFC008024 (2), 0xFC00C024 (3), 0xFC010024 (4) Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. TO: Timeout Value 0: The receiver timeout is disabled. 1–65535: The receiver timeout is enabled and TO is Timeout Delay / Bit Period.  2017 Microchip Technology Inc. DS60001525A-page 1347 SAMA5D4 SERIES 44.7.17 USART Transmitter Timeguard Register Name:US_TTGR Address:0xF802C028 (0), 0xF8030028 (1), 0xFC008028 (2), 0xFC00C028 (3), 0xFC010028 (4) Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. • TG: Timeguard Value 0: The transmitter timeguard is disabled. 1–255: The transmitter timeguard is enabled and TG is Timeguard Delay / Bit Period. DS60001525A-page 1348  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.7.18 USART FI DI RATIO Register Name:US_FIDI Address:0xF802C040 (0), 0xF8030040 (1), 0xFC008040 (2), 0xFC00C040 (3), 0xFC010040 (4) Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the baud rate generator generates no signal. 1–2: Do not use. 3–65535: If ISO7816 mode is selected, the baud rate is the clock provided on SCK divided by FI_DI_RATIO.  2017 Microchip Technology Inc. DS60001525A-page 1349 SAMA5D4 SERIES 44.7.19 USART Number of Errors Register Name:US_NER Address:0xF802C044 (0), 0xF8030044 (1), 0xFC008044 (2), 0xFC00C044 (3), 0xFC010044 (4) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS This register is relevant only if USART_MODE = 0x4 or 0x6 in the USART Mode Register. NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. DS60001525A-page 1350  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.7.20 USART IrDA Filter Register Name:US_IF Address:0xF802C04C (0), 0xF803004C (1), 0xFC00804C (2), 0xFC00C04C (3), 0xFC01004C (4) Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER This register is relevant only if USART_MODE = 0x8 in the USART Mode Register. This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. IRDA_FILTER: IrDA Filter The IRDA_FILTER value must be defined to meet the following criteria: tperipheral clock × (IRDA_FILTER + 3) < 1.41 µs  2017 Microchip Technology Inc. DS60001525A-page 1351 SAMA5D4 SERIES 44.7.21 USART Manchester Configuration Register Name:US_MAN Address:0xF802C050 (0), 0xF8030050 (1), 0xFC008050 (2), 0xFC00C050 (3), 0xFC010050 (4) Access:Read/Write 31 – 30 DRIFT 29 ONE 28 RX_MPOL 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 – 14 – 13 – 12 TX_MPOL 11 – 7 – 6 – 5 – 4 – 3 25 24 RX_PP 17 16 10 – 9 8 2 1 RX_PL TX_PP 0 TX_PL This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register. TX_PL: Transmitter Preamble Length 0: The transmitter preamble pattern generation is disabled 1–15: The preamble length is TX_PL × Bit Period TX_PP: Transmitter Preamble Pattern The following values assume that TX_MPOL field is not set: Value Name Description 0 ALL_ONE The preamble is composed of ‘1’s 1 ALL_ZERO The preamble is composed of ‘0’s 2 ZERO_ONE The preamble is composed of ‘01’s 3 ONE_ZERO The preamble is composed of ‘10’s TX_MPOL: Transmitter Manchester Polarity 0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition. 1: Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition. RX_PL: Receiver Preamble Length 0: The receiver preamble pattern detection is disabled 1–15: The detected preamble length is RX_PL × Bit Period RX_PP: Receiver Preamble Pattern detected The following values assume that RX_MPOL field is not set: Value Name Description 00 ALL_ONE The preamble is composed of ‘1’s 01 ALL_ZERO The preamble is composed of ‘0’s 10 ZERO_ONE The preamble is composed of ‘01’s 11 ONE_ZERO The preamble is composed of ‘10’s DS60001525A-page 1352  2017 Microchip Technology Inc. SAMA5D4 SERIES RX_MPOL: Receiver Manchester Polarity 0: Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition. 1: Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition. ONE: Must Be Set to 1 Bit 29 must always be set to 1 when programming the US_MAN register. DRIFT: Drift Compensation 0: The USART cannot recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled.  2017 Microchip Technology Inc. DS60001525A-page 1353 SAMA5D4 SERIES 44.7.22 USART Write Protection Mode Register Name:US_WPMR Address:0xF802C0E4 (0), 0xF80300E4 (1), 0xFC0080E4 (2), 0xFC00C0E4 (3), 0xFC0100E4 (4) Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x555341 (“USA” in ASCII). Refer to Section 44.6.9 “Register Write Protection” for the list of registers that can be write-protected. WPKEY: Write Protection Key Value 0x555341 Name Description PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. DS60001525A-page 1354  2017 Microchip Technology Inc. SAMA5D4 SERIES 44.7.23 USART Write Protection Status Register Name:US_WPSR Address:0xF802C0E8 (0), 0xF80300E8 (1), 0xFC0080E8 (2), 0xFC00C0E8 (3), 0xFC0100E8 (4) Access:Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of the US_WPSR. 1: A write protection violation has occurred since the last read of the US_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted.  2017 Microchip Technology Inc. DS60001525A-page 1355 SAMA5D4 SERIES 45. Software Modem Device (SMD) 45.1 Description The Software Modem Device (SMD) is a block for communication via a modem’s Digital Isolation Barrier (DIB) with a complementary Line Side Device (LSD). SMD and LSD are two parts of the “Transformer only” solution. The transformer is the only component connecting SMD and LSD and is used for power, clock and data transfers. Power and clock are supplied by the SMD and consumed by the LSD. The data flow is bidirectional. The data transfer is based on pulse width modulation for transmission from the SMD to the LSD, and for receiving from the LSD. There are two channels embedded into the protocol of the DIB link: • Data channel • Control channel Each channel is bidirectional. The data channel is used to transfer digitized signal samples at a constant rate of 16 bits at 16 kHz. The control channel is used to communicate with control registers of the LSD at a maximum rate of 8 bits at 16 kHz. The SMD performs all protocol-related data conversion for transmission and received data interpretation in both data and control channels of the link. The SMD incorporates both RX and TX FIFOs, available through the DMAC interface. Each FIFO is able to hold eight 32-bit words (equivalent to 16 modem data samples). 45.2 Embedded Characteristics • Modulations and protocols - V.90 - V.34 - V.32bis, V.32, V.22bis, V.22, V.23, V.21 - V.23 reverse, V.23 half-duplex - Bell 212A/Bell 103 - V.29 FastPOS - V.22bis fast connect - V.80 Synchronous Access Mode • Data compression and error correction - V.44 data compression (V.92 model) - V.42bis and MNP 5 data compression - V.42 LAPM and MNP 2-4 error correction - EIA/TIA 578 Class 1 and T.31 Class 1.0 • Call Waiting (CW) detection and Type II Caller ID decoding during data mode • Type I Caller ID (CID) decoding • 63 embedded and upgradable country profiles • Embedded AT commands • SmartDAA - Extension pick-up detection - Digital line protection - Line reversal detection - Line-in-use detection - Remote hang-up detection • Worldwide compliance DS60001525A-page 1356  2017 Microchip Technology Inc. SAMA5D4 SERIES 45.3 Block Diagram Figure 45-1: Software Modem Device Block Diagram SMD Controller SMD Core Byte Parallel Interface CPU Interrupt AHB  2017 Microchip Technology Inc. Control Channel Logic Control/Status Registers AHB Wrapper FIFO Interface 8x32 (2) DMA Parallel Interface DMA Channel Logic Ring Detection and Pulse Dialing Machines (masters) FIFO 2x16 DIB Interface Circuitry DIB Pads X X FIFO 2x16 DS60001525A-page 1357 SAMA5D4 SERIES 45.4 Software Modem Device (SMD) User Interface The SMD presents a number of registers through the AHB interface for software control and status functions. Table 45-1: Register Mapping Offset Register Name Access Reset 0x0C SMD Drive Register SMD_DRIVE Read/Write 0x00000002 DS60001525A-page 1358  2017 Microchip Technology Inc. SAMA5D4 SERIES 45.4.1 SMD Drive Register Name:SMD_DRIVE Address:0x0090000C Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 PWRCLKP_PCS 5 4 PWRCLKN_PCS2 3 2 1 PWRCLKP_PV PWRCLKP_PV2 DC_PWRCLKPN 0 MIE PWRCLKP_PCS: PWRCLKP Pin Control Select When DC_PWRCLKPN is a 1, the usage of PWRCLKP_PCS bits for direct control of PWRCLKP pin is enabled as follows: X1: High impedance on PWRCLKP pin. 00: Drive low on PWRCLKP pin. 10: Drive high on PWRCLKP pin. When DC_PWRCLKPN is a 0, the protocol logic controls PWRCLKP pin. If PWRCLKPN_FS bit is a 1, the above information is applied to PWRCLKN pin because of swapping with PWRCLKP. PWRCLKN_PCS2: PWRCLKN Pin Control Select When DC_PWRCLKPN is a 1, the usage of PWRCLKN_PCS2 bits for direct control of PWRCLKN pin is enabled as follows: X1: High impedance on PWRCLKN pin. 00: Drive low on PWRCLKN pin. 10: Drive high on PWRCLKN pin. When DC_PWRCLKPN is a 0, the protocol logic controls PWRCLKN pin. If PWRCLKPN_FS bit is a 1, the above information is applied to PWRCLKP pin because of swapping with PWRCLKN. PWRCLKP_PV: PWRCLKP Pin Value This bit reflects the PWRCLKP pin value if PWRCLKPN_FS = 0, or the PWRCLKN pin value if PWRCLKPN_FS = 1 (because of swapping with PWRCLKP). PWRCLKP_PV2: PWRCLKP Pin Value This bit reflects the PWRCLKN pin value if PWRCLKPN_FS = 0, or the PWRCLKP pin value if PWRCLKPN_FS = 1 (because of swapping with PWRCLKN). DC_PWRCLKPN: Direct Control of PWRCLKP, PWRCLKN Pins Enable 0: Enables protocol logic control of PWRCLKP, PWRCLKN pins. 1: Enables the use of PWRCLKP_PCS and PWRCLKN_PCS2 bits for direct control of PWRCLKP, PWRCLKN pins making them general purpose input/outputs (GPIOs). MIE: MADCVS Interrupt Enable 0: Disables smd_irq interrupt generation for MADCVS flag. 1: Enables smd_irq interrupt generation for MADCVS flag.  2017 Microchip Technology Inc. DS60001525A-page 1359 SAMA5D4 SERIES 46. Timer Counter (TC) 46.1 Description A Timer Counter (TC) module includes three identical TC channels. The number of implemented TC modules is device-specific. Each TC channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The TC embeds a quadrature decoder (QDEC) connected in front of the timers and driven by TIOA0, TIOB0 and TIOB1 inputs. When enabled, the QDEC performs the input lines filtering, decoding of quadrature signals and connects to the timers/counters in order to read the position and speed of the motor through the user interface. The TC block has two global registers which act upon all TC channels: • Block Control Register (TC_BCR)—allows channels to be started simultaneously with the same instruction • Block Mode Register (TC_BMR)—defines the external clock inputs for each channel, allowing them to be chained 46.2 Embedded Characteristics • Total number of TC channels implemented on this device: 9 • TC channel size: 32-bit • Wide range of functions including: - Frequency measurement - Event counting - Interval measurement - Pulse generation - Delay timing - Pulse Width Modulation - Up/down capabilities - Quadrature decoder - 2-bit Gray up/down count for stepper motor • Each channel is user-configurable and contains: - Three external clock inputs - Five Internal clock inputs - Two multi-purpose input/output signals acting as trigger event - Trigger/capture events can be directly synchronized by PWM signals • Internal interrupt signal • Compare event fault generation for PWM • Register Write Protection 46.3 Block Diagram Table 46-1: Timer Counter Clock Assignment Name Definition TIMER_CLOCK1 div2 TIMER_CLOCK2 div8 TIMER_CLOCK3 div32 TIMER_CLOCK4 div128 (1) TIMER_CLOCK5 slow_clock Note 1: When slow_clock is selected for Peripheral Clock (CSS = 0 in PMC Master Clock Register), slow_clock input is equivalent to Peripheral Clock. DS60001525A-page 1360  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 46-1: Block Diagram Timer Counter Parallel I/O Controller TIMER_CLOCK1 TCLK0 TIMER_CLOCK2 TIOA1 TIOA2 TIMER_CLOCK3 TCLK1 TIMER_CLOCK4 XC0 Timer/Counter Channel 0 XC1 TIOA TIOA0 TIOB0 TIOA0 TIOB TCLK2 TIOB0 XC2 TIMER_CLOCK5 TC0XC0S SYNC TCLK0 TCLK1 TCLK2 INT0 TCLK0 TCLK1 XC0 TIOA0 Timer/Counter Channel 1 XC1 TIOA TIOA1 TIOB1 TIOA1 TIOB TIOA2 TCLK2 TIOB1 XC2 SYNC TC1XC1S TCLK0 XC0 TCLK1 XC1 TCLK2 XC2 Timer/Counter Channel 2 INT1 TIOA TIOA2 TIOB2 TIOA2 TIOB TIOB2 TIOA0 TIOA1 SYNC TC2XC2S INT2 FAULT PWM Note: Interrupt Controller The QDEC connections are detailed in Figure 46-16. Table 46-2: Channel Signal Description Signal Name XC0, XC1, XC2 Description External Clock Inputs TIOAx Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output TIOBx Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output INT SYNC Interrupt Signal Output (internal signal) Synchronization Input Signal (from configuration register)  2017 Microchip Technology Inc. DS60001525A-page 1361 SAMA5D4 SERIES 46.4 Pin List Table 46-3: Pin List Pin Name Description Type TCLK0–TCLK2 External Clock Input Input TIOA0–TIOA2 I/O Line A I/O TIOB0–TIOB2 I/O Line B I/O 46.5 Product Dependencies 46.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 46-4: I/O Lines Instance Signal I/O Line Peripheral TC0 TCLK0 PE17 C TC0 TCLK1 PE14 B TC0 TCLK2 PE11 B TC0 TIOA0 PE15 C TC0 TIOA1 PE12 B TC0 TIOA2 PE9 B TC0 TIOB0 PE16 C TC0 TIOB1 PE13 B TC0 TIOB2 PE10 B TC1 TCLK3 PE8 B TC1 TCLK4 PE23 B TC1 TCLK5 PE20 B TC1 TIOA3 PE6 B TC1 TIOA4 PE21 B TC1 TIOA5 PE18 B TC1 TIOB3 PE7 B TC1 TIOB4 PE22 B TC1 TIOB5 PE19 B 46.5.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. DS60001525A-page 1362  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.5.3 Interrupt Sources The TC has an interrupt line connected to the interrupt controller. Handling the TC interrupt requires programming the interrupt controller before configuring the TC. Table 46-5: Peripheral IDs Instance ID TC0 40 TC1 41 TC2 42 46.5.4 Synchronization Inputs from PWM The TC has trigger/capture inputs internally connected to the PWM. Refer to Section 46.6.13 “Synchronization with PWM” and to the implementation of the Pulse Width Modulation (PWM) in this product. 46.5.5 Fault Output The TC has the FAULT output internally connected to the fault input of PWM. Refer to Section 46.6.17 “Fault Mode” and to the implementation of the Pulse Width Modulation (PWM) in this product. 46.6 46.6.1 Functional Description Description All channels of the Timer Counter are independent and identical in operation except when the QDEC is enabled. The registers for channel programming are listed in Table 46-6 “Register Mapping”. 46.6.2 32-bit Counter Each 32-bit channel is organized around a 32-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 232-1 and passes to zero, an overflow occurs and the COVFS bit in the TC Status Register (TC_SR) is set. The current value of the counter is accessible in real time by reading the TC Counter Value Register (TC_CV). The counter can be reset by a trigger. In this case, the counter value passes to zero on the next valid edge of the selected clock. 46.6.3 Clock Selection At block level, input clock signals of each channel can be connected either to the external inputs TCLKx, or to the internal I/O signals TIOAx for chaining(1) by programming the TC Block Mode Register (TC_BMR). Refer to Figure 46-2. Each channel can independently select an internal or external clock source for its counter(2): • External clock signals: XC0, XC1 or XC2 • Internal clock signals: div2, div8, div32, div128, slow_clock This selection is made by the TCCLKS bits in the TC Channel Mode Register (TC_CMR). The selected clock can be inverted with the CLKI bit in the TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the TC_CMR defines this signal (none, XC0, XC1, XC2). Refer to Figure 46-3. Note 1: In Waveform mode, to chain two timers, it is mandatory to initialize some parameters: - Configure TIOx outputs to 1 or 0 by writing the required value to TC_CMR.ASWTRG. - Bit TC_BCR.SYNC must be written to 1 to start the channels at the same time. 2: In all cases, if an external clock is used, the duration of each of its levels must be longer than the peripheral clock period, so the clock frequency will be at least 2.5 times lower than the peripheral clock.  2017 Microchip Technology Inc. DS60001525A-page 1363 SAMA5D4 SERIES Figure 46-2: Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK0 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 46-3: Clock Selection TCCLKS TIMER_CLOCK1 Synchronous Edge Detection TIMER_CLOCK2 CLKI TIMER_CLOCK3 TIMER_CLOCK4 Selected Clock TIMER_CLOCK5 XC0 XC1 XC2 Peripheral Clock BURST 1 DS60001525A-page 1364  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. Refer to Figure 46-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the TC Channel Control Register (TC_CCR). In Capture mode it can be disabled by an RB load event if LDBDIS is set to 1 in the TC_CMR. In Waveform mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the TC_CCR can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the TC_SR. • The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture mode (LDBSTOP = 1 in TC_CMR) or an RC compare event in Waveform mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands are effective only if the clock is enabled. Figure 46-4: Clock Control Selected Clock Trigger CLKSTA Q Q S CLKEN CLKDIS S R R Counter Clock 46.6.5 Stop Event Disable Event Operating Modes Each channel can operate independently in two different modes: • Capture mode provides measurement on signals. • Waveform mode provides wave generation. The TC operating mode is programmed with the WAVE bit in the TC_CMR. In Capture mode, TIOAx and TIOBx are configured as inputs. In Waveform mode, TIOAx is always configured to be an output and TIOBx is an output if it is not selected to be the external trigger. 46.6.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. The following triggers are common to both modes: • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. • SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. • Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in the TC_CMR. The channel can also be configured to have an external trigger. In Capture mode, the external trigger signal can be selected between TIOAx and TIOBx. In Waveform mode, an external event can be programmed on one of the following signals: TIOBx, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting bit ENETRG in the TC_CMR.  2017 Microchip Technology Inc. DS60001525A-page 1365 SAMA5D4 SERIES If an external trigger is used, the duration of the pulses must be longer than the peripheral clock period in order to be detected. 46.6.7 Capture Mode Capture mode is entered by clearing the WAVE bit in the TC_CMR. Capture mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOAx and TIOBx signals which are considered as inputs. Figure 46-5 shows the configuration of the TC channel when programmed in Capture mode. 46.6.8 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. They can be loaded with the counter value when a programmable event occurs on the signal TIOAx. The LDRA field in the TC_CMR defines the TIOAx selected edge for the loading of register A, and the LDRB field defines the TIOAx selected edge for the loading of Register B. The subsampling ratio defined by the SBSMPLR field in TC_CMR is applied to these selected edges, so that the loading of Register A and Register B occurs once every 1, 2, 4, 8 or 16 selected edges. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS bit) in the TC_SR. In this case, the old value is overwritten. 46.6.9 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in the TC_CMR selects TIOAx or TIOBx input signal as an external trigger or the trigger signal from the output comparator of the PWM module. The External Trigger Edge Selection parameter (ETRGEDG field in TC_CMR) defines the edge (rising, falling, or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. DS60001525A-page 1366  2017 Microchip Technology Inc.  2017 Microchip Technology Inc. MTIOA MTIOB 1 BURST ABETRG SWTRG If RA is not loaded or RB is loaded Edge Detector ETRGEDG Peripheral Clock CLKI R S OVF R S LDRB Edge Detector Edge Detector Edge Subsampler SBSMPLR Capture Register A LDBSTOP LDRA If RA is loaded CPCTRG Counter RESET Trig CLK Q Q CLKEN Compare RC = Register C Timer/Counter Channel LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 Synchronous Edge Detection CLKSTA COVFS INT Figure 46-5: TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS SAMA5D4 SERIES Capture Mode LOVRS CPCS LDRBS ETRGS LDRAS TC1_IMR DS60001525A-page 1367 SAMA5D4 SERIES 46.6.10 Waveform Mode Waveform mode is entered by setting the TC_CMRx.WAVE bit. In Waveform mode, the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOAx is configured as an output and TIOBx is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 46-6 shows the configuration of the TC channel when programmed in Waveform operating mode. 46.6.11 Waveform Selection Depending on the WAVSEL parameter in TC_CMR, the behavior of TC_CV varies. With any selection, TC_RA, TC_RB and TC_RC can all be used as compare registers. RA Compare is used to control the TIOAx output, RB Compare is used to control the TIOBx output (if correctly configured) and RC Compare is used to control TIOAx and/or TIOBx outputs. DS60001525A-page 1368  2017 Microchip Technology Inc.  2017 Microchip Technology Inc. 1 EEVT BURST Timer/Counter Channel Edge Detector EEVTEDG SWTRG Peripheral Clock ENETRG CLKI Trig CLK R S OVF WAVSEL RESET Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 Synchronous Edge Detection TIOB MTIOB TIOA MTIOA Figure 46-6: TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS SAMA5D4 SERIES Waveform Mode Output Controller CPCS CPBS COVFS TC1_SR ETRGS TC1_IMR DS60001525A-page 1369 SAMA5D4 SERIES 46.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 232-1. Once 232-1 has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. Refer to Figure 46-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. Refer to Figure 46-8. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 46-7: WAVSEL = 00 without Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 46-8: WAVSEL = 00 with Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples Time TIOB TIOA DS60001525A-page 1370  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. Refer to Figure 46-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. Refer to Figure 46-10. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 46-9: WAVSEL = 10 without Trigger Counter Value 2n-1 (n = counter size) Counter cleared by compare match with RC RC RB RA Waveform Examples Time TIOB TIOA Figure 46-10: WAVSEL = 10 with Trigger Counter Value 2n-1 (n = counter size) Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples Time TIOB TIOA  2017 Microchip Technology Inc. DS60001525A-page 1371 SAMA5D4 SERIES 46.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 232-1 . Once 232-1 is reached, the value of TC_CV is decremented to 0, then re-incremented to 232-1 and so on. Refer to Figure 46-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. Refer to Figure 46-12. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 46-11: WAVSEL = 01 without Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 46-12: WAVSEL = 01 with Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF Counter decremented by trigger RC RB Counter incremented by trigger RA Waveform Examples Time TIOB TIOA 46.6.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. Refer to Figure 46-13. DS60001525A-page 1372  2017 Microchip Technology Inc. SAMA5D4 SERIES A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. Refer to Figure 46-14. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 46-13: WAVSEL = 11 without Trigger Counter Value 2n-1 (n = counter size) Counter decremented by compare match with RC RC RB RA Time Waveform Examples TIOB TIOA Figure 46-14: WAVSEL = 11 with Trigger Counter Value 2n-1 (n = counter size) RC RB Counter decremented by compare match with RC Counter decremented by trigger Counter incremented by trigger RA Waveform Examples Time TIOB TIOA  2017 Microchip Technology Inc. DS60001525A-page 1373 SAMA5D4 SERIES 46.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOBx. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOBx is defined as an external event signal (EEVT = 0), TIOBx is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOAx. When an external event is defined, it can be used as a trigger by setting bit ENETRG in the TC_CMR. As in Capture mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. 46.6.13 Synchronization with PWM The inputs TIOAx/TIOBx can be bypassed, and thus channel trigger/capture events can be directly driven by the independent PWM module. PWM comparator outputs (internal signals without dead-time insertion - OCx), respectively source of the PWMH/L[2:0] outputs, are routed to the internal TC inputs. These specific TC inputs are multiplexed with TIOA/B input signal to drive the internal trigger/capture events. The selection can be programmed in the Extended Mode Register (TC_EMR) fields TRIGSRCA and TRIGSRCB (refer to Section 46.7.13 “TC Extended Mode Register”). Each channel of the TC module can be synchronized by a different PWM channel as described in Figure 46-15. DS60001525A-page 1374  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 46-15: Synchronization with PWM Timer/Counter TC_EMR0.TRIGSRCA Timer/Counter Channel 0 TIOA0 TIOA0 1 TC_EMR0.TRIGSRCB TIOB0 TIOB0 1 TC_EMR1.TRIGSRCA Timer/Counter Channel 1 TIOA1 TIOA1 1 TC_EMR1.TRIGSRCB TIOB1 TIOB1 1 TC_EMR2.TRIGSRCA Timer/Counter Channel 2 TIOA2 TIOA2 1 TC_EMR2.TRIGSRCB TIOB2 TIOB2 1 PWM comparator outputs (internal signals) respectively source of PWMH/L[2:0]  2017 Microchip Technology Inc. DS60001525A-page 1375 SAMA5D4 SERIES 46.6.14 Output Controller The output controller defines the output level changes on TIOAx and TIOBx following an event. TIOBx Control is used only if TIOBx is defined as output (not as an external event). The following events control TIOAx and TIOBx: • Software Trigger • External Event • RC Compare RA Compare controls TIOAx, and RB Compare controls TIOBx. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 46.6.15 46.6.15.1 Quadrature Decoder Description The quadrature decoder (QDEC) is driven by TIOA0, TIOB0, TIOB1 input pins and drives the timer/counter of channel 0 and 1. Channel 2 can be used as a time base in case of speed measurement requirements (refer to Figure 46-16). When writing a 0 to bit QDEN of the TC_BMR, the QDEC is bypassed and the IO pins are directly routed to the timer counter function. TIOA0 and TIOB0 are to be driven by the two dedicated quadrature signals from a rotary sensor mounted on the shaft of the off-chip motor. A third signal from the rotary sensor can be processed through pin TIOB1 and is typically dedicated to be driven by an index signal if it is provided by the sensor. This signal is not required to decode the quadrature signals PHA, PHB. Field TCCLKS of TC_CMRx must be configured to select XC0 input (i.e., 0x101). Field TC0XC0S has no effect as soon as the QDEC is enabled. Either speed or position/revolution can be measured. Position channel 0 accumulates the edges of PHA, PHB input signals giving a high accuracy on motor position whereas channel 1 accumulates the index pulses of the sensor, therefore the number of rotations. Concatenation of both values provides a high level of precision on motion system position. In Speed mode, position cannot be measured but revolution can be measured. Inputs from the rotary sensor can be filtered prior to down-stream processing. Accommodation of input polarity, phase definition and other factors are configurable. Interruptions can be generated on different events. A compare function (using TC_RC) is available on channel 0 (speed/position) or channel 1 (rotation) and can generate an interrupt by means of the CPCS flag in the TC_SRx. DS60001525A-page 1376  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 46-16: Predefined Connection of the Quadrature Decoder with Timer Counters Reset pulse SPEEDEN Quadrature Decoder 1 1 (Filter + Edge Detect + QD) TIOA Timer/Counter Channel 0 TIOA0 QDEN PHEdges 1 TIOB 1 XC0 TIOB0 TIOA0 PHA TIOB0 PHB TIOB1 IDX XC0 Speed/Position QDEN Index 1 TIOB TIOB1 1 XC0 Timer/Counter Channel 1 XC0 Rotation Direction Timer/Counter Channel 2 Speed Time Base 46.6.15.2 Input Pre-processing Input pre-processing consists of capabilities to take into account rotary sensor factors such as polarities and phase definition followed by configurable digital filtering. Each input can be negated and swapping PHA, PHB is also configurable. The MAXFILT field in the TC_BMR is used to configure a minimum duration for which the pulse is stated as valid. When the filter is active, pulses with a duration lower than MAXFILT +1 × tperipheral clock ns are not passed to down-stream logic.  2017 Microchip Technology Inc. DS60001525A-page 1377 SAMA5D4 SERIES Figure 46-17: Input Stage Input Pre-Processing MAXFILT SWAP 1 PHA Filter TIOA0 MAXFILT > 0 1 PHedge Direction and Edge Detection INVA 1 PHB Filter TIOB0 1 DIR 1 IDX INVB 1 1 IDX Filter TIOB1 IDXPHB INVIDX Input filtering can efficiently remove spurious pulses that might be generated by the presence of particulate contamination on the optical or magnetic disk of the rotary sensor. Spurious pulses can also occur in environments with high levels of electro-magnetic interference. Or, simply if vibration occurs even when rotation is fully stopped and the shaft of the motor is in such a position that the beginning of one of the reflective or magnetic bars on the rotary sensor disk is aligned with the light or magnetic (Hall) receiver cell of the rotary sensor. Any vibration can make the PHA, PHB signals toggle for a short duration. DS60001525A-page 1378  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 46-18: Filtering Examples MAXFILT = 2 Peripheral Clock particulate contamination PHA,B Filter Out Optical/Magnetic disk strips PHA PHB motor shaft stopped in such a position that rotary sensor cell is aligned with an edge of the disk rotation stop PHA PHB Edge area due to system vibration PHB Resulting PHA, PHB electrical waveforms PHA stop mechanical shock on system PHB vibration PHA, PHB electrical waveforms after filtering PHA PHB  2017 Microchip Technology Inc. DS60001525A-page 1379 SAMA5D4 SERIES 46.6.15.3 Direction Status and Change Detection After filtering, the quadrature signals are analyzed to extract the rotation direction and edges of the two quadrature signals detected in order to be counted by timer/counter logic downstream. The direction status can be directly read at anytime in the TC_QISR. The polarity of the direction flag status depends on the configuration written in TC_BMR. INVA, INVB, INVIDX, SWAP modify the polarity of DIR flag. Any change in rotation direction is reported in the TC_QISR and can generate an interrupt. The direction change condition is reported as soon as two consecutive edges on a phase signal have sampled the same value on the other phase signal and there is an edge on the other signal. The two consecutive edges of one phase signal sampling the same value on other phase signal is not sufficient to declare a direction change, for the reason that particulate contamination may mask one or more reflective bars on the optical or magnetic disk of the sensor. Refer to Figure 46-19 for waveforms. Figure 46-19: Rotation Change Detection Direction Change under normal conditions PHA change condition Report Time PHB DIR DIRCHG No direction change due to particulate contamination masking a reflective bar missing pulse PHA same phase PHB DIR spurious change condition (if detected in a simple way) DIRCHG The direction change detection is disabled when QDTRANS is set in the TC_BMR. In this case, the DIR flag report must not be used. A quadrature error is also reported by the QDEC via the QERR flag in the TC_QISR. This error is reported if the time difference between two edges on PHA, PHB is lower than a predefined value. This predefined value is configurable and corresponds to (MAXFILT + 1) × tperipheral clock ns. After being filtered there is no reason to have two edges closer than (MAXFILT + 1) × tperipheral clock ns under normal mode of operation. DS60001525A-page 1380  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 46-20: Quadrature Error Detection MAXFILT = 2 Peripheral Clock Abnormally formatted optical disk strips (theoretical view) PHA PHB strip edge inaccuracy due to disk etching/printing process PHA PHB resulting PHA, PHB electrical waveforms PHA Even with an abnormally formatted disk, there is no occurrence of PHA, PHB switching at the same time. PHB duration < MAXFILT QERR MAXFILT must be tuned according to several factors such as the peripheral clock frequency, type of rotary sensor and rotation speed to be achieved. 46.6.15.4 Position and Rotation Measurement When the POSEN bit is set in the TC_BMR, the motor axis position is processed on channel 0 (by means of the PHA, PHB edge detections) and the number of motor revolutions are recorded on channel 1 if the IDX signal is provided on the TIOB1 input. If no IDX signal is available, the internal counter can be cleared for each revolution if the number of counts per revolution is configured in TC_RC0.RC and the TC_CMR.CPCTRG bit is written to 1. The position measurement can be read in the TC_CV0 register and the rotation measurement can be read in the TC_CV1 register. Channel 0 and 1 must be configured in Capture mode (TC_CMR0.WAVE = 0). ‘Rising edge’ must be selected as the External Trigger Edge (TC_CMR.ETRGEDG = 0x01) and ‘TIOAx’ must be selected as the External Trigger (TC_CMR.ABETRG = 0x1). In parallel, the number of edges are accumulated on timer/counter channel 0 and can be read on the TC_CV0 register. Therefore, the accurate position can be read on both TC_CV registers and concatenated to form a 32-bit word. The timer/counter channel 0 is cleared for each increment of IDX count value. Depending on the quadrature signals, the direction is decoded and allows to count up or down in timer/counter channels 0 and 1. The direction status is reported on TC_QISR.  2017 Microchip Technology Inc. DS60001525A-page 1381 SAMA5D4 SERIES 46.6.15.5 Speed Measurement When SPEEDEN is set in the TC_BMR, the speed measure is enabled on channel 0. A time base must be defined on channel 2 by writing the TC_RC2 period register. Channel 2 must be configured in Waveform mode (WAVE bit set) in TC_CMR2. The WAVSEL field must be defined with 0x10 to clear the counter by comparison and matching with TC_RC value. Field ACPC must be defined at 0x11 to toggle TIOAx output. This time base is automatically fed back to TIOAx of channel 0 when QDEN and SPEEDEN are set. Channel 0 must be configured in Capture mode (WAVE = 0 in TC_CMR0). The ABETRG bit of TC_CMR0 must be configured at 1 to select TIOAx as a trigger for this channel. EDGTRG must be set to 0x01, to clear the counter on a rising edge of the TIOAx signal and field LDRA must be set accordingly to 0x01, to load TC_RA0 at the same time as the counter is cleared (LDRB must be set to 0x01). As a consequence, at the end of each time base period the differentiation required for the speed calculation is performed. The process must be started by configuring bits CLKEN and SWTRG in the TC_CCR. The speed can be read on field RA in TC_RA0. Channel 1 can still be used to count the number of revolutions of the motor. 46.6.15.6 Detecting a Missing Index Pulse To detect a missing index pulse due contamination, dust, etc., the TC_SR0.CPCS flag can be used. It is also possible to assert the interrupt line if the TC_SR0.CPCS flag is enabled as a source of the interrupt by writing a ‘1’ to TC_IER0.CPCS. The TC_RC0.RC field must be written with the nominal number of counts per revolution provided by the rotary encoder, plus a margin to eliminate potential noise (e.g., if nominal count per revolution is 1024, then TC_RC0.RC=1028). If the index pulse is missing, the timer value is not cleared and the nominal value is exceeded, then the comparator on the RC triggers an event, TC_SR0.CPCS=1, and the interrupt line is asserted if TC_IER0.CPCS=1. 46.6.16 2-bit Gray Up/Down Counter for Stepper Motor Each channel can be independently configured to generate a 2-bit Gray count waveform on corresponding TIOAx, TIOBx outputs by means of the GCEN bit in TC_SMMRx. Up or Down count can be defined by writing bit DOWN in TC_SMMRx. It is mandatory to configure the channel in Waveform mode in the TC_CMR. The period of the counters can be programmed in TC_RCx. Figure 46-21: 2-bit Gray Up/Down Counter WAVEx = GCENx =1 TIOAx TC_RCx TIOBx DOWNx 46.6.17 Fault Mode At any time, the TC_RCx registers can be used to perform a comparison on the respective current channel counter value (TC_CVx) with the value of TC_RCx register. The CPCSx flags can be set accordingly and an interrupt can be generated. This interrupt is processed but requires an unpredictable amount of time to be achieve the required action. It is possible to trigger the FAULT output of the TIMER1 with CPCS from TC_SR0 and/or CPCS from TC_SR1. Each source can be independently enabled/disabled in the TC_FMR. DS60001525A-page 1382  2017 Microchip Technology Inc. SAMA5D4 SERIES This can be useful to detect an overflow on speed and/or position when QDEC is processed and to act immediately by using the FAULT output. Figure 46-22: Fault Output Generation AND TC_SR0 flag CPCS OR TC_FMR / ENCF0 AND FAULT (to PWM input) TC_SR1 flag CPCS TC_FMR / ENCF1 46.6.18 Register Write Protection To prevent any single software error from corrupting TC behavior, certain registers in the address space can be write-protected by setting the WPEN bit in the TC Write Protection Mode Register (TC_WPMR). The Timer Counter clock of the first channel must be enabled to access TC_WPMR. The following registers can be write-protected: • • • • • • • • • TC Block Mode Register TC Channel Mode Register: Capture Mode TC Channel Mode Register: Waveform Mode TC Fault Mode Register TC Stepper Motor Mode Register TC Register A TC Register B TC Register C TC Extended Mode Register  2017 Microchip Technology Inc. DS60001525A-page 1383 SAMA5D4 SERIES 46.7 Timer Counter (TC) User Interface Table 46-6: Register Mapping Offset(1) Register Name Access Reset 0x00 + channel * 0x40 + 0x00 Channel Control Register TC_CCR Write-only – 0x00 + channel * 0x40 + 0x04 Channel Mode Register TC_CMR Read/Write 0 0x00 + channel * 0x40 + 0x08 Stepper Motor Mode Register TC_SMMR Read/Write 0 0x00 + channel * 0x40 + 0x0C Reserved – – – 0x00 + channel * 0x40 + 0x10 Counter Value TC_CV 0x00 + channel * 0x40 + 0x14 Register A Read-only 0 TC_RA Read/Write (2) 0 0 0x00 + channel * 0x40 + 0x18 Register B TC_RB Read/Write(2) 0x00 + channel * 0x40 + 0x1C Register C TC_RC Read/Write 0 0x00 + channel * 0x40 + 0x20 Status Register TC_SR Read-only 0 0x00 + channel * 0x40 + 0x24 Interrupt Enable Register TC_IER Write-only – 0x00 + channel * 0x40 + 0x28 Interrupt Disable Register TC_IDR Write-only – 0x00 + channel * 0x40 + 0x2C Interrupt Mask Register TC_IMR Read-only 0 0x00 + channel * 0x40 + 0x30 Extended Mode Register TC_EMR Read/Write 0 0xC0 Block Control Register TC_BCR Write-only – 0xC4 Block Mode Register TC_BMR Read/Write 0 0xC8 QDEC Interrupt Enable Register TC_QIER Write-only – 0xCC QDEC Interrupt Disable Register TC_QIDR Write-only – 0xD0 QDEC Interrupt Mask Register TC_QIMR Read-only 0 0xD4 QDEC Interrupt Status Register TC_QISR Read-only 0 0xD8 Fault Mode Register TC_FMR Read/Write 0 0xE4 Write Protection Mode Register TC_WPMR Read/Write 0 Reserved – – – 0xE8–0xFC Note 1: Channel index ranges from 0 to 2. 2: Read-only if TC_CMRx.WAVE = 0 DS60001525A-page 1384  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.7.1 TC Channel Control Register Name:TC_CCRx [x=0..2] Address:0xF801C000 (0)[0], 0xF801C040 (0)[1], 0xF801C080 (0)[2], 0xFC020000 (1)[0], 0xFC020040 (1)[1], 0xFC020080 (1)[2], 0xFC024000 (2)[0], 0xFC024040 (2)[1], 0xFC024080 (2)[2] Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 SWTRG 1 CLKDIS 0 CLKEN CLKEN: Counter Clock Enable Command 0: No effect. 1: Enables the clock if CLKDIS is not 1. CLKDIS: Counter Clock Disable Command 0: No effect. 1: Disables the clock. SWTRG: Software Trigger Command 0: No effect. 1: A software trigger is performed: the counter is reset and the clock is started.  2017 Microchip Technology Inc. DS60001525A-page 1385 SAMA5D4 SERIES 46.7.2 TC Channel Mode Register: Capture Mode Name:TC_CMRx [x=0..2] (CAPTURE_MODE) Address:0xF801C004 (0)[0], 0xF801C044 (0)[1], 0xF801C084 (0)[2], 0xFC020004 (1)[0], 0xFC020044 (1)[1], 0xFC020084 (1)[2], 0xFC024004 (2)[0], 0xFC024044 (2)[1], 0xFC024084 (2)[2] Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 SBSMPLR 20 19 18 17 16 15 WAVE 14 CPCTRG 13 – 12 – 11 – 10 ABETRG 9 7 LDBDIS 6 LDBSTOP 5 4 3 CLKI 2 1 TCCLKS LDRB BURST LDRA 8 ETRGEDG 0 This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. TCCLKS: Clock Selection Value Name Description 0 TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 1 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 2 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 3 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 4 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 5 XC0 Clock selected: XC0 6 XC1 Clock selected: XC1 7 XC2 Clock selected: XC2 To operate at maximum peripheral clock frequency, refer to Section 46.7.13 “TC Extended Mode Register”. CLKI: Clock Invert 0: Counter is incremented on rising edge of the clock. 1: Counter is incremented on falling edge of the clock. BURST: Burst Signal Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 XC0 XC0 is ANDed with the selected clock. 2 XC1 XC1 is ANDed with the selected clock. 3 XC2 XC2 is ANDed with the selected clock. LDBSTOP: Counter Clock Stopped with RB Loading 0: Counter clock is not stopped when RB loading occurs. 1: Counter clock is stopped when RB loading occurs. DS60001525A-page 1386  2017 Microchip Technology Inc. SAMA5D4 SERIES LDBDIS: Counter Clock Disable with RB Loading 0: Counter clock is not disabled when RB loading occurs. 1: Counter clock is disabled when RB loading occurs. ETRGEDG: External Trigger Edge Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge ABETRG: TIOAx or TIOBx External Trigger Selection 0: TIOBx is used as an external trigger. 1: TIOAx is used as an external trigger. CPCTRG: RC Compare Trigger Enable 0: RC Compare has no effect on the counter and its clock. 1: RC Compare resets the counter and starts the counter clock. WAVE: Waveform Mode 0: Capture mode is enabled. 1: Capture mode is disabled (Waveform mode is enabled). LDRA: RA Loading Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge of TIOAx 2 FALLING Falling edge of TIOAx 3 EDGE Each edge of TIOAx LDRB: RB Loading Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge of TIOAx 2 FALLING Falling edge of TIOAx 3 EDGE Each edge of TIOAx SBSMPLR: Loading Edge Subsampling Ratio Value Name Description 0 ONE Load a Capture Register each selected edge 1 HALF Load a Capture Register every 2 selected edges 2 FOURTH Load a Capture Register every 4 selected edges 3 EIGHTH Load a Capture Register every 8 selected edges 4 SIXTEENTH Load a Capture Register every 16 selected edges  2017 Microchip Technology Inc. DS60001525A-page 1387 SAMA5D4 SERIES 46.7.3 TC Channel Mode Register: Waveform Mode Name:TC_CMRx [x=0..2] (WAVEFORM_MODE) Address:0xF801C004 (0)[0], 0xF801C044 (0)[1], 0xF801C084 (0)[2], 0xFC020004 (1)[0], 0xFC020044 (1)[1], 0xFC020084 (1)[2], 0xFC024004 (2)[0], 0xFC024044 (2)[1], 0xFC024084 (2)[2] Access:Read/Write 31 30 29 BSWTRG 23 28 27 BEEVT 22 20 19 AEEVT 15 WAVE 14 13 7 CPCDIS 6 CPCSTOP WAVSEL 25 24 BCPC 21 ASWTRG 26 BCPB 18 17 16 ACPC 12 ENETRG 11 4 3 CLKI 5 BURST ACPA 10 9 EEVT 8 EEVTEDG 2 1 TCCLKS 0 This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. TCCLKS: Clock Selection Value Name Description 0 TIMER_CLOCK1 Clock selected: internal div2 clock signal (from PMC) 1 TIMER_CLOCK2 Clock selected: internal div8 clock signal (from PMC) 2 TIMER_CLOCK3 Clock selected: internal div32 clock signal (from PMC) 3 TIMER_CLOCK4 Clock selected: internal div128 clock signal (from PMC) 4 TIMER_CLOCK5 Clock selected: internal slow_clock clock signal (from PMC) 5 XC0 Clock selected: XC0 6 XC1 Clock selected: XC1 7 XC2 Clock selected: XC2 To operate at maximum peripheral clock frequency, refer to Section 46.7.13 “TC Extended Mode Register”. CLKI: Clock Invert 0: Counter is incremented on rising edge of the clock. 1: Counter is incremented on falling edge of the clock. BURST: Burst Signal Selection Value Name Description 0 NONE The clock is not gated by an external signal. 1 XC0 XC0 is ANDed with the selected clock. 2 XC1 XC1 is ANDed with the selected clock. 3 XC2 XC2 is ANDed with the selected clock. CPCSTOP: Counter Clock Stopped with RC Compare 0: Counter clock is not stopped when counter reaches RC. 1: Counter clock is stopped when counter reaches RC. DS60001525A-page 1388  2017 Microchip Technology Inc. SAMA5D4 SERIES CPCDIS: Counter Clock Disable with RC Compare 0: Counter clock is not disabled when counter reaches RC. 1: Counter clock is disabled when counter reaches RC. EEVTEDG: External Event Edge Selection Value Name Description 0 NONE None 1 RISING Rising edge 2 FALLING Falling edge 3 EDGE Each edge EEVT: External Event Selection Signal selected as external event. Value Name Description TIOB Direction 0 TIOB TIOB(1) Input 1 XC0 XC0 Output 2 XC1 XC1 Output 3 XC2 XC2 Output Note 1: If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. ENETRG: External Event Trigger Enable 0: The external event has no effect on the counter and its clock. 1: The external event resets the counter and starts the counter clock. Note: Whatever the value programmed in ENETRG, the selected external event only controls the TIOAx output and TIOBx if not used as input (trigger event input or other input used). WAVSEL: Waveform Selection Value Name Description 0 UP UP mode without automatic trigger on RC Compare 1 UPDOWN UPDOWN mode without automatic trigger on RC Compare 2 UP_RC UP mode with automatic trigger on RC Compare 3 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare WAVE: Waveform Mode 0: Waveform mode is disabled (Capture mode is enabled). 1: Waveform mode is enabled. ACPA: RA Compare Effect on TIOAx Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle  2017 Microchip Technology Inc. DS60001525A-page 1389 SAMA5D4 SERIES ACPC: RC Compare Effect on TIOAx Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle AEEVT: External Event Effect on TIOAx Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle ASWTRG: Software Trigger Effect on TIOAx Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle BCPB: RB Compare Effect on TIOBx Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle BCPC: RC Compare Effect on TIOBx Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle BEEVT: External Event Effect on TIOBx Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle DS60001525A-page 1390  2017 Microchip Technology Inc. SAMA5D4 SERIES BSWTRG: Software Trigger Effect on TIOBx Value Name Description 0 NONE None 1 SET Set 2 CLEAR Clear 3 TOGGLE Toggle  2017 Microchip Technology Inc. DS60001525A-page 1391 SAMA5D4 SERIES 46.7.4 TC Stepper Motor Mode Register Name:TC_SMMRx [x=0..2] Address:0xF801C008 (0)[0], 0xF801C048 (0)[1], 0xF801C088 (0)[2], 0xFC020008 (1)[0], 0xFC020048 (1)[1], 0xFC020088 (1)[2], 0xFC024008 (2)[0], 0xFC024048 (2)[1], 0xFC024088 (2)[2] Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 DOWN 0 GCEN This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. GCEN: Gray Count Enable 0: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by internal counter of channel x. 1: TIOAx [x=0..2] and TIOBx [x=0..2] are driven by a 2-bit Gray counter. DOWN: Down Count 0: Up counter. 1: Down counter. DS60001525A-page 1392  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.7.5 TC Counter Value Register Name:TC_CVx [x=0..2] Address:0xF801C010 (0)[0], 0xF801C050 (0)[1], 0xF801C090 (0)[2], 0xFC020010 (1)[0], 0xFC020050 (1)[1], 0xFC020090 (1)[2], 0xFC024010 (2)[0], 0xFC024050 (2)[1], 0xFC024090 (2)[2] Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CV 23 22 21 20 CV 15 14 13 12 CV 7 6 5 4 CV CV: Counter Value CV contains the counter value in real time.  2017 Microchip Technology Inc. DS60001525A-page 1393 SAMA5D4 SERIES 46.7.6 TC Register A Name:TC_RAx [x=0..2] Address:0xF801C014 (0)[0], 0xF801C054 (0)[1], 0xF801C094 (0)[2], 0xFC020014 (1)[0], 0xFC020054 (1)[1], 0xFC020094 (1)[2], 0xFC024014 (2)[0], 0xFC024054 (2)[1], 0xFC024094 (2)[2] Access:Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RA 23 22 21 20 RA 15 14 13 12 RA 7 6 5 4 RA This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. RA: Register A RA contains the Register A value in real time. DS60001525A-page 1394  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.7.7 TC Register B Name:TC_RBx [x=0..2] Address:0xF801C018 (0)[0], 0xF801C058 (0)[1], 0xF801C098 (0)[2], 0xFC020018 (1)[0], 0xFC020058 (1)[1], 0xFC020098 (1)[2], 0xFC024018 (2)[0], 0xFC024058 (2)[1], 0xFC024098 (2)[2] Access:Read-only if TC_CMRx.WAVE = 0, Read/Write if TC_CMRx.WAVE = 1 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RB 23 22 21 20 RB 15 14 13 12 RB 7 6 5 4 RB This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. RB: Register B RB contains the Register B value in real time.  2017 Microchip Technology Inc. DS60001525A-page 1395 SAMA5D4 SERIES 46.7.8 TC Register C Name:TC_RCx [x=0..2] Address:0xF801C01C (0)[0], 0xF801C05C (0)[1], 0xF801C09C (0)[2], 0xFC02001C (1)[0], 0xFC02005C (1)[1], 0xFC02009C (1)[2], 0xFC02401C (2)[0], 0xFC02405C (2)[1], 0xFC02409C (2)[2] Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RC 23 22 21 20 RC 15 14 13 12 RC 7 6 5 4 RC This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. RC: Register C RC contains the Register C value in real time. DS60001525A-page 1396  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.7.9 TC Status Register Name:TC_SRx [x=0..2] Address:0xF801C020 (0)[0], 0xF801C060 (0)[1], 0xF801C0A0 (0)[2], 0xFC020020 (1)[0], 0xFC020060 (1)[1], 0xFC0200A0 (1)[2], 0xFC024020 (2)[0], 0xFC024060 (2)[1], 0xFC0240A0 (2)[2] Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 MTIOB 17 MTIOA 16 CLKSTA 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS COVFS: Counter Overflow Status (cleared on read) 0: No counter overflow has occurred since the last read of the Status Register. 1: A counter overflow has occurred since the last read of the Status Register. LOVRS: Load Overrun Status (cleared on read) 0: Load overrun has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1. 1: RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if TC_CMRx.WAVE = 0. CPAS: RA Compare Status (cleared on read) 0: RA Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0. 1: RA Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1. CPBS: RB Compare Status (cleared on read) 0: RB Compare has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 0. 1: RB Compare has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 1. CPCS: RC Compare Status (cleared on read) 0: RC Compare has not occurred since the last read of the Status Register. 1: RC Compare has occurred since the last read of the Status Register. LDRAS: RA Loading Status (cleared on read) 0: RA Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1. 1: RA Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0. LDRBS: RB Loading Status (cleared on read) 0: RB Load has not occurred since the last read of the Status Register or TC_CMRx.WAVE = 1. 1: RB Load has occurred since the last read of the Status Register, if TC_CMRx.WAVE = 0. ETRGS: External Trigger Status (cleared on read) 0: External trigger has not occurred since the last read of the Status Register. 1: External trigger has occurred since the last read of the Status Register.  2017 Microchip Technology Inc. DS60001525A-page 1397 SAMA5D4 SERIES CLKSTA: Clock Enabling Status 0: Clock is disabled. 1: Clock is enabled. MTIOA: TIOAx Mirror 0: TIOAx is low. If TC_CMRx.WAVE = 0, this means that TIOAx pin is low. If TC_CMRx.WAVE = 1, this means that TIOAx is driven low. 1: TIOAx is high. If TC_CMRx.WAVE = 0, this means that TIOAx pin is high. If TC_CMRx.WAVE = 1, this means that TIOAx is driven high. MTIOB: TIOBx Mirror 0: TIOBx is low. If TC_CMRx.WAVE = 0, this means that TIOBx pin is low. If TC_CMRx.WAVE = 1, this means that TIOBx is driven low. 1: TIOBx is high. If TC_CMRx.WAVE = 0, this means that TIOBx pin is high. If TC_CMRx.WAVE = 1, this means that TIOBx is driven high. DS60001525A-page 1398  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.7.10 TC Interrupt Enable Register Name:TC_IERx [x=0..2] Address:0xF801C024 (0)[0], 0xF801C064 (0)[1], 0xF801C0A4 (0)[2], 0xFC020024 (1)[0], 0xFC020064 (1)[1], 0xFC0200A4 (1)[2], 0xFC024024 (2)[0], 0xFC024064 (2)[1], 0xFC0240A4 (2)[2] Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS COVFS: Counter Overflow 0: No effect. 1: Enables the Counter Overflow Interrupt. LOVRS: Load Overrun 0: No effect. 1: Enables the Load Overrun Interrupt. CPAS: RA Compare 0: No effect. 1: Enables the RA Compare Interrupt. CPBS: RB Compare 0: No effect. 1: Enables the RB Compare Interrupt. CPCS: RC Compare 0: No effect. 1: Enables the RC Compare Interrupt. LDRAS: RA Loading 0: No effect. 1: Enables the RA Load Interrupt. LDRBS: RB Loading 0: No effect. 1: Enables the RB Load Interrupt. ETRGS: External Trigger 0: No effect. 1: Enables the External Trigger Interrupt.  2017 Microchip Technology Inc. DS60001525A-page 1399 SAMA5D4 SERIES 46.7.11 TC Interrupt Disable Register Name:TC_IDRx [x=0..2] Address:0xF801C028 (0)[0], 0xF801C068 (0)[1], 0xF801C0A8 (0)[2], 0xFC020028 (1)[0], 0xFC020068 (1)[1], 0xFC0200A8 (1)[2], 0xFC024028 (2)[0], 0xFC024068 (2)[1], 0xFC0240A8 (2)[2] Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS COVFS: Counter Overflow 0: No effect. 1: Disables the Counter Overflow Interrupt. LOVRS: Load Overrun 0: No effect. 1: Disables the Load Overrun Interrupt (if TC_CMRx.WAVE = 0). CPAS: RA Compare 0: No effect. 1: Disables the RA Compare Interrupt (if TC_CMRx.WAVE = 1). CPBS: RB Compare 0: No effect. 1: Disables the RB Compare Interrupt (if TC_CMRx.WAVE = 1). CPCS: RC Compare 0: No effect. 1: Disables the RC Compare Interrupt. LDRAS: RA Loading 0: No effect. 1: Disables the RA Load Interrupt (if TC_CMRx.WAVE = 0). LDRBS: RB Loading 0: No effect. 1: Disables the RB Load Interrupt (if TC_CMRx.WAVE = 0). ETRGS: External Trigger 0: No effect. 1: Disables the External Trigger Interrupt. DS60001525A-page 1400  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.7.12 TC Interrupt Mask Register Name:TC_IMRx [x=0..2] Address:0xF801C02C (0)[0], 0xF801C06C (0)[1], 0xF801C0AC (0)[2], 0xFC02002C (1)[0], 0xFC02006C (1)[1], 0xFC0200AC (1)[2], 0xFC02402C (2)[0], 0xFC02406C (2)[1], 0xFC0240AC (2)[2] Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS COVFS: Counter Overflow 0: The Counter Overflow Interrupt is disabled. 1: The Counter Overflow Interrupt is enabled. LOVRS: Load Overrun 0: The Load Overrun Interrupt is disabled. 1: The Load Overrun Interrupt is enabled. CPAS: RA Compare 0: The RA Compare Interrupt is disabled. 1: The RA Compare Interrupt is enabled. CPBS: RB Compare 0: The RB Compare Interrupt is disabled. 1: The RB Compare Interrupt is enabled. CPCS: RC Compare 0: The RC Compare Interrupt is disabled. 1: The RC Compare Interrupt is enabled. LDRAS: RA Loading 0: The Load RA Interrupt is disabled. 1: The Load RA Interrupt is enabled. LDRBS: RB Loading 0: The Load RB Interrupt is disabled. 1: The Load RB Interrupt is enabled. ETRGS: External Trigger 0: The External Trigger Interrupt is disabled. 1: The External Trigger Interrupt is enabled.  2017 Microchip Technology Inc. DS60001525A-page 1401 SAMA5D4 SERIES 46.7.13 TC Extended Mode Register Name:TC_EMRx [x=0..2] Address:0xF801C030 (0)[0], 0xF801C070 (0)[1], 0xF801C0B0 (0)[2], 0xFC020030 (1)[0], 0xFC020070 (1)[1], 0xFC0200B0 (1)[2], 0xFC024030 (2)[0], 0xFC024070 (2)[1], 0xFC0240B0 (2)[2] Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NODIVCLK 7 – 6 – 5 4 3 – 2 – 1 TRIGSRCB 0 TRIGSRCA TRIGSRCA: Trigger Source for Input A Value Name Description 0 EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 1 PWMx The trigger/capture input A is driven internally by PWMx TRIGSRCB: Trigger Source for Input B Value Name Description 0 EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 1 PWMx The trigger/capture input B is driven internally by the comparator output (refer to Figure 46-15) of the PWMx. NODIVCLK: No Divided Clock 0: The selected clock is defined by field TCCLKS in TC_CMRx. 1: The selected clock is peripheral clock and TCCLKS field (TC_CMRx) has no effect. DS60001525A-page 1402  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.7.14 TC Block Control Register Name:TC_BCR Address:0xF801C0C0 (0), 0xFC0200C0 (1), 0xFC0240C0 (2) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SYNC SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.  2017 Microchip Technology Inc. DS60001525A-page 1403 SAMA5D4 SERIES 46.7.15 TC Block Mode Register Name:TC_BMR Address:0xF801C0C4 (0), 0xFC0200C4 (1), 0xFC0240C4 (2) Access:Read/Write 31 – 30 – 23 22 29 – 28 – 27 – 26 – 25 21 20 19 – 18 – 17 IDXPHB 16 SWAP 12 EDGPHA 11 QDTRANS 10 SPEEDEN 9 POSEN 8 QDEN 4 3 2 1 0 MAXFILT 15 INVIDX 14 INVB 13 INVA 7 – 6 – 5 TC2XC2S TC1XC1S 24 MAXFILT TC0XC0S This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. TC0XC0S: External Clock Signal 0 Selection Value Name Description 0 TCLK0 Signal connected to XC0: TCLK0 1 – Reserved 2 TIOA1 Signal connected to XC0: TIOA1 3 TIOA2 Signal connected to XC0: TIOA2 TC1XC1S: External Clock Signal 1 Selection Value Name Description 0 TCLK1 Signal connected to XC1: TCLK1 1 – Reserved 2 TIOA0 Signal connected to XC1: TIOA0 3 TIOA2 Signal connected to XC1: TIOA2 TC2XC2S: External Clock Signal 2 Selection Value Name Description 0 TCLK2 Signal connected to XC2: TCLK2 1 – Reserved 2 TIOA0 Signal connected to XC2: TIOA0 3 TIOA1 Signal connected to XC2: TIOA1 QDEN: Quadrature Decoder Enabled 0: Disabled. 1: Enables the QDEC (filter, edge detection and quadrature decoding). Quadrature decoding (direction change) can be disabled using QDTRANS bit. One of the POSEN or SPEEDEN bits must be also enabled. DS60001525A-page 1404  2017 Microchip Technology Inc. SAMA5D4 SERIES POSEN: Position Enabled 0: Disable position. 1: Enables the position measure on channel 0 and 1. SPEEDEN: Speed Enabled 0: Disabled. 1: Enables the speed measure on channel 0, the time base being provided by channel 2. QDTRANS: Quadrature Decoding Transparent 0: Full quadrature decoding logic is active (direction change detected). 1: Quadrature decoding logic is inactive (direction change inactive) but input filtering and edge detection are performed. EDGPHA: Edge on PHA Count Mode 0: Edges are detected on PHA only. 1: Edges are detected on both PHA and PHB. INVA: Inverted PHA 0: PHA (TIOA0) is directly driving the QDEC. 1: PHA is inverted before driving the QDEC. INVB: Inverted PHB 0: PHB (TIOB0) is directly driving the QDEC. 1: PHB is inverted before driving the QDEC. INVIDX: Inverted Index 0: IDX (TIOA1) is directly driving the QDEC. 1: IDX is inverted before driving the QDEC. SWAP: Swap PHA and PHB 0: No swap between PHA and PHB. 1: Swap PHA and PHB internally, prior to driving the QDEC. IDXPHB: Index Pin is PHB Pin 0: IDX pin of the rotary sensor must drive TIOA1. 1: IDX pin of the rotary sensor must drive TIOB0. MAXFILT: Maximum Filter 1–63: Defines the filtering capabilities. Pulses with a period shorter than MAXFILT+1 peripheral clock cycles are discarded.  2017 Microchip Technology Inc. DS60001525A-page 1405 SAMA5D4 SERIES 46.7.16 TC QDEC Interrupt Enable Register Name:TC_QIER Address:0xF801C0C8 (0), 0xFC0200C8 (1), 0xFC0240C8 (2) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX IDX: Index 0: No effect. 1: Enables the interrupt when a rising edge occurs on IDX input. DIRCHG: Direction Change 0: No effect. 1: Enables the interrupt when a change on rotation direction is detected. QERR: Quadrature Error 0: No effect. 1: Enables the interrupt when a quadrature error occurs on PHA, PHB. DS60001525A-page 1406  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.7.17 TC QDEC Interrupt Disable Register Name:TC_QIDR Address:0xF801C0CC (0), 0xFC0200CC (1), 0xFC0240CC (2) Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX IDX: Index 0: No effect. 1: Disables the interrupt when a rising edge occurs on IDX input. DIRCHG: Direction Change 0: No effect. 1: Disables the interrupt when a change on rotation direction is detected. QERR: Quadrature Error 0: No effect. 1: Disables the interrupt when a quadrature error occurs on PHA, PHB.  2017 Microchip Technology Inc. DS60001525A-page 1407 SAMA5D4 SERIES 46.7.18 TC QDEC Interrupt Mask Register Name:TC_QIMR Address:0xF801C0D0 (0), 0xFC0200D0 (1), 0xFC0240D0 (2) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX IDX: Index 0: The interrupt on IDX input is disabled. 1: The interrupt on IDX input is enabled. DIRCHG: Direction Change 0: The interrupt on rotation direction change is disabled. 1: The interrupt on rotation direction change is enabled. QERR: Quadrature Error 0: The interrupt on quadrature error is disabled. 1: The interrupt on quadrature error is enabled. DS60001525A-page 1408  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.7.19 TC QDEC Interrupt Status Register Name:TC_QISR Address:0xF801C0D4 (0), 0xFC0200D4 (1), 0xFC0240D4 (2) Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 DIR 7 – 6 – 5 – 4 – 3 – 2 QERR 1 DIRCHG 0 IDX IDX: Index 0: No Index input change since the last read of TC_QISR. 1: The IDX input has changed since the last read of TC_QISR. DIRCHG: Direction Change 0: No change on rotation direction since the last read of TC_QISR. 1: The rotation direction changed since the last read of TC_QISR. QERR: Quadrature Error 0: No quadrature error since the last read of TC_QISR. 1: A quadrature error occurred since the last read of TC_QISR. DIR: Direction Returns an image of the rotation direction.  2017 Microchip Technology Inc. DS60001525A-page 1409 SAMA5D4 SERIES 46.7.20 TC Fault Mode Register Name:TC_FMR Address:0xF801C0D8 (0), 0xFC0200D8 (1), 0xFC0240D8 (2) Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 ENCF1 0 ENCF0 This register can only be written if the WPEN bit is cleared in the TC Write Protection Mode Register. ENCF0: Enable Compare Fault Channel 0 0: Disables the FAULT output source (CPCS flag) from channel 0. 1: Enables the FAULT output source (CPCS flag) from channel 0. ENCF1: Enable Compare Fault Channel 1 0: Disables the FAULT output source (CPCS flag) from channel 1. 1: Enables the FAULT output source (CPCS flag) from channel 1. DS60001525A-page 1410  2017 Microchip Technology Inc. SAMA5D4 SERIES 46.7.21 TC Write Protection Mode Register Name:TC_WPMR Address:0xF801C0E4 (0), 0xFC0200E4 (1), 0xFC0240E4 (2) Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – WPEN: Write Protection Enable 0: Disables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII). 1: Enables the write protection if WPKEY corresponds to 0x54494D (“TIM” in ASCII). The Timer Counter clock of the first channel must be enabled to access this register. Refer to Section 46.6.18 “Register Write Protection” for a list of registers that can be write-protected and Timer Counter clock conditions. WPKEY: Write Protection Key Value 0x54494D Name PASSWD  2017 Microchip Technology Inc. Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. DS60001525A-page 1411 SAMA5D4 SERIES 47. Pulse Width Modulation Controller (PWM) 47.1 Description The Pulse Width Modulation Controller (PWM) generates output pulses on 4 channels independently according to parameters defined per channel. Each channel controls two complementary square output waveforms. Characteristics of the output waveforms such as period, duty-cycle, polarity and dead-times (also called dead-bands or non-overlapping times) are configured through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM peripheral clock. All accesses to the PWM are made through registers mapped on the peripheral bus. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period, the spread spectrum, the duty-cycle or the dead-times. Channels can be linked together as synchronous channels to be able to update their duty-cycle or dead-times at the same time. The PWM includes a spread-spectrum counter to allow a constantly varying period (only for Channel 0). This counter may be useful to minimize electromagnetic interference or to reduce the acoustic noise of a PWM driven motor. The PWM provides 8 independent comparison units capable of comparing a programmed value to the counter of the synchronous channels (counter of channel 0). These comparisons are intended to generate software interrupts, to trigger pulses on the 2 independent event lines (in order to synchronize ADC conversions with a lot of flexibility independently of the PWM outputs). PWM outputs can be overridden synchronously or asynchronously to their channel counter. The PWM provides a fault protection mechanism with 8 fault inputs, capable to detect a fault condition and to override the PWM outputs asynchronously (outputs forced to ‘0’, ‘1’ or Hi-Z). For safety usage, some configuration registers are write-protected. 47.2 Embedded Characteristics • 4 Channels • Common Clock Generator Providing Thirteen Different Clocks - A Modulo n Counter Providing Eleven Clocks - Two Independent Linear Dividers Working on Modulo n Counter Outputs • Independent Channels - Independent 16-bit Counter for Each Channel - Independent Complementary Outputs with 12-bit Dead-Time Generator (Also Called Dead-Band or Non-Overlapping Time) for Each Channel - Independent Enable Disable Command for Each Channel - Independent Clock Selection for Each Channel - Independent Period, Duty-Cycle and Dead-Time for Each Channel - Independent Double Buffering of Period, Duty-Cycle and Dead-Times for Each Channel - Independent Programmable Selection of The Output Waveform Polarity for Each Channel, with Double Buffering - Independent Programmable Center- or Left-aligned Output Waveform for Each Channel - Independent Output Override for Each Channel - Independent Interrupt for Each Channel, at Each Period for Left-Aligned or Center-Aligned Configuration - Independent Update Time Selection of Double Buffering Registers (Polarity, Duty Cycle) for Each Channel, at Each Period for Left-Aligned or Center-Aligned Configuration • 2 2-bit Gray Up/Down Channels for Stepper Motor Control • Spread Spectrum Counter to Allow a Constantly Varying Duty Cycle (only for Channel 0) • Synchronous Channel Mode - Synchronous Channels Share the Same Counter - Mode to Update the Synchronous Channels Registers after a Programmable Number of Periods • 2 Independent Events Lines Intended to Synchronize ADC Conversions - Programmable delay for Events Lines to delay ADC measurements • 8 Comparison Units Intended to Generate Interrupts, Pulses on Event Lines DS60001525A-page 1412  2017 Microchip Technology Inc. SAMA5D4 SERIES • 8 Programmable Fault Inputs Providing an Asynchronous Protection of PWM Outputs - 2 User Driven through PIO Inputs - PMC Driven when Crystal Oscillator Clock Fails - ADC Controller Driven through Configurable Comparison Function - Timer/Counter Driven through Configurable Comparison Function • Register Write Protection 47.3 Block Diagram Figure 47-1: Pulse Width Modulation Controller Block Diagram PWM Controller Channel x Update Period Duty-Cycle MUX Counter Channel x Clock Selector DTOHx Dead-Time Generator DTOLx OOOHx Output Override OOOLx PWMHx Fault Protection PWMLx PWMHx PWMLx SYNCx Comparator OCx PIO Channel 0 Update Period Comparator OC0 DTOH0 Dead-Time Generator DTOL0 OOOH0 Output Override OOOL0 PWMH0 Fault Protection PWML0 PWMH0 PWML0 Duty-Cycle Counter Channel 0 Clock Selector PWMFIx PIO PWMFI0 event line 0 event line 1 Comparison Units Events Generator ADC event line x PMC Peripheral Clock CLOCK Generator APB Interface Interrupt Generator Interrupt Controller APB 47.4 I/O Lines Description Each channel outputs two complementary external I/O lines. Table 47-1: I/O Line Description Name Description Type PWMHx PWM Waveform Output High for channel x Output PWMLx PWM Waveform Output Low for channel x Output PWMFIx PWM Fault Input x Input  2017 Microchip Technology Inc. DS60001525A-page 1413 SAMA5D4 SERIES 47.5 Product Dependencies 47.5.1 I/O Lines The pins used for interfacing the PWM are multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines are assigned to PWM outputs. Table 47-2: I/O Lines Instance Signal I/O Line Peripheral PWM PWMFI0 PC29 C PWM PWMFI1 PE7 C PWM PWMH0 PA26 B PWM PWMH0 PB14 C PWM PWMH0 PB26 C PWM PWMH0 PC30 C PWM PWMH1 PA28 B PWM PWMH1 PB11 C PWM PWMH1 PB28 C PWM PWMH1 PC31 C PWM PWMH2 PC0 B PWM PWMH2 PE12 C PWM PWMH3 PC2 B PWM PWMH3 PE14 C PWM PWML0 PA27 B PWM PWML0 PB15 C PWM PWML0 PB27 C PWM PWML0 PC27 C PWM PWML1 PA29 B PWM PWML1 PB10 C PWM PWML1 PB29 C PWM PWML1 PC28 C PWM PWML2 PC1 B PWM PWML2 PE13 C PWM PWML3 PC3 B PWM PWML3 PE8 C 47.5.2 Power Management The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off. DS60001525A-page 1414  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.5.3 Interrupt Sources The PWM interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the PWM interrupt requires the Interrupt Controller to be programmed first. Table 47-3: Peripheral IDs Instance ID PWM 43 47.5.4 Fault Inputs The PWM has the fault inputs connected to the different modules. Refer to the implementation of these modules within the product for detailed information about the fault generation procedure. The PWM receives faults from: • • • • PIO inputs the PMC the ADC controller Timer/Counters Table 47-4: Fault Inputs Fault Generator External PWM Fault Input Number Polarity Level(1) Fault Input ID PC29 PWMFI0 User-defined 0 PE7 PWMFI1 User-defined 1 Main OSC (PMC) – To be configured to 1 2 ADC – To be configured to 1 3 Timer0 – To be configured to 1 4 Timer1 – To be configured to 1 5 Timer2 – To be configured to 1 6 Note 1: FPOL field in PWMC_FMR. 47.6 Functional Description The PWM controller is primarily composed of a clock generator module and 4 channels. • Clocked by the peripheral clock, the clock generator module provides 13 clocks. • Each channel can independently choose one of the clock generator outputs. • Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers.  2017 Microchip Technology Inc. DS60001525A-page 1415 SAMA5D4 SERIES 47.6.1 PWM Clock Generator Figure 47-2: Functional View of the Clock Generator Block Diagram Peripheral Clock modulo n counter peripheral clock peripheral clock/2 peripheral clock/4 peripheral clock/8 peripheral clock/16 peripheral clock/32 peripheral clock/64 peripheral clock/128 peripheral clock/256 peripheral clock/512 peripheral clock/1024 Divider A PREA clkA DIVA PWM_MR Divider B PREB clkB DIVB PWM_MR The PWM peripheral clock is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks. The clock generator is divided into different blocks: - a modulo n counter which provides 11 clocks: fperipheral clock, fperipheral clock/2, fperipheral clock/4, fperipheral clock/8, fperipheral clock/16, fperipheral clock/32, fperipheral clock/64, fperipheral clock/128, fperipheral clock/256, fperipheral clock/512, fperipheral clock/1024 - two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the PWM Clock register (PWM_CLK). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value. After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) are set to ‘0’. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except the peripheral clock. This situation is also true when the PWM peripheral clock is turned off through the Power Management Controller. CAUTION: Before using the PWM controller, the programmer must first enable the peripheral clock in the Power Management Controller (PMC). DS60001525A-page 1416  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.6.2 PWM Channel 47.6.2.1 Channel Block Diagram Figure 47-3: Functional View of the Channel Block Diagram Channel x Update Period MUX Comparator x OCx PWMHx OOOHx DTOHx Dead-Time Output Fault OOOLx Generator DTOLx Override Protection PWMLx Duty-Cycle MUX from Clock Generator Clock Selector SYNCx Counter Channel x from APB Peripheral Bus Counter Channel 0 2-bit gray counter z Comparator y MUX z = 0 (x = 0, y = 1), z = 1 (x = 2, y = 3), z = 2 (x = 4, y = 5), z = 3 (x = 6, y = 7) Channel y (= x+1) OCy PWMHy OOOHy DTOHy Dead-Time Output Fault OOOLy PWMLy Generator DTOLy Override Protection Each of the 4 channels is composed of six blocks: • A clock selector which selects one of the clocks provided by the clock generator (described in Section 47.6.1 “PWM Clock Generator”). • A counter clocked by the output of the clock selector. This counter is incremented or decremented according to the channel configuration and comparators matches. The size of the counter is 16 bits. • A comparator used to compute the OCx output waveform according to the counter value and the configuration. The counter value can be the one of the channel counter or the one of the channel 0 counter according to SYNCx bit in the PWM Sync Channels Mode Register (PWM_SCM). • A 2-bit configurable gray counter enables the stepper motor driver. One gray counter drives 2 channels. • A dead-time generator providing two complementary outputs (DTOHx/DTOLx) which allows to drive external power control switches safely. • An output override block that can force the two complementary outputs to a programmed value (OOOHx/OOOLx). • An asynchronous fault protection mechanism that has the highest priority to override the two complementary outputs (PWMHx/ PWMLx) in case of fault detection (outputs forced to ‘0’, ‘1’ or Hi-Z). 47.6.2.2 Comparator The comparator continuously compares its counter value with the channel period defined by CPRD in the PWM Channel Period Register (PWM_CPRDx) and the duty-cycle defined by CDTY in the PWM Channel Duty Cycle Register (PWM_CDTYx) to generate an output signal OCx accordingly. The different properties of the waveform of the output OCx are: • the clock selection. The channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the PWM Channel Mode Register (PWM_CMRx). This field is reset at ‘0’. • the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register. If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: By using the PWM peripheral clock divided by a given prescaler value “X” (where X = 2PREA is 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula is: ( X × CPRD )------------------------------f peripheral clock  2017 Microchip Technology Inc. DS60001525A-page 1417 SAMA5D4 SERIES By using the PWM peripheral clock divided by a given prescaler value “X” (see above) and by either the DIVA or the DIVB divider. The formula becomes, respectively: (--------------------------------------------------X × C RPD × DIVA )( X × C RPD × DIVB ) or ---------------------------------------------------f peripheral clock f peripheral clock If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated: By using the PWM peripheral clock divided by a given prescaler value “X” (where X = 2PREA is 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula is: ( 2 × X × CPRD ) ---------------------------------------f peripheral clock By using the PWM peripheral clock divided by a given prescaler value “X” (see above) and by either the DIVA or the DIVB divider. The formula becomes, respectively: ( 2 × X × C PRD × DIVA ) ------------------------------------------------------------or f peripheral clock ( 2 × X × C PRD × DIVB ) ------------------------------------------------------------f peripheral clock • the waveform duty-cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register. If the waveform is left-aligned, then: ( period – 1 ⁄ fchannel_x_clock × CDTY ) duty cycle = ---------------------------------------------------------------------------------------------------period If the waveform is center-aligned, then: ( ( period ⁄ 2 ) – 1 ⁄ fchannel_x_clock × CDTY ) ) duty cycle = ------------------------------------------------------------------------------------------------------------------( period ⁄ 2 ) • the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL bit of PWM_CMRx. By default, the signal starts by a low level. the waveform alignment. The output waveform can be left- or centeraligned. Center-aligned waveforms can be used to generate non-overlapped waveforms. This property is defined in the CALG bit of PWM_CMRx. The default mode is left-aligned. Figure 47-4: Non-Overlapped Center-Aligned Waveforms No overlap OC0 OC1 Period Note: Refer to Figure 47-5 for a detailed description of center-aligned waveforms. When center-aligned, the channel counter increases up to CPRD and decreases down to 0. This ends the period. When left-aligned, the channel counter increases up to CPRD and is reset. This ends the period. Thus, for the same CPRD value, the period for a center-aligned channel is twice the period for a left-aligned channel. Waveforms are fixed at 0 when: • CDTY = CPRD and CPOL = 0 • CDTY = 0 and CPOL = 1 Waveforms are fixed at 1 (once the channel is enabled) when: • CDTY = 0 and CPOL = 0 • CDTY = CPRD and CPOL = 1 The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. DS60001525A-page 1418  2017 Microchip Technology Inc. SAMA5D4 SERIES Modifying CPOL in PWM Channel Mode Register while the channel is enabled can lead to an unexpected behavior of the device being driven by PWM. In addition to generating the output signals OCx, the comparator generates interrupts depending on the counter value. When the output waveform is left-aligned, the interrupt occurs at the end of the counter period. When the output waveform is center-aligned, the bit CES of PWM_CMRx defines when the channel counter interrupt occurs. If CES is set to ‘0’, the interrupt occurs at the end of the counter period. If CES is set to ‘1’, the interrupt occurs at the end of the counter period and at half of the counter period. Figure 47-5 illustrates the counter interrupts depending on the configuration.  2017 Microchip Technology Inc. DS60001525A-page 1419 SAMA5D4 SERIES Figure 47-5: Waveform Properties Channel x slected clock CHIDx(PWM_SR) CHIDx(PWM_ENA) CHIDx(PWM_DIS) Center Aligned CALG(PWM_CMRx) = 1 PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) Period Output Waveform OCx CPOL(PWM_CMRx) = 0 Output Waveform OCx CPOL(PWM_CMRx) = 1 Counter Event CHIDx(PWM_ISR) CES(PWM_CMRx) = 0 Counter Event CHIDx(PWM_ISR) CES(PWM_CMRx) = 1 Left Aligned CALG(PWM_CMRx) = 0 PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) Period Output Waveform OCx CPOL(PWM_CMRx) = 0 Output Waveform OCx CPOL(PWM_CMRx) = 1 Counter Event CHIDx(PWM_ISR) DS60001525A-page 1420  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.6.2.3 2-bit Gray Up/Down Counter for Stepper Motor A pair of channels may provide a 2-bit gray count waveform on two outputs. Dead-time generator and other downstream logic can be configured on these channels. Up or Down Count mode can be configured on-the-fly by means of PWM_SMMR configuration registers. When GCEN0 is set to ‘1’, channels 0 and 1 outputs are driven with gray counter. Figure 47-6: 2-bit Gray Up/Down Counter GCEN0 = 1 PWMH0 PWML0 PWMH1 PWML1 DOWNx 47.6.2.4 Dead-Time Generator The dead-time generator uses the comparator output OCx to provide the two complementary outputs DTOHx and DTOLx, which allows the PWM macrocell to drive external power control switches safely. When the dead-time generator is enabled by setting the bit DTE to 1 or 0 in the PWM Channel Mode Register (PWM_CMRx), dead-times (also called dead-bands or non-overlapping times) are inserted between the edges of the two complementary outputs DTOHx and DTOLx. Note that enabling or disabling the dead-time generator is allowed only if the channel is disabled. The dead-time is adjustable by the PWM Channel Dead Time Register (PWM_DTx). Each output of the dead-time generator can be adjusted separately by DTH and DTL. The dead-time values can be updated synchronously to the PWM period by using the PWM Channel Dead Time Update Register (PWM_DTUPDx). The dead-time is based on a specific counter which uses the same selected clock that feeds the channel counter of the comparator. Depending on the edge and the configuration of the dead-time, DTOHx and DTOLx are delayed until the counter has reached the value defined by DTH or DTL. An inverted configuration bit (DTHI and DTLI bit in PWM_CMRx) is provided for each output to invert the deadtime outputs. The following figure shows the waveform of the dead-time generator.  2017 Microchip Technology Inc. DS60001525A-page 1421 SAMA5D4 SERIES Figure 47-7: Complementary Output Waveforms Output waveform OCx CPOLx = 0 Output waveform DTOHx DTHIx = 0 Output waveform DTOLx DTLIx = 0 Output waveform DTOHx DTHIx = 1 Output waveform DTOLx DTLIx = 1 DTHx DTLx DTHx DTLx Output waveform OCx CPOLx = 1 Output waveform DTOHx DTHIx = 0 Output waveform DTOLx DTLIx = 0 Output waveform DTOHx DTHIx = 1 Output waveform DTOLx DTLIx = 1 DS60001525A-page 1422  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.6.2.5 Output Override The two complementary outputs DTOHx and DTOLx of the dead-time generator can be forced to a value defined by the software. Figure 47-8: Override Output Selection DTOHx 0 OOOHx OOVHx 1 OSHx DTOLx 0 OOOLx OOVLx 1 OSLx The fields OSHx and OSLx in the PWM Output Selection Register (PWM_OS) allow the outputs of the dead-time generator DTOHx and DTOLx to be overridden by the value defined in the fields OOVHx and OOVLx in the PWM Output Override Value Register (PWM_OOV). The set registers PWM Output Selection Set Register (PWM_OSS) and PWM Output Selection Set Update Register (PWM_OSSUPD) enable the override of the outputs of a channel regardless of other channels. In the same way, the clear registers PWM Output Selection Clear Register (PWM_OSC) and PWM Output Selection Clear Update Register (PWM_OSCUPD) disable the override of the outputs of a channel regardless of other channels. By using buffer registers PWM_OSSUPD and PWM_OSCUPD, the output selection of PWM outputs is done synchronously to the channel counter, at the beginning of the next PWM period. By using registers PWM_OSS and PWM_OSC, the output selection of PWM outputs is done asynchronously to the channel counter, as soon as the register is written. The value of the current output selection can be read in PWM_OS. While overriding PWM outputs, the channel counters continue to run, only the PWM outputs are forced to user defined values. 47.6.2.6 Fault Protection 8 inputs provide fault protection which can force any of the PWM output pairs to a programmable value. This mechanism has priority over output overriding. Figure 47-9: Fault Protection 0 fault input 0 Glitch Filter FIV0 1 = 0 FMOD0 SET OUT Fault 0 Status FS0 FPEx[0] CLR FPE0[0] FFIL0 0 fault input 1 Glitch Filter Write FCLR0 at 1 FPOL0 FIV1 1 = FMOD0 0 FMOD1 SET OUT FPEx[1] Write FCLR1 at 1 FMOD1 0 PWMHx 1 1 FPVHx SYNCx from fault 1 1 FPE0[1] FPOL1 0 From Output Override OOHx High Impedance State Fault 1 Status FS1 CLR FFIL1 from fault 0 1 1 0 FPZHx 0 Fault protection on PWM channel x 1 from fault y SYNCx fault input y High Impedance State FPVLx 1 0 FPZLx 1 OOLx From Output Override 0 PWMLx  2017 Microchip Technology Inc. DS60001525A-page 1423 SAMA5D4 SERIES The polarity level of the fault inputs is configured by the FPOL field in the PWM Fault Mode Register (PWM_FMR). For fault inputs coming from internal peripherals such as ADC or Timer Counter, the polarity level must be FPOL = 1. For fault inputs coming from external GPIO pins the polarity level depends on the user's implementation. The configuration of the Fault Activation mode (FMOD field in PWMC_FMR) depends on the peripheral generating the fault. If the corresponding peripheral does not have “Fault Clear” management, then the FMOD configuration to use must be FMOD = 1, to avoid spurious fault detection. Refer to the corresponding peripheral documentation for details on handling fault generation. Fault inputs may or may not be glitch-filtered depending on the FFIL field in PWM_FMR. When the filter is activated, glitches on fault inputs with a width inferior to the PWM peripheral clock period are rejected. A fault becomes active as soon as its corresponding fault input has a transition to the programmed polarity level. If the corresponding bit FMOD is set to ‘0’ in PWM_FMR, the fault remains active as long as the fault input is at this polarity level. If the corresponding FMOD field is set to ‘1’, the fault remains active until the fault input is no longer at this polarity level and until it is cleared by writing the corresponding bit FCLR in the PWM Fault Clear Register (PWM_FCR). In the PWM Fault Status Register (PWM_FSR), the field FIV indicates the current level of the fault inputs and the field FIS indicates whether a fault is currently active. Each fault can be taken into account or not by the fault protection mechanism in each channel. To be taken into account in the channel x, the fault y must be enabled by the bit FPEx[y] in the PWM Fault Protection Enable registers (PWM_FPE1). However, synchronous channels (refer to Section 47.6.2.8 “Synchronous Channels”) do not use their own fault enable bits, but those of the channel 0 (bits FPE0[y]). The fault protection on a channel is triggered when this channel is enabled and when any one of the faults that are enabled for this channel is active. It can be triggered even if the PWM peripheral clock is not running but only by a fault input that is not glitch-filtered. When the fault protection is triggered on a channel, the fault protection mechanism resets the counter of this channel and forces the channel outputs to the values defined by the fields FPVHx and FPVLx in the PWM Fault Protection Value Register 1 (PWM_FPV) and fields FPZHx/FPZLx in the PWM Fault Protection Value Register 2, as shown in Table 47-5. The output forcing is made asynchronously to the channel counter. Table 47-5: Forcing Values of PWM Outputs by Fault Protection FPZH/Lx FPVH/Lx Forcing Value of PWMH/Lx 0 0 0 0 1 1 1 – High impedance state (Hi-Z) CAUTION: • To prevent any unexpected activation of the status flag FSy in PWM_FSR, the FMODy bit can be set to ‘1’ only if the FPOLy bit has been previously configured to its final value. • To prevent any unexpected activation of the Fault Protection on the channel x, the bit FPEx[y] can be set to ‘1’ only if the FPOLy bit has been previously configured to its final value. If a comparison unit is enabled (refer to Section 47.6.3 “PWM Comparison Units”) and if a fault is triggered in the channel 0, then the comparison cannot match. As soon as the fault protection is triggered on a channel, an interrupt (different from the interrupt generated at the end of the PWM period) can be generated but only if it is enabled and not masked. The interrupt is reset by reading the interrupt status register, even if the fault which has caused the trigger of the fault protection is kept active. 47.6.2.7 Spread Spectrum Counter The PWM macrocell includes a spread spectrum counter allowing the generation of a constantly varying duty cycle on the output PWM waveform (only for the channel 0). This feature may be useful to minimize electromagnetic interference or to reduce the acoustic noise of a PWM driven motor. This is achieved by varying the effective period in a range defined by a spread spectrum value which is programmed by the field SPRD in the PWM Spread Spectrum Register (PWM_SSPR). The effective period of the output waveform is the value of the spread spectrum counter added to the programmed waveform period CPRD in the PWM Channel Period Register (PWM_CPRD0). It will cause the effective period to vary from CPRD-SPRD to CPRD+SPRD. This leads to a constantly varying duty cycle on the PWM output waveform because the duty cycle value programmed is unchanged. The value of the spread spectrum counter can change in two ways depending on the bit SPRDM in PWM_SSPR. If SPRDM = 0, the Triangular mode is selected. The spread spectrum counter starts to count from -SPRD when the channel 0 is enabled or after reset and counts upwards at each period of the channel counter. When it reaches SPRD, it restarts to count from -SPRD again. DS60001525A-page 1424  2017 Microchip Technology Inc. SAMA5D4 SERIES If SPRDM = 1, the Random mode is selected. A new random value is assigned to the spread spectrum counter at each period of the channel counter. This random value is between -SPRD and +SPRD and is uniformly distributed. Figure 47-10: Spread Spectrum Counter Max value of the channel counter CPRD+SPRD Period Value: CPRD Variation of the effective period CPRD-SPRD Duty Cycle Value: CDTY 0x0 47.6.2.8 Synchronous Channels Some channels can be linked together as synchronous channels. They have the same source clock, the same period, the same alignment and are started together. In this way, their counters are synchronized together. The synchronous channels are defined by the SYNCx bits in the PWM Sync Channels Mode Register (PWM_SCM). Only one group of synchronous channels is allowed. When a channel is defined as a synchronous channel, the channel 0 is also automatically defined as a synchronous channel. This is because the channel 0 counter configuration is used by all the synchronous channels. If a channel x is defined as a synchronous channel, the fields/bits for the channel 0 are used instead of those of channel x: • CPRE in PWM_CMR0 instead of CPRE in PWM_CMRx (same source clock) • CPRD in PWM_CPRD0 instead of CPRD in PWM_CPRDx (same period) • CALG in PWM_CMR0 instead of CALG in PWM_CMRx (same alignment) Modifying the fields CPRE, CPRD and CALG of for channels with index greater than 0 has no effect on output waveforms. Because counters of synchronous channels must start at the same time, they are all enabled together by enabling the channel 0 (by the CHID0 bit in PWM_ENA register). In the same way, they are all disabled together by disabling channel 0 (by the CHID0 bit in PWM_DIS register). However, a synchronous channel x different from channel 0 can be enabled or disabled independently from others (by the CHIDx bit in PWM_ENA and PWM_DIS registers). Defining a channel as a synchronous channel while it is an asynchronous channel (by writing the bit SYNCx to ‘1’ while it was at ‘0’) is allowed only if the channel is disabled at this time (CHIDx = 0 in PWM_SR). In the same way, defining a channel as an asynchronous channel while it is a synchronous channel (by writing the SYNCx bit to ‘0’ while it was ‘1’) is allowed only if the channel is disabled at this time. The UPDM field (Update Mode) in the PWM_SCM register selects one of the three methods to update the registers of the synchronous channels: • Method 1 (UPDM = 0): The period value, the duty-cycle values and the dead-time values must be written by the processor in their respective update registers (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx).The update is triggered at the next PWM period as soon as the bit UPDULOCK in the PWM Sync Channels Update Control Register (PWM_SCUC) is set to ‘1’ (refer to “Method 1: Manual write of duty-cycle values and manual trigger of the update”). • Method 2 (UPDM = 1): The period value, the duty-cycle values, the dead-time values and the update period value must be written by the processor in their respective update registers (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPD). The update of the period value and of the dead-time values is triggered at the next PWM period as soon as the bit UPDULOCK in the PWM_SCUC register is set to ‘1’. The update of the duty-cycle values and the update period value is triggered automatically after an update period defined by the field UPR in the PWM Sync Channels Update Period Register (PWM_SCUP) (refer to “Method 2: Manual write of duty-cycle values and automatic trigger of the update”).  2017 Microchip Technology Inc. DS60001525A-page 1425 SAMA5D4 SERIES Table 47-6: Summary of the Update of Registers of Synchronous Channels Register UPDM = 0 UPDM = 1 Write by the processor Period Value (PWM_CPRDUPDx) Update is triggered at the next PWM period as soon as the bit UPDULOCK is set to ‘1’ Write by the processor Dead-Time Values (PWM_DTUPDx) Update is triggered at the next PWM period as soon as the bit UPDULOCK is set to ‘1’ Duty-Cycle Values (PWM_CDTYUPDx) Write by the processor Write by the processor Update is triggered at the next PWM period as soon as the bit UPDULOCK is set to ‘1’ Update is triggered at the next PWM period as soon as the update period counter has reached the value UPR Not applicable Write by the processor Not applicable Update is triggered at the next PWM period as soon as the update period counter has reached the value UPR Update Period Value (PWM_SCUPUPD) Method 1: Manual write of duty-cycle values and manual trigger of the update In this mode, the update of the period value, the duty-cycle values and the dead-time values must be done by writing in their respective update registers with the processor (respectively PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx). To trigger the update, the user must use the bit UPDULOCK in the PWM_SCUC register which allows to update synchronously (at the same PWM period) the synchronous channels: • If the bit UPDULOCK is set to ‘1’, the update is done at the next PWM period of the synchronous channels. • If the UPDULOCK bit is not set to ‘1’, the update is locked and cannot be performed. After writing the UPDULOCK bit to ‘1’, it is held at this value until the update occurs, then it is read 0. Sequence for Method 1: 1. 2. 3. 4. 5. 6. Select the manual write of duty-cycle values and the manual update by setting the UPDM field to ‘0’ in the PWM_SCM register. Define the synchronous channels by the SYNCx bits in the PWM_SCM register. Enable the synchronous channels by writing CHID0 in the PWM_ENA register. If an update of the period value and/or the duty-cycle values and/or the dead-time values is required, write registers that need to be updated (PWM_CPRDUPDx, PWM_CDTYUPDx and PWM_DTUPDx). Set UPDULOCK to ‘1’ in PWM_SCUC. The update of the registers will occur at the beginning of the next PWM period. When the UPDULOCK bit is reset, go to Step 4. for new values. Figure 47-11: Method 1 (UPDM = 0) CCNT0 CDTYUPD 0x20 0x40 0x20 0x40 0x60 UPDULOCK CDTY 0x60 Method 2: Manual write of duty-cycle values and automatic trigger of the update DS60001525A-page 1426  2017 Microchip Technology Inc. SAMA5D4 SERIES In this mode, the update of the period value, the duty-cycle values, the dead-time values and the update period value must be done by writing in their respective update registers with the processor (respectively PWM_CPRDUPDx, PWM_CDTYUPDx, PWM_DTUPDx and PWM_SCUPUPD). To trigger the update of the period value and the dead-time values, the user must use the bit UPDULOCK in the PWM_SCUC register, which updates synchronously (at the same PWM period) the synchronous channels: • If the bit UPDULOCK is set to ‘1’, the update is done at the next PWM period of the synchronous channels. • If the UPDULOCK bit is not set to ‘1’, the update is locked and cannot be performed. After writing the UPDULOCK bit to ‘1’, it is held at this value until the update occurs, then it is read 0. The update of the duty-cycle values and the update period is triggered automatically after an update period. To configure the automatic update, the user must define a value for the update period by the UPR field in the PWM_SCUP register. The PWM controller waits UPR+1 period of synchronous channels before updating automatically the duty values and the update period value. The status of the duty-cycle value write is reported in the PWM Interrupt Status Register 2 (PWM_ISR2) by the following flags: • WRDY: this flag is set to ‘1’ when the PWM Controller is ready to receive new duty-cycle values and a new update period value. It is reset to ‘0’ when the PWM_ISR2 register is read. Depending on the interrupt mask in the PWM Interrupt Mask Register 2 (PWM_IMR2), an interrupt can be generated by these flags. Sequence for Method 2: 1. 2. 3. 4. 5. Select the manual write of duty-cycle values and the automatic update by setting the field UPDM to ‘1’ in the PWM_SCM register Define the synchronous channels by the bits SYNCx in the PWM_SCM register. Define the update period by the field UPR in the PWM_SCUP register. Enable the synchronous channels by writing CHID0 in the PWM_ENA register. If an update of the period value and/or of the dead-time values is required, write registers that need to be updated (PWM_CPRDUPDx, PWM_DTUPDx), else go to Step 8. 6. Set UPDULOCK to ‘1’ in PWM_SCUC. 7. The update of these registers will occur at the beginning of the next PWM period. At this moment the bit UPDULOCK is reset, go to Step 5. for new values. 8. If an update of the duty-cycle values and/or the update period is required, check first that write of new update values is possible by polling the flag WRDY (or by waiting for the corresponding interrupt) in PWM_ISR2. 9. Write registers that need to be updated (PWM_CDTYUPDx, PWM_SCUPUPD). 10. The update of these registers will occur at the next PWM period of the synchronous channels when the Update Period is elapsed. Go to Step 8. for new values. Figure 47-12: Method 2 (UPDM = 1) CCNT0 CDTYUPD UPRUPD 0x1 UPR 0x1 UPRCNT 0x0 CDTY 0x60 0x40 0x20 0x3 0x3 0x1 0x20 0x0 0x1 0x0 0x40 0x1 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x60 WRDY  2017 Microchip Technology Inc. DS60001525A-page 1427 SAMA5D4 SERIES 47.6.2.9 Update Time for Double-Buffering Registers All channels integrate a double-buffering system in order to prevent an unexpected output waveform while modifying the period, the spread spectrum value, the polarity, the duty-cycle, the dead-times, the output override, and the synchronous channels update period. This double-buffering system comprises the following update registers: • • • • • • • • PWM Sync Channels Update Period Update Register PWM Output Selection Set Update Register PWM Output Selection Clear Update Register PWM Spread Spectrum Update Register PWM Channel Duty Cycle Update Register PWM Channel Period Update Register PWM Channel Dead Time Update Register PWM Channel Mode Update Register When one of these update registers is written to, the write is stored, but the values are updated only at the next PWM period border. In Left-aligned mode (CALG = 0), the update occurs when the channel counter reaches the period value CPRD. In Center-aligned mode, the update occurs when the channel counter value is decremented and reaches the 0 value. In Center-aligned mode, it is possible to trigger the update of the polarity and the duty-cycle at the next half period border. This mode concerns the following update registers: • PWM Channel Duty Cycle Update Register • PWM Channel Mode Update Register The update occurs at the first half period following the write of the update register (either when the channel counter value is incrementing and reaches the period value CPRD, or when the channel counter value is decrementing and reaches the 0 value). To activate this mode, the user must write a one to the bit UPDS in the PWM Channel Mode Register. 47.6.3 PWM Comparison Units The PWM provides 8 independent comparison units able to compare a programmed value with the current value of the channel 0 counter (which is the channel counter of all synchronous channels, Section 47.6.2.8 “Synchronous Channels”). These comparisons are intended to generate pulses on the event lines (used to synchronize ADC, refer to Section 47.6.4 “PWM Event Lines”), to generate software interrupts. Figure 47-13: Comparison Unit Block Diagram CEN [PWM_CMPMx] fault on channel 0 CV [PWM_CMPVx] CNT [PWM_CCNT0] Comparison x = 1 CNT [PWM_CCNT0] is decrementing = 0 1 CVM [PWM_CMPVx] CALG [PWM_CMR0] CPRCNT [PWM_CMPMx] CTR [PWM_CMPMx] DS60001525A-page 1428 =  2017 Microchip Technology Inc. SAMA5D4 SERIES The comparison x matches when it is enabled by the bit CEN in the PWM Comparison x Mode Register (PWM_CMPMx for the comparison x) and when the counter of the channel 0 reaches the comparison value defined by the field CV in PWM Comparison x Value Register (PWM_CMPVx for the comparison x). If the counter of the channel 0 is center-aligned (CALG = 1 in PWM Channel Mode Register), the bit CVM in PWM_CMPVx defines if the comparison is made when the counter is counting up or counting down (in Left-alignment mode CALG = 0, this bit is useless). If a fault is active on the channel 0, the comparison is disabled and cannot match (refer to Section 47.6.2.6 “Fault Protection”). The user can define the periodicity of the comparison x by the fields CTR and CPR in PWM_CMPMx. The comparison is performed periodically once every CPR+1 periods of the counter of the channel 0, when the value of the comparison period counter CPRCNT in PWM_CMPMx reaches the value defined by CTR. CPR is the maximum value of the comparison period counter CPRCNT. If CPR = CTR = 0, the comparison is performed at each period of the counter of the channel 0. The comparison x configuration can be modified while the channel 0 is enabled by using the PWM Comparison x Mode Update Register (PWM_CMPMUPDx registers for the comparison x). In the same way, the comparison x value can be modified while the channel 0 is enabled by using the PWM Comparison x Value Update Register (PWM_CMPVUPDx registers for the comparison x). The update of the comparison x configuration and the comparison x value is triggered periodically after the comparison x update period. It is defined by the field CUPR in PWM_CMPMx. The comparison unit has an update period counter independent from the period counter to trigger this update. When the value of the comparison update period counter CUPRCNT (in PWM_CMPMx) reaches the value defined by CUPR, the update is triggered. The comparison x update period CUPR itself can be updated while the channel 0 is enabled by using the PWM_CMPMUPDx register. CAUTION: The write of PWM_CMPVUPDx must be followed by a write of PWM_CMPMUPDx. The comparison match and the comparison update can be source of an interrupt, but only if it is enabled and not masked. These interrupts can be enabled by the PWM Interrupt Enable Register 2 and disabled by the PWM Interrupt Disable Register 2. The comparison match interrupt and the comparison update interrupt are reset by reading the PWM Interrupt Status Register 2.  2017 Microchip Technology Inc. DS60001525A-page 1429 SAMA5D4 SERIES Figure 47-14: Comparison Waveform CCNT0 CVUPD 0x6 0x6 0x2 CVMVUPD CTRUPD 0x1 0x2 CPRUPD 0x1 0x3 CUPRUPD 0x3 0x2 CV 0x6 0x2 CTR 0x1 0x2 CPR 0x1 0x3 CUPR 0x3 0x2 CUPRCNT 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x0 0x1 0x2 0x0 0x1 CPRCNT 0x0 0x1 0x0 0x1 0x0 0x1 0x2 0x3 0x0 0x1 0x2 0x3 0x6 CVM Comparison Update CMPU Comparison Match CMPM 47.6.4 PWM Event Lines The PWM provides 2 independent event lines intended to trigger actions in other peripherals (e.g., for the Analog-to-Digital Converter (ADC)). A pulse (one cycle of the peripheral clock) is generated on an event line, when at least one of the selected comparisons is matching. The comparisons can be selected or unselected independently by the CSEL bits in the PWM Event Line x Register (PWM_ELMRx for the Event Line x). An example of event generation is provided in Figure 47-16. DS60001525A-page 1430  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 47-15: Event Line Block Diagram CMPM0 (PWM_ISR2) CSEL0 (PWM_ELMRx) CMPM1 (PWM_ISR2) CSEL1 (PWM_ELMRx) CMPM2 (PWM_ISR2) CSEL2 (PWM_ELMRx) PULSE GENERATOR Event Line x CMPM7 (PWM_ISR2) CSEL7 (PWM_ELMRx) Figure 47-16: Event Line Generation Waveform (Example) PWM_CCNTx CPRD(PWM_CPRD0) CV (PWM_CMPV1) CDTY(PWM_CDTY2) CDTY(PWM_CDTY1) CDTY(PWM_CDTY0) CV (PWM_CMPV0) Waveform OC0 Waveform OC1 Waveform OC2 Comparison Unit 0 Output PWM_CMPM0.CEN = 1 Comparison Unit 1 Output PWM_CMPM0.CEN = 1 Event Line 0 (trigger event for ADC) PWM_ELMR0.CSEL0 = 1 PWM_ELMR0.CSEL1 = 1 configurable delay PWM_CMPV0.CV ADC conversion 47.6.5 47.6.5.1 configurable delay PWM_CMPV1.CV ADC conversion PWM Controller Operations Initialization Before enabling the channels, they must be configured by the software application as described below: • • • • • • • Unlock User Interface by writing the WPCMD field in PWM_WPCR. Configuration of the clock generator (DIVA, PREA, DIVB, PREB in the PWM_CLK register if required). Selection of the clock for each channel (CPRE field in PWM_CMRx) Configuration of the waveform alignment for each channel (CALG field in PWM_CMRx) Selection of the counter event selection (if CALG = 1) for each channel (CES field in PWM_CMRx) Configuration of the output waveform polarity for each channel (CPOL bit in PWM_CMRx) Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CPRDUPDx register to update PWM_CPRDx as explained below.  2017 Microchip Technology Inc. DS60001525A-page 1431 SAMA5D4 SERIES • Configuration of the duty-cycle for each channel (CDTY in the PWM_CDTYx register). Writing in PWM_CDTYx register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CDTYUPDx register to update PWM_CDTYx as explained below. • Configuration of the dead-time generator for each channel (DTH and DTL in PWM_DTx) if enabled (DTE bit in PWM_CMRx). Writing in the PWM_DTx register is possible while the channel is disabled. After validation of the channel, the user must use PWM_DTUPDx register to update PWM_DTx • Selection of the synchronous channels (SYNCx in the PWM_SCM register) • Configuration of the Update mode (UPDM in PWM_SCM register) • Configuration of the update period (UPR in PWM_SCUP register) if needed • Configuration of the comparisons (PWM_CMPVx and PWM_CMPMx) • Configuration of the event lines (PWM_ELMRx) • Configuration of the fault inputs polarity (FPOL in PWM_FMR) • Configuration of the fault protection (FMOD and FFIL in PWM_FMR, PWM_FPV and PWM_FPE1) • Enable of the interrupts (writing CHIDx and FCHIDx in PWM_IER1, and writing WRDY, UNRE, CMPMx and CMPUx in PWM_IER2) • Enable of the PWM channels (writing CHIDx in the PWM_ENA register) 47.6.5.2 Source Clock Selection Criteria The large number of source clocks can make selection difficult. The relationship between the value in the PWM Channel Period Register (PWM_CPRDx) and the PWM Channel Duty Cycle Register (PWM_CDTYx) helps the user select the appropriate clock. The event number written in the Period Register gives the PWM accuracy. The Duty-Cycle quantum cannot be lower than 1/CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy. For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value from between 1 up to 14 in PWM_CDTYx. The resulting duty-cycle quantum cannot be lower than 1/15 of the PWM period. 47.6.5.3 Changing the Duty-Cycle, the Period and the Dead-Times It is possible to modulate the output waveform duty-cycle, period and dead-times. To prevent unexpected output waveform, the user must use the PWM Channel Duty Cycle Update Register (PWM_CDTYUPDx), the PWM Channel Period Update Register (PWM_CPRDUPDx) and the PWM Channel Dead Time Update Register (PWM_DTUPDx) to change waveform parameters while the channel is still enabled. • If the channel is an asynchronous channel (SYNCx = 0 in PWM Sync Channels Mode Register (PWM_SCM)), these registers hold the new period, duty-cycle and dead-times values until the end of the current PWM period and update the values for the next period. • If the channel is a synchronous channel and update method 0 is selected (SYNCx = 1 and UPDM = 0 in PWM_SCM register), these registers hold the new period, duty-cycle and dead-times values until the bit UPDULOCK is written at ‘1’ (in PWM Sync Channels Update Control Register (PWM_SCUC)) and the end of the current PWM period, then update the values for the next period. • If the channel is a synchronous channel and update method 1 or 2 is selected (SYNCx = 1 and UPDM = 1 or 2 in PWM_SCM register): - registers PWM_CPRDUPDx and PWM_DTUPDx hold the new period and dead-times values until the bit UPDULOCK is written at ‘1’ (in PWM_SCUC) and the end of the current PWM period, then update the values for the next period. - register PWM_CDTYUPDx holds the new duty-cycle value until the end of the update period of synchronous channels (when UPRCNT is equal to UPR in PWM Sync Channels Update Period Register (PWM_SCUP)) and the end of the current PWM period, then updates the value for the next period. Note: If the update registers PWM_CDTYUPDx, PWM_CPRDUPDx and PWM_DTUPDx are written several times between two updates, only the last written value is taken into account. DS60001525A-page 1432  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 47-17: Synchronized Period, Duty-Cycle and Dead-Time Update User's Writing User's Writing User's Writing PWM_DTUPDx Value PWM_CPRDUPDx Value PWM_CDTYUPDx Value PWM_CPRDx PWM_DTx PWM_CDTYx - If Asynchronous Channel -> End of PWM period - If Synchronous Channel -> End of PWM period and UPDULOCK = 1 - If Asynchronous Channel -> End of PWM period - If Synchronous Channel - If UPDM = 0 -> End of PWM period and UPDULOCK = 1 - If UPDM = 1 or 2 -> End of PWM period and end of Update Period 47.6.5.4 Changing the Update Period of Synchronous Channels It is possible to change the update period of synchronous channels while they are enabled. Refer to “Method 2: Manual write of duty-cycle values and automatic trigger of the update” To prevent an unexpected update of the synchronous channels registers, the user must use the PWM Sync Channels Update Period Update Register (PWM_SCUPUPD) to change the update period of synchronous channels while they are still enabled. This register holds the new value until the end of the update period of synchronous channels (when UPRCNT is equal to UPR in PWM_SCUP) and the end of the current PWM period, then updates the value for the next period. Note 1: If the update register PWM_SCUPUPD is written several times between two updates, only the last written value is taken into account. 2: Changing the update period does make sense only if there is one or more synchronous channels and if the update method 1 or 2 is selected (UPDM = 1 or 2 in PWM Sync Channels Mode Register).  2017 Microchip Technology Inc. DS60001525A-page 1433 SAMA5D4 SERIES Figure 47-18: Synchronized Update of Update Period Value of Synchronous Channels User's Writing PWM_SCUPUPD Value PWM_SCUP End of PWM period and end of update period of synchronous channels 47.6.5.5 Changing the Comparison Value and the Comparison Configuration It is possible to change the comparison values and the comparison configurations while the channel 0 is enabled (refer to Section 47.6.3 “PWM Comparison Units”). To prevent unexpected comparison match, the user must use the PWM Comparison x Value Update Register (PWM_CMPVUPDx) and the PWM Comparison x Mode Update Register (PWM_CMPMUPDx) to change, respectively, the comparison values and the comparison configurations while the channel 0 is still enabled. These registers hold the new values until the end of the comparison update period (when CUPRCNT is equal to CUPR in PWM Comparison x Mode Register (PWM_CMPMx) and the end of the current PWM period, then update the values for the next period. CAUTION: The write of the register PWM_CMPVUPDx must be followed by a write of the register PWM_CMPMUPDx. Note: If the update registers PWM_CMPVUPDx and PWM_CMPMUPDx are written several times between two updates, only the last written value are taken into account. DS60001525A-page 1434  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 47-19: Synchronized Update of Comparison Values and Configurations User's Writing User's Writing PWM_CMPVUPDx Value Comparison value for comparison x PWM_CMPMUPDx Value Comparison configuration for comparison x PWM_CMPVx PWM_CMPMx End of channel0 PWM period and end of comparison update period and and PWM_CMPMx written End of channel0 PWM period and end of comparison update period 47.6.5.6 Interrupt Sources Depending on the interrupt mask in PWM_IMR1 and PWM_IMR2, an interrupt can be generated at the end of the corresponding channel period (CHIDx in the PWM Interrupt Status Register 1 (PWM_ISR1)), after a fault event (FCHIDx in PWM_ISR1), after a comparison match (CMPMx in PWM_ISR2), after a comparison update (CMPUx in PWM_ISR2) or according to the Transfer mode of the synchronous channels (WRDY and UNRE in PWM_ISR2). If the interrupt is generated by the flags CHIDx or FCHIDx, the interrupt remains active until a read operation in PWM_ISR1 occurs. If the interrupt is generated by the flags WRDY or UNRE or CMPMx or CMPUx, the interrupt remains active until a read operation in PWM_ISR2 occurs. A channel interrupt is enabled by setting the corresponding bit in PWM_IER1 and PWM_IER2. A channel interrupt is disabled by setting the corresponding bit in PWM_IDR1 and PWM_IDR2. 47.6.6 Register Write Protection To prevent any single software error that may corrupt PWM behavior, the registers listed below can be write-protected by writing the field WPCMD in the PWM Write Protection Control Register (PWM_WPCR). They are divided into six groups: • Register group 0: - PWM Clock Register • Register group 1: - PWM Disable Register • Register group 2: - PWM Sync Channels Mode Register - PWM Channel Mode Register - PWM Stepper Motor Mode Register - PWM Channel Mode Update Register • Register group 3: - PWM Spread Spectrum Register - PWM Spread Spectrum Update Register - PWM Channel Period Register - PWM Channel Period Update Register  2017 Microchip Technology Inc. DS60001525A-page 1435 SAMA5D4 SERIES • Register group 4: - PWM Channel Dead Time Register - PWM Channel Dead Time Update Register • Register group 5: - PWM Fault Mode Register - PWM Fault Protection Value Register 1 There are two types of write protection: • SW write protection—can be enabled or disabled by software • HW write protection—can be enabled by software but only disabled by a hardware reset of the PWM controller Both types of write protection can be applied independently to a particular register group by means of the WPCMD and WPRGx fields in PWM_WPCR. If at least one type of write protection is active, the register group is write-protected. The value of field WPCMD defines the action to be performed: • 0: Disables SW write protection of the register groups of which the bit WPRGx is at ‘1’ • 1: Enables SW write protection of the register groups of which the bit WPRGx is at ‘1’ • 2: Enables HW write protection of the register groups of which the bit WPRGx is at ‘1’ At any time, the user can determine whether SW or HW write protection is active in a particular register group by the fields WPSWS and WPHWS in the PWM Write Protection Status Register (PWM_WPSR). If a write access to a write-protected register is detected, the WPVS flag in PWM_WPSR is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS and WPVSRC fields are automatically cleared after reading PWM_WPSR. DS60001525A-page 1436  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7 Pulse Width Modulation Controller (PWM) User Interface Table 47-7: Register Mapping Offset Register Name Access Reset 0x00 PWM Clock Register PWM_CLK Read/Write 0x0 0x04 PWM Enable Register PWM_ENA Write-only – 0x08 PWM Disable Register PWM_DIS Write-only – 0x0C PWM Status Register PWM_SR Read-only 0x0 0x10 PWM Interrupt Enable Register 1 PWM_IER1 Write-only – 0x14 PWM Interrupt Disable Register 1 PWM_IDR1 Write-only – 0x18 PWM Interrupt Mask Register 1 PWM_IMR1 Read-only 0x0 0x1C PWM Interrupt Status Register 1 PWM_ISR1 Read-only 0x0 0x20 PWM Sync Channels Mode Register PWM_SCM Read/Write 0x0 0x24 Reserved – – – 0x28 PWM Sync Channels Update Control Register PWM_SCUC Read/Write 0x0 0x2C PWM Sync Channels Update Period Register PWM_SCUP Read/Write 0x0 0x30 PWM Sync Channels Update Period Update Register PWM_SCUPUPD Write-only – 0x34 PWM Interrupt Enable Register 2 PWM_IER2 Write-only – 0x38 PWM Interrupt Disable Register 2 PWM_IDR2 Write-only – 0x3C PWM Interrupt Mask Register 2 PWM_IMR2 Read-only 0x0 0x40 PWM Interrupt Status Register 2 PWM_ISR2 Read-only 0x0 0x44 PWM Output Override Value Register PWM_OOV Read/Write 0x0 0x48 PWM Output Selection Register PWM_OS Read/Write 0x0 0x4C PWM Output Selection Set Register PWM_OSS Write-only – 0x50 PWM Output Selection Clear Register PWM_OSC Write-only – 0x54 PWM Output Selection Set Update Register PWM_OSSUPD Write-only – 0x58 PWM Output Selection Clear Update Register PWM_OSCUPD Write-only – 0x5C PWM Fault Mode Register PWM_FMR Read/Write 0x0 0x60 PWM Fault Status Register PWM_FSR Read-only 0x0 0x64 PWM Fault Clear Register PWM_FCR Write-only – 0x68 PWM Fault Protection Value Register 1 PWM_FPV1 Read/Write 0x0 0x6C PWM Fault Protection Enable Register PWM_FPE Read/Write 0x0 0x70–0x78 Reserved – – – 0x7C PWM Event Line 0 Mode Register PWM_ELMR0 Read/Write 0x0 0x80 PWM Event Line 1 Mode Register PWM_ELMR1 Read/Write 0x0 0x84–0x9C Reserved – – – 0xA0 PWM Spread Spectrum Register PWM_SSPR Read/Write 0x0 0xA4 PWM Spread Spectrum Update Register PWM_SSPUP Write-only – 0xA8–0xAC Reserved – – –  2017 Microchip Technology Inc. DS60001525A-page 1437 SAMA5D4 SERIES Table 47-7: Register Mapping (Continued) Offset Register Name Access Reset 0xB0 PWM Stepper Motor Mode Register PWM_SMMR Read/Write 0x0 0xB4–0xBC Reserved – – – 0xC0 PWM Fault Protection Value 2 Register PWM_FPV2 Read/Write 0x003F_003F 0xC4–0xE0 Reserved – – – 0xE4 PWM Write Protection Control Register PWM_WPCR Write-only – 0xE8 PWM Write Protection Status Register PWM_WPSR Read-only 0x0 0xEC–0xFC Reserved – – – 0x130 PWM Comparison 0 Value Register PWM_CMPV0 Read/Write 0x0 0x134 PWM Comparison 0 Value Update Register PWM_CMPVUPD0 Write-only – 0x138 PWM Comparison 0 Mode Register PWM_CMPM0 Read/Write 0x0 0x13C PWM Comparison 0 Mode Update Register PWM_CMPMUPD0 Write-only – 0x140 PWM Comparison 1 Value Register PWM_CMPV1 Read/Write 0x0 0x144 PWM Comparison 1 Value Update Register PWM_CMPVUPD1 Write-only – 0x148 PWM Comparison 1 Mode Register PWM_CMPM1 Read/Write 0x0 0x14C PWM Comparison 1 Mode Update Register PWM_CMPMUPD1 Write-only – 0x150 PWM Comparison 2 Value Register PWM_CMPV2 Read/Write 0x0 0x154 PWM Comparison 2 Value Update Register PWM_CMPVUPD2 Write-only – 0x158 PWM Comparison 2 Mode Register PWM_CMPM2 Read/Write 0x0 0x15C PWM Comparison 2 Mode Update Register PWM_CMPMUPD2 Write-only – 0x160 PWM Comparison 3 Value Register PWM_CMPV3 Read/Write 0x0 0x164 PWM Comparison 3 Value Update Register PWM_CMPVUPD3 Write-only – 0x168 PWM Comparison 3 Mode Register PWM_CMPM3 Read/Write 0x0 0x16C PWM Comparison 3 Mode Update Register PWM_CMPMUPD3 Write-only – 0x170 PWM Comparison 4 Value Register PWM_CMPV4 Read/Write 0x0 0x174 PWM Comparison 4 Value Update Register PWM_CMPVUPD4 Write-only – 0x178 PWM Comparison 4 Mode Register PWM_CMPM4 Read/Write 0x0 0x17C PWM Comparison 4 Mode Update Register PWM_CMPMUPD4 Write-only – 0x180 PWM Comparison 5 Value Register PWM_CMPV5 Read/Write 0x0 0x184 PWM Comparison 5 Value Update Register PWM_CMPVUPD5 Write-only – 0x188 PWM Comparison 5 Mode Register PWM_CMPM5 Read/Write 0x0 0x18C PWM Comparison 5 Mode Update Register PWM_CMPMUPD5 Write-only – 0x190 PWM Comparison 6 Value Register PWM_CMPV6 Read/Write 0x0 0x194 PWM Comparison 6 Value Update Register PWM_CMPVUPD6 Write-only – 0x198 PWM Comparison 6 Mode Register PWM_CMPM6 Read/Write 0x0 0x19C PWM Comparison 6 Mode Update Register PWM_CMPMUPD6 Write-only – 0x1A0 PWM Comparison 7 Value Register PWM_CMPV7 Read/Write 0x0 DS60001525A-page 1438  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 47-7: Register Mapping (Continued) Offset Register Name Access Reset 0x1A4 PWM Comparison 7 Value Update Register PWM_CMPVUPD7 Write-only – 0x1A8 PWM Comparison 7 Mode Register PWM_CMPM7 Read/Write 0x0 0x1AC PWM Comparison 7 Mode Update Register PWM_CMPMUPD7 Write-only – 0x1B0–0x1FC Reserved – – – 0x200 + ch_num * 0x20 + 0x00 PWM Channel Mode Register(1) PWM_CMR Read/Write 0x0 0x200 + ch_num * 0x20 + 0x04 PWM Channel Duty Cycle Register(1) PWM_CDTY Read/Write 0x0 0x200 + ch_num * 0x20 + 0x08 PWM Channel Duty Cycle Update Register(1) PWM_CDTYUPD Write-only – 0x200 + ch_num * 0x20 + 0x0C PWM Channel Period Register(1) PWM_CPRD Read/Write 0x0 0x200 + ch_num * 0x20 + 0x10 PWM Channel Period Update Register(1) PWM_CPRDUPD Write-only – 0x200 + ch_num * 0x20 + 0x14 PWM Channel Counter Register(1) PWM_CCNT Read-only 0x0 0x200 + ch_num * 0x20 + 0x18 PWM Channel Dead Time Register(1) PWM_DT Read/Write 0x0 0x200 + ch_num * 0x20 + 0x1C PWM Channel Dead Time Update Register(1) PWM_DTUPD Write-only – 0x400 + ch_num * 0x20 + 0x00 PWM Channel Mode Update Register(1) PWM_CMUPD Write-only – Note 1: Some registers are indexed with “ch_num” index ranging from 0 to 3.  2017 Microchip Technology Inc. DS60001525A-page 1439 SAMA5D4 SERIES 47.7.1 PWM Clock Register Name:PWM_CLK Address:0xF800C000 Access:Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 PREB 19 18 17 16 11 10 9 8 1 0 DIVB 15 – 14 – 13 – 12 – 7 6 5 4 PREA 3 2 DIVA This register can only be written if bits WPSWS0 and WPHWS0 are cleared in the PWM Write Protection Status Register. DIVA: CLKA Divide Factor Value Name 0 CLKA_POFF 1 PREA 2–255 PREA_DIV Description CLKA clock is turned off CLKA clock is clock selected by PREA CLKA clock is clock selected by PREA divided by DIVA factor DIVB: CLKB Divide Factor Value Name 0 CLKB_POFF 1 PREB 2–255 PREB_DIV Description CLKB clock is turned off CLKB clock is clock selected by PREB CLKB clock is clock selected by PREB divided by DIVB factor PREA: CLKA Source Clock Selection Value Name 0 CLK 1 CLK_DIV2 Peripheral clock/2 2 CLK_DIV4 Peripheral clock/4 3 CLK_DIV8 Peripheral clock/8 4 CLK_DIV16 Peripheral clock/16 5 CLK_DIV32 Peripheral clock/32 6 CLK_DIV64 Peripheral clock/64 DS60001525A-page 1440 Description Peripheral clock  2017 Microchip Technology Inc. SAMA5D4 SERIES 7 CLK_DIV128 Peripheral clock/128 8 CLK_DIV256 Peripheral clock/256 9 CLK_DIV512 Peripheral clock/512 10 CLK_DIV1024 Peripheral clock/1024 Other – Reserved PREB: CLKB Source Clock Selection Value Name 0 CLK 1 CLK_DIV2 Peripheral clock/2 2 CLK_DIV4 Peripheral clock/4 3 CLK_DIV8 Peripheral clock/8 4 CLK_DIV16 Peripheral clock/16 5 CLK_DIV32 Peripheral clock/32 6 CLK_DIV64 Peripheral clock/64 7 CLK_DIV128 Peripheral clock/128 8 CLK_DIV256 Peripheral clock/256 9 CLK_DIV512 Peripheral clock/512 10 CLK_DIV1024 Peripheral clock/1024 Other –  2017 Microchip Technology Inc. Description Peripheral clock Reserved DS60001525A-page 1441 SAMA5D4 SERIES 47.7.2 PWM Enable Register Name:PWM_ENA Address:0xF800C004 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 CHIDx: Channel ID 0: No effect. 1: Enable PWM output for channel x. DS60001525A-page 1442  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.3 PWM Disable Register Name:PWM_DIS Address:0xF800C008 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 This register can only be written if bits WPSWS1 and WPHWS1 are cleared in the PWM Write Protection Status Register. CHIDx: Channel ID 0: No effect. 1: Disable PWM output for channel x.  2017 Microchip Technology Inc. DS60001525A-page 1443 SAMA5D4 SERIES 47.7.4 PWM Status Register Name:PWM_SR Address:0xF800C00C Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 CHIDx: Channel ID 0: PWM output for channel x is disabled. 1: PWM output for channel x is enabled. DS60001525A-page 1444  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.5 PWM Interrupt Enable Register 1 Name:PWM_IER1 Address:0xF800C010 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 CHIDx: Counter Event on Channel x Interrupt Enable FCHIDx: Fault Protection Trigger on Channel x Interrupt Enable  2017 Microchip Technology Inc. DS60001525A-page 1445 SAMA5D4 SERIES 47.7.6 PWM Interrupt Disable Register 1 Name:PWM_IDR1 Address:0xF800C014 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 CHIDx: Counter Event on Channel x Interrupt Disable FCHIDx: Fault Protection Trigger on Channel x Interrupt Disable DS60001525A-page 1446  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.7 PWM Interrupt Mask Register 1 Name:PWM_IMR1 Address:0xF800C018 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 CHIDx: Counter Event on Channel x Interrupt Mask FCHIDx: Fault Protection Trigger on Channel x Interrupt Mask  2017 Microchip Technology Inc. DS60001525A-page 1447 SAMA5D4 SERIES 47.7.8 PWM Interrupt Status Register 1 Name:PWM_ISR1 Address:0xF800C01C Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FCHID3 18 FCHID2 17 FCHID1 16 FCHID0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 CHID3 2 CHID2 1 CHID1 0 CHID0 CHIDx: Counter Event on Channel x 0: No new counter event has occurred since the last read of PWM_ISR1. 1: At least one counter event has occurred since the last read of PWM_ISR1. FCHIDx: Fault Protection Trigger on Channel x 0: No new trigger of the fault protection since the last read of PWM_ISR1. 1: At least one trigger of the fault protection since the last read of PWM_ISR1. Note: Reading PWM_ISR1 automatically clears CHIDx and FCHIDx flags. DS60001525A-page 1448  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.9 PWM Sync Channels Mode Register Name:PWM_SCM Address:0xF800C020 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 SYNC3 2 SYNC2 1 SYNC1 0 SYNC0 16 UPDM This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register. SYNCx: Synchronous Channel x 0: Channel x is not a synchronous channel. 1: Channel x is a synchronous channel. UPDM: Synchronous Channels Update Mode Value Name Description 0 MODE0 Manual write of double buffer registers and manual update of synchronous channels(1) 1 MODE1 Manual write of double buffer registers and automatic update of synchronous channels(2) Note 1: The update occurs at the beginning of the next PWM period, when the UPDULOCK bit in PWM Sync Channels Update Control Register is set. 2: The update occurs when the Update Period is elapsed.  2017 Microchip Technology Inc. DS60001525A-page 1449 SAMA5D4 SERIES 47.7.10 PWM Sync Channels Update Control Register Name:PWM_SCUC Address:0xF800C028 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 UPDULOCK UPDULOCK: Synchronous Channels Update Unlock 0: No effect 1: If the UPDM field is set to ‘0’ in PWM Sync Channels Mode Register, writing the UPDULOCK bit to ‘1’ triggers the update of the period value, the duty-cycle and the dead-time values of synchronous channels at the beginning of the next PWM period. If the field UPDM is set to ‘1’ or ‘2’, writing the UPDULOCK bit to ‘1’ triggers only the update of the period value and of the dead-time values of synchronous channels. This bit is automatically reset when the update is done. DS60001525A-page 1450  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.11 PWM Sync Channels Update Period Register Name:PWM_SCUP Address:0xF800C02C Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 UPRCNT UPR UPR: Update Period Defines the time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in PWM Sync Channels Mode Register). This time is equal to UPR+1 periods of the synchronous channels. UPRCNT: Update Period Counter Reports the value of the update period counter.  2017 Microchip Technology Inc. DS60001525A-page 1451 SAMA5D4 SERIES 47.7.12 PWM Sync Channels Update Period Update Register Name:PWM_SCUPUPD Address:0xF800C030 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 2 1 0 UPRUPD This register acts as a double buffer for the UPR value. This prevents an unexpected automatic trigger of the update of synchronous channels. UPRUPD: Update Period Update Defines the time between each update of the synchronous channels if automatic trigger of the update is activated (UPDM = 1 or UPDM = 2 in PWM Sync Channels Mode Register). This time is equal to UPR+1 periods of the synchronous channels. DS60001525A-page 1452  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.13 PWM Interrupt Enable Register 2 Name:PWM_IER2 Address:0xF800C034 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 1 0 WRDY WRDY: Write Ready for Synchronous Channels Update Interrupt Enable UNRE: Synchronous Channels Update Underrun Error Interrupt Enable CMPMx: Comparison x Match Interrupt Enable CMPUx: Comparison x Update Interrupt Enable  2017 Microchip Technology Inc. DS60001525A-page 1453 SAMA5D4 SERIES 47.7.14 PWM Interrupt Disable Register 2 Name:PWM_IDR2 Address:0xF800C038 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 1 0 WRDY WRDY: Write Ready for Synchronous Channels Update Interrupt Disable UNRE: Synchronous Channels Update Underrun Error Interrupt Disable CMPMx: Comparison x Match Interrupt Disable CMPUx: Comparison x Update Interrupt Disable DS60001525A-page 1454  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.15 PWM Interrupt Mask Register 2 Name:PWM_IMR2 Address:0xF800C03C Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 1 0 WRDY WRDY: Write Ready for Synchronous Channels Update Interrupt Mask UNRE: Synchronous Channels Update Underrun Error Interrupt Mask CMPMx: Comparison x Match Interrupt Mask CMPUx: Comparison x Update Interrupt Mask  2017 Microchip Technology Inc. DS60001525A-page 1455 SAMA5D4 SERIES 47.7.16 PWM Interrupt Status Register 2 Name:PWM_ISR2 Address:0xF800C040 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CMPU7 22 CMPU6 21 CMPU5 20 CMPU4 19 CMPU3 18 CMPU2 17 CMPU1 16 CMPU0 15 CMPM7 14 CMPM6 13 CMPM5 12 CMPM4 11 CMPM3 10 CMPM2 9 CMPM1 8 CMPM0 7 – 6 – 5 – 4 – 3 UNRE 2 1 0 WRDY WRDY: Write Ready for Synchronous Channels Update 0: New duty-cycle and dead-time values for the synchronous channels cannot be written. 1: New duty-cycle and dead-time values for the synchronous channels can be written. UNRE: Synchronous Channels Update Underrun Error 0: No Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register. 1: At least one Synchronous Channels Update Underrun has occurred since the last read of the PWM_ISR2 register. CMPMx: Comparison x Match 0: The comparison x has not matched since the last read of the PWM_ISR2 register. 1: The comparison x has matched at least one time since the last read of the PWM_ISR2 register. CMPUx: Comparison x Update 0: The comparison x has not been updated since the last read of the PWM_ISR2 register. 1: The comparison x has been updated at least one time since the last read of the PWM_ISR2 register. Note: Reading PWM_ISR2 automatically clears flags WRDY, UNRE and CMPSx. DS60001525A-page 1456  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.17 PWM Output Override Value Register Name:PWM_OOV Address:0xF800C044 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OOVL3 18 OOVL2 17 OOVL1 16 OOVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OOVH3 2 OOVH2 1 OOVH1 0 OOVH0 OOVHx: Output Override Value for PWMH output of the channel x 0: Override value is 0 for PWMH output of channel x. 1: Override value is 1 for PWMH output of channel x. OOVLx: Output Override Value for PWML output of the channel x 0: Override value is 0 for PWML output of channel x. 1: Override value is 1 for PWML output of channel x.  2017 Microchip Technology Inc. DS60001525A-page 1457 SAMA5D4 SERIES 47.7.18 PWM Output Selection Register Name:PWM_OS Address:0xF800C048 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSL3 18 OSL2 17 OSL1 16 OSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSH3 2 OSH2 1 OSH1 0 OSH0 OSHx: Output Selection for PWMH output of the channel x 0: Dead-time generator output DTOHx selected as PWMH output of channel x. 1: Output override value OOVHx selected as PWMH output of channel x. OSLx: Output Selection for PWML output of the channel x 0: Dead-time generator output DTOLx selected as PWML output of channel x. 1: Output override value OOVLx selected as PWML output of channel x. DS60001525A-page 1458  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.19 PWM Output Selection Set Register Name:PWM_OSS Address:0xF800C04C Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSSL3 18 OSSL2 17 OSSL1 16 OSSL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSSH3 2 OSSH2 1 OSSH1 0 OSSH0 OSSHx: Output Selection Set for PWMH output of the channel x 0: No effect. 1: Output override value OOVHx selected as PWMH output of channel x. OSSLx: Output Selection Set for PWML output of the channel x 0: No effect. 1: Output override value OOVLx selected as PWML output of channel x.  2017 Microchip Technology Inc. DS60001525A-page 1459 SAMA5D4 SERIES 47.7.20 PWM Output Selection Clear Register Name:PWM_OSC Address:0xF800C050 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSCL3 18 OSCL2 17 OSCL1 16 OSCL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCH3 2 OSCH2 1 OSCH1 0 OSCH0 OSCHx: Output Selection Clear for PWMH output of the channel x 0: No effect. 1: Dead-time generator output DTOHx selected as PWMH output of channel x. OSCLx: Output Selection Clear for PWML output of the channel x 0: No effect. 1: Dead-time generator output DTOLx selected as PWML output of channel x. DS60001525A-page 1460  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.21 PWM Output Selection Set Update Register Name:PWM_OSSUPD Address:0xF800C054 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSSUPL3 18 OSSUPL2 17 OSSUPL1 16 OSSUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSSUPH3 2 OSSUPH2 1 OSSUPH1 0 OSSUPH0 OSSUPHx: Output Selection Set for PWMH output of the channel x 0: No effect. 1: Output override value OOVHx selected as PWMH output of channel x at the beginning of the next channel x PWM period. OSSUPLx: Output Selection Set for PWML output of the channel x 0: No effect. 1: Output override value OOVLx selected as PWML output of channel x at the beginning of the next channel x PWM period.  2017 Microchip Technology Inc. DS60001525A-page 1461 SAMA5D4 SERIES 47.7.22 PWM Output Selection Clear Update Register Name:PWM_OSCUPD Address:0xF800C058 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 OSCUPL3 18 OSCUPL2 17 OSCUPL1 16 OSCUPL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 OSCUPH3 2 OSCUPH2 1 OSCUPH1 0 OSCUPH0 OSCUPHx: Output Selection Clear for PWMH output of the channel x 0: No effect. 1: Dead-time generator output DTOHx selected as PWMH output of channel x at the beginning of the next channel x PWM period. OSCUPLx: Output Selection Clear for PWML output of the channel x 0: No effect. 1: Dead-time generator output DTOLx selected as PWML output of channel x at the beginning of the next channel x PWM period. DS60001525A-page 1462  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.23 PWM Fault Mode Register Name:PWM_FMR Address:0xF800C05C Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 FFIL 15 14 13 12 FMOD 7 6 5 4 FPOL This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register. Refer to Section 47.5.4 “Fault Inputs” for details on fault generation. FPOL: Fault Polarity For each bit y of FPOL, where y is the fault input number: 0: The fault y becomes active when the fault input y is at 0. 1: The fault y becomes active when the fault input y is at 1. FMOD: Fault Activation Mode For each bit y of FMOD, where y is the fault input number: 0: The fault y is active until the fault condition is removed at the peripheral(1) level. 1: The fault y stays active until the fault condition is removed at the peripheral(1) level AND until it is cleared in the PWM Fault Clear Register. Note 1: The peripheral generating the fault. FFIL: Fault Filtering For each bit y of FFIL, where y is the fault input number: 0: The fault input y is not filtered. 1: The fault input y is filtered. CAUTION: To prevent an unexpected activation of the status flag FSy in the PWM Fault Status Register, the bit FMODy can be set to ‘1’ only if the FPOLy bit has been previously configured to its final value.  2017 Microchip Technology Inc. DS60001525A-page 1463 SAMA5D4 SERIES 47.7.24 PWM Fault Status Register Name:PWM_FSR Address:0xF800C060 Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 FS 7 6 5 4 FIV Refer to Section 47.5.4 “Fault Inputs” for details on fault generation. FIV: Fault Input Value For each bit y of FIV, where y is the fault input number: 0: The current sampled value of the fault input y is 0 (after filtering if enabled). 1: The current sampled value of the fault input y is 1 (after filtering if enabled). FS: Fault Status For each bit y of FS, where y is the fault input number: 0: The fault y is not currently active. 1: The fault y is currently active. DS60001525A-page 1464  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.25 PWM Fault Clear Register Name:PWM_FCR Address:0xF800C064 Access:Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 – 23 22 21 20 – 15 14 13 12 – 7 6 5 4 FCLR Refer to Section 47.5.4 “Fault Inputs” for details on fault generation. FCLR: Fault Clear For each bit y of FCLR, where y is the fault input number: 0: No effect. 1: If bit y of FMOD field is set to ‘1’ and if the fault input y is not at the level defined by the bit y of FPOL field, the fault y is cleared and becomes inactive (FMOD and FPOL fields belong to PWM Fault Mode Register), else writing this bit to ‘1’ has no effect.  2017 Microchip Technology Inc. DS60001525A-page 1465 SAMA5D4 SERIES 47.7.26 PWM Fault Protection Value Register 1 Name:PWM_FPV1 Address:0xF800C068 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FPVL3 18 FPVL2 17 FPVL1 16 FPVL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 FPVH3 2 FPVH2 1 FPVH1 0 FPVH0 This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register. Refer to Section 47.5.4 “Fault Inputs” for details on fault generation. FPVHx: Fault Protection Value for PWMH output on channel x This bit is taken into account only if the bit FPZHx is set to ‘0’ in PWM Fault Protection Value Register 2. 0: PWMH output of channel x is forced to ‘0’ when fault occurs. 1: PWMH output of channel x is forced to ‘1’ when fault occurs. FPVLx: Fault Protection Value for PWML output on channel x This bit is taken into account only if the bit FPZLx is set to ‘0’ in PWM Fault Protection Value Register 2. 0: PWML output of channel x is forced to ‘0’ when fault occurs. 1: PWML output of channel x is forced to ‘1’ when fault occurs. DS60001525A-page 1466  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.27 PWM Fault Protection Enable Register Name:PWM_FPE Address:0xF800C06C Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FPE3 23 22 21 20 FPE2 15 14 13 12 FPE1 7 6 5 4 FPE0 This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register. Only the first 8 bits (number of fault input pins) of fields FPE0, FPE1, FPE2 and FPE3 are significant. Refer to Section 47.5.4 “Fault Inputs” for details on fault generation. FPEx: Fault Protection Enable for channel x For each bit y of FPEx, where y is the fault input number: 0: Fault y is not used for the fault protection of channel x. 1: Fault y is used for the fault protection of channel x. CAUTION: To prevent an unexpected activation of the fault protection, the bit y of FPEx field can be set to ‘1’ only if the corresponding FPOL field has been previously configured to its final value in PWM Fault Mode Register.  2017 Microchip Technology Inc. DS60001525A-page 1467 SAMA5D4 SERIES 47.7.28 PWM Event Line x Register Name:PWM_ELMRx Address:0xF800C07C Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 CSEL7 6 CSEL6 5 CSEL5 4 CSEL4 3 CSEL3 2 CSEL2 1 CSEL1 0 CSEL0 CSELy: Comparison y Selection 0: A pulse is not generated on the event line x when the comparison y matches. 1: A pulse is generated on the event line x when the comparison y match. DS60001525A-page 1468  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.29 PWM Spread Spectrum Register Name:PWM_SSPR Address:0xF800C0A0 Access:Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 SPRDM 19 18 17 16 11 10 9 8 3 2 1 0 SPRD 15 14 13 12 SPRD 7 6 5 4 SPRD This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register. Only the first 16 bits (channel counter size) are significant. SPRD: Spread Spectrum Limit Value The spread spectrum limit value defines the range for the spread spectrum counter. It is introduced in order to achieve constant varying PWM period for the output waveform. SPRDM: Spread Spectrum Counter Mode 0: Triangular mode. The spread spectrum counter starts to count from -SPRD when the channel 0 is enabled and counts upwards at each PWM period. When it reaches +SPRD, it restarts to count from -SPRD again. 1: Random mode. The spread spectrum counter is loaded with a new random value at each PWM period. This random value is uniformly distributed and is between -SPRD and +SPRD.  2017 Microchip Technology Inc. DS60001525A-page 1469 SAMA5D4 SERIES 47.7.30 PWM Spread Spectrum Update Register Name:PWM_SSPUP Address:0xF800C0A4 Access:Write-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 SPRDUP 15 14 13 12 SPRDUP 7 6 5 4 SPRDUP This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register. This register acts as a double buffer for the SPRD value. This prevents an unexpected waveform when modifying the spread spectrum limit value. Only the first 16 bits (channel counter size) are significant. SPRDUP: Spread Spectrum Limit Value Update The spread spectrum limit value defines the range for the spread spectrum counter. It is introduced in order to achieve constant varying period for the output waveform. DS60001525A-page 1470  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.31 PWM Stepper Motor Mode Register Name:PWM_SMMR Address:0xF800C0B0 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 DOWN1 16 DOWN0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 GCEN1 0 GCEN0 GCENx: Gray Count Enable 0: Disable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1] 1: Enable gray count generation on PWML[2*x], PWMH[2*x], PWML[2*x +1], PWMH[2*x +1]. DOWNx: Down Count 0: Up counter. 1: Down counter.  2017 Microchip Technology Inc. DS60001525A-page 1471 SAMA5D4 SERIES 47.7.32 PWM Fault Protection Value Register 2 Name:PWM_FPV2 Address:0xF800C0C0 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 FPZL3 18 FPZL2 17 FPZL1 16 FPZL0 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 FPZH3 2 FPZH2 1 FPZH1 0 FPZH0 This register can only be written if bits WPSWS5 and WPHWS5 are cleared in the PWM Write Protection Status Register. FPZHx: Fault Protection to Hi-Z for PWMH output on channel x 0: When fault occurs, PWMH output of channel x is forced to value defined by the bit FPVHx in PWM Fault Protection Value Register 1. 1: When fault occurs, PWMH output of channel x is forced to high-impedance state. FPZLx: Fault Protection to Hi-Z for PWML output on channel x 0: When fault occurs, PWML output of channel x is forced to value defined by the bit FPVLx in PWM Fault Protection Value Register 1. 1: When fault occurs, PWML output of channel x is forced to high-impedance state. DS60001525A-page 1472  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.33 PWM Write Protection Control Register Name:PWM_WPCR Address:0xF800C0E4 Access:Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 WPRG1 2 WPRG0 1 WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 WPRG5 6 WPRG4 5 WPRG3 4 WPRG2 0 WPCMD Refer to Section 47.6.6 “Register Write Protection” for the list of registers that can be write-protected. WPCMD: Write Protection Command This command is performed only if the WPKEY corresponds to 0x50574D (“PWM” in ASCII). Value Name 0 DISABLE_SW_PROT Disables the software write protection of the register groups of which the bit WPRGx is at ‘1’. 1 ENABLE_SW_PROT Enables the software write protection of the register groups of which the bit WPRGx is at ‘1’. ENABLE_HW_PROT Enables the hardware write protection of the register groups of which the bit WPRGx is at ‘1’. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. 2 Description WPRGx: Write Protection Register Group x 0: The WPCMD command has no effect on the register group x. 1: The WPCMD command is applied to the register group x. WPKEY: Write Protection Key Value Name 0x50574D PASSWD Description Writing any other value in this field aborts the write operation of the WPCMD field. Always reads as 0  2017 Microchip Technology Inc. DS60001525A-page 1473 SAMA5D4 SERIES 47.7.34 PWM Write Protection Status Register Name:PWM_WPSR Address:0xF800C0E8 Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 WPVSRC 23 22 21 20 WPVSRC 15 – 14 – 13 WPHWS5 12 WPHWS4 11 WPHWS3 10 WPHWS2 9 WPHWS1 8 WPHWS0 7 WPVS 6 – 5 WPSWS5 4 WPSWS4 3 WPSWS3 2 WPSWS2 1 WPSWS1 0 WPSWS0 WPSWSx: Write Protect SW Status 0: The SW write protection x of the register group x is disabled. 1: The SW write protection x of the register group x is enabled. WPHWSx: Write Protect HW Status 0: The HW write protection x of the register group x is disabled. 1: The HW write protection x of the register group x is enabled. WPVS: Write Protect Violation Status 0: No write protection violation has occurred since the last read of PWM_WPSR. 1: At least one write protection violation has occurred since the last read of PWM_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. WPVSRC: Write Protect Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. DS60001525A-page 1474  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.35 PWM Comparison x Value Register Name:PWM_CMPVx Address:0xF800C130 [0], 0xF800C140 [1], 0xF800C150 [2], 0xF800C160 [3], 0xF800C170 [4], 0xF800C180 [5], 0xF800C190 [6], 0xF800C1A0 [7] Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 CVM 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CV 15 14 13 12 CV 7 6 5 4 CV Only the first 16 bits (channel counter size) of field CV are significant. CV: Comparison x Value Define the comparison x value to be compared with the counter of the channel 0. CVM: Comparison x Value Mode 0: The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing. 1: The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing. Note: This bit is not relevant if the counter of the channel 0 is left-aligned (CALG = 0 in PWM Channel Mode Register)  2017 Microchip Technology Inc. DS60001525A-page 1475 SAMA5D4 SERIES 47.7.36 PWM Comparison x Value Update Register Name:PWM_CMPVUPDx Address:0xF800C134 [0], 0xF800C144 [1], 0xF800C154 [2], 0xF800C164 [3], 0xF800C174 [4], 0xF800C184 [5], 0xF800C194 [6], 0xF800C1A4 [7] Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 CVMUPD 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 CVUPD 15 14 13 12 CVUPD 7 6 5 4 CVUPD This register acts as a double buffer for the CV and CVM values. This prevents an unexpected comparison x match. Only the first 16 bits (channel counter size) of field CVUPD are significant. CVUPD: Comparison x Value Update Define the comparison x value to be compared with the counter of the channel 0. CVMUPD: Comparison x Value Mode Update 0: The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is incrementing. 1: The comparison x between the counter of the channel 0 and the comparison x value is performed when this counter is decrementing. Note: This bit is not relevant if the counter of the channel 0 is left-aligned (CALG = 0 in PWM Channel Mode Register) CAUTION: The write of the register PWM_CMPVUPDx must be followed by a write of the register PWM_CMPMUPDx. DS60001525A-page 1476  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.37 PWM Comparison x Mode Register Name:PWM_CMPMx Address:0xF800C138 [0], 0xF800C148 [1], 0xF800C158 [2], 0xF800C168 [3], 0xF800C178 [4], 0xF800C188 [5], 0xF800C198 [6], 0xF800C1A8 [7] Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 9 8 1 – 0 CEN CUPRCNT 15 14 CUPR 13 12 11 10 CPRCNT 7 6 CPR 5 4 CTR 3 – 2 – CEN: Comparison x Enable 0: The comparison x is disabled and can not match. 1: The comparison x is enabled and can match. CTR: Comparison x Trigger The comparison x is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined by CTR. CPR: Comparison x Period CPR defines the maximum value of the comparison x period counter (CPRCNT). The comparison x value is performed periodically once every CPR+1 periods of the channel 0 counter. CPRCNT: Comparison x Period Counter Reports the value of the comparison x period counter. Note: The field CPRCNT is read-only CUPR: Comparison x Update Period Defines the time between each update of the comparison x mode and the comparison x value. This time is equal to CUPR+1 periods of the channel 0 counter. CUPRCNT: Comparison x Update Period Counter Reports the value of the comparison x update period counter. Note: The field CUPRCNT is read-only  2017 Microchip Technology Inc. DS60001525A-page 1477 SAMA5D4 SERIES 47.7.38 PWM Comparison x Mode Update Register Name:PWM_CMPMUPDx Address:0xF800C13C [0], 0xF800C14C [1], 0xF800C15C [2], 0xF800C16C [3], 0xF800C17C [4], 0xF800C18C [5], 0xF800C19C [6], 0xF800C1AC [7] Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 18 17 16 15 – 14 – 13 – 12 – 11 9 8 7 6 5 4 3 – 1 – 0 CENUPD CTRUPD CUPRUPD 10 CPRUPD 2 – This register acts as a double buffer for the CEN, CTR, CPR and CUPR values. This prevents an unexpected comparison x match. CENUPD: Comparison x Enable Update 0: The comparison x is disabled and can not match. 1: The comparison x is enabled and can match. CTRUPD: Comparison x Trigger Update The comparison x is performed when the value of the comparison x period counter (CPRCNT) reaches the value defined by CTR. CPRUPD: Comparison x Period Update CPR defines the maximum value of the comparison x period counter (CPRCNT). The comparison x value is performed periodically once every CPR+1 periods of the channel 0 counter. CUPRUPD: Comparison x Update Period Update Defines the time between each update of the comparison x mode and the comparison x value. This time is equal to CUPR+1 periods of the channel 0 counter. DS60001525A-page 1478  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.39 PWM Channel Mode Register Name:PWM_CMRx [x=0..3] Address:0xF800C200 [0], 0xF800C220 [1], 0xF800C240 [2], 0xF800C260 [3] Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 DTLI 17 DTHI 16 DTE 15 – 14 – 13 – 12 – 11 UPDS 10 CES 9 CPOL 8 CALG 7 – 6 – 5 – 4 – 3 2 1 0 CPRE This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register. CPRE: Channel Prescaler Value Name Description 0 MCK Peripheral clock 1 MCK_DIV_2 Peripheral clock/2 2 MCK_DIV_4 Peripheral clock/4 3 MCK_DIV_8 Peripheral clock/8 4 MCK_DIV_16 Peripheral clock/16 5 MCK_DIV_32 Peripheral clock/32 6 MCK_DIV_64 Peripheral clock/64 7 MCK_DIV_128 Peripheral clock/128 8 MCK_DIV_256 Peripheral clock/256 9 MCK_DIV_512 Peripheral clock/512 10 MCK_DIV_1024 Peripheral clock/1024 11 CLKA Clock A 12 CLKB Clock B CALG: Channel Alignment 0: The period is left-aligned. 1: The period is center-aligned. CPOL: Channel Polarity 0: The OCx output waveform (output from the comparator) starts at a low level. 1: The OCx output waveform (output from the comparator) starts at a high level.  2017 Microchip Technology Inc. DS60001525A-page 1479 SAMA5D4 SERIES CES: Counter Event Selection The bit CES defines when the channel counter event occurs when the period is center-aligned (flag CHIDx in PWM Interrupt Status Register 1). CALG = 0 (Left Alignment): 0/1: The channel counter event occurs at the end of the PWM period. CALG = 1 (Center Alignment): 0: The channel counter event occurs at the end of the PWM period. 1: The channel counter event occurs at the end of the PWM period and at half the PWM period. UPDS: Update Selection When the period is center aligned, the bit UPDS defines when the update of the duty cycle, the polarity value/mode occurs after writing the corresponding update registers. CALG = 0 (Left Alignment): 0/1: The update always occurs at the end of the PWM period after writing the update register(s). CALG = 1 (Center Alignment): 0: The update occurs at the next end of the PWM period after writing the update register(s). 1: The update occurs at the next end of the PWM half period after writing the update register(s). DTE: Dead-Time Generator Enable 0: The dead-time generator is disabled. 1: The dead-time generator is enabled. DTHI: Dead-Time PWMHx Output Inverted 0: The dead-time PWMHx output is not inverted. 1: The dead-time PWMHx output is inverted. DTLI: Dead-Time PWMLx Output Inverted 0: The dead-time PWMLx output is not inverted. 1: The dead-time PWMLx output is inverted. DS60001525A-page 1480  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.40 PWM Channel Duty Cycle Register Name:PWM_CDTYx [x=0..3] Address:0xF800C204 [0], 0xF800C224 [1], 0xF800C244 [2], 0xF800C264 [3] Access:Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CDTY 15 14 13 12 CDTY 7 6 5 4 CDTY Only the first 16 bits (channel counter size) are significant. CDTY: Channel Duty-Cycle Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRDx).  2017 Microchip Technology Inc. DS60001525A-page 1481 SAMA5D4 SERIES 47.7.41 PWM Channel Duty Cycle Update Register Name:PWM_CDTYUPDx [x=0..3] Address:0xF800C208 [0], 0xF800C228 [1], 0xF800C248 [2], 0xF800C268 [3] Access:Write-only. 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CDTYUPD 15 14 13 12 CDTYUPD 7 6 5 4 CDTYUPD This register acts as a double buffer for the CDTY value. This prevents an unexpected waveform when modifying the waveform duty-cycle. Only the first 16 bits (channel counter size) are significant. CDTYUPD: Channel Duty-Cycle Update Defines the waveform duty-cycle. This value must be defined between 0 and CPRD (PWM_CPRDx). DS60001525A-page 1482  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.42 PWM Channel Period Register Name:PWM_CPRDx [x=0..3] Address:0xF800C20C [0], 0xF800C22C [1], 0xF800C24C [2], 0xF800C26C [3] Access:Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CPRD 15 14 13 12 CPRD 7 6 5 4 CPRD This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register. Only the first 16 bits (channel counter size) are significant. CPRD: Channel Period If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be calculated: – By using the PWM peripheral clock divided by a given prescaler value “X” (where X = 2PREA is 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula is: ( X × CPRD )------------------------------f peripheral clock – By using the PWM peripheral clock divided by a given prescaler value “X” (see above) and by either the DIVA or the DIVB divider. The formula becomes, respectively: (--------------------------------------------------X × CRPD × DIVA )( X × C RPD × DIVB ) or ---------------------------------------------------f peripheral clock f peripheral clock If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can be calculated: – By using the PWM peripheral clock divided by a given prescaler value “X” (where X = 2PREA is 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula is: (---------------------------------------2 × X × CPRD ) f peripheral clock – By using the PWM peripheral clock divided by a given prescaler value “X” (see above) and by either the DIVA or the DIVB divider. The formula becomes, respectively: (------------------------------------------------------------2 × X × C PRD × DIVA ) ( 2 × X × C PRD × DIVB ) or ------------------------------------------------------------f peripheral clock f peripheral clock  2017 Microchip Technology Inc. DS60001525A-page 1483 SAMA5D4 SERIES 47.7.43 PWM Channel Period Update Register Name:PWM_CPRDUPDx [x=0..3] Address:0xF800C210 [0], 0xF800C230 [1], 0xF800C250 [2], 0xF800C270 [3] Access:Write-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CPRDUPD 15 14 13 12 CPRDUPD 7 6 5 4 CPRDUPD This register can only be written if bits WPSWS3 and WPHWS3 are cleared in the PWM Write Protection Status Register. This register acts as a double buffer for the CPRD value. This prevents an unexpected waveform when modifying the waveform period. Only the first 16 bits (channel counter size) are significant. CPRDUPD: Channel Period Update If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be calculated: – By using the PWM peripheral clock divided by a given prescaler value “X” (where X = 2PREA is 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula is: (-------------------------------------------X × CPRDUPD ) f peripheral clock – By using the PWM peripheral clock divided by a given prescaler value “X” (see above) and by either the DIVA or the DIVB divider. The formula becomes, respectively: (----------------------------------------------------------------X × CRPDUPD × DIVA )( X × CRPDUPD × DIVB ) or -----------------------------------------------------------------f peripheral clock f peripheral clock If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can be calculated: – By using the PWM peripheral clock divided by a given prescaler value “X” (where X = 2PREA is 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula is: ( 2 × X × CPRDUPD )----------------------------------------------------f peripheral clock – By using the PWM peripheral clock divided by a given prescaler value “X” (see above) and by either the DIVA or the DIVB divider. The formula becomes, respectively: (-------------------------------------------------------------------------2 × X × C PRDUPD × DIVA -) ( 2 × X × C PRDUPD × DIVB ) or --------------------------------------------------------------------------f peripheral clock f peripheral clock DS60001525A-page 1484  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.44 PWM Channel Counter Register Name:PWM_CCNTx [x=0..3] Address:0xF800C214 [0], 0xF800C234 [1], 0xF800C254 [2], 0xF800C274 [3] Access:Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 CNT 15 14 13 12 CNT 7 6 5 4 CNT Only the first 16 bits (channel counter size) are significant. CNT: Channel Counter Register Channel counter value. This register is reset when: • the channel is enabled (writing CHIDx in the PWM_ENA register). • the channel counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left-aligned.  2017 Microchip Technology Inc. DS60001525A-page 1485 SAMA5D4 SERIES 47.7.45 PWM Channel Dead Time Register Name:PWM_DTx [x=0..3] Address:0xF800C218 [0], 0xF800C238 [1], 0xF800C258 [2], 0xF800C278 [3] Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTL 23 22 21 20 DTL 15 14 13 12 DTH 7 6 5 4 DTH This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the PWM Write Protection Status Register. Only the first 12 bits (dead-time counter size) of fields DTH and DTL are significant. DTH: Dead-Time Value for PWMHx Output Defines the dead-time value for PWMHx output. This value must be defined between 0 and the value (CPRD – CDTY) (PWM_CPRDx and PWM_CDTYx). DTL: Dead-Time Value for PWMLx Output Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx). DS60001525A-page 1486  2017 Microchip Technology Inc. SAMA5D4 SERIES 47.7.46 PWM Channel Dead Time Update Register Name:PWM_DTUPDx [x=0..3] Address:0xF800C21C [0], 0xF800C23C [1], 0xF800C25C [2], 0xF800C27C [3] Access:Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DTLUPD 23 22 21 20 DTLUPD 15 14 13 12 DTHUPD 7 6 5 4 DTHUPD This register can only be written if bits WPSWS4 and WPHWS4 are cleared in the PWM Write Protection Status Register. This register acts as a double buffer for the DTH and DTL values. This prevents an unexpected waveform when modifying the dead-time values. Only the first 12 bits (dead-time counter size) of fields DTHUPD and DTLUPD are significant. DTHUPD: Dead-Time Value Update for PWMHx Output Defines the dead-time value for PWMHx output. This value must be defined between 0 and the value (CPRD – CDTY) (PWM_CPRDx and PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period. DTLUPD: Dead-Time Value Update for PWMLx Output Defines the dead-time value for PWMLx output. This value must be defined between 0 and CDTY (PWM_CDTYx). This value is applied only at the beginning of the next channel x PWM period.  2017 Microchip Technology Inc. DS60001525A-page 1487 SAMA5D4 SERIES 47.7.47 PWM Channel Mode Update Register Name:PWM_CMUPDx [x=0..3] Address:0xF800C400 [0], 0xF800C420 [1], 0xF800C440 [2], 0xF800C460 [3] Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 CPOLINVUP 12 – 11 – 10 – 9 CPOLUP 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – This register can only be written if bits WPSWS2 and WPHWS2 are cleared in the PWM Write Protection Status Register. This register acts as a double buffer for the CPOL value. This prevents an unexpected waveform when modifying the polarity value. CPOLUP: Channel Polarity Update The write of this bit is taken into account only if the bit CPOLINVUP is written at ‘0’ at the same time. 0: The OCx output waveform (output from the comparator) starts at a low level. 1: The OCx output waveform (output from the comparator) starts at a high level. CPOLINVUP: Channel Polarity Inversion Update If this bit is written at ‘1’, the write of the bit CPOLUP is not taken into account. 0: No effect. 1: The OCx output waveform (output from the comparator) is inverted. DS60001525A-page 1488  2017 Microchip Technology Inc. SAMA5D4 SERIES 48. Analog-to-Digital Converter (ADC) 48.1 Description The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller providing enhanced resolution up to 12 bits. Refer to Figure 48-1 “Analog-to-Digital Converter Block Diagram with Touchscreen Mode”. It also integrates a 5-to-1 analog multiplexer, making possible the analog-to-digital conversions of 5 analog lines.The conversions extend from 0V to the voltage carried on pin ADVREF. The ADC digital controller embeds circuitry to reduce the resolution down to 8 bits. The 8-bit resolution mode prevents using 16-bit Peripheral DMA transfer into memory when only 8-bit resolution is required by the application. Note that using this low resolution mode does not increase the conversion rate. Conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. The 11-bit and 12-bit resolution modes are obtained by averaging multiple samples to decrease quantization noise. For the 11-bit mode, 4 samples are used, which gives a real sample rate of 1/4 of the actual sample frequency. For the 12-bit mode, 16 samples are used, giving a real sample rate of 1/16 of the actual sample frequency. This arrangement allows conversion speed to be traded for better accuracy. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are configurable. The comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a given range or outside the range, thresholds and ranges being fully configurable. The ADC Controller internal fault output is directly connected to PWM fault input. This input can be asserted by means of comparison circuitry in order to immediately put the PWM output in a safe state (pure combinational path). The ADC also integrates a Sleep mode and a conversion sequencer and connects with a DMA channel. These features reduce both power consumption and processor intervention. This ADC Controller includes a Resistive Touchscreen Controller. It supports 4-wire and 5-wire technologies. 48.2 • • • • • • • • • • • • • • • Embedded Characteristics 10-bit Resolution with Enhanced Mode up to 12 bits 320 ksps Conversion Rate Digital Averaging Function providing Enhanced Resolution Mode up to 12 bits Wide Range of Power Supply Operation Resistive 4-wire and 5-wire Touchscreen Controller - Position and Pressure Measurement for 4-wire Screens - Position Measurement for 5-wire Screens - Average of Up to 8 Measures for Noise Filtering Programmable Pen Detection Sensitivity Integrated Multiplexer Offering Up to 5 Independent Analog Inputs Individual Enable and Disable of Each Channel Hardware or Software Trigger from: - External Trigger Pin - Timer Counter Outputs (Corresponding TIOA Trigger) - Internal Trigger Counter - Trigger on Pen Contact Detection - PWM Event Line Drive of PWM Fault Input DMA Support Two Sleep Modes (Automatic Wakeup on Trigger) - Lowest Power Consumption (Voltage Reference OFF Between Conversions) - Fast Wakeup Time Response on Trigger Event (Voltage Reference ON Between Conversions) Channel Sequence Customizing Automatic Window Comparison of Converted Values Register Write Protection  2017 Microchip Technology Inc. DS60001525A-page 1489 SAMA5D4 SERIES 48.3 Block Diagram Figure 48-1: Analog-to-Digital Converter Block Diagram with Touchscreen Mode ADC Controller Periodic Trigger Trigger Selection ADTRG ADC Interrupt Control Logic Interrupt Controller ADC cell VDDANA ADCCLK ADVREF System Bus Touchscreen Analog Inputs AD0/XP/UL 0 AD1/XM/UR 1 Touchscreen Switches AD2/YP/LL AD3/YM/Sense 2 Peripheral Bridge 3 AD4/LR 4 PIO AD- Other Analog Inputs DMA Successive Approximation Register Analog-to-Digital Converter User Interface Bus Clock APB AD- PMC Peripheral Clock CHx AD- GND 48.4 Signal Description Table 48-1: ADC Pin Description Pin Name Description VDDANA Analog Power Supply ADVREF Reference Voltage AD0–AD4 Analog input Channels ADTRG External Trigger DS60001525A-page 1490  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.5 Product Dependencies 48.5.1 Power Management The ADC Controller is not continuously clocked. The programmer must first enable the ADC Controller peripheral clock in the Power Management Controller (PMC) before using the ADC Controller. However, if the application does not require ADC operations, the ADC Controller clock can be stopped when not needed and restarted when necessary. Configuring the ADC Controller does not require the ADC Controller clock to be enabled. 48.5.2 Interrupt Sources The ADC interrupt line is connected on one of the internal sources of the Interrupt Controller. Using the ADC interrupt requires the interrupt controller to be programmed first. Table 48-2: Peripheral IDs Instance ID ADC 44 48.5.3 I/O Lines The digital input ADTRG is multiplexed with digital functions on the I/O line and the selection of ADTRG is made using the PIO controller. The analog inputs ADC_ADx are multiplexed with digital functions on the I/O lines. ADC_ADx inputs are selected as inputs of the ADCC when writing a one in the corresponding CHx bit of ADC_CHER and the digital functions are not selected. Table 48-3: I/O Lines Instance Signal I/O Line Peripheral ADC ADTRG PE31 A ADC AD0 PC27 X1 ADC AD1 PC28 X1 ADC AD2 PC29 X1 ADC AD3 PC30 X1 ADC AD4 PC31 X1 48.5.4 Hardware Triggers The ADC can use internal signals to start conversions. Refer to “TRGSEL: Trigger Selection” for the exact wiring of internal triggers. 48.5.5 Fault Output The ADC Controller has the FAULT output connected to the FAULT input of PWM. Refer to Section 48.6.13 “Fault Output” and to Section PWM. 48.6 48.6.1 Functional Description Analog-to-Digital Conversion Once the programmed startup time (ADC_MR.STARTUP) has elapsed, ADC conversions are sequenced by three operating times: • Tracking time—the time for the ADC to charge its input sampling capacitor to the input voltage. The tracking time is always performed before the conversion time and can be configured using the TRACKTIM field in the Mode Register (ADC_MR). • ADC inherent conversion time—the time for the ADC to convert the sampled analog voltage. This time is constant and is defined from start of conversion to end of conversion. • Channel conversion period—the effective time between the end of the current channel conversion and the end of the next channel conversion.  2017 Microchip Technology Inc. DS60001525A-page 1491 SAMA5D4 SERIES Figure 48-2: Sequence of Consecutive ADC Conversions ADCCLK Trigger event (Hard or Soft) Analog cell IOs ADC_ON ADC_Start ADC_eoc ADC_SEL CH0 LCDR CH1 CH2 CH0 CH1 DRDY Conversion of CH0 Start Up Time (and tracking of CH0) 48.6.2 Tracking of CH1 Conversion of CH1 Tracking of CH2 ADC Clock The ADC uses the ADC clock (ADCCLK) to perform conversions. The ADC clock frequency is selected in the PRESCAL field of ADC_MR. The ADC clock frequency is between fperipheral clock/2, if PRESCAL is 0, and fperipheral clock/512, if PRESCAL is set to 255 (0xFF). PRESCAL must be programmed to provide the ADC clock frequency parameter given in the section “Electrical Characteristics”. 48.6.3 ADC Reference Voltage The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages convert to values based on a linear conversion. 48.6.4 Conversion Resolution The ADC analog cell features a 10-bit resolution. The ADC digital controller provides enhanced resolution up to 12 bits. The ADC digital controller embeds circuitry to reduce the resolution down to 8 bits. The 8-bit selection is performed by setting the LOWRES bit in ADC_MR. By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By setting the LOWRES bit, the ADC switches to the lowest resolution and the conversion results can be read in the lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding Channel Data Register (ADC_CDR) and of the LDATA field in the Last Converted Data Register (ADC_LCDR) read 0. If ADTRG is asynchronous to the ADC peripheral clock, the internal resynchronization introduces a jitter of 1 peripheral clock. This jitter may reduce the resolution of the converted signal. 48.6.5 Conversion Results When a conversion is completed, the resulting digital value is stored in the Channel Data Register (ADC_CDRx) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). By setting the TAG option in the Extended Mode Register (ADC_EMR), ADC_LCDR presents the channel number associated with the last converted data in the CHNB field. When a conversion is completed, the channel EOC bit and the DRDY bit in the Interrupt Status Register (ADC_ISR) are set. In the case of a connected DMA channel, DRDY rising triggers a data request. In any case, either EOC and DRDY can trigger an interrupt. Reading one of the ADC_CDRx clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit. DS60001525A-page 1492  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 48-3: EOCx and DRDY Flag Behavior Write the ADC_CR with START = 1 Read the ADC_CDRx Write the ADC_CR with START = 1 Read the ADC_LCDR CHx (ADC_CHSR) EOCx (ADC_ISR) DRDY (ADC_ISR) If ADC_CDR is not read before further incoming data is converted, the corresponding OVREx flag is set in the Overrun Status Register (ADC_OVER). New data converted when DRDY is high sets the GOVRE bit in ADC_ISR. The OVREx flag is automatically cleared when ADC_OVER is read, and the GOVRE flag is automatically cleared when ADC_ISR is read.  2017 Microchip Technology Inc. DS60001525A-page 1493 SAMA5D4 SERIES Figure 48-4: EOCx, OVREx and GOVREx Flag Behavior Trigger event CH0 (ADC_CHSR) CH1 (ADC_CHSR) ADC_LCDR Undefined Data ADC_CDR0 Undefined Data ADC_CDR1 EOC0 (ADC_ISR) EOC1 (ADC_ISR) GOVRE (ADC_ISR) Data B Data A Data C Data A Undefined Data Data C Data B Conversion A Read ADC_CDR0 Conversion C Conversion B Read ADC_CDR1 Read ADC_ISR DRDY (ADC_ISR) Read ADC_OVER OVRE0 (ADC_OVER) OVRE1 (ADC_OVER) Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and corresponding EOCx and GOVRE flags in ADC_ISR and OVREx flags in ADC_OVER are unpredictable. 48.6.6 Conversion Triggers Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the START bit at 1. The list of external/internal events is provided in Section 48.7.2 “ADC Mode Register”. The hardware trigger is selected using the TRGSEL field in ADC_MR. The selected hardware trigger is enabled if TRGMOD = 1, 2 or 3 in the ADC Trigger Register (ADC_TRGR). The TRGMOD field in the ADC Trigger Register (ADC_TRGR) selects the hardware trigger from the following: • • • • any edge, either rising or falling or both, detected on the external trigger pin ADTRG the Pen Detect, depending on how the PENDET bit is set in the ADC Touchscreen Mode Register (ADC_TSMR) a continuous trigger, meaning the ADC Controller restarts the next sequence as soon as it finishes the current one a periodic trigger, which is defined by programming the TRGPER field in ADC_TRGR The minimum time between two consecutive trigger events must be strictly greater than the duration time of the longest conversion sequence according to configuration of registers ADC_MR, ADC_CHSR, ADC_SEQRx, ADC_TSMR. If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of the selected signal. Due to asynchronous handling, the delay may vary in a range of two peripheral clock periods to one ADC clock period. This delay introduces sampling jitter in the A/D conversion process and may therefore degrade the conversion performance (e.g., SNR, THD). DS60001525A-page 1494  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 48-5: Hardware Trigger Delay trigger start delay If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform mode. Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) registers enable the analog channels to be enabled or disabled independently. If the ADC is used with a DMA, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. 48.6.7 Sleep Mode and Conversion Sequencer The ADC Sleep mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep mode is selected by setting the SLEEP bit in ADC_MR. Sleep mode is managed by a conversion sequencer, which automatically processes the conversions of all channels at lowest power consumption. This mode can be used when the minimum period of time between two successive trigger events is greater than the startup period of the ADC. See section “Electrical Characteristics”. When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a startup time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are ignored. The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using the internal timer (ADC_TRGR) or the PWM event line. The periodic acquisition of several samples can be processed automatically without any intervention of the processor via the DMA. The sequence can be customized by programming the Sequence Channel Register ADC_SEQR1 and setting the USEQ bit of the Mode Register (ADC_MR). The user can choose a specific order of channels and can program up to 5 conversions by sequence. The user is free to create a personal sequence by writing channel numbers in ADC_SEQR1. Not only can channel numbers be written in any sequence, channel numbers can be repeated several times. When the bit USEQ in ADC_MR is set, the fields USCHx in ADC_SEQR1 are used to define the sequence. Only enabled USCHx fields will be part of the sequence. Each USCHx field has a corresponding enable, CHx-1, in ADC_CHER. If all ADC channels (i.e., 5) are used on an application board, there is no restriction of usage of the user sequence. However, if some ADC channels are not enabled for conversion but rather used as pure digital inputs, the respective indexes of these channels cannot be used in the user sequence fields (refer to ADC_SEQRx). For example, if channel 4 is disabled (ADC_CSR[4] = 0), ADC_SEQRx fields USCH1 up to USCH5 must not contain the value 4. Thus the length of the user sequence may be limited by this behavior. As an example, if only four channels over 5 (CH0 up to CH3) are selected for ADC conversions, the user sequence length cannot exceed four channels. Each trigger event may launch up to four successive conversions of any combination of channels 0 up to 3 but no more (i.e., in this case the sequence CH0, CH0, CH1, CH1, CH1 is impossible). A sequence that repeats the same channel several times requires more enabled channels than channels actually used for conversion. For example, the sequence CH0, CH0, CH1, CH1 requires four enabled channels (four free channels on application boards) whereas only CH0, CH1 are really converted. Note: 48.6.8 The reference voltage pins always remain connected in Normal mode as in Sleep mode. Comparison Window The ADC Controller features automatic comparison functions. It compares converted values to a low threshold, a high threshold or both, depending on the value of the CMPMODE bit in ADC_EMR. The comparison can be done on all channels or only on the channel specified in the CMPSEL field of ADC_EMR. To compare all channels, the CMPALL bit of ADC_EMR must be set. Moreover, a filtering option can be set by writing the number of consecutive comparison matches needed to raise the flag. This number can be written and read in the CMPFILTER field of ADC_EMR. The filtering option is dedicated to reinforce the detection of an analog signal overpassing a predefined threshold. The filter is cleared as soon as ADC_ISR is read, so this filtering function must be used with peripheral DMA controller and works only when using Interrupt mode (no polling).  2017 Microchip Technology Inc. DS60001525A-page 1495 SAMA5D4 SERIES The flag can be read on the COMPE bit of the Interrupt Status Register (ADC_ISR) and can trigger an interrupt. The high threshold and the low threshold can be read/write in the Compare Window Register (ADC_CWR). If the comparison window is to be used with the LOWRES bit set in ADC_MR, the thresholds do not need to be adjusted, as the adjustment is done internally. However, whether the LOWRES bit is set or not, thresholds must always be configured in accordance with the maximum ADC resolution. 48.6.9 ADC Timings The ADC startup time is programmed through the STARTUP field in ADC_MR. See section “Electrical Characteristics”. The ADC controller provides a tracking time of ADC clock cycles. A minimal tracking time is necessary for the ADC to guarantee the best converted final value between two channel selections. This time must be programmed in the TRACKTIM field in ADC_MR. Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration. See section “Electrical Characteristics”. 48.6.10 Enhanced Resolution Mode and Digital Averaging Function 48.6.10.1 Enhanced Resolution Mode The Enhanced Resolution mode is enabled if LOWRES is cleared in ADC_MR, and the OSR field is configured to 1 or 2 in ADC_EMR. The enhancement is based on a digital averaging function. There is no averaging on the last index channel if the measure is triggered by an RTC event. In this mode, the ADC Controller will trade off conversion speed against accuracy by averaging multiple samples, thus providing a digital low-pass filter function. k = N–1 Σ 1 ADC_LCDR.LDATA = ----- × M ADC ( k ) k = 0 where N and M are given in the table below. Table 48-4: Digital Averaging Function Configuration versus OSR Values ADC_EMR.OSR Value ADC_LCDR.LDATA Length N Value M Value Full Scale Value Maximum Value 0 12 bits 1 1 4095 4095 1 13 bits 4 2 8191 8190 2 14 bits 16 4 16383 16381 The average result is valid in ADC_CDRx (x corresponds to the index of the channel) only if the EOCn flag is set in ADC_ISR and if the OVREn flag is cleared in ADC_OVER. The average result for all channels is valid in ADC_LCDR only if DRDY is set and GOVRE is cleared in ADC_ISR. Note that ADC_CDRs are not buffered. Therefore, when an averaging sequence is ongoing, the value in these registers changes after each averaging sample. However, overrun flags in ADC_OVER rise as soon as the first sample of an averaging sequence is received. Thus the previous averaged value is not read, even if the new averaged value is not ready. Consequently, when an overrun flag rises in ADC_OVER, it means that the previous unread data is lost but it does not mean that this data has been overwritten by the new averaged value as the averaging sequence concerning this channel can still be ongoing. When an oversampling is performed, the maximum value that can be read on ADC_CDRx or ADC_LCDR is not the full-scale value, even if the maximum voltage is supplied on the analog input. Refer to Table 48-4 “Digital Averaging Function Configuration versus OSR Values”. DS60001525A-page 1496  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.6.10.2 Averaging Function versus Trigger Events The samples can be defined in different ways for the averaging function depending on the configuration of the ASTE bit in ADC_EMR and the USEQ bit in ADC_MR. When USEQ = 0, there are two possible ways to generate the averaging through the trigger event. If ASTE = 0 in ADC_EMR, every trigger event generates one sample for each enabled channel as described in Figure 48-6. Therefore four trigger events are requested to get the result of averaging if OSR = 1. Figure 48-6: Digital Averaging Function Waveforms Over Multiple Trigger Events ADC_EMR.OSR = 1, ASTE = 0, ADC_CHSR[1:0] = 0x3 and ADC_MR.USEQ = 0 Internal/External Trigger Event ADC_SEL ADC_CDR[0] 0 0 1 CH0_0 0 1 0i1 0i2 0 1 1 0i3 0 1 CH0_1 0i1 Read ADC_CDR[0] EOC[0] OVR[0] ADC_CDR[1] CH1_0 1i1 1i2 1i3 CH1_1 1i1 Read ADC_CDR[1] Read ADC_CDR[1] EOC[1] ADC_LCDR CH1_0 CH0_1 CH1_1 DRDY Read ADC_LCDR Read ADC_LCDR Notes: ADC_SEL: Command to the ADC analog cell 0i1, 0i2, 0i3, 1i1, 1i2, 1i3 are intermediate results and CH0_0, CH0_1, CH1_0 and CH1_1 are final results of average function. If ASTE = 1 in ADC_EMR and USEQ = 0 in ADC_MR, the sequence to be converted, defined in ADC_CHSR, is automatically repeated n times (where n corresponds to the oversampling ratio defined in the OSR field in ADC_EMR). As a result, only one trigger is required to obtain the result of the averaging function as described in Figure 48-7.  2017 Microchip Technology Inc. DS60001525A-page 1497 SAMA5D4 SERIES Figure 48-7: Digital Averaging Function Waveforms on a Single Trigger Event ADC_EMR.OSR = 1, ASTE = 1, ADC_CHSR[1:0] = 0x3 and ADC_MR.USEQ = 0 Internal/External Trigger Event ADC_SEL ADC_CDR[0] 0 CH0_0 1 0 1 0i1 0 1 0i2 0 1 0 0i3 1 0 1 CH0_1 Read ADC_CDR[0] EOC[0] ADC_CDR[1] CH1_0 1i1 1i2 1i3 CH1_1 Read ADC_CDR[1] EOC[1] CH0_1 ADC_LCDR CH1_1 DRDY Read ADC_LCDR Note: ADC_SEL: Command to the ADC analog cell 0i1, 0i2, 0i3, 1i1, 1i2, 1i3 are intermediate results and CH0_0, CH0_1, CH1_0 and CH1_1 are final results of average function. When USEQ = 1, the user can define the channel sequence to be converted by configuring ADC_SEQRx and ADC_CHER so that channels are not interleaved during the averaging period. Under these conditions, a sample is defined for each end of conversion as described in Figure 48-8. When USEQ = 1 and ASTE = 1, OSR can be only configured to 1. Up to three channels can be converted in this mode. The averaging result will be placed in the corresponding ADC_CDRx and in ADC_LCDR for each trigger event. The ADC real sample rate remains the maximum ADC sample rate divided by 4. It is important that the user sequence follows a specific pattern. The user sequence must be programmed in such a way that it generates a stream of conversion, where a same channel is successively converted. Table 48-5: Example Sequence Configurations (USEQ = 1, ASTE = 1, OSR = 1) Number of Channels Non-interleaved Averaging - Register Value Register 1 (e.g., CH0) 2 (e.g., CH0, CH1) 3 (e.g., CH0, CH1, CH2) ADC_CHSR 0x0000_000F 0x0000_00FF 0x0000_0FFF ADC_SEQR1 0x0000_0000 0x1111_0000 0x1111_0000 ADC_SEQR2 0x0000_0000 0x0000_0000 0x0000_2222 DS60001525A-page 1498  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 48-8: Digital Averaging Function Waveforms on a Single Trigger Event, Non-interleaved ADC_EMR.OSR = 1, ASTE = 1, ADC_CHSR[7:0] = 0xFF and ADC_MR.USEQ = 1 ADC_SEQR1 = 0x1111_0000 Internal/External Trigger Event ADC_SEL ADC_CDR[0] 0 0 0 0 CH0_0 0i1 0i2 0i3 1 1 1 0 0 0 0 CH0_1 Read ADC_CDR[0] EOC[0] ADC_CDR[1] 1 CH1_0 1i1 1i2 1i3 CH1_1 Read ADC_CDR[1] EOC[1] ADC_LCDR CH0_1 CH1_1 DRDY Read ADC_LCDR Note: 48.6.11 48.6.11.1 ADC_SEL: Command to the ADC analog cell 0i1, 0i2, 0i3, 1i1, 1i2, 1i3 are intermediate results and CH0_0, CH0_1, CH1_0 and CH1_1 are final results of average function. Touchscreen Touchscreen Mode The TSMODE parameter of the ADC Touchscreen Mode Register (ADC_TSMR) is used to enable/disable the touchscreen functionality, to select the type of screen (4-wire or 5-wire) and, in the case of a 4-wire screen and to activate (or not) the pressure measurement. In 4-wire mode, channel 0, 1, 2 and 3 must not be used for classic ADC conversions. Likewise, in 5-wire mode, channel 0, 1, 2, 3, and 4 must not be used for classic ADC conversions. 48.6.11.2 4-wire Resistive Touchscreen Principles A resistive touchscreen is based on two resistive films, each one being fitted with a pair of electrodes, placed at the top and bottom on one film, and on the right and left on the other. In between, there is a layer acting as an insulator, but also enables contact when you press the screen. This is illustrated in Figure 48-9. The ADC controller has the ability to perform without external components: • position measurement • pressure measurement • pen detection  2017 Microchip Technology Inc. DS60001525A-page 1499 SAMA5D4 SERIES Figure 48-9: Touchscreen Position Measurement Pen Contact XP YM YP XM VDD XP YP XP Volt XM GND Vertical Position Detection 48.6.11.3 VDD YP Volt YM GND Horizontal Position Detection 4-wire Position Measurement Method As shown in Figure 48-9, to detect the position of a contact, a supply is first applied from top to bottom. Due to the linear resistance of the film, there is a voltage gradient from top to bottom. When a contact is performed on the screen, the voltage propagates at the point the two surfaces come into contact with the second film. If the input impedance on the right and left electrodes sense is high enough, the film does not affect this voltage, despite its resistive nature. For the horizontal direction, the same method is used, but by applying supply from left to right. The range depends on the supply voltage and on the loss in the switches that connect to the top and bottom electrodes. In an ideal world (linear, with no loss through switches), the horizontal position is equal to: VYM / VDD or VYP / VDD. The implementation with on-chip power switches is shown in Figure 48-10. The voltage measurement at the output of the switch compensates for the switches loss. It is possible to correct for switch loss by performing the operation: [VYP - VXM] / [VXP - VXM]. This requires additional measurements, as shown in Figure 48-10. DS60001525A-page 1500  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 48-10: Touchscreen Switches Implementation XP VDDANA 0 XM GND 1 To the ADC YP VDDANA 2 YM GND 3 VDDANA VDDANA Switch Resistor Switch Resistor YP XP XP YP YM XM Switch Resistor Switch Resistor GND Horizontal Position Detection 48.6.11.4 GND Vertical Position Detection 4-wire Pressure Measurement Method The method to measure the pressure (Rp) applied to the touchscreen is based on the known resistance of the X-Panel resistance (Rxp). Three conversions (Xpos,Z1,Z2) are necessary to determine the value of Rp (Zaxis resistance). Rp = Rxp × (Xpos/1024) × [(Z2/Z1)-1]  2017 Microchip Technology Inc. DS60001525A-page 1501 SAMA5D4 SERIES Figure 48-11: Pressure Measurement VDDANA VDDANA Switch Resistor Switch Resistor XP YP Open circuit Switch Resistor XP YP Rp YM XM Rp YM XM GND XPos Measure(Yp) YM XM Open circuit Switch Resistor Switch Resistor Open circuit XP YP Rp 48.6.11.5 VDDANA Switch Resistor GND GND Z1 Measure(Xp) Z2 Measure(Xp) 5-wire Resistive Touchscreen Principles To make a 5-wire touchscreen, a resistive layer with a contact point at each corner and a conductive layer are used. The 5-wire touchscreen differs from the 4-wire type mainly in that the voltage gradient is applied only to one layer, the resistive layer, while the other layer is the sense layer for both measurements. The measurement of the X position is obtained by biasing the upper left corner and lower left corner to VDDANA and the upper right corner and lower right to ground. To measure along the Y axis, bias the upper left corner and upper right corner to VDDANA and bias the lower left corner and lower right corner to ground. DS60001525A-page 1502  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 48-12: 5-Wire Principle UL Pen Contact Resistive layer UR Sense LL LR Conductive Layer UL VDDANA UR VDDANA for Yp GND for Xp Sense LL VDDANA for Xp GND for Yp 48.6.11.6 LR GND 5-wire Position Measurement Method In an application only monitoring clicks, 100 points per second is typically needed. For handwriting or motion detection, the number of measurements to consider is approximately 200 points per second. This must take into account that multiple measurements are included (oversampling, filtering) to compute the correct point. The 5-wire touchscreen panel works by applying a voltage at the corners of the resistive layer and measuring the vertical or horizontal resistive network with the sense input. The ADC converts the voltage measured at the point the panel is touched. A measurement of the Y position of the pointing device is made by: • Connecting Upper left (UL) and upper right (UR) corners to VDDANA • Connecting Lower left (LL) and lower right (LR) corners to ground. • The voltage measured is determined by the voltage divider developed at the point of touch (Yposition) and the SENSE input is converted by ADC. A measurement of the X position of the pointing device is made by: • Connecting the upper left (UL) and lower left (LL) corners to ground • Connecting the upper right and lower right corners to VDDANA. • The voltage measured is determined by the voltage divider developed at the point of touch (Xposition) and the SENSE input is converted by ADC.  2017 Microchip Technology Inc. DS60001525A-page 1503 SAMA5D4 SERIES Figure 48-13: Touchscreen Switches Implementation UL VDDANA 0 UR GND VDDANA 1 GND LL VDDANA Sense LR UL VDDANA 2 To the ADC 3 GND 4 UR VDDANA for Ypos GND for Xpos Sense LL 48.6.11.7 VDDANA for Xpos GND for Ypos LR GND Sequence and Noise Filtering The ADC Controller can manage ADC conversions and touchscreen measurement. On each trigger event the sequence of ADC conversions is performed as described in Section 48.6.7 “Sleep Mode and Conversion Sequencer”. The touchscreen measure frequency can be specified in number of trigger events by writing the TSFREQ parameter in ADC_TSMR. An internal counter counts triggers up to TSFREQ, and every time it rolls out, a touchscreen sequence is appended to the classic ADC conversion sequence (see Figure 48-14). Additionally the user can average multiple touchscreen measures by writing the TSAV parameter in ADC_TSMR. This can be 1, 2, 4 or 8 measures performed on consecutive triggers as illustrated in Figure 48-14 below. Consequently, the TSFREQ parameter must be greater or equal to the TSAV parameter. DS60001525A-page 1504  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 48-14: Insertion of Touchscreen Sequences (TSFREQ = 2; TSAV = 1) Trigger event ADC_SEL C T C T C C C C: Classic ADC Conversion Sequence - T C T C T: Touchscreen Sequence XRDY Read the ADC_XPOSR Read the ADC_XPOSR YRDY Note: 48.6.11.8 ADC_SEL: Command to the ADC analog cell Read the ADC_YPOSR Read the ADC_YPOSR Measured Values, Registers and Flags As soon as the controller finishes the Touchscreen sequence, XRDY, YRDY and PRDY are set and can generate an interrupt. These flags can be read in the ADC Interrupt Status Register (ADC_ISR). They are reset independently by reading in the ADC Touchscreen X Position Register (ADC_XPOSR), the ADC Touchscreen Y Position Register (ADC_YPOSR) and the ADC Touchscreen Pressure Register (ADC_PRESSR). ADC_XPOSR presents XPOS (VX - VXmin) on its LSB and XSCALE (VXMAX - VXmin) aligned on the 16th bit. ADC_YPOSR presents YPOS (VY - VYmin) on its LSB and YSCALE (VYMAX - VYmin) aligned on the 16th bit. To improve the quality of the measure, the user must calculate XPOS/XSCALE and YPOS/YSCALE. VXMAX, VXmin, VYMAX, and VYmin are measured at the first startup of the controller. These values can change during use, so it can be necessary to refresh them. Refresh can be done by writing ‘1’ in the TSCALIB field of the control Register (ADC_CR). ADC_PRESSR presents Z1 on its LSB and Z2 aligned on the 16th bit. See Section 48.6.11.4 “4-wire Pressure Measurement Method”. 48.6.11.9 Pen Detect Method When there is no contact, it is not necessary to perform a conversion. However, it is important to detect a contact by keeping the power consumption as low as possible. The implementation polarizes one panel by closing the switch on (XP/UL) and ties the horizontal panel by an embedded resistor connected to YM / Sense. This resistor is enabled by a fifth switch. Since there is no contact, no current is flowing and there is no related power consumption. As soon as a contact occurs, a current is flowing in the Touchscreen and a Schmitt trigger detects the voltage in the resistor. The Touchscreen Interrupt configuration is entered by programming the PENDET bit in ADC_TSMR. If this bit is written at 1, the controller samples the pen contact state when it is not converting and waiting for a trigger. To complete the circuit, a programmable debouncer is placed at the output of the Schmitt trigger. This debouncer is programmable up to 215 ADC clock periods. The debouncer length can be selected by programming the field PENDBC in ADC_TSMR. Due to the analog switch’s structure, the debouncer circuitry is only active when no conversion (touchscreen or classic ADC channels) is in progress. Thus, if the time between the end of a conversion sequence and the arrival of the next trigger event is lower than the debouncing time configured on PENDBC, the debouncer will not detect any contact.  2017 Microchip Technology Inc. DS60001525A-page 1505 SAMA5D4 SERIES Figure 48-15: Touchscreen Pen Detect X+/UL VDDANA 0 X-/UR GND VDDANA 1 GND Y+/LL Y-/SENSE LR VDDANA GND GND 2 To the ADC 3 4 PENDBC Debouncer Pen Interrupt GND The touchscreen pen detect can be used to generate an ADC interrupt to wake up the system. The pen detect generates two types of status, reported in ADC_ISR: • the PEN bit is set as soon as a contact exceeds the debouncing time as defined by PENDBC and remains set until ADC_ISR is read. • the NOPEN bit is set as soon as no current flows for a time over the debouncing time as defined by PENDBC and remains set until ADC_ISR is read. Both bits are automatically cleared as soon as ADC_ISR is read, and can generate an interrupt by writing ADC_IER. Moreover, the rising of either one of them clears the other, they cannot be set at the same time. The PENS bit of ADC_ISR shows the current status of the pen contact. 48.6.12 Buffer Structure The DMA read channel is triggered each time a new data is stored in ADC_LCDR. The same structure of data is repeatedly stored in ADC_LCDR each time a trigger event occurs. Depending on user mode of operation (ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_TSMR) the structure differs. Each data read to DMA buffer, carried on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR, the four most significant bits are carrying the channel number thus allowing an easier post-processing in the DMA buffer or better checking the DMA buffer integrity. DS60001525A-page 1506  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 48-16: Buffer Structure Assuming ADC_CHSR = 0x000_01600 ADC_EMR.TAG = 1 trig.event1 DMA Buffer Structure trig.event2 Assuming ADC_CHSR = 0x000_01600 ADC_EMR.TAG = 0 5 ADC_CDR5 DMA Transfer Base Address (BA) 6 ADC_CDR6 BA + 0x02 8 ADC_CDR8 BA + 0x04 5 ADC_CDR5 6 trig.event1 0 ADC_CDR5 0 ADC_CDR6 0 ADC_CDR8 BA + 0x06 0 ADC_CDR5 ADC_CDR6 BA + 0x08 0 ADC_CDR6 8 ADC_CDR8 BA + 0x0A 0 ADC_CDR8 5 ADC_CDR5 BA + [(N-1) * 6] 0 ADC_CDR5 6 ADC_CDR6 BA + [(N-1) * 6]+ 0x02 0 ADC_CDR6 8 ADC_CDR8 BA + [(N-1) * 6]+ 0x04 0 ADC_CDR8 DMA Buffer Structure trig.event2 trig.eventN trig.eventN As soon as touchscreen conversions are required, the pen detection function may help the post-processing of the buffer. Refer to Section 48.6.12.4 “Pen Detection Status”. 48.6.12.1 Classic ADC Channels Only (Touchscreen Disabled) When no touchscreen conversion is required (i.e., TSMODE = 0 in ADC_TSMR), the structure of data within the buffer is defined by ADC_MR, ADC_CHSR, ADC_SEQRx. See Figure 48-16. If the user sequence is not used (i.e., USEQ is cleared in ADC_MR) then only the value of ADC_CHSR defines the data structure. For each trigger event, enabled channels will be consecutively stored in ADC_LCDR and automatically read to the buffer. When the user sequence is configured (i.e., USEQ is set in ADC_MR) not only does ADC_CHSR modify the data structure of the buffer, but ADC_SEQRx registers may modify the data structure of the buffer as well. 48.6.12.2 Touchscreen Channels Only When only touchscreen conversions are required (i.e., TSMODE ≠ 0 in ADC_TSMR and ADC_CHSR equals 0), the structure of data within the buffer is defined by ADC_TSMR. When TSMODE = 1 or 3, each trigger event adds two half-words in the buffer (assuming TSAV = 0), first half-word being XPOS of ADC_XPOSR then YPOS of ADC_YPOSR. If TSAV/TSFREQ ≠ 0, the data structure remains unchanged. Not all trigger events add data to the buffer. When TSMODE = 2, each trigger event adds four half-words to the buffer (assuming TSAV = 0), first half-word being XPOS of ADC_XPOSR followed by YPOS of ADC_YPOSR and finally Z1 followed by Z2, both located in ADC_PRESSR. When TAG is set (ADC_EMR), the CHNB field (four most significant bits of ADC_LCDR) is cleared when XPOS is transmitted and set when YPOS is transmitted, allowing an easier post-processing of the buffer or a better checking of the buffer integrity. In case 4-wire with Pressure mode is selected, Z1 value is transmitted to the buffer along with tag set to 2 and Z2 is tagged with value 3. XSCALE and YSCALE (calibration values) are not transmitted to the buffer because they are supposed to be constant and moreover only measured at the very first startup of the controller or upon user request. There is no change in buffer structure whatever the value of PENDET bit configuration in ADC_TSMR but it is recommended to use the pen detection function for buffer post-processing (refer to Section 48.6.12.4 “Pen Detection Status”).  2017 Microchip Technology Inc. DS60001525A-page 1507 SAMA5D4 SERIES Figure 48-17: Buffer Structure When Only Touchscreen Channels are Enabled Assuming ADC_TSMR.TSMOD = 1 or 3 ADC_TSMR.TSAV = 0 ADC_CHSR = 0x000_00000, ADC_EMR.TAG = 1 trig.event1 DMA Buffer Structure trig.event2 0 ADC_XPOSR DMA Transfer Base Address (BA) 1 ADC_YPOSR BA + 0x02 0 ADC_XPOSR BA + 0x04 1 ADC_YPOSR BA + 0x06 0 ADC_XPOSR BA + [(N-1) * 4] trig.eventN 1 ADC_YPOSR DMA Buffer Structure trig.event2 DMA Buffer Structure trig.event2 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_XPOSR 0 ADC_YPOSR trig.eventN Assuming ADC_TSMR.TSMOD = 2 ADC_TSMR.TSAV = 0 ADC_CHSR = 0x000_00000, ADC_EMR(TAG) = 0 0 ADC_XPOSR trig.event1 DMA Transfer Base Address (BA) 0 ADC_XPOSR 1 ADC_YPOSR BA + 0x02 0 ADC_YPOSR 2 ADC_PRESSR(Z1) BA + 0x04 0 ADC_PRESSR(Z1) 3 ADC_PRESSR(Z2) BA + 0x06 0 ADC_PRESSR(Z2) 0 ADC_XPOSR BA + 0x08 0 ADC_XPOSR 1 ADC_YPOSR BA + 0x0A 0 ADC_YPOSR 2 ADC_PRESSR(Z1) BA + 0x0C 0 ADC_PRESSR(Z1) 3 ADC_PRESSR(Z2) BA + 0x0E 0 ADC_PRESSR(Z2) 0 ADC_XPOSR BA + [(N-1) * 8] 0 ADC_XPOSR 1 ADC_YPOSR 0 ADC_YPOSR 2 ADC_PRESSR(Z1) BA + [(N-1) * 8]+ 0x04 0 ADC_PRESSR(Z1) 3 ADC_PRESSR(Z2) BA + [(N-1) * 8]+ 0x06 0 ADC_PRESSR(Z2) DMA Buffer Structure trig.event2 trig.eventN 48.6.12.3 trig.event1 BA + [(N-1) * 4]+ 0x02 Assuming ADC_TSMR.TSMOD = 2 ADC_TSMR.TSAV = 0 ADC_CHSR = 0x000_00000, ADC_EMR.TAG = 1 trig.event1 Assuming ADC_TSMR.TSMOD = 1 or 3 ADC_TSMR.TSAV = 0 ADC_CHSR = 0x000_00000, ADC_EMR.TAG = 0 trig.eventN BA + [(N-1) * 8]+ 0x02 Interleaved Channels When both classic ADC channels (CH4/CH5 up to CH5 are set in ADC_CHSR) and touchscreen conversions are required (TSMODE ≠ 0 in ADC_TSMR) the structure of the buffer differs according to TSAV and TSFREQ values. If TSFREQ ≠ 0, not all events generate touchscreen conversions, therefore the buffer structure is based on 2TSFREQ trigger events. Given a TSFREQ value, the location of touchscreen conversion results depends on TSAV value. When TSFREQ = 0, TSAV must equal 0. There is no change in buffer structure whatever the value of PENDET bit configuration in ADC_TSMR but it is recommended to use the pen detection function for buffer post-processing (refer to Section 48.6.12.4 “Pen Detection Status”). DS60001525A-page 1508  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 48-18: Buffer Structure When Classic ADC and Touchscreen Channels are Interleaved Assuming ADC_TSMR.TSMOD = 1 ADC_TSMR.TSAV = ADC_TSMR(TSFREQ = 0 ADC_CHSR = 0x000_0100, ADC_EMR.TAG = 1 trig.event1 8 DMA Buffer Structure trig.event2 ADC_CDR8 DMA Transfer Base Address (BA) 0 ADC_XPOSR BA + 0x02 1 ADC_YPOSR BA + 0x04 Assuming ADC_TSMR.TSMOD = 1 ADC_TSMR.TSAV = ADC_TSMR.TSFREQ = 0 ADC_CHSR = 0x000_0100, ADC_EMR.TAG = 0 trig.event1 DMA Buffer Structure trig.event2 8 0 ADC_CDR8 BA + 0x06 ADC_XPOSR BA + 0x08 BA + 0x0A 1 ADC_YPOSR 8 ADC_CDR8 BA + [(N-1) * 6] ADC_XPOSR BA + [(N-1) * 6]+ 0x02 ADC_YPOSR BA + [(N-1) * 6]+ 0x04 trig.eventN ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR trig.eventN 0 1 Assuming ADC_TSMR.TSMOD = 1 ADC_TSMR.TSAV = 0, ADC_TSMR.TSFREQ = 1 ADC_CHSR = 0x000_0100, ADC_EMR.TAG = 1 trig.event1 ADC_CDR8 DMA Transfer Base Address (BA) 0 ADC_XPOSR BA + 0x02 1 ADC_YPOSR BA + 0x04 8 ADC_CDR8 BA + 0x06 8 Assuming ADC_TSMR.TSMOD = 1 ADC_TSMR.TSAV = 1, ADC_TSMR.TSFREQ = 1 ADC_CHSR = 0x000_0100, ADC_EMR.TAG = 1 trig.event1 trig.event2 DMA Buffer Structure trig.event2 trig.event3 ADC_CDR8 BA + 0x08 0 ADC_XPOSR BA + 0x0A 1 ADC_YPOSR BA + 0x0c 8 ADC_CDR8 BA + 0x0e 8 ADC_CDR8 BA + [(N-1) * 8] 0 ADC_XPOSR BA + [(N-1) * 8]+ 0x02 1 ADC_YPOSR BA + [(N-1) * 8]+ 0x04 8 ADC_CDR8 BA + [(N-1) * 8]+ 0x06 8 trig.event4 trig.eventN DMA Buffer Structure 8 ADC_CDR8 8 ADC_CDR8 0 ADC_XPOSR 1 ADC_YPOSR 8 ADC_CDR8 8 ADC_CDR8 0 ADC_XPOSR 1 ADC_YPOSR 8 ADC_CDR8 8 ADC_CDR8 0 ADC_XPOSR 1 ADC_YPOSR trig.event3 trig.event4 trig.eventN trig.eventN+1 48.6.12.4 0 trig.eventN+1 Pen Detection Status If the pen detection measure is enabled (PENDET is set in ADC_TSMR), the XPOS, YPOS, Z1, Z2 values transmitted to the buffer through ADC_LCDR are cleared (including the CHNB field), if the PENS flag of ADC_ISR is 0. When the PENS flag is set, XPOS, YPOS, Z1, Z2 are normally transmitted. Therefore, using pen detection together with tag function eases the post-processing of the buffer, especially to determine which touchscreen converted values correspond to a period of time when the pen was in contact with the screen.  2017 Microchip Technology Inc. DS60001525A-page 1509 SAMA5D4 SERIES When the pen detection is disabled or the tag function is disabled, XPOS, YPOS, Z1, Z2 are normally transmitted without tag and no relationship can be found with pen status, thus post-processing may not be easy. Figure 48-19: Buffer Structure With and Without Pen Detection Enabled Assuming ADC_TSMR.TSMOD = 1, PENDET = 1 ADC_TSMR.TSAV = ADC_TSMR.TSFREQ = 0 ADC_CHSR = 0x000_0100, ADC_EMR.TAG = 1 ADC_CDR8 DMA Transfer Base Address (BA) 0 ADC_XPOSR BA + 0x02 1 ADC_YPOSR BA + 0x04 PENS = 1 8 DMA buffer Structure trig.event2 8 ADC_CDR8 BA + 0x06 0 ADC_XPOSR BA + 0x08 trig.event1 DMA buffer Structure PENS = 1 trig.event1 Assuming ADC_TSMR.TSMOD = 1, PENDET = 1 ADC_TSMR.TSAV = ADC_TSMR.TSFREQ = 0 ADC_CHSR = 0x000_0100, ADC_EMR.TAG = 0 BA + 0x0A 1 ADC_YPOSR 8 ADC_CDR8 BA + [(N-1) * 6] 0 BA + [(N-1) * 6]+ 0x02 0 0 BA + [(N-1) * 6]+ 0x04 8 ADC_CDR8 0 0 0 0 0 2 successive tags cleared => PENS = 0 48.6.13 ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_CDR8 0 ADC_XPOSR 0 ADC_YPOSR 0 ADC_CDR8 0 ADC_XPOSR* 0 ADC_YPOSR* 0 ADC_CDR8 0 ADC_XPOSR* 0 ADC_YPOSR* trig.eventN PENS = 0 PENS = 0 trig.eventN trig.eventN+1 trig.event2 0 ADC_XPOSR*, ADC_YPOSR* can be any value when PENS = 0 Fault Output The ADC Controller internal fault output is directly connected to PWM fault input. Fault output may be asserted depending on the configuration of ADC_EMR and ADC_CWR and converted values. When the compare occurs, the ADC fault output generates a pulse of one peripheral clock cycle to the PWM fault input. This fault line can be enabled or disabled within PWM. Should it be activated and asserted by the ADC Controller, the PWM outputs are immediately placed in a safe state (pure combinational path). Note that the ADC fault output connected to the PWM is not the COMPE bit. Thus the Fault mode (FMOD) within the PWM configuration must be FMOD = 1. 48.6.14 Register Write Protection To prevent any single software error from corrupting ADC behavior, certain registers in the address space can be write-protected by setting the bit WPEN in the “ADC Write Protection Mode Register” (ADC_WPMR). If a write access to the protected registers is detected, the WPVS flag in the “ADC Write Protection Status Register” (ADC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted. The WPVS flag is automatically reset by reading ADC_WPSR. The following registers are write-protected when WPEN is set in ADC_WPMR: • • • • • • ADC Mode Register ADC Channel Sequence 1 Register ADC Channel Enable Register ADC Channel Disable Register ADC Extended Mode Register ADC Compare Window Register DS60001525A-page 1510  2017 Microchip Technology Inc. SAMA5D4 SERIES • ADC Analog Control Register • ADC Touchscreen Mode Register • ADC Trigger Register  2017 Microchip Technology Inc. DS60001525A-page 1511 SAMA5D4 SERIES 48.7 Analog-to-Digital (ADC) User Interface Table 48-6: Offset Register Mapping Register Name Access Reset 0x00 Control Register ADC_CR Write-only – 0x04 Mode Register ADC_MR Read/Write 0x00000000 0x08 Channel Sequence Register 1 ADC_SEQR1 Read/Write 0x00000000 0x0C Reserved – – – 0x10 Channel Enable Register ADC_CHER Write-only – 0x14 Channel Disable Register ADC_CHDR Write-only – 0x18 Channel Status Register ADC_CHSR Read-only 0x00000000 0x1C Reserved – – – 0x20 Last Converted Data Register ADC_LCDR Read-only 0x00000000 0x24 Interrupt Enable Register ADC_IER Write-only – 0x28 Interrupt Disable Register ADC_IDR Write-only – 0x2C Interrupt Mask Register ADC_IMR Read-only 0x00000000 0x30 Interrupt Status Register ADC_ISR Read-only 0x00000000 0x34 Reserved – – – 0x38 Reserved – – – 0x3C Overrun Status Register ADC_OVER Read-only 0x00000000 0x40 Extended Mode Register ADC_EMR Read/Write 0x00000000 0x44 Compare Window Register ADC_CWR Read/Write 0x00000000 0x48 Reserved – – – 0x4C Reserved – – – 0x50 Channel Data Register 0 ADC_CDR0 Read-only 0x00000000 0x54 Channel Data Register 1 ADC_CDR1 Read-only 0x00000000 ... ... ... ... Channel Data Register 4 ADC_CDR4 Read-only 0x00000000 Reserved – – – Analog Control Register ADC_ACR Read/Write 0x00000100 Reserved – – – 0xB0 Touchscreen Mode Register ADC_TSMR Read/Write 0x00000000 0xB4 Touchscreen X Position Register ADC_XPOSR Read-only 0x00000000 0xB8 Touchscreen Y Position Register ADC_YPOSR Read-only 0x00000000 0xBC Touchscreen Pressure Register ADC_PRESSR Read-only 0x00000000 0xC0 Trigger Register ADC_TRGR Read/Write 0x00000000 Reserved – – – ... 0x60 0x64–0x90 0x94 0x98–0xAC 0xC4–0xE0 DS60001525A-page 1512  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 48-6: Register Mapping (Continued) Offset Register Name 0xE4 Write Protection Mode Register 0xE8 0xEC–0xFC Note: Access Reset ADC_WPMR Read/Write 0x00000000 Write Protection Status Register ADC_WPSR Read-only 0x00000000 Reserved – – – Any offset not listed in the table must be considered as “reserved”.  2017 Microchip Technology Inc. DS60001525A-page 1513 SAMA5D4 SERIES 48.7.1 ADC Control Register Name:ADC_CR Address:0xFC034000 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TSCALIB 1 START 0 SWRST SWRST: Software Reset 0: No effect. 1: Resets the ADC, simulating a hardware reset. START: Start Conversion 0: No effect. 1: Begins analog-to-digital conversion. TSCALIB: Touchscreen Calibration 0: No effect. 1: Programs screen calibration (VDD/GND measurement) If conversion is in progress, the calibration sequence starts at the beginning of a new conversion sequence. If no conversion is in progress, the calibration sequence starts at the second conversion sequence located after the TSCALIB command (Sleep mode, waiting for a trigger event). TSCALIB measurement sequence does not affect the Last Converted Data Register (ADC_LCDR). DS60001525A-page 1514  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.7.2 ADC Mode Register Name:ADC_MR Address:0xFC034004 Access:Read/Write 31 USEQ 30 – 29 – 28 – 27 23 – 22 – 21 – 20 – 19 15 14 13 12 26 25 24 17 16 TRACKTIM 18 STARTUP 11 10 9 8 3 2 TRGSEL 1 0 – PRESCAL 7 – 6 – 5 SLEEP 4 LOWRES This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. TRGSEL: Trigger Selection Value Name Description 0 ADC_TRIG0 ADTRG 1 ADC_TRIG1 TIOA0 2 ADC_TRIG2 TIOA1 3 ADC_TRIG3 TIOA2 4 ADC_TRIG4 PWM event line 0 5 ADC_TRIG5 PWM_even line 1 6 ADC_TRIG6 Reserved 7 ADC_TRIG7 – Note: The trigger selection can be performed only if TRGMOD = 1,2 or 3 in ADC Trigger Register. LOWRES: Resolution Value Name Description 0 BITS_10 10-bit resolution. For higher resolution by averaging, refer to Section 48.7.13 “ADC Extended Mode Register”. 1 BITS_8 8-bit resolution SLEEP: Sleep Mode Value Name Description 0 NORMAL Normal Mode: The ADC core and reference voltage circuitry are kept ON between conversions. 1 SLEEP Sleep Mode: The ADC core and reference voltage circuitry are OFF between conversions. PRESCAL: Prescaler Rate Selection PRESCAL = (fperipheral clock / (2 × fADCCLK)) – 1.  2017 Microchip Technology Inc. DS60001525A-page 1515 SAMA5D4 SERIES STARTUP: Startup Time Value Name Description 0 SUT0 0 periods of ADCCLK 1 SUT8 8 periods of ADCCLK 2 SUT16 16 periods of ADCCLK 3 SUT24 24 periods of ADCCLK 4 SUT64 64 periods of ADCCLK 5 SUT80 80 periods of ADCCLK 6 SUT96 96 periods of ADCCLK 7 SUT112 112 periods of ADCCLK 8 SUT512 512 periods of ADCCLK 9 SUT576 576 periods of ADCCLK 10 SUT640 640 periods of ADCCLK 11 SUT704 704 periods of ADCCLK 12 SUT768 768 periods of ADCCLK 13 SUT832 832 periods of ADCCLK 14 SUT896 896 periods of ADCCLK 15 SUT960 960 periods of ADCCLK TRACKTIM: Tracking Time Tracking Time = (TRACKTIM + 1) × ADCCLK periods. USEQ: Use Sequence Enable Value Name Description 0 NUM_ORDER Normal Mode: The controller converts channels in a simple numeric order depending only on the channel index. 1 REG_ORDER User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 register and can be used to convert the same channel several times. DS60001525A-page 1516  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.7.3 ADC Channel Sequence 1 Register Name:ADC_SEQR1 Address:0xFC034008 Access:Read/Write 31 30 29 28 27 26 – 23 22 21 20 19 18 – 15 14 13 6 24 17 16 9 8 1 0 – 12 11 10 USCH4 7 25 – USCH3 5 4 3 USCH2 2 USCH1 This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. USCHx: User Sequence Number x The allowed range is 0 up to 4, thus only the sequencer from CH0 to CH4 can be used. This register activates only if the USEQ field in ADC_MR field is set to ‘1’. Any USCHx field is processed only if the CHx-1 it in ADC_CHSR reads logical ‘1’, else any value written in USCHx does not add the corresponding channel in the conversion sequence. Configuring the same value in different fields leads to multiple samples of the same channel during the conversion sequence. This can be done consecutively, or not, according to user needs. When configuring consecutive fields with the same value, the associated channel is sampled as many time as the number of consecutive values, this part of the conversion sequence being triggered by a unique event.  2017 Microchip Technology Inc. DS60001525A-page 1517 SAMA5D4 SERIES 48.7.4 ADC Channel Enable Register Name:ADC_CHER Address:0xFC034010 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. CHx: Channel x Enable 0: No effect. 1: Enables the corresponding channel. Note: If USEQ = 1 in ADC_MR, CHx corresponds to the enable of sequence number x+1 described in ADC_SEQR1 (e.g. CH0 enables sequence number USCH1). DS60001525A-page 1518  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.7.5 ADC Channel Disable Register Name:ADC_CHDR Address:0xFC034014 Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. CHx: Channel x Disable 0: No effect. 1: Disables the corresponding channel. Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and corresponding EOCx and GOVRE flags in ADC_ISR and OVREx flags in ADC_OVER are unpredictable.  2017 Microchip Technology Inc. DS60001525A-page 1519 SAMA5D4 SERIES 48.7.6 ADC Channel Status Register Name:ADC_CHSR Address:0xFC034018 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 CH4 3 CH3 2 CH2 1 CH1 0 CH0 CHx: Channel x Status 0: The corresponding channel is disabled. 1: The corresponding channel is enabled. DS60001525A-page 1520  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.7.7 ADC Last Converted Data Register Name:ADC_LCDR Address:0xFC034020 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 1 0 CHNB 7 6 LDATA 5 4 3 2 LDATA LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. CHNB: Channel Number Indicates the last converted channel when the TAG bit is set in ADC_EMR. If the TAG bit is not set, CHNB = 0.  2017 Microchip Technology Inc. DS60001525A-page 1521 SAMA5D4 SERIES 48.7.8 ADC Interrupt Enable Register Name:ADC_IER Address:0xFC034024 Access:Write-only 31 – 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. EOCx: End of Conversion Interrupt Enable x XRDY: Touchscreen Measure XPOS Ready Interrupt Enable YRDY: Touchscreen Measure YPOS Ready Interrupt Enable PRDY: Touchscreen Measure Pressure Ready Interrupt Enable DRDY: Data Ready Interrupt Enable GOVRE: General Overrun Error Interrupt Enable COMPE: Comparison Event Interrupt Enable PEN: Pen Contact Interrupt Enable NOPEN: No Pen Contact Interrupt Enable DS60001525A-page 1522  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.7.9 ADC Interrupt Disable Register Name:ADC_IDR Address:0xFC034028 Access:Write-only 31 – 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. EOCx: End of Conversion Interrupt Disable x XRDY: Touchscreen Measure XPOS Ready Interrupt Disable YRDY: Touchscreen Measure YPOS Ready Interrupt Disable PRDY: Touchscreen Measure Pressure Ready Interrupt Disable DRDY: Data Ready Interrupt Disable GOVRE: General Overrun Error Interrupt Disable COMPE: Comparison Event Interrupt Disable PEN: Pen Contact Interrupt Disable NOPEN: No Pen Contact Interrupt Disable  2017 Microchip Technology Inc. DS60001525A-page 1523 SAMA5D4 SERIES 48.7.10 ADC Interrupt Mask Register Name:ADC_IMR Address:0xFC03402C Access:Read-only 31 – 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. EOCx: End of Conversion Interrupt Mask x XRDY: Touchscreen Measure XPOS Ready Interrupt Mask YRDY: Touchscreen Measure YPOS Ready Interrupt Mask PRDY: Touchscreen Measure Pressure Ready Interrupt Mask DRDY: Data Ready Interrupt Mask GOVRE: General Overrun Error Interrupt Mask COMPE: Comparison Event Interrupt Mask PEN: Pen Contact Interrupt Mask NOPEN: No Pen Contact Interrupt Mask DS60001525A-page 1524  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.7.11 ADC Interrupt Status Register Name:ADC_ISR Address:0xFC034030 Access:Read-only 31 PENS 30 NOPEN 29 PEN 28 – 27 – 26 COMPE 25 GOVRE 24 DRDY 23 – 22 PRDY 21 YRDY 20 XRDY 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 EOC4 3 EOC3 2 EOC2 1 EOC1 0 EOC0 EOCx: End of Conversion x (automatically set / cleared) 0: The corresponding analog channel is disabled, or the conversion is not finished. This flag is cleared when reading the corresponding ADC_CDRx registers. 1: The corresponding analog channel is enabled and conversion is complete. XRDY: Touchscreen XPOS Measure Ready (cleared on read) 0: No measure has been performed since the last read of ADC_XPOSR. 1: At least one measure has been performed since the last read of ADC_ISR. YRDY: Touchscreen YPOS Measure Ready (cleared on read) 0: No measure has been performed since the last read of ADC_YPOSR. 1: At least one measure has been performed since the last read of ADC_ISR. PRDY: Touchscreen Pressure Measure Ready (cleared on read) 0: No measure has been performed since the last read of ADC_PRESSR. 1: At least one measure has been performed since the last read of ADC_ISR. DRDY: Data Ready (automatically set / cleared) 0: No data has been converted since the last read of ADC_LCDR. 1: At least one data has been converted and is available in ADC_LCDR. GOVRE: General Overrun Error (cleared on read) 0: No general overrun error occurred since the last read of ADC_ISR. 1: At least one general overrun error has occurred since the last read of ADC_ISR. COMPE: Comparison Event (cleared on read) 0: No comparison event since the last read of ADC_ISR. 1: At least one comparison event (defined in ADC_EMR and ADC_CWR) has occurred since the last read of ADC_ISR. PEN: Pen contact (cleared on read) 0: No pen contact since the last read of ADC_ISR. 1: At least one pen contact since the last read of ADC_ISR. NOPEN: No Pen Contact (cleared on read) 0: No loss of pen contact since the last read of ADC_ISR. 1: At least one loss of pen contact since the last read of ADC_ISR.  2017 Microchip Technology Inc. DS60001525A-page 1525 SAMA5D4 SERIES PENS: Pen Detect Status 0: The pen does not press the screen. 1: The pen presses the screen. Note: PENS is not a source of interruption. DS60001525A-page 1526  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.7.12 ADC Overrun Status Register Name:ADC_OVER Address:0xFC03403C Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 OVRE4 3 OVRE3 2 OVRE2 1 OVRE1 0 OVRE0 OVREx: Overrun Error x 0: No overrun error on the corresponding channel since the last read of ADC_OVER. 1: An overrun error has occurred on the corresponding channel since the last read of ADC_OVER. Note: An overrun error does not always mean that the unread data has been replaced by a new valid data. Refer to Section 48.6.10 “Enhanced Resolution Mode and Digital Averaging Function” for details.  2017 Microchip Technology Inc. DS60001525A-page 1527 SAMA5D4 SERIES 48.7.13 ADC Extended Mode Register Name:ADC_EMR Address:0xFC034040 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 23 – 22 – 21 – 20 ASTE 19 – 18 – 17 15 – 14 – 13 12 11 – 10 – 9 CMPALL 8 – 7 6 4 3 – 2 – 1 0 CMPFILTER 5 CMPSEL 24 TAG 16 OSR CMPMODE This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. CMPMODE: Comparison Mode Value Name Description 0 LOW When the converted data is lower than the low threshold of the window, generates the COMPE flag in ADC_ISR. 1 HIGH When the converted data is higher than the high threshold of the window, generates the COMPE flag in ADC_ISR. 2 IN When the converted data is in the comparison window, generates the COMPE flag in ADC_ISR. 3 OUT When the converted data is out of the comparison window, generates the COMPE flag in ADC_ISR. CMPSEL: Comparison Selected Channel If CMPALL = 0: CMPSEL indicates which channel has to be compared. If CMPALL = 1: No effect. CMPALL: Compare All Channels 0: Only channel indicated in CMPSEL field is compared. 1: All channels are compared. CMPFILTER: Compare Event Filtering Number of consecutive compare events necessary to raise the flag = CMPFILTER+1 When programmed to 0, the flag rises as soon as an event occurs. Refer to Section 48.6.8 “Comparison Window” when using filtering option (CMPFILTER > 0). OSR: Oversampling Rate Value Name Description 0 NO_AVERAGE No averaging. ADC sample rate is maximum. 1 OSR4 1-bit enhanced resolution by averaging. ADC sample rate divided by 4. 2 OSR16 2-bit enhanced resolution by averaging. ADC sample rate divided by 16. This field is active if LOWRES is cleared in the ADC Mode Register. DS60001525A-page 1528  2017 Microchip Technology Inc. SAMA5D4 SERIES ASTE: Averaging on Single Trigger Event Value Name Description 0 MULTI_TRIG_AVERAGE The average requests several trigger events. 1 SINGLE_TRIG_AVERAG E The average requests only one trigger event. TAG: Tag of ADC_LCDR 0: Sets CHNB field to zero in ADC_LCDR. 1: Appends the channel number to the conversion result in ADC_LCDR.  2017 Microchip Technology Inc. DS60001525A-page 1529 SAMA5D4 SERIES 48.7.14 ADC Compare Window Register Name:ADC_CWR Address:0xFC034044 Access:Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 HIGHTHRES 19 18 11 10 HIGHTHRES 15 – 14 – 13 – 12 – 7 6 5 4 LOWTHRES 3 2 LOWTHRES This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. LOWTHRES: Low Threshold Low threshold associated to compare settings of ADC_EMR. If LOWRES is set in ADC_MR, only the 10 LSB of LOWTHRES must be programmed. The two LSB will be automatically discarded to match the value carried on ADC_CDR (8-bit). HIGHTHRES: High Threshold High threshold associated to compare settings of ADC_EMR. If LOWRES is set in ADC_MR, only the 10 LSB of HIGHTHRES must be programmed. The two LSB will be automatically discarded to match the value carried on ADC_CDR (8-bit). DS60001525A-page 1530  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.7.15 ADC Channel Data Register Name:ADC_CDRx [x=0..4] Address:0xFC034050 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DATA 3 2 DATA DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. ADC_CDRx is only loaded if the corresponding analog channel is enabled.  2017 Microchip Technology Inc. DS60001525A-page 1531 SAMA5D4 SERIES 48.7.16 ADC Analog Control Register Name:ADC_ACR Address:0xFC034094 Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 0 PENDETSENS This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. PENDETSENS: Pen Detection Sensitivity Modifies the pen detection input pull-up resistor value. See the section ‘Electrical Characteristics’ for further details. DS60001525A-page 1532  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.7.17 ADC Touchscreen Mode Register Name:ADC_TSMR Address:0xFC0340B0 Access:Read/Write 31 30 29 28 27 – 26 – 18 PENDBC 23 – 22 NOTSDMA 21 – 20 – 19 15 – 14 – 13 – 12 – 11 7 – 6 – 5 4 3 – TSAV 25 – 24 PENDET 17 16 9 8 TSSCTIM 10 TSFREQ 2 – 1 0 TSMODE This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. TSMODE: Touchscreen Mode Value Name Description 0 NONE No Touchscreen 1 4_WIRE_NO_PM 4-wire Touchscreen without pressure measurement 2 4_WIRE 4-wire Touchscreen with pressure measurement 3 5_WIRE 5-wire Touchscreen When TSMOD equals 01 or 10 (i.e., 4-wire mode), channels 0, 1, 2 and 3 must not be used for classic ADC conversions. When TSMOD equals 11 (i.e., 5-wire mode), channels 0, 1, 2, 3, and 4 must not be used. TSAV: Touchscreen Average Value Name Description 0 NO_FILTER No Filtering. Only one ADC conversion per measure 1 AVG2CONV Averages 2 ADC conversions 2 AVG4CONV Averages 4 ADC conversions 3 AVG8CONV Averages 8 ADC conversions TSFREQ: Touchscreen Frequency Defines the touchscreen frequency compared to the trigger frequency. TSFREQ must be greater or equal to TSAV. The touchscreen frequency is: Touchscreen Frequency = Trigger Frequency / 2TSFREQ TSSCTIM: Touchscreen Switches Closure Time Defines closure time of analog switches necessary to establish the measurement conditions. The closure time is: Switch Closure Time = (TSSCTIM × 4) ADCCLK periods.  2017 Microchip Technology Inc. DS60001525A-page 1533 SAMA5D4 SERIES PENDET: Pen Contact Detection Enable 0: Pen contact detection disabled. 1: Pen contact detection enabled. When PENDET = 1, XPOS, YPOS, Z1, Z2 values of ADC_XPOSR, ADC_YPOSR, ADC_PRESSR are automatically cleared when PENS = 0 in ADC_ISR. NOTSDMA: No TouchScreen DMA 0: XPOS, YPOS, Z1, Z2 are transmitted in ADC_LCDR. 1: XPOS, YPOS, Z1, Z2 are never transmitted in ADC_LCDR, therefore the buffer does not contains touchscreen values. PENDBC: Pen Detect Debouncing Period Debouncing period = 2PENDBC ADCCLK periods. DS60001525A-page 1534  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.7.18 ADC Touchscreen X Position Register Name:ADC_XPOSR Address:0xFC0340B4 Access:Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 XSCALE 19 18 11 10 XSCALE 15 – 14 – 13 – 12 – 7 6 5 4 XPOS 3 2 XPOS XPOS: X Position The position measured is stored here. If XPOS = 0 or XPOS = XSIZE, the pen is on the border. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR), XPOS is tied to 0 while there is no detection of contact on the touchscreen (i.e., when PENS bit is cleared in ADC_ISR). XSCALE: Scale of XPOS Indicates the max value that XPOS can reach. This value should be close to 210.  2017 Microchip Technology Inc. DS60001525A-page 1535 SAMA5D4 SERIES 48.7.19 ADC Touchscreen Y Position Register Name:ADC_YPOSR Address:0xFC0340B8 Access:Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 YSCALE 19 18 11 10 YSCALE 15 – 14 – 13 – 12 – 7 6 5 4 YPOS 3 2 YPOS YPOS: Y Position The position measured is stored here. If YPOS = 0 or YPOS = YSIZE, the pen is on the border. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR), YPOS is tied to 0 while there is no detection of contact on the touchscreen (i.e., when PENS bit is cleared in ADC_ISR). YSCALE: Scale of YPOS Indicates the max value that YPOS can reach. This value should be close to 210. DS60001525A-page 1536  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.7.20 ADC Touchscreen Pressure Register Name:ADC_PRESSR Address:0xFC0340BC Access:Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 26 25 24 17 16 9 8 1 0 Z2 19 18 11 10 Z2 15 – 14 – 13 – 12 – 7 6 5 4 Z1 3 2 Z1 Z1: Data of Z1 Measurement Data Z1 necessary to calculate pen pressure. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR), Z1 is tied to 0 while there is no detection of contact on the touchscreen (i.e., when PENS bit is cleared in ADC_ISR). Z2: Data of Z2 Measurement Data Z2 necessary to calculate pen pressure. When pen detection is enabled (PENDET set to ‘1’ in ADC_TSMR), Z2 is tied to 0 while there is no detection of contact on the touchscreen (i.e., when PENS bit is cleared in ADC_ISR). Note: These two values are unavailable if TSMODE is not set to 2 in ADC_TSMR.  2017 Microchip Technology Inc. DS60001525A-page 1537 SAMA5D4 SERIES 48.7.21 ADC Trigger Register Name:ADC_TRGR Address:0xFC0340C0 Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 TRGPER 23 22 21 20 TRGPER 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 0 – – – – – 1 TRGMOD This register can only be written if the WPEN bit is cleared in the ADC Write Protection Mode Register. TRGMOD: Trigger Mode Value Name Description 0 NO_TRIGGER No trigger, only software trigger can start conversions 1 EXT_TRIG_RISE External trigger rising edge 2 EXT_TRIG_FALL External trigger falling edge 3 EXT_TRIG_ANY External trigger any edge 4 PEN_TRIG Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touchscreen only mode) 5 PERIOD_TRIG ADC internal periodic trigger (see field TRGPER) 6 CONTINUOUS Continuous Mode TRGPER: Trigger Period Effective only if TRGMOD defines a periodic trigger. Defines the periodic trigger period, with the following equation: Trigger Period = (TRGPER + 1) / ADCCLK The minimum time between two consecutive trigger events must be strictly greater than the duration time of the longest conversion sequence depending on the configuration of registers ADC_MR, ADC_CHSR, ADC_SEQRx, ADC_TSMR. When TRGMOD is set to pen detect trigger (i.e., 100) and averaging is used (i.e., field TSAV ≠ 0 in ADC_TSMR) only one measure is performed. Thus, XRDY, YRDY, PRDY, DRDY will not rise on pen contact trigger. To achieve measurement, several triggers must be provided either by software or by setting the TRGMOD on continuous trigger (i.e., 110) until flags rise. DS60001525A-page 1538  2017 Microchip Technology Inc. SAMA5D4 SERIES 48.7.22 ADC Write Protection Mode Register Name:ADC_WPMR Address:0xFC0340E4 Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPEN WPKEY 23 22 21 20 WPKEY 15 14 13 12 WPKEY 7 – 6 – 5 – 4 – WPEN: Write Protection Enable 0: Disables the write protection if WPKEY value corresponds to 0x414443 (“ADC” in ASCII). 1: Enables the write protection if WPKEY value corresponds to 0x414443 (“ADC” in ASCII). See Section 48.6.14 “Register Write Protection” for the list of write-protected registers. WPKEY: Write Protection Key Value 0x414443 Name PASSWD Description Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0  2017 Microchip Technology Inc. DS60001525A-page 1539 SAMA5D4 SERIES 48.7.23 ADC Write Protection Status Register Name:ADC_WPSR Address:0xFC0340E8 Access:Read-only 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 – 2 – 1 – 0 WPVS WPVSRC 15 14 13 12 WPVSRC 7 – 6 – 5 – 4 – WPVS: Write Protection Violation Status 0: No write protection violation has occurred since the last read of ADC_WPSR. 1: A write protection violation has occurred since the last read of ADC_WPSR. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. WPVSRC: Write Protection Violation Source When WPVS = 1, WPVSRC indicates the register address offset at which a write access has been attempted. DS60001525A-page 1540  2017 Microchip Technology Inc. SAMA5D4 SERIES 49. True Random Number Generator (TRNG) 49.1 Description The True Random Number Generator (TRNG) passes the American NIST Special Publication 800-22 (A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications) and the Diehard Suite of Tests. The TRNG may be used as an entropy source for seeding an NIST approved DRNG (Deterministic RNG) as required by FIPS PUB 1402 and 140-3. 49.2 Embedded Characteristics • Passes NIST Special Publication 800-22 Test Suite • Passes Diehard Suite of Tests • May be Used as Entropy Source for Seeding a NIST-approved DRNG (Deterministic RNG) as required by FIPS PUB 140-2 and 1403 • Provides a 32-bit Random Number Every 84 Clock Cycles 49.3 Block Diagram Figure 49-1: TRNG Block Diagram TRNG Interrupt Controller Control Logic MCK User Interface PMC Entropy Source APB 49.4 Product Dependencies 49.4.1 Power Management The TRNG interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TRNG user interface clock. The user interface clock is independent from any clock that may be used in the entropy source logic circuitry. The source of entropy can be enabled before enabling the user interface clock. 49.4.2 Interrupt Sources The TRNG interface has an interrupt line connected to the Interrupt Controller. In order to handle interrupts, the Interrupt Controller must be programmed before configuring the TRNG. Table 49-1: 49.5 Peripheral IDs Instance ID TRNG 53 Functional Description As soon as the TRNG is enabled in the Control register (TRNG_CR), the generator provides one 32-bit value every 84 clock cycles. The TRNG interrupt line can be enabled in the Interrupt Enable register (TRNG_IER), and disabled in the Interrupt Disable register (TRNG_IDR). This interrupt is set when a new random value is available and is cleared when the Status register (TRNG_ISR) is read. The flag TRNG_ISR.DATRDY is set when the random data is ready to be read out on the 32-bit Output Data register (TRNG_ODATA). The normal mode of operation checks that the flag in TRNG_ISR equals ‘1’ before reading TRNG_ODATA when a 32-bit random value is required by the software application.  2017 Microchip Technology Inc. DS60001525A-page 1541 SAMA5D4 SERIES Figure 49-2: TRNG Data Generation Sequence Clock TRNG_CR.ENABLE = 1 84 clock cycles 84 clock cycles 84 clock cycles TRNG Interrupt Line Read TRNG_ISR Read TRNG_ODATA DS60001525A-page 1542 Read TRNG_ISR Read TRNG_ODATA  2017 Microchip Technology Inc. SAMA5D4 SERIES 49.6 True Random Number Generator (TRNG) User Interface Table 49-2: Register Mapping Offset 0x00 Register Name Access Reset Write-only – – – Control Register TRNG_CR Reserved – 0x10 Interrupt Enable Register TRNG_IER Write-only – 0x14 Interrupt Disable Register TRNG_IDR Write-only – 0x18 Interrupt Mask Register TRNG_IMR Read-only 0x0000_0000 0x1C Interrupt Status Register TRNG_ISR Read-only 0x0000_0000 Reserved – – – Output Data Register TRNG_ODATA Read-only 0x0000_0000 0x54–0xE0 Reserved – – – 0xE4 Reserved – – – 0xE8–0xFC Reserved – – – 0x04–0x0C 0x20–0x4C 0x50  2017 Microchip Technology Inc. DS60001525A-page 1543 SAMA5D4 SERIES 49.6.1 TRNG Control Register Name:TRNG_CR Address:0xFC030000 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 KEY 23 22 21 20 KEY 15 14 13 12 KEY 7 6 5 4 3 2 1 0 – – – – – – – ENABLE ENABLE: Enables the TRNG to Provide Random Values 0: Disables the TRNG. 1: Enables the TRNG if 0x524E47 (“RNG” in ASCII) is written in KEY field at the same time. KEY: Security Key Value 0x524E47 Name Description PASSWD Writing any other value in this field aborts the write operation. DS60001525A-page 1544  2017 Microchip Technology Inc. SAMA5D4 SERIES 49.6.2 TRNG Interrupt Enable Register Name: TRNG_IER Address:0xFC030010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.  2017 Microchip Technology Inc. DS60001525A-page 1545 SAMA5D4 SERIES 49.6.3 TRNG Interrupt Disable Register Name: TRNG_IDR Address:0xFC030014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt. DS60001525A-page 1546  2017 Microchip Technology Inc. SAMA5D4 SERIES 49.6.4 TRNG Interrupt Mask Register Name: TRNG_IMR Address:0xFC030018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled.  2017 Microchip Technology Inc. DS60001525A-page 1547 SAMA5D4 SERIES 49.6.5 TRNG Interrupt Status Register Name: TRNG_ISR Address:0xFC03001C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready 0: Output data is not valid or TRNG is disabled. 1: New random value is completed. DATRDY is cleared when this register is read. DS60001525A-page 1548  2017 Microchip Technology Inc. SAMA5D4 SERIES 49.6.6 TRNG Output Data Register Name: TRNG_ODATA Address:0xFC030050 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA ODATA: Output Data The 32-bit Output Data register contains the 32-bit random data.  2017 Microchip Technology Inc. DS60001525A-page 1549 SAMA5D4 SERIES 50. Advanced Encryption Standard (AES) 50.1 Description The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 197 specification. The AES supports all five confidentiality modes of operation for symmetrical key block cipher algorithms (ECB, CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 800-38A Recommendation, as well as Galois/Counter Mode (GCM) as specified in the NIST Special Publication 800-38D Recommendation. It is compatible with all these modes via DMA Controller channels, minimizing processor intervention for large buffer transfers. The 128-bit/192-bit/256-bit key is stored in four/six/eight 32-bit write-only AES Key Word registers (AES_KEYWR0–7). The 128-bit input data and initialization vector (for some modes) are each stored in four 32-bit write-only AES Input Data registers (AES_IDATAR0–3) and AES Initialization Vector registers (AES_IVR0–3). As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process may be started. Then the encrypted/decrypted data are ready to be read out on the four 32-bit AES Output Data registers (AES_ODATAR0–3) or through the DMA channels. 50.2 Embedded Characteristics • • • • • Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) 128-bit/192-bit/256-bit Cryptographic Key 10/12/14 Clock Cycles Encryption/Decryption Inherent Processing Time with a 128-bit/192-bit/256-bit Cryptographic Key Double Input Buffer Optimizes Runtime Support of the Modes of Operation Specified in the NIST Special Publication 800-38A and NIST Special Publication 800-38D: - Electronic Codebook (ECB) - Cipher Block Chaining (CBC) including CBC-MAC - Cipher Feedback (CFB) - Output Feedback (OFB) - Counter (CTR) - Galois/Counter Mode (GCM) • 8, 16, 32, 64 and 128-bit Data Sizes Possible in CFB Mode • Last Output Data Mode Allows Optimized Message Authentication Code (MAC) Generation • Connection to DMA Optimizes Data Transfers for all Operating Modes 50.3 Product Dependencies 50.3.1 Power Management The AES may be clocked through the Power Management Controller (PMC), so the programmer must first to configure the PMC to enable the AES clock. 50.3.2 Interrupt Sources The AES interface has an interrupt line connected to the Interrupt Controller. Handling the AES interrupt requires programming the Interrupt Controller before configuring the AES. Table 50-1: Peripheral IDs Instance ID AES 12 DS60001525A-page 1550  2017 Microchip Technology Inc. SAMA5D4 SERIES 50.4 Functional Description The Advanced Encryption Standard (AES) specifies a FIPS-approved cryptographic algorithm that can be used to protect electronic data. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information. Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext converts the data back into its original form, called plaintext. The CIPHER bit in the AES Mode register (AES_MR) allows selection between the encryption and the decryption processes. The AES is capable of using cryptographic keys of 128/192/256 bits to encrypt and decrypt data in blocks of 128 bits. This 128-bit/192bit/256-bit key is defined in AES_KEYWRx. The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to the plaintext, a 128-bit data block called the initialization vector (IV), which must be set in AES_IVRx. The initialization vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message. AES_IVRx are also used by the CTR mode to set the counter value. 50.4.1 AES Register Endianness In Arm processor-based products, the system bus and processors manipulate data in little-endian form. The AES interface requires littleendian format words. However, in accordance with the protocol of the FIPS 197 specification, data is collected, processed and stored by the AES algorithm in big-endian form. The following example illustrates how to configure the AES: If the first 64 bits of a message (according to FIPS 197, i.e., big-endian format) to be processed is 0xcafedeca_01234567, then AES_IDATAR0 and AES_IDATAR1 registers must be written with the following pattern: • AES_IDATAR0 = 0xcadefeca • AES_IDATAR1 = 0x67452301 50.4.2 Operating Modes The AES supports the following modes of operation: • • • • ECB: Electronic Codebook CBC: Cipher Block Chaining OFB: Output Feedback CFB: Cipher Feedback - CFB8 (CFB where the length of the data segment is 8 bits) - CFB16 (CFB where the length of the data segment is 16 bits) - CFB32 (CFB where the length of the data segment is 32 bits) - CFB64 (CFB where the length of the data segment is 64 bits) - CFB128 (CFB where the length of the data segment is 128 bits) • CTR: Counter • GCM: Galois/Counter Mode The data preprocessing, data postprocessing and data chaining for the concerned modes are performed automatically. Refer to the NIST Special Publication 800-38A and NIST Special Publication 800-38D for more complete information. Mode selection is done by configuring the OPMOD field in AES_MR. In CFB mode, five data sizes are possible (8, 16, 32, 64 or 128 bits), configurable by means of the CFBS field in AES_MR (Section 50.5.2 “AES Mode Register”). In CTR mode, the size of the block counter embedded in the module is 16 bits. Therefore, there is a rollover after processing 1 Mbyte of data. If the file to be processed is greater than 1 Mbyte, this file must be split into fragments of 1 Mbyte or less for the first fragment if the initial value of the counter is greater than 0. Prior to loading the first fragment into AES_IDATARx, AES_IVRx must be fully programmed with the initial counter value. For any fragment, after the transfer is completed and prior to transferring the next fragment, AES_IVRx must be programmed with the appropriate counter value. 50.4.3 Double Input Buffer AES_IDATARx can be double-buffered to reduce the runtime of large files. This mode allows a new message block to be written when the previous message block is being processed. This is only possible when DMA accesses are performed (SMOD = 2). The DUALBUFF bit in AES_MR must be set to ‘1’ to access the double buffer.  2017 Microchip Technology Inc. DS60001525A-page 1551 SAMA5D4 SERIES 50.4.4 Start Modes The SMOD field in AES_MR allows selection of the encryption (or decryption) Start mode. 50.4.4.1 Manual Mode The sequence of actions is as follows: 1. 2. 3. Write AES_MR with all required fields, including but not limited to SMOD and OPMOD. Write the 128-bit/192-bit/256-bit key in AES_KEYWRx. Write the initialization vector (or counter) in AES_IVRx. Note: 4. 5. 6. 7. 8. AES_IVRx concerns all modes except ECB. Set the bit DATRDY (Data Ready) in the AES Interrupt Enable register (AES_IER), depending on whether an interrupt is required or not at the end of processing. Write the data to be encrypted/decrypted in the authorized AES_IDATARx (refer to Table 50-2). Set the START bit in the AES Control register (AES_CR) to begin the encryption or the decryption process. When processing completes, the DATRDY flag in the AES Interrupt Status register (AES_ISR) is raised. If an interrupt has been enabled by setting the DATRDY bit in AES_IER, the interrupt line of the AES is activated. When software reads one of AES_ODATARx, the DATRDY bit is automatically cleared. Table 50-2: Authorized Input Data Registers Operating Mode Input Data Registers to Write ECB All CBC All OFB All 128-bit CFB All 64-bit CFB AES_IDATAR0 and AES_IDATAR1 32-bit CFB AES_IDATAR0 16-bit CFB AES_IDATAR0 8-bit CFB AES_IDATAR0 CTR All GCM All Note 1: In 64-bit CFB mode, writing to AES_IDATAR2 and AES_IDATAR3 is not allowed and may lead to errors in processing. 2: In 32, 16, and 8-bit CFB modes, writing to AES_IDATAR1, AES_IDATAR2 and AES_IDATAR3 is not allowed and may lead to errors in processing. 50.4.4.2 Auto Mode The Auto Mode is similar to the manual one, except that in this mode, as soon as the correct number of AES_IDATARx is written, processing is automatically started without any action in AES_CR. 50.4.4.3 DMA Mode The DMA Controller can be used in association with the AES to perform an encryption/decryption of a buffer without any action by software during processing. The SMOD field in AES_MR must be configured to 2 and the DMA must be configured with non-incremental addresses. The start address of any transfer descriptor must be configured with the address of AES_IDATAR0. The DMA chunk size configuration depends on the AES mode of operation and is listed in Table 50-3. DS60001525A-page 1552  2017 Microchip Technology Inc. SAMA5D4 SERIES When writing data to AES with a first DMA channel, data are first fetched from a memory buffer (source data). It is recommended to configure the size of source data to “words” even for CFB modes. On the contrary, the destination data size depends on the mode of operation. When reading data from the AES with the second DMA channel, the source data is the data read from AES and data destination is the memory buffer. In this case, the source data size depends on the AES mode of operation and is listed in Table 50-3. Table 50-3: DMA Data Transfer Type for the Different Operating Modes Operating Mode Chunk Size Destination/Source Data Transfer Type ECB 4 Word CBC 4 Word OFB 4 Word CFB 128-bit 4 Word CFB 64-bit 1 Word CFB 32-bit 1 Word CFB 16-bit 1 Half-word CFB 8-bit 1 Byte CTR 4 Word GCM 4 Word 50.4.5 Last Output Data Mode This mode is used to generate cryptographic checksums on data (MAC) by means of cipher block chaining encryption algorithm (CBCMAC algorithm for example). After each end of encryption/decryption, the output data are available either on AES_ODATARx for Manual and Auto mode, or at the address specified in the receive buffer pointer for DMA mode (refer to Table 50-4). The Last Output Data (LOD) bit in AES_MR allows retrieval of only the last data of several encryption/decryption processes. Therefore, there is no need to define a read buffer in DMA mode. This data are only available in AES_ODATARx. 50.4.5.1 Manual and Auto Modes • If AES_MR.LOD = 0 The DATRDY flag is cleared when at least one AES_ODATARx is read (refer to Figure 50-1). Figure 50-1: Manual and Auto Modes with AES_MR.LOD = 0 Write START bit in AES_CR (Manual mode) or Write AES_IDATARx (Auto mode) Read AES_ODATARx DATRDY Encryption or Decryption Process If the user does not want to read AES_ODATARx between each encryption/decryption, the DATRDY flag will not be cleared. If the DATRDY flag is not cleared, the user cannot know the end of the following encryptions/decryptions. • If AES_MR.LOD = 1 This mode is optimized to process AES CPC-MAC operating mode.  2017 Microchip Technology Inc. DS60001525A-page 1553 SAMA5D4 SERIES The DATRDY flag is cleared when at least one AES_IDATAR is written (refer to Figure 50-2). No additional AES_ODATAR reads are necessary between consecutive encryptions/decryptions. Figure 50-2: Manual and Auto Modes with AES_MR.LOD = 1 Write START bit in AES_CR (Manual mode) or Write AES_IDATARx (Auto mode) Write AES_IDATARx DATRDY Encryption or Decryption Process 50.4.5.2 DMA Mode • If AES_MR.LOD = 0 This mode may be used for all AES operating modes except CBC-MAC where AES_MR.LOD = 1 mode is recommended. The end of the encryption/decryption is indicated by the end of DMA transfer associated to AES_ODATARx (refer to Figure 50-3). Two DMA channels are required: one for writing message blocks to AES_IDATARx and one to obtain the result from AES_ODATARx. Figure 50-3: DMA Transfer with AES_MR.LOD = 0 Enable DMA Channels associated to AES_IDATARx and AES_ODATARx Multiple Encryption or Decryption Processes DMA Buffer transfer complete flag /channel m DMA Buffer transfer complete flag /channel n Write accesses into AES_IDATARx Read accesses into AES_ODATARx Message fully processed (cipher or decipher) last block can be read • If AES_MR.LOD = 1 This mode is optimized to process AES CBC-MAC operating mode. The user must first wait for the DMA buffer transfer complete flag, then for the flag DATRDY to rise to ensure that the encryption/decryption is completed (refer to Figure 50-4). In this case, no receive buffers are required. The output data are only available on AES_ODATARx. DS60001525A-page 1554  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 50-4: DMA Transfer with AES_MR.LOD = 1 Enable DMA Channels associated with AES_IDATARx and AES_ODATARx registers Multiple Encryption or Decryption Processes DMA status flag for end of buffer transfer Write accesses into AES_IDATARx DATRDY Message fully processed (cipher or decipher) MAC result can be read Message fully transferred Table 50-4 summarizes the different cases. Table 50-4: Last Output Data Mode Behavior versus Start Modes Manual and Auto Modes Sequence AES_MR.LOD = 0 DATRDY Flag Clearing Condition(1) At least one AES_ODATAR must be read At least one AES_IDATAR must be written Not used Managed by the DMA DATRDY DATRDY 2 DMA Buffer transfer complete flags (channel m and channel n) DMA buffer transfer complete flag, then AES DATRDY flag In AES_ODATARx In AES_ODATARx At the address specified in the Channel Buffer Transfer Descriptor In AES_ODATARx End of Encryption/ Decryption Notification Encrypted/Decrypted Data Result Location AES_MR.LOD = 1 DMA Transfer AES_MR.LOD = 0 AES_MR.LOD = 1 Note 1: Depending on the mode, there are other ways of clearing the DATRDY flag. Refer to Section 50.5.6 “AES Interrupt Status Register”. Warning: In DMA mode, reading AES_ODATARx before the last data transfer may lead to unpredictable results. 50.4.6 50.4.6.1 Galois/Counter Mode (GCM) Description GCM comprises the AES engine in CTR mode along with a universal hash function (GHASH engine) that is defined over a binary Galois field to produce a message authentication tag (the AES CTR engine and the GHASH engine are depicted in Figure 50-5). The GHASH engine processes data packets after the AES operation. GCM assures the confidentiality of data through the AES Counter mode of operation for encryption. Authenticity of the confidential data is assured through the GHASH engine. GCM can also provide assurance of data that is not encrypted. Refer to the NIST Special Publication 800-38D for more complete information. GCM can be used with or without the DMA master. Messages may be processed as a single complete packet of data or they may be broken into multiple packets of data over time. GCM processing is computed on 128-bit input data fields. There is no support for unaligned data. The AES key length can be whatever length is supported by the AES module. The recommended programming procedure when using DMA is described in Section 50.4.6.3 “GCM Processing”.  2017 Microchip Technology Inc. DS60001525A-page 1555 SAMA5D4 SERIES Figure 50-5: GCM Block Diagram AES CTR Engine (AES_IVRx) (AES_CTRR) Counter 0 Incr32 Counter 1 (AES_CTRR) Incr32 Counter N (AES_KEYWRx) Cipher(Key) Cipher(Key) (AES_IDATARx) Cipher(Key) (AES_IDATARx) Plaintext N Plaintext 1 Ciphertext 1 (AES_IDATARx) AAD 1 Ciphertext N (AES_IDATARx) AAD N (AES_GHASHRx) (AES_GHASHRx) (AES_GHASHRx) GF128Mult(H) GF128Mult(H) (AES_GCMHRx)(1) (AES_AADLENR, AES_CLENR) GF128Mult(H) GF128Mult(H) len(AAD) || len(C) GF128Mult(H) (AES_TAGRx) GHASH Engine Auth Tag(T) Note: 1. Optional 50.4.6.2 Key Writing and Automatic Hash Subkey Calculation Whenever a new key (AES_KEYWRx) is written to the hardware, two automatic actions are processed: • GCM Hash Subkey H generation—The GCM hash subkey (H) is automatically generated. The GCM hash subkey generation must be complete before doing any other action. The DATRDY bit of AES_ISR indicates when the subkey generation is complete (with interrupt if configured). The GCM hash subkey calculation is processed with the formula H = CIPHER(Key, ). The generated GCM H value is then available in AES_GCMHRx. If the application software requires a specific hash subkey, the automatically generated H value can be overwritten in AES_GCMHRx. AES_GCMHRx can be written after the end of the hash subkey generation (refer to AES_ISR.DATRDY) and prior to starting the input data feed. • AES_GHASHRx Clear—AES_GHASHRx are automatically cleared. If a hash initial value is needed for the GHASH, it must be written to AES_GHASHRx - after a write to AES_KEYWRx, if any - before starting the input data feed DS60001525A-page 1556  2017 Microchip Technology Inc. SAMA5D4 SERIES 50.4.6.3 GCM Processing GCM processing is made up of three phases: 1. 2. 3. Processing the Additional Authenticated Data (AAD), hash computation only. Processing the Ciphertext (C), hash computation + ciphering/deciphering. Generating the Tag using length of AAD, length of C and J0 (refer to NIST documentation for details). The Tag generation can be done either automatically, after the end of AAD/C processing if GTAGEN is set in AES_MR, or done manually using the GHASH field in AES_GHASHRx (Refer to subsections Processing a Complete Message with Tag Generation and Manual GCM Tag Generation for details). • Processing a Complete Message with Tag Generation Use this procedure only if J0 four LSB bytes ≠ 0xFFFFFFFF. NOTE: If J0 four LSB bytes = 0xFFFFFFFF or if the value is unknown, use the procedure described in Processing a Complete Message without Tag Generation followed by the procedure in Manual GCM Tag Generation. Figure 50-6: Full Message Alignment 16-byte Boundaries C (Text) AAD Padding AADLEN Padding CLEN To process a complete message with Tag generation, the sequence is as follows: 1. 2. In AES_MR, set OPMOD to GCM and GTAGEN to ‘1’. Set KEYW in AES_KEYWRx and wait until AES_ISR.DATRDY is set (GCM hash subkey generation complete); use interrupt if needed. Refer to Section 50.4.6.2 “Key Writing and Automatic Hash Subkey Calculation”. 3. Calculate the J0 value as described in NIST documentation J0 = IV || 031 || 1 when len(IV) = 96 and J0 = GHASHH(IV || 0s+64 || [len(IV)]64) if len(IV) ≠ 96. Refer to Processing a Message with only AAD (GHASHH) for J0 generation. 4. Set IV in AES_IVRx with inc32(J0) (J0 + 1 on 32 bits). 5. Set AADLEN field in AES_AADLENR and CLEN field in AES_CLENR. 6. Fill the IDATA field of AES_IDATARx with the message to process according to the SMOD configuration used. If Manual Mode or Auto Mode is used, the DATRDY bit indicates when the data have been processed (however, no output data are generated when processing AAD). 7. Wait for TAGRDY to be set (use interrupt if needed), then read the TAG field of AES_TAGRx to obtain the authentication tag of the message. • Processing a Complete Message without Tag Generation Processing a message without generating the Tag can be used to customize the Tag generation, or to process a fragmented message. To manually generate the GCM Tag, refer to Manual GCM Tag Generation. To process a complete message without Tag generation, the sequence is as follows: 1. 2. 3. 4. 5. 6. In AES_MR, set OPMOD to GCM and GTAGEN to ‘0’. Set KEYW in AES_KEYWRx and wait until DATRDY bit of AES_ISR is set (GCM hash subkey generation complete); use interrupt if needed. After the GCM hash subkey generation is complete the GCM hash subkey can be read or overwritten with specific value in AES_GCMHRx. Refer to Section 50.4.6.2 “Key Writing and Automatic Hash Subkey Calculation”. Calculate the J0 value as described in NIST documentation J0 = IV || 031 || 1 when len(IV) = 96 and J0 = GHASHH(IV || 0s+64 || [len(IV)]64) if len(IV) ≠ 96. Refer to Processing a Message with only AAD (GHASHH) for J0 generation example when len(IV) ≠ 96. Set IV in AES_IVRx with inc32(J0) (J0 + 1 on 32 bits). Set AADLEN field in AES_AADLENR and CLEN field in AES_CLENR. Fill the IDATA field of AES_IDATARx with the message to process according to the SMOD configuration used. If Manual Mode or Auto Mode is used, the DATRDY bit indicates when the data have been processed (however, no output data are generated when processing AAD).  2017 Microchip Technology Inc. DS60001525A-page 1557 SAMA5D4 SERIES Make sure the last output data have been read if CLEN ≠ 0 (or wait for DATRDY), then read the GHASH field of AES_GHASHRx to obtain the hash value after the last processed data. • Processing a Fragmented Message without Tag Generation 7. If needed, a message can be processed by fragments, in such case automatic GCM Tag generation is not supported. To process a message by fragments, the sequence is as follows: • First fragment: 1. In AES_MR set OPMOD to GCM and GTAGEN to ‘0’. 2. Set KEYW in AES_KEYWRx and wait for DATRDY bit of AES_ISR to be set (GCM hash subkey generation complete); use interrupt if needed. After the GCM hash subkey generation is complete the GCM hash subkey can be read or overwritten with specific value in AES_GCMHRx. Refer to Section 50.4.6.2 “Key Writing and Automatic Hash Subkey Calculation”. 3. Calculate the J0 value as described in NIST documentation J0 = IV || 031 || 1 when len(IV) = 96 and J0 = GHASHH(IV || 0s+64 || [len(IV)]64) if len(IV) ≠ 96. Refer to Processing a Message with only AAD (GHASHH) for J0 generation example when len(IV) ≠ 96. 4. Set IV in AES_IVRx with inc32(J0) (J0 + 1 on 32 bits). 5. Set AADLEN field in AES_AADLENR and CLEN field in AES_CLENR according to the length of the first fragment, or set the fields with the full message length, both configurations work. 6. Fill the IDATA field of AES_IDATARx with the first fragment of the message to process (aligned on 16-byte boundary) according to the SMOD configuration used. If Manual Mode or Auto Mode is used the DATRDY bit indicates when the data have been processed (however, no output data are generated when processing AAD). 7. Make sure the last output data have been read if the fragment ends in C phase (or wait for DATRDY if the fragment ends in AAD phase), then read the GHASH field of AES_GHASHRx to obtain the value of the hash after the last processed data and finally read the CTR field of AES_CTR to obtain the value of the CTR encryption counter (not needed when the fragment ends in AAD phase). • Next fragment (or last fragment): 1. In AES_MR set OPMOD to GCM and GTAGEN to ‘0’. 2. Set KEYW in AES_KEYWRx and wait until DATRDY bit of AES_ISR is set (GCM hash subkey generation complete); use interrupt if needed. After the GCM hash subkey generation is complete the GCM hash subkey can be read or overwritten with specific value in AES_GCMHRx. Refer to Section 50.4.6.2 “Key Writing and Automatic Hash Subkey Calculation”. 3. Set IV in AES_IVRx with: - If the first block of the fragment is a block of Additional Authenticated data, set IV in AES_IVRx with the J0 initial value - If the first block of the fragment is a block of Plaintext data, set IV in AES_IVRx with a value constructed as follows: ‘LSB96(J0) || CTR’ value, (96 bit LSB of J0 concatenated with saved CTR value from previous fragment). 4. Set AADLEN field in AES_AADLENR and CLEN field in AES_CLENR according to the length of the current fragment, or set the fields with the remaining message length, both configurations work. 5. Fill the GHASH field of AES_GHASHRx with the value stored after the previous fragment. 6. Fill the IDATA field of AES_IDATARx with the current fragment of the message to process (aligned on 16 byte boundary) according to the SMOD configuration used. If Manual Mode or Auto Mode is used, the DATRDY bit indicates when the data have been processed (however, no output data are generated when processing AAD). 7. Make sure the last output data have been read if the fragment ends in C phase (or wait for DATRDY if the fragment ends in AAD phase), then read the GHASH field of AES_GHASHRx to obtain the value of the hash after the last processed data and finally read the CTR field of AES_CTR to obtain the value of the CTR encryption counter (not needed when the fragment ends in AAD phase). Note: Step 1 and 2 are required only if the value of the concerned registers has been modified. Once the last fragment has been processed, the GHASH value will allow manual generation of the GCM tag. Refer to Manual GCM Tag Generation. • Manual GCM Tag Generation This section describes the last steps of the GCM Tag generation. The Manual GCM Tag Generation is used to complete the GCM Tag Generation when the message has been processed without Tag Generation. Note: The Message Processing without Tag Generation must be finished before processing the Manual GCM Tag Generation. To generate a GCM Tag manually, the sequence is as follows: Processing S = GHASHH (AAD || 0v || C || 0u || [len(AAD)]64 || [len(C)]64): 1. 2. In AES_MR set OPMOD to GCM and GTAGEN to ‘0’. Set KEYW in AES_KEYWRx and wait for DATRDY bit of AES_ISR to be set (GCM hash subkey generation complete); use interrupt if needed. After the GCM hash subkey generation is complete the GCM hash subkey can be read or overwritten with specific value DS60001525A-page 1558  2017 Microchip Technology Inc. SAMA5D4 SERIES in AES_GCMHRx. Refer to Section 50.4.6.2 “Key Writing and Automatic Hash Subkey Calculation”. Set AADLEN field to 0x10 (16 bytes) in AES_AADLENR and CLEN field to ‘0’ in AES_CLENR. This will allow running a single GHASHH on a 16-byte input data (refer to Figure 50-7). Fill the GHASH field of AES_GHASHRx with the state of the GHASH field stored at the end of the message processing. Fill the IDATA field of AES_IDATARx according to the SMOD configuration used with ‘len(AAD)64 || len(C)64’ value as described in the NIST documentation and wait for DATRDY to be set; use interrupt if needed. Read the GHASH field of AES_GHASHRx to obtain the current value of the hash. 3. 4. 5. 6. Processing T = GCTRK(J0, S): 7. 8. 9. 10. In AES_MR, set OPMOD to CTR. Set the IV field in AES_IVRx with ‘J0’ value. Fill the IDATA field of AES_IDATARx with the GHASH value read at step 6 and wait for DATRDY to be set (use interrupt if needed). Read the ODATA field of AES_ODATARx to obtain the GCM Tag value. Note: Step 4 is optional if the GHASH field is to be filled with value ‘0’ (0 length packet for instance). • Processing a Message with only AAD (GHASHH) Figure 50-7: Single GHASHH Block Diagram (AADLEN ≤ 0x10 and CLEN = 0) GHASH IDATA GF128Mult(H) GHASH It is possible to process a message with only AAD setting the CLEN field to ‘0’ in AES_CLENR, this can be used for J0 generation when len(IV) ≠ 96 for instance. Example: Processing J0 when len(IV) ≠ 96 To process J0 = GHASHH(IV || 0s+64 || [len(IV)]64), the sequence is as follows: 1. 2. 3. 4. 5. In AES_MR, set OPMOD to GCM and GTAGEN to ‘0’. Set KEYW in AES_KEYWRx and wait until DATRDY bit of AES_ISR is set (GCM hash subkey generation complete); use interrupt if needed. After the GCM hash subkey generation is complete the GCM hash subkey can be read or overwritten with specific value in AES_GCMHRx. Refer to Section 50.4.6.2 “Key Writing and Automatic Hash Subkey Calculation”. Set AADLEN field with ‘len(IV || 0s+64 || [len(IV)]64)’ in AES_AADLENR and CLEN field to ‘0’ in AES_CLENR. This will allow running a GHASHH only. Fill the IDATA field of AES_IDATARx with the message to process (IV || 0s+64 || [len(IV)]64) according to the SMOD configuration used. If Manual Mode or Auto Mode is used, the DATRDY bit indicates when a GHASHH step is over (use interrupt if needed). Read the GHASH field of AES_GHASHRx to obtain the J0 value. Note: The GHASH value can be overwritten at any time by writing the GHASH field value of AES_GHASHRx, used to perform a GHASHH with an initial value for GHASH (write GHASH field between step 3 and step 4 in this case). • Processing a Single GF128 Multiplication The AES can also be used to process a single multiplication in the Galois field on 128 bits (GF128) using a single GHASHH with custom H value (refer to Figure 50-7). To run a GF128 multiplication (A x B), the sequence is as follows: 1. 2. 3. In AES_MR, set OPMOD to GCM and GTAGEN to ‘0’. Set AADLEN field with 0x10 (16 bytes) in AES_AADLENR and CLEN field to ‘0’ in AES_CLENR. This will allow running a single GHASHH. Fill the H field of AES_GCMHRx with B value.  2017 Microchip Technology Inc. DS60001525A-page 1559 SAMA5D4 SERIES 4. 5. Fill the IDATA field of AES_IDATARx with the A value according to the SMOD configuration used. If Manual Mode or Auto Mode is used, the DATRDY bit indicates when a GHASHH computation is over (use interrupt if needed). Read the GHASH field of AES_GHASHRx to obtain the result. Note: 50.4.7 50.4.7.1 The GHASH field of AES_GHASHRx can be initialized with a value C between step 3 and step 4 to run a ((A XOR C) x B) GF128 multiplication. Security Features Unspecified Register Access Detection When an unspecified register access occurs, the URAD flag in AES_ISR is raised. Its source is then reported in the Unspecified Register Access Type (URAT) field. Only the last unspecified register access is available through the URAT field. Several kinds of unspecified register accesses can occur: • • • • • • Input Data register written during the data processing when SMOD = IDATAR0_START Output Data register read during data processing Mode register written during data processing Output Data register read during sub-keys generation Mode register written during sub-keys generation Write-only register read access The URAD bit and the URAT field can only be reset by the SWRST bit in AES_CR. DS60001525A-page 1560  2017 Microchip Technology Inc. SAMA5D4 SERIES 50.5 Advanced Encryption Standard (AES) User Interface Table 50-5: Offset Register Mapping Register Name Access Reset 0x00 Control Register AES_CR Write-only – 0x04 Mode Register AES_MR Read/Write 0x0 Reserved – – – 0x10 Interrupt Enable Register AES_IER Write-only – 0x14 Interrupt Disable Register AES_IDR Write-only – 0x18 Interrupt Mask Register AES_IMR Read-only 0x0 0x1C Interrupt Status Register AES_ISR Read-only 0x0 0x20 Key Word Register 0 AES_KEYWR0 Write-only – 0x24 Key Word Register 1 AES_KEYWR1 Write-only – 0x28 Key Word Register 2 AES_KEYWR2 Write-only – 0x2C Key Word Register 3 AES_KEYWR3 Write-only – 0x30 Key Word Register 4 AES_KEYWR4 Write-only – 0x34 Key Word Register 5 AES_KEYWR5 Write-only – 0x38 Key Word Register 6 AES_KEYWR6 Write-only – 0x3C Key Word Register 7 AES_KEYWR7 Write-only – 0x40 Input Data Register 0 AES_IDATAR0 Write-only – 0x44 Input Data Register 1 AES_IDATAR1 Write-only – 0x48 Input Data Register 2 AES_IDATAR2 Write-only – 0x4C Input Data Register 3 AES_IDATAR3 Write-only – 0x50 Output Data Register 0 AES_ODATAR0 Read-only 0x0 0x54 Output Data Register 1 AES_ODATAR1 Read-only 0x0 0x58 Output Data Register 2 AES_ODATAR2 Read-only 0x0 0x5C Output Data Register 3 AES_ODATAR3 Read-only 0x0 0x60 Initialization Vector Register 0 AES_IVR0 Write-only – 0x64 Initialization Vector Register 1 AES_IVR1 Write-only – 0x68 Initialization Vector Register 2 AES_IVR2 Write-only – 0x6C Initialization Vector Register 3 AES_IVR3 Write-only – 0x70 Additional Authenticated Data Length Register AES_AADLENR Read/Write – 0x74 Plaintext/Ciphertext Length Register AES_CLENR Read/Write – 0x78 GCM Intermediate Hash Word Register 0 AES_GHASHR0 Read/Write – 0x7C GCM Intermediate Hash Word Register 1 AES_GHASHR1 Read/Write – 0x80 GCM Intermediate Hash Word Register 2 AES_GHASHR2 Read/Write – 0x84 GCM Intermediate Hash Word Register 3 AES_GHASHR3 Read/Write – 0x88 GCM Authentication Tag Word Register 0 AES_TAGR0 Read-only – 0x8C GCM Authentication Tag Word Register 1 AES_TAGR1 Read-only – 0x08–0x0C  2017 Microchip Technology Inc. DS60001525A-page 1561 SAMA5D4 SERIES Table 50-5: Offset Register Mapping (Continued) Register Name Access Reset 0x90 GCM Authentication Tag Word Register 2 AES_TAGR2 Read-only – 0x94 GCM Authentication Tag Word Register 3 AES_TAGR3 Read-only – 0x98 GCM Encryption Counter Value Register AES_CTRR Read-only – 0x9C GCM H Word Register 0 AES_GCMHR0 Read/Write – 0xA0 GCM H Word Register 1 AES_GCMHR1 Read/Write – 0xA4 GCM H Word Register 2 AES_GCMHR2 Read/Write – 0xA8 GCM H Word Register 3 AES_GCMHR3 Read/Write – 0xAC Reserved – – – 0xB0 Reserved – – – 0xB4 Reserved – – 0xC0–0xE0 Reserved – – – 0xE4–0xF8 Reserved – – – 0xFC Reserved – – – DS60001525A-page 1562 –  2017 Microchip Technology Inc. SAMA5D4 SERIES 50.5.1 AES Control Register Name: AES_CR Address:0xFC044000 Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – SWRST 7 6 5 4 3 2 1 0 – – – – – – – START START: Start Processing 0: No effect. 1: Starts manual encryption/decryption process. SWRST: Software Reset 0: No effect. 1: Resets the AES. A software-triggered hardware reset of the AES interface is performed.  2017 Microchip Technology Inc. DS60001525A-page 1563 SAMA5D4 SERIES 50.5.2 AES Mode Register Name: AES_MR Address:0xFC044004 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 CKEY 15 – 14 13 LOD 12 11 OPMOD 7 6 5 10 9 KEYSIZE 4 PROCDLY CFBS 8 SMOD 3 2 1 0 DUALBUFF – GTAGEN CIPHER CIPHER: Processing Mode 0: Decrypts data. 1: Encrypts data. GTAGEN: GCM Automatic Tag Generation Enable 0: Automatic GCM Tag generation disabled. 1: Automatic GCM Tag generation enabled. DUALBUFF: Dual Input Buffer Value Name Description 0 INACTIVE AES_IDATARx cannot be written during processing of previous block. 1 ACTIVE AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. PROCDLY: Processing Delay Processing Time = N × (PROCDLY + 1) where N = 10 when KEYSIZE = 0 N = 12 when KEYSIZE = 1 N = 14 when KEYSIZE = 2 The processing time represents the number of clock cycles that the AES needs in order to perform one encryption/decryption. Note: The best performance is achieved with PROCDLY equal to 0. SMOD: Start Mode Value Name Description 0 MANUAL_START Manual Mode 1 AUTO_START Auto Mode 2 IDATAR0_START AES_IDATAR0 access only Auto Mode (DMA) If a DMA transfer is used, configure SMOD to 2. Refer to Section 50.4.4.3 “DMA Mode” for more details. DS60001525A-page 1564  2017 Microchip Technology Inc. SAMA5D4 SERIES KEYSIZE: Key Size Value Name Description 0 AES128 AES Key Size is 128 bits 1 AES192 AES Key Size is 192 bits 2 AES256 AES Key Size is 256 bits OPMOD: Operating Mode Value Name Description 0 ECB ECB: Electronic Codebook mode 1 CBC CBC: Cipher Block Chaining mode 2 OFB OFB: Output Feedback mode 3 CFB CFB: Cipher Feedback mode 4 CTR CTR: Counter mode (16-bit internal counter) 5 GCM GCM: Galois/Counter mode For CBC-MAC operating mode, set OPMOD to CBC and LOD to 1. LOD: Last Output Data Mode 0: No effect. After each end of encryption/decryption, the output data are available either on the output data registers (Manual and Auto modes) or at the address specified in the Channel Buffer Transfer Descriptor for DMA mode. In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read. 1: The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads is necessary between consecutive encryptions/decryptions (refer to Section 50.4.5 “Last Output Data Mode”). Warning: In DMA mode, reading to the Output Data registers before the last data encryption/decryption process may lead to unpredictable results. CFBS: Cipher Feedback Data Size Value Name Description 0 SIZE_128BIT 128-bit 1 SIZE_64BIT 64-bit 2 SIZE_32BIT 32-bit 3 SIZE_16BIT 16-bit 4 SIZE_8BIT 8-bit CKEY: Key Value 0xE Name Description PASSWD This field must be written with 0xE the first time AES_MR is programmed. For subsequent programming of AES_MR, any value can be written, including that of 0xE. Always reads as 0.  2017 Microchip Technology Inc. DS60001525A-page 1565 SAMA5D4 SERIES 50.5.3 AES Interrupt Enable Register Name: AES_IER Address:0xFC044010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – TAGRDY 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. DATRDY: Data Ready Interrupt Enable URAD: Unspecified Register Access Detection Interrupt Enable TAGRDY: GCM Tag Ready Interrupt Enable DS60001525A-page 1566  2017 Microchip Technology Inc. SAMA5D4 SERIES 50.5.4 AES Interrupt Disable Register Name: AES_IDR Address:0xFC044014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – TAGRDY 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. DATRDY: Data Ready Interrupt Disable URAD: Unspecified Register Access Detection Interrupt Disable TAGRDY: GCM Tag Ready Interrupt Disable  2017 Microchip Technology Inc. DS60001525A-page 1567 SAMA5D4 SERIES 50.5.5 AES Interrupt Mask Register Name: AES_IMR Address:0xFC044018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – TAGRDY 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. DATRDY: Data Ready Interrupt Mask URAD: Unspecified Register Access Detection Interrupt Mask TAGRDY: GCM Tag Ready Interrupt Mask DS60001525A-page 1568  2017 Microchip Technology Inc. SAMA5D4 SERIES 50.5.6 AES Interrupt Status Register Name: AES_ISR Address:0xFC04401C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – TAGRDY 15 14 13 12 11 10 9 8 – – – URAD URAT 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) 0: Output data not valid. 1: Encryption or decryption process is completed. Note: If AES_MR.LOD = 1: In Manual and Auto mode, the DATRDY flag can also be cleared by writing at least one AES_IDATARx. URAD: Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) 0: No unspecified register access has been detected since the last SWRST. 1: At least one unspecified register access has been detected since the last SWRST. URAT: Unspecified Register Access (cleared by writing SWRST in AES_CR) Value Name Description 0 IDR_WR_PROCESSING Input Data register written during the data processing when SMOD = 2 mode. 1 ODR_RD_PROCESSING Output Data register read during the data processing. 2 MR_WR_PROCESSING Mode register written during the data processing. 3 ODR_RD_SUBKGEN Output Data register read during the sub-keys generation. 4 MR_WR_SUBKGEN Mode register written during the sub-keys generation. 5 WOR_RD_ACCESS Write-only register read access. Only the last Unspecified Register Access Type is available through the URAT field. TAGRDY: GCM Tag Ready 0: GCM Tag is not valid. 1: GCM Tag generation is complete (cleared by reading GCM Tag, starting another processing or when writing a new key).  2017 Microchip Technology Inc. DS60001525A-page 1569 SAMA5D4 SERIES 50.5.7 AES Key Word Register x Name: AES_KEYWRx [x=0..7] Address:0xFC044020 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEYW 23 22 21 20 KEYW 15 14 13 12 KEYW 7 6 5 4 KEYW KEYW: Key Word The four/six/eight 32-bit Key Word registers set the 128-bit/192-bit/256-bit cryptographic key used for AES encryption/decryption. AES_KEYWR0 corresponds to the first word of the key and respectively AES_KEYWR3/AES_KEYWR5/AES_KEYWR7 to the last one. Whenever a new key (AES_KEYWRx) is written to the hardware, two automatic actions are processed: • GCM hash subkey generation • AES_GHASHRx Clear Refer to Section 50.4.6.2 “Key Writing and Automatic Hash Subkey Calculation” for details. These registers are write-only to prevent the key from being read by another application. DS60001525A-page 1570  2017 Microchip Technology Inc. SAMA5D4 SERIES 50.5.8 AES Input Data Register x Name: AES_IDATARx [x=0..3] Address:0xFC044040 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA 23 22 21 20 IDATA 15 14 13 12 IDATA 7 6 5 4 IDATA IDATA: Input Data Word The four 32-bit Input Data registers set the 128-bit data block used for encryption/decryption. AES_IDATAR0 corresponds to the first word of the data to be encrypted/decrypted, and AES_IDATAR3 to the last one. These registers are write-only to prevent the input data from being read by another application.  2017 Microchip Technology Inc. DS60001525A-page 1571 SAMA5D4 SERIES 50.5.9 AES Output Data Register x Name: AES_ODATARx [x=0..3] Address:0xFC044050 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA ODATA: Output Data The four 32-bit Output Data registers contain the 128-bit data block that has been encrypted/decrypted. AES_ODATAR0 corresponds to the first word, AES_ODATAR3 to the last one. DS60001525A-page 1572  2017 Microchip Technology Inc. SAMA5D4 SERIES 50.5.10 AES Initialization Vector Register x Name: AES_IVRx [x=0..3] Address:0xFC044060 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IV 23 22 21 20 IV 15 14 13 12 IV 7 6 5 4 IV IV: Initialization Vector The four 32-bit Initialization Vector registers set the 128-bit Initialization Vector data block that is used by some modes of operation as an additional initial input. AES_IVR0 corresponds to the first word of the Initialization Vector, AES_IVR3 to the last one. These registers are write-only to prevent the Initialization Vector from being read by another application. For CBC, OFB and CFB modes, the IV input value corresponds to the initialization vector. For CTR mode, the IV input value corresponds to the initial counter value. Note: These registers are not used in ECB mode and must not be written.  2017 Microchip Technology Inc. DS60001525A-page 1573 SAMA5D4 SERIES 50.5.11 AES Additional Authenticated Data Length Register Name: AES_AADLENR Address:0xFC044070 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 AADLEN 23 22 21 20 AADLEN 15 14 13 12 AADLEN 7 6 5 4 AADLEN AADLEN: Additional Authenticated Data Length Length in bytes of the Additional Authenticated Data (AAD) that is to be processed. Note: The maximum byte length of the AAD portion of a message is limited to the 32-bit counter length. DS60001525A-page 1574  2017 Microchip Technology Inc. SAMA5D4 SERIES 50.5.12 AES Plaintext/Ciphertext Length Register Name: AES_CLENR Address:0xFC044074 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CLEN 23 22 21 20 CLEN 15 14 13 12 CLEN 7 6 5 4 CLEN CLEN: Plaintext/Ciphertext Length Length in bytes of the plaintext/ciphertext (C) data that is to be processed. Note: The maximum byte length of the C portion of a message is limited to the 32-bit counter length.  2017 Microchip Technology Inc. DS60001525A-page 1575 SAMA5D4 SERIES 50.5.13 AES GCM Intermediate Hash Word Register x Name: AES_GHASHRx [x=0..3] Address:0xFC044078 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 GHASH 23 22 21 20 GHASH 15 14 13 12 GHASH 7 6 5 4 GHASH GHASH: Intermediate GCM Hash Word x The four 32-bit Intermediate Hash Word registers expose the intermediate GHASH value. May be read to save the current GHASH value so processing can later be resumed, presumably on a later message fragment. Whenever a new key (AES_KEYWRx) is written to the hardware two automatic actions are processed: • GCM hash subkey generation • AES_GHASHRx Clear Refer to Section 50.4.6.2 “Key Writing and Automatic Hash Subkey Calculation” for details. If an application software-specific hash initial value is needed for the GHASH, it must be written to AES_GHASHRx: • after a write to AES_KEYWRx, if any, • before starting the input data feed. DS60001525A-page 1576  2017 Microchip Technology Inc. SAMA5D4 SERIES 50.5.14 AES GCM Authentication Tag Word Register x Name: AES_TAGRx [x=0..3] Address:0xFC044088 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TAG 23 22 21 20 TAG 15 14 13 12 TAG 7 6 5 4 TAG TAG: GCM Authentication Tag x The four 32-bit Tag registers contain the final 128-bit GCM Authentication tag (T) when GCM processing is complete. TAG0 corresponds to the first word, TAG3 to the last word.  2017 Microchip Technology Inc. DS60001525A-page 1577 SAMA5D4 SERIES 50.5.15 AES GCM Encryption Counter Value Register Name: AES_CTRR Address:0xFC044098 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CTR 23 22 21 20 CTR 15 14 13 12 CTR 7 6 5 4 CTR CTR: GCM Encryption Counter Reports the current value of the 32-bit GCM counter. DS60001525A-page 1578  2017 Microchip Technology Inc. SAMA5D4 SERIES 50.5.16 AES GCM H Word Register x Name: AES_GCMHRx [x=0..3] Address:0xFC04409C Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 H 23 22 21 20 H 15 14 13 12 H 7 6 5 4 H H: GCM H Word x The four 32-bit H Word registers contain the 128-bit GCM hash subkey H value. Whenever a new key (AES_KEYWRx) is written to the hardware, two automatic actions are processed: • GCM hash subkey H generation • AES_GHASHRx Clear If the application software requires a specific hash subkey, the automatically-generated H value can be overwritten in AES_GCMHRx. Refer to Section 50.4.6.2 “Key Writing and Automatic Hash Subkey Calculation” for details. Generating a GCM hash subkey H by a write in AES_GCMHRx enables to: • select the GCM hash subkey H for GHASH operations, • select one operand to process a single GF128 multiply.  2017 Microchip Technology Inc. DS60001525A-page 1579 SAMA5D4 SERIES 51. Triple Data Encryption Standard (TDES) 51.1 Description The Triple Data Encryption Standard (TDES) is compliant with the American FIPS (Federal Information Processing Standard) Publication 46-3 specification. The TDES supports the four different confidentiality modes of operation (ECB, CBC, OFB and CFB), specified in the FIPS (Federal Information Processing Standard) Publication 81 and is compatible with the Peripheral Data Controller channels for all of these modes, minimizing processor intervention for large buffer transfers. The 64-bit long keys and input data (and initialization vector for some modes) are each stored in two corresponding 32-bit write-only registers: Key x Word Registers TDES_KEYxWR0 and TDES_KEYxWR1 Input Data Registers TDES_IDATAR0 and TDES_IDATAR1 Initialization Vector Registers TDES_IVR0 and TDES_IVR1 As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process may be started. Then the encrypted/decrypted data is ready to be read out on the two 32-bit Output Data registers (TDES_ODATARx) or through the DMA channels. 51.2 Embedded Characteristics • • • • • • • • • Supports Single Data Encryption Standard (DES) and Triple Data Encryption Algorithm (TDEA or TDES) Compliant with FIPS Publication 46-3, Data Encryption Standard (DES) 64-bit Cryptographic Key for TDES Two-key or Three-key Algorithms for TDES 18-clock Cycles Encryption/Decryption Processing Time for DES 50-clock Cycles Encryption/Decryption Processing Time for TDES Supports eXtended Tiny Encryption Algorithm (XTEA) 128-bit key for XTEA and Programmable Round Number up to 64 Supports the Four Standard Modes of Operation specified in the FIPS Publication 81, DES Modes of Operation - Electronic Code Book (ECB) - Cipher Block Chaining (CBC) - Cipher Feedback (CFB) - Output Feedback (OFB) • 8-, 16-, 32- and 64-bit Data Sizes Possible in CFB Mode • Last Output Data Mode Allowing Optimized Message (Data) Authentication Code (MAC) Generation • Connection to DMA Optimizes Data Transfers for all Operating Modes 51.3 Product Dependencies 51.3.1 Power Management The TDES may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the TDES clock. 51.3.2 Interrupt Sources The TDES interface has an interrupt line connected to the interrupt controller. Handling the TDES interrupt requires programming the interrupt controller before configuring the TDES. Table 51-1: Peripheral IDs Instance ID TDES 14 DS60001525A-page 1580  2017 Microchip Technology Inc. SAMA5D4 SERIES 51.4 Functional Description The Data Encryption Standard (DES) and the Triple Data Encryption Algorithm (TDES) specify FIPS-approved cryptographic algorithms that can be used to protect electronic data. The TDES bit in the TDES Mode Register (TDES_MR) is used to select either the single DES or the Triple DES mode. Encryption (enciphering) converts data to an unintelligible form called ciphertext. Decrypting (deciphering) the ciphertext converts the data back into its original form, called plaintext. The CIPHER bit in TDES_MR is used to choose between encryption and decryption. A DES is capable of using cryptographic keys of 64 bits to encrypt and decrypt data in blocks of 64 bits. This 64-bit key is defined in the Key 1 Word Registers (TDES_KEY1WRx). A TDES key consists of three DES keys, which is also referred to as a key bundle. These three 64-bit keys are defined, respectively, in the Key 1, 2 and 3 Word Registers (TDES_KEY1WRx, TDES_KEY2WRx and TDES_KEY3WRx). In Triple DES mode (TDESMOD = 1 in TDES_MR), the KEYMOD bit in TDES_MR is used to choose between a two- and a three-key algorithm, as summarized in Table 51-2. Table 51-2: TDES Algorithms Summary Data Processing Sequence Steps Algorithm Mode First Second Third Encryption Encryption with Key 1 Decryption with Key 2 Encryption with Key 3 Decryption Decryption with Key 3 Encryption with Key 2 Decryption with Key 1 Encryption Encryption with Key 1 Decryption with Key 2 Encryption with Key 1 Decryption Decryption with Key 1 Encryption with Key 2 Decryption with Key 1 Three-key Two-key The input to the encryption processes of the CBC, CFB, and OFB modes includes, in addition to the plaintext, a 64-bit data block called the initialization vector (IV), which must be set in the Initialization Vector Registers (TDES_IVRx). The initialization vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message. The XTEA algorithm can be used instead of DES/TDES by configuring the TDESMOD field in TDES_MR with the appropriate value 0x2. An XTEA key consists of a 128-bit key. They are defined in the Key 1 and 2 Word Registers (TDES_KEY1WRx, TDES_KEY2WRx). The number of rounds of XTEA is defined in TDES_XTEA_RNDR and can be programmed up to 64 (1 round = 2 Feistel network rounds). All the start and operating modes of the TDES algorithm can be applied to the XTEA algorithm. 51.4.1 Operating Modes The TDES supports the following operating modes: • • • • ECB—Electronic Code Book CBC—Cipher Block Chaining OFB—Output Feedback CFB—Cipher Feedback - CFB8 (CFB where the length of the data segment is 8 bits) - CFB16 (CFB where the length of the data segment is 16 bits) - CFB32 (CFB where the length of the data segment is 32 bits) - CFB64 (CFB where the length of the data segment is 64 bits) The data pre-processing, post-processing and data chaining for each mode are automatically performed. Refer to the FIPS Publication 81 for more complete information. These modes are selected by setting the OPMOD field in TDES_MR. In CFB mode, four data sizes are possible (8, 16, 32 and 64 bits), configurable by means of the CFBS field in TDES_MR (refer to Section 51.5.2 “TDES Mode Register”). 51.4.2 Start Modes The SMOD field in TDES_MR selects the Encryption (or Decryption) start mode.  2017 Microchip Technology Inc. DS60001525A-page 1581 SAMA5D4 SERIES 51.4.2.1 Manual Mode The sequence is as follows: 1. 2. 3. Write the TDES_MR register with all required fields, including but not limited to SMOD and OPMOD. Write the 64-bit key(s) in the different Key Word Registers (TDES_KEYxWRx), depending on whether one, two or three keys are required. Write the initialization vector (or counter) in the Initialization Vector Registers (TDES_IVRx). Note: 4. 5. Note: 6. 7. 8. The Initialization Vector Registers concern all modes except ECB. Set the bit DATRDY (Data Ready) in the TDES Interrupt Enable register (TDES_IER), depending on whether an interrupt is required or not at the end of processing. Write the data to be encrypted/decrypted in the authorized Input Data Registers (refer to Table 51-3). In 32-, 16- and 8-bit CFB modes, writing to TDES_IDATAR1 is not allowed and may lead to processing errors. Set the START bit in the TDES Control Register (TDES_CR) to begin the encryption or decryption process. When the processing completes, the bit DATRDY in the TDES Interrupt Status Register (TDES_ISR) rises. If an interrupt has been enabled by setting the bit DATRDY in TDES_IER, the interrupt line of the TDES is activated. When the software reads one of the Output Data Registers (TDES_ODATARx), the DATRDY bit is automatically cleared. Table 51-3: Authorized Input Data Registers Operating Mode Input Data Registers to Write ECB All CBC All OFB All CFB 64-bit All CFB 32-bit TDES_IDATAR0 CFB 16-bit TDES_IDATAR0 CFB 8-bit TDES_IDATAR0 51.4.2.2 Auto Mode The Auto Mode is similar to the Manual Mode, except that as soon as the correct number of Input Data registers is written, processing is automatically started without any action in TDES_CR. 51.4.2.3 DMA Mode The DMA Controller can be used in association with the TDES to perform an encryption/decryption of a buffer without any action by the software during processing. The SMOD field of TDES_MR must be set to 0x2 and the DMA must be configured with non-incremental addresses. The start address of any transfer descriptor must be set in TDES_IDATAR0. The DMA chunk size configuration depends on the TDES mode of operation and is listed in Table 51-4. When writing data to TDES with the first DMA channel, data will be fetched from a memory buffer (source data). It is recommended to configure the size of source data to “words” even for CFB modes. On the contrary, the destination data size depends on the mode of operation. When reading data from the TDES with the second DMA channel, the source data is the data read from TDES and data destination is the memory buffer. In this case, source data size depends on the TDES mode of operation and is listed in Table 51-4. Table 51-4: DMA Data Transfer Type for the Different Operating Modes Operating Mode Chunk Size Destination/Source Data Transfer Type ECB 1 Word CBC 1 Word OFB 1 Word DS60001525A-page 1582  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 51-4: DMA Data Transfer Type for the Different Operating Modes (Continued) Operating Mode Chunk Size Destination/Source Data Transfer Type CFB 64-bit 1 Word CFB 32-bit 1 Word CFB 16-bit 1 Half-word CFB 8-bit 1 Byte 51.4.3 Last Output Data Mode This mode is used to generate cryptographic checksums on data (MAC) using a CBC-MAC or a CFB encryption algorithm (refer to FIPS Publication 81 Appendix F). After each end of encryption/decryption, the output data is available either on the output data registers for Manual and Auto modes or at the address specified in the receive buffer pointer for DMA mode (refer to Table 51-5 “Last Output Data Mode Behavior versus Start Modes”). The Last Output Data bit (LOD) in TDES_MR can be used to retrieve only the last data of several encryption/decryption processes. This data is only available on the Output Data Registers (TDES_ODATARx). Therefore, there is no need to define a read buffer in DMA mode. 51.4.3.1 Manual and Auto Modes TDES_MR.LOD = 0 The DATRDY flag is cleared when at least one of the Output Data Registers is read. Refer to Figure 51-1. Figure 51-1: Manual and Auto Modes with LOD = 0 Write START bit in TDES_CR (Manual mode) or Write TDES_IDATARx register(s) (Auto mode) Read TDES_ODATARx DATRDY Encryption or Decryption Process If the user does not want to read the output data registers between each encryption/decryption, the DATRDY flag will not be cleared. If the DATRDY flag is not cleared, the user will not be informed of the end of the encryptions/decryptions that follow. TDES_MR.LOD = 1 The DATRDY flag is cleared when at least one Input Data Register is written, before the start of a new transfer. Refer to Figure 51-2. No further Output Data Register reads are necessary between consecutive encryptions/decryptions.  2017 Microchip Technology Inc. DS60001525A-page 1583 SAMA5D4 SERIES Figure 51-2: Manual and Auto Modes with LOD = 1 Write START bit in TDES_CR (Manual mode) or Write TDES_IDATARx register(s) (Auto mode) Write TDES_IDATARx register(s) DATRDY Encryption or Decryption Process 51.4.3.2 DMA Mode TDES_MR.LOD = 0 This mode may be used for all TDES operating modes except CBC-MAC where LOD = 1 mode is recommended. The end of the encryption/decryption is indicated by the end of DMA transfer associated to TDES_ODATARx (refer to Figure 51-3). Two DMA channels are required: one for writing message blocks to TDES_IDATARx and one to obtain the result from TDES_ODATARx. Figure 51-3: DMA Transfer with LOD = 0 Enable DMA Channels associated to TDES_IDATARx and TDES_ODATARx Multiple Encryption or Decryption Processes DMA buffer transfer complete flag/channel m DMA buffer transfer complete flag/channel n Write accesses into TDES_IDATARx Read accesses into TDES_ODATARx Message fully processed (cipher or decipher) last block can be read TDES_MR.LOD = 1 This mode is optimized to process the TDES CBC-MAC operating mode. The user must first wait for the DMA buffer transfer complete flag, then for the flag DATRDY to rise to ensure that the encryption/decryption is completed (refer to Figure 51-4). In this case, no receive buffers are required. The output data is only available on TDES_ODATARx. Figure 51-4: DMA Transfer with LOD = 1 Enable DMA Channels associated with TDES_IDATARx and TDES_ODATARx Multiple Encryption or Decryption Processes DMA status flag for end of buffer transfer Write accesses into TDES_IDATARx DATRDY Message fully transferred DS60001525A-page 1584 Message fully processed (cipher or decipher) MAC result can be read  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 51-5 summarizes the different cases. Table 51-5: Last Output Data Mode Behavior versus Start Modes Manual and Auto Modes Sequence DMA Transfer LOD = 0 LOD = 1 LOD = 0 LOD = 1 DATRDY Flag Clearing Condition (1) At least one Output Data Register must be read At least one Input Data Register must be written Not used Managed by the DMA End of Encryption/ Decryption DATRDY DATRDY 2 DMA Buffer transfer complete flags (channel m and channel n) DMA buffer transfer complete flag, then TDES DATRDY flag Encrypted/Decrypted Data Result Location In the Output Data Registers In the Output Data Registers Not available In the Output Data Registers Note 1: Depending on the mode, there are other ways of clearing the DATRDY flag. Refer to Section 51.5.6 “TDES Interrupt Status Register”. Warning: In DMA mode, reading to the Output Data registers before the last data transfer may lead to unpredictable results. 51.4.4 51.4.4.1 Security Features Unspecified Register Access Detection When an unspecified register access occurs, the URAD bit in TDES_ISR is set. Its source is then reported in the Unspecified Register Access Type field (URAT). Only the last unspecified register access is available through the URAT field. Several kinds of unspecified register accesses can occur: • • • • Input Data Register written during the data processing in DMA mode Output Data Register read during the data processing Mode Register written during the data processing Write-only register read access The URAD bit and the URAT field can only be reset by the SWRST bit in TDES_CR.  2017 Microchip Technology Inc. DS60001525A-page 1585 SAMA5D4 SERIES 51.5 Triple Data Encryption Standard (TDES) User Interface Table 51-6: Offset Register Mapping Register Name Access Reset 0x00 Control Register TDES_CR Write-only – 0x04 Mode Register TDES_MR Read/Write 0x2 Reserved – – – 0x10 Interrupt Enable Register TDES_IER Write-only – 0x14 Interrupt Disable Register TDES_IDR Write-only – 0x18 Interrupt Mask Register TDES_IMR Read-only 0x0 0x1C Interrupt Status Register TDES_ISR Read-only 0x0000001E 0x20 Key 1 Word Register 0 TDES_KEY1WR0 Write-only – 0x24 Key 1 Word Register 1 TDES_KEY1WR1 Write-only – 0x28 Key 2 Word Register 0 TDES_KEY2WR0 Write-only – 0x2C Key 2 Word Register 1 TDES_KEY2WR1 Write-only – 0x30 Key 3 Word Register 0 TDES_KEY3WR0 Write-only – 0x34 Key 3 Word Register 1 TDES_KEY3WR1 Write-only – Reserved – – – 0x40 Input Data Register 0 TDES_IDATAR0 Write-only – 0x44 Input Data Register 1 TDES_IDATAR1 Write-only – Reserved – – – 0x50 Output Data Register 0 TDES_ODATAR0 Read-only 0x0 0x54 Output Data Register 1 TDES_ODATAR1 Read-only 0x0 Reserved – – – 0x60 Initialization Vector Register 0 TDES_IVR0 Write-only – 0x64 Initialization Vector Register 1 TDES_IVR1 Write-only – Reserved – XTEA Rounds Register TDES_XTEA_RNDR Reserved – 0x08–0x0C 0x38–0x3C 0x48–0x4C 0x58–0x5C 0x68–0x6C 0x70 0x74–0xFC DS60001525A-page 1586 – – Read/Write 0x0 – –  2017 Microchip Technology Inc. SAMA5D4 SERIES 51.5.1 TDES Control Register Name: TDES_CR Address:0xFC04C000 Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – SWRST 7 6 5 4 3 2 1 0 – – – – – – – START • START: Start Processing 0: No effect 1: Starts Manual encryption/decryption process. SWRST: Software Reset 0: No effect 1: Resets the TDES. A software triggered hardware reset of the TDES interface is performed.  2017 Microchip Technology Inc. DS60001525A-page 1587 SAMA5D4 SERIES 51.5.2 TDES Mode Register Name: TDES_MR Address:0xFC04C004 Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – – – 15 14 13 12 11 10 LOD – – – 2 OPMOD 7 6 5 4 3 – – – KEYMOD – 16 CFBS 9 8 SMOD 1 TDESMOD 0 CIPHER CIPHER: Processing Mode 0 (DECRYPT): Decrypts data. 1 (ENCRYPT): Encrypts data. TDESMOD: ALGORITHM Mode Value Name Description 0x0 SINGLE_DES Single DES processing using TDES_KEY1WRx registers 0x1 TRIPLE_DES Triple DES processing using TDES_KEY1WRx, TDES_KEY2WRx and TDES_KEY3WRx registers 0x2 XTEA XTEA processing using TDES_KEY1WRx, TDES_KEY2WRx Values which are not listed in the table must be considered as “reserved”. KEYMOD: Key Mode 0: Three-key algorithm is selected. 1: Two-key algorithm is selected. There is no need to write TDES_KEY3WRx registers. SMOD: Start Mode Value Name Description 0x0 MANUAL_START Manual Mode 0x1 AUTO_START Auto Mode 0x2 IDATAR0_START TDES_IDATAR0 accesses only Auto Mode Values which are not listed in the table must be considered as “reserved”. If a DMA transfer is used, 0x2 must be configured. Refer to Section 51.4.3.2 “DMA Mode” for more details. OPMOD: Operating Mode Value Name Description 0x0 ECB Electronic Code Book mode 0x1 CBC Cipher Block Chaining mode 0x2 OFB Output Feedback mode 0x3 CFB Cipher Feedback mode DS60001525A-page 1588  2017 Microchip Technology Inc. SAMA5D4 SERIES For CBC-MAC operating mode, set OPMOD to CBC and LOD to 1. LOD: Last Output Data Mode 0: No effect. After each end of encryption/decryption, the output data is available either on the output data registers (Manual and Auto modes). In Manual and Auto modes, the DATRDY flag is cleared when at least one of the Output Data registers is read. 1: The DATRDY flag is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads are necessary between consecutive encryptions/decryptions (refer to Section 51.4.3 “Last Output Data Mode”). Warning: In DMA mode, reading to the Output Data registers before the last data encryption/decryption process may lead to unpredictable result. CFBS: Cipher Feedback Data Size Value Name Description 0x0 SIZE_64BIT 64-bit 0x1 SIZE_32BIT 32-bit 0x2 SIZE_16BIT 16-bit 0x3 SIZE_8BIT 8-bit  2017 Microchip Technology Inc. DS60001525A-page 1589 SAMA5D4 SERIES 51.5.3 TDES Interrupt Enable Register Name: TDES_IER Address:0xFC04C010 Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt. URAD: Unspecified Register Access Detection Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt. DS60001525A-page 1590  2017 Microchip Technology Inc. SAMA5D4 SERIES 51.5.4 TDES Interrupt Disable Register Name: TDES_IDR Address:0xFC04C014 Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt. URAD: Unspecified Register Access Detection Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.  2017 Microchip Technology Inc. DS60001525A-page 1591 SAMA5D4 SERIES 51.5.5 TDES Interrupt Mask Register Name: TDES_IMR Address:0xFC04C018 Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. URAD: Unspecified Register Access Detection Interrupt Mask 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. DS60001525A-page 1592  2017 Microchip Technology Inc. SAMA5D4 SERIES 51.5.6 TDES Interrupt Status Register Name: TDES_ISR Address:0xFC04C01C Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – URAD URAT 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready (cleared by setting bit START or bit SWRST in TDES_CR or by reading TDES_ODATARx) 0: Output data is not valid. 1: Encryption or decryption process is completed. Note: If TDES_MR.LOD = 1: In Manual and Auto modes, the DATRDY flag can also be cleared by writing at least one TDES_IDATARx. URAD: Unspecified Register Access Detection Status (cleared by setting bit TDES_CR.SWRST) 0: No unspecified register access has been detected since the last write of bit TDES_CR.SWRST. 1: At least one unspecified register access has been detected since the last write of bit TDES_CR.SWRST. URAT: Unspecified Register Access (cleared by setting bit TDES_CR.SWRST) Value Name Description 0x0 IDR_WR_PROCESSING Input Data Register written during data processing when SMOD = 0x2 mode. 0x1 ODR_RD_PROCESSING Output Data Register read during data processing. 0x2 MR_WR_PROCESSING Mode Register written during data processing. 0x3 WOR_RD_ACCESS Write-only register read access. Only the last Unspecified Register Access Type is available through the URAT field.  2017 Microchip Technology Inc. DS60001525A-page 1593 SAMA5D4 SERIES 51.5.7 TDES Key 1 Word Register x Name: TDES_KEY1WRx Address:0xFC04C020 Access:Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY1W 23 22 21 20 KEY1W 15 14 13 12 KEY1W 7 6 5 4 KEY1W KEY1W: Key 1 Word The two 32-bit Key 1 Word registers are used to set the 64-bit cryptographic key used for encryption/decryption. KEY1W0 refers to the first word of the key and KEY1W1 to the last one. These registers are write-only to prevent the key from being read by another application. In XTEA mode, the key is defined on 128 bits. These registers contain the 64 LSB bits of the encryption/decryption key. DS60001525A-page 1594  2017 Microchip Technology Inc. SAMA5D4 SERIES 51.5.8 TDES Key 2 Word Register x Name: TDES_KEY2WRx Address:0xFC04C028 Access:Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY2W 23 22 21 20 KEY2W 15 14 13 12 KEY2W 7 6 5 4 KEY2W KEY2W: Key 2 Word The two 32-bit Key 2 Word registers are used to set the 64-bit cryptographic key used for encryption/decryption. KEY2W0 refers to the first word of the key and KEY2W1 to the last one. These registers are write-only to prevent the key from being read by another application. Note: KEY2WRx registers are not used in DES mode. In XTEA mode, the key is defined on 128 bits. These registers contain the 64 MSB bits of the encryption/decryption key.  2017 Microchip Technology Inc. DS60001525A-page 1595 SAMA5D4 SERIES 51.5.9 TDES Key 3 Word Register x Name: TDES_KEY3WRx Address:0xFC04C030 Access:Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEY3W 23 22 21 20 KEY3W 15 14 13 12 KEY3W 7 6 5 4 KEY3W KEY3W: Key 3 Word The two 32-bit Key 3 Word registers are used to set the 64-bit cryptographic key used for encryption/decryption. KEY3W0 refers to the first word of the key and KEY3W1 to the last one. These registers are write-only to prevent the key from being read by another application. Note: KEY3WRx registers are not used in DES mode, TDES with two-key algorithm selected and XTEA mode. DS60001525A-page 1596  2017 Microchip Technology Inc. SAMA5D4 SERIES 51.5.10 TDES Input Data Register x Name: TDES_IDATARx Address:0xFC04C040 Access:Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA 23 22 21 20 IDATA 15 14 13 12 IDATA 7 6 5 4 IDATA IDATA: Input Data The two 32-bit Input Data registers are used to set the 64-bit data block used for encryption/decryption. IDATA0 refers to the first word of the data to be encrypted/decrypted, and IDATA1 to the last one. These registers are write-only to prevent the input data from being read by another application.  2017 Microchip Technology Inc. DS60001525A-page 1597 SAMA5D4 SERIES 51.5.11 TDES Output Data Register x Name: TDES_ODATARx Address:0xFC04C050 Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA ODATA: Output Data The two 32-bit Output Data registers contain the 64-bit data block which has been encrypted/decrypted. ODATA1 refers to the first word, ODATA2 to the last one. DS60001525A-page 1598  2017 Microchip Technology Inc. SAMA5D4 SERIES 51.5.12 TDES Initialization Vector Register x Name: TDES_IVRx Address:0xFC04C060 Access:Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IV 23 22 21 20 IV 15 14 13 12 IV 7 6 5 4 IV IV: Initialization Vector The two 32-bit Initialization Vector registers are used to set the 64-bit initialization vector data block, which is used by some modes of operation as an additional initial input. IV1 refers to the first word of the Initialization Vector, IV2 to the last one. These registers are write-only to prevent the Initialization Vector from being read by another application. Note: These registers are not used for the ECB mode and must not be written.  2017 Microchip Technology Inc. DS60001525A-page 1599 SAMA5D4 SERIES 51.5.13 TDES XTEA Rounds Register Name: TDES_XTEA_RNDR Address:0xFC04C070 Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – XTEA_RNDS XTEA_RNDS: Number of Rounds This 6-bit field is used to define the number of complete rounds (1 complete round = 2 Feistel rounds) processed in XTEA algorithm. The value of XTEA_RNDS has no effect if the TDESMOD field in TDES_MR is set to 0x0 or 0x1. Note: 0x00 corresponds to 1 complete round, 0x01 corresponds to 2 complete rounds, etc. DS60001525A-page 1600  2017 Microchip Technology Inc. SAMA5D4 SERIES 52. Secure Hash Algorithm (SHA) 52.1 Description The Secure Hash Algorithm (SHA) is compliant with the American FIPS (Federal Information Processing Standard) Publication 180-2 specification. The 512/1024-bit block of message is respectively stored in 16/32 x 32-bit registers, (SHA_IDATARx/SHA_IODATARx) which are writeonly. As soon as the input data is written, the hash processing may be started. The registers comprising the block of a padded message must be entered consecutively. Then the message digest is ready to be read out on the 5 up to 8/16 x 32-bit output data registers (SHA_IODATARx) or through the DMA channels. 52.2 Embedded Characteristics • • • • Supports Secure Hash Algorithm (SHA1, SHA224, SHA256, SHA384, SHA512) Compliant with FIPS Publication 180-2 Supports initial hash values registers (HMAC acceleration or other) Configurable Processing Period: - 85 Clock Cycles to obtain a fast SHA1 runtime, 88 clock cycles for SHA384, SHA512 or 209 Clock Cycles for Maximizing Bandwidth of Other Applications - 72 Clock Cycles to obtain a fast SHA224, SHA256 runtime or 194 Clock Cycles for Maximizing Bandwidth of Other Applications • Connection to DMA Channel Capabilities Optimizes Data Transfers • Double Input Buffer Optimizes Runtime 52.3 Product Dependencies 52.3.1 Power Management The SHA may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the SHA clock. 52.3.2 Interrupt Sources The SHA interface has an interrupt line connected to the Interrupt Controller. Handling the SHA interrupt requires programming the interrupt controller before configuring the SHA. Table 52-1: Peripheral IDs Instance ID SHA 15 52.4 Functional Description The Secure Hash Algorithm (SHA) module requires a padded message according to FIPS180-2 specification. The first block of the message must be indicated to the module by a specific command. The SHA module produces an N-bit message digest each time a block is written and processing period ends, where N is 160 for SHA1, 224 for SHA224,256 for SHA256, 384 for SHA384, 512 for SHA512. 52.4.1 SHA Algorithm The SHA can process SHA1, SHA224, SHA256, SHA384, SHA512 by configuring the ALGO field in the SHA Mode register (SHA_MR). 52.4.2 Processing Period The processing period can be configured. The short processing period allocates bandwidth to the SHA module, whereas the long processing period allocates more bandwidth on the system bus to other applications. An example is DMA channels not associated with SHA. In SHA1 mode, the shortest processing period is 85 clock cycles + 2 clock cycles for start command synchronization. The longest period is 209 clock cycles + 2 clock cycles.  2017 Microchip Technology Inc. DS60001525A-page 1601 SAMA5D4 SERIES In SHA384, SHA512 mode, the shortest processing period is 88 clock cycles + 2 clock cycles for start command synchronization. The longest period is 209 clock cycles + 2 clock cycles. In SHA256 and SHA224 mode, the shortest processing period is 72 clock cycles + 2 clock cycles for start command synchronization. The longest period is 194 clock cycles + 2 clock cycles. 52.4.3 Double Input Buffer The SHA Input Data registers (SHA_IDATARx) can be double-buffered to reduce the runtime of large files. Double-buffering allows a new message block to be written while the previous message block is being processed. This is only possible when DMA accesses are performed (SMOD = 2). The DUALBUFF bit in the SHA_MR must be set to have double input buffer access. 52.4.4 Internal Registers for Initial Hash Value The SHA module embeds a set of initial hash value registers to store user initial hash values (refer to Figure 52-1). These registers are internal registers and are accessed through SHA Input Data registers (SHA_IDATARx). The initial hash value registers can be used to compute a custom hash algorithm with different initial constants, or to continue a hash computation by providing the intermediate hash value previously returned by the SHA module. To write the initial hash values in the registers, follow this sequence: 1. 2. Set bit WUIHV in SHA_CR. Write the initial hash values in SHA_IDATARx. The number of registers to write depends on the hash algorithm selected: - SHA_IDATAR0 to SHA_IDATAR4 for the SHA1 algorithm - SHA_IDATAR0 to SHA_IDATAR7 for the SHA224 and SHA256 algorithms - SHA_IDATAR0 to SHA_IDATAR15 for the SHA384 and SHA512 algorithms 3. Clear bit WUIHV in SHA_CR. The internal registers are selected when bit UIHV is set in SHA_MR. Figure 52-1: User Initial Hash Value Internal Register Access User Interface Internal Registers SHA Engine SHA_IDATARx IDATARx DataPath 0 1 SHA_CR.WUIHV 0 FIPS180 H Values 0 1 1 User Initial Hash Values SHA_MR.UIHV SHA_MR.FIRST 52.4.5 Set Clear end of 1st block Start Modes The SMOD field in the SHA_MR is used to select the Hash Processing Start mode. 52.4.5.1 Manual Mode In Manual mode, the sequence is as follows: 1. 2. Set the bit DATRDY (Data Ready) in the SHA_IER, depending on whether an interrupt is required at the end of processing. If the initial hash values differ from the FIPS standard, set the bits UIHV in the SHA_MR depending on the configure the initial values. If the initial hash values comply with the FIPS180-2 specification, clear the bits UIHV in the SHA_MR. DS60001525A-page 1602  2017 Microchip Technology Inc. SAMA5D4 SERIES 3. 4. 5. 6. 7. 8. For the first block of a message, the FIRST command must be set by writing a 1 into the corresponding bit of the SHA Control Register (SHA_CR). For the other blocks, there is nothing to write. Write the block to be processed in the SHA_IDATARx. To begin processing, set the START bit in the SHA_CR. When processing is completed, the bit DATRDY in the Interrupt Status register (SHA_ISR) raises. If an interrupt has been enabled by setting the bit DATRDY in SHA_IER, the interrupt line of the SHA is activated. Repeat the write procedure for each block, start procedure and wait for the interrupt procedure up to the last block of the entire message. Each time the start procedure is complete, the DATRDY flag is cleared. After the last block is processed (DATRDY flag is set, if an interrupt has been enabled by setting the bit DATRDY in SHA_IER, the interrupt line of the SHA is activated), read the message digest in the Output Data Registers. The DATRDY flag is automatically cleared when reading the SHA_IODATARx registers. 52.4.5.2 Auto Mode In Auto mode, processing starts as soon as the correct number of SHA_IDATARx is written. No action in the SHA_CR is necessary. 52.4.5.3 DMA Mode The DMA can be used in association with the SHA to perform the algorithm on a complete message without any action by the software during processing. The SMOD field in SHA_MR must be configured to 2. The DMA must be configured with non-incremental addresses. The start address of any transfer descriptor must be set to point to the SHA_IDATAR0. The DMA chunk size must be set to transfer, for each trigger request, 16 words of 32 bits. The FIRST bit of the SHA_CR must be set before starting the DMA when the first block is transferred. The DMA generates an interrupt when the end of buffer transfer is completed but the SHA processing is still in progress. The end of SHA processing is indicated by the flag DATRDY in the SHA_SR. The end of SHA processing requires two interrupts to be verified. The DMA end of transfer interrupt must be verified first, then the SHA DATRDY interrupt must be enabled and verified (refer to Figure 52-2). Figure 52-2: Interrupts Processing with DMA Enable DMA Channels associated with SHA_IDATARx registers Message Processing (Multiple Block) DMA status flag for end of buffer transfer Write accesses into SHA_IDATARx DATRDY Message fully transferred 52.4.5.4 Message fully processed SHA result can be read SHA Register Endianism In Arm processor-based products, the system bus and processors manipulate data in little-endian form. The SHA interface requires littleendian format words. However, in accordance with the protocol of FIPS 180-2 specification, data is collected, processed and stored by the SHA algorithm in big-endian form. The following example illustrates how to configure the SHA: If the first 64 bits of a message (according to FIPS 180-2, i.e., big-endian format) to be processed is 0xcafedeca_01234567, then the SHA_IDATAR0 and SHA_IDATAR1 registers must be written with the following pattern: • SHA_IDATAR0 = 0xcadefeca • SHA_IDATAR1 = 0x67452301  2017 Microchip Technology Inc. DS60001525A-page 1603 SAMA5D4 SERIES In a little-endian system, the message (according to FIPS 180-2) starting with pattern 0xcafedeca_01234567 is stored into memory as follows: - 0xca stored at initial offset (for example 0x00), then 0xfe stored at initial offset + 1 (i.e., 0x01), 0xde stored at initial offset + 2 (i.e., 0x02), 0xca stored at initial offset + 3 (i.e., 0x03). If the message is received through a serial-to-parallel communication channel, the first received character is 0xca and it is stored at the first memory location (initial offset). The second byte, 0xfe, is stored at initial offset + 1. When reading on a 32-bit little-endian system bus, the first word read back from system memory is 0xcadefeca. When the SHA_IODATARx registers are read, the hash result is organized in little-endian format, allowing system memory storage in the same format as the message. Taking an example from the FIPS 180-2 specification Appendix B.1, the endianism conversion can be observed. For this example, the 512-bit message is: 0x6162638000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000000000000018 and the expected SHA-256 result is: 0xba7816bf_8f01cfea_414140de_5dae2223_b00361a3_96177a9c_b410ff61_f20015ad If the message has not already been stored in the system memory, the first step is to convert the input message to little-endian before writing to the SHA_IDATARx registers. This would result in a write of: SHA_IDATAR0 = 0x80636261...... SHA_IDATAR15 = 0x18000000 The data in the output message digest registers, SHA_IODATARx, contain SHA_IODATAR0 = 0xbf1678ba... SHA_IODATAR7 = 0xad1500f2 which is the little-endian format of 0xba7816bf,..., 0xf20015ad. Reading SHA_IODATAR0 to SHA_IODATAR1 and storing into a little-endian memory system forces hash results to be stored in the same format as the message. When the output message is read, the user can convert back to big-endian for a resulting message value of: 0xba7816bf_8f01cfea_414140de_5dae2223_b00361a3_96177a9c_b410ff61_f20015ad 52.4.6 Security Features When an unspecified register access occurs, the URAD bit in the SHA_ISR is set. Its source is then reported in the Unspecified Register Access Type field (URAT). Only the last unspecified register access is available through the URAT field. Several kinds of unspecified register accesses can occur: • • • • SHA_IDATARx written during data processing in DMA mode SHA_IODATARx read during data processing SHA_MR written during data processing Write-only register read access The URAD bit and the URAT field can only be reset by the SWRST bit in the SHA_CR. DS60001525A-page 1604  2017 Microchip Technology Inc. SAMA5D4 SERIES 52.5 Secure Hash Algorithm (SHA) User Interface Table 52-2: Offset Register Mapping Register Name Access Reset 0x00 Control Register SHA_CR Write-only – 0x04 Mode Register SHA_MR Read/Write 0x0000100 Reserved – – – 0x10 Interrupt Enable Register SHA_IER Write-only – 0x14 Interrupt Disable Register SHA_IDR Write-only – 0x18 Interrupt Mask Register SHA_IMR Read-only 0x0 0x1C Interrupt Status Register SHA_ISR Read-only 0x0 Reserved – – – Input Data 0 Register SHA_IDATAR0 Write-only – ... ... ... ... 0x7C Input Data 15 Register SHA_IDATAR15 Write-only – 0x80 Input/Output Data 0 Register SHA_IODATAR0 Read/Write 0x0 ... ... ... ... 0x9C Input/Output Data 7 Register SHA_IODATAR7 Read/Write 0x0 0xA0 Input/Output Data 8 Register SHA_IODATAR8 Read/Write 0x0 ... ... ... ... Input/Output Data 15 Register SHA_IODATAR15 Read/Write 0x0 Reserved – – – 0x08–0x0C 0x20–0x3C 0x40 ... ... ... 0xBC 0xC0–0xFC  2017 Microchip Technology Inc. DS60001525A-page 1605 SAMA5D4 SERIES 52.5.1 SHA Control Register Name: SHA_CR Address:0xFC050000 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – WUIHV – – – SWRST 7 6 5 4 3 2 1 0 – – – FIRST – – – START • START: Start Processing 0: No effect. 1: Starts manual hash algorithm process. • FIRST: First Block of a Message 0: No effect. 1: Indicates that the next block to process is the first one of a message. SWRST: Software Reset 0: No effect. 1: Resets the SHA. A software-triggered hardware reset of the SHA interface is performed. WUIHV: Write User Initial Hash Values 0: SHA_IDATARx accesses are routed to the data registers. 1: SHA_IDATARx accesses are routed to the internal registers (user initial hash values). DS60001525A-page 1606  2017 Microchip Technology Inc. SAMA5D4 SERIES 52.5.2 SHA Mode Register Name: SHA_MR Address:0xFC050004 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – DUALBUFF 15 14 13 12 11 10 9 8 – – – – ALGO 7 6 5 4 3 2 – – UIHV PROCDLY – – 1 0 SMOD SMOD: Start Mode Value Name Description 0 MANUAL_START Manual Mode 1 AUTO_START Auto Mode 2 IDATAR0_START SHA_IDATAR0 access only Auto Mode Values not listed in the table must be considered as “reserved”. If a DMA transfer is used, configure the SMOD value with 1 or 2. Refer to Section 52.4.5.3 “DMA Mode” for more details. PROCDLY: Processing Delay Value Name Description 0 SHORTEST SHA processing runtime is the shortest one 1 LONGEST SHA processing runtime is the longest one (reduces the SHA bandwidth requirement, reduces the system bus overload) When SHA1 algorithm is processed, runtime period is either 85 or 209 clock cycles. When SHA256 or SHA224 algorithm is processed, runtime period is either 72 or 194 clock cycles. When SHA384 or SHA512 algorithm is processed, runtime period is either 88 or 209 clock cycles. UIHV: User Initial Hash Values 0: The SHA algorithm is started with the standard initial values as defined in the FIPS180-2 specification. 1: The SHA algorithm is started with the user initial hash values stored in the internal initial hash value registers. ALGO: SHA Algorithm Value Name Description 0 SHA1 SHA1 algorithm processed 1 SHA256 SHA256 algorithm processed 2 SHA384 SHA384 algorithm processed 3 SHA512 SHA512 algorithm processed 4 SHA224 SHA224 algorithm processed Values not listed in the table must be considered as “reserved”.  2017 Microchip Technology Inc. DS60001525A-page 1607 SAMA5D4 SERIES DUALBUFF: Dual Input Buffer Value Name Description 0 INACTIVE SHA_IDATARx and SHA_IODATARx cannot be written during processing of previous block. 1 ACTIVE SHA_IDATARx and SHA_IODATARx can be written during processing of previous block when SMOD value = 2. It speeds up the overall runtime of large files. DS60001525A-page 1608  2017 Microchip Technology Inc. SAMA5D4 SERIES 52.5.3 SHA Interrupt Enable Register Name: SHA_IER Address:0xFC050010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. DATRDY: Data Ready Interrupt Enable URAD: Unspecified Register Access Detection Interrupt Enable  2017 Microchip Technology Inc. DS60001525A-page 1609 SAMA5D4 SERIES 52.5.4 SHA Interrupt Disable Register Name: SHA_IDR Address:0xFC050014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. DATRDY: Data Ready Interrupt Disable URAD: Unspecified Register Access Detection Interrupt Disable DS60001525A-page 1610  2017 Microchip Technology Inc. SAMA5D4 SERIES 52.5.5 SHA Interrupt Mask Register Name: SHA_IMR Address:0xFC050018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. DATRDY: Data Ready Interrupt Mask URAD: Unspecified Register Access Detection Interrupt Mask  2017 Microchip Technology Inc. DS60001525A-page 1611 SAMA5D4 SERIES 52.5.6 SHA Interrupt Status Register Name: SHA_ISR Address:0xFC05001C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – URAD URAT 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready (cleared by writing a 1 to bit SWRST or START in SHA_CR, or by reading SHA_IODATARx) 0: Output data is not valid. 1: 512/1024-bit block process is completed. DATRDY is cleared when one of the following conditions is met: • Bit START in SHA_CR is set. • Bit SWRST in SHA_CR is set. • The hash result is read. URAD: Unspecified Register Access Detection Status (cleared by writing a 1 to SWRST bit in SHA_CR) 0: No unspecified register access has been detected since the last SWRST. 1: At least one unspecified register access has been detected since the last SWRST. URAT: Unspecified Register Access Type (cleared by writing a 1 to SWRST bit in SHA_CR) Value Description 0 SHA_IDATAR0 to SHA_IDATAR15 written during the data processing in DMA mode (URAD = 1 and URAT = 0 can occur only if DUALBUFF is cleared in SHA_MR). 1 Output Data Register read during the data processing. 2 SHA_MR written during the data processing. 3 Write-only register read access. Only the last Unspecified Register Access Type is available through the URAT field. DS60001525A-page 1612  2017 Microchip Technology Inc. SAMA5D4 SERIES 52.5.7 SHA Input Data x Register Name: SHA_IDATARx [x=0..15] Address:0xFC050040 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA 23 22 21 20 IDATA 15 14 13 12 IDATA 7 6 5 4 IDATA IDATA: Input Data The 32-bit Input Data registers allow to load the data block used for hash processing. These registers are write-only to prevent the input data from being read by another application. SHA_IDATAR0 corresponds to the first word of the block, SHA_IDATAR15 to the last word of the last block in case SHA algorithm is set to SHA1, SHA224, SHA256 or SHA_IODATA15R to the last word of the block if SHA algorithm is SHA384 or SHA512 (refer to Section 52.5.8 “SHA Input/Output Data Register x”).  2017 Microchip Technology Inc. DS60001525A-page 1613 SAMA5D4 SERIES 52.5.8 SHA Input/Output Data Register x Name: SHA_IODATARx [x=0..15] Address:0xFC050080 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IODATA 23 22 21 20 IODATA 15 14 13 12 IODATA 7 6 5 4 IODATA IODATA: Input/Output Data These registers can be used to read the resulting message digest and to write the second part of the message block when the SHA algorithm is SHA-384 or SHA-512. SHA_IODATA0R to SHA_IODATA15R can be written or read but reading these offsets does not return the content of corresponding parts (words) of the message block. Only results from SHA calculation can be read through these registers. When SHA processing is in progress, these registers return 0x0000. SHA_IODATAR0 corresponds to the first word of the message digest; SHA_IODATAR4 to the last one in SHA1 mode, SHA_ODATAR6 in SHA224, SHA_IODATAR7 in SHA256, SHA_IODATAR11 in SHA384 or SHA_IODATAR15 in SHA512. When SHA224 is selected, the content of SHA_ODATAR7 must be ignored. When SHA384 is selected, the content of SHA_IODATAR12 to SHA_IODATAR15 must be ignored. DS60001525A-page 1614  2017 Microchip Technology Inc. SAMA5D4 SERIES 53. Advanced Encryption Standard Bridge (AESB) 53.1 Description The Advanced Encryption Standard Bridge (AESB) is intended to provide on-the-fly off-chip memory encryption/decryption compliant with the American FIPS (Federal Information Processing Standard) Publication 197 specification. The AESB supports three confidentiality modes of operation for symmetrical key block cipher algorithms (ECB, CBC and CTR), as specified in the NIST Special Publication 800-38A Recommendation. The 128-bit key is stored in four 32-bit registers (AESB_KEYWRx) which are all write-only. The 128-bit input data and initialization vector (for some modes) are each stored in four 32-bit registers (AESB_IDATARx and AESB_IVRx) which are all write-only. As soon as the initialization vector, the input data and the key are configured, the encryption/decryption process may be started. Then the encrypted/decrypted data will be ready to be read out on the four 32-bit output data registers (AESB_ODATARx). 53.2 Embedded Characteristics • • • • • • • On-the-fly off-chip memory encryption/decryption Compliant with FIPS Publication 197, Advanced Encryption Standard (AES) 128-bit cryptographic key On-The-Fly encryption/decryption 10 clock cycles encryption/decryption inherent processing time Double input buffer optimizes runtime Support of the three standard modes of operation specified in the NIST Special Publication 800-38A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques: - Electronic Code Book (ECB) - Cipher Block Chaining (CBC) including CBC-MAC - Counter (CTR) • Last Output Data mode allows optimized Message Authentication Code (MAC) generation 53.3 Product Dependencies 53.3.1 Power Management The AESB may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the AESB clock. 53.3.2 Interrupt The AESB interface has an interrupt line connected to the Interrupt Controller. Handling the AESB interrupt requires programming the Interrupt Controller before configuring the AESB. Table 53-1: 53.4 Peripheral IDs Instance ID AESB 13 Functional Description The Advanced Encryption Standard Bridge (AESB) specifies a FIPS-approved cryptographic algorithm that can be used to protect electronic data. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information. Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext converts the data back into its original form, called plaintext. The CIPHER bit in the AESB Mode Register (AESB_MR) allows selection between the encryption and the decryption processes. The AESB is capable of using cryptographic keys of 128 bits to encrypt and decrypt data in blocks of 128 bits. This 128-bit key is defined in the Key Registers (AESB_KEYWRx).  2017 Microchip Technology Inc. DS60001525A-page 1615 SAMA5D4 SERIES The input to the encryption processes of the CBC mode includes, in addition to the plaintext, a 128-bit data block called the initialization vector (IV), which must be set in the Initialization Vector Registers (AESB_IVRx). The initialization vector is used in an initial step in the encryption of a message and in the corresponding decryption of the message. The Initialization Vector Registers are also used by the CTR mode to set the counter value. 53.4.1 Operating Modes The AESB supports the following modes of operation: • ECB—Electronic Code Book • CBC—Cipher Block Chaining • CTR—Counter The data pre-processing, post-processing and data chaining for the operating modes are performed automatically. Refer to the NIST Special Publication 800-38A Recommendation for more complete information. The modes are selected by the OPMOD field in AESB_MR. In CTR mode, the size of the block counter embedded in the module is 16 bits. Therefore, there is a rollover after processing 1 megabyte of data. If the file to be processed is greater than 1 megabyte, this file must be split into fragments of 1 megabyte or less for the first fragment if the initial value of the counter is greater than 0. Prior to loading the first fragment into AESB_IDATARx registers, the AESB_IVRx registers must be cleared. For any fragment, after the transfer is completed and prior to transferring the next fragment, AESB_IVR0 must be programmed so that the fragment number (0 for the first fragment, 1 for the second one, and so on) is written in the 16 MSB of AESB_IVR0. If the initial value of the counter is greater than 0 and the data buffer size to be processed is greater than 1 megabyte, the size of the first fragment to be processed must be 1 megabyte minus 16x(initial value) to prevent a rollover of the internal 1-bit counter. 53.4.2 Double Input Buffer The input data register can be double-buffered to reduce the runtime of large files. This mode allows writing a new message block when the previous message block is being processed. The DUALBUFF bit in register AESB_MR must be set to 1 to access the double buffer. 53.4.3 Start Modes The SMOD field in register AESB_MR allows selection of the Encryption (or Decryption) Start mode. 53.4.3.1 Manual Mode The sequence is as follows: 1. 2. 3. Write AESB_MR with all required fields, including but not limited to SMOD and OPMOD. Write the 128-bit key in the Key Registers (AESB_KEYWRx). Write the initialization vector (or counter) in the Initialization Vector Registers (AESB_IVRx). Note: 4. 5. The Initialization Vector Registers concern all modes except ECB. Set the DATRDY (Data Ready) bit in the AESB Interrupt Enable Register (AESB_IER) depending on whether an interrupt is required, or not, at the end of processing. Write the data to be encrypted/decrypted in the authorized Input Data Registers (refer to Table 53-2). Table 53-2: 6. 7. 8. Authorized Input Data Registers Operating Mode Input Data Registers to Write ECB All CBC All CTR All Set the START bit in the AESB Control Register (AESB_CR) to begin the encryption or decryption process. When processing is complete, the DATRDY bit in the AESB Interrupt Status Register (AESB_ISR) raises. If an interrupt has been enabled by setting the DATRDY bit in AESB_IER, the interrupt line of the AESB is activated. When the software reads one of the Output Data Registers (AESB_ODATARx), the AESB_ISR.DATRDY bit is automatically cleared. DS60001525A-page 1616  2017 Microchip Technology Inc. SAMA5D4 SERIES 53.4.3.2 Auto Mode Auto mode is similar to Manual mode, except that in Auto mode, as soon as the correct number of Input Data registers is written, processing starts automatically without any action in the Control Register. 53.4.4 Last Output Data Mode Last Output Data mode is used to generate cryptographic checksums on data (MAC) by means of a cipher block chaining encryption algorithm (the CBC-MAC algorithm for example). After each end of encryption/decryption, the output data are available on the output data registers for Manual and Auto modes. The Last Output Data (LOD) bit in AESB_MR allows retrieval of only the last data of several encryption/decryption processes. Those data are only available on the Output Data Registers (AESB_ODATARx). 53.4.5 53.4.5.1 Manual and Auto Modes If AESB_MR.LOD = 0 The AESB_ISR.DATRDY bit is cleared when at least one of the Output Data Registers is read (refer to Figure 53-1). Figure 53-1: Manual and Auto Modes with AESB_MR.LOD = 0 Write START bit in AESB_CR (Manual mode) or Write AESB_IDATARx register(s) (Auto mode) Read the AESB_ODATARx DATRDY Encryption or Decryption Process If the user does not want to read the output data registers between each encryption/decryption, the AESB_ISR.DATRDY bit will not be cleared. If the AESB_ISR.DATRDY bit is not cleared, the user cannot know the end of the following encryptions/decryptions. 53.4.5.2 If AESB_MR.LOD = 1 The AESB_ISR.DATRDY bit is cleared when at least one Input Data Register is written, so before the start of a new transfer (refer to Figure 53-2). No more Output Data Register reads are necessary between consecutive encryptions/decryptions. Figure 53-2: Manual and Auto Modes with AESB_MR.LOD = 1 Write START bit in AESB_CR (Manual mode) or Write AESB_IDATARx register(s) (Auto mode) Write AESB_IDATARx register(s) DATRDY Encryption or Decryption Process  2017 Microchip Technology Inc. DS60001525A-page 1617 SAMA5D4 SERIES 53.4.6 53.4.6.1 Automatic Bridge Mode Description The Automatic Bridge mode, when the AESB block is connected between the system bus and a DDR port, provides automatic encryption/ decryption to/from a DDR port without any action on the part of the user. For Automatic Bridge mode, the OPMODE field must be configured to 0x4 in AESB_MR (refer to Section 53.6.2 “AESB Mode Register”). If bit AESB_MR.AAHB is set and field AESB_MR.OPMODE = 0x4, there is no compliance with the standard CTR mode of operation. In case of write transfer, this mode automatically encrypts the data before writing it to the final slave destination. In case of read transfer, this mode automatically decrypts the data read from the target slave before putting it on the system bus. Therefore, this mode does not work if the automatically encrypted data is moved at another address outside of the AESB IP scope. This means that for a given data, the encrypted value is not the same if written at different addresses. 53.4.6.2 Configuration The Automatic Bridge mode can be enabled by setting bit AESB_MR.AAHB. The IV (Initialization Vector) field of the AESB Initialization Vector Register x (AESB_IVRx) can be used to add a nonce in the encryption process in order to bring even more security (ignored if not filled). In this case, any value encrypted with a given nonce can only be decrypted with this nonce. If another nonce is set for the IV field, any value encrypted with the previous nonce cannot be decrypted anymore (refer to Section 53.6.10 “AESB Initialization Vector Register x”). Dual buffer usage (write a 1 to bit AESB_MR.DUALBUFF) is recommended for improved performance. 53.5 53.5.1 Security Features Unspecified Register Access Detection When an unspecified register access occurs, the URAD bit in AESB_ISR raises. Its source is then reported in the Unspecified Register Access Type (URAT) field. Only the last unspecified register access is available through the URAT field. Several kinds of unspecified register accesses can occur: • • • • • • Input Data Register written during the data processing when SMOD = IDATAR0_START Output Data Register read during data processing Mode Register written during data processing Output Data Register read during sub-keys generation Mode Register written during sub-keys generation Write-only register read access The URAD bit and the URAT field can only be reset by the SWRST bit in AESB_CR. DS60001525A-page 1618  2017 Microchip Technology Inc. SAMA5D4 SERIES 53.6 Advanced Encryption Standard Bridge (AESB) User Interface Table 53-3: Offset Register Mapping Register Name Access Reset 0x00 Control Register AESB_CR Write-only – 0x04 Mode Register AESB_MR Read/Write 0x0 Reserved – – – 0x10 Interrupt Enable Register AESB_IER Write-only – 0x14 Interrupt Disable Register AESB_IDR Write-only – 0x18 Interrupt Mask Register AESB_IMR Read-only 0x0 0x1C Interrupt Status Register AESB_ISR Read-only 0x0 0x20 Key Word Register 0 AESB_KEYWR0 Write-only – 0x24 Key Word Register 1 AESB_KEYWR1 Write-only – 0x28 Key Word Register 2 AESB_KEYWR2 Write-only – 0x2C Key Word Register 3 AESB_KEYWR3 Write-only – Reserved – – – 0x40 Input Data Register 0 AESB_IDATAR0 Write-only – 0x44 Input Data Register 1 AESB_IDATAR1 Write-only – 0x48 Input Data Register 2 AESB_IDATAR2 Write-only – 0x4C Input Data Register 3 AESB_IDATAR3 Write-only – 0x50 Output Data Register 0 AESB_ODATAR0 Read-only 0x0 0x54 Output Data Register 1 AESB_ODATAR1 Read-only 0x0 0x58 Output Data Register 2 AESB_ODATAR2 Read-only 0x0 0x5C Output Data Register 3 AESB_ODATAR3 Read-only 0x0 0x60 Initialization Vector Register 0 AESB_IVR0 Write-only – 0x64 Initialization Vector Register 1 AESB_IVR1 Write-only – 0x68 Initialization Vector Register 2 AESB_IVR2 Write-only – 0x6C Initialization Vector Register 3 AESB_IVR3 Write-only – Reserved – – – 0x08–0x0C 0x30–0x3C 0x70–0xFC  2017 Microchip Technology Inc. DS60001525A-page 1619 SAMA5D4 SERIES 53.6.1 AESB Control Register Name: AESB_CR Address:0xF0020000 Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – SWRST 7 6 5 4 3 2 1 0 – – – – – – – START START: Start Processing 0: No effect 1: Starts manual encryption/decryption process SWRST: Software Reset 0: No effect 1: Resets the AESB. A software triggered hardware reset of the AESB interface is performed. DS60001525A-page 1620  2017 Microchip Technology Inc. SAMA5D4 SERIES 53.6.2 AESB Mode Register Name: AESB_MR Address:0xF0020004 Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 11 10 9 – – CKEY 15 14 13 LOD 12 OPMOD 7 6 5 PROCDLY 4 8 SMOD 3 2 1 0 DUALBUFF AAHB – CIPHER CIPHER: Processing Mode 0: Decrypts data 1: Encrypts data AAHB: Automatic Bridge Mode 0: Automatic Bridge mode disabled 1: Automatic Bridge mode enabled DUALBUFF: Dual Input Buffer Value Name Description 0x0 INACTIVE AESB_IDATARx cannot be written during processing of previous block. 0x1 ACTIVE AESB_IDATARx can be written during processing of previous block when SMOD = 0x2. It speeds up the overall runtime of large files. PROCDLY: Processing Delay Processing Time = 12 × (PROCDLY + 1) The Processing Time represents the number of clock cycles that the AESB needs in order to perform one encryption/decryption . Note: The best performance is achieved with PROCDLY equal to 0. SMOD: Start Mode Value Name Description 0x0 MANUAL_STAR T Manual mode 0x1 AUTO_START Auto mode 0x2 IDATAR0_START AESB_IDATAR0 access only Auto mode Values which are not listed in the table must be considered as “reserved”.  2017 Microchip Technology Inc. DS60001525A-page 1621 SAMA5D4 SERIES OPMOD: Operating Mode Value Name Description 0x0 ECB Electronic Code Book mode 0x1 CBC Cipher Block Chaining mode 0x2 – Reserved 0x3 – Reserved 0x4 CTR Counter mode (16-bit internal counter) Values which are not listed in the table must be considered as “reserved”. For CBC-MAC operating mode, configure OPMOD to 0x1 (CBC) and set LOD to 1. Note: If the OPMODE field is set to 0x4 and AAHB = 1, there is no compliance with the standard CTR mode of operation. LOD: Last Output Data Mode 0: No effect. After each end of encryption/decryption, the output data will be available either on the output data registers (Manual and Auto modes). In Manual and Auto modes, the AESB_ISR.DATRDY bit is cleared when at least one of the Output Data registers is read. 1: The AESB_ISR.DATRDY bit is cleared when at least one of the Input Data Registers is written. No more Output Data Register reads are necessary between consecutive encryptions/decryptions (refer to Section 53.4.4 “Last Output Data Mode”). CKEY: Key Value 0xE Name Description PASSWD This field must be written with 0xE the first time that AES_MR is programmed. For subsequent programming of the AES_MR register, any value can be written, including that of 0xE.Always reads as 0. DS60001525A-page 1622  2017 Microchip Technology Inc. SAMA5D4 SERIES 53.6.3 AESB Interrupt Enable Register Name: AESB_IER Address:0xF0020010 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Enables the corresponding interrupt. DATRDY: Data Ready Interrupt Enable URAD: Unspecified Register Access Detection Interrupt Enable  2017 Microchip Technology Inc. DS60001525A-page 1623 SAMA5D4 SERIES 53.6.4 AESB Interrupt Disable Register Name: AESB_IDR Address:0xF0020014 Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: No effect. 1: Disables the corresponding interrupt. DATRDY: Data Ready Interrupt Disable URAD: Unspecified Register Access Detection Interrupt Disable DS60001525A-page 1624  2017 Microchip Technology Inc. SAMA5D4 SERIES 53.6.5 AESB Interrupt Mask Register Name: AESB_IMR Address:0xF0020018 Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – URAD 7 6 5 4 3 2 1 0 – – – – – – – DATRDY The following configuration values are valid for all listed bit names of this register: 0: The corresponding interrupt is not enabled. 1: The corresponding interrupt is enabled. DATRDY: Data Ready Interrupt Mask URAD: Unspecified Register Access Detection Interrupt Mask  2017 Microchip Technology Inc. DS60001525A-page 1625 SAMA5D4 SERIES 53.6.6 AESB Interrupt Status Register Name: AESB_ISR Address:0xF002001C Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – URAD URAT 7 6 5 4 3 2 1 0 – – – – – – – DATRDY DATRDY: Data Ready 0: Output data not valid. 1: Encryption or decryption process is completed. DATRDY is cleared when a Manual encryption/decryption occurs (START bit in AESB_CR) or when a software triggered hardware reset of the AESB interface is performed (SWRST bit in AESB_CR). AESB_MR.LOD = 0: In Manual and Auto modes, the DATRDY bit can also be cleared when at least one of the Output Data Registers is read. AESB_MR.LOD = 1: In Manual and Auto modes, the DATRDY bit can also be cleared when at least one of the Input Data Registers is written. URAD: Unspecified Register Access Detection Status 0: No unspecified register access has been detected since the last SWRST. 1: At least one unspecified register access has been detected since the last SWRST. URAD bit is reset only by the SWRST bit in AESB_CR. URAT: Unspecified Register Access Value Name Description 0x0 IDR_WR_PROCESSING Input Data Register written during the data processing when SMOD = 0x2 mode 0x1 ODR_RD_PROCESSING Output Data Register read during the data processing 0x2 MR_WR_PROCESSING Mode Register written during the data processing 0x3 ODR_RD_SUBKGEN Output Data Register read during the sub-keys generation 0x4 MR_WR_SUBKGEN Mode Register written during the sub-keys generation 0x5 WOR_RD_ACCESS Write-only register read access Only the last Unspecified Register Access Type is available through the URAT field. URAT field is reset only by the SWRST bit in AESB_CR. DS60001525A-page 1626  2017 Microchip Technology Inc. SAMA5D4 SERIES 53.6.7 AESB Key Word Register x Name: AESB_KEYWRx Address:0xF0020020 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 KEYW 23 22 21 20 KEYW 15 14 13 12 KEYW 7 6 5 4 KEYW KEYW: Key Word The four 32-bit Key Word registers set the 128-bit cryptographic key used for encryption/decryption. AESB_KEYWR0 corresponds to the first word of the key, AESB_KEYWR3 to the last one. These registers are write-only to prevent the key from being read by another application.  2017 Microchip Technology Inc. DS60001525A-page 1627 SAMA5D4 SERIES 53.6.8 AESB Input Data Register x Name: AESB_IDATARx Address:0xF0020040 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IDATA 23 22 21 20 IDATA 15 14 13 12 IDATA 7 6 5 4 IDATA IDATA: Input Data Word The four 32-bit Input Data registers set the 128-bit data block used for encryption/decryption. AESB_IDATAR0 corresponds to the first word of the data to be encrypted/decrypted, AESB_IDATAR3 to the last one. These registers are write-only to prevent the input data from being read by another application. DS60001525A-page 1628  2017 Microchip Technology Inc. SAMA5D4 SERIES 53.6.9 AESB Output Data Register x Name: AESB_ODATARx Address:0xF0020050 Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ODATA 23 22 21 20 ODATA 15 14 13 12 ODATA 7 6 5 4 ODATA ODATA: Output Data The four 32-bit Output Data registers contain the 128-bit data block that has been encrypted/decrypted. AESB_ODATAR0 corresponds to the first word, AESB_ODATAR3 to the last one.  2017 Microchip Technology Inc. DS60001525A-page 1629 SAMA5D4 SERIES 53.6.10 AESB Initialization Vector Register x Name: AESB_IVRx Address:0xF0020060 Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IV 23 22 21 20 IV 15 14 13 12 IV 7 6 5 4 IV IV: Initialization Vector The four 32-bit Initialization Vector registers set the 128-bit Initialization Vector data block that is used by some modes of operation as an additional initial input. AESB_IVR0 corresponds to the first word of the Initialization Vector, AESB_IVR3 to the last one. These registers are write-only to prevent the Initialization Vector from being read by another application. For CBC mode, the IV input value corresponds to the initialization vector. For CTR mode, the IV input value corresponds to the initial counter value. Note: These registers are not used in ECB mode and must not be written. For Automatic Bridge dedicated mode, the IV input value corresponds to the initial nonce. DS60001525A-page 1630  2017 Microchip Technology Inc. SAMA5D4 SERIES 54. Integrity Check Monitor (ICM) 54.1 Description The Integrity Check Monitor (ICM) is a DMA controller that performs hash calculation over multiple memory regions through the use of transfer descriptors located in memory (ICM Descriptor Area). The Hash function is based on the Secure Hash Algorithm (SHA). The ICM controller integrates two modes of operation. The first one is used to hash a list of memory regions and save the digests to memory (ICM Hash Area). The second mode is an active monitoring of the memory. In that mode, the hash function is evaluated and compared to the digest located at a predefined memory address (ICM Hash Area). If a mismatch occurs, an interrupt is raised. Refer to Figure 54-1 for an example of four-region monitoring. Hash and Descriptor areas are located in Memory instance i2, and the four regions are split in memory instances i0 and i1. Figure 54-1: Four-region Monitoring Example Processor Interrupt Controller ICM System Interconnect Memory i0 Memory Region 0 Memory Region 1 Memory i1 Memory i2 Memory Region 2 ICM Hash Area Memory Region 3 ICM Descriptor Area The ICM SHA engine is compliant with the American FIPS (Federal Information Processing Standard) Publication 180-2 specification. The following terms are concise definitions of the ICM concepts used throughout this document: • • • • Region—a partition of instruction or data memory space Region Descriptor—a data structure stored in memory, defining region attributes Region Attributes—region start address, region size, region SHA engine processing mode, Write Back or Compare function mode Context Registers—a set of ICM non-memory-mapped, internal registers which are automatically loaded, containing the attributes of the region being processed • Main List—a list of region descriptors. Each element associates the start address of a region with a set of attributes. • Secondary List—a linked list defined on a per region basis that describes the memory layout of the region (when the region is noncontiguous) • Hash Area—predefined memory space where the region hash results (digest) are stored 54.2 • • • • • Embedded Characteristics DMA AHB master interface Supports monitoring of up to 4 Non-Contiguous Memory Regions Supports block gathering through the use of linked list Supports Secure Hash Algorithm (SHA1, SHA224, SHA256) Compliant with FIPS Publication 180-2  2017 Microchip Technology Inc. DS60001525A-page 1631 SAMA5D4 SERIES • Configurable Processing Period: - When SHA1 algorithm is processed, the runtime period is either 85 or 209 clock cycles. - When SHA256 or SHA224 algorithm is processed, the runtime period is either 72 or 194 clock cycles. • Programmable Bus burden 54.3 Block Diagram Figure 54-2: Integrity Check Monitor Block Diagram APB Host Interface Configuration Registers SHA Hash Engine Context Registers Monitoring FSM Integrity Scheduler Master DMA Interface Bus Layer 54.4 Product Dependencies 54.4.1 Power Management The peripheral clock is not continuously provided to the ICM. The programmer must first enable the ICM clock in the Power Management Controller (PMC) before using the ICM. 54.4.2 Interrupt Sources The ICM interface has an interrupt line connected to the Interrupt Controller. Handling the ICM interrupt requires programming the interrupt controller before configuring the ICM. Table 54-1: Peripheral IDs Instance ID ICM 9 DS60001525A-page 1632  2017 Microchip Technology Inc. SAMA5D4 SERIES 54.5 54.5.1 Functional Description Overview The Integrity Check Monitor (ICM) is a DMA controller that performs SHA-based memory hashing over memory regions. As shown in Figure 54-2, it integrates a DMA interface, a Monitoring Finite State Machine (FSM), an integrity scheduler, a set of context registers, a SHA engine, an interface for configuration and status registers. The ICM integrates a Secure Hash Algorithm Engine (SHA). This engine requires a message padded according to FIPS180-2 specification when used as a SHA calculation unit only. Otherwise, if the ICM is used as integrated check for memory content, the padding is not mandatory. The SHA module produces an N-bit message digest each time a block is read and a processing period ends. N is 160 for SHA1, 224 for SHA224, 256 for SHA256. When the ICM module is enabled, it sequentially retrieves a circular list of region descriptors from the memory (Main List described in Figure 54-3). Up to four regions may be monitored. Each region descriptor is composed of four words indicating the layout of the memory region (refer to Figure 54-4). It also contains the hashing engine configuration on a per region basis. As soon as the descriptor is loaded from the memory and context registers are updated with the data structure, the hashing operation starts. A programmable number of blocks (refer to TRSIZE field of the ICM_RCTRL structure member) is transferred from the memory to the SHA engine. When the desired number of blocks have been transferred, the digest is whether moved to memory (Write Back function) or compared with a digest reference located in the system memory (Compare function). If a digest mismatch occurs, an interrupt is triggered if unmasked. The ICM module passes through the region descriptor list until the end of the list marked by an End of List bit set to one. To continuously monitor the list of regions, the WRAP bit must be set to one in the last data structure. Figure 54-3: ICM Region Descriptor and Hash Areas Main List infinite loop when wrap bit is set End of Region N WRAP=1 Region N Descriptor ICM Descriptor Area - Contiguous Read-only Memory Secondary List End of Region 1 List WRAP=0 Region 1 Descriptor End of Region 0 WRAP=0 Region 0 Descriptor Region N Hash ICM Hash Area Contiguous Read-write once Memory Region 1 Hash Region 0 Hash Each region descriptor supports gathering of data through the use of the Secondary List. Unlike the Main List, the Secondary List cannot modify the configuration attributes of the region. When the end of the Secondary List has been encountered, the ICM returns to the Main List. Memory integrity monitoring can be considered as a background service and the mandatory bandwidth shall be very limited. In order to limit the ICM memory bandwidth, use the BBC field of the ICM_CFG register to control ICM memory load.  2017 Microchip Technology Inc. DS60001525A-page 1633 SAMA5D4 SERIES Figure 54-4: Region Descriptor Main List Region 3 Descriptor Region 2 Descriptor Optional Region 0 Secondary List Region 1 Descriptor ICMDSCR Region 0 Descriptor End of Region 0 0x00C Region NEXT 0x00C Region NEXT 0x008 Region CTRL 0x008 Region CTRL 0x004 Region CFG 0x004 Unused 0x000 Region ADDR 0x000 Region ADDR Figure 54-5 shows an example of the mandatory ICM settings to monitor three memory data blocks of the system memory (defined as two regions) with one region being not contiguous (two separate areas) and one contiguous memory area. For each said region, the SHA algorithm may be independently selected (different for each region). The wrap allows continuous monitoring. DS60001525A-page 1634  2017 Microchip Technology Inc. SAMA5D4 SERIES Figure 54-5: Example: Monitoring of 3 Memory Data Blocks (Defined as 2 Regions) Size of region1 block (S1) R S i egi Bl n g on oc l e 1 k Da ta System Memory, data areas System Memory, region descriptor structure wrap=1 effect NEXT=0 R D egi at o n a Bl 0 oc k 1 Size of region0 block 1 (S0B1) @md+24 S1 wrap=1, etc @md+20 @md+16 @r1d @r1d 3 2 1 @r0db1 3 NEXT=@sd @md+12 @md+8 S0B0 wrap=0, etc @md+4 @r0db0 @md Region 1 Single Descriptor Region 0 Main Descriptor 1 2 NEXT=0 R D egi at o n a Bl 0 oc k 0 S0B1 Size of region0 block 0 (S0B0) @md+28 don’t care @r0db1 @sd+12 @sd+8 @sd+4 @sd Region 0 Second Descriptor @r0db0 54.5.2 ICM Region Descriptor Structure The ICM Region Descriptor Area is a contiguous area of system memory that the controller and the processor can access. When the ICM controller is activated, the controller performs a descriptor fetch operation at *(ICM_DSCR) address. If the Main List contains more than one descriptor (i.e., more than one region is to be monitored), the fetch address is *(ICM_DSCR) + (RID 100 kHz tHIGH — µs fTWCK ≤ 100 kHz tHIGH — µs fTWCK > 100 kHz tHIGH — µs fTWCK ≤ 100 kHz 0 (HOLD + 3) × tperipheral µs fTWCK > 100 kHz 0 fTWCK ≤ 100 kHz tLOW - (HOLD + 3) × tperipheral clock — ns fTWCK > 100 kHz tLOW - (HOLD + 3) × tperipheral clock — ns fTWCK ≤ 100 kHz tHIGH — µs fTWCK > 100 kHz tHIGH — µs fTWCK ≤ 100 kHz tLOW — µs fTWCK > 100 kHz tLOW — µs clock Data Hold Time tsu(data) Data Setup Time tsu(stop) Setup time for STOP condition tBUF Bus free time between a STOP and START condition (HOLD + 3) × tperipheral µs clock Note 1: Required only for fTWCK > 100 kHz 2: Cb = capacitance of one bus line in pF. Per I2C Standard, Cb Max = 400 pF 3: The TWCK low period is defined as follows: tLOW = ((CLDIV × 2CKDIV) + 3) × tMCK 4: The TWCK high period is defined as follows: tHIGH = ((CHDIV × 2CKDIV) + 3) × tMCK DS60001525A-page 1696  2017 Microchip Technology Inc. SAMA5D4 SERIES 57. Mechanical Characteristics 57.1 361-ball TFBGA Mechanical Characteristics Figure 57-1: 361-ball TFBGA Package Drawing  2017 Microchip Technology Inc. DS60001525A-page 1697 SAMA5D4 SERIES Table 57-1: 361-ball TFBGA Package Characteristics Moisture Sensitivity Level Table 57-2: Device and 361-ball TFBGA Package Maximum Weight 490 Table 57-3: 3 mg Package Reference JEDEC Drawing Reference MO-275-LLAC-1 J-STD-609 Classification e8 Table 57-4: Package Information Ball Land 0.45 mm ± 0.05 Nominal Ball Diameter 0.4 mm Solder Mask Opening 0.35 mm ± 0.05 Solder Mask Definition SMD Solder LF35 DS60001525A-page 1698  2017 Microchip Technology Inc. SAMA5D4 SERIES 57.2 289-ball LFBGA Mechanical Characteristics Figure 57-2: 289-ball LFBGA Package Drawing  2017 Microchip Technology Inc. DS60001525A-page 1699 SAMA5D4 SERIES Table 57-5: 289-ball LFBGA Package Characteristics Moisture Sensitivity Level Table 57-6: Device and 289-ball LFBGA Package Maximum Weight 450 Table 57-7: 3 mg Package Reference JEDEC Drawing Reference MO-275-JJAC-1 J-STD-609 Classification e8 Table 57-8: Package Information Ball Land 0.45 mm ± 0.05 Nominal Ball Diameter 0.4 mm Solder Mask Opening 0.35 mm ± 0.05 Solder Mask Definition SMD Solder LF35 DS60001525A-page 1700  2017 Microchip Technology Inc. SAMA5D4 SERIES 58. Schematic Checklist The schematic checklist provides the user with the requirements regarding the different pin connections that must be considered before starting any new board design. It also provides information on the minimum hardware resources required to quickly develop an application with the SAMA5D4. It does not consider PCB layout constraints. It also provides recommendations regarding low-power design constraints to minimize power consumption. This information is not intended to be exhaustive. Its objective is to cover as many configurations of use as possible. The checklist contains a column for use by designers, making it easy to track and verify each line item.  2017 Microchip Technology Inc. DS60001525A-page 1701 SAMA5D4 SERIES 58.1 Power Supply CAUTION: The board design must comply with the powerup and powerdown sequence guidelines provided in the datasheet to guarantee reliable operation of the device. Figure 58-1: 1.2V, 1.8V, 2V, 2.5V, 3.3V Power Supplies Schematics (1) 10μH VDDOSC 1R 100nF 4.7μF PMIC DC/DC GNDOSC VDDIOM 100nF 3.3V GNDIOM VDDIOP 100nF GNDIOP VDDUTMII 100nF GNDUTMI VDDCORE DC/DC 10μF 5V 100nF GNDCORE 1.8V VDDIODDR 10μF 100nF GNDIODDR LDO VDDFUSE 100nF 2.5V GNDFUSE LDO VDDANA 3.3V 100nF GNDANA LDO VDDBU 2V 100nF GNDBU VCCCORE 10μF LDO 100nF SAMA5D4 GNDCORE VDDPLLA 100nF VCCCORE GNDPLL VDDUTMIC 100nF GNDUTMI Note 1: These values are given only as a typical example. DS60001525A-page 1702  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 58-1: Power Supply Connections Signal Name Recommended Pin Connection 1.62 V to 1.98 V VDDCORE Decoupling/Filtering capacitors (10 µF and 100 nF)(1)(2) Description Powers the regulator that generates core power supply on VCCCORE. Must be established after VDDIOP and VDDANA. Decoupling/filtering capacitors must be added to improve startup stability and reduce source voltage drop. Supply ripple must not exceed 20 mVrms. 1.16 V to 1.32 V VCCCORE Decoupling/Filtering capacitors (10 µF and 100 nF)(1)(2) VDDIODDR VCCCORE is supplied by the SAMA5D4 internal regulator and powers the internal logic. 1.70 V to 1.90 V Powers the DDR2 Interface I/O lines. or or 1.14 V to 1.30 V Powers the LPDDR2 Interface I/O lines. Decoupling/Filtering capacitors Decoupling/filtering capacitors must be added to improve startup stability and reduce source voltage drop. (10 µF and 100 nF)(1)(2) Powers the NAND and HSMC Interface I/O lines. VDDIOM 1.65 V to 1.95 V Dual voltage range is supported. or The I/O drives are selected by programming the DRIVE0 and DRIVE1 fields in the SFR_EBICFG register. 3.0 V to 3.6 V Decoupling capacitor (100 nF)(1)(2) Decoupling/filtering capacitors must be added to improve startup stability and reduce source voltage drop. Powers the peripherals I/O lines. VDDIOP(3) VDDBU 3.0 V to 3.6 V Must be established prior to VDDCORE. Decoupling capacitors (100 nF)(1)(2) Decoupling/filtering capacitors must be added to improve startup stability and reduce source voltage drop. 1.8 V to 2.6 V Powers the Slow Clock oscillator, the internal 64 kHz RC and a part of the System Controller. Decoupling capacitor (100 nF)(1)(2) Must be established first. Supply ripple must not exceed 30 mVrms. VDDUTMIC VDDUTMII  2017 Microchip Technology Inc. 1.1 V to 1.32 V Decoupling capacitors (100 nF)(1)(2) 3.0 V to 3.6 V Decoupling capacitor (100 nF)(1)(2) Powers the USB device and host UTMI+ core and the UTMI PLL. Must be connected to VCCCORE. Decoupling/filtering capacitors must be added to improve startup stability and reduce source voltage drop. Powers the USB device and host UTMI+ interface. Decoupling/filtering capacitors must be added to improve startup stability and reduce source voltage drop. DS60001525A-page 1703 SAMA5D4 SERIES Table 58-1: Power Supply Connections (Continued) Signal Name Recommended Pin Connection Description Powers the PLLA cell. Must be connected to VCCCORE. VDDPLLA 1.1 V to 1.32 V Decoupling capacitor (100 nF) (1)(2) The VDDPLLA power supply pin draws small current, but it is noise sensitive. Care must be taken in VDDPLLA power supply routing, decoupling and also on bypass capacitors. Supply ripple must not exceed 10 mVrms. Powers the main oscillator cell. VDDOSC 3.0 V to 3.6 V Decoupling/Filtering RLC circuit(1) The VDDOSC power supply pin is noise-sensitive. Care must be taken in VDDOSC power supply routing, decoupling and also on bypass capacitors. Supply ripple must not exceed 30 mVrms. 3.0 V to 3.6 V VDDANA (3) VDDFUSE GNDCORE GNDIODDR GNDIOM Decoupling capacitor (100 nF) Powers the analog parts. (1)(2) Must rise at same time as VDDIOP. Application-dependent Can be connected to VDDIOP with filtering. 2.25 V to 2.75 V Powers the fuse box for programming. Decoupling capacitor (100 nF)(1)(2) VDDFUSE must not be left floating. Core Chip ground DDR2/LPDDR/LPDDR2 interface I/O lines ground NAND and HSMC Interface I/O lines ground GNDCORE pins are common to VDDCORE and VCCCORE pins. GNDCORE pins should be connected as shortly as possible to the system ground plane. GNDIODDR pins should be connected as shortly as possible to the system ground plane. GNDIOM pins should be connected as shortly as possible to the system ground plane. GNDIOP pins are common to VDDIOP pins. GNDIOP Peripherals and ISI I/O lines ground GNDBU Backup ground GNDUTMI UDPHS and UHPHS UTMI+ Core and interface ground GNDPLL PLLA cell ground GNDOSC PLLUTMI and Oscillator ground GNDIOP pins should be connected as shortly as possible to the system ground plane. GNDBU pin is provided for VDDBU pins. GNDBU pin should be connected as shortly as possible to the system ground plane. GNDUTMI pins are common to VDDUTMII and VDDUTMIC pins. GNDUTMI pins should be connected as shortly as possible to the system ground plane. GNDPLL pin is provided for VDDPLLA pins. GNDPLL pin should be connected as shortly as possible to the system ground plane. GNDOSC pin is provided for VDDOSC pins. DS60001525A-page 1704 GNDOSC pin should be connected as shortly as possible to the system ground plane.  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 58-1: Power Supply Connections (Continued) Signal Name Recommended Pin Connection GNDANA Analog ground GNDFUSE Fuse box ground Description GNDANA pins are common to VDDANA pins. GNDANA pins should be connected as shortly as possible to the system ground plane. GNDFUSE pins are common to VDDFUSE pins. GNDFUSE pins should be connected as shortly as possible to the system ground plane. Note 1: These values are given only as a typical example. 2: Decoupling capacitors must be connected as close as possible to the microprocessor and on each corresponding pin. 100nF VDDCORE 100nF VDDCORE 100nF VDDCORE GND 3: Must rise at the same time as VDDIOP. This specific power sequence ensures a reliable operation of the device.  2017 Microchip Technology Inc. DS60001525A-page 1705 SAMA5D4 SERIES 58.2 Clock, Oscillator and PLL Table 58-2: Clock, Oscillator and PLL Connections Signal Name Recommended Pin Connection Description Crystal Load Capacitance to check (CCRYSTAL). SAMA5D4 XIN XOUT GNDOSC Crystals between 8 and 16 MHz XIN XOUT 12 MHz Main Oscillator in Normal Mode USB High Speed (not Full Speed) Host and Device peripherals need a 12 MHz clock. Capacitors on XIN and XOUT (Crystal Load Capacitance-dependent) CCRYSTAL CLEXT CLEXT Example: for a 12 MHz crystal with a load capacitance of CCRYSTAL = 15 pF, external capacitors are required: CLEXT = 22 pF. Refer to Section 56. “Electrical Characteristics”. XIN XIN: external clock source XOUT XOUT: can be left unconnected VDDOSC square wave signal External clock source up to 50 MHz 12 MHz Main Oscillator in Bypass Mode USB High speed (not Full Speed) Host and Device peripherals need a 12 MHz clock. XIN XIN: can be left unconnected XOUT XOUT: can be left unconnected 12 MHz Main Oscillator Disabled USB High Speed (not Full Speed) Host and Device peripherals need a 12 MHz clock. DS60001525A-page 1706 Duty Cycle: 40 to 60% Refer to Section 56. “Electrical Characteristics”. Typical nominal frequency 12 MHz (Internal 12 MHz RC Oscillator) Duty Cycle: 45 to 55% Refer to Section 56. “Electrical Characteristics”.  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 58-2: Clock, Oscillator and PLL Connections (Continued) Signal Name Recommended Pin Connection Description Crystal load capacitance to check (CCRYSTAL32). SAMA5D4 XIN32 XIN32 XOUT32 Slow Clock Oscillator XOUT32 GNDBU 32.768 kHz Crystal C CRYSTAL32 Capacitors on XIN32 and XOUT32 (Crystal Load Capacitance-dependent) CLEXT32 CLEXT32 Example: for a 32.768 kHz crystal with a load capacitance of CCRYSTAL32 = 12.5 pF, external capacitors are required: CLEXT32 = 19 pF. Refer to Section 56. “Electrical Characteristics”. XIN32 VDDBU square wave signal XOUT32 Slow Clock Oscillator in Bypass Mode XIN32: external clock source External clock source up to 44 kHz XOUT32: can be left unconnected Duty Cycle: 40 to 60% Refer to Section 56. “Electrical Characteristics”. XIN32 XIN32: can be left unconnected Typical nominal frequency 32 kHz (internal 32 kHz RC oscillator) XOUT32: can be left unconnected Duty Cycle: 45 to 55% XOUT32 Slow Clock Oscillator Disabled  2017 Microchip Technology Inc. Refer to Section 56. “Electrical Characteristics”. DS60001525A-page 1707 SAMA5D4 SERIES Table 58-2: Clock, Oscillator and PLL Connections (Continued) Signal Name Recommended Pin Connection Description Bias Voltage Reference for USB To minimize noise on the VBG pin, it is recommended to configure the following layout: - VBG path as short as possible - ground connection to GNDUTMI VBG 0.9–1.1V(2) 5K62 ± 1% Ω VBG 10 pF GNDUTMI VBG can be left unconnected if USB is not used. Refer to Section 2. “Signal Description”. DS60001525A-page 1708  2017 Microchip Technology Inc. SAMA5D4 SERIES 58.3 ICE and JTAG Table 58-3: ICE and JTAG Connections(1) Signal Name Recommended Pin Connection TCK Pullup (100 kΩ)(2) TMS Pullup (100 kΩ)(2) TDI Pullup (100 kΩ)(2) TDO Floating NTRST Refer to the pin description section. Description This pin is a Schmitt trigger input. Internal pullup resistor to VDDIOP (100 kΩ). This pin is a Schmitt trigger input. Internal pullup resistor to VDDIOP (100 kΩ). This pin is a Schmitt trigger input. Internal pullup resistor to VDDIOP (100 kΩ). Output driven at up to VDDIOP. This pin is a Schmitt trigger input. Internal pullup resistor to VDDIOP (100 kΩ). (3) JTAGSEL In harsh environments , it is strongly recommended to tie this pin to GNDBU if not used or to add an external low-value resistor (such as 1 kΩ). Internal pulldown resistor to GNDBU (15 kΩ). Must be tied to VDDBU to enter JTAG Boundary Scan. Note 1: It is recommended to establish accessibility to a JTAG connector for debug in any case. 2: These values are given only as a typical example. 3: In a well-shielded environment subject to low magnetic and electric field interference, the pin may be left unconnected. In noisy environments, a connection to ground is recommended. 58.4 Reset and Test Table 58-4: Reset and Test Connections Signal Name Recommended Pin Connection Application-dependent. NRST TST Can be connected to a push button for hardware reset. In harsh environments(1), it is strongly recommended to tie this pin to GNDBU to add an external low-value resistor (such as 10 kΩ). Description NRST pin is a Schmitt trigger input. No internal pullup resistor. This pin is a Schmitt trigger input. Internal pulldown resistor to GNDBU (15 kΩ). Note 1: In a well-shielded environment subject to low magnetic and electric field interference, the pin may be left unconnected. In noisy environments, a connection to ground is recommended.  2017 Microchip Technology Inc. DS60001525A-page 1709 SAMA5D4 SERIES 58.5 Shutdown/Wakeup Logic Table 58-5: Shutdown/Wakeup Logic Connections Signal Name Recommended Pin Connection Description Application-dependent. A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies. SHDN WKUP 58.6 0 V to VDDBU This pin is a push-pull output. SHDN pin is driven low to GNDBU by the Shutdown Controller (SHDWC). This pin is an input-only. WKUP behavior can be configured through the Shutdown Controller (SHDWC). Parallel Input/Output (PIO) Table 58-6: PIO Connections Signal Name Recommended Pin Connection Description All PIOs are pulled-up inputs (100 kΩ) at reset except those which are multiplexed with the Address Bus signals that require to be enabled as peripherals: PAx In Section 3. “Package and Pinout”, refer to the column ‘Reset State’ of the Pin Description table. PBx PCx Application-dependent. Schmitt trigger on all inputs. PDx PEx To reduce power consumption if not used, the concerned PIO can be configured as an output, driven at ‘0’ with internal pullup disabled. 58.7 Analog-to-Digital Converter (ADC) Table 58-7: ADC Connections Signal Name ADVREF Recommended Pin Connection Description 3.3 V to VDDANA ADVREF is a pure analog input. Decoupling/filtering capacitors. To reduce power consumption if the ADC is not used, connect ADVREF to GNDANA. Application-dependent. 58.8 External Bus Interface (EBI) Table 58-8: EBI Connections Signal Name Recommended Pin Connection D0–D15 Application-dependent. A0–A25 Application-dependent. Description Data Bus (D0 to D15) All data lines are pulled-up inputs to VDDIOM at reset. Address Bus (A0 to A25) All address lines are driven to ‘0’ at reset. Table 58-9 and Table 58-10 detail the connections to be applied between the EBI pins and the external devices for each Memory Controller. DS60001525A-page 1710  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 58-9: EBI Pins and External Static Devices Connections Pins of the Interfaced Device 8-bit Static Device Signals: EBI_ 16-bit Static Device 2 x 8-bit Static Devices Controller SMC (Static Memory Controller) D0–D7 D0–D7 D0–D7 D0–D7 D8–D15 – D8–D15 D8–D15 A0/NBS0 A0 – NLB A1 A1 A0 A0 A2–A22 A[2:22] A[1:21] A[1:21] A23–A25 A[23:25] A[22:24] A[22:24] NCS0 CS CS CS NCS1 CS CS CS NCS2 CS CS CS NCS3/NANDCS CS CS CS NRD/NANDOE OE OE OE NWE/NWR0/NANDWE NWR1/NBS1 (1) WE – WE WE WE(1) NUB Note 1: NWR0 enables lower byte writes. NWR1 enables upper byte writes. Table 58-10: EBI Pins and NAND Flash Device Connections Signals: EBI_ Pins of the Interfaced Device 8-bit NAND Flash Controller 16-bit NAND Flash NFC (NAND Flash Controller) D0–D7 NFD0–NFD7 NFD0–NFD7 D8–D15 – NFD8–NFD15 A21/NANDALE ALE ALE A22/NANDCLE CLE CLE NRD/NANDOE RE RE NWE/NWR0/NANDWE WE WE NCS3/NANDCS CE CE NANDRDY R/B R/B A0/NBS0 – – A1–A20 – – A23–A25 – – NWR1/NBS1 – – NCS0 – –  2017 Microchip Technology Inc. DS60001525A-page 1711 SAMA5D4 SERIES Table 58-10: EBI Pins and NAND Flash Device Connections Pins of the Interfaced Device Signals: EBI_ 8-bit NAND Flash Controller 16-bit NAND Flash NFC (NAND Flash Controller) NCS1 – – NCS2 – – NWAIT – – 58.9 DDR2 Bus Interface Table 58-11: DDR2 I/O Lines Usage vs Operating Modes Signal Name DDR2 Mode LPDDR2 Mode LPDDR Controller MPDDRC (Multi-port DDR-SDRAM Controller) DDR_VREF VDDIODDR/2 VDDIODDR/2 VDDIODDR/2 DDR_CALP GND via 200Ω resistor GND via 240Ω resistor GND via 200Ω resistor DDR_CALN VDDIODDR via 200Ω resistor VDDIODDR via 240Ω resistor VDDIODDR via 200Ω resistor DDR_CK, DDR_CKN CLK and CLKN CLK and CLKN CLK and CLKN DDR_CKE CLKE CLKE CLKE DDR_CS CS CS CS DDR_BA[2..0] BA[2..0] BA[2..0] BA[2..0] DDR_WE WE CA2 WE DDR_RAS–DDR_CAS RAS, CAS CA0, CA1 RAS, CAS DDR_A[13..0] A[13:0] CAx, with x>2 A[13:0] DDR_D[31..0] D[31:0] D[31:0] D[31:0] DQS[3..0], DQSN[3..0] DQS[3:0] DQSN[3:0] DQS[3:0] DQSN[3:0] DQS[3:0] DQSN connected to DDR_VREF DQM[3..0] DQM[3..0] DQM[3..0] DQM[3..0] 58.10 USB High-Speed Host Port (UHPHS)/USB High-Speed Device Port (UDPHS) Table 58-12: UHPHS/UDPHS Connections Signal Name Recommended Pin Connection Description HHSDMA/ DHSDM(1) Application-dependent(2)(3) Pulldown output at reset. HHSDPB/HHSDMB Application-dependent(2) Pulldown output at reset. HHSDPC/HHSDMC Application-dependent(2) Pulldown output at reset. HHSDPA/DHSDP(1) Note 1: UDPHS shares Port A with UHPHS. 2: Example of USB High Speed Host connection: Refer to Section 36. “USB Host High Speed Port (UHPHS)”. DS60001525A-page 1712  2017 Microchip Technology Inc. SAMA5D4 SERIES PIO (VBUS ENABLE) “A” Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND +5V HHSDM/HFSDM 3 4 Shell = Shield 1 2 HHSDP/HFSDP 5K62 ± 1% Ω VBG 10 pF GNDUTMI 3: Typical USB High Speed Device connection: Refer to Section 35. “USB High Speed Device Port (UDPHS)”. PIO (VBUS DETECT) 15k Ω (1) “B” Receptacle 1 = VBUS 2 = D3 = D+ 4 = GND 1 2 3 4 DHSDM/DFSDM Shell = Shield (1) 22k Ω CRPB CRPB:1μF to 10μF DHSDP/DFSDP 5K62 ± 1%Ω VBG 10 pF GNDUTMI (1) The values shown on the 22 kΩ and 15 kΩ resistors are only valid with 3.3V supplied PIOs. 58.11 Boot Program Hardware Constraints Refer to Section 12. “Standard Boot Strategies” for more details on the boot program. 58.11.1 Boot Program Supported Crystals (MHz) A 12 MHz crystal or external clock (in bypass mode) is mandatory in order to generate USB and PLL clocks correctly for the following boots.  2017 Microchip Technology Inc. DS60001525A-page 1713 SAMA5D4 SERIES 58.11.2 NAND Flash Boot Boot is possible if the first page contains a valid header or if it is ONFI compliant. For more details, refer to Section 12.4.4.1 “NAND Flash Boot: NAND Flash Detection”. Table 58-13: Pins Driven during NAND Flash Boot Program Execution Peripheral Pin PIO Line EBI CS3 SMC NANDOE PC13 EBI CS3 SMC NANDWE PC14 EBI CS3 SMC NANDCS PC15 EBI CS3 SMC NANDRDY PC16 EBI CS3 SMC NANDALE PC17 EBI CS3 SMC NANDCLE PC18 EBI CS3 SMC Cmd/Addr/Data – 58.11.3 SD Card Boot SD card boot supports all SD card memories compliant with SD Memory Card Specification V2.0. This includes SDHC cards. Table 58-14: Pins Driven During SD Card Boot Program Execution Peripheral Pin PIO Line MCI1 MCI1_CK PE18 MCI1 MCI1_CDA PE19 MCI1 MCI1_D0 PE20 MCI1 MCI1_D1 PE21 MCI1 MCI1_D2 PE22 MCI1 MCI1_D3 PE23 Note: 58.11.4 The MCI1 pins are pulldown by default (typical value 70 kΩ). To function correctly, the signals require an external pullup resistor and the internal pulldown resistor must be disabled. Serial and DataFlash Boot Two kinds of SPI Flash are supported: SPI Serial Flash and SPI DataFlash. The SPI Flash bootloader tries to boot on SPI0 Chip Select 0, first looking for SPI Serial Flash, and then for SPI DataFlash. The SPI Flash Boot program supports: • All SPI Serial Flash devices • All DataFlash devices Table 58-15: Pins Driven During Serial or DataFlash Boot Program Execution Peripheral Pin PIO Line SPI0 MOSI PC1 SPI0 MISO PC0 SPI0 SPCK PC2 SPI0 NPCS0 PC3 SPI0 NPCS1 PC4 DS60001525A-page 1714  2017 Microchip Technology Inc. SAMA5D4 SERIES 58.11.5 TWI EEPROM Boot The TWI EEPROM Flash boot program searches for a valid application in an EEPROM memory. TWI EEPROM boot supports all I2C-compatible EEPROM memories using 7-bit device (address 0x50). Table 58-16: Pins Driven During TWI EEPROM Boot Program Execution Peripheral Pin PIO Line TWI0 TWD0 PA30 TWI0 TWCK0 PA31 58.11.6 SAM-BA Boot The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device Port. Table 58-17: Pins Driven During SAM-BA Boot Program Execution Peripheral Pin PIO Line DBGU DRXD PB24 DBGU DTXD PB25  2017 Microchip Technology Inc. DS60001525A-page 1715 SAMA5D4 SERIES 59. Marking All devices are marked with the company logo and the ordering code. Additional marking is as follows: YYWWC V XXXXXXX ARM where • • • • • “YY”: Manufactory year “WW”: Manufactory week “C”: Assembly country code (optional) “V”: Revision “XXXXXXX”: Lot number DS60001525A-page 1716  2017 Microchip Technology Inc. SAMA5D4 SERIES 60. Ordering Information Table 60-1: Ordering Information Ordering Code ATSAMA5D44A-CU MRL Package A Carrier Type Operating Temperature Range Tray TFBGA361 ATSAMA5D44A-CUR A ATSAMA5D43A-CU A Tape and Reel Tray LFBGA289 ATSAMA5D43A-CUR A ATSAMA5D42A-CU A Tape and Reel Tray TFBGA361 ATSAMA5D42A-CUR A ATSAMA5D41A-CU A Tape and Reel Tray LFBGA289 ATSAMA5D41A-CUR ATSAMA5D44B-CU A B Tape and Reel Industrial Tray -40°C to 85°C TFBGA361 ATSAMA5D44B-CUR B ATSAMA5D43B-CU B Tape and Reel Tray LFBGA289 ATSAMA5D43B-CUR B ATSAMA5D42B-CU B Tape and Reel Tray TFBGA361 ATSAMA5D42B-CUR B ATSAMA5D41B-CU B Tape and Reel Tray LFBGA289 ATSAMA5D41B-CUR  2017 Microchip Technology Inc. B Tape and Reel DS60001525A-page 1717 SAMA5D4 SERIES 61. Errata Errata are described in the following sections: Section 61.1 “Errata - SAMA5D4 MRL B Parts” Section 61.2 “Errata - SAMA5D4 MRL A Parts” 61.1 Errata - SAMA5D4 MRL B Parts This section describes errata relevant to the devices listed in the following table. Table 61-1: Ordering Information Device Name ATSAMA5D44B ATSAMA5D43B ATSAMA5D42B ATSAMA5D41B 61.1.1 61.1.1.1 Standard Boot Strategies Boot ROM: Xmodem is Not Working Due to a bug in the ROM code, Xmodem is not working. Problem Fix/Workaround None. 61.1.2 61.1.2.1 LCD Controller (LCDC) LCDC PWM Is Not Usable with DIV_1 When field PWMPS in register LCDC_LCDCFG6 is set to DIV_1 value, the PWM output is stuck. The LCDC PWM works correctly for the dividers DIV_2 up to DIV_64. Problem Fix/Workaround None. 61.1.3 61.1.3.1 ADC (Analog-to-Digital Controller) Compare Window limitations in user sequence When USEQ = 1 in ADC_MR and CMPALL = 0 in ADC_EMR, the compare window function does not work for all sequences programmed into ADC_SEQR1 and ADC_SEQR2. Problem Fix/Workaround To have a correct compare window function on a given channel X selected by means of CMPSEL = X in ADC_EMR, the ADC_CHSR[X] must be set. For example, if ADC_CHSR = 0x0000_000F and ADC_SEQ1R = 0x0000_3300, both channel index 0 and 3 can be used for comparison (i.e., CMPSEL = 0 and CMPSEL = 3 can be used, COMPE flag will behave correctly in ADC_ISR). If ADC_CHSR = 0x0000_000F and ADC_SEQ1R = 0x0000_1100, both channel index 0 and 1 can be used for comparison (i.e., CMPSEL = 0 and CMPSEL = 1 can be used, COMPE flag will behave correctly in ADC_ISR). If ADC_CHSR = 0x0000_000F and ADC_SEQ1R = 0x0000_4400, only channel index 0 can be used for comparison (i.e., CMPSEL = 0 can be used, COMPE flag will behave correctly in ADC_ISR). Channel 4 cannot be used for comparison because ADC_CHSR[4] = 0. DS60001525A-page 1718  2017 Microchip Technology Inc. SAMA5D4 SERIES 61.1.3.2 Differential mode limitations in user sequence If Differential mode is used with user sequence, the analog pad configuration is not the one expected. For instance, if USCH4 is set to channel 2, the user must configure DIFF2 to enable differential mode on channel 2 (this is the expected behavior). However, due to this bug the ADC Controller will look at the DIFF4 state instead the DIFF2 state. Problem Fix/Workaround Set the differential mode on the DIFFx bit corresponding to the related sequence number instead of setting the differential mode on the DIFFx bit of the related channel number. 61.1.3.3 Calibration issue after Sleep Mode Calibration does not work after exiting sleep state. The sleep state is entered when the SLEEP bit in ADC_MR is set or if all channels are disabled after a first series of conversion. Problem Fix/Workaround 1. 2. 3. If the SLEEP bit is set in ADC_MR and a new calibration is required at anytime, the SLEEP bit must first be disabled after which a dummy conversion must be performed. At the end of the conversion (EOC) a new calibration can be started. At the end of the calibration, the SLEEP bit can be set again to 1 and normal conversions can again be performed. If the SLEEP bit is not used but all channels are disabled at any time, the equivalent of the “sleep” state is reached by the internal finite state machine of the ADC controller. Therefore a dummy conversion must be performed, after which the calibration can be performed. The Soft reset command can be performed prior to start a calibration but the configuration of all channels is cleared and must be reprogrammed. 61.1.4 61.1.4.1 Multi-port DDR-SDRAM Controller (MPDDRC) LPDDR2 Refresh Per Bank Not Functional The refresh per bank feature for 8-bank LPDDR2 memories is not functional. The REF_PB bit in the MPDDRC_RTR must be set to 0 (reset value). Problem Fix/Workaround None. 61.1.4.2 Scrambling/Unscrambling Feature Not Supported On All Devices The external data bus scrambling/unscrambling feature is only available on 32-bit memory devices connected on the external bus interface. Problem Fix/Workaround None. 61.1.4.3 MPDDRC_TPR1 Incoherency Between Write and Read Value The value read in register MPDDRC_TRP1 does not correspond to the written value. Problem Fix/Workaround If MPDDRC_TRP1 is written with a ‘Value’, the read can be computed using the formula below: Value = (MPDDRC_TRP1 & 0x000000FF) | ((MPDDRC_TRP1 & 0xFFFFFF00) 2 bits lost TXSRD[23:16] becomes TXSRD[25:18] TXSNR[15:8] becomes TXSNR[17:10] Bits [9:8] unused TRFC[6:0] unchanged  2017 Microchip Technology Inc. DS60001525A-page 1719 SAMA5D4 SERIES 61.1.5 61.1.5.1 Static Memory Controller (SMC) Scrambling/Unscrambling Feature Not Supported On All Devices The external data bus scrambling/unscrambling feature is only available on 32-bit memory devices connected on the external bus interface. Problem Fix/Workaround None. 61.1.6 61.1.6.1 PIO Controller PE0 and PE1 Reset State The reset of the I/Os PE0 and PE1 is output, high level with pulldown enable instead of output low level. Problem Fix/Workaround None 61.1.7 61.1.7.1 DMA Controller DMA Request Overflow Error When a DMA memory-to-memory transfer is performed, if the hardware request line selected by the field XDMAC_CCx.PERID toggles when the copy is enabled, the XDMAC_CISx.ROIS flag is set incorrectly. The memory copy proceeds normally and the data area is correctly transferred. Problem Fix/Workaround Configure the field XDMAC_CCx.PERID to an unused peripheral ID (refer to Table 8-1 "Peripheral Identifiers"). 61.1.8 61.1.8.1 Two-wire Interface (TWI) The TWI Clear Command Does Not Work Bus reset using the “CLEAR” bit of the TWI control register does not work correctly during a bus busy state. Problem Fix/Workaround When the TWI master detects the SDA line stuck in low state the procedure to recover is: 1. 2. 3. 4. 5. 6. Reconfigure the SDA/SCL lines as PIO. Try to assert a Logic 1 on the SDA line (PIO output = 1). Read the SDA line state. If the PIO state is a Logic 0, then generate a clock pulse on SCL (1-0-1 transition). Read the SDA line state. If the SDA line = 0, go to Step 3; if SDA = 1, go to Step 5. Generate a STOP condition. Reconfigure SDA/SCL PIOs as peripheral. 61.1.9 61.1.9.1 Serial Synchronous Controller (SSC) Inverted Left/Right Channels When the SSC is in Slave mode, the TF signal is derived from the codec and not controlled by the SSC. The SSC transmits the data when detecting the falling edge on the TF signal after the SSC transmission is enabled. In some cases of overflow, a left/right channel inversion may occur. In this case, the SSC must be re-initialized. Problem Fix/Workaround Using the SSC in Master mode will ensure that TF is controlled by the SSC. No error occurs. If the SSC must be used in TF Slave mode, the SSC must be started by writing TXEN and RXEN synchronously with TXSYN flag rising in the SSC_SR. DS60001525A-page 1720  2017 Microchip Technology Inc. SAMA5D4 SERIES 61.1.9.2 Unexpected Delay on TD Output When SSC is configured with the following conditions: • RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge • RFMR.FSOS = None (input) • TCMR.START = Receive Start an unexpected delay of 2 or 3 system clock cycles is added to TD output. Problem Fix/Workaround None. 61.1.10 Universal Synchronous Asynchronous Receiver Transceiver (USART) 61.1.10.1 USART Framing error not detected if last data bit is 1 If a bad frame is received (incorrect baud rate) with the last data bit being sampled at 1, there is no detection of frame error. Problem Fix/Workaround There is no general fix. When performing baud rate detection with receive part, the transmit frame must be sent with a parity bit set to 0. 61.1.11 Ethernet MAC (GMAC) 61.1.11.1 Bad Association of Timestamps and PTP packets An issue in the association mechanism between event registers and queued PTP packets may lead to timestamps incorrectly associated with these packets. Even if it is highly unlikely to queue consecutive packets of the same type, there is no way to know to which frame the content of the PTP event registers refers. Problem Fix/Workaround None. 61.2 Errata - SAMA5D4 MRL A Parts This section describes errata relevant to the devices listed in the following table. Table 61-2: Ordering Information Device Name ATSAMA5D44A ATSAMA5D43A ATSAMA5D42A ATSAMA5D41A 61.2.1 61.2.1.1 Standard Boot Strategies Boot ROM: Xmodem is Not Working Due to a bug in the ROM code, Xmodem is not working. Problem Fix/Workaround None. 61.2.1.2 Boot ROM: Boot on MCI0 is Not Working Boot on MCI0 is not working. Problem Fix/Workaround Use a different boot media.  2017 Microchip Technology Inc. DS60001525A-page 1721 SAMA5D4 SERIES 61.2.2 61.2.2.1 LCD Controller (LCDC) LCDC PWM Is Not Usable with DIV_1 When field PWMPS in register LCDC_LCDCFG6 is set to DIV_1 value, the PWM output is stuck. The LCDC PWM works correctly for the dividers DIV_2 up to DIV_64. Problem Fix/Workaround None. 61.2.3 61.2.3.1 ADC (Analog-to-Digital Controller) Compare Window limitations in user sequence When USEQ = 1 in ADC_MR and CMPALL = 0 in ADC_EMR, the compare window function does not work for all sequences programmed into ADC_SEQR1 and ADC_SEQR2. Problem Fix/Workaround To have a correct compare window function on a given channel X selected by means of CMPSEL = X in ADC_EMR, the ADC_CHSR[X] must be set. For example, if ADC_CHSR = 0x0000_000F and ADC_SEQ1R = 0x0000_3300, both channel index 0 and 3 can be used for comparison (i.e., CMPSEL = 0 and CMPSEL = 3 can be used, COMPE flag will behave correctly in ADC_ISR). If ADC_CHSR = 0x0000_000F and ADC_SEQ1R = 0x0000_1100, both channel index 0 and 1 can be used for comparison (i.e., CMPSEL = 0 and CMPSEL = 1 can be used, COMPE flag will behave correctly in ADC_ISR). If ADC_CHSR = 0x0000_000F and ADC_SEQ1R = 0x0000_4400, only channel index 0 can be used for comparison (i.e., CMPSEL = 0 can be used, COMPE flag will behave correctly in ADC_ISR). Channel 4 cannot be used for comparison because ADC_CHSR[4] = 0. 61.2.3.2 Differential mode limitations in user sequence If Differential mode is used with user sequence, the analog pad configuration is not the one expected. For instance, if USCH4 is set to channel 2, the user must configure DIFF2 to enable differential mode on channel 2 (this is the expected behavior). However, due to this bug the ADC Controller will look at the DIFF4 state instead the DIFF2 state. Problem Fix/Workaround Set the differential mode on the DIFFx bit corresponding to the related sequence number instead of setting the differential mode on the DIFFx bit of the related channel number. 61.2.3.3 Calibration issue after Sleep Mode Calibration does not work after exiting sleep state. The sleep state is entered when the SLEEP bit in ADC_MR is set or if all channels are disabled after a first series of conversion. Problem Fix/Workaround 1. 2. 3. If the SLEEP bit is set in ADC_MR and a new calibration is required at anytime, the SLEEP bit must first be disabled after which a dummy conversion must be performed. At the end of the conversion (EOC) a new calibration can be started. At the end of the calibration, the SLEEP bit can be set again to 1 and normal conversions can again be performed. If the SLEEP bit is not used but all channels are disabled at any time, the equivalent of the “sleep” state is reached by the internal finite state machine of the ADC controller. Therefore a dummy conversion must be performed, after which the calibration can be performed. The Soft reset command can be performed prior to start a calibration but the configuration of all channels is cleared and must be reprogrammed. 61.2.4 61.2.4.1 Multi-port DDR-SDRAM Controller (MPDDRC) LPDDR2 Refresh Per Bank Not Functional The refresh per bank feature for 8-bank LPDDR2 memories is not functional. The REF_PB bit in the MPDDRC_RTR must be set to 0 (reset value). Problem Fix/Workaround None. DS60001525A-page 1722  2017 Microchip Technology Inc. SAMA5D4 SERIES 61.2.4.2 Scrambling/Unscrambling Feature Not Supported On All Devices The external data bus scrambling/unscrambling feature is only available on 32-bit memory devices connected on the external bus interface. Problem Fix/Workaround None. 61.2.4.3 MPDDRC_TPR1 Incoherency Between Write and Read Value The value read in register MPDDRC_TRP1 does not correspond to the written value. Problem Fix/Workaround If MPDDRC_TRP1 is written with a ‘Value’, the read can be computed using the formula below: Value = (MPDDRC_TRP1 & 0x000000FF) | ((MPDDRC_TRP1 & 0xFFFFFF00) 2 bits lost TXSRD[23:16] becomes TXSRD[25:18] TXSNR[15:8] becomes TXSNR[17:10] Bits [9:8] unused TRFC[6:0] unchanged 61.2.5 61.2.5.1 Static Memory Controller (SMC) Scrambling/Unscrambling Feature Not Supported On All Devices The external data bus scrambling/unscrambling feature is only available on 32-bit memory devices connected on the external bus interface. Problem Fix/Workaround None. 61.2.6 61.2.6.1 PIO Controller PE0 and PE1 Reset State The reset of the I/Os PE0 and PE1 is output, high level with pulldown enable instead of output low level. Problem Fix/Workaround None 61.2.7 61.2.7.1 DMA Controller DMA Request Overflow Error When a DMA memory-to-memory transfer is performed, if the hardware request line selected by the field XDMAC_CCx.PERID toggles when the copy is enabled, the XDMAC_CISx.ROIS flag is set incorrectly. The memory copy proceeds normally and the data area is correctly transferred. Problem Fix/Workaround Configure the field XDMAC_CCx.PERID to an unused peripheral ID (refer to Table 8-1 "Peripheral Identifiers"). 61.2.8 61.2.8.1 Two-wire Interface (TWI) The TWI Clear Command Does Not Work Bus reset using the “CLEAR” bit of the TWI control register does not work correctly during a bus busy state. Problem Fix/Workaround When the TWI master detects the SDA line stuck in low state the procedure to recover is: 1. 2. 3. 4. Reconfigure the SDA/SCL lines as PIO. Try to assert a Logic 1 on the SDA line (PIO output = 1). Read the SDA line state. If the PIO state is a Logic 0, then generate a clock pulse on SCL (1-0-1 transition). Read the SDA line state. If the SDA line = 0, go to Step 3; if SDA = 1, go to Step 5.  2017 Microchip Technology Inc. DS60001525A-page 1723 SAMA5D4 SERIES 5. 6. Generate a STOP condition. Reconfigure SDA/SCL PIOs as peripheral. 61.2.9 61.2.9.1 Serial Synchronous Controller (SSC) Inverted Left/Right Channels When the SSC is in Slave mode, the TF signal is derived from the codec and not controlled by the SSC. The SSC transmits the data when detecting the falling edge on the TF signal after the SSC transmission is enabled. In some cases of overflow, a left/right channel inversion may occur. In this case, the SSC must be re-initialized. Problem Fix/Workaround Using the SSC in Master mode will ensure that TF is controlled by the SSC. No error occurs. If the SSC must be used in TF Slave mode, the SSC must be started by writing TXEN and RXEN synchronously with TXSYN flag rising in the SSC_SR. 61.2.9.2 Unexpected Delay on TD Output When SSC is configured with the following conditions: • RCMR.START = Start on falling edge/Start on Rising edge/Start on any edge • RFMR.FSOS = None (input) • TCMR.START = Receive Start an unexpected delay of 2 or 3 system clock cycles is added to TD output. Problem Fix/Workaround None. 61.2.10 61.2.10.1 Universal Synchronous Asynchronous Receiver Transceiver (USART) USART Framing error not detected if last data bit is 1 If a bad frame is received (incorrect baud rate) with the last data bit being sampled at 1, there is no detection of frame error. Problem Fix/Workaround There is no general fix. When performing baud rate detection with receive part, the transmit frame must be sent with a parity bit set to 0. 61.2.11 61.2.11.1 Ethernet MAC (GMAC) Bad Association of Timestamps and PTP packets An issue in the association mechanism between event registers and queued PTP packets may lead to timestamps incorrectly associated with these packets. Even if it is highly unlikely to queue consecutive packets of the same type, there is no way to know to which frame the content of the PTP event registers refers. Problem Fix/Workaround None. DS60001525A-page 1724  2017 Microchip Technology Inc. SAMA5D4 SERIES Revision History In the tables that follow, the most recent version of the document appears first. Table 61-3: Issue Date SAMA5D4 Datasheet DS60001525 Rev. A Revision History Changes General - Template update: Moved from Atmel to Microchip template. - The datasheet is assigned a new document number (DS60001525) and revision letter is reset to A. --- Document number DS60001525 revision A corresponds to what would have been 11238 revision E. - ISBN number assigned. Section 3. “Package and Pinout” Section 3-1 “TFBGA361 Pin Description”: added note (1) Section 3-1 “TFBGA361 Pin Description”: added note (1) Section 4. “Power Considerations” Table 4-1 Power Supplies: updated VDDBU minimum value from 1.88V to 1.8V Section 12. “Standard Boot Strategies” Table 12-3 “PIO Driven during Boot Program Execution”, SAM-BA Monitor row: corrected pin names Table 12-7 “Customer Fuse Matrix”: added note (1) Section 16. “Special Function Registers (SFR)” Removed Analog Configuration Register and modified Table 16-1 “Register Mapping” accordingly Added Section 23. “System Controller Write Protection (SYSCWP)” Section 32. “LCD Controller (LCDC)” Restored Overlay 2 Layer content. Oct-2017 Section 40. “Two-wire Interface (TWI)” Updated Table 40-7 “Register Mapping” at offset 0x44 and added Section 40.8.12 “TWI Filter Register” Section 46. “Timer Counter (TC)” Removed: - Item “Read of the Capture registers by the DMAC” from the list of ”Embedded Characteristics” - Figure 45-6 “Example of Transfer with DMAC in Capture Mode” - Section 45.7.5 “TC Register AB” Section 56. “Electrical Characteristics” Table 56-54 “Two-wire Serial Bus Requirements”: corrected formulas in notes (3) and (4) Section 58. “Schematic Checklist” Table 58-1 “Power Supply Connections”: updated VDDBU range from “1.88V to 2.12V” to “1.8V to 2.6V” Updated Section 59. “Marking” Section 60. “Ordering Information” Table 60-1 “Ordering Information”: added MRL B parts Section 61. “Errata” Added: - Section 61.1 “Errata - SAMA5D4 MRL B Parts” - Section 61.2.11 “Ethernet MAC (GMAC)”  2017 Microchip Technology Inc. DS60001525A-page 1725 SAMA5D4 SERIES Table 61-4: Doc. Rev. SAMA5D4 11238 Rev. D Datasheet Revision History Date Changes Section 12. “Standard Boot Strategies” Table 12-8 “Special Function Fuse Bits”: removed column for bit MD and rows on SAM-BA Monitor. D 10-Oct-16 Section 29. “Multiport DDR-SDRAM Controller (MPDDRC)” Throughout: CAS latency corrected to 2, 3. Section 61. “Errata” Added Section 61.2.10.1 “USART Framing error not detected if last data bit is 1”. DS60001525A-page 1726  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 61-5: Doc. Rev. SAMA5D4 11238 Rev. C Datasheet Revision History Date Changes “Features” Replaced: - “NEON Multimedia Architecture” with “NEON Media Processing Engine” - “Low-power 32 kHz RC Oscillator” with “Internal low-power 64 kHz (typical) RC Oscillator” Section 1. “Block Diagram” Updated Figure 1-1 “Block Diagram” Section 3. “Package and Pinout” Table 3-1 ”TFBGA361 Pin Description” and Table 3-2 ”LFBGA289 Pin Description”: updated reset state for signals PA0, PA9, PA16, PB24, PB25, PD12, PE0-PE5, PE7-PE23, PE24-PE28 Section 4. “Power Considerations” Updated Section 4.7.3 “External Bus Interface” Table 4-1 "Power Supplies": corrected VDDBU maximum value to 2.6V Section 5. “Memories” Figure 5-1 “Memory Mapping”: changed color code of block “SMC” to Programmable Secured (PS) Section 8. “Peripherals” Updated Table 8-1 ”Peripheral Identifiers” Reworked Section 8.4 “Peripheral Clock Type” Section 13. “L2 Cache Controller (L2CC)” C 12-Jul-16 Table 13-2 “Register Mapping”: updated reset value for L2CC_IDR, L2CC_TRCR and L2CC_DRCR Section 13.5.1 “L2CC Cache ID Register”: changed cache ID value from ‘0x410000C8’ to ‘0x410000C9' Section 14. “AXI Matrix (AXIMX)” Table 14-1 “Register Mapping”: in both rows, removed 0x00000000 reset value Section 15. “Matrix (H64MX/H32MX)” Removed all information regarding compliance of Bus Matrix user interface with the ARM Advanced Peripheral Bus (APB) Section 15.2 “Embedded Characteristics”: removed bullet “AMBA Advanced High-performance Bus (AHBLite) compliant interface”; modified last item to read “ARM TrustZone technology” Table 15-3 "Master to Slave Access on H64MX": replaced “H64MX APB - User interfaces” with “H64MX Peripheral Bridge” Table 15-9 “Peripheral Identifiers”: modified row 22 (HSMC now Programmable Secure); in row 60, removed CTB content (changed to Reserved); in row 63, removed CATB content (changed to Reserved) Section 16. “Special Function Registers (SFR)” Section 16.3.1 “DDR Configuration Register”: added note Updated Section 16.3.8 “AIC Interrupt Redirection Register” Removed EBI Configuration Register Section 17. “Advanced Interrupt Controller (AIC)” Updated Section 17.8.3.3 “Interrupt Handlers” and Section 17.8.4.3 “Fast Interrupt Handlers” Removed sections “Interrupt Vectoring” and “Fast Interrupt Vectoring”  2017 Microchip Technology Inc. DS60001525A-page 1727 SAMA5D4 SERIES Table 61-5: Doc. Rev. SAMA5D4 11238 Rev. C Datasheet Revision History Date Changes Section 18. “Watchdog Timer (WDT)” Replaced “Idle mode” with “Sleep mode (idle mode)” in Section 18.1 “Description” and with “Sleep mode” in Section 18.4 “Functional Description” Added “When setting the WDDIS bit, and while it is set, the fields WDV and WDD must not be modified.” in Section 18.4 “Functional Description” and Section 18.5.2 “Watchdog Timer Mode Register” (WDDIS bit description) Modified paragraph starting with “The reload of the WDT must occur...” in Section 18.4 “Functional Description” Section 19. “Reset Controller (RSTC)” Renamed 'proc_nreset' to 'Processor Reset', 'periph_nreset' to 'Peripheral Reset', 'backup_neset' to 'Backup Reset', 'rstc_irq' to 'Reset Controller Interrupt', 'wd_fault' to 'Watchdog Fault', ‘user_reset’ to User Reset Section 20. “Shutdown Controller (SHDWC)” Updated Section 20.2 “Embedded Characteristics” Section 22. “Real-time Clock (RTC)” Reworked Section 22.5.6 “Updating Time/Calendar” Reworked Figure 22-5. "Calibration Circuitry Waveforms" Section 22.6.1 “RTC Control Register”: updated CALEVSEL bit description Updated Section 22.6.16 “RTC TimeStamp Source Register” Section 24. “Secure Fuse Controller (SFC)” C (cont’d) Table 24-1 "Register Mapping": access “Read/Write” corrected to “Write-only” for SFC_IER and SFC_IDR 12-Jul-16 Section 24.4.4.3 “Fuse Masking”: corrected data register names Section 24.5.2 “SFC Mode Register”: updated MSK field description Section 25. “Clock Generator” Renamed “UTMI Phase Lock Loop Programming” to “UTMI PLL Clock” Updated Figure 25-1. "Clock Generator Block Diagram" Added Figure 25-4. "Main Frequency Counter Block Diagram" Section 25.4 “Slow Clock”: removed “This allows the slow clock to be valid in a short time (about 100 μs)” Section 25.4.2 “32.768 kHz Crystal Oscillator”: deleted Figure 2-5. Typical 32.768 kHz Crystal Oscillator Connection Section 25.5.3 “Main Clock Source Selection”: added detail on advantages of different oscillators Section 25.5.5 “Main Frequency Counter”: updated speed of counter incrementation Section 26. “Power Management Controller (PMC)” Reorganized order of sections within the chapter Updated Section 26.2 “Embedded Characteristics” for Matrix Clocks, Peripheral Clocks and Generic Clock Updated Figure 26-1. "General Clock Block Diagram" and Figure 26-3. "H32MX 32-bit Matrix Clock Configuration" Figure 26-6. "Clock Failure Detection (Example)": corrected CDFEV to CFDEV and CDFS to CFDS Added warning under Figure 26-5. "Fast Startup from Ultra-low-power Mode" Updated Section 26.6 “Matrix Clock Controller” Section 26.16 “Programming Sequence”, sub-section “Selecting Master Clock and Processor Clock”: updated sequence following "If a new value for CSS field corresponds to PLL Clock" DS60001525A-page 1728  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 61-5: Doc. Rev. SAMA5D4 11238 Rev. C Datasheet Revision History Date Changes Section 26. “Power Management Controller (PMC)” (cont’d) Section 26.19.10 “PMC Clock Generator PLLA Register”: changed DIVA description for value ‘0’ Section 26.19.11 “PMC Master Clock Register”: updated H32MXDIV field description Section 26.19.17 “PMC Status Register”: added APLLCKRDY bit (bit 22) Section 27. “Parallel Input/Output Controller (PIO)” Corrected register name from “MATRIX_PSELRx” to “MATRIX_SPSELRx” throughout the section Table 27-4 "Register Mapping": “Peripheral Select Register 1” corrected to “Peripheral ABCD Select Register 1”; “Peripheral Select Register 2” corrected to “Peripheral ABCD Select Register 2” Section 28. “Multiport DDR-SDRAM Controller (MPDDRC)” Section 28.4.3 “Low-power DDR2-SDRAM Initialization”: inserted the sentence “Read the MPDDRC_MR and add a memory barrier assembler instruction just after the read” in steps 3, 5, 7, 9–14 Section 28.7.7 “MPDDRC Low-power Register”: updated DS, TIMEOUT and UPD_MR field descriptions Section 28.7.9 “MPDDRC Low-power DDR2 Low-power Register”: updated DS field description; deleted SR field description Section 28.7.12 “MPDDRC I/O Calibration Register”: updated RDIV field description Section 28.7.16 “MPDDRC Configuration Arbiter Register”: updated ARB field description Section 29. “Static Memory Controller (SMC)” Section 29.2 “Embedded Characteristics”: added NFC SRAM bullet Figure 29-1. "Block Diagram": deleted “(8 Kbytes)” from NFC Internal SRAM block C (cont’d) 12-Jul-16 Removed NFCCMD field and modified Section 29.17.2.1 “Building NFC Address Command Example” and Section 29.17.2.2 “NFC Address Command” accordingly Section 29.17.3 “NFC Initialization”: changed instances of “rbn” to “Ready/Busy” Section 29.17.4.1 “NFC SRAM Mapping”: in second paragraph, deleted sentence “The NFC SRAM size is 8 Kbytes” Table 29-20 "Register Mapping": removed reset value from HSMC_CTRL (register is write-only) Removed acronym ‘HSMC’ from full, written-out register names in Table 29-20 "Register Mapping" and in corresponding register description sections (however, kept ‘HSMC_’ in short register names) Section 29.20.3 “NFC Status Register”: updated RB_RISE and RB_FALL bit descriptions Section 29.20.36 “Timings Register”: removed RBNSEL field Section 30. “DMA Controller (XDMAC)” Updated Figure 30-1 “DMA Controller (XDMAC) Block Diagram” Section 30.5.4.1 “Single Block With Single Microblock Transfer”: added information on memory-to-memory transfer Section 30.8 “XDMAC Software Requirements”: added information on memory-to-memory transfer and XDMAC_CC.INITD Table 30-4 "Register Mapping" and corresponding register description sections: corrected access of XDMAC_GTYPE, XDMAC_GCFG, XDMAC_GWAC, XDMAC_CIM Section 30.9.3 “XDMAC Global Weighted Arbiter Configuration Register”: replaced “XDMAC scheduler” with “DMAC scheduler” throughout Section 30.9.6 “XDMAC Global Interrupt Mask Register”: corrected access to Read-only Section 30.9.28 “XDMAC Channel x [x = 0..15] Configuration Register”: updated PERID field description; corrected INITD bit description  2017 Microchip Technology Inc. DS60001525A-page 1729 SAMA5D4 SERIES Table 61-5: Doc. Rev. SAMA5D4 11238 Rev. C Datasheet Revision History Date Changes Section 31. “LCD Controller (LCDC)” Updated Section 31.2 “Embedded Characteristics” Section 31.5.3 “Interrupt Sources”: “Advanced Interrupt Controller” and “AIC” changed to “interrupt controller” Updated Section 31.6.1.1 “Pixel Clock Period Configuration” Section 31.7.2 “LCD Controller Configuration Register 1”: width of fields HSPW and VSPW changed from 8bit to 10-bit Section 31.7.3 “LCD Controller Configuration Register 2”: width of fields VFPW and VBPW changed from 8bit to 10-bit Section 33. “Image Sensor Interface (ISI)” Section 33.6.12 “ISI Interrupt Enable Register”, Section 33.6.13 “ISI Interrupt Disable Register”: changed access from “Read/Write” to “Write-only” Section 33.6.14 “ISI Interrupt Mask Register”: changed access from “Read/Write” to “Read-only” Section 35. “USB Host High Speed Port (UHPHS)” Updated Section 35.5.2 “Power Management” Added Section 35.7 “USB Host High Speed Port (UHPHS) User Interface” Section 36. “Ethernet MAC (GMAC)” Updated Section 36.1 “Description” C (cont’d) Table 36-1 "GMAC Connections in Different Modes": added table note on GTXCK 12-Jul-16 Section 36.5.2 “Power Management”: deleted reference to PMC_PCER Section 36.5.3 “Interrupt Sources”: added information on interrupt sources and priority queues; deleted reference to ‘Advanced Interrupt Controller’. Replaced by ‘interrupt controller’. Section 36.6.14 “IEEE 1588 Support”: removed reference to ‘output pins’ in 2nd paragraph; deleted reference to GMAC_TSSx Added Section 36.6.18 “Energy-efficient Ethernet Support” and Section 36.6.19 “LPI Operation in the GMAC” Section 36.7.1.2 “Receive Buffer List” and Section 36.7.1.3 “Transmit Buffer List”: added note at end of sections on queue pointer initialization Table 36-17 "Register Mapping": added registers at offsets 0x270 to 0x27C Section 36.8.1 “GMAC Network Control Register”: added bit 19: TXLPIEN: Enable LPI Transmission (was ‘reserved’). Added bit description. Section 36.8.3 “GMAC Network Status Register”: added bit 7: RXLPIS: LPI Indication (was‘reserved’). Added bit description. Section 36.8.13 “GMAC Interrupt Mask Register”: added bit 26: SRI, and bit 28: WOL Added bit 27: RXLPISBC (Receive LPI indication Status Bit Change) and bit 29: TSUTIMCOMP (TSU timer comparison interrupt) in: - Section 36.8.10 “GMAC Interrupt Status Register” - Section 36.8.11 “GMAC Interrupt Enable Register” - Section 36.8.12 “GMAC Interrupt Disable Register” - Section 36.8.13 “GMAC Interrupt Mask Register” DS60001525A-page 1730  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 61-5: Doc. Rev. SAMA5D4 11238 Rev. C Datasheet Revision History Date Changes Section 36. “Ethernet MAC (GMAC)” (cont’d) Added the following sections: - Section 36.8.104 “GMAC Received LPI Transitions” - Section 36.8.105 “GMAC Received LPI Time” - Section 36.8.106 “GMAC Transmit LPI Transitions” - Section 36.8.107 “GMAC Transmit LPI Time” Section 37. “High Speed Multimedia Card Interface (HSMCI)” Section 37.8.5 “WRITE_SINGLE_BLOCK/WRITE_MULTIPLE_BLOCK Operation using DMA Controller”: instance of “HSMCI_ARG” corrected to “HSMCI_ARGR” Table 37-9 “Register Mapping”: added reset value for HSMCI_WPMR and HSMCI_WPSR Section 37.14.2 “HSMCI Mode Register”: modified CLKDIV field description Section 38. “Serial Peripheral Interface (SPI)” Section 38.7.3 “Master Mode Operations”: modified transmission condition description Table 38-5 "Register Mapping": for Chip Select Register, replaced fixed offset with equation Section 38.8.1 “SPI Control Register”: added bit REQCLR Section 38.8.9 “SPI Chip Select Register”: updated description of fields CSNAAT, SCBR, DLYBS and DLYBCT Section 40. “Synchronous Serial Controller (SSC)” Figure 40-19. "Interrupt Block Diagram": renamed RXSYNC to RXSYN; renamed TXSYNC to TXSYN C (cont’d) 12-Jul-16 Section 40.8.10 “Register Write Protection”: replaced "AIC behavior" with "SSC behavior" Section 41. “Debug Unit (DBGU)” Section 41-3 “Register Mapping”: added reset value for Chip ID Register (DBGU_CIDR) Section 41.6.10 “Debug Unit Chip ID Register”: modified “ARCH: Architecture Identifier” field description to show only relevant values Section 43. “Universal Synchronous Asynchronous Receiver Transceiver (USART)” Section 43.6.1 “Baud Rate Generator”: corrected value in "The frequency of the signal provided on SCK must be at least..." Section 43.6.1.2 “Fractional Baud Rate in Asynchronous Mode”: added warning “When the value of field FP is greater than 0...”; removed sentence “This feature is only available when using USART normal mode.” Section 43.6.1.3 “Baud Rate in Synchronous Mode or SPI Mode”: corrected calculation for SCK maximum frequency Section 43.6.3.4 “Manchester Decoder”: corrected “MANE flag” with “MANERR” flag Added Figure 43-27. "RTS Line Software Control when US_MR.USART_MODE = 2" Section 43.6.4 “ISO7816 Mode”: corrected USART_MODE value for prototcol T = 1 Section 43.6.7.5 “Character Transmission”: added content “An additional condition...on the receiver side.”; corrected bit names: RTSEN to RCS, RTSDIS to FCS Section 43.6.7.7 “Receiver Timeout”: deleted redundant paragraphs on STTTO and RETTO Section 43.7.1 “USART Control Register”: updated RTSDIS bit description Section 43.7.3 “USART Mode Register”: updated description for row 0xE, SPI_MASTER Section 43.7.15 “USART Baud Rate Generator Register”: added warning “When the value of field FP is greater than 0...” to FP field description  2017 Microchip Technology Inc. DS60001525A-page 1731 SAMA5D4 SERIES Table 61-5: Doc. Rev. SAMA5D4 11238 Rev. C Datasheet Revision History Date Changes Section 45. “Timer Counter (TC)” Throughout, replaced TIOA, TIOB, TCLK with TIOAx, TIOBx, TCLKx Section 45.2 “Embedded Characteristics”: rephrased "Total number of TC channels" to read "Total number of TC channels implemented on this device” Reformatted and renamed Table 45-2 "Channel Signal Description" Section 45.6.3 “Clock Selection”: updated notes (1) and (2) Section 45.6.9 “Transfer with DMAC in Capture Mode”: added “in Capture mode” and updated Figure 7-4 “Example of Transfer with DMAC_PDC in Capture Mode” Section 45.6.16.4 “Position and Rotation Measurement”: added sentence about internal counter clearing Added Section 45.6.16.6 “Detecting a Missing Index Pulse” Section 46. “Pulse Width Modulation Controller (PWM)” Removed all content related to DMA. Updated Figure 46-1. "Pulse Width Modulation Controller Block Diagram" Updated Section 46.6.2.2 “Comparator” Section 46.6.5.1 “Initialization”: modified “Enable of the interrupts...” list item Updated Section 46.6.5.6 “Interrupt Sources” Corrected PWM period formulas in Section 46.7.42 “PWM Channel Period Register” and Section 46.7.43 “PWM Channel Period Update Register” In register descriptions, added reference to Section 46.5.4 “Fault Inputs” C (cont’d) 12-Jul-16 Section 47. “Analog-to-Digital Converter (ADC)” Renamed “Hold time” to “Transfer time” throughout Section 47.1 “Description”: removed “Finally, the user can configure ADC timings, such as startup time and tracking time.” Updated Section 47.2 “Embedded Characteristics” Section 47.5 “Product Dependencies”: removed sections “Timer Triggers”, “Conversion Performances” and “PWM Event Line” Added Section 47.5.4 “Hardware Triggers” Reworked Section 47.6.1 “Analog-to-Digital Conversion” Modified Section 47.6.4 “Conversion Resolution” and Section 47.6.6 “Conversion Triggers” Section 47.6.8 “Comparison Window”: replaced ADC_SR with ADC_ISR Section 47.6.9 “ADC Timings”: reworded first paragraph; “ADC_ADTRG” corrected to “ADTRG” Revised Section 47.6.10 “Enhanced Resolution Mode and Digital Averaging Function” Section 47.6.12.1 “Classic ADC Channels Only (Touchscreen Disabled)”: changed title (was “Classical ADC Channels Only”) Table 47-6 “Register Mapping”: defined offsets 0x48 and 0x4C as reserved Modified information about USCHx fields in Section 47.7.3 “ADC Channel Sequence 1 Register” and Section 47.6.7 “Sleep Mode and Conversion Sequencer” Section 47.7.4 “ADC Channel Enable Register”: updated CHx field description Section 47.7.13 “ADC Extended Mode Register”: modified CMPMOD bit description Section 47.7.21 “ADC Trigger Register”: added sentence about register write protection DS60001525A-page 1732  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 61-5: Doc. Rev. SAMA5D4 11238 Rev. C Datasheet Revision History Date Changes Section 49. “Advanced Encryption Standard (AES)” Section 49.1 “Description”: corrected index of AES_KEYWR0 registers from 3 to 7. Section 49.2 “Embedded Characteristics”: replaced “12/14/16 Clock Cycles Encryption/Decryption Processing Time” with “10/12/14 Clock Cycles Encryption/Decryption Inherent Processing Time” Section 49.4.2 “Operating Modes”: removed text with restriction on CTR counter size Section 50. “Triple Data Encryption Standard (TDES)” Section 50.4.1 “Operating Modes”: deleted sentence “The OFB and CFB modes of operation are only available if 2-key mode is selected (KEYMOD = 1 in TDES_MR).” Section 50.4.3 “Last Output Data Mode”: deleted sentence “No more Output Data Register reads are necessary between consecutive encryptions/decryptions Section 50.5.2 “TDES Mode Register”: in OPMOD field description, deleted sentence “The OFB and CFB modes of operation are only available if 2-key mode is selected (KEYMOD = 1).” Section 52. “Advanced Encryption Standard Bridge (AESB)” Updated Section 52.1 “Description” C (cont’d) 12-Jul-16 Section 52.2 “Embedded Characteristics”: added “On-the-fly off-chip memory encryption/decryption”; replaced "12 clock cycles encryption/decryption processing time with a 128-bit cryptographic key" with "10 clock cycles encryption/decryption inherent processing time" Section 53. “Integrity Check Monitor (ICM)” Table 53-9 "Register Mapping": changed Status Register access type from Write-only to Read only Section 53.5.2.2 “ICM Region Configuration Structure Member”: removed MRPROT field Section 53.6.1 “ICM Configuration Register”: removed fields HAPROT and DAPROT; updated DUALBUFF field description Section 55. “Electrical Characteristics” Table 55-2 "DC Characteristics": corrected VDDOSC minimum value Corrected Figure 55-16. "SSC Transmitter, TK and TF in Input", Figure 55-18. "SSC Receiver, RK in Input and RF in Output" and Figure 55-19. "SSC Receiver, RK and RF in Output" (swapped CKI = 1 and CKI = 0) Added Section 55.20 “USART in Asynchronous Modes” Section 56. “Mechanical Characteristics” Updated Table 56-2 "Device and 361-ball TFBGA Package Maximum Weight" and Table 56-6 "Device and 289-ball LFBGA Package Maximum Weight" Section 60. “Errata” Added Section 60.7 “DMA Controller”, Section 60.8 “Two-wire Interface (TWI)” and Section 60.9 “Serial Synchronous Controller (SSC)”  2017 Microchip Technology Inc. DS60001525A-page 1733 SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History Date Changes Throughout: editorial and formatting changes; harmonized package naming (TFBGA and LFBGA) Section “Description” Updated maximum processor frequency from 528 MHz to 600 MHz; added paragraph relating to low-power modes; in fifth paragraph, changed “hashing function” to “SHA function” Section “Features” Updated core performance from “832 MIPS @ 528 MHz” to “945 MIPS @ 600 MHz”; bullet “System running up to 176 MHz...” changed to “System running up to 200 MHz...”; inserted bullet “Three Low-power Modes: Idle, Ultra Low-power, and Backup”; added “ICM” and “AESB” to “Cryptography” features Section 1. “Block Diagram” Figure 1-1 “Block Diagram”: added block “Osc RC 12M”; added “Backup Area” caption; "32K OSC" block renamed to "32K XTAL Oscillator"; “SHDWC” corrected to “SHDC”; renumbered three timer counter blocks as TC0, TC1, and TC2 (were previously nine TC channels numbered TC0–TC8); renamed “Cyphering” to “AESB”; moved “Scrambling” from “Trustzone Secured Multi-Layer Matrix” into DDR controller block Section 3. “Package and Pinout” Table 3-1 ”TFBGA361 Pin Description”: changed I/O type ‘ANAIN2’ to ‘GPIO’ (signals PD18–PD27) Table 3-2 ”LFBGA289 Pin Description”: changed I/O type ‘ANAIN2’ to ‘GPIO’ (signals PD18–PD27); at end of table, added pin K10 (Not connected) Table 3-3 ”SAMA5D4 I/O Type Description”: removed I/O type ‘ANAIN2’ row Table 3-4 ”SAMA5D4 I/O Type Assignment and Frequency”: removed I/O type ‘ANAIN2’ row B 24-Aug-15 Section 4. “Power Considerations” Updated Section 4.2 “Powerup Considerations” and Section 4.5 “Powerdown Considerations” Section 5. “Memories” Figure 5-1 “Memory Mapping”: corrected “SHDC” to “SHDWC”; changed NFC SRAM space from 4 Kbytes to 16 Kbytes Section 6. “Real-time Event Management” Updated Table 6-1 ”Real-time Event Mapping List” Section 7. “System Controller” Figure 7-1 “System Controller Block Diagram”: removed ‘WDRPROC’ caption between Watchdog Timer and Reset Controller Section 8. “Peripherals” Table 8-1 ”Peripheral Identifiers”: added ‘SHDWC’ to “Wired-OR interrupts” for System Controller Interrupt Section 11. “Boot Sequence Controller (BSC)” Corrected register name “Boot Sequence Configuration Register” to “Boot Sequence Controller Configuration Register” Section 12. “Standard Boot Strategies” Section 12.4.4.4 “SPI Flash Boot”: updated section “Supported DataFlash Devices” Section 12.5.3.2 “USB Class”: removed reference to “Windows 7” Updated Section 12.6 “Fuse Box Controller” DS60001525A-page 1734  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History (Continued) Date Changes Section 13. “L2 Cache Controller (L2CC)” Table 13-2 ”Register Mapping”: changed L2CC_IDR reset value from ‘0x4100_00C8’ to ‘0x4100_00C9’ Section 13.5.1 “L2CC Cache ID Register”: changed cache ID value from ‘0x410000C8’ to ‘0x410000C9’ Section 14. “AXI Matrix (AXIMX)” Section 14.2 “Embedded Characteristics”: changed “2 Masters” to “1 Master” and deleted subbullet “AHB/ AXI bridge from AHB Matrix” from masters Section 15. “Matrix (H64MX/H32MX)” Table 15-2 ”List of H64MX Slaves”: replaced “AESOTF” with “AESB” in description of slave 3 Modified description of WPVS flag in Section 15.11 “Register Write Protection” and Section 15.13.11 “Write Protection Status Register” Section 16. “Special Function Registers (SFR)” Table 16-1 “Register Mapping”: - at offset 0x44, added Analog Configuration Register (SFR_ANACFG) - added reset values for SFR_EBICFG and SFR_AICREDIR - added footnote “If an offset is not listed in the table it must be considered as reserved.” Added Section 16.3.6 “Analog Configuration Register” Section 17. “Advanced Interrupt Controller (AIC)” Table 17-3 ”Register Mapping”: added row for reserved offsets 0x70–0xE0 Deleted reset values from individual register description sections (register reset values are provided in Table 17-3 ”Register Mapping”) Section 18. “Watchdog Timer (WDT)” B 24-Aug-15 Section 18.4 “Functional Description”: in fifth paragraph, “WDT_MR can be written only once” changed to “WDT_MR can be written until a LOCKMR command is issued in WDT_CR” Section 18.5.1 “Watchdog Timer Control Register”: added note on modification of WDT_CR values; added LOCKMR bit Section 18.5.2 “Watchdog Timer Mode Register”: changed access from “Read/Write Once” to “Read/Write; updated note on write access; updated note on modification of WDT_MR values Section 18.5.3 “Watchdog Timer Status Register”: appended names of bits WDUNF and WDERR with “(cleared on read)” Section 19. “Reset Controller (RSTC)” Figure 19-1 “Reset Controller Block Diagram”: removed WDRPROC signal Section 19.3 “Functional Description”: deleted redundant section “Reset Controller Status Register” (register is described in Section 19.4.2 “Reset Controller Status Register”) Section 19.3.3.5 “Watchdog Reset”: deleted content referencing WDRPROC bit in WDT_MR Figure 19-7 “Watchdog Reset”: deleted caption “(only if WDRPROC = 0)” from periph_nreset waveform Section 19.4.2 “Reset Controller Status Register”: updated descriptions of bits URSTS and NRSTL Section 20. “Shutdown Controller (SHDWC)” Table 20-1 ”I/O Lines Description”: added line WKUP1 Section 20.6 “Functional Description”: inserted subsection heading “Wake-up Inputs” Section 22. “Real-time Clock (RTC)” Updated Section 22.1 “Description” Updated Section 22.2 “Embedded Characteristics” Figure 22-1 “Real-time Clock Block Diagram”: renamed “APB” to “System Bus”  2017 Microchip Technology Inc. DS60001525A-page 1735 SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History (Continued) Date Changes Section 22. “Real-time Clock (RTC)” (cont’d) Updated Section 22.5 “Functional Description” Section 22.5.5 “RTC Internal Free Running Counter Error Checking”: replaced “RTC status clear control register” with “Status Clear Command Register” Updated Section 22.5.7 “RTC Accurate Clock Calibration” Table 22-2 ”Register Mapping”: added reserved offset 0xCC Section 22.6.1 “RTC Control Register”: updated descriptions of value ‘0’ for bits UPDTIM and UPDCAL Section 22.6.3 “RTC Time Register”: deleted sentence “All non-significant bits read zero.” Section 22.6.4 “RTC Calendar Register”: deleted sentence “All non-significant bits read zero.” Section 22.6.11 “RTC Interrupt Mask Register”: added TDERR bit Section 22.6.13 “RTC TimeStamp Time Register 0”: added sentence “RTC_TSTR0 reports the timestamp of the first tamper event after reading RTC_TSSR0”; deleted sentence “All non-significant bits read zero.” Section 22.6.14 “RTC TimeStamp Time Register 1”: added sentence “RTC_TSTR1 reports the timestamp of the last tamper event”; deleted sentence “All non-significant bits read zero.” Section 22.6.15 “RTC TimeStamp Date Register”: added sentence “RTC_TSTR0 reports the timestamp of the first tamper event after reading RTC_TSSR0, and RTC_TSTR1 reports the timestamp of the last tamper event”; deleted sentence “All non-significant bits read zero.” Section 22.6.16 “RTC TimeStamp Source Register”: inserted addresses; removed bits DET15:DET8 (register bits 31:24 now reserved) Section 23. “Slow Clock Controller (SCKC)” Harmonized naming of oscillators Updated Section 23.1 “Description” B 24-Aug-15 Updated Section 23.2 “Embedded Characteristics” Updated Figure 23-1. "Block Diagram" Inserted heading Section 23.4 “Functional Description” and updated content Section 24. “Secure Fuse Controller (SFC)” Replaced instances of “Atmel area” with “Atmel reserved area” throughout Updated Section 24.1 “Description” Updated Section 24.2 “Embedded Characteristics” Updated Figure 24-1 “SFC Block Diagram” Section 24.4 “Functional Description”: removed section “Programming Lock Fuse” Added Section 24.4.1 “Accessing the SFC” Updated Section 24.4.2 “Fuse Partitioning” Updated Section 24.4.4.2 “Fuse Programming” Section 24.4.4.3 “Fuse Masking”: at end of section, added sentence “The MSK bit has no effect on the programming of masked fuses.” Updated Section 24.4.5 “Fuse Functions” (old title “Specific Fuse Function) Table 24-1 ”Register Mapping”: updated number of listed SFC Data Registers Section 24.5.3 “SFC Interrupt Enable Register”: added bit PGMF; removed APLE bit Section 24.5.4 “SFC Interrupt Disable Register”: added bit PGMF; removed APLE bit Section 24.5.5 “SFC Interrupt Mask Register”: added bit PGMF; removed APLE bit Section 24.5.6 “SFC Status Register”: updated bit descriptions; added bit PGMF Section 24.5.7 “SFC Data Register x”: in “Name” line, added register index range DS60001525A-page 1736  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History (Continued) Date Changes Section 25. “Clock Generator” Updated Section 25.2 “Embedded Characteristics” Updated Section 25.3 “Block Diagram” Replaced Section 26.4 “Main Clock Selection” with Section 25.4 “Slow Clock” Extensive revision of Section 25.5 “Main Clock” (including subsections) Updated Section 25.7 “UTMI Phase Lock Loop Programming” Section 26. “Power Management Controller (PMC)” Harmonized oscillator naming; changed instances of “Sleep mode” to “Idle mode” Updated Figure 26-1 “General Clock Block Diagram” Section 26.4 “Master Clock Controller”: in first paragraph, changed “MCK is the clock provided to all the peripherals and the memory controller” to “MCK is the source clock of the peripheral clocks”; added note concerning fields MDIV and CSS Updated Section 26.5 “Processor Clock Controller” Updated Section 26.7 “LCDC Clock Controller” Section 26.8 “USB Device and Host Clocks”: removed last paragraph referencing the FREQ field and the SFR UTMI Clock Trimming Register (this register is not present) Added Section 26.11 “Fast Startup from Ultra Low-power (ULP) Mode” Revised Section 26.12 “Peripheral Clock Controller” Section 26.13 “Programmable Clock Controller”: in first sentence, changed “The PMC controls two signals” to read “The PMC controls three signals” B 24-Aug-15 Section 26.15 “32.768 kHz Crystal Oscillator Frequency Monitor”: changed title (was “Slow Crystal Clock Frequency Monitor”) and updated content Section 26.16 “Programming Sequence”: updated step 6 and step 9 Section 26.18 “Register Write Protection”: added three registers (PMC Peripheral Clock Disable Register 0, PMC Clock Generator Main Oscillator Register, and PMC Peripheral Clock Enable Register 1) to list of protectable registers Table 26-3 ”Register Mapping”: added row for reserved offset 0x110 Section 26.19.1 “PMC System Clock Enable Register”: added sentence about register write protection; updated LCDCK bit description Section 26.19.2 “PMC System Clock Disable Register”: added sentence about register write protection; updated LCDCK bit description Section 26.19.3 “PMC System Clock Status Register”: updated LCDCK bit description Section 26.19.8 “PMC Clock Generator Main Oscillator Register”: added sentence about register write protection; updated descriptions of bits MOSCXTBY and CFDEN Section 26.19.9 “PMC Clock Generator Main Clock Frequency Register”: added sentence about register write protection; updated field descriptions Section 26.19.10 “PMC Clock Generator PLLA Register”: added sentence about register write protection; removed warning referencing bit 29 Section 26.19.11 “PMC Master Clock Register”: added sentence about register write protection; updated descriptions of fields CSS and MDIV Section 26.19.12 “PMC USB Clock Register”: added sentence about register write protection Section 26.19.14 “PMC Programmable Clock Register”: added sentence about register write protection Section 26.19.15 “PMC Interrupt Enable Register”: removed MOSCRCS bit Section 26.19.16 “PMC Interrupt Disable Register”: removed MOSCRCS bit Section 26.19.17 “PMC Status Register”: added OSCSELS bit; removed MOSCRCS bit  2017 Microchip Technology Inc. DS60001525A-page 1737 SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History (Continued) Date Changes Section 26. “Power Management Controller (PMC)” (cont’d) Section 26.19.18 “PMC Interrupt Mask Register”: removed MOSCRCS bit Section 26.19.20 “PLL Charge Pump Current Register”: added sentence about register write protection; updated description of field ICP_PLLA Section 26.19.26 “PMC Peripheral Control Register”: updated description of field GCKDI Section 27. “Parallel Input/Output Controller (PIO)” Section 27.1 “Description”: changed number of programmable I/O lines from 32 to 152 Section 27.2 “Embedded Characteristics”: changed number of programmable I/O lines and number of bits of data output from 32 to 152 Figure 27-1 “Block Diagram”: modified to replace maximum number of pins with “x” integer Added Table 27-1 ”Peripheral IDs” Section 27.5 “Functional Description”: changed number of programmable I/O lines and number of possible indexes per signal from 32 to 152 Section 27.5.3 “Peripheral A or B or C or D Selection”: corrected “corresponding bit at level zero in PIO_ABCDSR2 means peripheral D is selected” to read “corresponding bit at level one in PIO_ABCDSR2 means peripheral D is selected” Section 28. “Multi-port DDR-SDRAM Controller (MPDDRC)” Section 28.2 “Embedded Characteristics”: updated list of supported configurations Section 28.4.1 “Low-power DDR1-SDRAM Initialization”: modified Step 9 Section 28.5.1 “DDR-SDRAM Controller Write Cycle”: updated text and inserted Table 28-1 ”CAS Write Latency” B 24-Aug-15 Section 28.5.2 “DDR-SDRAM Controller Read Cycle”: updated text and inserted Table 28-2 ”CAS Read Latency” Updated Section 28.5.3.2 “Power-down Mode” Added Section 28.6.3 “DDR-SDRAM Address Mapping for Low-cost Memories” Table 28-31 ”Register Mapping”: removed four “MPDDRC Smart Adaptation Wrapper” registers (offset range 0x60–0x6C now reserved); reworded footnote to read “Values vary with the product implementation” Updated Section 28.7.1 “MPDDRC Mode Register” Updated Section 28.7.7 “MPDDRC Low-power Register” Updated Section 28.7.8 “MPDDRC Memory Device Register” Section 28.7.12 “MPDDRC I/O Calibration Register”: updated field descriptions of RDIV and EN_CALIB Removed section “MPDDRC Smart Adaptation Wrapper x Register” Section 28.7.26 “MPDDRC DLL Master Offset Register”: renamed “MPDDRC_DLL_MO” to “MPDDRC_DLL_MAO”; renamed field “MxOFF: Master x Delay Line Offset” to “MAOFF: Master Delay Line Offset” Section 29. “Static Memory Controller (SMC)” Section 29.2 “Embedded Characteristics”: added NFC SRAM bullet Figure 29-1 “Block Diagram”: deleted “(8 Kbytes)” from NFC Internal SRAM block Section 29.17.4.1 “NFC SRAM Mapping”: in second paragraph, deleted sentence “The NFC SRAM size is 8 Kbytes” Section 29.19.3.1 “Error Location”: in first paragraph, changed “32 fully programmable coefficients” to “24 fully programmable coefficients” Table 29-20 ”Register Mapping”: changed access of HSMC_SIGMA0 from “Read/Write” to “Read-only” Added Section 29.20.30 “PMECC Error Location SIGMA 0 Register” Section 29.20.31 “PMECC Error Location SIGMA x Register”: in ‘Name’ line, changed [x=0..24] to [x=1..24] DS60001525A-page 1738  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History (Continued) Date Changes Section 30. “DMA Controller (XDMAC)” Section 30.2 “Embedded Characteristics”: added bullet “1 Kbyte Embedded FIFO” Section 31. “LCD Controller (LCDC)” Figure 31-1 “Block Diagram”: added “OVRx: Overlay” to legend Section 32. “Video Decoder (VDEC)” Section 32.11.2 “Interrupt Sources”: replaced instance of “Advanced Interrupt Controller (AIC)” and “AIC” with “interrupt controller” Section 33. “Image Sensor Interface (ISI)” Section 33.2 “Embedded Characteristics”: updated bullet “Preview Path”; added bullet “Codec Path up to 2048 × 2048” Added Section 33.4 “Product Dependencies” Figure 33-3 “HSYNC and VSYNC Synchronization”: corrected bus name from DATA[7..0] to ISI_DATA[7..0]. Figure 33-4 “SAV and EAV Sequence Synchronization”: corrected bus name from DATA[7..0] to ISI_DATA[7..0] Section 33.5.4.3 “Memory Interface”: changed heading “Grayscale Mode” to “12-bit Grayscale Mode” and updated content; added section “8-bit Grayscale Mode” Removed ‘Reset’ line from register descriptions to avoid redundancy with Table 33-13 ”Register Mapping” Section 33.6.2 “ISI Configuration 2 Register”: updated IM_VSIZE and IM_HSIZE field descriptions Section 33.6.3 “ISI Preview Size Register”: updated PREV_VSIZE and PREV_HSIZE field descriptions Section 33.6.11 “ISI Status Register”: updated bit descriptions Section 34. “USB High Speed Device Port (UDPHS)” B 24-Aug-15 Figure 34-1 “Block Diagram”: updated signal line configuration between UTMI and DP and between UTMI and DM Figure 34-2 “Board Schematic”: modified diagram and added two footnotes Section 34.7.1 “UDPHS Control Register”: added “(cleared upon USB reset)” to relevant field descriptions Section 34.7.2 “UDPHS Frame Number Register”: added “(cleared upon USB reset)” to field descriptions Section 34.7.3 “UDPHS Interrupt Enable Register”: added bit DMA_7 to bitmap; added “(cleared upon USB reset)” to bit descriptions Section 34.7.4 “UDPHS Interrupt Status Register”: added bit DMA_7 to bitmap; added “(cleared upon USB reset)” to description of bits EPT_x Section 34.7.8 “UDPHS Endpoint Configuration Register”: added “(cleared upon USB reset)” to field descriptions Section 34.7.9 “UDPHS Endpoint Control Enable Register (Control, Bulk, Interrupt Endpoints)”: inserted register addresses Section 34.7.13 “UDPHS Endpoint Control Register (Control, Bulk, Interrupt Endpoints)”: inserted register addresses; added “(cleared upon USB reset)” to bit descriptions Section 34.7.14 “UDPHS Endpoint Control Register (Isochronous Endpoint)”: added “(cleared upon USB reset)” to bit descriptions Section 34.7.15 “UDPHS Endpoint Set Status Register (Control, Bulk, Interrupt Endpoints)”: inserted register addresses Section 34.7.17 “UDPHS Endpoint Clear Status Register (Control, Bulk, Interrupt Endpoints)”: inserted register addresses Section 34.7.19 “UDPHS Endpoint Status Register (Control, Bulk, Interrupt Endpoints)”: inserted register addresses; updated description of BUSY_BANK_STA field; added “(cleared upon USB reset)” to field descriptions  2017 Microchip Technology Inc. DS60001525A-page 1739 SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History (Continued) Date Changes Section 34. “USB High Speed Device Port (UDPHS)” (cont’d) Section 34.7.20 “UDPHS Endpoint Status Register (Isochronous Endpoint)”: updated description of BUSY_BANK_STA field; added “(cleared upon USB reset)” to field descriptions Section 35. “USB Host High Speed Port (UHPHS)” Section 35.5.3 “Interrupt Sources”: replaced instance of “Advanced Interrupt Controller (AIC)” and “AIC” with “interrupt controller” Section 36. “Ethernet MAC (GMAC)” Section 36.2 “Embedded Characteristics”: updated bullet “Interrupt generation ...” Added Section 36.5 “Product Dependencies” Updated Section 36.6.2 “1588 Time Stamp Unit” Reworded Section 36.6.3 “AHB Direct Memory Access Interface” Section 36.6.3.2 “Transmit AHB Buffers”: updated third and eleventh paragraphs Section 36.6.4 “MAC Transmit Block”: updated second paragraph Section 36.6.5 “MAC Receive Block”: updated fourth and sixth paragraphs Section 36.6.7 “MAC Filtering Block”: updated first and sixth paragraphs Section 36.6.14 “IEEE 1588 Support”: added paragraph beginning “IEEE 802.1AS is mostly a subset of 1588...” Updated Section 36.6.15 “Time Stamp Unit” Table 36-17 “Register Mapping”: - updated descriptions of GMAC_HRB, GMAC_HRT, GMAC_SAB1, GMAC_SAT1, GMAC_SAB2, GMAC_SAT2, GMAC_SAB3, GMAC_SAT3, GMAC_SAB4, GMAC_SAT4, GMAC_SAMB1, and GMAC_SAMT1, GMAC_ORLO, GMAC_ORHI, and GMAC_TSL B 24-Aug-15 - new registers GMAC_RJFML (offset 0x048); GMAC_NSC (offset 0x0DC); GMAC_SCL (offset 0x0E0); GMAC_SCH (offset 0x0E4); GMAC_EFTSH (offset 0x0E8); GMAC_EFRSH (offset 0x0EC); GMAC_PEFTSH (offset 0x0F0); GMAC_PEFRSH (offset 0x0F4); GMAC_TISUBN (offset 0x1BC); GMAC_TSH (offset 0x1C0) - removed GMAC_TSSSL (offset 0x1C8) and GMAC_TSSN (offset 0x1CC) - offset 0x1E0: PTP Event Frame Transmitted Seconds / GMAC_EFTS replaced by PTP Event Frame Transmitted Seconds Low Register / GMAC_EFTSL - offset 0x1E8: PTP Event Frame Received Seconds / GMAC_EFRS replaced by PTP Event Frame Received Seconds Low Register / GMAC_EFRSL - offset 0x1F0: PTP Peer Event Frame Transmitted Seconds / GMAC_PEFTS replaced by PTP Peer Event Frame Transmitted Seconds Low Register / GMAC_PEFTSL - offset 0x1F8: PTP Peer Event Frame Received Seconds / GMAC_PEFRS replaced by PTP Peer Event Frame Received Seconds Low Register / GMAC_PEFRSL - updated reserved space Section 36.8.6 “GMAC Transmit Status Register”: updated TXGO bit description Section 36.8.9 “GMAC Receive Status Register”: updated RXOVR bit description Section 36.8.11 “GMAC Interrupt Enable Register”: updated bit descriptions Section 36.8.12 “GMAC Interrupt Disable Register”: updated bit descriptions Section 36.8.13 “GMAC Interrupt Mask Register”: updated bit descriptions Section 36.8.14 “GMAC PHY Maintenance Register”: added content on Clause 22/Clause 45 PHYs read/ write access; updated CLTTO bit description Added Section 36.8.17 “GMAC RX Jumbo Frame Max Length Register” Added Section 36.8.38 “GMAC 1588 Timer Nanosecond Comparison Register” Added Section 36.8.39 “GMAC 1588 Timer Second Comparison Low Register” DS60001525A-page 1740  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History (Continued) Date Changes Section 36. “Ethernet MAC (GMAC)” (cont’d) Added Section 36.8.40 “GMAC 1588 Timer Second Comparison High Register” Added Section 36.8.41 “GMAC PTP Event Frame Transmitted Seconds High Register” Added Section 36.8.42 “GMAC PTP Event Frame Received Seconds High Register” Added Section 36.8.43 “GMAC PTP Peer Event Frame Transmitted Seconds High Register” Added Section 36.8.44 “GMAC PTP Peer Event Frame Received Seconds High Register” Section 36.8.50 “GMAC Pause Frames Transmitted Register”: changed PFTX field description Removed sections “1588 Timer Sync Strobe Seconds [31:0] Register” and “1588 Timer Sync Strobe Nanoseconds Register” Added Section 36.8.90 “GMAC 1588 Timer Increment Sub-nanoseconds Register” Added Section 36.8.91 “GMAC 1588 Timer Seconds High Register” Section 36.8.96 “GMAC PTP Event Frame Transmitted Seconds Low Register” (was “PTP Event Frame Transmitted Seconds Register”): updated RUD field description Section 36.8.97 “GMAC PTP Event Frame Transmitted Nanoseconds Register”: updated RUD field description Section 37. “High Speed Multimedia Card Interface (HSMCI)” Section 37.14.12 “HSMCI Status Register”: reworded clearing descriptions in relevant bit descriptions Added Section 37.14.20 “HSMCI FIFOx Memory Aperture” Section 38. “Serial Peripheral Interface (SPI)” Section 38.7.3 “Master Mode Operations”: modified text describing behavior of TDRE and TXEMPTY flags; added note ”When the SPI is enabled, the TDRE and TXEMPTY flags are set.” B 24-Aug-15 Added Figure 38-5 “TDRE and TXEMPTY flag behavior” Revised Figure 38-7 “Master Mode Flow Diagram” Section 38.7.3.5 “Peripheral Selection”: in last paragraph, “command must be issued before writing the last character” replaced by “command must be issued after writing the last character” Section 38.7.3.8 “Peripheral Deselection without DMA”: in last sentence, “(LASTXFER) bit in the SPI_MR” replaced by “(LASTXFER) bit in SPI_CR” Section 38.8.1 “SPI Control Register”: updated description of bit SPIDIS Section 38.8.5 “SPI Status Register”: updated description of bits RDRF, TDRE, and TXEMPTY Section 38.8.9 “SPI Chip Select Register”: updated descriptions of fields SCBR, DLYBS, and DLYBCT Section 39. “Two-wire Interface (TWI)” Section 39.1 “Description”: removed sentence: "Arbitration of the bus is performed internally and puts the TWIHS in Slave mode automatically if the bus arbitration is lost." Replaced section “Application Block Diagram” with updated Section 39.5 “I/O Lines Description” Removed section “Application Block Diagram” from Section 39.7.3 “Master Mode” and Section 39.7.5 “Slave Mode” Section 39.7.3.2 “Programming Master Mode”: replaced prefixes "TWIHS_" with "TWI_" Section 39.7.3.3 “Master Transmitter Mode”: modified 3rd paragraph related to NACK; added note on clearing TXRDY flag Section 39.7.3.5 “Internal Address”: under “10-bit Slave Addressing”, removed reference to “Atmel AT24LC512 EEPROM” Section 39.7.3.6 “Using the DMA Controller”: replaced instances of “(Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required” with “(Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWI_SR” Section 39.7.5.3 “Receiving Data”: under “Read Sequence”, added note on clearing TXRDY flag  2017 Microchip Technology Inc. DS60001525A-page 1741 SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History (Continued) Date Changes Section 39. “Two-wire Interface (TWI)” (cont’d) Corrected Figure 39-22 “Read Access Ordered by a Master” and Figure 39-23 “Write Access Ordered by a Master” (replaced EOSVACC with EOSACC) Corrected Figure 39-24 “Master Performs a General Call” (replaced GCACC with GACC) Figure 39-26 “Clock Synchronization in Write Mode”: replaced “SCL is stretched” with “TWCK is stretched” Section 39.7.5.5 “Using the DMA Controller”: replaced instances of “(Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required” with “(Only if peripheral clock must be disabled) Wait for the TXCOMP flag to be raised in TWI_SR” Corrected Figure 39-29 “Read Write Flowchart in Slave Mode” (changed “SVREAD = 0” to “SVREAD = 1”; changed "RXRDY = 0" to "RXRDY = 1") Section 39.8.1 “TWI Control Register”: updated START bit description Section 39.8.5 “TWI Clock Waveform Generator Register”: updated descriptions of fields CLDIV, CHDIV, and CKDIV Section 39.8.6 “TWI Status Register”: updated bit descriptions Section 42. “Universal Asynchronous Receiver Transmitter (UART)” Section 42.2 “Embedded Characteristics”: deleted bullet “Baud rate can be driven by processor independent source clock” Added Table 42-3 ”Peripheral IDs” Revised Section 42.5.1 “Baud Rate Generator” Section 42.6.2 “UART Mode Register”: removed BRSRCCK bit Section 42.6.9 “UART Baud Rate Generator Register”: updated CD field description B 24-Aug-15 Section 43. “Universal Synchronous Asynchronous Receiver Transmitter (USART)” Section 43.5.1 “I/O Lines”: deleted paragraph “To prevent the TXD line ...” Figure 43-2 “Baud Rate Generator”: added label “Selected Clock” to USCLKS mux output Section “Baud Rate Calculation Example”: in baud rate calculation formula, replaced “fperipheral clock” with “Selected Clock” Figure 43-3 “Fractional Baud Rate Generator”: added label “Selected Clock” to USCLKS mux output Section 43.6.1.3 “Baud Rate in Synchronous Mode or SPI Mode”: in second paragraph, replaced “fperipheral with “Selected Clock” clock” Updated Section 43.6.3.15 “Hardware Handshaking” Section 43.6.7.5 “Character Transmission”: after first paragraph, inserted new paragraph “The chip select line is de-asserted for a period equivalent to three bits between the transmission of two data.” Section 43.7.1 “USART Control Register”: updated STTTO bit description Section 43.7.6 “USART Interrupt Enable Register (SPI_MODE)”: added bit NSSE (register bit 19) Section 43.7.8 “USART Interrupt Disable Register (SPI_MODE)”: added bit NSSE (register bit 19) Section 43.7.10 “USART Interrupt Mask Register (SPI_MODE)”: added bit NSSE (register bit 19) Section 43.7.11 “USART Channel Status Register”: updated bit descriptions; added bit NSSE (register bit 19) and bit NSS (register bit 23) Section 43.7.12 “USART Channel Status Register (SPI_MODE)”: updated bit descriptions Section 43.7.15 “USART Baud Rate Generator Register”: restructured equations in CD field description Section 43.7.16 “USART Receiver Time-out Register”: restructured equation in TO field description Section 43.7.17 “USART Transmitter Timeguard Register”: restructured equation in TG bit description DS60001525A-page 1742  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History (Continued) Date Changes Section 45. “Timer Counter (TC)” Updated Section 45.1 “Description” Section 45.2 “Embedded Characteristics”: updated to indicate “9” as total number of TC channels Section 45.3 “Block Diagram”: inserted Table 45-1 ”Timer Counter Clock Assignment” (table was previously in Section 45.1 “Description”) Added Table 45-5 ”Peripheral IDs” Section 45.6.3 “Clock Selection”: updated names of external clock signals Section 45.6.14 “Synchronization with PWM”: in second paragraph, added output reference “OCx”; in third paragraph, corrected field names TRGSRCA and TRGSRCB to TRIGSRCA and TRIGSRCB Section 45.6.16 “Quadrature Decoder”: removed subsection “Missing Pulse Detection and Auto-correction” Section 45.6.16.4 “Position and Rotation Measurement”: in second paragraph, described selection of External Trigger Edge and External Trigger Section 45.6.16.5 “Speed Measurement”: in fifth paragraph, replaced “EDGTRG can be set to 0x01” with “ETRGEDG must be set to 0x01” Section 45.6.19 “Register Write Protection”: moved to end of Section 45.6 “Functional Description”; inserted sentence “The Timer Counter clock of the first channel must be enabled to access TC_WPMR” Section 45.7.2 “TC Channel Mode Register: Capture Mode”: in ‘Name’ line, replaced “(WAVE = 0)” with “(CAPTURE_MODE)”; updated TCCLKS field description for values 0–4 Section 45.7.3 “TC Channel Mode Register: Waveform Mode”: in ‘Name’ line, replaced “(WAVE = 1)” with “(WAVEFORM_MODE)”; inserted addresses; updated TCCLKS field description for values 0–4 B 24-Aug-15 Section 45.7.10 “TC Status Register”: updated bit descriptions (CKLSTA description unchanged) Section 45.7.14 “TC Extended Mode Register”: updated TRIGSRCB bit value ‘1’ description Section 45.7.16 “TC Block Mode Register”: removed AUTOC bit and MAXCMP field Section 45.7.20 “TC QDEC Interrupt Status Register”: removed MPE bit Section 45.7.22 “TC Write Protection Mode Register”: updated WPEN bit description Section 46. “Pulse Width Modulation Controller (PWM)” Section 46.2 “Embedded Characteristics”: renamed bullet “Programmable Fault/Break Inputs ... Outputs” to “Programmable Fault Inputs ... Outputs” Section 46.5.3 “Interrupt Sources”: deleted sentence “Note that it is not recommended to use the PWM interrupt line in Edge-sensitive mode.” Section 46.6.2.8 “Synchronous Channels”: in fourth paragraph, corrected references to bits, fields and registers; updated step 13 under heading “Method 3: Automatic write of duty-cycle values and automatic trigger of the update” Added Figure 46-18 “Event Line Generation Waveform (Example)” Table 46-7 ”Register Mapping”: removed reset value from PWM_SCUPUPD (register is write-only) Section 46.7.1 “PWM Clock Register”: inserted individual descriptions for fields DIVA, DIVB, PREA, and PREB Section 46.7.34 “PWM Write Protection Control Register” and Section 46.7.35 “PWM Write Protection Status Register”: removed reset value line Section 46.7.40 “PWM Channel Mode Register”: updated CPRE field description  2017 Microchip Technology Inc. DS60001525A-page 1743 SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History (Continued) Date Changes Section 46. “Pulse Width Modulation Controller (PWM)” (cont’d) Corrected referenced register name PWM_CPRx to PWM_CPRDx in Section 46.7.41 “PWM Channel Duty Cycle Register”, Section 46.7.42 “PWM Channel Duty Cycle Update Register”, Section 46.7.46 “PWM Channel Dead Time Register”, and Section 46.7.47 “PWM Channel Dead Time Update Register” Section 47. “Analog-to-Digital Converter (ADC)” Section 47.5 “Product Dependencies”: removed section “Analog Inputs” Updated Section 47.5.3 “I/O Lines” Revised Section 47.6.1 “Analog-to-Digital Conversion” Added Section 47.6.2 “ADC Clock” Section 47.6.3 “ADC Reference Voltage”: changed title (was “Conversion Reference”) Section 47.6.8 “Comparison Window”: in second paragraph, added details on filtering option Section 47.7.2 “ADC Mode Register”: - added configuration ADC_TRG7 in TRGSEL field description table - modified equation in PRESCAL bit description Section 47.7.11 “ADC Interrupt Status Register”: updated bit descriptions (PENS description unchanged) Section 47.7.13 “ADC Extended Mode Register”: updated CMPFILTER field description Section 48. “True Random Number Generator (TRNG)” Section 48.1 “Description”: updated names of referenced test suites Section 48.2 “Embedded Characteristics”: updated names of referenced test suites B 24-Aug-15 Section 48.5 “Functional Description”: updated terminology in text and in Figure 48-2 “TRNG Data Generation Sequence” Table 48-2 “Register Mapping”: defined offset ranges 0x04–0x0C, 0x20–0x4C, and 0x54–0xFC as reserved Removed “Reset” line from Section 48.6.4 “TRNG Interrupt Mask Register”, Section 48.6.5 “TRNG Interrupt Status Register” and Section 48.6.6 “TRNG Output Data Register” Section 49. “Advanced Encryption Standard (AES)” Added Section 49.4.1 “AES Register Endianism” Section 49.4.5.2 “DMA Mode”: removed references to ‘BTC’ throughout and replaced with generic wording Section 49.5.6 “AES Interrupt Status Register”: updated descriptions of DATRDY URAD, and URAT Added register address in Section 49.5.11 “AES Additional Authenticated Data Length Register”, Section 49.5.12 “AES Plaintext/Ciphertext Length Register”, Section 49.5.13 “AES GCM Intermediate Hash Word Register x”, Section 49.5.14 “AES GCM Authentication Tag Word Register x”, Section 49.5.15 “AES GCM Encryption Counter Value Register” and Section 49.5.16 “AES GCM H Word Register x” Section 50. “Triple Data Encryption Standard (TDES)” Section 50.3.2 “Interrupt Sources”: replaced instance of “Advanced Interrupt Controller (AIC)” and “AIC” with “interrupt controller” Updated Section 50.4.3.2 “DMA Mode” Table 50-6 “Register Mapping”: - defined offset ranges 0x68–0x6C and 0x74–0xFC as “Reserved” - for TDES_XTEA_RNDR, defined access as “Read/Write” and added reset value 0x0 Section 50.5.6 “TDES Interrupt Status Register”: updated field descriptions DS60001525A-page 1744  2017 Microchip Technology Inc. SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History (Continued) Date Changes Section 51. “Secure Hash Algorithm (SHA)” Register index position in register names and acronyms modifed: - from “SHA Input Data x Register” to “SHA Input Data Register x” - from “SHA Input/Output Data x Register” to “SHA Input/Output Data Register x” - from “SHA_IDATAxR” to “SHA_IDATARx” - from “SHA_IODATAxR” to “SHA_IODATARx” Updated Section 51.4.4 “Internal Registers for Initial Hash Value” Section 51.4.5.3 “DMA Mode”: changed “The FIRST bit of the control register should be set to 1 prior to start the DMA” to “The FIRST bit of the SHA_CR must be set before starting the DMA” Section 51.4.5.4 “SHA Register Endianism”: rephrased first part of section Table 51-2 “Register Mapping”: in last row, defined offset range 0xC0–0xFC as reserved Section 51.5.1 “SHA Control Register”: modified WUIHV bit description Section 51.5.2 “SHA Mode Register”: modified UIHV bit description; removed configurations HMAC_SHA384, HMAC_SHA512, and HMAC_SHA224 from ALGO field values table; deleted notation “7 words for SHA224, , 12 words for SHA384, 16 words for SHA512” from end of section Section 51.5.6 “SHA Interrupt Status Register”: updated field descriptions Section 51.5.8 “SHA Input/Output Data Register x”: in IODATA field description, changed instance of “SHA_IODATAR5 to the last one in SHA1 mode...” to “SHA_IODATAR4 to the last one in SHA1 mode...” Section 53. “Integrity Check Monitor (ICM)” Section 53.5.1 “Overview”: reorganized and updated content under this new heading B 24-Aug-15 Section 53.5.2.2 “ICM Region Configuration Structure Member”: updated descriptions of fields RHIEN, DMIEN, BEIEN, WCIEN, ECIEN, SUIEN, and MPROT Updated Section 53.5.4 “Using ICM as SHA Engine” Added Section 53.5.4.1 “Settings for Simple SHA Calculation” Moved Section 53.5.7 “Security Features” to end of Section 53.5 “Functional Description” Section 53.6.1 “ICM Configuration Register”: updated description of fields DAPROT and HAPROT Section 53.6.3 “ICM Status Register”: updated description of fields RAWRMDIS and RMDIS Section 55. “Electrical Characteristics” Section 55.3.2.3 “Ultra-low-power Mode”: in second step, deleted “If not used, 12 MHz RC Oscillator can be disabled. MOSCRCEN is set to 0 in CKGR_MOR.” Updated Table 55-3 ”Low-power Mode Configuration Summary” Section 55.3.3 “Power Consumption Versus Modes”: updated TA description Updated Table 55-5 ”Power Consumption in Active Mode” Updated Table 55-6 ”Power Consumption in Idle Mode” Table 55-7 ”VDDCORE Power Consumption in Ultra-low-Power Mode (AMP2)”: removed “ULP 512 Hz” mode row Table 55-8 ”Processor Clock Waveform Parameters”: updated maximum value to 600 MHz Table 55-9 ”Master Clock Waveform Parameters”: updated maximum value to 200 MHz Section 55.5 “Crystal Oscillator Characteristics”: removed figure “Main Oscillator Schematics” (redundant with diagram provided in Table 57-2 ”Clock, Oscillator and PLL Connections”) Section 55.7 “32 kHz Crystal Oscillator Characteristics”: removed figure “32 kHz Oscillator Schematics” (redundant with diagram provided in Table 57-2 ”Clock, Oscillator and PLL Connections”) Updated Section 55.8 “64 kHz RC Oscillator Characteristics” (was previously “32 kHz RC Oscillator Characteristics”)  2017 Microchip Technology Inc. DS60001525A-page 1745 SAMA5D4 SERIES Table 61-6: Doc. Rev. SAMA5D4 11238 Rev. B Datasheet Revision History (Continued) Date Changes Section 55. “Electrical Characteristics” (cont’d) Table 55-12 ”XIN Clock Electrical Characteristics”: updated conditions Table 55-23 ”Channel Conversion Time and ADC Clock”: updated parameter “ADC Clock Frequency” Section 55.14.1 “Maximum SPI Frequency”: updated content under headings “Master Write Mode” and “Master Read Mode” Section 55.15 “MPDDRC Timings”: updated “DDRCK cycle time” minimum values for DDR2-SDRAM, LPDDR1-SDRAM, and LPDDR2-SDRAM Section 55.15.1 “Board Design Constraints”: in first sentence, corrected instance of SAM2613 to SAMA5D4 Table 55-38 ”SPI Timings with 1.8V Peripheral Supply (SPI0 only)”: added missing footnote Table 55-43 ”SSC Timings with 3.3V Peripheral Supply”: updated values of SSC4 and SSC7; replaced two footnotes with single footnote Table 55-44 ”SSC Timings with 1.8V Peripheral Supply (SSC1 only)”: updated values of SSC4 and SSC7; added single footnote Table 55-49 ”Ethernet MAC MII Specific Signals”: deleted footnote “See Note (1) of Table 56-48.” Table 55-50 ”Ethernet MAC RMII Mode”: deleted footnote “See Note (1) of Table 56-48.” B 24-Aug-15 Table 55-53 ”USART SPI Timings 1.8V Peripheral Supply (USART3 and USART4 only)”: added missing footnote Added Figure 55-29 “Minimum and Maximum Access Time for USART SPI Output Signal” Updated Figure 55-30 “Two-wire Serial Bus Timing” Table 55-54 ”Two-wire Serial Bus Requirements”: in last row, corrected parameter symbol to ”tBUF” and conditions to “tLOW” Section 56. “Mechanical Characteristics” Changed instances of “LFBGA” to “TFBGA” for 361-ball package Updated Figure 56-1 “361-ball TFBGA Package Drawing” Section 57. “Schematic Checklist” Table 57-1 ”Power Supply Connections”: updated description of VDDCORE and VDDANA; deleted footnote 4. “For more information, see Table 56-29 “Core Power Supply POR Characteristics”.” Section 60. “Errata” Added Section 60.1.2 “Boot ROM: Boot on MCI0 is Not Working” Added Section 60.6 “PIO Controller” Table 61-7: SAMA5D4 11238 Rev. A Datasheet Revision History Doc. Rev. Date A 30-Sep-14 DS60001525A-page 1746 Changes First release  2017 Microchip Technology Inc. SAMA5D4 SERIES The Microchip Web Site Microchip provides online support via our web site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Customer Change Notification Service Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Design Support”, click on “Customer Change Notification” and follow the registration instructions. Customer Support Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support  2017 Microchip Technology Inc. DS60001525A-page 1747 SAMA5D4 SERIES Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. ATSAMA5 D44 B - C U R Example: a) Architecture ATSAMA5D44B-CUR = Arm Cortex-A5 general-purpose microprocessor, 361-ball, Industrial temperature, BGA Package. Product Group Mask Revision Package Temperature Range Carrier Type Architecture: ATSAMA5 = Arm Cortex-A5 MPU Product Group: D41, D43 D42, D44 = 289-ball general-purpose microprocessors = 361-ball general-purpose microprocessors Mask Revision: B, A Package: C = BGA Temperature Range: U = -40°C to +85°C (Industrial) Carrier Type: Blank R Note 1: 2: DS60001525A-page 1748 = Standard Packaging (tray) = Tape and Reel(1) Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Small form-factor packaging options may be available. Please check www.microchip.com/packaging for small-form factor package availability, or contact your local Sales Office.  2017 Microchip Technology Inc. Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. 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Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2017, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-2245-7  2017 Microchip Technology Inc. DS60001525A-page 1749 Quality Management System Certified by DNV ISO/TS 16949 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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