SAM L21
SAM L21 Family Data Sheet
Introduction
Atmel® SMART SAM L21 is a series of ultra low-power microcontrollers using 32-bit Arm® Cortex®-M0+ processor at
maximum 48 MHz (2.46 CoreMark®/MHz) and up to 256 KB Flash and 40 KB of SRAM in a 32-pin, 48-pin, and 64pin package. The sophisticated power management technologies, such as power domain gating, SleepWalking, ultra
low-power peripherals allow very low-power consumptions. The highly configurable peripherals include a touch
controller supporting capacitive interfaces with proximity sensing.
Features
•
Processor
– Arm Cortex-M0+ CPU running at up to 48 MHz
• Single-cycle hardware multiplier
• Micro Trace Buffer
•
Memories
– 32/64/128/256-KB in-system self-programmable Flash
– 1/2/4/8-KB Flash Read-While-Write section
– 4/8/16/32-KB SRAM main memory
– 2/4/8/8-KB SRAM low-power memory
•
System
– Power-on Reset (POR) and Brown-out Detection (BOD)
– Internal and external clock options
– External Interrupt Controller (EIC)
– 16 external interrupts
– One non-maskable interrupt
– Two-pin Serial Wire Debug (SWD) programming, testing, and debugging interface
•
Low Power
– Idle, Stand-by, Backup, and Off Sleep modes
– SleepWalking peripherals
– Static and Dynamic Power Gating Architecture
– Battery backup support
– Two performance levels
– Embedded Buck/LDO regulator supporting on-the-fly selection
•
Peripherals
– 16-channel Direct Memory Access Controller (DMAC)
– 12-channel Event System
– Up to five 16-bit Timer/Counters (TC) including one low-power TC, each configurable as:
• 16-bit TC with two compare/capture channels
• 8-bit TC with two compare/capture channels
• 32-bit TC with two compare/capture channels, by using two TCs
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SAM L21 Family Data Sheet
– Two 24-bit and one 16-bit Timer/Counters for Control (TCC), with extended functions:
• Up to four compare channels with optional complementary output
• Generation of synchronized pulse width modulation (PWM) pattern across port pins
• Deterministic fault protection, fast decay and configurable dead-time between complementary output
• Dithering that increase resolution with up to 5 bit and reduce quantization error
– 32-bit Real Time Counter (RTC) with clock/calendar function
– Watchdog Timer (WDT)
– CRC-32 generator
– One full-speed (12 Mbps) Universal Serial Bus (USB) 2.0 interface
• Embedded host and device function
• Eight endpoints
– Up to six Serial Communication Interfaces (SERCOM) including one low-power SERCOM, each
configurable to operate as either:
• USART with full-duplex and single-wire half-duplex configuration
• I2C up to 3.4 MHz
• SPI
• LIN slave
– One AES encryption engine
– One True Random Generator (TRNG)
– One Configurable Custom Logic (CCL)
– One 12-bit, 1MSPS Analog-to-Digital Converter (ADC) with up to 20 channels
• Differential and single-ended input
• Automatic offset and gain error compensation
• Oversampling and decimation in hardware to support 13-bit, 14-bit, 15-bit, or 16-bit resolution
– Two 12-bit, 1 MSPS dual output Digital-to-Analog Converter (DAC)
– Two Analog Comparators (AC) with window compare function
– Three Operational Amplifiers (OPAMP)
– Peripheral Touch Controller (PTC)
• 169-channel capacitive touch and proximity sensing
• Wake up on touch in Stand-by mode
•
•
Oscillators
– 32.768 kHz crystal oscillator (XOSC32K)
– 0.4-32 MHz crystal oscillator (XOSC)
– 32.768 kHz internal oscillator (OSC32K)
– 32.768 kHz ultra low-power internal oscillator (OSCULP32K)
– 16/12/8/4 MHz high-accuracy internal oscillator (OSC16M)
– 48 MHz Digital Frequency Locked Loop (DFLL48M)
– 96 MHz Fractional Digital Phased Locked Loop (FDPLL96M)
I/O
– Up to 51 programmable I/O pins
•
•
Easy migration from the SAM D family of devices
Packages
– 64-pin TQFP, QFN, WLCSP
– 48-pin TQFP, QFN
– 32-pin TQFP, QFN
•
Operating voltage
– 1.62V – 3.63V
•
Temperature range
– -40°C to 85°C
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SAM L21 Family Data Sheet
– -40°C to 105°C
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SAM L21 Family Data Sheet
Table of Contents
Introduction.....................................................................................................................................................1
Features......................................................................................................................................................... 1
1.
Description............................................................................................................................................ 14
2.
Configuration Summary........................................................................................................................ 15
3.
Ordering Information............................................................................................................................. 17
3.1.
3.2.
3.3.
3.4.
SAM L21J...................................................................................................................................17
SAM L21G..................................................................................................................................18
SAM L21E.................................................................................................................................. 18
Device Identification................................................................................................................... 19
4.
Block Diagram.......................................................................................................................................21
5.
Pinout.................................................................................................................................................... 22
5.1.
5.2.
5.3.
5.4.
SAM L21J...................................................................................................................................22
SAM L21J WLCSP64................................................................................................................. 23
SAM L21G..................................................................................................................................24
SAM L21E.................................................................................................................................. 25
6.
Signal Descriptions List.........................................................................................................................26
7.
I/O Multiplexing and Considerations..................................................................................................... 28
7.1.
7.2.
8.
Analog Connections of Peripherals.......................................................................................................33
8.1.
8.2.
8.3.
8.4.
9.
Multiplexed Signals.................................................................................................................... 28
Other Functions..........................................................................................................................30
Block Diagram............................................................................................................................ 33
Analog Connections................................................................................................................... 33
Reference Voltages.................................................................................................................... 34
Analog ONDEMAND Function................................................................................................... 34
Power Supply and Start-Up Considerations..........................................................................................36
9.1.
9.2.
9.3.
9.4.
9.5.
Power Domain Overview............................................................................................................36
Power Supply Considerations.................................................................................................... 36
Power-Up................................................................................................................................... 39
Power-On Reset and Brown-Out Detector................................................................................. 40
Performance Level Overview..................................................................................................... 41
10. Product Mapping................................................................................................................................... 42
11. Memories.............................................................................................................................................. 43
11.1.
11.2.
11.3.
11.4.
11.5.
Embedded Memories................................................................................................................. 43
Physical Memory Map................................................................................................................ 43
NVM User Row Mapping............................................................................................................44
NVM Software Calibration Area Mapping...................................................................................45
NVM Temperature Log Row....................................................................................................... 45
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11.6. Serial Number............................................................................................................................ 46
12. Processor and Architecture...................................................................................................................47
12.1.
12.2.
12.3.
12.4.
Cortex M0+ Processor............................................................................................................... 47
Nested Vector Interrupt Controller..............................................................................................48
Micro Trace Buffer...................................................................................................................... 50
High-Speed Bus System............................................................................................................ 50
13. PAC - Peripheral Access Controller...................................................................................................... 55
13.1.
13.2.
13.3.
13.4.
13.5.
13.6.
13.7.
Overview.................................................................................................................................... 55
Features..................................................................................................................................... 55
Block Diagram............................................................................................................................ 55
Product Dependencies............................................................................................................... 55
Functional Description................................................................................................................56
Register Summary......................................................................................................................59
Register Description................................................................................................................... 60
14. Peripherals Configuration Summary..................................................................................................... 79
15. DSU - Device Service Unit.................................................................................................................... 82
15.1. Overview.................................................................................................................................... 82
15.2. Features..................................................................................................................................... 82
15.3. Block Diagram............................................................................................................................ 82
15.4. Signal Description...................................................................................................................... 83
15.5. Product Dependencies............................................................................................................... 83
15.6. Debug Operation........................................................................................................................ 84
15.7. Chip Erase..................................................................................................................................85
15.8. Programming..............................................................................................................................86
15.9. Intellectual Property Protection.................................................................................................. 86
15.10. Device Identification................................................................................................................... 87
15.11. Functional Description................................................................................................................88
15.12. Register Summary..................................................................................................................... 93
15.13. Register Description...................................................................................................................94
16. Clock System.......................................................................................................................................117
16.1.
16.2.
16.3.
16.4.
16.5.
16.6.
16.7.
Clock Distribution......................................................................................................................117
Synchronous and Asynchronous Clocks.................................................................................. 118
Register Synchronization..........................................................................................................119
Enabling a Peripheral............................................................................................................... 121
On Demand Clock Requests....................................................................................................121
Power Consumption vs. Speed................................................................................................ 122
Clocks after Reset.................................................................................................................... 122
17. GCLK - Generic Clock Controller........................................................................................................ 123
17.1.
17.2.
17.3.
17.4.
17.5.
Overview.................................................................................................................................. 123
Features................................................................................................................................... 123
Block Diagram.......................................................................................................................... 123
Signal Description.................................................................................................................... 124
Product Dependencies............................................................................................................. 124
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17.6. Functional Description..............................................................................................................125
17.7. Sleep Mode Operation............................................................................................................. 128
17.8. Additional Features.................................................................................................................. 129
17.9. Register Summary....................................................................................................................130
17.10. Register Description.................................................................................................................131
18. MCLK – Main Clock............................................................................................................................ 139
18.1.
18.2.
18.3.
18.4.
18.5.
18.6.
18.7.
18.8.
Overview.................................................................................................................................. 139
Features................................................................................................................................... 139
Block Diagram.......................................................................................................................... 139
Signal Description.................................................................................................................... 139
Product Dependencies............................................................................................................. 139
Functional Description..............................................................................................................141
Register Summary - MCLK...................................................................................................... 146
Register Description................................................................................................................. 146
19. RSTC – Reset Controller.................................................................................................................... 164
19.1.
19.2.
19.3.
19.4.
19.5.
19.6.
19.7.
19.8.
Overview.................................................................................................................................. 164
Features................................................................................................................................... 164
Block Diagram.......................................................................................................................... 164
Signal Description.................................................................................................................... 164
Product Dependencies............................................................................................................. 165
Functional Description..............................................................................................................166
Register Summary....................................................................................................................169
Register Description................................................................................................................. 169
20. PM – Power Manager......................................................................................................................... 176
20.1.
20.2.
20.3.
20.4.
20.5.
20.6.
20.7.
20.8.
Overview.................................................................................................................................. 176
Features................................................................................................................................... 176
Block Diagram.......................................................................................................................... 176
Signal Description.................................................................................................................... 177
Product Dependencies............................................................................................................. 177
Functional Description..............................................................................................................178
Register Summary....................................................................................................................198
Register Description................................................................................................................. 198
21. OSCCTRL – Oscillators Controller......................................................................................................208
21.1.
21.2.
21.3.
21.4.
21.5.
21.6.
21.7.
21.8.
Overview.................................................................................................................................. 208
Features................................................................................................................................... 208
Block Diagram.......................................................................................................................... 209
Signal Description.................................................................................................................... 209
Product Dependencies............................................................................................................. 209
Functional Description..............................................................................................................210
Register Summary....................................................................................................................220
Register Description................................................................................................................. 221
22. OSC32KCTRL – 32KHz Oscillators Controller................................................................................... 247
22.1. Overview.................................................................................................................................. 247
22.2. Features................................................................................................................................... 247
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22.3.
22.4.
22.5.
22.6.
22.7.
22.8.
Block Diagram.......................................................................................................................... 247
Signal Description.................................................................................................................... 248
Product Dependencies............................................................................................................. 248
Functional Description..............................................................................................................249
Register Summary....................................................................................................................253
Register Description................................................................................................................. 253
23. SUPC – Supply Controller...................................................................................................................264
23.1.
23.2.
23.3.
23.4.
23.5.
23.6.
23.7.
23.8.
Overview.................................................................................................................................. 264
Features................................................................................................................................... 264
Block Diagram.......................................................................................................................... 265
Signal Description.................................................................................................................... 265
Product Dependencies............................................................................................................. 265
Functional Description..............................................................................................................266
Register Summary....................................................................................................................274
Register Description................................................................................................................. 274
24. WDT – Watchdog Timer...................................................................................................................... 293
24.1.
24.2.
24.3.
24.4.
24.5.
24.6.
24.7.
24.8.
Overview.................................................................................................................................. 293
Features................................................................................................................................... 293
Block Diagram.......................................................................................................................... 293
Signal Description.................................................................................................................... 294
Product Dependencies............................................................................................................. 294
Functional Description..............................................................................................................295
Register Summary....................................................................................................................300
Register Description................................................................................................................. 300
25. RTC – Real-Time Counter...................................................................................................................309
25.1. Overview.................................................................................................................................. 309
25.2. Features................................................................................................................................... 309
25.3. Block Diagram.......................................................................................................................... 309
25.4. Signal Description.................................................................................................................... 310
25.5. Product Dependencies............................................................................................................. 310
25.6. Functional Description.............................................................................................................. 311
25.7. Register Summary - COUNT32................................................................................................317
25.8. Register Description - COUNT32............................................................................................. 317
25.9. Register Summary - COUNT16................................................................................................332
25.10. Register Description - COUNT16.............................................................................................332
25.11. Register Summary - CLOCK.................................................................................................... 348
25.12. Register Description - CLOCK................................................................................................. 348
26. DMAC – Direct Memory Access Controller......................................................................................... 364
26.1.
26.2.
26.3.
26.4.
26.5.
26.6.
26.7.
Overview.................................................................................................................................. 364
Features................................................................................................................................... 364
Block Diagram.......................................................................................................................... 366
Signal Description.................................................................................................................... 367
Product Dependencies............................................................................................................. 367
Functional Description..............................................................................................................368
Register Summary....................................................................................................................386
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26.8. Register Description................................................................................................................. 387
26.9. Register Summary - LP SRAM.................................................................................................415
26.10. Register Description - LP SRAM..............................................................................................415
27. EIC – External Interrupt Controller...................................................................................................... 422
27.1.
27.2.
27.3.
27.4.
27.5.
27.6.
27.7.
27.8.
Overview.................................................................................................................................. 422
Features................................................................................................................................... 422
Block Diagram.......................................................................................................................... 422
Signal Description.................................................................................................................... 422
Product Dependencies............................................................................................................. 423
Functional Description..............................................................................................................424
Register Summary....................................................................................................................429
Register Description................................................................................................................. 429
28. NVMCTRL – Non-Volatile Memory Controller.....................................................................................440
28.1.
28.2.
28.3.
28.4.
28.5.
28.6.
28.7.
28.8.
Overview.................................................................................................................................. 440
Features................................................................................................................................... 440
Block Diagram.......................................................................................................................... 440
Signal Description.................................................................................................................... 440
Product Dependencies............................................................................................................. 441
Functional Description..............................................................................................................442
Register Summary....................................................................................................................448
Register Description................................................................................................................. 448
29. PORT - I/O Pin Controller....................................................................................................................461
29.1.
29.2.
29.3.
29.4.
29.5.
29.6.
29.7.
29.8.
Overview.................................................................................................................................. 461
Features................................................................................................................................... 461
Block Diagram.......................................................................................................................... 462
Signal Description.................................................................................................................... 462
Product Dependencies............................................................................................................. 462
Functional Description..............................................................................................................464
Register Summary....................................................................................................................470
Register Description................................................................................................................. 471
30. EVSYS – Event System...................................................................................................................... 488
30.1.
30.2.
30.3.
30.4.
30.5.
30.6.
30.7.
30.8.
Overview.................................................................................................................................. 488
Features................................................................................................................................... 488
Block Diagram.......................................................................................................................... 488
Signal Description.................................................................................................................... 488
Product Dependencies............................................................................................................. 489
Functional Description..............................................................................................................490
Register Summary....................................................................................................................494
Register Description................................................................................................................. 494
31. SERCOM – Serial Communication Interface...................................................................................... 509
31.1.
31.2.
31.3.
31.4.
Overview.................................................................................................................................. 509
Features................................................................................................................................... 509
Block Diagram.......................................................................................................................... 510
Signal Description.................................................................................................................... 510
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SAM L21 Family Data Sheet
31.5. Product Dependencies............................................................................................................. 510
31.6. Functional Description..............................................................................................................512
32. SERCOM USART – SERCOM Universal Synchronous and Asynchronous Receiver and Transmitter
............................................................................................................................................................ 517
32.1.
32.2.
32.3.
32.4.
32.5.
32.6.
32.7.
32.8.
Overview.................................................................................................................................. 517
USART Features...................................................................................................................... 517
Block Diagram.......................................................................................................................... 518
Signal Description.................................................................................................................... 518
Product Dependencies............................................................................................................. 518
Functional Description..............................................................................................................520
Register Summary....................................................................................................................530
Register Description................................................................................................................. 530
33. SERCOM SPI – SERCOM Serial Peripheral Interface....................................................................... 547
33.1.
33.2.
33.3.
33.4.
33.5.
33.6.
33.7.
33.8.
Overview.................................................................................................................................. 547
Features................................................................................................................................... 547
Block Diagram.......................................................................................................................... 548
Signal Description.................................................................................................................... 548
Product Dependencies............................................................................................................. 548
Functional Description..............................................................................................................550
Register Summary....................................................................................................................558
Register Description................................................................................................................. 558
34. SERCOM I2C – SERCOM Inter-Integrated Circuit..............................................................................573
34.1. Overview.................................................................................................................................. 573
34.2. Features................................................................................................................................... 573
34.3. Block Diagram.......................................................................................................................... 574
34.4. Signal Description.................................................................................................................... 574
34.5. Product Dependencies............................................................................................................. 574
34.6. Functional Description..............................................................................................................576
34.7. Register Summary - I2C Slave.................................................................................................592
34.8. Register Description - I2C Slave...............................................................................................592
34.9. Register Summary - I2C Master...............................................................................................605
34.10. Register Description - I2C Master............................................................................................ 605
35. TC – Timer/Counter.............................................................................................................................623
35.1.
35.2.
35.3.
35.4.
35.5.
35.6.
35.7.
Overview.................................................................................................................................. 623
Features................................................................................................................................... 623
Block Diagram.......................................................................................................................... 624
Signal Description.................................................................................................................... 624
Product Dependencies............................................................................................................. 625
Functional Description..............................................................................................................626
Register Description................................................................................................................. 639
36. TCC – Timer/Counter for Control Applications....................................................................................699
36.1. Overview.................................................................................................................................. 699
36.2. Features................................................................................................................................... 699
36.3. Block Diagram.......................................................................................................................... 700
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36.4.
36.5.
36.6.
36.7.
36.8.
Signal Description.................................................................................................................... 700
Product Dependencies............................................................................................................. 700
Functional Description..............................................................................................................701
Register Summary....................................................................................................................734
Register Description................................................................................................................. 736
37. TRNG – True Random Number Generator......................................................................................... 774
37.1.
37.2.
37.3.
37.4.
37.5.
37.6.
37.7.
37.8.
Overview.................................................................................................................................. 774
Features................................................................................................................................... 774
Block Diagram.......................................................................................................................... 774
Signal Description.................................................................................................................... 774
Product Dependencies............................................................................................................. 774
Functional Description..............................................................................................................775
Register Summary....................................................................................................................777
Register Description................................................................................................................. 777
38. AES – Advanced Encryption Standard............................................................................................... 784
38.1.
38.2.
38.3.
38.4.
38.5.
38.6.
38.7.
38.8.
Overview.................................................................................................................................. 784
Features................................................................................................................................... 784
Block Diagram.......................................................................................................................... 785
Signal Description.................................................................................................................... 785
Product Dependencies............................................................................................................. 785
Functional Description..............................................................................................................786
Register Summary....................................................................................................................794
Register Description................................................................................................................. 796
39. USB – Universal Serial Bus................................................................................................................ 812
39.1. Overview.................................................................................................................................. 812
39.2. Features................................................................................................................................... 812
39.3. USB Block Diagram..................................................................................................................813
39.4. Signal Description.................................................................................................................... 813
39.5. Product Dependencies............................................................................................................. 813
39.6. Functional Description..............................................................................................................815
39.7. Communication Device Host Register Summary..................................................................... 831
39.8. Communication Device Host Register Description...................................................................831
39.9. Device Registers - Common -Register Summary.................................................................... 838
39.10. Device Registers - Common.................................................................................................... 838
39.11. Device Endpoint Register Summary........................................................................................ 851
39.12. Device Endpoint Register Description......................................................................................851
39.13. Endpoint Descriptor Structure.................................................................................................. 860
39.14. Device Endpoint RAM Register Summary............................................................................... 861
39.15. Device Endpoint RAM Register Description.............................................................................861
39.16. Host Registers - Common - Register Summary.......................................................................867
39.17. Host Registers - Common - Register Description.................................................................... 867
39.18. Host Registers - Pipe - Register Summary.............................................................................. 881
39.19. Host Registers - Pipe - Register Description............................................................................881
39.20. Pipe Descriptor Structure......................................................................................................... 892
39.21. Host Registers - Pipe RAM - Register Summary..................................................................... 893
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SAM L21 Family Data Sheet
39.22. Host Registers - Pipe RAM - Register Description...................................................................893
40. CCL – Configurable Custom Logic......................................................................................................901
40.1.
40.2.
40.3.
40.4.
40.5.
40.6.
40.7.
40.8.
Overview.................................................................................................................................. 901
Features................................................................................................................................... 901
Block Diagram.......................................................................................................................... 902
Signal Description.................................................................................................................... 902
Product Dependencies............................................................................................................. 902
Functional Description..............................................................................................................903
Register Summary....................................................................................................................913
Register Description................................................................................................................. 913
41. Operational Amplifier Controller (OPAMP).......................................................................................... 918
41.1.
41.2.
41.3.
41.4.
41.5.
41.6.
41.7.
41.8.
Overview.................................................................................................................................. 918
Features................................................................................................................................... 918
Block Diagram.......................................................................................................................... 919
Signal Description.................................................................................................................... 919
Product Dependencies............................................................................................................. 919
Functional Description..............................................................................................................921
Register Summary....................................................................................................................932
Register Description................................................................................................................. 932
42. ADC – Analog-to-Digital Converter..................................................................................................... 938
42.1.
42.2.
42.3.
42.4.
42.5.
42.6.
42.7.
42.8.
Overview.................................................................................................................................. 938
Features................................................................................................................................... 938
Block Diagram.......................................................................................................................... 939
Signal Description.................................................................................................................... 940
Product Dependencies............................................................................................................. 940
Functional Description..............................................................................................................941
Register Summary....................................................................................................................952
Register Description................................................................................................................. 952
43. AC – Analog Comparators.................................................................................................................. 979
43.1.
43.2.
43.3.
43.4.
43.5.
43.6.
43.7.
43.8.
Overview.................................................................................................................................. 979
Features................................................................................................................................... 979
Block Diagram.......................................................................................................................... 980
Signal Description.................................................................................................................... 980
Product Dependencies............................................................................................................. 980
Functional Description..............................................................................................................981
Register Summary....................................................................................................................990
Register Description................................................................................................................. 990
44. DAC – Digital-to-Analog Converter................................................................................................... 1006
44.1.
44.2.
44.3.
44.4.
44.5.
44.6.
Overview................................................................................................................................ 1006
Features................................................................................................................................. 1006
Block Diagram........................................................................................................................ 1006
Signal Description.................................................................................................................. 1007
Product Dependencies........................................................................................................... 1007
Functional Description............................................................................................................1008
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44.7. Register Summary..................................................................................................................1015
44.8. Register Description............................................................................................................... 1015
45. PTC - Peripheral Touch Controller.................................................................................................... 1034
45.1.
45.2.
45.3.
45.4.
45.5.
45.6.
Overview................................................................................................................................ 1034
Features................................................................................................................................. 1034
Block Diagram........................................................................................................................ 1035
Signal Description.................................................................................................................. 1036
Product Dependencies........................................................................................................... 1036
Functional Description............................................................................................................1037
46. Electrical Characteristics...................................................................................................................1039
46.1. Disclaimer...............................................................................................................................1039
46.2. Absolute Maximum Ratings....................................................................................................1039
46.3. General Operating Ratings.....................................................................................................1039
46.4. Supply Characteristics............................................................................................................1040
46.5. Maximum Clock Frequencies................................................................................................. 1040
46.6. Power Consumption............................................................................................................... 1042
46.7. Wake-Up Time........................................................................................................................1047
46.8. I/O Pin Characteristics............................................................................................................1047
46.9. Injection Current..................................................................................................................... 1049
46.10. Analog Characteristics........................................................................................................... 1050
46.11. NVM Characteristics...............................................................................................................1065
46.12. Oscillators Characteristics......................................................................................................1066
46.13. Timing Characteristics............................................................................................................1072
46.14. USB Characteristics............................................................................................................... 1076
47. Electrical Characteristics - Extended Temperature Range 105°C.....................................................1078
47.1.
47.2.
47.3.
47.4.
47.5.
47.6.
47.7.
47.8.
47.9.
Disclaimer...............................................................................................................................1078
General Operating Ratings - 105°C....................................................................................... 1078
Power Consumption............................................................................................................... 1078
I/O Pin Characteristics............................................................................................................1083
Injection Current - 105°C........................................................................................................1084
Analog Characteristics........................................................................................................... 1085
NVM Characteristics...............................................................................................................1094
Oscillators Characteristics......................................................................................................1095
Timing Characteristics............................................................................................................ 1102
48. Typical Characteristics.......................................................................................................................1106
48.1. Power Consumption over Temperature in Sleep Modes........................................................ 1106
49. Appendix A........................................................................................................................................ 1108
49.1. SIL 2-Enabled Functional Safety Devices.............................................................................. 1108
50. Packaging Information.......................................................................................................................1109
50.1. Thermal Considerations......................................................................................................... 1109
50.2. Package Drawings..................................................................................................................1110
50.3. Soldering Profile......................................................................................................................1119
51. Schematic Checklist.......................................................................................................................... 1120
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51.1.
51.2.
51.3.
51.4.
51.5.
51.6.
51.7.
51.8.
Introduction.............................................................................................................................1120
Power Supply......................................................................................................................... 1120
External Analog Reference Connections................................................................................1123
External Reset Circuit.............................................................................................................1124
Unused or Unconnected Pins.................................................................................................1126
Clocks and Crystal Oscillators................................................................................................1126
Programming and Debug Ports.............................................................................................. 1128
USB Interface......................................................................................................................... 1131
52. Conventions.......................................................................................................................................1133
52.1.
52.2.
52.3.
52.4.
Numerical Notation................................................................................................................. 1133
Memory Size and Type...........................................................................................................1133
Frequency and Time...............................................................................................................1133
Registers and Bits.................................................................................................................. 1134
53. Acronyms and Abbreviations.............................................................................................................1135
54. Datasheet Revision History............................................................................................................... 1137
54.1. Rev. C - 03/2020.....................................................................................................................1137
54.2. Rev B - 02/2020......................................................................................................................1137
54.3. Rev. A - 02/2017.....................................................................................................................1138
54.4. Rev J - 06/2016...................................................................................................................... 1140
54.5. Rev I - 02/2016....................................................................................................................... 1142
54.6. Rev H - 12/2015..................................................................................................................... 1143
54.7. Rev G - 11/2015......................................................................................................................1143
54.8. Rev F - 09/2015......................................................................................................................1146
54.9. Rev E - 07/2015......................................................................................................................1148
54.10. Rev D - 06/2015..................................................................................................................... 1149
54.11. Rev C - 03/2015..................................................................................................................... 1151
54.12. Rev B - 02/2015..................................................................................................................... 1153
54.13. Rev A - 01/2015..................................................................................................................... 1154
The Microchip Web Site............................................................................................................................1155
Customer Change Notification Service.....................................................................................................1155
Customer Support.................................................................................................................................... 1155
Product Identification System................................................................................................................... 1156
Microchip Devices Code Protection Feature............................................................................................ 1156
Legal Notice..............................................................................................................................................1156
Trademarks...............................................................................................................................................1157
Quality Management System Certified by DNV........................................................................................1157
Worldwide Sales and Service................................................................................................................... 1158
© 2020 Microchip Technology Inc.
DS60001477C-page 13
SAM L21 Family Data Sheet
Description
1.
Description
Atmel® SMART SAM L21 is a series of ultra low-power microcontrollers using the 32-bit Arm® Cortex®-M0+
processor, and ranging from 32-pin to 64-pin with up to 256 KB Flash and 40 KB of SRAM. The SAM L21 devices
operate at a maximum frequency of 48 MHz and reach 2.46 CoreMark®/MHz. They are designed for simple and
intuitive migration with identical peripheral modules, hex compatible code, identical linear address map and pin
compatible migration paths between all devices in the product series. All devices include intelligent and flexible
peripherals, Atmel Event System for inter-peripheral signaling, and support for capacitive touch button, slider and
wheel user interfaces.
The Atmel SAM L21 devices provide the following features: In-system programmable Flash, 16-channel direct
memory access (DMA) controller, 12-channel Event System, programmable interrupt controller, up to 51
programmable I/O pins, 32-bit real-time clock and calendar, up to five 16-bit Timer/Counters (TC) and three Timer/
Counters for Control (TCC) where each TC/TCC can be configured to perform frequency and waveform generation,
accurate program execution timing or input capture with time and frequency measurement of digital signals. The TCs
can operate in 8-bit or 16-bit mode, selected TCs can be cascaded to form a 32-bit TC, and three timer/counters
have extended functions optimized for motor, lighting, and other control applications. Two TCC can operate in 24-bit
mode, the third TCC can operate in 16-bit mode. The series provide one full-speed USB 2.0 embedded host and
device interface; up to six Serial Communication Modules (SERCOM) that each can be configured to act as an
USART, UART, SPI, I2C up to 3.4 MHz, SMBus, PMBus, and LIN slave; up to twenty channel 1 MSPS 12-bit ADC
with programmable gain and optional oversampling and decimation supporting up to 16-bit resolution, two 12-bit 1
MSPS DACs, two analog comparators with window mode, three independent cascadable OPAMPs supporting
internal connection with others analog features, Peripheral Touch Controller supporting up to 192 buttons, sliders,
wheels and proximity sensing; programmable Watchdog Timer (WDT), Brown-out Detector (BOD) and Power-on
Reset (POR) and two-pin Serial Wire Debug (SWD) program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can be used as a source for
the system clock. Different clock domains can be independently configured to run at different frequencies, enabling
power saving by running each peripheral at its optimal clock frequency, and thus maintaining a high CPU frequency
while reducing power consumption.
The SAM L21 devices have four software-selectable sleep modes: Idle, Stand-by, Backup and Off. In Idle mode the
CPU is stopped while all other functions can be kept running. In Stand-by mode all clocks and functions are stopped
except those selected to continue running. In this mode all RAMs and logic contents are retained. The device
supports SleepWalking. This feature allows the peripheral to wake up from sleep based on predefined conditions,
and thus allows some internal operation like DMA transfer and the CPU to wake up only when needed, for example,
when a threshold is crossed or a result is ready. The Event System supports synchronous and asynchronous events,
allowing peripherals to receive, react, and send events even in Stand-by mode.
The SAM L21 devices have two software-selectable performance levels (PL0 and PL2) allowing the user to scale the
lowest core voltage level that will support the operating frequency. To further minimize consumption, specifically
leakage dissipation, the SAM L21 devices utilizes power domain gating technique with retention to turn off some logic
area while keeping its logic state. This technique is fully handled by hardware.
The Flash program memory can be reprogrammed in-system through the SWD interface. The same interface can be
used for non-intrusive on-chip debugging of application code. A boot loader running in the device can use any
communication interface to download and upgrade the application program in the Flash memory.
The Atmel SAM L21 devices are supported with a full suite of programs and system development tools, including C
compilers, macro assemblers, program debugger/simulators, programmers and evaluation kits.
© 2020 Microchip Technology Inc.
DS60001477C-page 14
SAM L21 Family Data Sheet
Configuration Summary
2.
Configuration Summary
SAM L21J
SAM L21G
SAM L21E
Pins
64
48
32
General Purpose I/O-pins
(GPIOs)
51
37
25
256/128/64-KB
256/128/64-KB
256/128/64/32-KB
8/4/2-KB
8/4/2-KB
8/4/2/1-KB
32/16/8-KB
32/16/8-KB
32/16/8/4-KB
Low-power SRAM
8/8/4-KB
8/8/4-KB
8/8/4/2-KB
Timer Counter (TC)
instances(1)
5
3
3
Waveform output channels
per TC instance
2
2
2
Timer Counter for Control
(TCC) instances
3
3
3
Waveform output channels
per TCC
8/4/2
8/4/2
6/4/2
DMA channels
16
16
16
USB interface
1
1
1
AES engine
1
1
1
Configurable Custom Logic
(CCL) (LUTs)
4
4
4
True Random Generator
(TRNG)
1
1
1
Serial Communication
Interface (SERCOM)
instances
6
6
6
Analog-to-Digital Converter
(ADC) channels
20
14
10
Analog Comparators (AC)
2
2
2
Digital-to-Analog Converter
(DAC) channels
2
2
2
Operational Amplifier
(OPAMP)
3
3
3
Yes
Yes
Yes
1
1
1
One 32-bit value or
One 32-bit value or
One 32-bit value or
two 16-bit values
two 16-bit values
two 16-bit values
16
16
16
Flash
Flash RWW section
System SRAM
Real-Time Counter (RTC)
RTC alarms
RTC compare values
External Interrupt lines
© 2020 Microchip Technology Inc.
DS60001477C-page 15
SAM L21 Family Data Sheet
Configuration Summary
...........continued
SAM L21J
SAM L21G
SAM L21E
Peripheral Touch Controller
(PTC) channels (X- x YLines) for mutual
capacitance (2)
169 (13x13)
81 (9x9)
42 (7x6)
Peripheral Touch Controller
(PTC) channels for self
capacitance (Y-Lines only)
16
10
7
(3)
Maximum CPU frequency
Packages
48 MHz
QFN
QFN
QFN
TQFP
TQFP
TQFP
WLCSP(4)
Oscillators
32.768 kHz crystal oscillator (XOSC32K)
0.4-32 MHz crystal oscillator (XOSC)
32.768 kHz internal oscillator (OSC32K)
32 KHz ultra low-power internal oscillator (OSCULP32K)
16/12/8/4-MHz high-accuracy internal oscillator (OSC16M)
48 MHz Digital Frequency Locked Loop (DFLL48M)
96 MHz Fractional Digital Phased Locked Loop (FDPLL96M)
Event System channels
12
12
12
SW Debug Interface
Yes
Yes
Yes
Watchdog Timer (WDT)
Yes
Yes
Yes
Note:
1. For SAM L21E and SAM L21G devices, only TC0, TC1 and TC4 are available.
2. The number of X-lines and Y-lines depends on the configuration of the device, as some I/O lines can be
configured as either X-lines or Y-lines. Refer to Multiplexed Signals for additional information. The number in
the configuration summary is the maximum number of channels that can be obtained.
3. The number of Y-lines depends on the configuration of the device, as some I/O lines can be configured as
either X-lines or Y-lines. The number given here is the maximum number of Y-lines that can be obtained.
4. WLCSP parts are programmed with a specific SPI bootloader. Refer to the Application Note “AT09002” for
additional information.
© 2020 Microchip Technology Inc.
DS60001477C-page 16
SAM L21 Family Data Sheet
Ordering Information
3.
Ordering Information
SAML 21 E 15 B - M U T
Product Family
Package Carrier
SAML = Low Power ULP Microcontroller
T = Tape and Reel
Product Series
21 = Cortex M0+ CPU, Advanced Feature Set
+ DMA + USB
Package Grade
U = -40 to 85°C Matte Sn Plating
N = -40 to 105°C Matte Sn Plating
Pin Count
E = 32 Pins
G = 48 Pins
J = 64 Pins
Package Type
A = TQFP
Flash Memory Density
M = QFN
U = WLCSP
18 = 256KB
17 = 128KB
16 = 64KB
15 = 32KB
Device Variant
A = Engineering Samples Only
B = Released to Production
Note: The device variant (last letter of the ordering number) is independent of the die revision
(DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of
the die.
3.1
SAM L21J
Table 3-1. SAM L21J Ordering Codes
Ordering Code
ATSAML21J16B-AUT
FLASH
(bytes)
SRAM (bytes)
64K
8K
-40°C to 85°C
ATSAML21J16B-MUT
Carrier Type
TQFP64
Tape & Reel
QFN64
ATSAML21J16B-ANT
ATSAML21J16B-MNT
ATSAML21J17B-AUT
Package
128K
16K
-40°C to
105°C
TQFP64
-40°C to 85°C
TQFP64
QFN64
ATSAML21J17B-MUT
QFN64
ATSAML21J17B-UUT
WLCSP64
ATSAML21J17B-ANT
ATSAML21J17B-MNT
© 2020 Microchip Technology Inc.
-40°C to
105°C
Tape & Reel
TQFP64
QFN64
DS60001477C-page 17
SAM L21 Family Data Sheet
Ordering Information
...........continued
Ordering Code
ATSAML21J18B-AUT
FLASH
(bytes)
SRAM (bytes)
256K
32K
Carrier Type
TQFP64
Tape & Reel
ATSAML21J18B-MUT
QFN64
ATSAML21J18B-UUT
WLCSP64
ATSAML21J18B-ANT
-40°C to
105°C
ATSAML21J18B-MNT
3.2
-40°C to 85°C
Package
TQFP64
QFN64
SAM L21G
Table 3-2. SAM L21G Ordering Codes
Ordering Code
ATSAML21G16B-AUT
FLASH
(bytes)
SRAM (bytes)
64K
8K
-40°C to 85°C
ATSAML21G16B-MUT
ATSAML21G16B-MNT
128K
16K
Tape & Reel
TQFP48
-40°C to 85°C
TQFP48
QFN48
Tape & Reel
QFN48
ATSAML21G17B-ANT
ATSAML21G17B-MNT
256K
32K
-40°C to
105°C
TQFP48
-40°C to 85°C
TQFP48
ATSAML21G18B-MUT
QFN48
Tape & Reel
QFN48
ATSAML21G18B-ANT
-40°C to
105°C
ATSAML21G18B-MNT
3.3
TQFP48
-40°C to
105°C
ATSAML21G17B-MUT
ATSAML21G18B-AUT
Carrier Type
QFN48
ATSAML21G16B-ANT
ATSAML21G17B-AUT
Package
TQFP48
QFN48
SAM L21E
Table 3-3. SAM L21E
Ordering Code
ATSAML21E15B-AUT
FLASH
(bytes)
32K
SRAM (bytes) Temperature
Range
4K
-40°C to 85°C
ATSAML21E15B-MUT
ATSAML21E15B-ANT
ATSAML21E15B-MNT
© 2020 Microchip Technology Inc.
Package
Carrier Type
TQFP32
Tape & Reel
QFN32
-40°C to
105°C
TQFP32
QFN32
DS60001477C-page 18
SAM L21 Family Data Sheet
Ordering Information
...........continued
Ordering Code
FLASH
(bytes)
ATSAML21E16B-AUT
64K
SRAM (bytes) Temperature
Range
8K
-40°C to 85°C
ATSAML21E16B-MUT
Carrier Type
TQFP32
Tape & Reel
QFN32
ATSAML21E16B-ANT
ATSAML21E16B-MNT
ATSAML21E17B-AUT
128K
16K
-40°C to
105°C
TQFP32
-40°C to 85°C
TQFP32
QFN32
ATSAML21E17B-MUT
Tape & Reel
QFN32
ATSAML21E17B-ANT
ATSAML21E17B-MNT
ATSAML21E18B-AUT
256K
32K
-40°C to
105°C
TQFP32
-40°C to 85°C
TQFP32
ATSAML21E18B-MUT
QFN32
Tape & Reel
QFN32
ATSAML21E18B-ANT
-40°C to
105°C
ATSAML21E18B-MNT
3.4
Package
TQFP32
QFN32
Device Identification
The Device Service Unit (DSU) peripheral provides the Device Selection bits in the Device Identification register
(DID.DEVSEL) to identify the device by software. The SAM L21 variants have a reset value of DID = 0x1081drxx,
with the LSB identifying the die number ('d'), the die revision ('r') and the device selection ('xx').
Table 3-4. SAM L21 Device Identification Values
DEVSEL (DID[7:0])
Device
0x00
SAML21J18A
0x01
SAML21J17A
0x02
SAML21J16A
0x03-0x04
Reserved
0x05
SAML21G18A
0x06
SAML21G17A
0x07
SAML21G16A
0x08-0x09
Reserved
0x0A
SAML21E18A
0x0B
SAML21E17A
0x0C
SAML21E16A
0x0D
SAML21E15A
0x0E
Reserved
0x0F
SAML21J18B
0x10
SAML21J17B
0x11
SAML21J16B
© 2020 Microchip Technology Inc.
DS60001477C-page 19
SAM L21 Family Data Sheet
Ordering Information
...........continued
DEVSEL (DID[7:0])
Device
0x12-0x13
Reserved
0x14
SAML21G18B
0x15
SAML21G17B
0x16
SAML21G16B
0x17-0x18
Reserved
0x19
SAML21E18B
0x1A
SAML21E17B
0x1B
SAML21E16B
0x1C
SAML21E15B
0x1D-0xFF
Reserved
Note: The device variant (last letter of the ordering number) is independent of the die revision
(DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of
the die.
References:
15. DSU - Device Service Unit
15.13.9 DID
© 2020 Microchip Technology Inc.
DS60001477C-page 20
SAM L21 Family Data Sheet
Block Diagram
IOBUS
SWCLK
CORTEX-M0+
PROCESSOR
Fmax 48 MHz
SERIAL
WIRE
EVENT
SWDIO
MEMORY
TRACE BUFFER
Block Diagram
DEVICE
SERVICE
UNIT
256/128/64/32KB
NVM
32/16/8/4KB
RAM
NVM
CONTROLLER
Cache
SRAM
CONTROLLER
S
M
M
S
S
HIGH SPEED
BUS MATRIX
S
S
M
M
S
DP
USB FS
DEVICE
MINI-HOST
DM
SOF 1KHZ
8/8/4/2KB
RAM
AHB-APB
BRIDGE B
S
LP SRAM
CONTROLLER
S
LOW POWER
BUS MATRIX
PERIPHERAL
ACCESS
CONTROLLER
S
S
DMA
M
S
EVENT
AHB-APB
BRIDGE D
AHB-APB
BRIDGE C
DMA
56xxSERCOM
SERCOM
MAIN CLOCKS
CONTROLLER
OSCILLATORS CONTROLLER
OSC16M
XOSC
GCLK_IO[7..0]
FDPLL96M
GENERIC CLOCK
CONTROLLER
NMI
WO0
4 x TIMER / COUNTER
EVENT 8 x Timer Counter
WO1
DMA
WO0
WO1
(2)
WOn
DMA
AES
DMA
WATCHDOG
TIMER
EXTINT[15..0]
DMA
3x TIMER / COUNTER
FOR CONTROL
EVENT
EVENT SYSTEM
DFLL48M
XIN
XOUT
DMA
EVENT
TRNG
Dual Channels
12-bit DAC 1MSPS
EXTERNAL INTERRUPT
CONTROLLER
SERCOM
POWER
MANAGER
XOUT32
TIMER / COUNTER
XOSC32K
OSCULP32K
OSC32K
20-CHANNEL
12-bit ADC 1MSPS
EVENT
2 ANALOG
COMPARATORS
EVENT
SUPPLY CONTROLLER
BOD33
DMA
VREF
VREG
EVENT
RESET
EXTWAKEx
VREFA
PAD0
PAD1
PAD2
PAD3
PERIPHERAL
TOUCH
CONTROLLER
WO1
AIN[19..0]
VREFA
VREFB
AIN[3..0]
X[15..0]
Y[15..0]
OA_NEG
RESET
CONTROLLER
REAL TIME
COUNTER
VOUT[1..0]
WO0
DMA
OSC32K CONTROLLER
XIN32
PAD0
PAD1
PAD2
PAD3
EVENT
AHB-APB
BRIDGE A
PORT
AHB-APB
BRIDGE E
PORT
4.
3 x OPAMP
OA_POS
OA_OUT
IN[2..0]
4 x CCL
EVENT
OUT
EVENT
Note:
1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC
signals.
2. The three TCC instances have different configurations, including the number of Waveform Output (WO) lines.
© 2020 Microchip Technology Inc.
DS60001477C-page 21
SAM L21 Family Data Sheet
Pinout
Pinout
5.1
SAM L21J
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PB03
PB02
PB01
PB00
PB31
PB30
PA31
PA30
VDDIN
VSW
GND
VDDCORE
RESET
PA27
PB23
PB22
5.
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PB17
PB16
PA19
PA18
PA17
PA16
VDDIO
GND
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PB12
PB13
PB14
PB15
PA12
PA13
PA14
PA15
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
PA00
PA01
PA02
PA03
PB04
PB05
GNDANA
VDDANA
PB06
PB07
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED INPUT/OUTPUT SUPPLY
RESET PIN
© 2020 Microchip Technology Inc.
DS60001477C-page 22
SAM L21 Family Data Sheet
Pinout
5.2
SAM L21J WLCSP64
8
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
7
PA16
6
5
PB16
PA13
PB13
PB14
PA08
PB08
PB30
PB06
PA00
PA02
PB01
PA01
GNDANA
VDDANA
PB31
PB04
PA06
PB07
PA30
PB00
PA07
PA04
GND
VDDIN
PB05
PB09
PA05
PA31
PB11
PA09
VDDCORE
VSW
PB02
PA10
PA11
PB23
PB12
GND
RESET
PA27
PB17
VDDIO
PB22
PA24
VDDIO
1
GND
PA21
PB15
PB10
PA25
PA19
GND
PA12
2
VDDIO
PA23
PA18
PA14
3
PA22
PA20
PA17
PA15
4
PA03
PB03
REGULATED INPUT/OUPUT SUPPLY
© 2020 Microchip Technology Inc.
DS60001477C-page 23
SAM L21 Family Data Sheet
Pinout
48
47
46
45
44
43
42
41
40
39
38
37
PB03
PB02
PA31
PA30
VDDIN
VSW
GND
VDDCORE
RESET
PA27
PB23
PB22
SAM L21G
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
VDDIO
GND
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
13
14
15
16
17
18
19
20
21
22
23
24
PA00
PA01
PA02
PA03
GNDANA
VDDANA
PB08
PB09
PA04
PA05
PA06
PA07
PA08
PA09
PA10
PA11
VDDIO
GND
PB10
PB11
PA12
PA13
PA14
PA15
5.3
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED INPUT/OUTPUT SUPPLY
RESET PIN
© 2020 Microchip Technology Inc.
DS60001477C-page 24
SAM L21 Family Data Sheet
Pinout
32
31
30
29
28
27
26
25
PA31
PA30
VDDIN
VSW
GND
VDDCORE
RESET
PA27
SAM L21E
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PA25
PA24
PA23
PA22
PA19
PA18
PA17
PA16
9
10
11
12
13
14
15
16
PA00
PA01
PA02
PA03
PA04
PA05
PA06
PA07
VDDANA
GND
PA08
PA09
PA10
PA11
PA14
PA15
5.4
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED INPUT/OUTPUT SUPPLY
RESET PIN
© 2020 Microchip Technology Inc.
DS60001477C-page 25
SAM L21 Family Data Sheet
Signal Descriptions List
6.
Signal Descriptions List
The following table provides details on signal names classified by peripheral.
Table 6-1. Signal Descriptions List
Signal Name
Function
Type
Active Level
Analog Comparators (AC)
AIN[3:0]
AC Analog Inputs
Analog
CMP[1:0]
AC Comparator Outputs
Digital
Analog-to- Digital Converter (ADC)
AIN[19:0]
ADC Analog Inputs
Analog
VREFA
ADC Voltage External Reference A
Analog
VREFB
ADC Voltage External Reference B
Analog
Digital-to-Analog Converter (DAC)
VOUT[1:0]
DAC Voltage output
Analog
VREFA
DAC Voltage External Reference
Analog
Operational Amplifier (OPAMP)
OANEG[2:0]
OPAMP Analog Negative Inputs
Analog
OAPOS[2:0]
OPAMP Analog Positive Inputs
Analog
OAOUT[2:0]
OPAMP Analog outputs
Analog
External Interrupt Controller (EIC)
EXTINT[15:0]
External Interrupts inputs
Digital
NMI
External Non-Maskable Interrupt
input
Digital
External wake-up inputs
Digital
Reset Controller (RSTC)
EXTWAKE[7:0]
Generic Clock Generator (GCLK)
GCLK_IO[7:0]
Generic Clock (source clock inputs or Digital
generic clock generator output)
Custom Control Logic (CCL)
IN[11:0]
Logic Inputs
Digital
OUT[3:0]
Logic Outputs
Digital
Supply Controller (SUPC)
VBAT
External battery supply Inputs
Analog
PSOK
Main Power Supply OK input
Digital
OUT[1:0]
Logic Outputs
Digital
Reset input
Digital
Power Manager (PM)
RESETN
© 2020 Microchip Technology Inc.
Low
DS60001477C-page 26
SAM L21 Family Data Sheet
Signal Descriptions List
...........continued
Signal Name
Function
Type
Active Level
Serial Communication Interface (SERCOMx)
PAD[3:0]
SERCOM Inputs/Outputs Pads
Digital
Oscillators Control (OSCCTRL)
XIN
Crystal or external clock Input
Analog/Digital
XOUT
Crystal Output
Analog
32 kHz Oscillators Control (OSC32KCTRL)
XIN32
32 kHz Crystal or external clock Input Analog/Digital
XOUT32
32 kHz Crystal Output
Analog
Waveform Outputs
Digital
Waveform Outputs
Digital
Timer Counter (TCx)
WO[1:0]
Timer Counter (TCCx)
WO[7:0]
Peripheral Touch Controller (PTC)
X[15:0]
PTC Input
Analog
Y[15:0]
PTC Input
Analog
General Purpose I/O (PORT)
PA25 - PA00
Parallel I/O Controller I/O Port A
Digital
PA27
Parallel I/O Controller I/O Port A
Digital
PA31 - PA30
Parallel I/O Controller I/O Port A
Digital
PB17 - PB00
Parallel I/O Controller I/O Port B
Digital
PB23 - PB22
Parallel I/O Controller I/O Port B
Digital
PB31 - PB30
Parallel I/O Controller I/O Port B
Digital
Universal Serial Bus (USB)
DP
DP for USB
Digital
DM
DM for USB
Digital
SOF 1 kHz
USB Start of Frame
Digital
© 2020 Microchip Technology Inc.
DS60001477C-page 27
SAM L21 Family Data Sheet
I/O Multiplexing and Considerations
7.
I/O Multiplexing and Considerations
7.1
Multiplexed Signals
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be assigned to one of
the peripheral functions A, B, C, D, E, F, G, H or I. To enable a peripheral function on a pin, the Peripheral Multiplexer
Enable bit in the Pin Configuration register corresponding to that pin (PINCFGn.PMUXEN, n = 0..31) in the PORT
must be written to '1'. The selection of peripheral function A to H is done by writing to the Peripheral Multiplexing Odd
and Even bits in the Peripheral Multiplexing register (PMUXn.PMUXE/O) in the PORT.
This table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 7-1. PORT Function Multiplexing
Pin
I/O pin
Supply
B(1)(2)
C
D
E
F
G
H
I
SERCOM (1)
(2)
SERCOM-ALT
TC/TCC (3)
TCC
COM
AC/GCLK/
SUPC
CCL
EXTINT[0]/
EXTWAKE[0]
SERCOM1/
PAD[0]
TCC2/
WO[0]
VSWOUT
EXTINT[1]/
EXTWAKE[1]
SERCOM1/
PAD[1]
TCC2/
WO[1]
PA02(5)
VDDANA
EXTINT[2]/
EXTWAKE[2]
4
PA03
VDDANA
EXTINT[3]/
EXTWAKE[3]
5
PB04
VDDANA
6
PB05
VDDANA
9
PB06
10
7
SAML21E
SAML21G
SAML21J
1
1
1
PA00
VSWOUT
2
2
2
PA01
3
3
3
4
4
A
EIC/RSTC
REF
ADC
AC
PTC
DAC
AIN[0]
Y[0]
AIN[1]
Y[1]
EXTINT[4]
AIN[12]
Y[10]
EXTINT[5]
AIN[13]
Y[11]
OA_NEG[1]
VDDANA
EXTINT[6]
AIN[14]
Y[12]
OA_NEG[2]
PB07
VDDANA
EXTINT[7]
AIN[15]
Y[13]
11
PB08(5)
VDDANA
EXTINT[8]
AIN[2]
8
12
PB09
VDDANA
EXTINT[9]
AIN[3]
5
9
13
PA04(5)
VDDANA
EXTINT[4]/
EXTWAKE[4]
6
10
14
PA05(5)
VDDANA
7
11
15
PA06
8
12
16
11
13
17
VREFA
VREFB
AIN[4]
AIN[0]
EXTINT[5]/
EXTWAKE[5]
AIN[5]
AIN[1]
VDDANA
EXTINT[6]/
EXTWAKE[6]
AIN[6]
AIN[2]
PA07(5)
VDDANA
EXTINT[7]/
EXTWAKE[7]
AIN[7]
AIN[3]
PA08(5)
VDDIO(6)
NMI
AIN[16]
VOUT[1]
Y[4]
X[0]
14
18
PA09
VDDIO(6)
EXTINT[9]
AIN[17]
X[1]
Y[7]
13
15
19
PA10
VDDIO(6)
EXTINT[10]
AIN[18]
X[2]
Y[8]
14
16
20
PA11
VDDIO(6)
EXTINT[11]
AIN[19]
X[3]
Y[9]
OA_NEG[0]
CCL2
IN[0]
CCL2
IN[1]
Y[15]
Y[6]
12
VOUT[0]
OPAMP
OA_OUT[1]
SERCOM4/
PAD[0]
TC0/WO[0]
CCL2
IN[2]
OA_POS[1]
SERCOM4/
PAD[1]
TC0/WO[1]
CCL2
OUT
OA_OUT[2]
SERCOM0/
PAD[0]
TCC0/
WO[0]
CCL0
IN[0]
OA_POS[2]
SERCOM0/
PAD[1]
TCC0/
WO[1]
CCL0
IN[1]
OA_POS[0]
SERCOM0/
PAD[2]
TCC1/
WO[0]
CCL0
IN[2]
OA_OUT[0]
SERCOM0/
PAD[3]
TCC1/
WO[1]
CCL0
OUT
SERCOM0/
PAD[0]
SERCOM2/
PAD[0]
TCC0/
WO[0]
TCC1/
WO[2]
CCL1
IN[0]
SERCOM0/
PAD[1]
SERCOM2/
PAD[1]
TCC0/
WO[1]
TCC1/
WO[3]
CCL1
IN[1]
SERCOM0/
PAD[2]
SERCOM2/
PAD[2]
TCC1/
WO[0]
TCC0/
WO[2]
GCLK_IO[4]
CCL1
IN[2]
SERCOM0/
PAD[3]
SERCOM2/
PAD[3]
TCC1/
WO[1]
TCC0/
WO[3]
GCLK_IO[5]
CCL1
OUT
19
23
PB10
VDDIO
EXTINT[10]
Y[2]
SERCOM4/
PAD[2]
TC1/WO[0]
TCC0/
WO[4]
GCLK_IO[4]
CCL1
IN[2]
20
24
PB11
VDDIO
EXTINT[11]
Y[3]
SERCOM4/
PAD[3]
TC1/WO[1]
TCC0/
WO[5]
GCLK_IO[5]
CCL1
OUT
25
PB12
VDDIO
EXTINT[12]
X[12]
Y[5]
SERCOM4/
PAD[0
TC0/WO[0]
TCC0/
WO[6]
GCLK_IO[6]
26
PB13
VDDIO
EXTINT[13]
X[13]
Y[14]
SERCOM4/
PAD[1]
TC0/WO[1]
TCC0/
WO[7]
GCLK_IO[7]
27
PB14
VDDIO
EXTINT[14]
X[14]
SERCOM4/
PAD[2]
TC1/WO[0]
© 2020 Microchip Technology Inc.
GCLK_IO[0]
DS60001477C-page 28
CCL3
IN[0]
SAM L21 Family Data Sheet
I/O Multiplexing and Considerations
...........continued
Pin
SAML21E
SAML21G
I/O pin
Supply
SAML21J
B(1)(2)
A
EIC/RSTC
REF
ADC
AC
PTC
OPAMP
C
D
E
F
G
H
I
SERCOM (1)
(2)
SERCOM-ALT
TC/TCC (3)
TCC
COM
AC/GCLK/
SUPC
CCL
GCLK_IO[1]
CCL3
IN[1]
28
PB15
VDDIO
EXTINT[15]
21
29
PA12
VDDIO
EXTINT[12]
SERCOM2/
PAD[0]
SERCOM4/
PAD[0]
TCC2/
WO[0]
TCC0/
WO[6]
AC/CMP[0]
22
30
PA13
VDDIO
EXTINT[13]
SERCOM2/
PAD[1]
SERCOM4/
PAD[1]
TCC2/
WO[1]
TCC0/
WO[7]
AC/CMP[1]
15
23
31
PA14
VDDIO(6)
EXTINT[14]
SERCOM2/
PAD[2]
SERCOM4/
PAD[2]
TC4/WO[0]
TCC0/
WO[4]
GCLK_IO[0]
16
24
32
PA15
VDDIO(6)
EXTINT[15]
SERCOM2/
PAD[3]
SERCOM4/
PAD[3]
TC4/WO[1]
TCC0/
WO[5]
GCLK_IO[1]
17
25
35
PA16
VDDIO(6)
EXTINT[0]
X[4]
SERCOM1/
PAD[0]
SERCOM3/
PAD[0]
TCC2/
WO[0]
TCC0/
WO[6]
GCLK_IO[2]
CCL0
IN[0]
18
26
36
PA17
VDDIO(6)
EXTINT[1]
X[5]
SERCOM1/
PAD[1]
SERCOM3/
PAD[1]
TCC2/
WO[1]
TCC0/
WO[7]
GCLK_IO[3]
CCL0
IN[1]
19
27
37
PA18
VDDIO(6)
EXTINT[2]
X[6]
SERCOM1/
PAD[2]
SERCOM3/
PAD[2]
TC4/WO[0]
TCC0/
WO[2]
AC/CMP[0]
CCL0
IN[2]
20
28
38
PA19
VDDIO(6)
EXTINT[3]
X[7]
SERCOM1/
PAD[3]
SERCOM3/
PAD[3]
TC4/WO[1]
TCC0/
WO[3]
AC/CMP[1]
CCL0
OUT
39
PB16
VDDIO
EXTINT[0]
SERCOM5/
PAD[0]
TC2/WO[0]
TCC0/
WO[4]
GCLK_IO[2]
CCL3
IN[2]
40
PB17
VDDIO
EXTINT[1]
SERCOM5/
PAD[1]
TC2/WO[1]
TCC0/
WO[5]
GCLK_IO[3]
CCL3
OUT
29
41
PA20
VDDIO
EXTINT[4]
X[8]
SERCOM5/
PAD[2]
SERCOM3/
PAD[2]
TC3/WO[0]
TCC0/
WO[6]
GCLK_IO[4]
30
42
PA21
VDDIO
EXTINT[5]
X[9]
SERCOM5/
PAD[3]
SERCOM3/
PAD[3]
TC3/WO[1]
TCC0/
WO[7]
GCLK_IO[5]
21
31
43
PA22
VDDIO(6)
EXTINT[6]
X[10]
SERCOM3/
PAD[0]
SERCOM5/
PAD[0]
TC0/WO[0]
TCC0/
WO[4]
GCLK_IO[6]
CCL2
IN[0]
22
32
44
PA23
VDDIO(6)
EXTINT[7]
X[11]
SERCOM3/
PAD[1]
SERCOM5/
PAD[1]
TC0/WO[1]
TCC0/
WO[5]
USB/SOF
1kHz
GCLK_IO[7]
CCL2
IN[1]
23
33
45
PA24
VDDIO(6)
EXTINT[12]
SERCOM3/
PAD[2]
SERCOM5/
PAD[2]
TC1/WO[0]
TCC1/
WO[2]
USB/DM
CCL2
IN[2]
24
34
46
PA25
VDDIO(6)
EXTINT[13]
SERCOM3/
PAD[3]
SERCOM5/
PAD[3]
TC1/WO[1]
TCC1/
WO[3]
USB/DP
CCL2
OUT
37
49
PB22
VDDIN
EXTINT[6]
SERCOM5/
PAD[2]
TC3/WO[0]
GCLK_IO[0]
CCL0
IN[0]
38
50
PB23
VDDIN
EXTINT[7]
SERCOM5/
PAD[3]
TC3/WO[1]
GCLK_IO[1]
CCL0
OUT
25
39
51
PA27
VDDIN
EXTINT[15]
31
45
57
PA30
VDDIN
EXTINT[10]
SERCOM1/
PAD[2]
TCC1/
WO[0]
CORTEX_
M0P/
SWCLK
32
46
58
PA31
VDDIN
EXTINT[11]
SERCOM1/
PAD[3]
TCC1/
WO[1]
SWDIO (4)
59
PB30
VDDIN
EXTINT[14]
SERCOM5/
PAD[0]
TCC0/
WO[0]
TCC1/
WO[2]
60
PB31
VDDIN
EXTINT[15]
SERCOM5/
PAD[1]
TCC0/
WO[1]
TCC1/
WO[3]
61
PB00
VSWOUT
EXTINT[0]
AIN[8]
SERCOM5/
PAD[2]
TC3/WO[0]
CCL0
IN[1]
62
PB01
VSWOUT
EXTINT[1]
AIN[9]
SERCOM5/
PAD[3]
TC3/WO[1]
CCL0
IN[2]
47
63
PB02
VSWOUT
EXTINT[2]
AIN[10]
SERCOM5/
PAD[0]
TC2/WO[0]
CCL0
OUT
48
64
PB03
VSWOUT
EXTINT[3]
AIN[11]
SERCOM5/
PAD[1]
TC2/WO[1]
© 2020 Microchip Technology Inc.
X[15]
DAC
SERCOM4/
PAD[3]
TC1/WO[1]
GCLK_IO[0]
GCLK_IO[0]
DS60001477C-page 29
CCL1
IN[0]
CCL1
OUT
SAM L21 Family Data Sheet
I/O Multiplexing and Considerations
Note:
1. All analog pin functions are on peripheral function B. Peripheral function B must be selected to disable the
digital control of the pin.
2. Only some pins can be used in SERCOM I2C mode. See also 7.2.4 SERCOM I2C Pins.
3. TC2 and TC3 are not supported on SAM L21G. Refer to 2. Configuration Summary for details.
4. This function is only activated in the presence of a debugger.
5. When an analog peripheral is enabled, the analog output of the peripheral will interfere with the alternative
functions of this pin. This is also true even when the peripheral is used for internal purposes.
6. On SAM L21E, VDDIO is electrically connected to the VDDANA domain and supplied through VDDANA.
7. Clusters of multiple GPIO pins are sharing the same supply pin. See 7.2.5 GPIO Clusters.
References:
Electrical Characteristics
7.2
Other Functions
7.2.1
Oscillator Pinout
The oscillators are not mapped to the normal PORT functions and their multiplexing are controlled by registers in the
Oscillators Controller (OSCCTRL) and in the 32 kHz Oscillator Controller (OSC32KCTRL).
Table 7-2. Oscillator Pinout
Oscillator
Supply
Signal
I/O pin
XOSC
VDDIO
XIN
PA14
XOUT
PA15
XIN32
PA00
XOUT32
PA01
XOSC32K
VSWOUT
Note: To improve the cycle-to-cycle jitter of XOSC32, it is recommended to keep the neighboring pins of XIN32 and
XOUT32 pins as static as possible as shown in the table below:
Table 7-3. XOSC32 Jitter Minimization
Package Pin Count
Static Signal Recommended
64
PB00, PB01, PB02, PB03, PA02, PA03
48
PB02, PB03, PA02, PA03
32
PA02, PA03
References:
51. Schematic Checklist
External Real time Oscillator
7.2.2
Serial Wire Debug Interface Pinout
Only the SWCLK pin is mapped to the normal PORT functions. A debugger cold-plugging or hot-plugging detection
will automatically switch the SWDIO port to the SWDIO function.
Table 7-4. Serial Wire Debug Interface Pinout
Signal
Supply
I/O pin
SWCLK
VDDIN
PA30
© 2020 Microchip Technology Inc.
DS60001477C-page 30
SAM L21 Family Data Sheet
I/O Multiplexing and Considerations
...........continued
7.2.3
Signal
Supply
I/O pin
SWDIO
VDDIN
PA31
Supply Controller Pinout
The outputs of the Supply Controller (SUPC) are not mapped to the normal PORT functions. They are controlled by
registers in the SUPC.
Table 7-5. SUPC Output Function
7.2.4
Signal
I/O Pin
PSOK
PB00
OUT[0]
PB01
OUT[1]
PB02
VBAT
PB03
SERCOM I2C Pins
Table 7-6. SERCOM Pins Supporting I2C
Device
Pins Supporting I2C Hs mode
SAML21E
PA08, PA09, PA16, PA17, PA22, PA23
SAML21G
PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23
SAML21J
PA08, PA09, PA12, PA13, PA16, PA17, PA22, PA23, PB12, PB13, PB16, PB17, PB30,
PB31
Note: When the I2C is enabled, internal pull-up resistors are not available. External pull-up resistors are required for
proper function.
7.2.5
GPIO Clusters
Table 7-7. GPIO Clusters
PACKAGE
CLUSTER
GPIO
SUPPLIES PINS CONNECTED TO
THE CLUSTER
64pins
1
PB31
PB30
PA31
PA30
PA27
2
PB23
PB22
PA25
PA24
PA23
PA22
PA21
PA20
PB17
PB16
4
PA15
PA14
PA13
PA12
PB15
PB14
PB13
PB12
PB11
PB10
5
PA11
PA10
PA09
PA08
6
PA07
PA06
PA05
PA04
PB09
PB08
7
PA01
PA00
PB03
PB02
PB01
PB00
© 2020 Microchip Technology Inc.
VDDIN pin56/GND pin54
PA19
PA18
PA17
PA16
VDDIO pin 48/GND pin47 and VDDIO
pin34/GND pin33
VDDIO pin 34/GND pin33 and VDDIO
pin21/GND pin22
VDDIO pin21/GND pin22
PB07
PB06
PB05
PB04
PA03
PA02
VDDANA pin 8/GNDANA pin7
VSWOUT
DS60001477C-page 31
SAM L21 Family Data Sheet
I/O Multiplexing and Considerations
...........continued
PACKAGE
CLUSTER
GPIO
48pins
1
PA31
PA30
2
PA28
PA27
PB23
PB22
3
PA25
PA24
PA23
PA22
4
PA11
PA10
PA09
PA08
5
PA07
PA06
PA05
PA04
PB09
PB08
VDDANA pin6/GNDANA pin5
6
PA03
PA02
PA01
PA00
PB03
PB02
VDDANA pin6/GNDANA pin5
1
PA31
PA30
PA27
PA25
PA24
PA23
PA22
2
PA18
PA17
PA16
PA15
PA14
PA11
PA10
3
PA07
PA06
PA05
PA04
PA03
PA02
4
PA01
PA00
32pins
7.2.6
SUPPLIES PINS CONNECTED TO
THE CLUSTER
VDDIN pin44/GND pin42
VDDIN pin44/GND pin42 and VDDIO
pin36/GND pin35
PA21
PA20
PA19
PA18
PA17
PA16
PA15
PA14
PA13
PA12
PB11
PB10
VDDIO pin36/GND pin35 and VDDIO
pin17/GND pin18
VDDIO pin17/GND pin18
VDDIN pin30/GND pin 28
PA09
PA08
VDDANA pin9/GND pin 10
VDDANA pin9/GND pin10
VSWOUT
TCC Configurations
The SAM L21 has three instances of the Timer/Counter for Control applications (TCC) peripheral, TCC[2:0]. The
following table lists the features for each TCC instance.
Table 7-8. TCC Configuration Summary
TCC#
Channels
(CC_NUM)
Waveform
Output
(WO_NUM)
Counter size
Fault
Dithering
Output
matrix
Dead Time
Insertion
(DTI)
SWAP
Pattern
generation
0
4
8
24-bit
Yes
Yes
Yes
Yes
Yes
Yes
1
2
4
24-bit
Yes
Yes
2
2
2
16-bit
Yes
Yes
Note: The number of CC registers (CC_NUM) for each TCC corresponds to the number of compare/capture
channels, so that a TCC can have more Waveform Outputs (WO_NUM) than CC registers.
© 2020 Microchip Technology Inc.
DS60001477C-page 32
SAM L21 Family Data Sheet
Analog Connections of Peripherals
8.
Analog Connections of Peripherals
This chapter provides a global view of the analog system, the signal interconnections, and the ONDEMAND function
of the peripherals that process analog signals, such as AC, ADC, DAC, OPAMP.
8.1
Block Diagram
Figure 8-1. Interconnections of Analog Signal Components
GND
DAC
OA0TAP
+
OA0POS
ADC
VDDANA
OPAMP0
-
OA0NEG
DAC
OA0OUT
Not shared
with DAC
GND
UG
AIN0
+
VDDANA
-
VDD
SCALER
R2
HYSTERESIS
ENABLE
OA0TAP
Internal ref.
DAC0
output
buffer
VOUT0
R1
DAC1
output
buffer
COMPCTRLn
OA0POS
ENABLE
BANDGAP
GND
VREFA
INTREF
VDDANA
DAC
OA0NEG
DAC
CMP0
COMP0
AIN1
HYSTERESIS
+
AIN2
CMP1
COMP1
GND
VOUT1
AIN3
OA0OUT
OA1TAP
OA1POS
+
ADC
VDDANA
-
OPAMP2
OPAMP1
OA1OUT
-
OA1NEG
DAC
GND
UG
VDDANA
ADC0
ADC1
ADC2
...
ADCn
OPAMP01
R2
OA1TAP
MUXPOS
ADC
OPAMP2
R1
OA1POS
POST
PROCESSING
OA1NEG
OA0OUT
ADC0
...
GND
MUXNEG
ADCn
INT.SIG
INT.SIG
INTREF
OA0POS
INTVCC
OA1POS
GND
VREFA
VREFB
OA1OUT
OA0TAP
OA2POS
+
OA2OUT
OPAMP2
-
OA0NEG
PRESCALER
ADC/ AC
VDDANA
GND
UG
OA1NEG
OA2NEG
DAC
VDDANA
R2
OA2TAP
R1
OA2POS
OA2NEG
OA1OUT
GND
8.2
Analog Connections
The analog peripherals can be connected to each other according to the block diagram above. To configure a
particular peripheral refer to the corresponding description in this data sheet.
Peripherals can be connected through a pad. In this case, the digital functionality of the pad is lost and its
configuration must not interfere with the analog connection.
© 2020 Microchip Technology Inc.
DS60001477C-page 33
SAM L21 Family Data Sheet
Analog Connections of Peripherals
Important:
When an analog peripheral is enabled, the analog output of the peripheral will interfere with the alternative
functions of the output pads. This is also true even when the peripheral is used for internal purposes.
Analog inputs do not interfere with alternative pad functions.
References:
7. I/O Multiplexing and Considerations
8.3
Reference Voltages
Some analog peripherals require a reference voltage for proper operation. Aside from external voltages (i.e.,
VDDANA), the device provides has a DETREF module that provides two internal voltage references:
• BANDGAP: a stable voltage reference, refer to the Electrical Characteristics
• INTREF: a variable voltage reference, configured by the Voltage References System Control register in the
Supply Controller (SUPC.VREF)
The respective reference voltage source may be selected within the peripheral's registers:
• ADC: Reference Control register (ADC.REFCTRL)
• AC: Fixed to BANDGAP
• DAC: Reference Selection bits in the Control B register (DAC.CTRLB.REFSEL)
8.4
Analog ONDEMAND Function
General Function
The analog ONDEMAND feature allows other analog peripherals to request the OPAMP.
Note: The analog ONDEMAND is independent of the ONDEMAND bit located in each source clock controller, used
for requesting source clocks.
The OPAMP can be enabled by requests from ADC or AC.
The request mechanism is activated by writing a '1' to the OPAMP.OPAMPCTRLx.ONDEMAND bit. When a request
is sent by one of the peripherals to OPAMPx, the OPAMPx will start up and acknowledge the request as soon as it is
fully enabled.
If the OPAMP.OPAMPCTRLx.ONDEMAND bit is '0' but OPAMPx is enabled already, a request will be immediately
acknowledged. If OPAMPCTRLx.ONDEMAND=0 and the OPAMPx is disabled, requests will not be acknowledged:
requests are handled only when the OPAMP output is active (OPAMPCTRLx.ANAOUT=1).
In Standby sleep mode, the ONDEMAND operation is still active if OPAMPCTRLx.ONDEMAND=1. If
OPAMPCTRLx.ONDEMAND=0, the OPAMPx is disabled.
The OPAMP controller peripheral must be configured appropriately before being requested.
For the ADC peripheral, ONDEMAND requests to the OPAMP are enabled by writing the ADC.CTRLA.ONDEMAND
bit to '1'.
For the AC peripheral,there is no explicit ONDEMAND bit in the registers. ONDEMAND requests to OPAMPx are
issued either when the AC is used in single-shot mode, or when comparisons are triggered by events from the Event
System. The OPAMP must be selected as input of the AC previously.
When the Negative Input MUX Selection bit field of the Comparator 1 Control register is set to
DAC/OPAMP (AC.COMPCTRL1.MUXNEG=0x7), the AC will start issuing ONDEMAND requests to
OPAMP.
© 2020 Microchip Technology Inc.
DS60001477C-page 34
SAM L21 Family Data Sheet
Analog Connections of Peripherals
Alternative Requests
When OPAMPx is set to accept ONDEMAND requests (OPAMP.OPAMCTRLx.ONDEMAND=1) but the ADC is not
configured to issue requests to it (ADC.CTRLA.ONDEMAND=0), the ADC will send continuous requests to the
receiver selected by ADC.INPUTCTRL.MUXPOS.
If ADC.INPUTCTRL.MUXPOS=0x1E, OPAMP0 and OPAMP1 will receive requests.
If ADC.INPUTCTRL.MUXPOS=0x1F, only OPAMP2 will receive requests.
When OPAMPx is set to accept ONDEMAND requests (OPAMP.OPAMCTRLx.ONDEMAND=1) but the AC is not
configured to issue requests to it (AC.CTRLA.ONDEMAND=0), the AC will send continuous requests to the receiver
selected by AC.COMPCTRLx.MUXNEG.
If AC.COMPCTRL1.MUXNEG=0x7, OPAMP2 will receive requests.
If AC.COMPCTRL0.MUXNEG=0x7, DAC0 will receive requests.
References:
41. Operational Amplifier Controller (OPAMP)
AC
ADC
© 2020 Microchip Technology Inc.
DS60001477C-page 35
SAM L21 Family Data Sheet
Power Supply and Start-Up Considerations
PA[7:2]
PB[9:4]
VBAT (PB[3])
PA[31:27]
VBAT
VDDIN
VDDANA
ADC
PB[31:22]
VDDIN
VSW
GND
Power Domain Overview
VDDCORE
9.1
GNDANA
Power Supply and Start-Up Considerations
VDDANA
9.
VOLTAGE
REGULATOR
RTC, PM,
SUPC, RSTC
OSC16M
VDDBU
VSWOUT
BOD12
AC
PDBACKUP
DAC
PTC
POR
VOLTAGE
REGULATOR
BOD33
OSC32K
PB[3:0]
XOSC32K
PA[1:0]
OSCULP32K
OPAMP
VDDCORE
VDDIO
VDDIO
POR
PDTOP
Digital Logic
PD0
Digital Logic
PD1
Digital Logic
PD2
PD1
Digital Logic
EIC, WDT, PORT
MCLK OSCCTRL,
GCLK, EVSYS,
SERCOM5, TC4,
ADC, AC, PTC,
OPAMP, CC
SERCOM[4:0],
TCC[2:0]
TC[3:0], DAC,
I2S,
AES,
AES,
TRNG
TRNG
PAC, DMAC
SERCOM[4:0],
USB, DSU
NVMCTRL,
TCC[2:0]
CM0+
TC[3:0], DAC,
I2S,
AES,
TRNG
LOWNVM
POWER
PAC,
DMAC
RAM
DFLL48M
LOW POWER
RAM
LOW
HIGHPOWER
SPEED
RAM
PA[25:8]
PB[17:10]
XOSC
FDPLL96M
The Atmel SAM L21 power domains operate independenly of each other:
• VDDCORE, VDDIO and VDDIN share GND, whereas VDDANA refers to GNDANA.
• VDDANA and VDDIN must share the main supply, VDD.
• VDDCORE serves as the internal voltage regulator output. It powers the core, memories, peripherals, DFLL48M
and FDPLL96M.
• VSWOUT and VDDBU are internal power domains.
• On SAM L21E, VDDIO is electrically connected to the VDDANA domain and supplied through VDDANA.
9.2
Power Supply Considerations
9.2.1
Power Supplies
The Atmel SAM L21 has several different power supply pins:
•
•
•
•
VDDIO powers I/O lines and XOSC. Voltage is 1.62V to 3.63V
VDDIN powers I/O lines, OSC16M, the internal regulator for VDDCORE and the Automatic Power Switch.
Voltage is 1.62V to 3.63V
VDDANA powers I/O lines and the ADC, AC, DAC, PTC and OPAMP. Voltage is 1.62V to 3.63V
VBAT powers the Automatic Power Switch. Voltage is 1.62V to 3.63V
© 2020 Microchip Technology Inc.
DS60001477C-page 36
SAM L21 Family Data Sheet
Power Supply and Start-Up Considerations
•
•
VDDCORE serves as the internal voltage regulator output. It powers the core, memories, peripherals, DFLL48M
and FDPLL96M. Voltage is 0.9V to 1.2V typical.
The Automatic Power Switch is a configurable switch that selects between VDDIN and VBAT as supply for the
internal output VSWOUT, see the figure in Power Domain Overview.
The same voltage must be applied to both VDDIN and VDDANA. This common voltage is referred to as VDD in the
datasheet.
When the Peripheral Touch Controller (PTC) is used, VDDIO must be equal to VDD. When the PTC is not used by
the user application, VDDIO may be lower than VDD.
The ground pins, GND, are common to VDDCORE, VDDIO and VDDIN. The ground pin for VDDANA is GNDANA.
For decoupling recommendations for the different power supplies, refer to the schematic checklist.
References:
51. Schematic Checklist
9.2.2
Voltage Regulator
The SAM L21 internal Voltage Regulator has four different modes:
•
•
•
•
Linear mode: This is the default mode when CPU and peripherals are running. It does not require an external
inductor.
Switching mode. This is the most efficient mode when the CPU and peripherals are running. This mode can be
selected by software on the fly.
Low Power (LP) mode. This is the default mode used when the chip is in standby mode.
Shutdown mode. When the chip is in backup mode, the internal regulator is off.
Note that the Voltage Regulator modes are controlled by the Power Manager.
9.2.3
Typical Powering Schematic
The SAM L21 uses a single supply from 1.62V to 3.63V.
The following figure shows the recommended power supply connection.
© 2020 Microchip Technology Inc.
DS60001477C-page 37
SAM L21 Family Data Sheet
Power Supply and Start-Up Considerations
Figure 9-1. Power Supply Connection for Linear Mode Only
SAM L21
IOs Supply
(1.62V — 3.63V)
Main Supply
VBAT (PB03)
VDDIO
VDDANA
(1.62V — 3.63V)
VDDIN
VSW
VDDCORE
GND
GNDANA
Figure 9-2. Power Supply Connection for Switching/Linear Mode
SAM L21
IOs Supply
(1.62V — 3.63V)
Main Supply
VDDIO
VBAT (PB03)
VDDANA
(1.62V — 3.63V)
VDDIN
VSW
VDDCORE
GND
GNDANA
© 2020 Microchip Technology Inc.
DS60001477C-page 38
SAM L21 Family Data Sheet
Power Supply and Start-Up Considerations
Figure 9-3. Power Supply Connection for Battery Backup
SAM L21
IOs Supply
(1.62V — 3.63V)
Main Supply
VDDIO
VBAT (PB03)
VDDANA
(1.62V — 3.63V)
VDDIN
VSW
VDDCORE
GND
GNDANA
9.2.4
Power-Up Sequence
9.2.4.1
Supply Order
VDDIN and VDDANA must have the same supply sequence. Ideally, they must be connected together.
VDDIO can rise before or after VDDIN and VDDANA. Note that VDDIO supplies the XOSC, so VDDIO must be
present before the application uses the XOSC feature. This is also applicable to all digital features present on pins
supplied by VDDIO.
9.2.4.2
Minimum Rise Rate
The two integrated power-on reset (POR) circuits monitoring VDDIN and VDDIO require a minimum rise rate.
References:
Electrical Characteristics46. Electrical Characteristics
9.2.4.3
Maximum Rise Rate
The rise rate of the power supplies must not exceed the values described in Electrical Characteristics.
References:
46. Electrical Characteristics
9.3
Power-Up
This section summarizes the power-up sequence of the SAM L21. The behavior after power-up is controlled by the
Power Manager.
References:
20. PM – Power Manager
© 2020 Microchip Technology Inc.
DS60001477C-page 39
SAM L21 Family Data Sheet
Power Supply and Start-Up Considerations
9.3.1
Starting of Internal Regulator
After power-up, the device is set to its initial state and kept in Reset, until the power has stabilized throughout the
device. The default performance level after power-up is PL0. See section on 20. PM – Power Manager for details.
The internal regulator provides the internal VDDCORE corresponding to this performance level. Once the external
voltage VDDIN and the internal VDDCORE reach a stable value, the internal Reset is released.
9.3.2
Starting of Clocks
Once the power has stabilized and the internal Reset is released, the device will use a 4MHz clock by default. The
clock source for this clock signal is OSC16M, which is enabled and configured at 4MHz after a reset by default. This
is also the default time base for Generic Clock Generator 0. In turn, Generator 0 provides the main clock
GCLK_MAIN which is used by the Power Manager (PM).
Some synchronous system clocks are active after Start-Up, allowing software execution. Synchronous system clocks
that are running receive the 4MHz clock from Generic Clock Generator 0. Other generic clocks are disabled.
References:
20. PM – Power Manager
18.6.2.6 Peripheral Clock Masking
9.3.3
I/O Pins
After power-up, the I/O pins are tri-stated except PA30, which is pull-up enabled and configured as input.
References:
20. PM – Power Manager
9.3.4
Fetching of Initial Instructions
After Reset has been released, the CPU starts fetching PC and SP values from the Reset address, 0x00000000. This
points to the first executable address in the internal Flash memory. The code read from the internal Flash can be
used to configure the clock system and clock sources. Refer to the ARM Architecture Reference Manual for more
information on CPU startup (http://www.arm.com).
References:
20. PM – Power Manager
17. GCLK - Generic Clock Controller
21. OSCCTRL – Oscillators Controller
22. OSC32KCTRL – 32KHz Oscillators Controller
9.4
Power-On Reset and Brown-Out Detector
The SAM L21 embeds three features to monitor, warn and/or reset the device:
• POR: Power-on Reset on VDDIN, VSWOUT and VDDIO
• BOD33: Brown-out detector on VSWOUT/VBAT
• Brown-out detector internal to the voltage regulator for VDDCORE. BOD12 is calibrated in production and its
calibration parameters are stored in the NVM User Row. This data should not be changed if the User Row is
written to in order to assure correct behavior.
9.4.1
Power-On Reset on VDDIN
VDDIN is monitored by POR. Monitoring is always activated, including startup and all sleep modes. If VDDIN goes
below the threshold voltage, the entire chip is reset.
9.4.2
Power-On Reset on VSWOUT
VSWOUT is monitored by POR. Monitoring is always activated, including startup and all sleep modes. If VSWOUT
goes below the threshold voltage, the entire chip is reset.
© 2020 Microchip Technology Inc.
DS60001477C-page 40
SAM L21 Family Data Sheet
Power Supply and Start-Up Considerations
9.4.3
Power-On Reset on VDDIO
VDDIO is monitored by POR. Monitoring is always activated, including startup and all sleep modes. If VDDIO goes
below the threshold voltage, all I/Os supplied by VSWOUT are reset.
9.4.4
Brown-Out Detector on VSWOUT/VBAT
BOD33 monitors VSWOUT or VBAT depending on configuration.
References:
23. SUPC – Supply Controller
SUPC - Battery Backup Power Switch
9.4.5
Brown-Out Detector on VDDCORE
Once the device has started up, BOD12 monitors the internal VDDCORE.
References:
23. SUPC – Supply Controller
SUPC - Battery Backup Power Switch
9.5
Performance Level Overview
By default, the device will start in Performance Level 0. This PL0 is aiming for the lowest power consumption by
limiting logic speeds and the CPU frequency. As a consequence, all GCLK will have limited capabilities, and some
peripherals and clock sources will not work or with limited capabilities:
List of peripherals/clock sources not available in PL0:
• USB (limited by logic frequency)
• DFLL48M
List of peripherals/clock sources with limited capabilities in PL0:
• All AHB/APB peripherals are limited by CPU frequency
• DPLL96M: may be able to generate 48MHz internally, but the output cannot be used by logic
• GCLK: the maximum frequency is by factor 4 compared to PL2
• SW interface: the maximum frequency is by factor 4 compared to PL2
• TC: the maximum frequency is by factor 4 compared to PL2
• TCC:the maximum frequency is by factor 4 compared to PL2
• SERCOM: the maximum frequency is by factor 4 compared to PL2
List of peripherals/clock sources with full capabilities in PL0:
• AC
• ADC
• DAC
• EIC
• OPAMP
• OSC16M
• PTC
• All 32KHz clock sources and peripherals
Full functionality and capability will be ensured in PL2. When transitioning between performance levels, the Supply
Controller (SUPC) will provide a configurable smooth voltage scaling transition.
References:
20. PM – Power Manager
23. SUPC – Supply Controller
Block Diagram
© 2020 Microchip Technology Inc.
DS60001477C-page 41
SAM L21 Family Data Sheet
Product Mapping
10.
Product Mapping
Figure 10-1. Atmel SAM L21 Product Mapping
Global Memory Space
0x00000000
Code
0x40000000
0x00000000
Internal Flash
Code
0x20000000
0x00400000
SRAM
Undefined
0x40000800
Reserved
SRAM
0x20000000
0x40000000
SRAM
Low Power
0x40002400
Undefined
AHB-APB
0x40000000
0x60000200
AHB-APB
Bridge A
System
Reserved
Reserved
0x42000000
AHB-APB
Bridge C
SCS
Reserved
0x43000000
AHB-APB
Bridge D
ROMTable
Reserved
0x41002000
0x41004000
0x41006000
0x41008000
0x41FFFFFF
RSTC
OSCCTRL
OSC32KCTRL
SUPC
GCLK
WDT
RTC
EIC
PORT
Reserved
0x40FFFFFF
AHB-APB
Bridge E
USB
0x44FFFFFF
AHB-APB Bridge E
DSU
0x44000000
NVMCTRL
0x44000400
MTB
0x44000800
Reserved
0x44FFFFFF
© 2020 Microchip Technology Inc.
AHB-APB Bridge C
0x42000000
0x42000400
0x42000800
0x42000C00
0x42001000
0x42001400
0x42001800
0x42001C00
0x42002000
0x42002400
AHB-APB Bridge D
0x43000000
0x43000400
0x43000800
0x44000000
AHB-APB Bridge B
0x41000000
0x40002C00
MCLK
AHB-APB
Bridge B
System
0xFFFFFFFF
0x40002800
PM
0x41000000
0xFFFFFFFF
0xE0100000
0x40002000
0x30002000
0x60000000
0xE00FF000
0x40001800
0x40001C00
0x30000000
Reserved
0x40001000
0x20008000
0x43000000
0xE000F000
0x40000C00
0x40001400
Internal SRAM
Peripherals
0xE000E000
0x40000400
0x1FFFFFFF
0x22008000
0xE0000000
AHB-APB Bridge A
0x43000C00
0x43001000
0x43001400
PAC
0x43001800
DMAC
0x43001C00
Reserved
0x43002000
0x42002800
EVSYS
0x42002C00
SERCOM5
0x42003000
TC4
0x42003400
ADC
0x42003800
AC
0x42003C00
PTC
SERCOM0
SERCOM1
SERCOM2
SERCOM3
SERCOM4
TCC0
TCC1
TCC2
TC0
TC1
TC2
TC3
DAC
AES
0x42FFFFFF
TRNG
Reserved
OPAMP
CCL
Reserved
0x43FFFFFF
DS60001477C-page 42
SAM L21 Family Data Sheet
Memories
11.
Memories
11.1
Embedded Memories
•
•
•
11.2
Internal high-speed Flash with Read-While-Write (RWW) capability on a section of the array
Internal high-speed RAM, single-cycle access at full speed
Internal low-power RAM, single-cycle access at full speed
Physical Memory Map
The high-speed bus is implemented as a bus matrix. All high-speed bus addresses are fixed, and they are never
remapped in any way, even during boot. The 32-bit physical address space is mapped as follows:
Table 11-1. SAM L21 Physical Memory Map(1)
Memory
Start address
Size [KB]
SAML21x18
SAML21x17
SAML21x16
SAML21E15
Embedded Flash
0x00000000
256
128
64
32
Embedded RWW section
0x00400000
8
4
2
1
Embedded SRAM
0x20000000
32
16
8
4
Embedded low-power SRAM
0x30000000
8
8
4
2
Peripheral Bridge A
0x40000000
64
64
64
64
Peripheral Bridge B
0x41000000
64
64
64
64
Peripheral Bridge C
0x42000000
64
64
64
64
Peripheral Bridge D
0x43000000
64
64
64
64
Peripheral Bridge E
0x44000000
64
64
64
64
IOBUS
0x60000000
0.5
0.5
0.5
0.5
Note: 1. x = G, J, or E.
Table 11-2. Flash Memory Parameters(1)
Device
Flash size [KB]
Number of pages
Page size [Bytes]
SAML21x18
256
4096
64
SAML21x17
128
2048
64
SAML21x16
64
1024
64
SAML21E15
32
512
64
Note: 1. x = G, J, or E.
Table 11-3. RWW Section Parameters(1)
Device
Flash size [KB]
Number of pages
Page size [Bytes]
SAML21x18
8
128
64
SAML21x17
4
64
64
© 2020 Microchip Technology Inc.
DS60001477C-page 43
SAM L21 Family Data Sheet
Memories
...........continued
Device
Flash size [KB]
Number of pages
Page size [Bytes]
SAML21x16
2
32
64
SAML21E15
1
16
64
Note: 1. x = G, J, or E.
11.3
NVM User Row Mapping
The Non Volatile Memory (NVM) User Row contains calibration data that are automatically read at device power-on.
The NVM User Row can be read at address 0x00804000.
To write the NVM User Row refer to the documentation of the NVMCTRL - Non-Volatile Memory Controller.
Note: When writing to the User Row, the new values do not get loaded by the other peripherals on the device until a
device Reset occurs.
Table 11-4. NVM User Row Mapping
Bit Pos. Name
Usage
Factory
Setting
Related Peripheral
Register
2:0
BOOTPROT
Used to select one of eight different
bootloader sizes.
0x7
NVMCTRL
3
Reserved
—
0x1
—
6:4
EEPROM
Used to select one of eight different
EEPROM sizes.
0x7
NVMCTRL
7
Reserved
—
0x1
—
13:8
BOD33 Level
BOD33 threshold level at power-on.
0x06
SUPC.BOD33
14
BOD33 Disable
BOD33 Disable at power-on.
0x0
SUPC.BOD33
16:15
BOD33 Action
BOD33 Action at power-on.
0x1
SUPC.BOD33
25:17
Reserved
Factory settings - do not change.
0x08F
-
26
WDT Enable
WDT Enable at power-on.
0x0
WDT.CTRLA
27
WDT Always-On
WDT Always-On at power-on.
0x0
WDT.CTRLA
31:28
WDT Period
WDT Period at power-on.
0xB
WDT.CONFIG
35:32
WDT Window
WDT Window mode time-out at power-on.
0xB
WDT.CONFIG
39:36
WDT EWOFFSET WDT Early Warning Interrupt Time Offset
at power-on.
0xB
WDT.EWCTRL
40
WDT WEN
0x0
WDT.CTRLA
41
BOD33 Hysteresis BOD33 Hysteresis configuration at poweron.
0x0
SUPC.BOD33
42
BOD12 Hysteresis ENG: BOD12 Hysteresis configuration at
power-on.
'0'
SUPC.BOD12
47:42
Reserved
Factory settings - do not change.
0x3E
—
63:48
LOCK
NVM Region Lock Bits.
0xFFFF
NVMCTRL
WDT Timer Window Mode Enable at
power-on.
References:
© 2020 Microchip Technology Inc.
DS60001477C-page 44
SAM L21 Family Data Sheet
Memories
NVMCTRL
SUPC
WDT
11.4
NVM Software Calibration Area Mapping
The NVM Software Calibration Area contains calibration data that are determined and written during production test.
These calibration values should be read by the application software and written back to the corresponding register.
The NVM Software Calibration Area can be read at address 0x00806020.
The NVM Software Calibration Area can not be written.
Table 11-5. NVM Software Calibration Area Mapping
Bit Position Name
Description
2:0
BIASREFBUF
ADC linearity. To be written to ADC CALIB.BIASREFBUF
5:3
BIASCOMP
ADC bias calibration. To be written to ADC CALIB.BIASCOMP
12:6
OSC32KCAL
OSC32K calibration. To be written to OSC32KCTRL OSC32K.CALIB
17:13
USB_TRANSN
USB pad calibration. To be written to USB PADCAL.TRANSN
22:18
USB_TRANSP
USB pad calibration. To be written to USB PADCAL.TRANSP
25:23
USB_TRIM
USB pad calibration. To be written to USB PADCAL.TRIM
31:26
DFLL48M_COARSE_CAL DFLL48M coarse calibration. To be written to OSCCTRL
DFLLVAL.COARSE
References:
ADC - Calibration Register
USB -Pad Calibration Register
OSCCTRL - DFLLVAL Register
11.5
NVM Temperature Log Row
The NVM Temperature Log Row contains calibration data that are determined and written during production test.
These calibration values are required for calculating the temperature from measuring the temperature sensor in the
Supply Controller (SUPC) by the ADC.
The NVM Temperature Log Row can be read at address 0x00806030.
The NVM Temperature Log Row can not be written.
Table 11-6. Temperature Log Row Content
Bit Position
Name
Description
7:0
ROOM_TEMP_VAL_INT
Integer part of room temperature in °C
11:8
ROOM_TEMP_VAL_DEC
Decimal part of room temperature
19:12
HOT_TEMP_VAL_INT
Integer part of hot temperature in °C
23:20
HOT_TEMP_VAL_DEC
Decimal part of hot temperature
31:24
ROOM_INT1V_VAL
2’s complement of the internal 1V reference drift at room temperature (versus a 1.0 centered value)
39:32
HOT_INT1V_VAL
2’s complement of the internal 1V reference drift at hot temperature (versus a 1.0 centered value)
© 2020 Microchip Technology Inc.
DS60001477C-page 45
SAM L21 Family Data Sheet
Memories
...........continued
Bit Position
Name
Description
51:40
ROOM_ADC_VAL
Temperature sensor 12bit ADC conversion at room temperature
63:52
HOT_ADC_VAL
Temperature sensor 12bit ADC conversion at hot temperature
References:
42.6.3.2 Device Temperature Measurement
46.10.9 Temperature Sensor Characteristics
11.6
Serial Number
Each device has a unique 128-bit serial number which is a concatenation of four 32-bit words contained at the
following addresses:
Word 0: 0x0080A00C
Word 1: 0x0080A040
Word 2: 0x0080A044
Word 3: 0x0080A048
The uniqueness of the serial number is guaranteed only when using all 128 bits.
© 2020 Microchip Technology Inc.
DS60001477C-page 46
SAM L21 Family Data Sheet
Processor and Architecture
12.
Processor and Architecture
12.1
Cortex M0+ Processor
The Atmel SAM L21 implements the ARM®Cortex™-M0+ processor, based on the ARMv6 Architecture and
Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and
upward compatible to Cortex-M3 and M4 cores. The implemented ARM Cortex-M0+ is revision r0p1. For more
information refer to http://www.arm.com
12.1.1
Cortex M0+ Configuration
Table 12-1. Cortex M0+ Configuration in Atmel SAM L21
Features
Cortex M0+ options
Atmel SAM L21 configuration
Interrupts
External interrupts 0-32
29
Data endianness
Little-endian or big-endian
Little-endian
SysTick timer
Present or absent
Present
Number of watchpoint comparators
0, 1, 2
2
Number of breakpoint comparators
0, 1, 2, 3, 4
4
Halting debug support
Present or absent
Present
Multiplier
Fast or small
Fast (single cycle)
Single-cycle I/O port
Present or absent
Present
Wake-up interrupt controller
Supported or not supported
Not supported
Vector Table Offset Register
Present or absent
Present
Unprivileged/Privileged support
Present or absent
Absent - All software run in privileged
mode only
Memory Protection Unit
Not present or 8-region
Not present
Reset all registers
Present or absent
Absent
Instruction fetch width
16-bit only or mostly 32-bit
32-bit
The ARM Cortex-M0+ core has two bus interfaces:
•
•
Single 32-bit AMBA-3 AHB-Lite system interface that provides connections to peripherals and all system
memory including Flash memory and RAM
Single 32-bit I/O port bus interfacing to the PORT with 1-cycle loads and stores
12.1.1.1 Cortex M0+ Peripherals
•
•
System Control Space (SCS)
– The processor provides debug through registers in the SCS. Refer to the Cortex-M0+ Technical Reference
Manual for details (http://www.arm.com)
Nested Vector Interrupt Controller (NVIC)
– External interrupt signals connect to the NVIC, and the NVIC prioritizes the interrupts. Software can set the
priority of each interrupt. The NVIC and the Cortex-M0+ processor core are closely coupled, providing low
latency interrupt processing and efficient processing of late arriving interrupts. Refer to the Cortex-M0+
Technical Reference Manual for details (http://www.arm.com).
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SAM L21 Family Data Sheet
Processor and Architecture
•
•
•
Note: When the CPU frequency is much higher than the APB frequency it is recommended to insert a
memory read barrier after each CPU write to registers mapped on the APB. Failing to do so in such
conditions may lead to unexpected behavior such as re-entering a peripheral interrupt handler just after
leaving it.
System Timer (SysTick)
– The System Timer is a 24-bit timer clocked by CLK_CPU that extends the functionality of both the
processor and the NVIC. Refer to the Cortex-M0+ Technical Reference Manual for details (http://
www.arm.com).
System Control Block (SCB)
– The System Control Block provides system implementation information, and system control. This includes
configuration, control, and reporting of the system exceptions. Refer to the Cortex-M0+ Devices Generic
User Guide for details (http://www.arm.com)
Micro Trace Buffer (MTB)
– The CoreSight MTB-M0+ (MTB) provides a simple execution trace capability to the Cortex-M0+ processor.
Refer to section MTB-Micro Trace Buffer and the CoreSight MTB-M0+ Technical Reference Manual for
details (http://www.arm.com).
12.1.1.2 Cortex M0+ Address Map
Table 12-2. Cortex-M0+ Address Map
Address
Peripheral
0xE000E000
System Control Space (SCS)
0xE000E010
System Timer (SysTick)
0xE000E100
Nested Vectored Interrupt Controller (NVIC)
0xE000ED00
System Control Block (SCB)
0x41006000
Micro Trace Buffer (MTB)
12.1.1.3 I/O Interface
The device allows direct access to PORT registers. Accesses to the AMBA® AHB-Lite™ and the single cycle I/O
interface can be made concurrently, so the Cortex M0+ processor can fetch the next instructions while accessing the
I/Os. This enables single cycle I/O access to be sustained for as long as necessary.
References:
29. PORT - I/O Pin Controller
12.2
Nested Vector Interrupt Controller
12.2.1
Overview
The Nested Vectored Interrupt Controller (NVIC) in the SAM L21 supports 32 interrupt lines with four different priority
levels. For more details, refer to the Cortex-M0+ Technical Reference Manual (http://www.arm.com).
12.2.2
Interrupt Line Mapping
Each of the 28 interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral
can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register.
An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually
enabled by writing a 1 to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and
disabled by writing 1 to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register.
An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is
enabled.
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SAM L21 Family Data Sheet
Processor and Architecture
The interrupt requests for one peripheral are ORed together on system level, generating one interrupt request for
each peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending
registers (SETPEND/CLRPEND bits in ISPR/ICPR).
For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA
bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.
Table 12-3. Interrupt Line Mapping
Peripheral source
NVIC line
EIC NMI – External Interrupt Controller
NMI
PM – Power Manager
0
MCLK - Main Clock
OSCCTRL - Oscillators Controller
OSC32KCTRL - 32KHz Oscillators Controller
SUPC - Supply Controller
PAC - Protecion Access Controller
WDT – Watchdog Timer
1
RTC – Real Time Counter
2
EIC – External Interrupt Controller
3
NVMCTRL – Non-Volatile Memory Controller
4
DMAC - Direct Memory Access Controller
5
USB - Universal Serial Bus
6
EVSYS – Event System
7
SERCOM0 – Serial Communication Interface 0
8
SERCOM1 – Serial Communication Interface 1
9
SERCOM2 – Serial Communication Interface 2
10
SERCOM3 – Serial Communication Interface 3
11
SERCOM4 – Serial Communication Interface 4
12
SERCOM5 – Serial Communication Interface 5
13
TCC0 – Timer Counter for Control 0
14
TCC1 – Timer Counter for Control 1
15
TCC2 – Timer Counter for Control 2
16
TC0 – Timer Counter 0
17
TC1 – Timer Counter 1
18
TC2 – Timer Counter 2
19
TC3 – Timer Counter 3
20
TC4 – Timer Counter 4
21
ADC – Analog-to-Digital Converter
22
AC – Analog Comparator
23
DAC – Digital-to-Analog Converter
24
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SAM L21 Family Data Sheet
Processor and Architecture
...........continued
Peripheral source
NVIC line
PTC – Peripheral Touch Controller
25
AES - Advanced Encrytpion Standard module
26
TRNG - True Random Number Generator
27
12.3
Micro Trace Buffer
12.3.1
Features
•
•
•
•
12.3.2
Program flow tracing for the Cortex-M0+ processor
MTB SRAM can be used for both trace and general purpose storage by the processor
The position and size of the trace buffer in SRAM is configurable by software
CoreSight compliant
Overview
When enabled, the MTB records the changes in program flow that are reported by the Cortex-M0+ processor over
the execution trace interface. This interface is shared between the Cortex-M0+ processor and the CoreSight MTBM0+. The information is stored by the MTB in the SRAM as trace packets. An off-chip debugger can extract the trace
information using the Debug Access Port to read the trace information from the SRAM. The debugger can then
reconstruct the program flow from this information.
The MTB stores trace information into the SRAM and gives the processor access to the SRAM simultaneously. The
MTB ensures that trace write accesses have priority over processor accesses.
An execution trace packet consists of a pair of 32-bit words that the MTB generates when it detects a non-sequential
change of the program pounter (PC) value. A non-sequential PC change can occur during branch instructions or
during exception entry. See the CoreSight MTB-M0+ Technical Reference Manual for more details on the MTB
execution trace packet format.
Tracing is enabled when the MASTER.EN bit in the Master Trace Control Register is 1. There are various ways to set
the bit to 1 to start tracing, or to 0 to stop tracing. See the CoreSight Cortex-M0+ Technical Reference Manual for
more details on the Trace start and stop and for a detailed description of the MTB’s MASTER register. The MTB can
be programmed to stop tracing automatically when the memory fills to a specified watermark level or to start or stop
tracing by writing directly to the MASTER.EN bit. If the watermark mechanism is not being used and the trace buffer
overflows, then the buffer wraps around overwriting previous trace packets.
The base address of the MTB registers is 0x41006000; this address is also written in the CoreSight ROM Table. The
offset of each register from the base address is fixed and as defined by the CoreSight MTB-M0+ Technical Reference
Manual. The MTB has four programmable registers to control the behavior of the trace features:
• POSITION: Contains the trace write pointer and the wrap bit
• MASTER: Contains the main trace enable bit and other trace control fields
• FLOW: Contains the WATERMARK address and the AUTOSTOP and AUTOHALT control bits
• BASE: Indicates where the SRAM is located in the processor memory map. This register is provided to enable
auto discovery of the MTB SRAM location by a debug agent
See the CoreSight MTB-M0+ Technical Reference Manual for a detailed description of these registers.
12.4
12.4.1
High-Speed Bus System
Overview
The High-Speed Bus System combines two Bus Interconnection Matrixes for standard Master/Slave communication,
and two unified FlexRAM System Memory areas with multiple access capabilities. Some masters from a matrix can
connect some slaves on the other matrix thanks to two low-latency AHB to AHB bridges: H2LBRIDGE and
L2HBRIDGE.
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SAM L21 Family Data Sheet
Processor and Architecture
12.4.2
Features
High-Speed Bus Matrix has the following features:
•
•
•
•
Symmetric crossbar bus switch implementation
Allows concurrent accesses from different masters to different slaves
32-bit data bus
Operation at a one-to-one clock frequency with the bus masters
H2LBRIDGE has the following features:
• LP clock division support
• Write: Posted-write FIFO of 3 words, no bus stall until it is full
• Write: 1 cycle bus stall when full when LP clock is not divided
• 2 stall cycles on read when LP clock is not divided
• Ultra low latency mode:
– Suitable when the HS clock frequency is not above half the maximum device clock frequency
– Removes all intrinsic bridge stall cycles (except those needed for LP clock ratio adaptation)
– Enabled by writing a '1' in 0x41008120 using a 32-bit write access
L2HBRIDGE has the following features:
• LP clock division support
• Write: Posted-write FIFO of 1 word, no bus stall until it is full
• Write: 1 cycle bus stall when full when LP clock is not divided
• 2 stall cycles on read when LP clock is not divided
• ultra low latency mode:
– Suitable when the HS clock frequency is not above half the maximum device clock frequency
– Removes all intrinsic bridge stall cycles (except those needed for LP clock ratio adaptation)
– Enabled by writing a '1' in 0x41008120 using a 32-bit write access
Figure 12-1. High-Speed Bus System Components
M M
H2LBRIDGES S
H2LBRIDGE
HMATRIXLP
HMATRIXHS
S S S S S
© 2020 Microchip Technology Inc.
M M
M H2LBRIDGEM
L2HBRIDGES M
L2HBRIDGE
S L2HBRIDGES
S S S S S S S S
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SAM L21 Family Data Sheet
Processor and Architecture
Configuration
Figure 12-2. Master-Slave Relations High-Speed Bus Matrix
High-Speed Bus
MASTERS
CM0+
0
DSU
1
L2HBRIDGEM
2
Internal Flash
HS SRAM PORT 0
HS SRAM PORT 1
AHB-APB Bridge B
H2LBRIDGES
High-Speed Bus SLAVES
0
1
2
3
4
Figure 12-3. Master-Slave Relations Low-Power Bus Matrix
H2LBRIDGEM
0
DMAC
2
AHB-APB Bridge A
AHB-APB Bridge C
AHB-APB Bridge D
AHB-APB Bridge E
LP SRAM PORT 2
LP SRAM PORT 1
L2HBRIDGES
HS SRAM PORT 2
Low-Power Bus SLAVES
Low-Power Bus
MASTERS
12.4.3
0
1
2
3
5
7
8
9
Table 12-4. High-Speed Bus Matrix Masters
High-Speed Bus Matrix Masters
Master ID
CM0+ - Cortex M0+ Processor
0
DSU - Device Service Unit
1
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SAM L21 Family Data Sheet
Processor and Architecture
...........continued
High-Speed Bus Matrix Masters
Master ID
L2HBRIDGEM - Low-Power to High-Speed bus matrix
AHB to AHB bridge
2
Table 12-5. High-Speed Bus Matrix Slaves
High-Speed Bus Matrix Slaves
Slave ID
Internal Flash Memory
0
HS SRAM Port 0 - CM0+ Access
1
HS SRAM Port 1 - DSU Access
2
AHB-APB Bridge B
3
H2LBRIDGES - High-Speed to Low-Power bus matrix
AHB to AHB bridge
4
Table 12-6. Low-Power Bus Matrix Masters
Low-Power Bus Matrix Masters
Master ID
H2LBRIDGEM - High-Speed to Low-Power bus matrix
AHB to AHB bridge
0
DMAC - Direct Memory Access Controller - Data Access
2
Table 12-7. Low-Power Bus Matrix Slaves
12.4.4
Low-Power Bus Matrix Slaves
Slave ID
AHB-APB Bridge A
0
AHB-APB Bridge C
1
AHB-APB Bridge D
2
AHB-APB Bridge E
3
LP SRAM Port 2- H2LBRIDGEM access
5
LP SRAM Port 1- DMAC access
7
L2HBRIDGES - Low-Power to High-Speed bus matrix
AHB to AHB bridge
8
HS SRAM Port 2- HMATRIXLP access
9
SRAM Quality of Service
To ensure that masters with latency requirements get sufficient priority when accessing RAM, priority levels can be
assigned to the masters for different types of access.
The Quality of Service (QoS) level is independently selected for each master accessing the RAM. For any access to
the RAM, the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level
configuration are shown in the following table.
Table 12-8. Quality of Service
Value
Name
Description
0x0
DISABLE
Background (no sensitive operation)
0x1
LOW
Sensitive Bandwidth
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Processor and Architecture
...........continued
Value
Name
Description
0x2
MEDIUM
Sensitive Latency
0x3
HIGH
Critical Latency
If a master is configured with QoS level DISABLE (0x0) or LOW (0x1) there will be a minimum latency of one cycle
for the RAM access.
The priority order for concurrent accesses are decided by two factors. First, the QoS level for the master and second,
a static priority given by the port ID. The lowest port ID has the highest static priority. See the tables below for details.
The MTB has a fixed QoS level HIGH (0x3).
The CPU QoS level can be written/read, using 32-bit access only, at address 0x41008114 bits [1:0]. Its reset value is
0x3.
Refer to different master QOSCTRL registers for configuring QoS for the other masters (USB, DMAC).
Table 12-9. HS SRAM Port Connections QoS
HS SRAM Port Connection
Port ID
Connection Type
QoS
default QoS
MTB - Micro Trace Buffer
4
Direct
STATIC-3
0x3
USB - Universal Serial Bus
3
Direct
IP-QOSCTRL
0x3
HMATRIXLP - Low-Power Bus
Matrix
2
Bus Matrix
0x44000934(1),
DSU - Device Service Unit
1
Bus Matrix
0x4100201C(1)
0x2
CM0+ - Cortex M0+ Processor
0
Bus Matrix
0x41008114(1), bits[1:0]
0x3
bits[1:0]
0x2
Note:
1. Using 32-bit access only.
Table 12-10. LP SRAM Port Connections QoS
LP SRAM Port Connection
Port ID
Connection Type
QoS
default QoS
DMAC - Direct Memory Access
Controller - Write-Back Access
5, 6
Direct
IP-QOSCTRL.WRBQOS
0x2
DMAC - Direct Memory Access
Controller - Fetch Access
3, 4
Direct
IP-QOSCTRL.FQOS
0x2
H2LBRIDGEM - HS to LP bus
matrix AHB to AHB bridge
2
Bus Matrix
0x44000924(1), bits[1:0]
0x2
DMAC - Direct Memory Access
Controller - Data Access
1
Bus Matrix
IP-QOSCTRL.DQOS
0x2
Note:
1. Using 32-bit access only.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.
PAC - Peripheral Access Controller
13.1
Overview
The Peripheral Access Controller provides an interface for the locking and unlocking of peripheral registers within the
device. It reports all violations that could happen when accessing a peripheral: write protected access, illegal access,
enable protected access, access when clock synchronization or software reset is on-going. These errors are reported
in a unique interrupt flag for a peripheral. The PAC module also reports errors occurring at the slave bus level, when
an access to a non-existing address is detected.
13.2
Features
•
13.3
Manages write protection access and reports access errors for the peripheral modules or bridges
Block Diagram
Figure 13-1. PAC Block Diagram
PAC
IRQ
Slave ERROR
SLAVEs
INTFLAG
APB
Peripheral ERROR
PERIPHERAL m
BUSn
WRITE CONTROL
PAC CONTROL
PERIPHERAL 0
Peripheral ERROR
PERIPHERAL m
BUS0
WRITE CONTROL
13.4
PERIPHERAL 0
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
13.4.1
I/O Lines
Not applicable.
13.4.2
Power Management
The PAC can continue to operate in any sleep mode where the selected source clock is running. The PAC interrupts
can be used to wake up the device from sleep modes. The events can trigger other operations in the system without
exiting sleep modes.
References:
20. PM – Power Manager
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SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.4.3
Clocks
The PAC bus clock (CLK_PAC_APB) can be enabled and disabled in the Main Clock module. The default state of
CLK_PAC_APB can be found in the referenced links.
References:
18. MCLK – Main Clock
18.6.2.6 Peripheral Clock Masking
13.4.4
DMA
Not applicable.
13.4.5
Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the PAC interrupt requires the Interrupt
Controller to be configured first. Refer to 12.2 Nested Vector Interrupt Controller for more details.
Table 13-1. Interrupt Lines
13.4.6
Instances
NVIC Line
PAC
PACERR
Events
The events are connected to the Event System, which may need configuration.
References:
30. EVSYS – Event System
13.4.7
Debug Operation
When the CPU is halted in debug mode, write protection of all peripherals is disabled and the PAC continues normal
operation.
13.4.8
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for
the following registers:
•
•
•
Write Control (WRCTRL) register
AHB Slave Bus Interrupt Flag Status and Clear (INTFLAGAHB) register
Peripheral Interrupt Flag Status and Clear n (INTFLAG A/B/C...) registers
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
13.5
13.5.1
Functional Description
Principle of Operation
The Peripheral Access Control module allows the user to set a write protection on peripheral modules and generate
an interrupt in case of a peripheral access violation. The peripheral’s protection can be set, cleared or locked at the
user discretion. A set of Interrupt Flag and Status registers informs the user on the status of the violation in the
peripherals. In addition, slaves bus errors can be also reported in the cases where reserved area is accessed by the
application.
13.5.2
Basic Operation
13.5.2.1 Initialization, Enabling and Resetting
The PAC is always enabled after reset.
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SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
Only a hardware reset will reset the PAC module.
13.5.2.2 Operations
The PAC module allows the user to set, clear or lock the write protection status of all peripherals on all Peripheral
Bridges.
If a peripheral register violation occurs, the Peripheral Interrupt Flag n registers (INTFLAGn) are updated to inform
the user on the status of the violation in the peripherals connected to the Peripheral Bridge n (n = A,B,C ...). The
corresponding Peripheral Write Control Status n register (STATUSn) gives the state of the write protection for all
peripherals connected to the corresponding Peripheral Bridge n. Refer to the 13.5.2.3 Peripheral Access Errors for
details.
The PAC module also report the errors occurring at slave bus level when an access to reserved area is detected.
AHB Slave Bus Interrupt Flag register (INTFLAGAHB) informs the user on the status of the violation in the
corresponding slave. Refer to the 13.5.2.6 AHB Slave Bus Errors for details.
13.5.2.3 Peripheral Access Errors
The following events will generate a Peripheral Access Error:
•
•
•
Protected write: To avoid unexpected writes to a peripheral's registers, each peripheral can be write protected.
Only the registers denoted as “PAC Write-Protection” in the module’s data sheet can be protected. If a
peripheral is not write protected, write data accesses are performed normally. If a peripheral is write protected
and if a write access is attempted, data will not be written and peripheral returns an access error. The
corresponding interrupt flag bit in the INTFLAGn register will be set.
Illegal access: Access to an unimplemented register within the module.
Synchronized write error: For write-synchronized registers an error will be reported if the register is written while
a synchronization is ongoing.
When any of the INTFLAGn registers bit are set, an interrupt will be requested if the PAC interrupt enable bit is set.
References:
Register Synchronization
13.5.2.4 Write Access Protection Management
Peripheral access control can be enabled or disabled by writing to the WRCTRL register.
The data written to the WRCTRL register is composed of two fields; WRCTRL.PERID and WRCTRL.KEY. The
WRCTRL.PERID is an unique identifier corresponding to a peripheral. The WRCTRL.KEY is a key value that defines
the operation to be done on the control access bit. These operations can be “clear protection”, “set protection” and
“set and lock protection bit”.
The “clear protection” operation will remove the write access protection for the peripheral selected by
WRCTRL.PERID. Write accesses are allowed for the registers in this peripheral.
The “set protection” operation will set the write access protection for the peripheral selected by WRCTRL.PERID.
Write accesses are not allowed for the registers with write protection property in this peripheral.
The “set and lock protection” operation will set the write access protection for the peripheral selected by
WRCTRL.PERID and locks the access rights of the selected peripheral registers. The write access protection will
only be cleared by a hardware reset.
The peripheral access control status can be read from the corresponding STATUSn register.
13.5.2.5 Write Access Protection Management Errors
Only word-wise writes to the WRCTRL register will effectively change the access protection. Other type of accesses
will have no effect and will cause a PAC write access error. This error is reported in the INTFLAGn.PAC bit
corresponding to the PAC module.
PAC also offers an additional safety feature for correct program execution with an interrupt generated on double write
clear protection or double write set protection. If a peripheral is write protected and a subsequent set protection
operation is detected then the PAC returns an error, and similarly for a double clear protection operation.
In addition, an error is generated when writing a “set and lock” protection to a write-protected peripheral or when a
write access is done to a locked set protection. This can be used to ensure that the application follows the intended
program flow by always following a write protect with an unprotect and conversely. However in applications where a
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
write protected peripheral is used in several contexts, e.g. interrupt, care should be taken so that either the interrupt
can not happen while the main application or other interrupt levels manipulates the write protection status or when
the interrupt handler needs to unprotect the peripheral based on the current protection status by reading the STATUS
register.
The errors generated while accessing the PAC module registers (eg. key error, double protect error...) will set the
INTFLAGn.PAC flag.
13.5.2.6 AHB Slave Bus Errors
The PAC module reports errors occurring at the AHB Slave bus level. These errors are generated when an access is
performed at an address where no slave (bridge or peripheral) is mapped . These errors are reported in the
corresponding bits of the INTFLAGAHB register.
13.5.2.7 Generating Events
The PAC module can also generate an event when any of the Interrupt Flag registers bit are set. To enable the PAC
event generation, the control bit EVCTRL.ERREO must be set a '1'.
13.5.3
DMA Operation
Not applicable.
13.5.4
Interrupts
The PAC has the following interrupt source:
•
Error (ERR): Indicates that a peripheral access violation occurred in one of the peripherals controlled by the PAC
module, or a bridge error occurred in one of the bridges reported by the PAC
– This interrupt is a synchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAGAHB and INTFLAGn) registers is set when the interrupt condition occurs. Each interrupt can be individually
enabled by writing a '1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by
writing a '1' to the corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is
generated when the interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains
active until the interrupt flag is cleared, the interrupt is disabled, or the PAC is reset. All interrupt requests from the
peripheral are ORed together on system level to generate one combined interrupt request to the NVIC. The user
must read the INTFLAGAHB and INTFLAGn registers to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated.
References:
20.6.3.3 Sleep Mode Controller
Nested Vector Interrupt Controller
13.5.5
Events
The PAC can generate the following output event:
• Error (ERR): Generated when one of the interrupt flag registers bits is set
Writing a '1' to an Event Output bit in the Event Control Register (EVCTRL.ERREO) enables the corresponding
output event. Writing a '0' to this bit disables the corresponding output event.
References:
30. EVSYS – Event System
13.5.6
Sleep Mode Operation
In Sleep mode, the PAC is kept enabled if an available bus master (CPU, DMA) is running. The PAC will continue to
catch access errors from the module and generate interrupts or events.
13.5.7
Synchronization
Not applicable.
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SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.6
Register Summary
Offset
Name
0x00
WRCTRL
0x04
0x05
...
0x07
0x08
0x09
0x0A
...
0x0F
EVCTRL
Bit Pos.
7:0
15:8
23:16
31:24
7:0
PERID[7:0]
PERID[15:8]
KEY[7:0]
ERREO
Reserved
INTENCLR
INTENSET
7:0
7:0
ERR
ERR
Reserved
7:0
15:8
0x10
INTFLAGAHB
23:16
H2LBRIDGES
LPRAMDMAC
LPRAMPICO
P
LPRAMHS
WDT
GCLK
SUPC
HPB1
HSRAMDSU HSRAMCM0P
HPB4
HPB3
HPB2
HPB0
OSCCTRL
RSTC
HSRAMLP
L2HBRIDGES
MCLK
PM
PORT
EIC
RTC
31:24
7:0
0x14
0x18
0x1C
0x20
INTFLAGA
INTFLAGB
INTFLAGC
INTFLAGD
0x24
INTFLAGE
0x28
...
0x33
Reserved
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
0x34
0x38
STATUSA
STATUSB
OSC32KCTR
L
DSUSTANDB
Y
FLASH
HMATRIXHS
MTB
NVMCTRL
DSU
USB
TCC2
TCC1
TRNG
TCC0
AES
SERCOM4
DAC
SERCOM3
TC3
SERCOM2
TC2
SERCOM1
TC1
SERCOM0
TC0
CCL
OPAMP
PTC
AC
ADC
TC4
SERCOM5
EVSYS
HMATRIXLP
DMAC
PAC
RSTC
MCLK
PM
PORT
EIC
RTC
NVMCTRL
DSU
USB
WDT
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2020 Microchip Technology Inc.
GCLK
SUPC
OSC32KCTR
L
DSUSTANDB
Y
HMATRIXHS
OSCCTRL
MTB
DS60001477C-page 59
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
...........continued
Offset
Name
0x3C
STATUSC
0x40
STATUSD
0x44
STATUSE
13.7
Bit Pos.
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
TCC2
TCC1
TRNG
TCC0
AES
SERCOM4
DAC
SERCOM3
TC3
SERCOM2
TC2
SERCOM1
TC1
SERCOM0
TC0
CCL
OPAMP
PTC
AC
ADC
TC4
SERCOM5
EVSYS
HMATRIXLP
DMAC
PAC
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC writeprotection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to the related links.
© 2020 Microchip Technology Inc.
DS60001477C-page 60
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.1
Write Control
Name:
Offset:
Reset:
Property:
Bit
WRCTRL
0x00
0x00000000
–
31
30
29
28
23
22
21
20
27
26
25
24
19
18
17
16
RW
0
RW
0
RW
0
RW
0
11
10
9
8
RW
0
RW
0
RW
0
RW
0
3
2
1
0
RW
0
RW
0
RW
0
RW
0
Access
Reset
Bit
KEY[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bit
15
14
13
12
PERID[15:8]
Access
Reset
Bit
RW
0
RW
0
RW
0
RW
0
7
6
5
4
PERID[7:0]
Access
Reset
RW
0
RW
0
RW
0
RW
0
Bits 23:16 – KEY[7:0] Peripheral Access Control Key
These bits define the peripheral access control key:
Value
Name
Description
0x0
OFF
No action
0x1
CLEAR
Clear the peripheral write control
0x2
SET
Set the peripheral write control
0x3
LOCK
Set and lock the peripheral write control until the next hardware reset
Bits 15:0 – PERID[15:0] Peripheral Identifier
The PERID represents the peripheral whose control is changed using the WRCTRL.KEY. The Peripheral Identifier is
calculated following formula:
����� = 32* BridgeNumber + N
Where BridgeNumber represents the Peripheral Bridge Number (0 for Peripheral Bridge A, 1 for Peripheral Bridge B,
etc). N represents the peripheral index from the respective Bridge Number:
Table 13-2. PERID Values
Periph. Bridge Name
BridgeNumber
PERID Values
A
B
C
D
E
0
1
2
3
4
0+N
32+N
64+N
96+N
128+N
© 2020 Microchip Technology Inc.
DS60001477C-page 61
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.2
Event Control
Name:
Offset:
Reset:
Property:
Bit
7
EVCTRL
0x04
0x00
-
6
Access
Reset
5
4
3
2
1
0
ERREO
R/W
0
Bit 0 – ERREO Peripheral Access Error Event Output
This bit indicates if the Peripheral Access Error Event Output is enabled or disabled. When enabled, an event will be
generated when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:
Value
Description
0
Peripheral Access Error Event Output is disabled.
1
Peripheral Access Error Event Output is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 62
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.3
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x08
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENSET).
Bit
7
6
Access
Reset
5
4
3
2
1
0
ERR
R/W
0
Bit 0 – ERR Peripheral Access Error Interrupt Disable
This bit indicates that the Peripheral Access Error Interrupt is disabled and an interrupt request will be generated
when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Peripheral Access Error interrupt Enable bit and disables the corresponding
interrupt request.
Value
Description
0
Peripheral Access Error interrupt is disabled.
1
Peripheral Access Error interrupt is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 63
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.4
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x09
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set register (INTENCLR).
Bit
7
6
Access
Reset
5
4
3
2
1
0
ERR
R/W
0
Bit 0 – ERR Peripheral Access Error Interrupt Enable
This bit indicates that the Peripheral Access Error Interrupt is enabled and an interrupt request will be generated
when one of the interrupt flag registers bits (INTFLAGAHB, INTFLAGn) is set:
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Peripheral Access Error interrupt Enable bit and enables the corresponding interrupt
request.
Value
Description
0
Peripheral Access Error interrupt is disabled.
1
Peripheral Access Error interrupt is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 64
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.5
AHB Slave Bus Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
INTFLAGAHB
0x10
0x000000
–
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit
31
30
29
28
27
26
25
HSRAMLP
R/W
0
24
L2HBRIDGES
R/W
0
21
LPRAMHS
R/W
0
20
19
HPB4
R/W
0
18
HPB3
R/W
0
17
HPB2
R/W
0
16
HPB0
R/W
0
Access
Reset
Bit
23
22
LPRAMDMAC LPRAMPICOP
Access
R/W
R/W
Reset
0
0
Bit
15
14
13
12
11
10
9
8
7
6
5
4
H2LBRIDGES
R/W
0
3
HPB1
R/W
0
2
HSRAMDSU
R/W
0
1
HSRAMCM0P
R/W
0
0
FLASH
R/W
0
Access
Reset
Bit
Access
Reset
Bit 25 – HSRAMLP Interrupt Flag for SLAVE HSRAMLP
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 24 – L2HBRIDGES Interrupt Flag for SLAVE L2HBRIDGES
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 23 – LPRAMDMAC Interrupt Flag for SLAVE LPRAMDMAC
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 22 – LPRAMPICOP Interrupt Flag for SLAVE LPRAMPICOP
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 21 – LPRAMHS Interrupt Flag for SLAVE LPRAMHS
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
© 2020 Microchip Technology Inc.
DS60001477C-page 65
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
Bit 19 – HPB4 Interrupt Flag for SLAVE HPB4
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 18 – HPB3 Interrupt Flag for SLAVE HPB3
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 17 – HPB2 Interrupt Flag for SLAVE HPB2
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 16 – HPB0 Interrupt Flag for SLAVE HPB0
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 4 – H2LBRIDGES Interrupt Flag for SLAVE H2LBRIDGES
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 3 – HPB1 Interrupt Flag for SLAVE HPB1
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 2 – HSRAMDSU Interrupt Flag for SLAVE HSRAMDSU
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 1 – HSRAMCM0P Interrupt Flag for SLAVE HSRAMCM0P
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
Bit 0 – FLASH Interrupt Flag for SLAVE FLASH
This flag is cleared by writing a '1' to the flag. This flag is set when an access error is detected by the SLAVE n, and
will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the corresponding INTFLAGAHB interrupt flag.
© 2020 Microchip Technology Inc.
DS60001477C-page 66
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.6
Peripheral Interrupt Flag Status and Clear A
Name:
Offset:
Reset:
Property:
INTFLAGA
0x14
0x000000
–
This flag is cleared by writing a '1' to the flag.
This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective
INTFLAGA bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding INTFLAGA interrupt flag.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
DSUSTANDBY
R/W
0
11
10
PORT
R/W
0
9
EIC
R/W
0
8
RTC
R/W
0
7
WDT
R/W
0
6
GCLK
R/W
0
5
SUPC
R/W
0
4
OSC32KCTRL
R/W
0
3
OSCCTRL
R/W
0
2
RSTC
R/W
0
1
MCLK
R/W
0
0
PM
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 12 – DSUSTANDBY Interrupt Flag for DSUSTANDBY
Bit 10 – PORT Interrupt Flag for PORT
Bit 9 – EIC Interrupt Flag for EIC
Bit 8 – RTC Interrupt Flag for RTC
Bit 7 – WDT Interrupt Flag for WDT
Bit 6 – GCLK Interrupt Flag for GCLK
Bit 5 – SUPC Interrupt Flag for SUPC
Bit 4 – OSC32KCTRL Interrupt Flag for OSC32KCTRL
Bit 3 – OSCCTRL Interrupt Flag for OSCCTRL
Bit 2 – RSTC Interrupt Flag for RSTC
Bit 1 – MCLK Interrupt Flag for MCLK
© 2020 Microchip Technology Inc.
DS60001477C-page 67
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
Bit 0 – PM Interrupt Flag for PM
© 2020 Microchip Technology Inc.
DS60001477C-page 68
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.7
Peripheral Interrupt Flag Status and Clear B
Name:
Offset:
Reset:
Property:
INTFLAGB
0x18
0x000000
–
This flag is cleared by writing a '1' to the flag.
This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective
INTFLAGB bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding INTFLAGB interrupt flag.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
HMATRIXHS
R/W
0
3
MTB
R/W
0
2
NVMCTRL
R/W
0
1
DSU
R/W
0
0
USB
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – HMATRIXHS Interrupt Flag for HMATRIXHS
Bit 3 – MTB Interrupt Flag for MTB
Bit 2 – NVMCTRL Interrupt Flag for NVMCTRL
Bit 1 – DSU Interrupt Flag for DSU
Bit 0 – USB Interrupt Flag for USB
© 2020 Microchip Technology Inc.
DS60001477C-page 69
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.8
Peripheral Interrupt Flag Status and Clear C
Name:
Offset:
Reset:
Property:
INTFLAGC
0x1C
0x000000
–
This flag is cleared by writing a one to the flag.
This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective
INTFLAGC bit, and will generate an interrupt request if INTENCLR/SET.ERR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding INTFLAGC interrupt flag.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
TRNG
R/W
0
13
AES
R/W
0
12
DAC
R/W
0
11
TC3
R/W
0
10
TC2
R/W
0
9
TC1
R/W
0
8
TC0
R/W
0
7
TCC2
R/W
0
6
TCC1
R/W
0
5
TCC0
R/W
0
4
SERCOM4
R/W
0
3
SERCOM3
R/W
0
2
SERCOM2
R/W
0
1
SERCOM1
R/W
0
0
SERCOM0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 14 – TRNG Interrupt Flag for PTC
Bit 13 – AES Interrupt Flag for AC
Bit 12 – DAC Interrupt Flag for ADC
Bits 8, 9, 10, 11 – TC Interrupt Flag for TCn [n = 3..0]
Bits 5, 6, 7 – TCC Interrupt Flag for TCCn [n = 2..0]
Bits 0, 1, 2, 3, 4 – SERCOM Interrupt Flag for SERCOMn [n = 5..0]
© 2020 Microchip Technology Inc.
DS60001477C-page 70
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.9
Peripheral Interrupt Flag Status and Clear D
Name:
Offset:
Reset:
Property:
INTFLAGD
0x20
0x000000
–
This flag is cleared by writing a '1' to the flag.
This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective
INTFLAGD bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding INTFLAGD interrupt flag.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
CCL
R/W
0
6
OPAMP
R/W
0
5
PTC
R/W
0
4
AC
R/W
0
3
ADC
R/W
0
2
TC4
R/W
0
1
SERCOM5
R/W
0
0
EVSYS
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 7 – CCL Interrupt Flag for CCL
Bit 6 – OPAMP Interrupt Flag for OPAMP
Bit 5 – PTC Interrupt Flag for PTC
Bit 4 – AC Interrupt Flag for AC
Bit 3 – ADC Interrupt Flag for ADC
Bit 2 – TC4 Interrupt Flag for TC4
Bit 1 – SERCOM5 Interrupt Flag for SERCOM5
Bit 0 – EVSYS Interrupt Flag for EVSYS
© 2020 Microchip Technology Inc.
DS60001477C-page 71
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.10 Peripheral Interrupt Flag Status and Clear E
Name:
Offset:
Reset:
Property:
INTFLAGE
0x24
0x000000
–
This flag is cleared by writing a '1' to the flag.
This flag is set when a Peripheral Access Error occurs while accessing the peripheral associated with the respective
INTFLAGE bit, and will generate an interrupt request if INTENCLR/SET.ERR is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding INTFLAGE interrupt flag.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
HMATRIXLP
R/W
0
1
DMAC
R/W
0
0
PAC
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 2 – HMATRIXLP Interrupt Flag for HMATRIXLP
Bit 1 – DMAC Interrupt Flag for DMAC
Bit 0 – PAC Interrupt Flag for PAC
© 2020 Microchip Technology Inc.
DS60001477C-page 72
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.11 Peripheral Write Protection Status A
Name:
Offset:
Reset:
Property:
STATUSA
0x34
0x000000
–
Writing to this register has no effect.
Reading STATUS register returns the peripheral write protection status:
Bit
Value
Description
0
Peripheral is not write protected.
1
Peripheral is write protected.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
DSUSTANDBY
R
0
11
10
PORT
R
0
9
EIC
R
0
8
RTC
R
0
7
WDT
R
0
6
GCLK
R
0
5
SUPC
R
0
4
OSC32KCTRL
R
0
3
OSCCTRL
R
0
2
RSTC
R
0
1
MCLK
R
0
0
PM
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 12 – DSUSTANDBY Peripheral DSUSTANDBY Write Protection Status
Bit 10 – PORT Peripheral PORT Write Protection Status
Bit 9 – EIC Peripheral EIC Write Protection Status
Bit 8 – RTC Peripheral RTC Write Protection Status
Bit 7 – WDT Peripheral WDT Write Protection Status
Bit 6 – GCLK Peripheral GCLK Write Protection Status
Bit 5 – SUPC Peripheral SUPC Write Protection Status
Bit 4 – OSC32KCTRL Peripheral OSC32KCTRL Write Protection Status
Bit 3 – OSCCTRL Peripheral OSCCTRL Write Protection Status
Bit 2 – RSTC Peripheral RSTC Write Protection Status
Bit 1 – MCLK Peripheral MCLK Write Protection Status
© 2020 Microchip Technology Inc.
DS60001477C-page 73
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
Bit 0 – PM Peripheral ATW Write Protection Status
© 2020 Microchip Technology Inc.
DS60001477C-page 74
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.12 Peripheral Write Protection Status B
Name:
Offset:
Reset:
Property:
STATUSB
0x38
0x000000
–
Writing to this register has no effect.
Reading STATUS register returns the peripheral write protection status:
Bit
Value
Description
0
Peripheral is not write protected.
1
Peripheral is write protected.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
HMATRIXHS
R
0
3
MTB
R
0
2
NVMCTRL
R
0
1
DSU
R
0
0
USB
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 4 – HMATRIXHS Peripheral HMATRIXHS Write Protection Status
Bit 3 – MTB Peripheral MTB Write Protection Status
Bit 2 – NVMCTRL Peripheral NVMCTRLWrite Protection Status
Bit 1 – DSU Peripheral DSU Write Protection Status
Bit 0 – USB Peripheral USB Write Protection Status
© 2020 Microchip Technology Inc.
DS60001477C-page 75
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.13 Peripheral Write Protection Status C
Name:
Offset:
Reset:
Property:
STATUSC
0x3C
0x00000000
–
Writing to this register has no effect.
Reading STATUS register returns the peripheral write protection status:
Bit
Value
Description
0
Peripheral is not write protected.
1
Peripheral is write protected.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
TRNG
R
0
13
AES
R
0
12
DAC
R
0
11
TC3
R
0
10
TC2
R
0
9
TC1
R
0
8
TC0
R
0
7
TCC2
R
0
6
TCC1
R
0
5
TCC0
R
0
4
SERCOM4
R
0
3
SERCOM3
R
0
2
SERCOM2
R
0
1
SERCOM1
R
0
0
SERCOM0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 14 – TRNG Peripheral TRNG Write Protection Status
Bit 13 – AES Peripheral AES Write Protection Status
Bit 12 – DAC Peripheral DAC Write Protection Status
Bits 8, 9, 10, 11 – TCn Peripheral TCn Write Protection Status [n = 3..0]
Bits 5, 6, 7 – TCCn Peripheral TCC Write Protection Status
Bits 0, 1, 2, 3, 4 – SERCOMn Peripheral SERCOMn Write Protection Status [n = 4..0]
© 2020 Microchip Technology Inc.
DS60001477C-page 76
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.14 Peripheral Write Protection Status D
Name:
Offset:
Reset:
Property:
STATUSD
0x40
0x000000
–
Writing to this register has no effect.
Reading STATUS register returns peripheral write protection status:
Bit
Value
Description
0
Peripheral is not write protected.
1
Peripheral is write protected.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
CCL
R
0
6
OPAMP
R
0
5
PTC
R
0
4
AC
R
0
3
ADC
R
0
2
TC4
R
0
1
SERCOM5
R
0
0
EVSYS
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 7 – CCL Peripheral CCL Write Protection Status
Bit 6 – OPAMP Peripheral OPAMP Write Protection Status
Bit 5 – PTC Peripheral PTC Write Protection Status
Bit 4 – AC Peripheral AC Write Protection Status
Bit 3 – ADC Peripheral ADC Write Protection Status
Bit 2 – TC4 Peripheral TC4 Write Protection Status
Bit 1 – SERCOM5 Peripheral SERCOM5 Write Protection Status
Bit 0 – EVSYS Peripheral EVSYS Write Protection Status
© 2020 Microchip Technology Inc.
DS60001477C-page 77
SAM L21 Family Data Sheet
PAC - Peripheral Access Controller
13.7.15 Peripheral Write Protection Status E
Name:
Offset:
Reset:
Property:
STATUSE
0x44
0x000000
–
Writing to this register has no effect.
Reading STATUS register returns peripheral write protection status:
Bit
Value
Description
0
Peripheral is not write protected.
1
Peripheral is write protected.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
HMATRIXLP
R
0
1
DMAC
R
0
0
PAC
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 2 – HMATRIXLP Peripheral HMATRIXLP Write Protection Status
Bit 1 – DMAC Peripheral DMAC Write Protection Status
Bit 0 – PAC Peripheral PAC Write Protection Status
© 2020 Microchip Technology Inc.
DS60001477C-page 78
SAM L21 Family Data Sheet
Peripherals Configuration Summary
14.
Peripherals Configuration Summary
Table 14-1. Peripherals Configuration Summary
Peripheral
name
Base address
IRQ
line
AHB clock
APB clock
Clock
Domain
Generic
Clock
PAC
Events
DMA
Power
domain
Index
Enabled
at Reset
Index
Enabled
at Reset
Name
Index
Index
Prot at
Reset
User
Generator
Index
Sleep
Walking
Name
AHB-APB Bridge
A
0x40000000
—
0
Y
—
—
Low Power
—
—
—
—
—
—
N/A
PD1
PM
0x40000000
0
—
—
0
Y
Backup
—
0
N
—
—
—
N/A
PDBACKUP
MCLK
0x40000400
0
—
—
1
Y
Low Power
—
1
N
—
—
—
Y
PD0
RSTC
0x40000800
—
—
—
2
Y
Backup
—
2
N
—
—
—
N/A
PDBACKUP
OSCCTRL
0x40000C00
0
—
—
3
Y
Low Power
0: DFLL48M
reference
3
N
—
—
—
Y
PD0
1: FDPLL96M
clk source
2: FDPLL96M
32kHz
OSC32KCTRL
0x40001000
0
—
—
4
Y
Backup
—
4
N
—
—
—
—
PDBACKUP
SUPC
0x40001400
0
—
—
5
Y
Backup
—
5
N
—
—
—
N/A
PDBACKUP
GCLK
0x40001800
—
—
—
6
Y
Low Power
—
6
N
—
—
—
N/A
PD0
WDT
0x40001C00
1
—
—
7
Y
Low Power
—
7
N
—
—
—
Y
PDTOP
RTC
0x40002000
2
—
—
8
Y
Backup
—
8
N
—
1: CMP0/
ALARM0
—
Y
PDBACKUP
2: CMP1
3: OVF
4-11: PER0-7
EIC
0x40002400
3,
NMI
—
—
9
Y
Low Power
3
9
N
—
12-27:
EXTINT0-15
—
Y
PDTOP
PORT
0x40002800
—
—
—
10
Y
Low Power
—
10
N
0-3 : EV0-3
—
—
Y
PDTOP
AHB-APB Bridge
B
0x41000000
—
1
Y
—
—
CPU
—
—
—
—
—
—
N/A
PD2
USB
0x41000000
6
12
Y
0
Y
CPU
4
0
N
—
—
—
Y
PD2
DSU
0x41002000
—
5
Y
1
Y
CPU
—
1
Y
—
—
—
N/A
PD2
NVMCTRL
0x41004000
4
8
Y
2
Y
CPU
—
2
N
—
—
—
Y
PD2
MTB
0x41006000
—
—
—
—
—
CPU
—
—
—
43,44: Start,
Stop
—
—
N/A
PD2
AHB-APB Bridge
C
0x42000000
—
2
Y
—
—
Low Power
—
—
—
—
—
—
N/A
PD1
SERCOM0
0x42000000
8
—
—
0
Y
Low Power
18: CORE
0
N
—
—
1: RX
Y
PD1
Y
PD1
Y
PD1
Y
PD1
Y
PD1
17: SLOW
SERCOM1
0x42000400
9
—
—
1
Y
Low Power
19: CORE
2: TX
1
N
—
—
17: SLOW
SERCOM2
0x42000800
10
—
—
2
Y
Low Power
20: CORE
4: TX
2
N
—
—
17: SLOW
SERCOM3
0x42000C00
11
—
—
3
Y
Low Power
21: CORE
0x42001000
12
—
—
4
Y
Low Power
22: CORE
17: SLOW
© 2020 Microchip Technology Inc.
5: RX
6: TX
3
N
—
—
17: SLOW
SERCOM4
3: RX
7: RX
8: TX
4
N
—
—
9: RX
10: TX
DS60001477C-page 79
SAM L21 Family Data Sheet
Peripherals Configuration Summary
...........continued
Peripheral
name
Base address
TCC0
0x42001400
IRQ
line
14
AHB clock
APB clock
Clock
Domain
Generic
Clock
PAC
Events
Index
Enabled
at Reset
Index
Enabled
at Reset
Name
Index
Index
Prot at
Reset
—
—
5
Y
Low Power
25
5
N
DMA
Power
domain
User
Generator
Index
Sleep
Walking
Name
12-13: EV0-1
36: OVF
11: OVF
Y
PD1
14-17:
MC0-3
37: TRG
12-15: MC0-3
Y
PD1
Y
PD1
Y
PD1
Y
PD1
Y
PD1
Y
PD1
38: CNT
39-42: MC0-3
TCC1
0x42001800
15
—
—
6
Y
Low Power
25
6
N
18-19: EV0-1
43: OVF
16: OVF
20-21:
MC0-1
44: TRG
17-18: MC0-1
45: CNT
46-47: MC0-1
TCC2
0x42001C00
16
—
—
7
Y
Low Power
26
7
N
22-23: EV0-1
48: OVF
19: OVF
24-25:
MC0-1
49: TRG
20-21: MC0-1
50: CNT
51-52: MC0-1
TC0
0x42002000
TC1
0x42002400
TC2
0x42002800
TC3
0x42002C00
17
18
19
20
—
—
—
—
—
—
—
—
8
9
10
11
Y
Y
Y
Y
Low Power
Low Power
Low Power
Low Power
27
27
28
28
8
9
10
11
N
N
N
N
26: EVU
27: EVU
28: EVU
29: EVU
53: OVF
22: OVF
54-55: MC0-1
23-24: MC0-1
56: OVF
25: OVF
57-58: MC0-1
26-27: MC0-1
59: OVF
28: OVF
60-61: MC0-1
29-30: MC0-1
62: OVF
31: OVF
63-64: MC0-1
32-33: MC0-1
DAC
0x42003000
24
—
—
12
Y
Low Power
32
12
N
35-36:
START0-1
73-74:
EMPTY0-1
38-39:
EMPTY0-1
Y
PD1
AES
0x42003400
26
—
—
13
Y
Low Power
—
13
N
—
—
44 : WR
Y
PD1
45 : RD
TRNG
0x42003800
27
—
—
14
Y
Low Power
—
14
N
—
77 : READY
—
Y
PD1
AHB-APB Bridge
D
0x43000000
—
3
Y
—
—
Low Power
—
—
—
—
—
—
N/A
PD1
EVSYS
0x43000000
7
—
—
0
Y
Low Power
5-16: one per
CHANNEL
0
N
—
—
—
Y
PD0
SERCOM5
0x43000400
13
—
—
1
Y
Low Power
24: CORE
1
N
—
—
—
Y
PD0
2
N
—
65: OVF
34: OVF
Y
PD0
66-67: MC0-1
35-36: MC0-1
37: RESRDY
Y
PD0
—
Y
PD0
—
—
PD0
23: SLOW
TC4
0x43000800
ADC
0x43000C00
21
22
—
—
—
—
2
3
Y
Y
Low Power
Low Power
29
30
3
N
31: START
68: RESRDY
32: SYNC
69: WINMON
70-71:
COMP0-1
AC
0x43001000
23
—
—
4
Y
Low Power
31
4
N
33-34:
SOC0-1
PTC
0x43001400
25
—
—
5
Y
Low Power
33
5
N
37: STCONV
72: WIN0
75: EOC
76: WCOMP
OPAMP
0x43001800
—
—
—
6
Y
Low Power
—
6
N
—
—
—
Y
PD0
CCL
0x43001C00
—
—
—
7
Y
Low Power
34
7
N
38 : LUTIN0
78 : LUTOUT0
—
Y
PD0
39 : LUTIN1
79 : LUTOUT1
40: LUTIN2
80: LUTOUT2
41: LUTIN3
81: LUTOUT3
AHB-APB Bridge
E
0x44000000
—
4
Y
—
—
Low Power
—
—
—
—
—
—
N/A
PD1
PAC
0x44000000
0
14
Y
0
Y
Low Power
—
0
—
—
82 : ACCERR
—
N/A
PD1
© 2020 Microchip Technology Inc.
DS60001477C-page 80
SAM L21 Family Data Sheet
Peripherals Configuration Summary
...........continued
Peripheral
name
DMAC
Base address
0x44000400
IRQ
line
—
AHB clock
APB clock
Clock
Domain
Generic
Clock
PAC
Index
Enabled
at Reset
Index
Enabled
at Reset
Name
Index
Index
Prot at
Reset
User
Generator
Index
Sleep
Walking
Name
11
Y
—
—
Low Power
—
1
—
4-11: CH0-7
28-35: CH0-7
—
Y
PD1
© 2020 Microchip Technology Inc.
Events
DMA
Power
domain
DS60001477C-page 81
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.
DSU - Device Service Unit
15.1
Overview
The Device Service Unit (DSU) provides a means of detecting debugger probes. It enables the ARM Debug Access
Port (DAP) to have control over multiplexed debug pads and CPU reset. The DSU also provides system-level
services to debug adapters in an ARM debug system. It implements a CoreSight Debug ROM that provides device
identification as well as identification of other debug components within the system. Hence, it complies with the ARM
Peripheral Identification specification. The DSU also provides system services to applications that need memory
testing, as required for IEC60730 Class B compliance, for example. The DSU can be accessed simultaneously by a
debugger and the CPU, as it is connected on the High-Speed Bus Matrix. For security reasons, some of the DSU
features will be limited or unavailable when the device is protected by the NVMCTRL security bit.
References:
28. NVMCTRL – Non-Volatile Memory Controller
28.6.6 Security Bit
15.2
Features
•
•
•
•
•
•
•
•
15.3
CPU reset extension
Debugger probe detection (Cold- and Hot-Plugging)
Chip-Erase command and status
32-bit cyclic redundancy check (CRC32) of any memory accessible through the bus matrix
ARM® CoreSight™ compliant device identification
Two debug communications channels
Debug access port security filter
Onboard memory built-in self-test (MBIST)
Block Diagram
Figure 15-1. DSU Block Diagram
DSU
RESET
SWCLK
debugger_present
DEBUGGER PROBE
INTERFACE
cpu_reset_extension
CPU
DAP
AHB-AP
DAP SECURITY FILTER
NVMCTRL
DBG
CORESIGHT ROM
PORT
M
S
CRC-32
SWDIO
MBIST
M
HIGH-SPEED
BUS MATRIX
CHIP ERASE
© 2020 Microchip Technology Inc.
DS60001477C-page 82
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.4
Signal Description
The DSU uses three signals to function.
Signal Name
Type
Description
RESET
Digital Input
External reset
SWCLK
Digital Input
SW clock
SWDIO
Digital I/O
SW bidirectional data pin
References:
7. I/O Multiplexing and Considerations
15.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
15.5.1
IO Lines
The SWCLK pin is by default assigned to the DSU module to allow debugger probe detection and to stretch the CPU
reset phase. For more information, refer to 15.6.3 Debugger Probe Detection. The Hot-Plugging feature depends on
the PORT configuration. If the SWCLK pin function is changed in the PORT or if the PORT_MUX is disabled, the HotPlugging feature is disabled until a power-reset or an external reset.
15.5.2
Power Management
The DSU will continue to operate in any sleep mode where the selected source clock is running.
References:
20. PM – Power Manager
15.5.3
Clocks
The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Main Clock
Controller18. MCLK – Main Clock and 18.6.2.6 Peripheral Clock Masking.
The DSU bus clocks (CLK_DSU_APB and CLK_DSU_AHB) can be enabled and disabled by the Power Manager.
Refer to 20. PM – Power Manager for further information.
15.5.4
Interrupts
Not applicable.
15.5.5
Events
Not applicable.
15.5.6
Register Access Protection
Registers with write-access can be optionally write-protected by the 13. PAC - Peripheral Access Controller, except
for the following:
• Debug Communication Channel 0 register (DCC0)
• Debug Communication Channel 1 register (DCC1)
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply
for accesses through an external debugger.
15.5.7
Analog Connections
Not applicable.
© 2020 Microchip Technology Inc.
DS60001477C-page 83
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.6
15.6.1
Debug Operation
Principle of Operation
The DSU provides basic services to allow on-chip debug using the ARM Debug Access Port and the ARM processor
debug resources:
• CPU reset extension
• Debugger probe detection
For more details on the ARM debug components, refer to the ARM Debug Interface v5 Architecture Specification.
15.6.2
CPU Reset Extension
“CPU reset extension” refers to the extension of the reset phase of the CPU core after the external reset is released.
This ensures that the CPU is not executing code at startup while a debugger is connects to the system. The
debugger is detected on a RESET release event when SWCLK is low. At startup, SWCLK is internally pulled up to
avoid false detection of a debugger if the SWCLK pin is left unconnected. When the CPU is held in the reset
extension phase, the CPU Reset Extension bit of the Status A register (STATUSA.CRSTEXT) is set. To release the
CPU, write a '1' to STATUSA.CRSTEXT. STATUSA.CRSTEXT will then be set to '0'. Writing a '0' to
STATUSA.CRSTEXT has no effect. For security reasons, it is not possible to release the CPU reset extension when
the device is protected by the NVMCTRL security bit. Trying to do so sets the Protection Error bit (PERR) of the
Status A register (STATUSA.PERR).
Figure 15-2. Typical CPU Reset Extension Set and Clear Timing Diagram
SWCLK
RESET
DSU CRSTEXT
Clear
CPU reset
extension
CPU_STATE
reset
running
References:
28.6.6 Security Bit
28. NVMCTRL – Non-Volatile Memory Controller
15.6.3
Debugger Probe Detection
15.6.3.1 Cold Plugging
Cold-Plugging is the detection of a debugger when the system is in reset. Cold-Plugging is detected when the CPU
reset extension is requested, as described above.
15.6.3.2 Hot Plugging
Hot-Plugging is the detection of a debugger probe when the system is not in reset. Hot-Plugging is not possible under
reset because the detector is reset when POR or RESET are asserted. Hot-Plugging is active when a SWCLK falling
edge is detected. The SWCLK pad is multiplexed with other functions and the user must ensure that its default
function is assigned to the debug system. If the SWCLK function is changed, the Hot-Plugging feature is disabled
until a power-reset or external reset occurs. Availability of the Hot-Plugging feature can be read from the HotPlugging Enable bit of the Status B register (STATUSB.HPE).
© 2020 Microchip Technology Inc.
DS60001477C-page 84
SAM L21 Family Data Sheet
DSU - Device Service Unit
Figure 15-3. Hot-Plugging Detection Timing Diagram
SWCLK
RESET
CPU_STATE
reset
running
Hot-Plugging
The presence of a debugger probe is detected when either Hot-Plugging or Cold-Plugging is detected. Once
detected, the Debugger Present bit of the Status B register (STATUSB.DBGPRES) is set. For security reasons, HotPlugging is not available when the device is protected by the NVMCTRL security bit.
This detection requires that pads are correctly powered. Thus, at cold startup, this detection cannot be done until
POR is released. If the device is protected, Cold-Plugging is the only way to detect a debugger probe, and so the
external reset timing must be longer than the POR timing. If external reset is deasserted before POR release, the
user must retry the procedure above until it gets connected to the device.
References:
28. NVMCTRL – Non-Volatile Memory Controller
28.6.6 Security Bit
15.7
Chip Erase
Chip-Erase consists of removing all sensitive information stored in the chip and clearing the NVMCTRL security bit.
Therefore, all volatile memories and the Flash memory (including the EEPROM emulation area) will be erased. The
Flash auxiliary rows, including the user row, will not be erased.
When the device is protected, the debugger must first reset the device in order to be detected. This ensures that
internal registers are reset after the protected state is removed. The Chip-Erase operation is triggered by writing a '1'
to the Chip-Erase bit in the Control register (CTRL.CE). This command will be discarded if the DSU is protected by
the Peripheral Access Controller (PAC). Once issued, the module clears volatile memories prior to erasing the Flash
array. To ensure that the Chip-Erase operation is completed, check the Done bit of the Status A register
(STATUSA.DONE).
The Chip-Erase operation depends on clocks and power management features that can be altered by the CPU. For
that reason, it is recommended to issue a Chip- Erase after a Cold-Plugging procedure to ensure that the device is in
a known and safe state.
The recommended sequence is as follows:
1. Issue the Cold-Plugging procedure (refer to 15.6.3.1 Cold Plugging). The device then:
1.1.
Detects the debugger probe.
1.2.
Holds the CPU in reset.
2. Issue the Chip-Erase command by writing a '1' to CTRL.CE. The device then:
2.1.
Clears the system volatile memories.
2.2.
Erases the whole Flash array (including the EEPROM emulation area, not including auxiliary rows).
2.3.
Erases the lock row, removing the NVMCTRL security bit protection.
3. Check for completion by polling STATUSA.DONE (read as '1' when completed).
4. Reset the device to let the NVMCTRL update the fuses.
© 2020 Microchip Technology Inc.
DS60001477C-page 85
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.8
Programming
Programming the Flash or RAM memories is only possible when the device is not protected by the NVMCTRL
security bit. The programming procedure is as follows:
1. At power up, RESET is driven low by a debugger. The on-chip regulator holds the system in a POR state until
the input supply is above the POR threshold (refer to Powe-On Reset (POR) characteristics). The system
continues to be held in this static state until the internally regulated supplies have reached a safe operating
state.
2. The PM starts, clocks are switched to the slow clock (Core Clock, System Clock, Flash Clock and any Bus
Clocks that do not have clock gate control). Internal resets are maintained due to the external reset.
3. The debugger maintains a low level on SWCLK. RESET is released, resulting in a debugger Cold-Plugging
procedure.
4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock.
5. The CPU remains in Reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released.
6. A Chip-Erase is issued to ensure that the Flash is fully erased prior to programming.
7. Programming is available through the AHB-AP.
8. After the operation is completed, the chip can be restarted either by asserting RESET, toggling power, or
writing a '1' to the Status A register CPU Reset Phase Extension bit (STATUSA.CRSTEXT). Make sure that
the SWCLK pin is high when releasing RESET to prevent extending the CPU reset.
References:
46. Electrical Characteristics
NVMCTRL
Security Bit
15.9
Intellectual Property Protection
Intellectual property protection consists of restricting access to internal memories from external tools when the device
is protected, and this is accomplished by setting the NVMCTRL security bit. This protected state can be removed by
issuing a Chip-Erase (refer to 15.7 Chip Erase). When the device is protected, read/write accesses using the AHBAP are limited to the DSU address range and DSU commands are restricted. When issuing a Chip-Erase, sensitive
information is erased from volatile memory and Flash.
The DSU implements a security filter that monitors the AHB transactions inside the DAP. If the device is protected,
then AHB-AP read/write accesses outside the DSU external address range are discarded, causing an error response
that sets the ARM AHB-AP sticky error bits (refer to the ARM Debug Interface v5 Architecture Specification on http://
www.arm.com).
The DSU is intended to be accessed either:
• Internally from the CPU, without any limitation, even when the device is protected
• Externally from a debug adapter, with some restrictions when the device is protected
For security reasons, DSU features have limitations when used from a debug adapter. To differentiate external
accesses from internal ones, the first 0x100 bytes of the DSU register map has been mirrored at offset 0x100:
• The first 0x100 bytes form the internal address range
• The next 0x100 bytes form the external address range
When the device is protected, the DAP can only issue MEM-AP accesses in the DSU range 0x0100-0x2000.
The DSU operating registers are located in the 0x0000-0x00FF area and remapped in 0x0100-0x01FF to differentiate
accesses coming from a debugger and the CPU. If the device is protected and an access is issued in the region
0x0100-0x01FF, it is subject to security restrictions. For more information, refer to the Table 15-1.
© 2020 Microchip Technology Inc.
DS60001477C-page 86
SAM L21 Family Data Sheet
DSU - Device Service Unit
Figure 15-4. APB Memory Mapping
0x0000
DSU operating
registers
Internal address range
(cannot be accessed from debug tools when the device is
protected by the NVMCTRL security bit)
0x00FC
0x0100
Mirrored
DSU operating
registers
0x01FD
Empty
External address range
(can be accessed from debug tools with some restrictions)
0x1000
DSU CoreSight
ROM
0x1FFC
Some features not activated by APB transactions are not available when the device is protected:
Table 15-1. Feature Availability Under Protection
Features
Availability when the device is protected
CPU Reset Extension
Yes
Clear CPU Reset Extension
No
Debugger Cold-Plugging
Yes
Debugger Hot-Plugging
No
References:
28. NVMCTRL – Non-Volatile Memory Controller
Security Bit
15.10
Device Identification
Device identification relies on the ARM CoreSight component identification scheme, which allows the chip to be
identified as an Atmel device implementing a DSU. The DSU contains identification registers to differentiate the
device.
15.10.1 CoreSight Identification
A system-level ARM CoreSight ROM table is present in the device to identify the vendor and the chip identification
method. Its address is provided in the MEM-AP BASE register inside the ARM Debug Access Port. The CoreSight
ROM implements a 64-bit conceptual ID composed as follows from the PID0 to PID7 CoreSight ROM Table registers:
© 2020 Microchip Technology Inc.
DS60001477C-page 87
SAM L21 Family Data Sheet
DSU - Device Service Unit
Figure 15-5. Conceptual 64-bit Peripheral ID
Table 15-2. Conceptual 64-Bit Peripheral ID Bit Descriptions
Field
Size Description
Location
JEP-106 CC code 4
Atmel continuation code: 0x0
PID4
JEP-106 ID code
7
Atmel device ID: 0x1F
PID1+PID2
4KB count
4
Indicates that the CoreSight component is a ROM: 0x0
PID4
RevAnd
4
Not used; read as 0
PID3
CUSMOD
4
Not used; read as 0
PID3
PARTNUM
12
Contains 0xCD0 to indicate that DSU is present
PID0+PID1
REVISION
4
DSU revision (starts at 0x0 and increments by 1 at both major and minor
PID3
revisions). Identifies DSU identification method variants. If 0x0, this indicates
that device identification can be completed by reading the Device
Identification register (DID)
For more information, refer to the ARM Debug Interface Version 5 Architecture Specification.
15.10.2 Chip Identification Method
The DSU DID register identifies the device by implementing the following information:
•
•
•
•
15.11
Processor identification
Product family identification
Product series identification
Device select
Functional Description
15.11.1 Principle of Operation
The DSU provides memory services such as CRC32 or MBIST that require almost the same interface. Hence, the
Address, Length and Data registers (ADDR, LENGTH, DATA) are shared. These shared registers must be configured
first; then a command can be issued by writing the Control register. When a command is ongoing, other commands
are discarded until the current operation is completed. Hence, the user must wait for the STATUSA.DONE bit to be
set prior to issuing another one.
15.11.2 Basic Operation
15.11.2.1 Initialization
The module is enabled by enabling its clocks. For more details, refer to 15.5.3 Clocks. The DSU registers can be
PAC write-protected.
References:
© 2020 Microchip Technology Inc.
DS60001477C-page 88
SAM L21 Family Data Sheet
DSU - Device Service Unit
13. PAC - Peripheral Access Controller
15.11.2.2 Operation From a Debug Adapter
Debug adapters should access the DSU registers in the external address range 0x100 – 0x2000. If the device is
protected by the NVMCTRL security bit, accessing the first 0x100 bytes causes the system to return an error. Refer
to 15.9 Intellectual Property Protection.
References:
28. NVMCTRL – Non-Volatile Memory Controller
Security Bit
15.11.2.3 Operation From the CPU
There are no restrictions when accessing DSU registers from the CPU. However, the user should access DSU
registers in the internal address range (0x0 – 0x100) to avoid external security restrictions. Refer to 15.9 Intellectual
Property Protection.
15.11.3 32-bit Cyclic Redundancy Check CRC32
The DSU unit provides support for calculating a cyclic redundancy check (CRC32) value for a memory area
(including Flash and AHB RAM).
When the CRC32 command is issued from:
• The internal range, the CRC32 can be operated at any memory location
• The external range, the CRC32 operation is restricted; DATA, ADDR, and LENGTH values are forced (see
below)
Table 15-3. AMOD Bit Descriptions when Operating CRC32
AMOD[1:0] Short name External range restrictions
0
ARRAY
CRC32 is restricted to the full Flash array area (EEPROM emulation area not included)
DATA forced to 0xFFFFFFFF before calculation (no seed)
1
EEPROM
CRC32 of the whole EEPROM emulation area DATA forced to 0xFFFFFFFF before
calculation (no seed)
2-3
Reserved
The algorithm employed is the industry standard CRC32 algorithm using the generator polynomial 0xEDB88320
(reversed representation).
15.11.3.1 Starting CRC32 Calculation
CRC32 calculation for a memory range is started after writing the start address into the Address register (ADDR) and
the size of the memory range into the Length register (LENGTH). Both must be word-aligned.
The initial value used for the CRC32 calculation must be written to the Data register (DATA). This value will usually be
0xFFFFFFFF, but can be, for example, the result of a previous CRC32 calculation if generating a common CRC32 of
separate memory blocks.
Once completed, the calculated CRC32 value can be read out of the Data register. The read value must be
complemented to match standard CRC32 implementations or kept non-inverted if used as starting point for
subsequent CRC32 calculations.
If the device is in protected state by the NVMCTRL security bit, it is only possible to calculate the CRC32 of the whole
flash array when operated from the external address space. In most cases, this area will be the entire onboard nonvolatile memory. The Address, Length and Data registers will be forced to predefined values once the CRC32
operation is started, and values written by the user are ignored. This allows the user to verify the contents of a
protected device.
The actual test is started by writing a '1' in the 32-bit Cyclic Redundancy Check bit of the Control register
(CTRL.CRC). A running CRC32 operation can be canceled by resetting the module (writing '1' to CTRL.SWRST).
References:
28. NVMCTRL – Non-Volatile Memory Controller
© 2020 Microchip Technology Inc.
DS60001477C-page 89
SAM L21 Family Data Sheet
DSU - Device Service Unit
Security Bit
15.11.3.2 Interpreting the Results
The user should monitor the Status A register. When the operation is completed, STATUSA.DONE is set. Then the
Bus Error bit of the Status A register (STATUSA.BERR) must be read to ensure that no bus error occurred.
15.11.4 Debug Communication Channels
The Debug Communication Channels (DCCO and DCC1) consist of a pair of registers with associated handshake
logic, accessible by both CPU and debugger even if the device is protected by the NVMCTRL security bit. The
registers can be used to exchange data between the CPU and the debugger, during run time as well as in debug
mode. This enables the user to build a custom debug protocol using only these registers.
The DCC0 and DCC1 registers are accessible when the protected state is active. When the device is protected,
however, it is not possible to connect a debugger while the CPU is running (STATUSA.CRSTEXT is not writable and
the CPU is held under Reset).
Two Debug Communication Channel status bits in the Status B registers (STATUS.DCCDx) indicate whether a new
value has been written in DCC0 or DCC1. These bits, DCC0D and DCC1D, are located in the STATUSB registers.
They are automatically set on write and cleared on read.
Note: The DCC0 and DCC1 registers are shared with the on-board memory testing logic (MBIST). Accordingly,
DCC0 and DCC1 must not be used while performing MBIST operations.
References:
NVMCTRL
28.6.6 Security Bit
15.11.5 Testing of On-Board Memories MBIST
The DSU implements a feature for automatic testing of memory also known as MBIST (memory built-in self test). This
is primarily intended for production test of on-board memories. MBIST cannot be operated from the external address
range when the device is protected by the NVMCTRL security bit. If an MBIST command is issued when the device is
protected, a protection error is reported in the Protection Error bit in the Status A register (STATUSA.PERR).
1.
Algorithm
The algorithm used for testing is a type of March algorithm called "March LR". This algorithm is able to detect
a wide range of memory defects, while still keeping a linear run time. The algorithm is:
1.1.
1.2.
1.3.
1.4.
1.5.
1.6.
Write entire memory to '0', in any order.
Bit for bit read '0', write '1', in descending order.
Bit for bit read '1', write '0', read '0', write '1', in ascending order.
Bit for bit read '1', write '0', in ascending order.
Bit for bit read '0', write '1', read '1', write '0', in ascending order.
Read '0' from entire memory, in ascending order.
The specific implementation used has a run time which depends on the CPU clock frequency and the number
of bytes tested in the RAM. The detected faults are:
2.
– Address decoder faults
– Stuck-at faults
– Transition faults
– Coupling faults
– Linked Coupling faults
Starting MBIST
To test a memory, you need to write the start address of the memory to the ADDR.ADDR bit field, and the size
of the memory into the Length register.
For best test coverage, an entire physical memory block should be tested at once. It is possible to test only a
subset of a memory, but the test coverage will then be somewhat lower.
The actual test is started by writing a '1' to CTRL.MBIST. A running MBIST operation can be canceled by
writing a '1' to CTRL.SWRST.
© 2020 Microchip Technology Inc.
DS60001477C-page 90
SAM L21 Family Data Sheet
DSU - Device Service Unit
3.
4.
Interpreting the Results
The tester should monitor the STATUSA register. When the operation is completed, STATUSA.DONE is set.
There are two different modes:
– ADDR.AMOD=0: exit-on-error (default)
In this mode, the algorithm terminates either when a fault is detected or on successful completion. In both
cases, STATUSA.DONE is set. If an error was detected, STATUSA.FAIL will be set. User then can read
the DATA and ADDR registers to locate the fault.
– ADDR.AMOD=1: pause-on-error
In this mode, the MBIST algorithm is paused when an error is detected. In such a situation, only
STATUSA.FAIL is asserted. The state machine waits for user to clear STATUSA.FAIL by writing a '1' in
STATUSA.FAIL to resume. Prior to resuming, user can read the DATA and ADDR registers to locate the
fault.
Locating Faults
If the test stops with STATUSA.FAIL set, one or more bits failed the test. The test stops at the first detected
error. The position of the failing bit can be found by reading the following registers:
– ADDR: Address of the word containing the failing bit
– DATA: contains data to identify which bit failed, and during which phase of the test it failed. The DATA
register will in this case contains the following bit groups:
Figure 15-6. DATA bits Description When MBIST Operation Returns an Error
Bit
31
30
29
28
27
26
25
24
Bit
23
22
21
20
19
18
17
16
Bit
15
14
13
12
11
10
9
8
phase
Bit
7
6
5
4
3
2
0
1
bit_index
•
•
bit_index: contains the bit number of the failing bit
phase: indicates which phase of the test failed and the cause of the error, as listed in the following table.
Table 15-4. MBIST Operation Phases
Phase
Test actions
0
Write all bits to zero. This phase cannot fail.
1
Read '0', write '1', increment address
2
Read '1', write '0'
3
Read '0', write '1', decrement address
4
Read '1', write '0', decrement address
5
Read '0', write '1'
6
Read '1', write '0', decrement address
7
Read all zeros. bit_index is not used
© 2020 Microchip Technology Inc.
DS60001477C-page 91
SAM L21 Family Data Sheet
DSU - Device Service Unit
Table 15-5. AMOD Bit Descriptions for MBIST
AMOD[1:0]
Description
0x0
Exit on Error
0x1
Pause on Error
0x2, 0x3
Reserved
References:
NVMCTRL
Security Bit
15.11.6 System Services Availability when Accessed Externally
External access: Access performed in the DSU address offset 0x200-0x1FFF range.
Internal access: Access performed in the DSU address offset 0x0-0x100 range.
Table 15-6. Available Features when Operated From The External Address Range and Device is Protected
Features
Availability From The External Address Range and
Device is Protected
Chip-Erase command and status
Yes
CRC32
Yes, only full array or full EEPROM
CoreSight Compliant Device identification
Yes
Debug communication channels
Yes
Testing of onboard memories (MBIST)
No
STATUSA.CRSTEXT clearing
No (STATUSA.PERR is set when attempting to do so)
© 2020 Microchip Technology Inc.
DS60001477C-page 92
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.12
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
CTRL
STATUSA
STATUSB
Reserved
7:0
7:0
7:0
0x04
ADDR
0x08
LENGTH
0x0C
DATA
0x10
DCC0
0x14
DCC1
0x18
DID
0x1C
...
0x0FFF
0x1000
ENTRY0
ENTRY1
0x1008
END
0x100C
...
0x1FCB
Reserved
0x1FD0
MBIST
FAIL
DCCD1
BERR
DCCD0
CRC
CRSTEXT
DBGPRES
ADDR[5:0]
SWRST
DONE
PROT
AMOD[1:0]
ADDR[13:6]
ADDR[21:14]
ADDR[29:22]
LENGTH[5:0]
LENGTH[13:6]
LENGTH[21:14]
LENGTH[29:22]
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
DEVSEL[7:0]
DIE[3:0]
REVISION[3:0]
FAMILY[0]
SERIES[5:0]
PROCESSOR[3:0]
FAMILY[4:1]
Reserved
0x1004
0x1FCC
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CE
PERR
HPE
MEMTYPE
PID4
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
© 2020 Microchip Technology Inc.
FMT
EPRES
FMT
EPRES
ADDOFF[3:0]
ADDOFF[11:4]
ADDOFF[19:12]
ADDOFF[3:0]
ADDOFF[11:4]
ADDOFF[19:12]
END[7:0]
END[15:8]
END[23:16]
END[31:24]
SMEMP
FKBC[3:0]
JEPCC[3:0]
DS60001477C-page 93
SAM L21 Family Data Sheet
DSU - Device Service Unit
...........continued
Offset
Name
0x1FD4
...
0x1FDF
Reserved
0x1FE0
0x1FE4
0x1FE8
0x1FEC
0x1FF0
0x1FF4
0x1FF8
0x1FFC
15.13
PID0
PID1
PID2
PID3
CID0
CID1
CID2
CID3
Bit Pos.
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
PARTNBL[7:0]
JEPIDCL[3:0]
REVISION[3:0]
PARTNBH[3:0]
JEPU
REVAND[3:0]
JEPIDCH[2:0]
CUSMOD[3:0]
PREAMBLEB0[7:0]
CCLASS[3:0]
PREAMBLE[3:0]
PREAMBLEB2[7:0]
PREAMBLEB3[7:0]
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC writeprotection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to 15.5.6 Register Access Protection.
© 2020 Microchip Technology Inc.
DS60001477C-page 94
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.1 Control
Name:
Offset:
Reset:
Property:
Bit
7
CTRL
0x0000
0x00
PAC Write-Protection
6
5
Access
Reset
4
CE
W
0
3
MBIST
W
0
2
1
CRC
W
0
0
SWRST
W
0
Bit 4 – CE Chip-Erase
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the Chip-Erase operation.
Bit 3 – MBIST Memory Built-In Self-Test
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the memory BIST algorithm.
Bit 1 – CRC 32-bit Cyclic Redundancy Check
Writing a '0' to this bit has no effect.
Writing a '1' to this bit starts the cyclic redundancy check algorithm.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets the module.
© 2020 Microchip Technology Inc.
DS60001477C-page 95
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.2 Status A
Name:
Offset:
Reset:
Property:
Bit
7
STATUSA
0x0001
0x00
PAC Write-Protection
6
5
Access
Reset
4
PERR
R/W
0
3
FAIL
R/W
0
2
BERR
R/W
0
1
CRSTEXT
R/W
0
0
DONE
R/W
0
Bit 4 – PERR Protection Error
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Protection Error bit.
This bit is set when a command that is not allowed in protected state is issued.
Bit 3 – FAIL Failure
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Failure bit.
This bit is set when a DSU operation failure is detected.
Bit 2 – BERR Bus Error
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Bus Error bit.
This bit is set when a bus error is detected.
Bit 1 – CRSTEXT CPU Reset Phase Extension
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the CPU Reset Phase Extension bit.
This bit is set when a debug adapter Cold-Plugging is detected, which extends the CPU reset phase.
Bit 0 – DONE Done
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Done bit.
This bit is set when a DSU operation is completed.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.3 Status B
Name:
Offset:
Reset:
Property:
Bit
7
STATUSB
0x0002
0x10000
PAC Write Protection
6
Access
Reset
5
4
HPE
R
1
3
DCCD1
R
0
2
DCCD0
R
0
1
DBGPRES
R
0
0
PROT
R
0
Bit 4 – HPE Hot-Plugging Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set when Hot-Plugging is enabled.
This bit is cleared when Hot-Plugging is disabled. This is the case when the SWCLK function is changed. Only a
power Reset or a external Reset can set it again.
Bits 2, 3 – DCCDx Debug Communication Channel x Dirty [x=1..0]
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set when DCCx is written.
This bit is cleared when DCCx is read.
Bit 1 – DBGPRES Debugger Present
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set when a debugger probe is detected.
This bit is never cleared.
Bit 0 – PROT Protected
Writing a '0' to this bit has no effect.
Writing a '1' to this bit has no effect.
This bit is set at power-up when the device is protected.
This bit is never cleared.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.4 Address
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
ADDR
0x0004
0x00000000
PAC Write-Protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
ADDR[29:22]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
4
3
2
1
20
19
ADDR[21:14]
R/W
R/W
0
0
12
ADDR[13:6]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
7
6
5
0
ADDR[5:0]
Access
Reset
R/W
0
R/W
0
R/W
0
AMOD[1:0]
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:2 – ADDR[29:0] Address
Initial word start address needed for memory operations.
Bits 1:0 – AMOD[1:0] Access Mode
The functionality of these bits is dependent on the operation mode.
Bit description when operating CRC32: refer to 15.11.3 32-bit Cyclic Redundancy Check CRC32
Bit description when testing onboard memories (MBIST): refer to 15.11.5 Testing of On-Board Memories MBIST
© 2020 Microchip Technology Inc.
DS60001477C-page 98
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.5 Length
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
LENGTH
0x0008
0x00000000
PAC Write-Protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
28
27
LENGTH[29:22]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
20
19
LENGTH[21:14]
R/W
R/W
0
0
12
11
LENGTH[13:6]
R/W
R/W
0
0
4
LENGTH[5:0]
R/W
R/W
0
0
Bits 31:2 – LENGTH[29:0] Length
Length in words needed for memory operations.
© 2020 Microchip Technology Inc.
DS60001477C-page 99
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.6 Data
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
DATA
0x000C
0x00000000
PAC Write-Protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
DATA[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
20
19
DATA[23:16]
R/W
R/W
0
0
12
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0] Data
Memory operation initial value or result value.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.7 Debug Communication Channel 0
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
DCC0
0x0010
0x00000000
-
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
DATA[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
20
19
DATA[23:16]
R/W
R/W
0
0
12
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0] Data
Data register.
© 2020 Microchip Technology Inc.
DS60001477C-page 101
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.8 Debug Communication Channel 1
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
DCC1
0x0014
0x00000000
-
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
DATA[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
20
19
DATA[23:16]
R/W
R/W
0
0
12
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0] Data
Data register.
© 2020 Microchip Technology Inc.
DS60001477C-page 102
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.9 Device Identification
Name:
Offset:
Reset:
Property:
DID
0x0018
see related links
PAC Write-Protection
The information in this register is related to the Ordering Information.
Bit
Access
Reset
Bit
Access
Reset
Bit
31
30
29
PROCESSOR[3:0]
R
R
p
p
28
R
p
R
f
23
FAMILY[0]
R
f
22
20
19
15
14
R
p
21
27
26
25
24
R
f
R
f
R
f
18
17
16
FAMILY[4:1]
SERIES[5:0]
R
s
R
s
R
s
R
s
R
s
R
s
13
12
11
8
R
r
10
9
REVISION[3:0]
R
R
r
r
R
r
3
2
1
0
R
x
R
x
R
x
R
x
DIE[3:0]
Access
Reset
R
d
R
d
R
d
R
d
Bit
7
6
5
4
DEVSEL[7:0]
Access
Reset
R
x
R
x
R
x
R
x
Bits 31:28 – PROCESSOR[3:0] Processor
The value of this field defines the processor used on the device.
Bits 27:23 – FAMILY[4:0] Product Family
The value of this field corresponds to the Product Family part of the ordering code.
Bits 21:16 – SERIES[5:0] Product Series
The value of this field corresponds to the Product Series part of the ordering code.
Bits 15:12 – DIE[3:0] Die Number
Identifies the die family.
Bits 11:8 – REVISION[3:0] Revision Number
Identifies the die revision number. 0x0=rev.A, 0x1=rev.B etc.
Note: The device variant (last letter of the ordering number) is independent of the die revision
(DSU.DID.REVISION): The device variant denotes functional differences, whereas the die revision marks evolution of
the die.
Bits 7:0 – DEVSEL[7:0] Device Selection
This bit field identifies a device within a product family and product series. Refer to the Ordering Information for
device configurations and corresponding values for Flash memory density, pin count and device variant. For further
information, refer to Device Identification.
© 2020 Microchip Technology Inc.
DS60001477C-page 103
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.10 CoreSight ROM Table Entry 0
Name:
Offset:
Reset:
Property:
ENTRY0
0x1000
0xXXXXX00X
PAC Write-Protection
Bit
31
30
29
28
27
ADDOFF[19:12]
R
R
x
x
26
25
24
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
Bit
23
22
21
18
17
16
R
x
20
19
ADDOFF[11:4]
R
R
x
x
Access
Reset
R
x
R
x
R
x
R
x
R
x
Bit
15
14
13
12
11
10
9
8
3
2
1
FMT
R
1
0
EPRES
R
x
ADDOFF[3:0]
Access
Reset
R
x
R
x
R
x
R
x
Bit
7
6
5
4
Access
Reset
Bits 31:12 – ADDOFF[19:0] Address Offset
The base address of the component, relative to the base address of this ROM table.
Bit 1 – FMT Format
Always reads as '1', indicating a 32-bit ROM table.
Bit 0 – EPRES Entry Present
This bit indicates whether an entry is present at this location in the ROM table.
This bit is set at power-up if the device is not protected indicating that the entry is not present.
This bit is cleared at power-up if the device is not protected indicating that the entry is present.
© 2020 Microchip Technology Inc.
DS60001477C-page 104
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.11 CoreSight ROM Table Entry 1
Name:
Offset:
Reset:
Property:
ENTRY1
0x1004
0xXXXXX00X
PAC Write-Protection
Bit
31
30
29
28
27
ADDOFF[19:12]
R
R
x
x
26
25
24
Access
Reset
R
x
R
x
R
x
R
x
R
x
R
x
Bit
23
22
21
18
17
16
R
x
20
19
ADDOFF[11:4]
R
R
x
x
Access
Reset
R
x
R
x
R
x
R
x
R
x
Bit
15
14
13
12
11
10
9
8
3
2
1
FMT
R
1
0
EPRES
R
x
ADDOFF[3:0]
Access
Reset
R
x
R
x
R
x
R
x
Bit
7
6
5
4
Access
Reset
Bits 31:12 – ADDOFF[19:0] Address Offset
The base address of the component, relative to the base address of this ROM table.
Bit 1 – FMT Format
Always read as '1', indicating a 32-bit ROM table.
Bit 0 – EPRES Entry Present
This bit indicates whether an entry is present at this location in the ROM table.
This bit is set at power-up if the device is not protected indicating that the entry is not present.
This bit is cleared at power-up if the device is not protected indicating that the entry is present.
© 2020 Microchip Technology Inc.
-
DS60001477C-page 105
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.12 CoreSight ROM Table End
Name:
Offset:
Reset:
Property:
Bit
31
END
0x1008
0x00000000
-
30
29
28
27
26
25
24
R
0
R
0
R
0
R
0
19
18
17
16
R
0
R
0
R
0
R
0
11
10
9
8
R
0
R
0
R
0
R
0
3
2
1
0
R
0
R
0
R
0
R
0
END[31:24]
Access
Reset
R
0
R
0
R
0
R
0
Bit
23
22
21
20
END[23:16]
Access
Reset
R
0
R
0
R
0
R
0
Bit
15
14
13
12
END[15:8]
Access
Reset
R
0
R
0
R
0
R
0
Bit
7
6
5
4
END[7:0]
Access
Reset
R
0
R
0
R
0
R
0
Bits 31:0 – END[31:0] End Marker
Indicates the end of the CoreSight ROM table entries.
© 2020 Microchip Technology Inc.
DS60001477C-page 106
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.13 CoreSight ROM Table Memory Type
Name:
Offset:
Reset:
Property:
Bit
MEMTYPE
0x1FCC
0x0000000X
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
SMEMP
R
x
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 0 – SMEMP System Memory Present
This bit indicates whether system memory is present on the bus that connects to the ROM table.
This bit is set at power-up if the device is not protected, indicating that the system memory is accessible from a
debug adapter.
This bit is cleared at power-up if the device is protected, indicating that the system memory is not accessible from a
debug adapter.
© 2020 Microchip Technology Inc.
DS60001477C-page 107
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.14 Peripheral Identification 4
Name:
Offset:
Reset:
Property:
Bit
PID4
0x1FD0
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
FKBC[3:0]
Access
Reset
R
0
R
0
JEPCC[3:0]
R
0
R
0
R
0
R
0
Bits 7:4 – FKBC[3:0] 4KB Count
These bits will always return zero when read, indicating that this debug component occupies one 4KB block.
Bits 3:0 – JEPCC[3:0] JEP-106 Continuation Code
These bits will always return zero when read, indicating an Atmel device.
© 2020 Microchip Technology Inc.
DS60001477C-page 108
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.15 Peripheral Identification 0
Name:
Offset:
Reset:
Property:
Bit
PID0
0x1FE0
0x000000D0
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
PARTNBL[7:0]
Access
Reset
R
1
R
1
R
0
R
1
Bits 7:0 – PARTNBL[7:0] Part Number Low
These bits will always return 0xD0 when read, indicating that this device implements a DSU module instance.
© 2020 Microchip Technology Inc.
DS60001477C-page 109
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.16 Peripheral Identification 1
Name:
Offset:
Reset:
Property:
Bit
PID1
0x1FE4
0x000000FC
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
R
1
R
1
R
1
1
PARTNBH[3:0]
R
R
1
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
JEPIDCL[3:0]
Access
Reset
R
1
R
1
R
0
Bits 7:4 – JEPIDCL[3:0] Low part of the JEP-106 Identity Code
These bits will always return 0xF when read, indicating a Atmel device (Atmel JEP-106 identity code is 0x1F).
Bits 3:0 – PARTNBH[3:0] Part Number High
These bits will always return 0xC when read, indicating that this device implements a DSU module instance.
© 2020 Microchip Technology Inc.
DS60001477C-page 110
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.17 Peripheral Identification 2
Name:
Offset:
Reset:
Property:
Bit
PID2
0x1FE8
0x00000009
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
4
1
JEPIDCH[2:0]
R
0
0
R
0
3
JEPU
R
1
2
Access
Reset
5
REVISION[3:0]
R
R
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
R
0
R
0
R
1
Bits 7:4 – REVISION[3:0] Revision Number
Revision of the peripheral. Starts at 0x0 and increments by one at both major and minor revisions.
Bit 3 – JEPU JEP-106 Identity Code is used
This bit will always return one when read, indicating that JEP-106 code is used.
Bits 2:0 – JEPIDCH[2:0] JEP-106 Identity Code High
These bits will always return 0x1 when read, indicating an Atmel device (Atmel JEP-106 identity code is 0x1F).
© 2020 Microchip Technology Inc.
DS60001477C-page 111
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.18 Peripheral Identification 3
Name:
Offset:
Reset:
Property:
Bit
PID3
0x1FEC
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
REVAND[3:0]
Access
Reset
R
0
R
0
CUSMOD[3:0]
R
0
R
0
R
0
R
0
Bits 7:4 – REVAND[3:0] Revision Number
These bits will always return 0x0 when read.
Bits 3:0 – CUSMOD[3:0] ARM CUSMOD
These bits will always return 0x0 when read.
© 2020 Microchip Technology Inc.
DS60001477C-page 112
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.19 Component Identification 0
Name:
Offset:
Reset:
Property:
Bit
CID0
0x1FF0
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
PREAMBLEB0[7:0]
R
R
0
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 7:0 – PREAMBLEB0[7:0] Preamble Byte 0
These bits will always return 0xD when read.
© 2020 Microchip Technology Inc.
DS60001477C-page 113
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.20 Component Identification 1
Name:
Offset:
Reset:
Property:
Bit
CID1
0x1FF4
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
0
R
0
R
0
R
0
2
1
PREAMBLE[3:0]
R
R
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
CCLASS[3:0]
Access
Reset
R
0
R
0
R
0
Bits 7:4 – CCLASS[3:0] Component Class
These bits will always return 0x1 when read indicating that this ARM CoreSight component is ROM table (refer to the
ARM Debug Interface v5 Architecture Specification at http://www.arm.com).
Bits 3:0 – PREAMBLE[3:0] Preamble
These bits will always return 0x0 when read.
© 2020 Microchip Technology Inc.
DS60001477C-page 114
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.21 Component Identification 2
Name:
Offset:
Reset:
Property:
Bit
CID2
0x1FF8
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
PREAMBLEB2[7:0]
R
R
0
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 7:0 – PREAMBLEB2[7:0] Preamble Byte 2
These bits will always return 0x05 when read.
© 2020 Microchip Technology Inc.
DS60001477C-page 115
SAM L21 Family Data Sheet
DSU - Device Service Unit
15.13.22 Component Identification 3
Name:
Offset:
Reset:
Property:
Bit
CID3
0x1FFC
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
PREAMBLEB3[7:0]
R
R
0
0
R
0
R
0
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 7:0 – PREAMBLEB3[7:0] Preamble Byte 3
These bits will always return 0xB1 when read.
© 2020 Microchip Technology Inc.
DS60001477C-page 116
SAM L21 Family Data Sheet
Clock System
16.
Clock System
This chapter summarizes the clock distribution and terminology in the SAM L21 device. It will not explain every detail
of its configuration. For in-depth documentation, see the respective peripherals descriptions and the 17. GCLK Generic Clock Controllerand 18. MCLK – Main Clock documentation.
16.1
Clock Distribution
Figure 16-1. Clock Distribution
MCLK
GCLK_DFLL48M_REF
GCLK_MAIN
GCLK
OSCCTRL
XOSC
GCLK Generator 0
Peripheral Channel 0
(DFLL48M Reference)
GCLK Generator 1
Peripheral Channel 1
(FDPLL96M Reference)
GCLK_DPLL
GCLK Generator x
Peripheral Channel 2
(FDPLL96M Reference)
GCLK_DPLL_32K
OSC16M
DFLL48M
FDPLL96M
OSCK32CTRL
OSC32K
Peripheral Channel 3
32kHz
XOSC32K
32kHz
1kHz
OSCULP32K
Peripheral 0
Generic
Clocks
1kHz
Peripheral Channel y
32kHz
Peripheral z
1kHz
AHB/APB System Clocks
GCLK_DPLL
GCLK_DPLL_32K
Syncronous Clock
Controller
RTC
CLK_RTC_OSC
CLK_WDT_OSC
CLK_ULP32K
WDT
EIC
OPAMP
The SAM L21 clock system consists of:
•
Clock sources, i.e. oscillators controlled by OSCCTRL and OSC32KCTRL
– A clock source provides a time base that is used by other components, such as Generic Clock Generators.
Example clock sources are the internal 16MHz oscillator (OSC16M), external crystal oscillator (XOSC) and
the Digital Frequency Locked Loop (DFLL48M).
•
Generic Clock Controller (GCLK), which generates, controls and distributes the asynchronous clock consisting
of:
– Generic Clock Generators: These are programmable prescalers that can use any of the system clock
sources as a time base. The Generic Clock Generator 0 generates the clock signal GCLK_MAIN, which is
used by the Power Manager and the Main Clock (MCLK) module, which in turn generates synchronous
clocks.
– Generic Clocks: These are clock signals generated by Generic Clock Generators and output by the
Peripheral Channels, and serve as clocks for the peripherals of the system. Multiple instances of a
© 2020 Microchip Technology Inc.
DS60001477C-page 117
SAM L21 Family Data Sheet
Clock System
peripheral will typically have a separate Generic Clock for each instance. Generic Clock 0 serves as the
clock source for the DFLL48M clock input (when multiplying another clock source).
•
Main Clock Controller (MCLK)
– The MCLK generates and controls the synchronous clocks on the system. This includes the CPU, bus
clocks (APB, AHB) as well as the synchronous (to the CPU) user interfaces of the peripherals. It contains
clock masks that can turn on/off the user interface of a peripheral as well as prescalers for the CPU and
bus clocks.
The next figure shows an example where SERCOM0 is clocked by the DFLL48M in open loop mode. The DFLL48M
is enabled, the Generic Clock Generator 1 uses the DFLL48M as its clock source and feeds into Peripheral Channel
13. The Generic Clock , also called GCLK_SERCOM0_CORE, is connected to SERCOM0. The SERCOM0 interface,
clocked by CLK_SERCOM0_APB, has been unmasked in the APBC Mask register in the MCLK.
Figure 16-2. Example of SERCOM Clock
MCLK
Syncronous Clock
Controller
OSCCTRL
CLK_SERCOM0_APB
GCLK
DFLL48M
Generic Clock
Generator 1
Peripheral
Channel 13
GCLK_SERCOM0_CORE
SERCOM 0
To customize the clock distribution, refer to these registers and bit fields:
• The source oscillator for a generic clock generator n is selected by writing to the Source bit field in the Generator
Control n register (GCLK.GENCTRLn.SRC).
• A Peripheral Channel m can be configured to use a specific Generic Clock Generator by writing to the Generic
Clock Generator bit field in the respective Peripheral Channel m register (GCLK.PCHCTRLm.GEN)
• The Peripheral Channel number, m, is fixed for a given peripheral. See the Mapping table in the description of
GCLK.PCHCTRLm.
• The AHB clocks are enabled and disabled by writing to the respective bit in the AHB Mask register
(MCLK.AHBMASK).
• The APB clocks are enabled and disabled by writing to the respective bit in the APB x Mask registers
(MCLK.APBxMASK).
16.2
Synchronous and Asynchronous Clocks
As the CPU and the peripherals can be in different clock domains, i.e. they are clocked from different clock sources
and/or with different clock speeds, some peripheral accesses by the CPU need to be synchronized. In this case the
peripheral includes a Synchronization Busy (SYNCBUSY) register that can be used to check if a sync operation is in
progress.
For a general description, see 16.3 Register Synchronization. Some peripherals have specific properties described
in their individual sub-chapter “Synchronization”.
In the data sheet, references to Synchronous Clocks are referring to the CPU and bus clocks (MCLK), while
asynchronous clocks are generated by the 17. GCLK - Generic Clock Controller.
References:
17.6.3 Synchronization
© 2020 Microchip Technology Inc.
DS60001477C-page 118
SAM L21 Family Data Sheet
Clock System
16.3
Register Synchronization
16.3.1
Overview
All peripherals are composed of one digital bus interface connected to the APB or AHB bus and running from a
corresponding clock in the Main Clock domain, and one peripheral core running from the peripheral Generic Clock
(GCLK).
Communication between these clock domains must be synchronized. This mechanism is implemented in hardware,
so the synchronization process takes place even if the peripheral generic clock is running from the same clock source
and on the same frequency as the bus interface.
All registers in the bus interface are accessible without synchronization.
All registers in the peripheral core are synchronized when written. Some registers in the peripheral core are
synchronized when read.
Each individual register description will have the properties "Read-Synchronized" and/or "Write-Synchronized" if a
register is synchronized.
As shown in the figure below, each register that requires synchronization has its individual synchronizer and its
individual synchronization status bit in the Synchronization Busy register (SYNCBUSY).
Note: For registers requiring both read- and write-synchronization, the corresponding bit in SYNCBUSY is shared.
Figure 16-3. Register Synchronization Overview
Synchronous Domain
(CLK_APB)
Asynchronous Domain
(GCLK)
Non Sync’d reg
Sync
Sync
Read-Sync’d reg Read-only register
Sync
Periperal Bus
Write-Sync’d reg Write-only register
R/W-Sync’d reg
Sync
SYNCBUSY
Write-Sync’d reg R/W register
INTFLAG
© 2020 Microchip Technology Inc.
Read-only register
Sync
Non Sync’d reg
R/W register
DS60001477C-page 119
SAM L21 Family Data Sheet
Clock System
16.3.2
General Write Synchronization
Write-Synchronization is triggered by writing to a register in the peripheral clock domain. The respective bit in the
Synchronization Busy register (SYNCBUSY) will be set when the write-synchronization starts and cleared when the
write-synchronization is complete. Refer to 16.3.7 Synchronization Delay for details on the synchronization delay.
When write-synchronization is ongoing for a register, any subsequent write attempts to this register will be discarded,
and an error will be reported.
Example:
REGA, REGB are 8-bit core registers. REGC is a 16-bit core register.
Offset
Register
0x00
REGA
0x01
REGB
0x02
REGC
0x03
Synchronization is per register, so multiple registers can be synchronized in parallel. Consequently, after REGA (8-bit
access) was written, REGB (8-bit access) can be written immediately without error.
REGC (16-bit access) can be written without affecting REGA or REGB. If REGC is written to in two consecutive 8-bit
accesses without waiting for synchronization, the second write attempt will be discarded and an error is generated.
A 32-bit access to offset 0x00 will write all three registers. Note that REGA, REGB and REGC can be updated at
different times because of independent write synchronization.
References:
13. PAC - Peripheral Access Controller
16.3.3
General Read Synchronization
Read-synchronized registers are synchronized each time the register value is updated but the corresponding
SYNCBUSY bits are not set. Reading a read-synchronized register does not start a new synchronization, it returns
the last synchronized value.
Note: The corresponding bits in SYNCBUSY will automatically be set when the device wakes up from sleep
because read-synchronized registers need to be synchronized. Therefore reading a read-synchronized register
before its corresponding SYNCBUSY bit is cleared will return the last synchronized value before sleep mode.
16.3.4
Completion of Synchronization
In order to check if synchronization is complete, the user can either poll the relevant bits in SYNCBUSY or use the
Synchronisation Ready interrupt (if available). The Synchronization Ready interrupt flag will be set when all ongoing
synchronizations are complete, i.e. when all bits in SYNCBUSY are '0'.
16.3.5
Enable Write Synchronization
Setting the Enable bit in a module's Control A register (CTRLA.ENABLE) will trigger write-synchronization and set
SYNCBUSY.ENABLE.
CTRLA.ENABLE will read its new value immediately after being written.
SYNCBUSY.ENABLE will be cleared by hardware when the operation is complete.
The Synchronisation Ready interrupt (if available) cannot be used to enable write-synchronization.
16.3.6
Software Reset Write-Synchronization
Setting the Software Reset bit in CTRLA (CTRLA.SWRST=1) will trigger write-synchronization and set
SYNCBUSY.SWRST. When writing a ‘1’ to the CTRLA.SWRST bit it will immediately read as ‘1’.
CTRL.SWRST and SYNCBUSY.SWRST will be cleared by hardware when the peripheral has been reset.
Writing a '0' to the CTRL.SWRST bit has no effect.
© 2020 Microchip Technology Inc.
DS60001477C-page 120
SAM L21 Family Data Sheet
Clock System
The Ready interrupt (if available) cannot be used for Software Reset write-synchronization.
16.3.7
Synchronization Delay
The synchronization will delay write and read accesses by a certain amount. This delay D is within the range of:
5×PGCLK + 2×PAPB < D < 6×PGCLK + 3×PAPB
Where PGCLK is the period of the generic clock and PAPB is the period of the peripheral bus clock. A normal peripheral
bus register access duration is 2×PAPB.
16.4
Enabling a Peripheral
In order to enable a peripheral that is clocked by a Generic Clock, the following parts of the system needs to be
configured:
•
•
•
•
16.5
A running Clock Source
A clock from the Generic Clock Generator must be configured to use one of the running Clock Sources, and the
Generator must be enabled.
The Peripheral Channel that provides the Generic Clock signal to the peripheral must be configured to use a
running Generic Clock Generator, and the Generic Clock must be enabled.
The user interface of the peripheral needs to be unmasked in the PM. If this is not done the peripheral registers
will read all 0’s and any writing attempts to the peripheral will be discarded.
On Demand Clock Requests
Figure 16-4. Clock Request Routing
Clock request
DFLL48M
Generic Clock
Generator
ENABLE
GENEN
RUNSTDBY
RUNSTDBY
Clock request
Generic Clock
Periph. Channel
Clock request
Peripheral
CLKEN
ENABLE
RUNSTDBY
ONDEMAND
All clock sources in the system can be run in an on-demand mode: the clock source is in a stopped state unless a
peripheral is requesting the clock source. Clock requests propagate from the peripheral, via the GCLK, to the clock
source. If one or more peripheral is using a clock source, the clock source will be started/kept running. As soon as
the clock source is no longer needed and no peripheral has an active request, the clock source will be stopped until
requested again.
The clock request can reach the clock source only if the peripheral, the generic clock and the clock from the Generic
Clock Generator in-between are enabled. The time taken from a clock request being asserted to the clock source
being ready is dependent on the clock source startup time, clock source frequency as well as the divider used in the
Generic Clock Generator. The total startup time Tstart from a clock request until the clock is available for the
peripheral is between:
Tstart_max = Clock source startup time + 2 × clock source periods + 2 × divided clock source periods
Tstart_min = Clock source startup time + 1 × clock source period + 1 × divided clock source period
The time between the last active clock request stopped and the clock is shut down, Tstop, is between:
Tstop_min = 1 × divided clock source period + 1 × clock source period
Tstop_max = 2 × divided clock source periods + 2 × clock source periods
The On-Demand function can be disabled individually for each clock source by clearing the ONDEMAND bit located
in each clock source controller. Consequently, the clock will always run whatever the clock request status is. This has
the effect of removing the clock source startup time at the cost of power consumption.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
Clock System
The clock request mechanism can be configured to work in standby mode by setting the RUNSDTBY bits of the
modules, see Figure 16-4.
16.6
Power Consumption vs. Speed
When targeting for either a low-power or a fast acting system, some considerations have to be taken into account
due to the nature of the asynchronous clocking of the peripherals:
If clocking a peripheral with a very low clock, the active power consumption of the peripheral will be lower. At the
same time the synchronization to the synchronous (CPU) clock domain is dependent on the peripheral clock speed,
and will take longer with a slower peripheral clock. This will cause worse response times and longer synchronization
delays.
16.7
Clocks after Reset
On any Reset the synchronous clocks start to their initial state:
•
•
•
OSC16M is enabled and configured to run at 4MHz
Generic Generator 0 uses OSC16M as source and generates GCLK_MAIN
CPU and BUS clocks are undivided
On a Power-on Reset, the 32KHz clock sources are reset and the GCLK module starts to its initial state:
•
•
All Generic Clock Generators are disabled except
– Generator 0 is using OSC16M at 4MHz as source and generates GCLK_MAIN
All Peripheral Channels in GCLK are disabled
On a User Reset the GCLK module starts to its initial state, except for:
•
Generic Clocks that are write-locked, i.e., the according WRTLOCK is set to 1 prior to Reset
References:
19. RSTC – Reset Controller
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
17.
GCLK - Generic Clock Controller
17.1
Overview
Depending on the application, peripherals may require specific clock frequencies to operate correctly. The Generic
Clock controller (GCLK) provides Generic Clock Generators that can provide a wide range of clock frequencies.
Generators can be set to use different external and internal oscillators as source. The clock of each Generator can be
divided. The outputs from the Generators are used as sources for the Peripheral Channels, which provide the
Generic Clock (GCLK_PERIPH) to the peripheral modules, as shown in Figure 17-2. The number of Peripheral
Clocks depends on how many peripherals the device has.
Note: The Generator 0 is always the direct source of the GCLK_MAIN signal.
17.2
Features
•
•
17.3
Provides a device-defined, configurable number of Peripheral Channel clocks
Wide frequency range
Block Diagram
The generation of Peripheral Clock signals (GCLK_PERIPH) and the Main Clock (GCLK_MAIN) can be seen in
Device Clocking Diagram.
Figure 17-1. Device Clocking Diagram
GENERIC CLOCK CONTROLLER
OSCCTR
Generic Clock Generator
XOSC
DPLL96M
Peripheral Channel
OSC16M
GCLK_PERIPH
DFLL48M
OSC32CTRL
XOSC32K
Clock
Divider &
Masker
Clock
Gate
PERIPHERAL
OSCULP32K
OSC32K
GCLK_IO
GCLK_MAIN
MCLK
The GCLK block diagram is shown below:
© 2020 Microchip Technology Inc.
DS60001477C-page 123
SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
Figure 17-2. Generic Clock Controller Block Diagram
Generic Clock Generator 0
Clock Sources
Clock
Divider &
Masker
GCLK_IO[0]
(I/O input)
GCLK_MAIN
GCLKGEN[0]
GCLK_IO[0]
(I/O output)
Peripheral Channel 0
Clock
Gate
GCLK_PERIPH[0]
GCLK_IO[1]
(I/O output)
Generic Clock Generator 1
Clock
Divider &
Masker
GCLK_IO[1]
(I/O input)
Peripheral Channel 1
GCLKGEN[1]
Clock
Gate
GCLK_PERIPH[1]
Generic Clock Generator n
GCLK_IO[n]
(I/O input)
Clock
Divider &
Masker
GCLK_IO[n]
(I/O output)
GCLKGEN[n]
Peripheral Channel m
Clock
Gate
GCLK_PERIPH[m]
GCLKGEN[n:0]
17.4
Signal Description
Table 17-1. GCLK Signal Description
Signal Name
Type
Description
GCLK_IO[7:0]
Digital I/O
Clock source for Generators when
input
Generic Clock signal when output
Note: One signal can be mapped on several pins.
References:
7. I/O Multiplexing and Considerations
17.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
17.5.1
I/O Lines
Using the GCLK I/O lines requires the I/O pins to be configured.
References:
29. PORT - I/O Pin Controller
17.5.2
Power Management
The GCLK can operate in all sleep modes, if required.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
References:
20. PM – Power Manager
17.5.3
Clocks
The GCLK bus clock (CLK_GCLK_APB) can be enabled and disabled in the Main Clock Controller.
References:
18.6.2.6 Peripheral Clock Masking
22. OSC32KCTRL – 32KHz Oscillators Controller
17.5.4
DMA
Not applicable.
17.5.5
Interrupts
Not applicable.
17.5.6
Events
Not applicable.
17.5.7
Debug Operation
When the CPU is halted in debug mode the GCLK continues normal operation. If the GCLK is configured in a way
that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss
may result during debugging.
17.5.8
Register Access Protection
All registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC).
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply
for accesses through an external debugger.
References:
13. PAC - Peripheral Access Controller
17.5.9
Analog Connections
Not applicable.
17.6
Functional Description
17.6.1
Principle of Operation
The GCLK module is comprised of Generic Clock Generators (Generators) sourcing up to 64 Peripheral Channels
and the Main Clock signal GCLK_MAIN.
A clock source selected as input to a Generator can either be used directly, or it can be prescaled in the Generator. A
generator output is used by one or more Peripheral Channels to provide a peripheral generic clock signal
(GCLK_PERIPH) to the peripherals.
17.6.1.1 Basic Operation
17.6.1.1.1 Initialization
Before a Generator is enabled, the corresponding clock source should be enabled. The Peripheral clock must be
configured as outlined by the following steps:
1. The Generator must be enabled (GENCTRLn.GENEN=1) and the division factor must be set
(GENTRLn.DIVSEL and GENCTRLn.DIV) by performing a single 32-bit write to the Generator Control register
(GENCTRLn).
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
2.
The Generic Clock for a peripheral must be configured by writing to the respective Peripheral Channel Control
register (PCHCTRLm). The Generator used as the source for the Peripheral Clock must be written to the GEN
bit field in the Peripheral Channel Control register (PCHCTRLm.GEN).
Note: Each Generator n is configured by one dedicated register GENCTRLn.
Note: Each Peripheral Channel m is configured by one dedicated register PCHCTRLm.
17.6.1.1.2 Enabling, Disabling, and Resetting
The GCLK module has no enable/disable bit to enable or disable the whole module.
The GCLK is reset by setting the Software Reset bit in the Control A register (CTRLA.SWRST) to 1. All registers in
the GCLK will be reset to their initial state, except for Peripheral Channels and associated Generators that have their
Write Lock bit set to 1 (PCHCTRLm.WRTLOCK). For further details, refer to 17.6.2.4 Configuration Lock.
17.6.1.1.3 Generic Clock Generator
Each Generator (GCLK_GEN) can be set to run from one of nine different clock sources except GCLK_GEN[1],
which can be set to run from one of eight sources. GCLK_GEN[1] is the only Generator that can be selected as
source to others Generators.
Each generator GCLK_GEN[x] can be connected to one specific pin (GCLK_IO[y]). The GCLK_IO[y] can be set to
act as source to GCLK_GEN[x] or to output the clock signal generated by GCLK_GEN[x].
The selected source can be divided. Each Generator can be enabled or disabled independently.
Each GCLK_GEN clock signal can then be used as clock source for Peripheral Channels. Each Generator output is
allocated to one or several Peripherals.
GCLK_GEN[0] is used as GCLK_MAIN for the synchronous clock controller inside the Main Clock Controller. Refer to
the Main Clock Controller description for details on the synchronous clock generation.
Figure 17-3. Generic Clock Generator
17.6.1.1.4 Enabling a Generator
A Generator is enabled by writing a '1' to the Generator Enable bit in the Generator Control register
(GENCTRLn.GENEN=1).
17.6.1.1.5 Disabling a Generator
A Generator is disabled by writing a '0' to GENCTRLn.GENEN. When GENCTRLn.GENEN=0, the GCLK_GEN[n]
clock is disabled and gated.
17.6.1.1.6 Selecting a Clock Source for the Generator
Each Generator can individually select a clock source by setting the Source Select bit group in the Generator Control
register (GENCTRLn.SRC).
Changing from one clock source, for example A, to another clock source, B, can be done on the fly: If clock source B
is not ready, the Generator will continue using clock source A. As soon as source B is ready, the Generator will switch
to it. During the switching operation, the Generator maintains clock requests to both clock sources A and B, and will
release source A as soon as the switch is done. The according bit in SYNCBUSY register (SYNCBUSY.GENCTRLn)
will remain '1' until the switch operation is completed.
© 2020 Microchip Technology Inc.
DS60001477C-page 126
SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
The available clock sources are device dependent (usually the oscillators, RC oscillators, DPLL, and DFLL). Only
Generator 1 can be used as a common source for all other generators.
17.6.1.1.7 Changing the Clock Frequency
The selected source for a Generator can be divided by writing a division value in the Division Factor bit field of the
Generator Control register (GENCTRLn.DIV). How the actual division factor is calculated is depending on the Divide
Selection bit (GENCTRLn.DIVSEL).
If GENCTRLn.DIVSEL=0 and GENCTRLn.DIV is either 0 or 1, the output clock will be undivided.
Note: The number of DIV bits for each Generator is device dependent.
17.6.1.1.8 Duty Cycle
When dividing a clock with an odd division factor, the duty-cycle will not be 50/50. Setting the Improve Duty Cycle bit
of the Generator Control register (GENCTRLn.IDC) will result in a 50/50 duty cycle.
17.6.1.1.9 External Clock
The output clock (GCLK_GEN) of each Generator can be sent to I/O pins (GCLK_IO).
If the Output Enable bit in the Generator Control register is set (GENCTRLn.OE = 1) and the generator is enabled
(GENCTRLn.GENEN=1), the Generator requests its clock source and the GCLK_GEN clock is output to an I/O pin.
If GENCTRLn.OE is 0, the according I/O pin is set to an Output Off Value, which is selected by GENCTRLn.OOV: If
GENCTRLn.OOV is '0', the output clock will be low when turned off. If this bit is '1', the output clock will be high when
turned off.
In Standby mode, if the clock is output (GENCTRLn.OE=1), the clock on the I/O pin is frozen to the OOV value if the
Run In Standby bit of the Generic Control register (GENCTRLn.RUNSTDBY) is zero. If GENCTRLn.RUNSTDBY is
'1', the GCLKGEN clock is kept running and output to the I/O pin.
References:
20.6.3.6 Power Domain Controller
17.6.2
Peripheral Clock
Figure 17-4. Peripheral Clock
17.6.2.1 Enabling a Peripheral Clock
Before a Peripheral Clock is enabled, one of the Generators must be enabled (GENCTRLn.GENEN) and selected as
source for the Peripheral Channel by setting the Generator Selection bits in the Peripheral Channel Control register
(PCHCTRL.GEN). Any available Generator can be selected as clock source for each Peripheral Channel.
When a Generator has been selected, the peripheral clock is enabled by setting the Channel Enable bit in the
Peripheral Channel Control register, PCHCTRLm.CHEN = 1. The PCHCTRLm.CHEN bit must be synchronized to the
generic clock domain. PCHCTRLm.CHEN will continue to read as its previous state until the synchronization is
complete.
17.6.2.2 Disabling a Peripheral Clock
A Peripheral Clock is disabled by writing PCHCTRLm.CHEN=0. The PCHCTRLm.CHEN bit must be synchronized to
the Generic Clock domain. PCHCTRLm.CHEN will stay in its previous state until the synchronization is complete.
The Peripheral Clock is gated when disabled.
© 2020 Microchip Technology Inc.
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DS60001477C-page 127
SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
17.6.2.3 Selecting the Clock Source for a Peripheral
When changing a peripheral clock source by writing to PCHCTRLm.GEN, the peripheral clock must be disabled
before re-enabling it with the new clock source setting. This prevents glitches during the transition:
1. Disable the Peripheral Channel by writing PCHCTRLm.CHEN=0
2. Assert that PCHCTRLm.CHEN reads '0'
3. Change the source of the Peripheral Channel by writing PCHCTRLm.GEN
4. Re-enable the Peripheral Channel by writing PCHCTRLm.CHEN=1
References:
17.10.4 PCHCTRLm
17.6.2.4 Configuration Lock
The peripheral clock configuration can be locked for further write accesses by setting the Write Lock bit in the
Peripheral Channel Control register PCHCTRLm.WRTLOCK=1). All writing to the PCHCTRLm register will be
ignored. It can only be unlocked by a Power Reset.
The Generator source of a locked Peripheral Channel will be locked, too: The corresponding GENCTRLn register is
locked, and can be unlocked only by a Power Reset.
There is one exception concerning the Generator 0. As it is used as GCLK_MAIN, it cannot be locked. It is reset by
any Reset and will start up in a known configuration. The software reset (CTRLA.SWRST) can not unlock the
registers.
In case of an external Reset, the Generator source will be disabled. Even if the WRTLOCK bit is written to '1' the
peripheral channels are disabled (PCHCTRLm.CHEN set to '0') until the Generator source is enabled again. Then,
the PCHCTRLm.CHEN are set to '1' again.
References:
17.10.4 PCHCTRLm
17.10.1 CTRLA
17.6.3
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
An exception is the Channel Enable bit in the Peripheral Channel Control registers (PCHCTRLm.CHEN). When
changing this bit, the bit value must be read-back to ensure the synchronization is complete and to assert glitch free
internal operation. Note that changing the bit value under ongoing synchronization will not generate an error.
The following registers are synchronized when written:
• Generic Clock Generator Control register (GENCTRLn)
• Control A register (CTRLA)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
References:
17.10.1 CTRLA
17.10.4 PCHCTRLm
17.7
Sleep Mode Operation
17.7.1
SleepWalking
The GCLK module supports the SleepWalking feature.
If the system is in a sleep mode where the Generic Clocks are stopped, a peripheral that needs its clock in order to
execute a process must request it from the Generic Clock Controller.
© 2020 Microchip Technology Inc.
DS60001477C-page 128
SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
The Generic Clock Controller receives this request, determines which Generic Clock Generator is involved and which
clock source needs to be awakened. It then wakes up the respective clock source, enables the Generator and
Peripheral Channel stages successively, and delivers the clock to the peripheral.
The RUNSTDBY bit in the Generator Control register controls clock output to pin during standby sleep mode. If the
bit is cleared, the Generator output is not available on pin. When set, the GCLK can continuously output the
generator output to GCLK_IO. Refer to 17.6.1.1.9 External Clock for details.
References:
20. PM – Power Manager
17.7.2
Minimize Power Consumption in Standby
The following table identifies when a Clock Generator is off in Standby Mode, minimizing the power consumption:
Table 17-2. Clock Generator n Activity in Standby Mode
17.7.3
Request for Clock n
present
GENCTRLn.RUNSTDBY
GENCTRLn.OE
Clock Generator n
yes
-
-
active
no
1
1
active
no
1
0
OFF
no
0
1
OFF
no
0
0
OFF
Entering Standby Mode
There may occur a delay when the device is put into Standby, until the power is turned off. This delay is caused by
running Clock Generators: if the Run in Standby bit in the Generator Control register (GENCTRLn.RUNSTDBY) is '0',
GCLK must verify that the clock is turned of properly. The duration of this verification is frequency-dependent.
References:
20. PM – Power Manager
17.8
Additional Features
17.8.1
Peripheral Clock Enable after Reset
The Generic Clock Controller must be able to provide a generic clock to some specific peripherals after a Reset. That
means that the configuration of the Generators and Peripheral Channels after Reset is device-dependent.
Refer to GENCTRLn.SRC for details on GENCTRLn reset.
Refer to PCHCTRLm.SRC for details on PCHCTRLm reset.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
17.9
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
...
0x03
CTRLA
7:0
Reserved
0x04
SYNCBUSY
0x08
...
0x1F
Reserved
0x20
0x24
0x28
0x2C
0x30
0x34
0x38
0x3C
GENCTRL0
GENCTRL1
GENCTRL2
GENCTRL3
GENCTRL4
GENCTRL5
GENCTRL6
GENCTRL7
0x40
GENCTRL8
0x44
...
0x7F
Reserved
0x80
SWRST
PCHCTRL0
7:0
15:8
23:16
31:24
GENCTRL5
GENCTRL4
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
WRTLOCK
CHEN
GENCTRL3
GENCTRL2
GENCTRL1
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
RUNSTDBY
DIVSEL
OE
DIV[7:0]
DIV[15:8]
GENCTRL0
GENCTRL8
GENCTRL7
SWRST
GENCTRL6
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
SRC[4:0]
OOV
IDC
GENEN
GEN[3:0]
...
© 2020 Microchip Technology Inc.
DS60001477C-page 130
SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
...........continued
Offset
Name
Bit Pos.
0x0108
PCHCTRL34
7:0
15:8
23:16
31:24
17.10
WRTLOCK
CHEN
GEN[3:0]
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC writeprotection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to 17.5.8 Register Access Protection.
Some registers are synchronized when read and/or written. Synchronization is denoted by the "Write-Synchronized"
or the "Read-Synchronized" property in each individual register description. For details, refer to 17.6.3
Synchronization.
© 2020 Microchip Technology Inc.
DS60001477C-page 131
SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
17.10.1 Control A
Name:
Offset:
Reset:
Property:
Bit
7
CTRLA
0x00
0x00
PAC Write-Protection, Write-Synchronized
6
Access
Reset
5
4
3
2
1
0
SWRST
R/W
0
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Setting this bit to 1 will reset all registers in the GCLK to their initial state after a Power Reset, except for generic
clocks and associated Generators that have their WRTLOCK bit in PCHCTRLm set to 1.
Refer to GENCTRL Reset Value for details on GENCTRL register reset.
Refer to PCHCTRL Reset Value for details on PCHCTRL register reset.
Due to synchronization, there is a waiting period between setting CTRLA.SWRST and a completed Reset.
CTRLA.SWRST and SYNCBUSY.SWRST will both be cleared when the reset is complete.
Value
Description
0
There is no Reset operation ongoing.
1
A Reset operation is ongoing.
© 2020 Microchip Technology Inc.
DS60001477C-page 132
SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
17.10.2 Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x04
0x00000000
–
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
GENCTRL8
R
0
9
GENCTRL7
R
0
8
GENCTRL6
R
0
7
GENCTRL5
R
0
6
GENCTRL4
R
0
5
GENCTRL3
R
0
4
GENCTRL2
R
0
3
GENCTRL1
R
0
2
GENCTRL0
R
0
1
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 2, 3, 4, 5, 6, 7, 8, 9, 10 – GENCTRLn Generator Control n Synchronization Busy
This bit is cleared when the synchronization of the Generator Control n register (GENCTRLn) between clock domains
is complete, or when clock switching operation is complete.
This bit is set when the synchronization of the Generator Control n register (GENCTRLn) between clock domains is
started.
Bit 0 – SWRST Software Reset Synchronization Busy
This bit is cleared when the synchronization of the CTRLA.SWRST register bit between clock domains is complete.
This bit is set when the synchronization of the CTRLA.SWRST register bit between clock domains is started.
© 2020 Microchip Technology Inc.
DS60001477C-page 133
SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
17.10.3 Generator Control
Name:
Offset:
Reset:
Property:
GENCTRLn
0x20 + n*0x04 [n=0..8]
0x00000106 (GENCTRL0), 0x00000000 (others)
PAC Write-Protection, Write-Synchronized
GENCTRLn controls the settings of Generic Generator n (n=0..8).
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
DIV[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
DIV[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
RUNSTDBY
12
DIVSEL
11
OE
10
OOV
9
IDC
8
GENEN
7
6
5
4
3
1
0
R/W
0
R/W
0
2
SRC[4:0]
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bits 31:16 – DIV[15:0] Division Factor
These bits represent a division value for the corresponding Generator. The actual division factor is dependent on the
state of DIVSEL. The number of relevant DIV bits for each Generator can be seen in this table. Written bits outside of
the specified range will be ignored.
Table 17-3. Division Factor Bits
Generic Clock Generator
Division Factor Bits
Generator 0
Generator 1
Generator 2 - 8
8 division factor bits - DIV[7:0]
16 division factor bits - DIV[15:0]
8 division factor bits - DIV[7:0]
Bit 13 – RUNSTDBY Run in Standby
This bit is used to keep the Generator running in Standby as long as it is configured to output to a dedicated
GCLK_IO pin. If GENCTRLn.OE is zero, this bit has no effect and the generator will only be running if a peripheral
requires the clock.
Value
Description
0
The Generator is stopped in Standby and the GCLK_IO pin state (one or zero) will be dependent on
the setting in GENCTRL.OOV.
1
The Generator is kept running and output to its dedicated GCLK_IO pin during Standby mode.
Bit 12 – DIVSEL Divide Selection
This bit determines how the division factor of the clock source of the Generator will be calculated from DIV. If the
clock source should not be divided, DIVSEL must be 0 and the GENCTRLn.DIV value must be either 0 or 1.
Value
Description
0
The Generator clock frequency equals the clock source frequency divided by GENCTRLn.DIV.
1
The Generator clock frequency equals the clock source frequency divided by 2^(GENCTRLn.DIV+1).
© 2020 Microchip Technology Inc.
DS60001477C-page 134
SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
Bit 11 – OE Output Enable
This bit is used to output the Generator clock output to the corresponding pin (GCLK_IO), as long as GCLK_IO is not
defined as the Generator source in the GENCTRLn.SRC bit field.
Value
Description
0
No Generator clock signal on pin GCLK_IO.
1
The Generator clock signal is output on the corresponding GCLK_IO, unless GCLK_IO is selected as a
generator source in the GENCTRLn.SRC bit field.
Bit 10 – OOV Output Off Value
This bit is used to control the clock output value on pin (GCLK_IO) when the Generator is turned off or the OE bit is
zero, as long as GCLK_IO is not defined as the Generator source in the GENCTRLn.SRC bit field.
Value
Description
0
The GCLK_IO will be LOW when generator is turned off or when the OE bit is zero.
1
The GCLK_IO will be HIGH when generator is turned off or when the OE bit is zero.
Bit 9 – IDC Improve Duty Cycle
This bit is used to improve the duty cycle of the Generator output to 50/50 for odd division factors.
Value
Description
0
Generator output clock duty cycle is not balanced to 50/50 for odd division factors.
1
Generator output clock duty cycle is 50/50.
Bit 8 – GENEN Generator Enable
This bit is used to enable and disable the Generator.
Value
Description
0
Generator is disabled.
1
Generator is enabled.
Bits 4:0 – SRC[4:0] Generator Clock Source Selection
These bits select the Generator clock source, as shown in this table.
Table 17-4. Generator Clock Source Selection
Value
Name
Description
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09-0x1F
XOSC
GCLK_IN
GCLK_GEN1
OSCULP32K
OSC32K
XOSC32K
OSC16M
DFLL48M
DPLL96M
Reserved
XOSC oscillator output
Generator input pad (GCLK_IO)
Generic clock generator 1 output
OSCULP32K oscillator output
OSC32K oscillator output
XOSC32K oscillator output
OSC16M oscillator output
DFLL48M output
DPLL96M output
Reserved for future use
A Power Reset will reset all GENCTRLn registers. the Reset values of the GENCTRLn registers are shown in table
below.
Table 17-5. GENCTRLn Reset Value after a Power Reset
GCLK Generator
Reset Value after a Power Reset
0
others
0x00000106
0x00000000
A User Reset will reset the associated GENCTRL register unless the Generator is the source of a locked Peripheral
Channel (PCHCTRLm.WRTLOCK=1). The reset values of the GENCTRL register are as shown in the table below.
© 2020 Microchip Technology Inc.
DS60001477C-page 135
SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
Table 17-6. GENCTRLn Reset Value after a User Reset
GCLK Generator Reset Value after a User Reset
0
others
0x00000106
No change if the generator is used by a Peripheral Channel m with PCHCTRLm.WRTLOCK=1
else 0x00000000
© 2020 Microchip Technology Inc.
DS60001477C-page 136
SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
17.10.4 Peripheral Channel Control
Name:
Offset:
Reset:
Property:
PCHCTRLm
0x80 + m*0x04 [m=0..34]
0x00000000
PAC Write-Protection
PCHTRLm controls the settings of Peripheral Channel number m (m=0..34).
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
WRTLOCK
R/W
0
6
CHEN
R/W
0
5
4
3
2
1
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
GEN[3:0]
R/W
0
R/W
0
Bit 7 – WRTLOCK Write Lock
After this bit is set to '1', further writes to the PCHCTRLm register will be discarded. The control register of the
corresponding Generator n (GENCTRLn), as assigned in PCHCTRLm.GEN, will also be locked. It can only be
unlocked by a Power Reset.
Note that Generator 0 cannot be locked.
Value
Description
0
The Peripheral Channel register and the associated Generator register are not locked
1
The Peripheral Channel register and the associated Generator register are locked
Bit 6 – CHEN Channel Enable
This bit is used to enable and disable a Peripheral Channel.
Value
Description
0
The Peripheral Channel is disabled
1
The Peripheral Channel is enabled
Bits 3:0 – GEN[3:0] Generator Selection
This bit field selects the Generator to be used as the source of a peripheral clock, as shown in the table below:
Table 17-7. Generator Selection
Value
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
Generic Clock Generator 0
Generic Clock Generator 1
Generic Clock Generator 2
Generic Clock Generator 3
Generic Clock Generator 4
Generic Clock Generator 5
Generic Clock Generator 6
© 2020 Microchip Technology Inc.
DS60001477C-page 137
SAM L21 Family Data Sheet
GCLK - Generic Clock Controller
...........continued
Value
Description
0x7
0x8
0x9 - 0xF
Generic Clock Generator 7
Generic Clock Generator 8
Reserved
Table 17-8. Reset Value after a User Reset or a Power Reset
Reset
PCHCTRLm.GEN
PCHCTRLm.CHEN
PCHCTRLm.WRTLOCK
Power Reset
User Reset
0x0
If WRTLOCK = 0
: 0x0
0x0
If WRTLOCK = 0
: 0x0
0x0
No change
If WRTLOCK = 1: no change
If WRTLOCK = 1: no change
A Power Reset will reset all the PCHCTRLm registers.
A User Reset will reset a PCHCTRL if WRTLOCK=0, or else, the content of that PCHCTRL remains unchanged.
PCHCTRL register Reset values are shown in the table PCHCTRLm Mapping.
Table 17-9. PCHCTRLm Mapping
index(m)
Name
Description
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
GCLK_DFLL48M_REF
GCLK_DPLL
GCLK_DPLL_32K
GCLK_EIC
GCLK_USB
GCLK_EVSYS_CHANNEL_0
GCLK_EVSYS_CHANNEL_1
GCLK_EVSYS_CHANNEL_2
GCLK_EVSYS_CHANNEL_3
GCLK_EVSYS_CHANNEL_4
GCLK_EVSYS_CHANNEL_5
GCLK_EVSYS_CHANNEL_6
GCLK_EVSYS_CHANNEL_7
GCLK_EVSYS_CHANNEL_8
GCLK_EVSYS_CHANNEL_9
GCLK_EVSYS_CHANNEL_10
GCLK_EVSYS_CHANNEL_11
GCLK_SERCOM[0,1,2,3,4]_SLOW
GCLK_SERCOM0_CORE
GCLK_SERCOM1_CORE
GCLK_SERCOM2_CORE
GCLK_SERCOM3_CORE
GCLK_SERCOM4_CORE
GCLK_SERCOM5_SLOW
GCLK_SERCOM5_CORE
GCLK_TCC0, GCLK_TCC1
GCLK_TCC2
GCLK_TC0, GCLK_TC1
GCLK_TC2, GCLK_TC3
GCLK_TC4
GCLK_ADC
GCLK_AC
GCLK_DAC
GCLK_PTC
GCLK_CCL
DFLL48M Reference
FDPLL96M input clock source for reference
FDPLL96M 32kHz clock for FDPLL96M internal lock timer
EIC
USB
EVSYS_CHANNEL_0
EVSYS_CHANNEL_1
EVSYS_CHANNEL_2
EVSYS_CHANNEL_3
EVSYS_CHANNEL_4
EVSYS_CHANNEL_5
EVSYS_CHANNEL_6
EVSYS_CHANNEL_7
EVSYS_CHANNEL_8
EVSYS_CHANNEL_9
EVSYS_CHANNEL_10
EVSYS_CHANNEL_11
SERCOM[0,1,2,3,4]_SLOW
SERCOM0_CORE
SERCOM1_CORE
SERCOM2_CORE
SERCOM3_CORE
SERCOM4_CORE
SERCOM5_SLOW
SERCOM5_CORE
TCC0,TCC1
TCC2
TC0,TC1
TC2,TC3
TC4
ADC
AC
DAC
PTC
CCL
© 2020 Microchip Technology Inc.
DS60001477C-page 138
SAM L21 Family Data Sheet
MCLK – Main Clock
18.
MCLK – Main Clock
18.1
Overview
The Main Clock (MCLK) controls the synchronous clock generation of the device.
Using a clock provided by the Generic Clock Module (GCLK_MAIN), the Main Clock Controller provides synchronous
system clocks to the CPU and the modules connected to the AHBx and the APBx bus. The synchronous system
clocks are divided into a number of clock domains. Each clock domain can run at different frequencies, enabling the
user to save power by running peripherals at a relatively low clock frequency, while maintaining high CPU
performance or vice versa. In addition, the clock can be masked for individual modules, enabling the user to minimize
power consumption.
18.2
Features
•
•
•
18.3
Generates CPU, AHB, and APB system clocks
– Clock source and division factor from GCLK
– Clock prescaler with 1x to 128x division
Safe run-time clock switching from GCLK
Module-level clock gating through maskable peripheral clocks
Block Diagram
Figure 18-1. MCLK Block Diagram
CLK_APBx
GCLK
GCLK_MAIN
MAIN
CLOCK CONTROLLER
CLK_AHBx
PERIPHERALS
CLK_CPU
CPU
18.4
Signal Description
Not applicable.
18.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
18.5.1
I/O Lines
Not applicable.
© 2020 Microchip Technology Inc.
DS60001477C-page 139
SAM L21 Family Data Sheet
MCLK – Main Clock
18.5.2
Power Management
The MCLK will operate in all sleep modes if a synchronous clock is required in these modes.
References:
20. PM – Power Manager
18.5.3
Clocks
The MCLK bus clock (CLK_MCLK_APB) can be enabled and disabled in the Main Clock module, and the default
state of CLK_MCLK_APB can be found in the Peripheral Clock Masking section. If this clock is disabled, it can only
be re-enabled by a reset.
The Generic Clock GCLK_MAIN is required to generate the Main Clocks. GCLK_MAIN is configured in the Generic
Clock Controller, and can be re-configured by the user if needed.
References:
17. GCLK - Generic Clock Controller
18.6.2.6 Peripheral Clock Masking
18.5.3.1 Main Clock
The main clock GCLK_MAIN is the common source for the synchronous clocks. This is fed into the common 8-bit
prescaler that is used to generate synchronous clocks to the CPU, AHBx, and APBx modules.
18.5.3.2 CPU Clock
The CPU clock (CLK_CPU) is routed to the CPU. Halting the CPU clock inhibits the CPU from executing instructions.
18.5.3.3 APBx and AHBx Clock
The APBx clocks (CLK_APBx) and the AHBx clocks (CLK_AHBx) are the root clock source used by modules
requiring a clock on the APBx and the AHBx bus. These clocks are always synchronous to the CPU clock, but can be
divided by a prescaler, and can run even when the CPU clock is turned off in sleep mode. A clock gater is inserted
after the common APB clock to gate any APBx clock of a module on APBx bus, as well as the AHBx clock.
18.5.3.4 Clock Domains
The device has these synchronous clock domains:
•
•
•
CPU synchronous clock domain (CPU Clock Domain). Frequency is fCPU.
Low Power synchronous clock domain (LP Clock Domain). Frequency is fLP.
Backup synchronous clock domain. (BUP Clock Domain). Frequency is fBUP.
See the references for the clock domain partitioning. Refer to the Maximum Clock Frequencies in the Electrical
Characterization section for maximum frequencies in each performance level.
References:
18.6.2.6 Peripheral Clock Masking
18.5.4
DMA
Not applicable.
18.5.5
Interrupts
The interrupt request line is connected to the Interrupt Controller. Using the MCLK interrupt requires the Interrupt
Controller to be configured first.
18.5.6
Events
Not applicable.
18.5.7
Debug Operation
When the CPU is halted in debug mode, the MCLK continues normal operation. In sleep mode, the clocks generated
from the MCLK are kept running to allow the debugger accessing any module. As a consequence, power
measurements are incorrect in debug mode.
© 2020 Microchip Technology Inc.
DS60001477C-page 140
SAM L21 Family Data Sheet
MCLK – Main Clock
18.5.8
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC), except for
the following registers:
•
Interrupt Flag register (INTFLAG)
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
References:
13. PAC - Peripheral Access Controller
18.5.9
Analog Connections
Not applicable.
18.6
Functional Description
18.6.1
Principle of Operation
The GCLK_MAIN clock signal from the GCLK module is the source for the main clock, which in turn is the common
root for the synchronous clocks for the CPU, APBx, and AHBx modules. The GCLK_MAIN is divided by an 8-bit
prescaler. Each of the derived clocks can run from any divided or undivided main clock, ensuring synchronous clock
sources for each clock domain. Each clock domain (CPU, LP) can be changed on the fly to respond to variable load
in the application as long as fCPU ≥ fLP ≥ fBUP. The clocks for each module in a clock domain can be masked
individually to avoid power consumption in inactive modules. Depending on the sleep mode, some clock domains can
be turned off.
18.6.2
Basic Operation
18.6.2.1 Initialization
After a Reset, the default clock source of the GCLK_MAIN clock is started and calibrated before the CPU starts
running. The GCLK_MAIN clock is selected as the main clock without any prescaler division.
By default, only the necessary clocks are enabled.
References:
18.6.2.6 Peripheral Clock Masking
18.6.2.2 Enabling, Disabling, and Resetting
The MCLK module is always enabled and cannot be reset.
18.6.2.3 Selecting the Main Clock Source
Refer to the Generic Clock Controller description for details on how to configure the clock source of the GCLK_MAIN
clock.
18.6.2.4 Selecting the Synchronous Clock Division Ratio
The main clock CLK_MAIN feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By
default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU
clock domain by writing the Division (DIV) bits in the CPU Clock Division register CPUDIV, resulting in a CPU clock
domain frequency determined by this equation:
���� =
�����
������
If the application attempts to write forbidden values in CPUDIV, and LPDIV registers, the registers are written but
these bad values are not used and a violation is reported to the PAC module.
Division bits (DIV) can be written without halting or disabling peripheral modules. Writing DIV bits allows a new clock
setting to be written to all synchronous clocks belonging to the corresponding clock domain at the same time.
© 2020 Microchip Technology Inc.
DS60001477C-page 141
SAM L21 Family Data Sheet
MCLK – Main Clock
Figure 18-2. Synchronous Clock Selection and Prescaler
Sleep Controller
Sleep mode
Backup
Clock Domain: fBUP
MASK
Clock
gate
CLK_APBx
gate
Clock
gate
Clock
Clock
gate
clk_apb_ipn
clk_apb_ip1
clk_apb_ip0
Clock
gate
Clock
gate
Clock
gate
clk_apb_ipn
clk_apb_ip1
clk_apb_ip0
Clock
gate
Clock
gate
Clock
gate
clk_ahb_ipn
clk_ahb_ip1
clk_ahb_ip0
Clock
gate
clk_apb_ipn
clk_apb_ip1
clk_apb_ip0
gate
Clock
gate
Clock
Clock
gate
clk_ahb_ipn
clk_ahb_ip1
clk_ahb_ip0
PERIPHERALS
BUPDIV
MASK
Clock
gate
CLK_APBx
MASK
Clock
gate
CLK_AHBx
Clock
gate
CLK_APB_HS
Low Power
Clock Domain: fLP
PERIPHERALS
LPDIV
MASK
MASK
GCLK
GCLKMAIN
Prescaler
Clock
gate
CLK_AHB_HS
Clock
gate
CLK_CPU
CPU
Clock Domain: fCPU
PERIPHERALS
CPU
CPUDIV
References:
46. Electrical Characteristics
13. PAC - Peripheral Access Controller
18.6.2.5 Clock Ready Flag
There is a slight delay between writing to CPUDIV, LPDIV until the new clock settings become effective.
During this interval, the Clock Ready flag in the Interrupt Flag Status and Clear register (INTFLAG.CKRDY) will return
zero when read. If CKRDY in the INTENSET register is set to '1', the Clock Ready interrupt will be triggered when the
new clock setting is effective. The clock settings (CLKCFG) must not be re-written while INTFLAG. CKRDY reads '0'.
The system may become unstable or hang, and a violation is reported to the PAC module.
References:
13. PAC - Peripheral Access Controller
18.6.2.6 Peripheral Clock Masking
It is possible to disable/enable the AHB or APB clock for a peripheral by writing the corresponding bit in the Clock
Mask registers (APBxMASK) to '0'/'1'. The default state of the peripheral clocks is shown here.
Table 18-1. Peripheral Clock Default State
CPU Clock Domain
Peripheral Clock
Default State
CLK_BRIDGE_B_AHB
Enabled
© 2020 Microchip Technology Inc.
DS60001477C-page 142
SAM L21 Family Data Sheet
MCLK – Main Clock
...........continued
CPU Clock Domain
Peripheral Clock
Default State
CLK_DSU_AHB
Enabled
CLK_DSU_APB
Enabled
CLK_USB_AHB
Enabled
CLK_USB_APB
Enabled
CLK_NVMCTRL_AHB
Enabled
CLK_NVMCTRL_APB
Enabled
Backup Clock Domain
Peripheral Clock
Default State
CLK_OSC32KCTRL_APB
Enabled
CLK_PM_APB
Enabled
CLK_SUPC_APB
Enabled
CLK_RSTC_APB
Enabled
CLK_RTC_APB
Enabled
Low Power Clock Domain
Peripheral Clock
Default State
CLK_AC_APB
Enabled
CLK_ADC_APB
Enabled
CLK_AES_APB
Enabled
CLK_BRIDGE_A_AHB
Enabled
CLK_BRIDGE_C_AHB
Enabled
CLK_BRIDGE_D_AHB
Enabled
CLK_BRIDGE_E_AHB
Enabled
CLK_CCL_APB
Enabled
CLK_DAC_APB
Enabled
CLK_DMAC_AHB
Enabled
CLK_EIC_APB
Enabled
CLK_EVSYS_APB
Enabled
CLK_GCLK_APB
Enabled
CLK_MCLK_APB
Enabled
CLK_OPAMP_APB
Enabled
CLK_OSCCTRL_APB
Enabled
CLK_PAC_AHB
Enabled
CLK_PAC_APB
Enabled
© 2020 Microchip Technology Inc.
DS60001477C-page 143
SAM L21 Family Data Sheet
MCLK – Main Clock
...........continued
Low Power Clock Domain
Peripheral Clock
Default State
CLK_PORT_APB
Enabled
CLK_PTC_APB
Enabled
CLK_SERCOM0_APB
Enabled
CLK_SERCOM1_APB
Enabled
CLK_SERCOM2_APB
Enabled
CLK_SERCOM3_APB
Enabled
CLK_SERCOM4_APB
Enabled
CLK_SERCOM5_APB
Enabled
CLK_TCC0_APB
Enabled
CLK_TCC1_APB
Enabled
CLK_TCC2_APB
Enabled
CLK_TC0_APB
Enabled
CLK_TC1_APB
Enabled
CLK_TC2_APB
Enabled
CLK_TC3_APB
Enabled
CLK_TC4_APB
Enabled
CLK_TRNG_APB
Enabled
CLK_WDT_APB
Enabled
When the APB clock is not provided to a module, its registers cannot be read or written. The module can be reenabled later by writing the corresponding mask bit to '1'.
A module may be connected to several clock domains (for instance, AHB and APB), in which case it will have several
mask bits.
Note that clocks should only be switched off if it is certain that the module will not be used: Switching off the clock for
the NVM Controller (NVMCTRL) will cause a problem if the CPU needs to read from the Flash Memory. Switching off
the clock to the MCLK module (which contains the mask registers) or the corresponding APBx bridge, will make it
impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset.
18.6.3
DMA Operation
Not applicable.
18.6.4
Interrupts
The peripheral has the following interrupt sources:
•
Clock Ready (CKRDY): indicates that CPU clocks are ready. This interrupt is a synchronous wake-up source.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be enabled individually by writing a
'1' to the corresponding enabling bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to
the corresponding clearing bit in the Interrupt Enable Clear (INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, the interrupt is disabled or the peripheral is reset. An
interrupt flag is cleared by writing a '1' to the corresponding bit in the INTFLAG register. Each peripheral can have
© 2020 Microchip Technology Inc.
DS60001477C-page 144
SAM L21 Family Data Sheet
MCLK – Main Clock
one interrupt request line per interrupt source or one common interrupt request line for all the interrupt sources. If the
peripheral has one common interrupt request line for all the interrupt sources, the user must read the INTFLAG
register to determine which interrupt condition is present.
References:
20. PM – Power Manager
20.6.3.3 Sleep Mode Controller
12.4.1 Overview
18.6.5
Events
Not applicable.
18.6.6
Sleep Mode Operation
In IDLE sleep mode, the MCLK is still running on the selected main clock.
In STANDBY sleep mode, the MCLK is frozen if no synchronous clock is required.
© 2020 Microchip Technology Inc.
DS60001477C-page 145
SAM L21 Family Data Sheet
MCLK – Main Clock
18.7
Register Summary - MCLK
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
...
0x0F
CTRLA
INTENCLR
INTENSET
INTFLAG
CPUDIV
LPDIV
BUPDIV
7:0
7:0
7:0
7:0
7:0
7:0
7:0
0x10
AHBMASK
0x14
CPUDIV[7:0]
LPDIV[7:0]
BUPDIV[7:0]
Reserved
APBAMASK
0x18
APBBMASK
0x1C
APBCMASK
0x20
APBDMASK
0x24
APBEMASK
18.8
CKRDY
CKRDY
CKRDY
7:0
15:8
23:16
31:24
Reserved
Reserved
PAC
DSU
Reserved
APBE
USB
APBD
DMAC
APBC
Reserved
APBB
Reserved
APBA
NVMCTRL
7:0
WDT
GCLK
SUPC
OSC32KCTR
L
OSCCTRL
RSTC
MCLK
PM
PORT
EIC
RTC
NVMCTRL
DSU
USB
SERCOM2
TC2
SERCOM1
TC1
SERCOM0
TC0
TC4
SERCOM5
EVSYS
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
Reserved[3:0]
Reserved[11:4]
Reserved[19:12]
Reserved[4:0]
TCC2
TCC1
TRNG
TCC0
AES
CCL
OPAMP
PTC
Reserved[12:5]
Reserved[20:13]
Reserved[28:21]
SERCOM4
SERCOM3
DAC
TC3
AC
ADC
Reserved[6:0]
Reserved[14:7]
Reserved[22:15]
Reserved[30:23]
PAC
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers can be write-protected optionally by the Peripheral Access Controller (PAC). This is denoted by the
property "PAC Write-Protection" in each individual register description. Refer to the 18.5.8 Register Access
Protection for details.
© 2020 Microchip Technology Inc.
DS60001477C-page 146
SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.1
Control A
Name:
Offset:
Reset:
Property:
CTRLA
0x00
0x00
PAC Write-Protection
All bits in this register are reserved.
Bit
7
6
5
4
3
2
1
0
Access
Reset
© 2020 Microchip Technology Inc.
DS60001477C-page 147
SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.2
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x01
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
7
6
Access
Reset
5
4
3
2
1
0
CKRDY
R/W
0
Bit 0 – CKRDY Clock Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Clock Ready Interrupt Enable bit and the corresponding interrupt request.
Value
Description
0
The Clock Ready interrupt is disabled.
1
The Clock Ready interrupt is enabled and will generate an interrupt request when the Clock Ready
Interrupt Flag is set.
© 2020 Microchip Technology Inc.
DS60001477C-page 148
SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.3
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x02
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
7
6
5
4
3
2
1
Access
Reset
0
CKRDY
R/W
0
Bit 0 – CKRDY Clock Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Clock Ready Interrupt Enable bit and enable the Clock Ready interrupt.
Value
Description
0
The Clock Ready interrupt is disabled.
1
The Clock Ready interrupt is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 149
SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.4
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x03
0x01
–
6
Access
Reset
5
4
3
2
1
0
CKRDY
R/W
1
Bit 0 – CKRDY Clock Ready
This flag is cleared by writing a '1' to the flag.
This flag is set when the synchronous CPU, APBx, and AHBx clocks have frequencies as indicated in the CLKCFG
registers and will generate an interrupt if INTENCLR/SET.CKRDY is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Clock Ready interrupt flag.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.5
CPU Clock Division
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
CPUDIV
0x04
0x01
PAC Write-Protection
7
6
5
R/W
0
R/W
0
R/W
0
4
3
CPUDIV[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
1
Bits 7:0 – CPUDIV[7:0] CPU Clock Division Factor
These bits define the division ratio of the main clock prescaler related to the CPU clock domain.
To ensure correct operation, frequencies must be selected so that FCPU≥ FLP (i.e. LPDIV ≥CPUDIV).
Frequencies must never exceed the specified maximum frequency for each clock domain.
Value
Name
Description
0x01
DIV1
Divide by 1
0x02
DIV2
Divide by 2
0x04
DIV4
Divide by 4
0x08
DIV8
Divide by 8
0x10
DIV16
Divide by 16
0x20
DIV32
Divide by 32
0x40
DIV64
Divide by 64
0x80
DIV128
Divide by 128
others
Reserved
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.6
Low Power Clock Division
Name:
Offset:
Reset:
Property:
Bit
7
LPDIV
0x05
0x01
PAC Write-Protection
6
5
4
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
1
LPDIV[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – LPDIV[7:0] Low-Power Clock Division Factor
These bits define the division ratio of the main clock prescaler (2n) related to the Low Power clock domain. To ensure
correct operation, frequencies must be selected so that FCPU ≥ FLP ≥ F_BUP (i.e. BUPDIV ≥ LPDIV ≥ CPUDIV). Also,
frequencies must never exceed the specified maximum frequency for each clock domain.
Refer to the Maximum Clock Frequencies in the Electrical Characterization section for maximum frequencies in each
performance level.
Value
Name
Description
0x01
DIV1
Divide by 1
0x02
DIV2
Divide by 2
0x04
DIV4
Divide by 4
0x08
DIV8
Divide by 8
0x10
DIV16
Divide by 16
0x20
DIV32
Divide by 32
0x40
DIV64
Divide by 64
0x80
DIV128
Divide by 128
others
Reserved
© 2020 Microchip Technology Inc.
DS60001477C-page 152
SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.7
Backup Clock Division
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
BUPDIV
0x06
0x01
PAC Write-Protection
7
6
5
R/W
0
R/W
0
R/W
0
4
3
BUPDIV[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – BUPDIV[7:0] Backup Clock Division Factor
These bits define the division ratio of the main clock prescaler (2n) related to the Backup clock domain. To ensure
correct operation, frequencies must be selected so that FCPU ≥ F_BUP (i.e. BUPDIV ≥ CPUDIV). Also, frequencies
must never exceed the specified maximum frequency for each clock domain.
Refer to the Maximum Clock Frequencies in the Electrical Characterization section for maximum frequencies in each
performance level.
Value
Name
Description
0x01
DIV1
Divide by 1
0x02
DIV2
Divide by 2
0x04
DIV4
Divide by 4
0x08
DIV8
Divide by 8
0x10
DIV16
Divide by 16
0x20
DIV32
Divide by 32
0x40
DIV64
Divide by 64
0x80
DIV128
Divide by 128
others
Reserved
© 2020 Microchip Technology Inc.
DS60001477C-page 153
SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.8
AHB Mask
Name:
Offset:
Reset:
Property:
Bit
AHBMASK
0x10
0x000FFFFF
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
PAC
R
1
13
Reserved
R
1
12
USB
R/W
1
11
DMAC
R/W
1
10
Reserved
R
1
9
Reserved
R
1
8
NVMCTRL
R/W
1
7
Reserved
R
1
6
Reserved
R
1
5
DSU
R/W
1
4
APBE
R/W
1
3
APBD
R/W
1
2
APBC
R/W
1
1
APBB
R/W
1
0
APBA
R/W
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 14 – PAC PAC AHB Clock Enable
Value
Description
0
The AHB clock for the PAC is stopped.
1
The AHB clock for the PAC is enabled.
Bits 13,10,9,7,6 – Reserved Reserved bits
Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved
bits to their reset value. If no reset value is given, write 0.
Bit 12 – USB USB AHB Clock Enable
Value
Description
0
The AHB clock for the USB is stopped.
1
The AHB clock for the USB is enabled.
Bit 11 – DMAC DMAC AHB Clock Enable
Value
Description
0
The AHB clock for the DMAC is stopped.
1
The AHB clock for the DMAC is enabled.
Bit 8 – NVMCTRL NVMCTRL AHB Clock Enable
Value
Description
0
The AHB clock for the NVMCTRL is stopped.
1
The AHB clock for the NVMCTRL is enabled.
Bit 5 – DSU DSU AHB Clock Enable
Value
Description
0
The AHB clock for the DSU is stopped.
1
The AHB clock for the DSU is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 154
SAM L21 Family Data Sheet
MCLK – Main Clock
Bit 4 – APBE APBE AHB Clock Enable
Value
Description
0
The AHB clock for the APBE is stopped.
1
The AHB clock for the APBE is enabled.
Bit 3 – APBD APBD AHB Clock Enable
Value
Description
0
The AHB clock for the APBD is stopped.
1
The AHB clock for the APBD is enabled
Bit 2 – APBC APBC AHB Clock Enable
Value
Description
0
The AHB clock for the APBC is stopped.
1
The AHB clock for the APBC is enabled
Bit 1 – APBB APBB AHB Clock Enable
Value
Description
0
The AHB clock for the APBB is stopped.
1
The AHB clock for the APBB is enabled.
Bit 0 – APBA APBA AHB Clock Enable
Value
Description
0
The AHB clock for the APBA is stopped.
1
The AHB clock for the APBA is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 155
SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.9
APBA Mask
Name:
Offset:
Reset:
Property:
APBAMASK
0x14
0x00001FFF
PAC Write-Protection
Bit
31
30
29
Access
Reset
R
0
R
0
R
0
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
Access
Reset
R
0
14
13
Reserved[3:0]
R
R
0
0
Bit
Access
Reset
7
WDT
R
1
6
GCLK
R/W
1
5
SUPC
R/W
1
28
27
Reserved[19:12]
R
R
0
0
26
25
24
R
0
R
0
R
0
20
19
Reserved[11:4]
R
R
0
0
18
17
16
R
0
R
0
R
0
11
10
PORT
R
1
9
EIC
R
1
8
RTC
R
1
3
OSCCTRL
R/W
1
2
RSTC
R/W
1
1
MCLK
R/W
1
0
PM
R/W
1
12
R
1
4
OSC32KCTRL
R/W
1
Bits 31:12 – Reserved[19:0] For future use
Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved
bits to their reset value. If no reset value is given, write 0.
Bit 10 – PORT PORT APBA Clock Enable
Value
Description
0
The APBA clock for the PORT is stopped.
1
The APBA clock for the PORT is enabled.
Bit 9 – EIC EIC APBA Clock Enable
Value
Description
0
The APBA clock for the EIC is stopped.
1
The APBA clock for the EIC is enabled.
Bit 8 – RTC RTC APBA Clock Enable
Value
Description
0
The APBA clock for the RTC is stopped.
1
The APBA clock for the RTC is enabled.
Bit 7 – WDT WDT APBA Clock Enable
Value
Description
0
The APBA clock for the WDT is stopped.
1
The APBA clock for the WDT is enabled.
Bit 6 – GCLK GCLK APBA Clock Enable
Value
Description
0
The APBA clock for the GCLK is stopped.
1
The APBA clock for the GCLK is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 156
SAM L21 Family Data Sheet
MCLK – Main Clock
Bit 5 – SUPC SUPC APBA Clock Enable
Value
Description
0
The APBA clock for the SUPC is stopped.
1
The APBA clock for the SUPC is enabled.
Bit 4 – OSC32KCTRL OSC32KCTRL APBA Clock Enable
Value
Description
0
The APBA clock for the OSC32KCTRL is stopped.
1
The APBA clock for the OSC32KCTRL is enabled.
Bit 3 – OSCCTRL OSCCTRL APBA Clock Enable
Value
Description
0
The APBA clock for the OSCCTRL is stopped.
1
The APBA clock for the OSCCTRL is enabled.
Bit 2 – RSTC RSTC APBA Clock Enable
Value
Description
0
The APBA clock for the RSTC is stopped.
1
The APBA clock for the RSTC is enabled.
Bit 1 – MCLK MCLK APBA Clock Enable
Value
Description
0
The APBA clock for the MCLK is stopped.
1
The APBA clock for the MCLK is enabled.
Bit 0 – PM PM APBA Clock Enable
Value
Description
0
The APBA clock for the PM is stopped.
1
The APBA clock for the PM is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 157
SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.10 APBB Mask
Name:
Offset:
Reset:
Property:
APBBMASK
0x18
0x00000017
PAC Write-Protection
Bit
31
30
29
Access
Reset
R
0
R
0
R
0
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
Access
Reset
R
0
R
0
5
Reserved[4:0]
R
0
28
27
Reserved[28:21]
R
R
0
0
26
25
24
R
0
R
0
R
0
20
19
Reserved[20:13]
R
R
0
0
18
17
16
R
0
R
0
R
0
12
11
Reserved[12:5]
R
R
0
0
10
9
8
R
0
R
0
R
0
2
NVMCTRL
R/W
1
1
DSU
R/W
1
0
USB
R/W
1
4
3
R
1
R
0
Bits 31:3 – Reserved[28:0] Reserved bits
Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved
bits to their reset value. If no reset value is given, write 0.
Bit 2 – NVMCTRL NVMCTRL APBB Clock Enable
Value
Description
0
The APBB clock for the NVMCTRL is stopped
1
The APBB clock for the NVMCTRL is enabled
Bit 1 – DSU DSU APBB Clock Enable
Value
Description
0
The APBB clock for the DSU is stopped
1
The APBB clock for the DSU is enabled
Bit 0 – USB USB APBB Clock Enable
Value
Description
0
The APBB clock for the USB is stopped
1
The APBB clock for the USB is enabled
© 2020 Microchip Technology Inc.
DS60001477C-page 158
SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.11 APBC Mask
Name:
Offset:
Reset:
Property:
Bit
APBCMASK
0x1C
0x0000 7FFF
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
TRNG
R
1
13
AES
R
1
12
DAC
R
1
11
TC3
R
1
10
TC2
R
1
9
TC1
R
1
8
TC0
R
1
7
TCC2
R
1
6
TCC1
R/W
1
5
TCC0
R/W
1
4
SERCOM4
R/W
1
3
SERCOM3
R/W
1
2
SERCOM2
R/W
1
1
SERCOM1
R/W
1
0
SERCOM0
R/W
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 14 – TRNG TRNG APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TRNG is stopped.
1
The APBC clock for the TRNG is enabled.
Bit 13 – AES AES APBC Mask Clock Enable
Value
Description
0
The APBC clock for the AES is stopped.
1
The APBC clock for the AES is enabled.
Bit 12 – DAC DAC APBC Mask Clock Enable
Value
Description
0
The APBC clock for the DAC is stopped.
1
The APBC clock for the DAC is enabled.
Bit 11 – TC3 TC3 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC3 is stopped.
1
The APBC clock for the TC3 is enabled.
Bit 10 – TC2 TC2 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC2 is stopped.
1
The APBC clock for the TC2 is enabled.
Bit 9 – TC1 TC1 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC1 is stopped.
© 2020 Microchip Technology Inc.
DS60001477C-page 159
SAM L21 Family Data Sheet
MCLK – Main Clock
Value
1
Description
The APBC clock for the TC1 is enabled.
Bit 8 – TC0 TC0 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TC0 is stopped.
1
The APBC clock for the TC0 is enabled.
Bit 7 – TCC2 TCC2 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TCC2 is stopped.
1
The APBC clock for the TCC2 is enabled.
Bit 6 – TCC1 TCC1 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TCC1 is stopped.
1
The APBC clock for the TCC1 is enabled.
Bit 5 – TCC0 TCC0 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the TCC0 is stopped.
1
The APBC clock for the TCC0 is enabled.
Bit 4 – SERCOM4 SERCOM4 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM4 is stopped.
1
The APBC clock for the SERCOM4 is enabled.
Bit 3 – SERCOM3 SERCOM3 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM3 is stopped.
1
The APBC clock for the SERCOM3 is enabled.
Bit 2 – SERCOM2 SERCOM2 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM2 is stopped.
1
The APBC clock for the SERCOM2 is enabled.
Bit 1 – SERCOM1 SERCOM1 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM1 is stopped.
1
The APBC clock for the SERCOM1 is enabled.
Bit 0 – SERCOM0 SERCOM0 APBC Mask Clock Enable
Value
Description
0
The APBC clock for the SERCOM0 is stopped.
1
The APBC clock for the SERCOM0 is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 160
SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.12 APBD Mask
Name:
Offset:
Reset:
Property:
Bit
APBDMASK
0x20
0x000000FF
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
CCL
R
1
6
OPAMP
R/W
1
5
PTC
R/W
1
4
AC
R/W
1
3
ADC
R/W
1
2
TC4
R/W
1
1
SERCOM5
R/W
1
0
EVSYS
R/W
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit 7 – CCL CCL APBD Clock Enable
Value
Description
0
The APBD clock for the CCL is stopped.
1
The APBD clock for the CCL is enabled.
Bit 6 – OPAMP OPAMP APBD Clock Enable
Value
Description
0
The APBD clock for the OPAMP is stopped.
1
The APBD clock for the OPAMP is enabled.
Bit 5 – PTC PTC APBD Clock Enable
Value
Description
0
The APBD clock for the PTC is stopped.
1
The APBD clock for the PTC is enabled.
Bit 4 – AC AC APBD Clock Enable
Value
Description
0
The APBD clock for the AC is stopped.
1
The APBD clock for the AC is enabled.
Bit 3 – ADC ADC APBD Clock Enable
Value
Description
0
The APBD clock for the ADC is stopped.
1
The APBD clock for the ADC is enabled.
Bit 2 – TC4 TC4 APBD Clock Enable
Value
Description
0
The APBD clock for the TC4 is stopped.
1
The APBD clock for the TC4 is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 161
SAM L21 Family Data Sheet
MCLK – Main Clock
Bit 1 – SERCOM5 SERCOM5 APBD Clock Enable
Value
Description
0
The APBD clock for the SERCOM5 is stopped.
1
The APBD clock for the SERCOM5 is enabled.
Bit 0 – EVSYS EVSYS APBD Clock Enable
Value
Description
0
The APBD clock for the EVSYS is stopped.
1
The APBD clock for the EVSYS is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 162
SAM L21 Family Data Sheet
MCLK – Main Clock
18.8.13 APBE Mask
Name:
Offset:
Reset:
Property:
APBEMASK
0x24
0x0000 000D
PAC Write-Protection
Bit
31
30
29
Access
Reset
R
0
R
0
R
0
Bit
23
22
21
Access
Reset
R
0
R
0
R
0
Bit
15
14
13
Access
Reset
R
0
R
0
R
0
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
28
27
Reserved[30:23]
R
R
0
0
26
25
24
R
0
R
0
R
0
20
19
Reserved[22:15]
R
R
0
0
18
17
16
R
0
R
0
R
0
12
11
Reserved[14:7]
R
R
0
0
10
9
8
R
0
R
0
R
0
3
2
1
R
1
R
1
R
0
0
PAC
R/W
1
4
Reserved[6:0]
R
0
Bits 31:1 – Reserved[30:0] For future use
Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved
bits to their reset value. If no reset value is given, write 0.
Bit 0 – PAC PAC APBE Clock Enable
Value
Description
0
The APBE clock for the PAC is stopped.
1
The APBE clock for the PAC is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 163
SAM L21 Family Data Sheet
RSTC – Reset Controller
19.
RSTC – Reset Controller
19.1
Overview
The Reset Controller (RSTC) manages the reset of the microcontroller. It issues a microcontroller reset, sets the
device to its initial state and allows the reset source to be identified by software.
19.2
Features
•
•
•
19.3
Reset the microcontroller and set it to an initial state according to the reset source
Reset cause register for reading the reset source from the application code
Multiple reset sources
– Power supply reset sources: POR, BOD12, BOD33
– User reset sources: External reset (RESET), Watchdog reset, and System Reset Request
Block Diagram
Figure 19-1. Reset System
RESET SOURCES
RESET CONTROLLER
BOD12
BOD33
RTC
32kHz clock sources
WDT with ALWAYSON
GCLK with WRTLOCK
POR
Debug Logic
RESET
WDT
Other Modules
CPU
BACKUP EXIT
RTC
RCAUSE
BKUPEXIT
BBPS
SUPC
EXTWAKEx
External Wakeup
Detector
OSC32KCTRL
19.4
Signal Description
Signal Name
Type
Description
RESET
Digital input
External reset
© 2020 Microchip Technology Inc.
DS60001477C-page 164
SAM L21 Family Data Sheet
RSTC – Reset Controller
...........continued
Signal Name
Type
Description
EXTWAKE[7:0]
Digital input
External wakeup for backup mode
One signal can be mapped on several pins.
References:
7. I/O Multiplexing and Considerations
19.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
19.5.1
I/O Lines
Using the External Wake-up Lines requires the I/O pins to be configured in input mode before entering backup mode.
External Wake-up function is active only in backup mode.
CAUTION
19.5.2
The EXTWAKE pins can not wake up the device after it has entered Battery Backup Mode, as the I/O pin
configuration is lost in this mode.
Power Management
The Reset Controller module is always on.
19.5.3
Clocks
The RSTC bus clock (CLK_RSTC_APB) can be enabled and disabled in the Main Clock Controller.
A 32KHz clock is required to clock the RSTC if the debounce counter of the external wake-up detector is used.
References:
MCLK - Main Clock
Peripheral Clock Masking
OSC32KCTRL
19.5.4
DMA
Not applicable.
19.5.5
Interrupts
Not applicable.
19.5.6
Events
Not applicable.
19.5.7
Debug Operation
When the CPU is halted in debug mode, the RSTC continues normal operation.
19.5.8
Register Access Protection
All registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC).
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply
for accesses through an external debugger.
© 2020 Microchip Technology Inc.
DS60001477C-page 165
SAM L21 Family Data Sheet
RSTC – Reset Controller
References:
13. PAC - Peripheral Access Controller
19.5.9
Analog Connections
Not applicable.
19.6
Functional Description
19.6.1
Principle of Operation
The Reset Controller collects the various Reset sources and generates Reset for the device.
19.6.2
Basic Operation
19.6.2.1 Initialization
After a power-on Reset, the RSTC is enabled and the Reset Cause (RCAUSE) register indicates the POR source.
19.6.2.2 Enabling, Disabling, and Resetting
The RSTC module is always enabled.
19.6.2.3 External Wake-Up Detector
The External Wake-up detector is activated in Backup Sleep Mode only. In all other sleep modes, the debounce
counter is stopped. Before entering Backup Mode, each external wake-up pin can be enabled by configuring the
Wake-up Enable (WKEN) register. The corresponding I/O lines must also be configured in input mode using port
configuration (PORT). The wake-up level can also be configured by using the Wake-up Polarity (WKPOL) register. If
WKPOLx is written to 0 (default value), the input wake-up pin is active low. If WKPOLx=1 the pin is active high. All the
resulting signals are wired-ORed to trigger a debounce counter which can be programmed with the Wake-up
Debounce Configuration (WKDBCONF) register.
In Backup Mode, the debounce counter is running if at least one external wake-up pin is enabled and the
WKDBCONF is configured to any other value than OFF. It is clocked by the OSCULP32K clock provided by the
OSC32KCTRL module. If an enabled wake-up pin is asserted for a time longer than the debouncing period, the
BKUPEXIT.EXTWAKE bit is set, and the value of each enable external wake-up pin is stored in the WKCAUSE
register. This will allow the application to identify the external wake-up source when booting up from a backup exit
reset. A backup reset is then applied. Refer to 19.6.2.4 Reset Causes and Effects for details.
Figure 19-2. External Wake-up Block Diagram
BKUPEXIT
EXTWAKE
EXTWAKEx
Polarity
WKPOLx WKENx WKCAUSEx
Debouncer
EXTWAKEx
Polarity
WKPOLx WKENx WKCAUSEx
WKDBCONF
32KHz
© 2020 Microchip Technology Inc.
DS60001477C-page 166
SAM L21 Family Data Sheet
RSTC – Reset Controller
19.6.2.4 Reset Causes and Effects
The latest Reset cause is available in RCAUSE register, and can be read during the application boot sequence in
order to determine proper action.
These are the groups of Reset sources:
•
•
•
Power supply Reset: Resets caused by an electrical issue. It covers POR and BODs Resets
User Reset: Resets caused by the application. It covers external Resets, system Reset requests and watchdog
Resets
Backup reset: Resets caused by a Backup Mode exit condition
The following table lists the parts of the device that are reset, depending on the Reset type.
Table 19-1. Effects of the Different Reset Causes
Power Supply Reset
User Reset
Backup Reset
POR, BOD33 BOD12 External Reset WDT Reset,
System Reset
Request,
RTC, EXTWAKE,
BBPS
RTC, OSC32KCTRL,
Y
RSTC, CTRLA.IORET bit of
PM
N
N
N
N
GCLK with WRTLOCK
Y
Y
N
N
Y
Debug logic
Y
Y
Y
N
Y
Others
Y
Y
Y
Y
Y
The external Reset is generated when pulling the RESET pin low.
The POR, BOD12, and BOD33 Reset sources are generated by their corresponding module in the Supply Controller
Interface (SUPC).
The WDT Reset is generated by the Watchdog Timer.
The System Reset Request is a Reset generated by the CPU when asserting the SYSRESETREQ bit located in the
Reset Control register of the CPU (for details refer to the ARM® Cortex™ Technical Reference Manual on http://
www.arm.com).
From Backup Mode, the chip can be waken-up upon these conditions:
•
•
•
Battery Backup Power Switch (BBPS): generated by the SUPC controller when the 3.3V VDDIO is restored.
External wake up (EXTWAKEn): internally generated by the RSTC.
Real-Time Counter interrupt. For details refer to the applicable INTFLAG in the RTC for details.
If one of these conditions is triggered in Backup Mode, the RCAUSE.BACKUP bit is set and the Backup Exit Register
(BKUPEXIT) is updated.
References:
SUPC - Supply Controller
Battery Backup Power Switch
19.6.3
Additional Features
Not applicable.
19.6.4
DMA Operation
Not applicable.
19.6.5
Interrupts
Not applicable.
© 2020 Microchip Technology Inc.
DS60001477C-page 167
SAM L21 Family Data Sheet
RSTC – Reset Controller
19.6.6
Events
Not applicable.
19.6.7
Sleep Mode Operation
The RSTC module is active in all sleep modes.
© 2020 Microchip Technology Inc.
DS60001477C-page 168
SAM L21 Family Data Sheet
RSTC – Reset Controller
19.7
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
...
0x07
RCAUSE
Reserved
BKUPEXIT
Reserved
WKDBCONF
7:0
0x08
WKPOL
0x0A
...
0x0B
Reserved
0x0C
WKEN
0x0E
...
0x0F
Reserved
0x10
WKCAUSE
19.8
BACKUP
SYST
WDT
EXT
BOD33
BOD12
POR
7:0
BBPS
RTC
EXTWAKE
7:0
WKDBCNT[4:0]
Reserved
7:0
15:8
WKPOL[7:0]
7:0
15:8
WKEN[7:0]
7:0
15:8
WKCAUSE[7:0]
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16- and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers are optionally write-protected by the Peripheral Access Controller (PAC). Optional PAC writeprotection is denoted by the "PAC Write-Protection" property in each individual register description. For details, refer
to 19.5.8 Register Access Protection.
© 2020 Microchip Technology Inc.
DS60001477C-page 169
SAM L21 Family Data Sheet
RSTC – Reset Controller
19.8.1
Reset Cause
Name:
Offset:
Reset:
Property:
RCAUSE
0x00
Latest Reset Source
–
When a Reset occurs, the bit corresponding to the Reset source is set to '1' and all other bits are written to '0'.
Bit
Access
Reset
7
BACKUP
R
x
6
SYST
R
x
5
WDT
R
x
4
EXT
R
x
3
2
BOD33
R
x
1
BOD12
R
x
0
POR
R
x
Bit 7 – BACKUP Backup Reset
This bit is set if either a Backup or Reset has occurred. Refer to BKUPEXIT register to identify the source of the
Backup Reset.
Bit 6 – SYST System Reset Request
This bit is set if a System Reset Request has occurred. Refer to the Cortex processor documentation for more
details.
Bit 5 – WDT Watchdog Reset
This bit is set if a Watchdog Timer Reset has occurred.
Bit 4 – EXT External Reset
This bit is set if an external Reset has occurred.
Bit 2 – BOD33 Brown Out 33 Detector Reset
This bit is set if a BOD33 Reset has occurred.
Bit 1 – BOD12 Brown Out 12 Detector Reset
This bit is set if a BOD12 Reset has occurred.
Bit 0 – POR Power On Reset
This bit is set if a POR has occurred.
© 2020 Microchip Technology Inc.
DS60001477C-page 170
SAM L21 Family Data Sheet
RSTC – Reset Controller
19.8.2
Backup Exit Source
Name:
Offset:
Reset:
Property:
BKUPEXIT
0x02
Latest Backup Exit Source
–
When a Backup Reset occurs, the bit corresponding to the exit condition is set to '1', the other bits are written to '0'.
In some specific cases, the RTC and BBPS bits can be set together, e.g. when the device leaves the battery Backup
Mode caused by a BBPS condition, and a RTC event was generated during the Battery Backup Mode period.
Bit
7
6
Access
Reset
5
4
3
2
BBPS
R
x
1
RTC
R
x
0
EXTWAKE
R
x
Bit 2 – BBPS Battery Backup Power Switch
This bit is set if the Battery Backup Power Switch of the Supply Controller changes back from battery mode to main
power mode.
Bit 1 – RTC Real Timer Counter Interrupt
This bit is set if an RTC interrupt flag is set in Backup Mode. For more information, refer to the 25. RTC – Real-Time
Counter.
Bit 0 – EXTWAKE External Wake-up
This bit is set if the wake-up detector has detected an external wake-up condition in Backup Mode.
© 2020 Microchip Technology Inc.
DS60001477C-page 171
SAM L21 Family Data Sheet
RSTC – Reset Controller
19.8.3
Wakeup Debounce Configuration
Name:
Offset:
Reset:
Property:
Bit
7
WKDBCONF
0x04
0x00
PAC Write-Protection
6
Access
Reset
5
4
3
R/W
0
R/W
0
2
WKDBCNT[4:0]
R/W
0
1
0
R/W
0
R/W
0
Bits 4:0 – WKDBCNT[4:0] Wakeup Debounce Counter Value
These bits define the Debounce Mode used when waking up by external wakeup pin from Backup Mode.
WKDBCNT
Name
Description
0x00
OFF
0x01
0x02
0x03
0x04
0x05
0x06
0x07
2CK32
3CK32
32CK32
512CK32
4096CK32
32768CK32
-
No debouncing. Input pin is low or high level sensitive depending on its
WKPOLx bit.
Input pin shall be active for at least two 32KHz clock periods.
Input pin shall be active for at least three 32KHz clock periods.
Input pin shall be active for at least 32 32KHz clock periods.
Input pin shall be active for at least 512 32KHz clock periods.
Input pin shall be active for at least 4096 32KHz clock periods.
Input pin shall be active for at least 32768 32KHz clock periods.
Reserved
© 2020 Microchip Technology Inc.
DS60001477C-page 172
SAM L21 Family Data Sheet
RSTC – Reset Controller
19.8.4
Wakeup Polarity
Name:
Offset:
Reset:
Property:
Bit
WKPOL
0x08
0x0000
PAC Write-Protection
15
14
13
12
7
6
5
4
R/W
0
R/W
0
R/W
0
11
10
9
8
2
1
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
3
WKPOL[7:0]
R/W
R/W
0
0
Bits 7:0 – WKPOL[7:0] Wakeup Polarity
These bits define the polarity of each wakeup input pin.
Value
Description
0
Input pin x is active low.
1
Input pin x is active high.
© 2020 Microchip Technology Inc.
DS60001477C-page 173
SAM L21 Family Data Sheet
RSTC – Reset Controller
19.8.5
Wakeup Enable
Name:
Offset:
Reset:
Property:
WKEN
0x0C
0x0000
PAC Write-Protection
These bits enable wakeup for input pins from Backup Mode.
Bit
15
14
13
12
7
6
5
4
11
10
9
8
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
Access
Reset
Bit
WKEN[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – WKEN[7:0] Wakeup Enable
Value
Description
0
The wakeup for input pin x from backup mode is disabled.
1
The wakeup for input pin x from backup mode is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 174
SAM L21 Family Data Sheet
RSTC – Reset Controller
19.8.6
Wakeup Cause
Name:
Offset:
Reset:
Property:
Bit
WKCAUSE
0x10
0x0000
-
15
14
13
12
11
10
9
8
Bit
7
6
5
2
1
0
Access
Reset
R
0
R
0
R
0
4
3
WKCAUSE[7:0]
R
R
0
0
R
0
R
0
R
0
Access
Reset
Bits 7:0 – WKCAUSE[7:0] Wakeup Cause x
This bit is updated when exiting Backup Mode.
Value
Description
0
Input pin x is not active or WKENx is written to '0'.
1
Input pin x is active and WKENx is written to '1'.
© 2020 Microchip Technology Inc.
DS60001477C-page 175
SAM L21 Family Data Sheet
PM – Power Manager
20.
20.1
PM – Power Manager
Overview
The Power Manager (PM) controls the sleep modes and the power domain gating of the device.
Various sleep modes are provided in order to fit power consumption requirements. This enables the PM to stop
unused modules in order to save power. In active mode, the CPU is executing application code. When the device
enters a sleep mode, program execution is stopped and some modules and clock domains are automatically
switched off by the PM according to the sleep mode. The application code decides which sleep mode to enter and
when. Interrupts from enabled peripherals and all enabled reset sources can restore the device from a sleep mode to
active mode.
Performance level technique consists of adjusting the regulator output voltage to reduce power consumption. The
user can select on the fly the performance level configuration which best suits the application.
The power domain gating technique enables the PM to turn off unused power domain supplies individually, while
keeping others powered up. Based on activity monitoring, power domain gating is managed automatically by
hardware without software intervention. This technique is transparent for the application while minimizing the static
consumption. The user can also manually control which power domains will be turned on and off in standby sleep
mode.
In backup mode, the PM allows retaining the state of the I/O lines, preventing I/O lines from toggling during wake-up.
The internal state of the logic is retained (retention state) allowing the application context to be kept in non-active
states.
20.2
Features
•
20.3
Power management control
– Sleep modes: Idle, Standby, Backup, and Off
– Performance levels: PL0 and PL2
– SleepWalking available in Standby mode.
– Full retention state in Standby mode
– I/O lines retention in Backup mode
Block Diagram
Figure 20-1. PM Block Diagram
POWER MANAGER
POWER DOMAIN
CONTROLLER
POWER LEVEL SWITCHES
FOR POWER DOMAINS
STDBYCFG
MAIN CLOCK
CONTROLLER
SLEEP MODE
CONTROLLER
SUPPLY
CONTROLLER
SLEEPCFG
PERFORMANCE LEVEL
CONTROLLER
PLCF
© 2020 Microchip Technology Inc.
DS60001477C-page 176
SAM L21 Family Data Sheet
PM – Power Manager
20.4
Signal Description
Not applicable.
20.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
20.5.1
I/O Lines
Not applicable.
20.5.2
Clocks
The PM bus clock (CLK_PM_APB) can be enabled and disabled in the Main Clock module. If this clock is disabled, it
can only be re-enabled by a system reset.
20.5.3
DMA
Not applicable.
20.5.4
Interrupts
The interrupt request line is connected to the interrupt controller. Using the PM interrupt requires the interrupt
controller to be configured first.
References:
NVIC Overview
20.5.5
Events
Not applicable.
20.5.6
Debug Operation
When the CPU is halted in debug mode, the PM continues normal operation. If standby sleep mode is requested by
the system while in debug mode, the power domains are not turned off. As a consequence, power measurements
while in debug mode are not relevant.
If Backup sleep mode is requested by the system while in debug mode, the core domains are kept on, and the debug
modules are kept running to allow the debugger to access internal registers. When exiting the backup mode upon a
reset condition, the core domains are reset except the debug logic, allowing users to keep using their current debug
session.
Hot plugging in standby mode is supported except if the power domain PD2 is in retention state.
Cold or Hot plugging in OFF or Backup mode is not supported.
20.5.7
Register Access Protection
Registers with write-access can be write-protected optionally by the peripheral access controller (PAC).
PAC Write-Protection is not available for the following registers:
•
Interrupt Flag register (INTFLAG). Refer to 20.8.6 INTFLAG for details
Optional PAC Write-Protection is denoted by the "PAC Write-Protection" property in each individual register
description.
Write-protection does not apply to accesses through an external debugger.
References:
Peripheral Access Controller
20.5.8
Analog Connections
Not applicable.
© 2020 Microchip Technology Inc.
DS60001477C-page 177
SAM L21 Family Data Sheet
PM – Power Manager
20.6
20.6.1
Functional Description
Terminology
The following is a list of terms used to describe the Power Managemement features of this microcontroller.
20.6.1.1 Performance Levels
To help balance between performance and power consumption, the device has two performance levels. Each of the
performance levels has a maximum operating frequency and a corresponding maximum consumption in µA/MHz.
It is the application's responsibility to configure the appropriate PL depending on the application activity level. When
the application selects a new PL, the voltage applied on the full logic area moves from one value to another. This
voltage scaling technique allows to reduce the active power consumption while decreasing the maximum frequency
of the device.
PL0
Performance Level 0 (PL0) provides the maximum energy efficiency configuration.
Refer to 46. Electrical Characteristics for details on energy consumption and maximum operating frequency.
PL2
Performance Level 2 (PL2) provides the maximum operating frequency.
Refer to 46. Electrical Characteristics for details on energy consumption and maximum operating frequency.
20.6.1.2 Power Domains
In addition to the supply domains, such as VDDIO, VDDIN and VDDANA, the device provides these power domains:
• PD0, PD1, PD2
• PDTOP
• PDBACKUP
The PD0, PD1 and PD2 are "switchable power domains". In standby or backup sleep mode, they can be turned off to
save leakage consumption according to user configuration.
The three peripheral domains, PD0, PD1, and PD2, can be in retention state when none of the contained peripherals
are required, but if a peripheral power domain PDn is powered, lower power domains will be powered, too. For
example, if no peripherals are being used in PD2 and one or several peripherals in PD1 are active, then PD2 will be
powered down, PD1 will be powered, and PD0 will automatically be powered, even if no peripheral is being used.
© 2020 Microchip Technology Inc.
DS60001477C-page 178
SAM L21 Family Data Sheet
PM – Power Manager
Figure 20-2. Power Domain Partitioning
PD2
SERIAL
WIRE
SWDIO
DEVICE
SERVICE
UNIT
256/128/64/32KB
NVM
32/16/8/4KB
RAM
NVM
CONTROLLER
Cache
SRAM
CONTROLLER
M
M
M
S
S
HIGH SPEED
BUS MATRIX
S
S
M
PD1
S
M
SRAM
CONTROLLER
LOW POWER
BUS MATRIX
PERIPHERAL
ACCESS CONTROLLER
S
AHB-APB
BRIDGE E
S
S
AHB-APB
BRIDGE A
AHB-APB
BRIDGED
DMA
AHB-APB
BRIDGE C
PAD0
PAD1
PAD2
PAD3
DMA
5 x SERCOM
4 x TIMER / COUNTER
OSCILLATORS CONTROLLER
DMA
3x TIMER / COUNTER
FOR CONTROL
OSC16M
DFLL48M
XOSC
WO0
DMA
MAIN CLOCKS
CONTROLLER
PORT
S
M
S
PD0
DMA
GENERIC CLOCK
CONTROLLER
EXTINT[15..0]
NMI
WATCHDOG
TIMER
EXTERNAL INTERRUPT
CONTROLLER
PDBACKUP POWER
MANAGER
OSC32K CONTROLLER
XOSC32K
OSCULP32K
OSC32K
DMA
EVENT SYSTEM
PDTOP
Dual Channels
12-bit DAC 1MSPS
VREF
VREG
VOUT[1..0]
VREFP
PAD0
PAD1
PAD2
PAD3
WO0
DMA
TIMER / COUNTER
20-CHANNEL
12-bit ADC 1MSPS
2 ANALOG
COMPARATORS
SUPPLY CONTROLLER
BOD33
WO0
WO1
(2)
WOn
TRNG
SERCOM
DMA
WO1
AES
FDPLL96M
DMA
GCLK_IO[7..0]
XIN32
XOUT32
DM
SOF 1KHZ
8/4/2/2KB
RAM
AHB-APB
BRIDGE B
XIN
XOUT
DP
USB FS
DEVICE
MINI-HOST
PORT
SWCLK
CORTEX-M0+
PROCESSOR
Fmax 48 MHz
MEMORY
TRACE BUFFER
IOBUS
PERIPHERAL
TOUCH
CONTROLLER
WO1
AIN[19..0]
VREFA
VREFB
AIN[3..0]
X[15..0]
Y[15..0]
OA_NEG
RESET
EXTWAKEx
RESET
CONTROLLER
3 x OPAMP
OA_POS
OA_OUT
IN[2..0]
REAL TIME
COUNTER
© 2020 Microchip Technology Inc.
4 x CCL
OUT
DS60001477C-page 179
SAM L21 Family Data Sheet
PM – Power Manager
Related Links:
Power Domain Overview
PD0
PD0 is the lowest Power Domain. It contains the Event System, the Generic Clock Controller, Oscillators Controller,
the Main Clocks Controller. Additionally, PD0 contains a number of peripherals that allow the device to wake up from
an interrupt: one SERCOM (SERCOM5), one Timer/Counter (TC4), ADC, AC, OPAMP, CCL, and the PTC. The PLL
oscillator sources, DFLL48M and FDPLL96M, are in PD0 as well.
See also 20.6.1.2 Power Domains.
This power domain will automatically be activated if either PD1 or PD2 are activated.
PD1
PD1 is the intermediate Power Domain. PD1 contains the DMA controller, the Peripheral Access Controller, and the
Low Power Bus Matrix. It also contains the Timer/Counter for Control instances, the AES peripheral, the TRNG, the
DAC and the low-power SRAM. PD1 contains the SERCOMs (except for SERCOM5, present in PD0), and the Timer
Counters (except TC4, present in PD0).
When active, PD1 automatically activates PD0.
PD2
PD2 is the highest power domain. When activated, it will automatically activate both PD1 and PD0.
It contains the CM0+ core, the Non-Volatile Memory Controller, the Device Service Unit, USB, and the SRAM. See
also 20.6.1.2 Power Domains.
PDTOP
PDTOP contains all controllers located in the core domain. It is powered when in Active, Idle or Standby mode. It
does not have a retention mode; it is either in an active state, or off. When in Backup or Off mode, this domain is
completely powered down.
PDBACKUP
The Backup Power Domain (PDBACKUP) is always on, except in the off sleep mode. It contains the 32KHz oscillator
sources, the Supply Controller, the Reset Controller, the Real Time Counter, and the Power Manager itself.
20.6.1.3 Sleep Modes
The device can be set in a sleep mode. In sleep mode, the CPU is stopped and the peripherals are either active or
idle, according to the sleep mode depth:
•
•
•
•
Idle sleep mode: The CPU is stopped. Synchronous clocks are stopped except when requested. The logic is
retained.
Standby sleep mode: The CPU is stopped as well as the peripherals. The logic is retained, and power domain
gating can be used to reduce power consumption further.
Backup sleep mode: Only the backup domain is kept powered to allow few features to run (RTC, 32KHz clock
sources, and wake-up from external pins).
Off sleep mode: The entire device is powered off.
20.6.1.4 Power Domain States and Gating
In Standby sleep mode, the Power Domain Gating technique allows for selecting the state of a PDn power domain
automatically (e.g. for executing sleepwalking tasks) or manually:
Active State
The power domain is powered according to the performance level
Retention State The main voltage supply for the power domain is switched off, while maintaining a secondary lowpower supply for sequential cells. The logic context is restored when waking up.
Off State
The power domain is entirely powered off. The logic context is lost.
© 2020 Microchip Technology Inc.
DS60001477C-page 180
SAM L21 Family Data Sheet
PM – Power Manager
20.6.2
Principle of Operation
In active mode, all clock domains and power domains are active, allowing software execution and peripheral
operation. The PM Sleep Mode Controller allows to save power by choosing between different sleep modes
depending on application requirements, see 20.6.3.3 Sleep Mode Controller.
The PM Performance Level Controller allows to optimize either for low power consumption or high performance.
The PM Power Domain Controller allows to reduce the power consumption in standby mode even further.
20.6.3
Basic Operation
20.6.3.1 Initialization
After a power-on reset, the PM is enabled, the device is in ACTIVE mode, the performance level is PL0 (the lowest
power consumption) and all the power domains are in active state.
20.6.3.2 Enabling, Disabling and Resetting
The PM is always enabled and can not be reset.
20.6.3.3 Sleep Mode Controller
A Sleep mode is entered by executing the Wait For Interrupt instruction (WFI). The Sleep Mode bits in the Sleep
Configuration register (SLEEPCFG.SLEEPMODE) select the level of the sleep mode.
Note: A small latency happens between the store instruction and actual writing of the SLEEPCFG register due to
bridges. Software must ensure that the SLEEPCFG register reads the desired value before issuing a WFI instruction.
Note: After power-up, the MAINVREG low power mode takes some time to stabilize. Once stabilized, the
INTFLAG.SLEEPRDY bit is set. Before entering Standby, or Backup mode, software must ensure that the
INTFLAG.SLEEPRDY bit is set.
Table 20-1. Sleep Mode Entry and Exit Table
Mode
Mode Entry
Wake-Up Sources
IDLE
SLEEPCFG.SLEEPMODE = IDLE
_n
Synchronous (2) (APB, AHB), asynchronous (1)
STANDBY
SLEEPCFG.SLEEPMODE = STANDBY
Synchronous(3), Asynchronous
BACKUP
SLEEPCFG.SLEEPMODE = BACKUP
Backup reset detected by the RSTC
OFF
SLEEPCFG.SLEEPMODE = OFF
External Reset
Note:
1. Asynchronous: interrupt generated on generic clock, external clock, or external event.
2. Synchronous: interrupt generated on the APB clock.
3. Synchronous interrupt only for peripherals configured to run in standby.
Note: The type of wake-up sources (synchronous or asynchronous) is given in each module interrupt section.
The sleep modes (idle, standby, backup, and off) and their effect on the clocks activity, the regulator and the NVM
state are described in the table and the sections below. Refer to Power Domain Controller for the power domain
gating effect.
Table 20-2. Sleep Mode Overview
Mode
Main
clock
CPU
AHBx and APBx GCLK clocks
clock
Active
Run
Run
Run
IDLE
Run
Stop
STANDBY
Stop(1)
Stop
Oscillators
Regulator
NVM
ONDEMAND = 0
ONDEMAND = 1
Run(3)
Run
Run if requested
MAINVREG
active
Stop(1)
Run(3)
Run
Run if requested
MAINVREG
active
Stop(1)
Stop(1)
Run if requested or
RUNSTDBY=1
Run if requested
MAINVREG in
low power mode
Ultra Low power
© 2020 Microchip Technology Inc.
DS60001477C-page 181
SAM L21 Family Data Sheet
PM – Power Manager
...........continued
Mode
Main
clock
CPU
AHBx and APBx GCLK clocks
clock
BACKUP
Stop
Stop
Stop
OFF
Stop
Stop
Stop
Oscillators
Regulator
NVM
ONDEMAND = 0
ONDEMAND = 1
Stop
Stop
Stop
Backup
regulator
(ULPVREG)
OFF
OFF
OFF
OFF
OFF
OFF
Note:
1. Running if requested by peripheral during SleepWalking.
2. Running during SleepWalking.
3. Following On-Demand Clock Request principle.
IDLE Mode
The IDLE mode allows power optimization with the fastest wake-up time.
The CPU is stopped, and peripherals are still working. As in active mode, the AHBx and APBx clocks for peripheral
are still provided if requested. As the main clock source is still running, wake-up time is very fast.
•
•
Entering IDLE mode: The IDLE mode is entered by executing the WFI instruction. Additionally, if the
SLEEPONEXIT bit in the ARM Cortex System Control register (SCR) is set, the IDLE mode will be entered
when the CPU exits the lowest priority ISR (Interrupt Service Routine, see ARM Cortex documentation for
details). This mechanism can be useful for applications that only require the processor to run when an interrupt
occurs. Before entering the IDLE mode, the user must select the idle Sleep Mode in the Sleep Configuration
register (SLEEPCFG.SLEEPMODE=IDLE).
Exiting IDLE mode: The processor wakes the system up when it detects any non-masked interrupt with sufficient
priority to cause exception entry. The system goes back to the ACTIVE mode. The CPU and affected modules
are restarted.
GCLK clocks, regulators and RAM are not affected by the idle sleep mode and operate in normal mode.
STANDBY Mode
The STANDBY mode is the lowest power configuration while keeping the state of the logic and the content of the
RAM.
In this mode, all clocks are stopped except those configured to be running sleepwalking tasks. The clocks can also
be active on request or at all times, depending on their on-demand and run-in-standby settings. Either synchronous
(CLK_APBx or CLK_AHBx) or generic (GCLK_x) clocks or both can be involved in sleepwalking tasks. This is the
case when for example the SERCOM RUNSTDBY bit is written to '1'.
•
•
Entering STANDBY mode: This mode is entered by executing the WFI instruction after writing the Sleep Mode
bit in the Sleep Configuration register (SLEEPCFG.SLEEPMODE=STANDBY). The SLEEPONEXIT feature is
also available as in IDLE mode.
Exiting STANDBY mode: Any peripheral able to generate an asynchronous interrupt can wake up the system.
For example, a peripheral running on a GCLK clock can trigger an interrupt. When the enabled asynchronous
wake-up event occurs and the system is woken up, the device will either execute the interrupt service routine or
continue the normal program execution according to the Priority Mask Register (PRIMASK) configuration of the
CPU.
Refer to 20.6.3.7 Regulators, RAMs, and NVM State in Sleep Mode for the RAM state.
The regulator operates in low-power mode by default and switches automatically to the normal mode in case of a
sleepwalking task requiring more power. It returns automatically to low power mode when the sleepwalking task is
completed.
© 2020 Microchip Technology Inc.
DS60001477C-page 182
SAM L21 Family Data Sheet
PM – Power Manager
BACKUP Mode
The BACKUP mode allows achieving the lowest power consumption aside from OFF. The device is entirely powered
off except for the backup domain. All peripherals in backup domain are allowed to run, e.g. the RTC can be clocked
by a 32.768kHz oscillator. All PM registers are reset except the CTRLA.IORET bit.
•
•
Entering Backup mode: This mode is entered by executing the WFI instruction after selecting the Backup mode
by writing the Sleep Mode bits in the Sleep Configuration register (SLEEPCFG.SLEEPMODE=BACKUP).
Exiting Backup mode: is triggered when a Backup Reset is detected by the Reset Controller (RSTC).
OFF Mode
In OFF mode, the device is entirely powered-off.
•
•
Entering OFF mode: This mode is entered by selecting the OFF mode in the Sleep Configuration register by
writing the Sleep Mode bits (SLEEPCFG.SLEEPMODE=OFF), and subsequent execution of the WFI instruction.
Exiting OFF mode: This mode is left by pulling the RESET pin low, or when a power Reset is done.
20.6.3.4 I/O Lines Retention in BACKUP Mode
When entering BACKUP mode, the PORT is powered off but the pin configuration is retained. When the device exits
the BACKUP mode, the I/O line configuration can either be released or stretched, based on the I/O Retention bit in
the CTRLA register (CTRLA.IORET).
•
•
If IORET=0 when exiting BACKUP mode, the I/O lines configuration is released and driven by the reset value of
the PORT.
If the IORET=1 when exiting BACKUP mode, the configuration of the I/O lines is retained until the IORET bit is
written to 0. It allows the I/O lines to be retained until the application has programmed the PORT.
20.6.3.5 Performance Level
The application can change the performance level on the fly writing to the by Performance Level Select bit in the
Performance Level Configuration register (PLCFG.PLSEL).
When changing to a lower performance level, the bus frequency must be reduced before writing PLCFG.PLSEL in
order to avoid exceeding the limit of the target performance level.
When changing to a higher performance level, the bus frequency can be increased only after the Performance Level
Ready flag in the Interrupt Flag Status and Clear (INTFLAG.PLRDY) bit set to '1', indicating that the performance
level transition is complete.
After a reset, the device starts in the lowest PL (lowest power consumption and lowest max frequency). The
application can then switch to another PL at anytime without any stop in the code execution. As shown in Figure
20-3, performance level transition is possible only when the device is in active mode.
The Performance Level Disable bit in the Performance Level Configuration register (PLCFG.PLDIS) can be used to
freeze the performance level to PL0. This disables the performance level hardware mechanism in order to reduce
both the power consumption and the wake-up startup time from standby sleep mode.
Note: This bit PLCFG.PLDIS must be changed only when the current performance level is PL0.
Any attempt to modify this bit while the performance level is not PL0 is discarded and a violation is reported to the
PAC module. Any attempt to change the performance level to PLn (with n>0) while PLCFG.PLDIS=1 is discarded and
a violation is reported to the PAC module.
© 2020 Microchip Technology Inc.
DS60001477C-page 183
SAM L21 Family Data Sheet
PM – Power Manager
Figure 20-3. Sleep Modes and Performance Level Transitions
RESET
PLCFG.PLSEL
ACTIVE PLn
ACTIVE PL0
SLEEPCFG.
IDLE
IRQ
IDLE PLn
SLEEPCFG.
STANDBY
IRQ
STANDBY
Backup
Reset
SLEEPCFG.
BACKUP
BACKUP
SLEEPCFG.
OFF
ext reset
OFF
20.6.3.6 Power Domain Controller
The Power Domain Controller provides several ways of how power domains are handled while the device is in
standby mode or entering standby mode:
•
Default operation - all peripherals idle
When entering standby mode, the power domains PD0, PD1, and PD2 are set in retention state. This allows for
very low power consumption while retaining all the logic content of these power domains. When exiting standby
mode, all power domains are set back to active state.
•
Default operation - SleepWalking with static power gating (static SleepWalking)
When a peripheral needs to remain running while the device is entering standby mode (e.g. to perform a
sleepwalking task, or because of its RUNSTDBY bit written to '1') the power domain of the peripheral (PDn)
remains in active state as well as the inferior power domains (PDm with m MASK)
return 1;
return 0;
}
Dithering on Period
Writing DITHERCY in PER will lead to an average PWM period configured by the following formulas.
DITH4 mode:
��������� =
DITHERCY
1
+ PER
16
�GCLK_TCC
Note: If DITH4 mode is enabled, the last 4 significant bits from PER/CCx or COUNT register correspond to the
DITHERCY value, rest of the bits corresponds to PER/CCx or COUNT value.
© 2020 Microchip Technology Inc.
DS60001477C-page 716
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
DITH5 mode:
��������� =
DITHERCY
1
+ PER
32
�GCLK_TCC
��������� =
DITHERCY
1
+ PER
64
�GCLK_TCC
DITH6 mode:
Dithering on Pulse Width
Writing DITHERCY in CCx will lead to an average PWM pulse width configured by the following formula.
DITH4 mode:
������������ℎ =
DITHERCY
1
+ CCx
16
�GCLK_TCC
������������ℎ =
DITHERCY
1
+ CCx
32
�GCLK_TCC
������������ℎ =
DITHERCY
1
+ CCx
64
�GCLK_TCC
DITH5 mode:
DITH6 mode:
Note: The PWM period will remain static in this case.
36.6.3.4 Ramp Operations
Three ramp operation modes are supported. All of them require the timer/counter running in single-slope PWM
generation. The ramp mode is selected by writing to the Ramp Mode bits in the Waveform Control register
(WAVE.RAMP).
RAMP1 Operation
This is the default PWM operation, described in Single-Slope PWM Generation.
RAMP2 Operation
These operation modes are dedicated for power factor correction (PFC), Half-Bridge and Push-Pull SMPS
topologies, where two consecutive timer/counter cycles are interleaved, see Figure 36-18. In cycle A, odd channel
output is disabled, and in cycle B, even channel output is disabled. The ramp index changes after each update, but
can be software modified using the Ramp index command bits in Control B Set register (CTRLBSET.IDXCMD).
Standard RAMP2 (RAMP2) Operation
Ramp A and B periods are controlled by the PER register value. The PER value can be different on each ramp by the
Circular Period buffer option in the Wave register (WAVE.CIPEREN=1). This mode uses a two-channel TCC to
generate two output signals, or one output signal with another CC channel enabled in capture mode.
© 2020 Microchip Technology Inc.
DS60001477C-page 717
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Figure 36-18. RAMP2 Standard Operation
Ramp
A
B
A
B
Retrigger
on
FaultA
TOP(B)
TOP(A)
CC0
TOP(B)
CIPEREN = 1
CC1
CC1
COUNT
"clear" update
"match"
CC0
ZERO
WO[0]
POL0 = 1
WO[1]
Keep on FaultB
POL1 = 1
FaultA input
FaultB input
Alternate RAMP2 (RAMP2A) Operation
Alternate RAMP2 operation is similar to RAMP2, but CC0 controls both WO[0] and WO[1] waveforms when the
corresponding circular buffer option is enabled (CIPEREN=1). The waveform polarity is the same on both outputs.
Channel 1 can be used in capture mode.
Figure 36-19. RAMP2 Alternate Operation
Ramp
A
B
A
TOP(B)
TOP(A)
B
Retrigger
on
FaultA
CC0(A)
TOP(B)
CIPEREN = 1
CC0(B)
CC0(B)
COUNT
"clear" update
"match"
CICCEN0 = 1
CC0(A)
ZERO
WO[0]
WO[1]
Keep on FaultB
POL0 = 1
FaultA input
FaultB input
Critical RAMP2 (RAMP2C) Operation
Critical RAMP2 operation provides a way to cover RAMP2 operation requirements without the update constraint
associated to the use of circular buffers. In this mode, CC0 is controlling the period of ramp A and PER is controlling
the period of ramp B. When using more than two channels, WO[0] output is controlled by CC2 (HIGH) and CC0
(LOW). On TCC with 2 channels, a pulse on WO[0] will last the entire period of ramp A, if WAVE.POL0=0.
© 2020 Microchip Technology Inc.
DS60001477C-page 718
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Figure 36-20. RAMP2 Critical Operation With More Than 2 Channels
Ramp
A
B
A
B
Retrigger
on
FaultA
TOP
CC0
TOP
CC1
CC1
COUNT
"clear" update
"match"
CC2
CC2
ZERO
WO[0]
POL2 = 1
WO[1]
Keep on FaultB
POL1 = 1
FaultA input
FaultB input
Figure 36-21. RAMP2 Critical Operation With 2 Channels
Ramp
A
B
A
TOP
CC0
CC1
COUNT
B
Retrigger
on
FaultA
"clear" update
"match"
TOP
CC1
ZERO
WO[0]
WO[1]
POL0 = 0
Keep on FaultB
POL1 = 1
FaultA input
FaultB input
36.6.3.5 Recoverable Faults
Recoverable faults can restart or halt the timer/counter. Two faults, called Fault A and Fault B, can trigger recoverable
fault actions on the compare channels CC0 and CC1 of the TCC. The compare channels' outputs can be clamped to
inactive state either as long as the fault condition is present, or from the first valid fault condition detection on until the
end of the timer/counter cycle.
Fault Inputs
The first two channel input events (TCCxMC0 and TCCxMC1) can be used as Fault A and Fault B inputs,
respectively. Event system channels connected to these fault inputs must be configured as asynchronous. The TCC
must work in a PWM mode.
© 2020 Microchip Technology Inc.
DS60001477C-page 719
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Fault Filtering
There are three filters available for each input Fault A and Fault B. They are configured by the corresponding
Recoverable Fault n Configuration registers (FCTRLA and FCTRLB). The three filters can either be used
independently or in any combination.
Input
Filtering
By default, the event detection is asynchronous. When the event occurs, the fault system will
immediately and asynchronously perform the selected fault action on the compare channel output, also
in device power modes where the clock is not available. To avoid false fault detection on external
events (e.g. due to a glitch on an I/O port) a digital filter can be enabled and configured by the Fault B
Filter Value bits in the Fault n Configuration registers (FCTRLn.FILTERVAL). If the event width is less
than FILTERVAL (in clock cycles), the event will be discarded. A valid event will be delayed by
FILTERVAL clock cycles.
Fault
Blanking
This ignores any fault input for a certain time just after a selected waveform output edge. This can be
used to prevent false fault triggering due to signal bouncing, as shown in the figure below. Blanking can
be enabled by writing an edge triggering configuration to the Fault n Blanking Mode bits in the
Recoverable Fault n Configuration register (FCTRLn.BLANK). The desired duration of the blanking
must be written to the Fault n Blanking Time bits (FCTRLn.BLANKVAL).
The blanking time tbis calculated by
�� =
1 + BLANKVAL
�GCLK_TCCx_PRESC
Here, fGCLK_TCCx_PRESC is the frequency of the prescaled peripheral clock frequency fGCLK_TCCx.
The prescaler is enabled by writing '1' to the Fault n Blanking Prescaler bit (FCTRLn.BLANKPRESC).
When disabled, fGCLK_TCCx_PRESC=fGCLK_TCCx. When enabled, fGCLK_TCCx_PRESC=fGCLK_TCCx/64.
The maximum blanking time (FCTRLn.BLANKVAL=
255) at fGCLK_TCCx=96MHz is 2.67µs (no prescaler) or 170µs (prescaling). For fGCLK_TCCx=1MHz, the
maximum blanking time is either 170µs (no prescaling) or 10.9ms (prescaling enabled).
Figure 36-22. Fault Blanking in RAMP1 Operation with Inverted Polarity
"clear" update
"match"
TOP
"Fault input enabled"
- "Fault input disabled"
CC0
x
"Fault discarded"
COUNT
ZERO
CMP0
FCTRLA.BLANKVAL = 0
FaultA Blanking
FCTRLA.BLANKVAL > 0
FCTRLA.BLANKVAL > 0
x
-
xxx
FaultA Input
WO[0]
Fault
Qualification
This is enabled by writing a '1' to the Fault n Qualification bit in the Recoverable Fault n
Configuration register (FCTRLn.QUAL). When the recoverable fault qualification is enabled
(FCTRLn.QUAL=1), the fault input is disabled all the time the corresponding channel output has
an inactive level, as shown in the figures below.
© 2020 Microchip Technology Inc.
DS60001477C-page 720
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Figure 36-23. Fault Qualification in RAMP1 Operation
MAX
"clear" update
TOP
"match"
CC0
COUNT
"Fault input enabled"
- "Fault input disabled"
CC1
x
"Fault discarded"
ZERO
-
Fault A Input Qual
-
-
-
-
x x x
x x x x x x
Fault Input A
Fault B Input Qual
-
-
-
x x x
-
x x x x x
-
x x x x x x x
-
x x x x
Fault Input B
Figure 36-24. Fault Qualification in RAMP2 Operation with Inverted Polarity
Cycle
"clear" update
MAX
"match"
TOP
"Fault input enabled"
COUNT
CC0
- "Fault input disabled"
x
CC1
"Fault discarded"
ZERO
Fault A Input Qual
-
-
x
x
-
x
x
x
x
x
x
x
x
x
x
Fault Input A
-
Fault B Input Qual
x
x
x
x
-
x
x
x
x
-
x
x
x
x
x
x
x
Fault Input B
Fault Actions
Different fault actions can be configured individually for Fault A and Fault B. Most fault actions are not mutually
exclusive; hence two or more actions can be enabled at the same time to achieve a result that is a combination of
fault actions.
Keep
Action
This is enabled by writing the Fault n Keeper bit in the Recoverable Fault n Configuration register
(FCTRLn.KEEP) to '1'. When enabled, the corresponding channel output will be clamped to zero as
long as the fault condition is present. The clamp will be released on the start of the first cycle after the
fault condition is no longer present, see next Figure.
Figure 36-25. Waveform Generation with Fault Qualification and Keep Action
MAX
"clear" update
TOP
"match"
COUNT
"Fault input enabled"
CC0
- "Fault input disabled"
x
"Fault discarded"
ZERO
Fault A Input Qual
-
-
-
-
x
-
x
x
x
Fault Input A
WO[0]
© 2020 Microchip Technology Inc.
KEEP
KEEP
DS60001477C-page 721
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Restart
Action
This is enabled by writing the Fault n Restart bit in Recoverable Fault n Configuration register
(FCTRLn.RESTART) to '1'. When enabled, the timer/counter will be restarted as soon as the
corresponding fault condition is present. The ongoing cycle is stopped and the timer/counter starts a new
cycle, see Figure 36-26. In Ramp 1 mode, when the new cycle starts, the compare outputs will be
clamped to inactive level as long as the fault condition is present.
Note: For RAMP2 operation, when a new timer/counter cycle starts the cycle index will change
automatically, see Figure 36-27. Fault A and Fault B are qualified only during the cycle A and cycle B
respectively: Fault A is disabled during cycle B, and Fault B is disabled during cycle A.
Figure 36-26. Waveform Generation in RAMP1 mode with Restart Action
MAX
"clear" update
"match"
TOP
CC0
COUNT
CC1
ZERO
Restart
Restart
Fault Input A
WO[0]
WO[1]
Figure 36-27. Waveform Generation in RAMP2 mode with Restart Action
Cycle
CCx=ZERO
CCx=TOP
"clear" update
"match"
MAX
TOP
COUNT
CC0/CC1
ZERO
No fault A action
in cycle B
Restart
Fault Input A
WO[0]
WO[1]
Capture
Action
Several capture actions can be selected by writing the Fault n Capture Action bits in the Fault n Control
register (FCTRLn.CAPTURE). When one of the capture operations is selected, the counter value is
captured when the fault occurs. These capture operations are available:
• CAPT - the equivalent to a standard capture operation, for further details refer to 36.6.2.7 Capture
Operations
• CAPTMIN - gets the minimum time stamped value: on each new local minimum captured value, an
event or interrupt is issued.
• CAPTMAX - gets the maximum time stamped value: on each new local maximum captured value,
an event or interrupt (IT) is issued, see Figure 36-28.
© 2020 Microchip Technology Inc.
DS60001477C-page 722
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
•
•
•
LOCMIN - notifies by event or interrupt when a local minimum captured value is detected.
LOCMAX - notifies by event or interrupt when a local maximum captured value is detected.
DERIV0 - notifies by event or interrupt when a local extreme captured value is detected, see Figure
36-29.
CCx Content:
In CAPTMIN and CAPTMAX operations, CCx keeps the respective extremum captured values, see
Figure 36-28. In LOCMIN, LOCMAX or DERIV0 operation, CCx follows the counter value at fault time,
see Figure 36-29.
Before enabling CAPTMIN or CAPTMAX mode of capture, the user must initialize the corresponding
CCx register value to a value different from zero (for CAPTMIN) top (for CAPTMAX). If the CCx register
initial value is zero (for CAPTMIN) top (for CAPTMAX), no captures will be performed using the
corresponding channel.
MCx Behaviour:
In LOCMIN and LOCMAX operation, capture is performed on each capture event. The MCx interrupt
flag is set only when the captured value is upper or equal (for LOCMIN) or lower or equal (for LOCMAX)
to the previous captured value. So interrupt flag is set when a new relative local Minimum (for
CAPTMIN) or Maximum (for CAPTMAX) value has been detected. DERIV0 is equivalent to an OR
function of (LOCMIN, LOCMAX).
In CAPT operation, capture is performed on each capture event. The MCx interrupt flag is set on each
new capture.
In CAPTMIN and CAPTMAX operation, capture is performed only when on capture event time, the
counter value is lower (for CAPTMIN) or upper (for CAPMAX) than the last captured value. The MCx
interrupt flag is set only when on capture event time, the counter value is upper or equal (for CAPTMIN)
or lower or equal (for CAPTMAX) to the value captured on the previous event. So interrupt flag is set
when a new absolute local Minimum (for CAPTMIN) or Maximum (for CAPTMAX) value has been
detected.
Interrupt Generation
In CAPT mode, an interrupt is generated on each filtered Fault n and each dedicated CCx channel
capture counter value. In other modes, an interrupt is only generated on an extreme captured value.
Figure 36-28. Capture Action “CAPTMAX”
TOP
COUNT
CC0
"clear" update
"match"
ZERO
FaultA Input
CC0 Event/
Interrupt
© 2020 Microchip Technology Inc.
DS60001477C-page 723
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Figure 36-29. Capture Action “DERIV0”
TOP
COUNT
"update"
"match"
CC0
ZERO
FaultA Input
CC0 Event/
Interrupt
Hardware
Halt Action
This is configured by writing 0x1 to the Fault n Halt mode bits in the Recoverable Fault n
Configuration register (FCTRLn.HALT). When enabled, the timer/counter is halted and the cycle is
extended as long as the corresponding fault is present.
The next figure ('Waveform Generation with Halt and Restart Actions') shows an example where both
restart action and hardware halt action are enabled for Fault A. The compare channel 0 output is
clamped to inactive level as long as the timer/counter is halted. The timer/counter resumes the
counting operation as soon as the fault condition is no longer present. As the restart action is enabled
in this example, the timer/counter is restarted after the fault condition is no longer present.
The figure after that ('Waveform Generation with Fault Qualification, Halt, and Restart Actions') shows
a similar example, but with additionally enabled fault qualification. Here, counting is resumed after the
fault condition is no longer present.
Note that in RAMP2 and RAMP2A operations, when a new timer/counter cycle starts, the cycle index
will automatically change.
Figure 36-30. Waveform Generation with Halt and Restart Actions
MAX
"clear" update
"match"
TOP
COUNT
CC0
HALT
ZERO
Restart
Restart
Fault Input A
WO[0]
© 2020 Microchip Technology Inc.
DS60001477C-page 724
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Figure 36-31. Waveform Generation with Fault Qualification, Halt, and Restart Actions
MAX
"update"
"match"
TOP
CC0
COUNT
HALT
ZERO
Resume
Fault A Input Qual
-
-
-
-
x
-
x
x
Fault Input A
KEEP
WO[0]
Software
Halt Action
This is configured by writing 0x2 to the Fault n Halt mode bits in the Recoverable Fault n
configuration register (FCTRLn.HALT). Software halt action is similar to hardware halt action, but in
order to restart the timer/counter, the corresponding fault condition must not be present anymore,
and the corresponding FAULT n bit in the STATUS register must be cleared by software.
Figure 36-32. Waveform Generation with Software Halt, Fault Qualification, Keep and Restart Actions
MAX
"update"
"match"
TOP
COUNT
CC0
HALT
ZERO
Restart
Fault A Input Qual
-
-
Restart
-
x
-
x
Fault Input A
Software Clear
WO[0]
KEEP
NO
KEEP
36.6.3.6 Non-Recoverable Faults
The non-recoverable fault action will force all the compare outputs to a pre-defined level programmed into the Driver
Control register (DRVCTRL.NRE and DRVCTRL.NRV). The non-recoverable fault input (EV0 and EV1) actions are
enabled in Event Control register (EVCTRL.EVACT0 and EVCTRL.EVACT1).
To avoid false fault detection on external events (e.g. a glitch on an I/O port) a digital filter can be enabled using NonRecoverable Fault Input x Filter Value bits in the Driver Control register (DRVCTRL.FILTERVALn). Therefore, the
event detection is synchronous, and event action is delayed by the selected digital filter value clock cycles.
When the Fault Detection on Debug Break Detection bit in Debug Control register (DGBCTRL.FDDBD) is written to
'1', a non-recoverable Debug Faults State and an interrupt (DFS) is generated when the system goes in debug
operation.
In RAMP2, RAMP2A, or DSBOTH operation, when the Lock Update bit in the Control B register is set by writing
CTRLBSET.LUPD=1 and the ramp index or counter direction changes, a non-recoverable Update Fault State and the
respective interrupt (UFS) are generated.
© 2020 Microchip Technology Inc.
DS60001477C-page 725
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.6.3.7 Time-Stamp Capture
This feature is enabled when the Capture Time Stamp (STAMP) Event Action in Event Control register
(EVCTRL.EVACT) is selected. The counter TOP value must be smaller than MAX.
When a capture event is detected, the COUNT value is copied into the corresponding Channel x Compare/Capture
Value (CCx) register. In case of an overflow, the MAX value is copied into the corresponding CCx register.
When a valid captured value is present in the capture channel register, the corresponding Capture Channel x
Interrupt Flag (INTFLAG.MCx) is set.
The timer/counter can detect capture overflow of the input capture channels: When a new capture event is detected
while the Capture Channel interrupt flag (INTFLAG.MCx) is still set, the new time-stamp will not be stored and
INTFLAG.ERR will be set.
Figure 36-33. Time-Stamp
Capture Events
MAX
TOP
"capture"
"overflow"
COUNT
ZERO
CCx Value
COUNT
COUNT
TOP
COUNT
MAX
36.6.3.8 Waveform Extension
Figure 36-34 shows a schematic diagram of actions of the four optional units that follow the recoverable fault stage
on a port pin pair: Output Matrix (OTMX), Dead-Time Insertion (DTI), SWAP and Pattern Generation. The DTI and
SWAP units can be seen as a four port pair slices:
• Slice 0 DTI0 / SWAP0 acting on port pins (WO[0], WO[WO_NUM/2 +0])
• Slice 1 DTI1 / SWAP1 acting on port pins (WO[1], WO[WO_NUM/2 +1])
And more generally:
• Slice n DTIx / SWAPx acting on port pins (WO[x], WO[WO_NUM/2 +x])
Figure 36-34. Waveform Extension Stage Details
WEX
OTMX
DTI
PORTS
SWAP
OTMX[x+WO_NUM/2]
PATTERN
PGV[x+WO_NUM/2]
P[x+WO_NUM/2]
LS
OTMX
DTIx
HS
PGO[x+WO_NUM/2]
DTIxEN
INV[x+WO_NUM/2]
SWAPx
PGO[x]
INV[x]
P[x]
OTMX[x]
PGV[x]
The output matrix (OTMX) unit distributes compare channels, according to the selectable configurations in Table
36-4.
© 2020 Microchip Technology Inc.
DS60001477C-page 726
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Table 36-4. Output Matrix Channel Pin Routing Configuration
Value
OTMX[x]
0x0
CC3
CC2
CC1
CC0
CC3
CC2
CC1
CC0
0x1
CC1
CC0
CC1
CC0
CC1
CC0
CC1
CC0
0x2
CC0
CC0
CC0
CC0
CC0
CC0
CC0
CC0
0x3
CC1
CC1
CC1
CC1
CC1
CC1
CC1
CC0
Notes on Table 36-4:
•
Configuration 0x0 is the default configuration. The channel location is the default one, and channels are
distributed on outputs modulo the number of channels. Channel 0 is routed to the Output matrix output
OTMX[0], and Channel 1 to OTMX[1]. If there are more outputs than channels, then channel 0 is duplicated to
the Output matrix output OTMX[CC_NUM], channel 1 to OTMX[CC_NUM+1] and so on.
• Configuration 0x1 distributes the channels on output modulo half the number of channels. This assigns twice the
number of output locations to the lower channels than the default configuration. This can be used, for example,
to control the four transistors of a full bridge using only two compare channels.
Using pattern generation, some of these four outputs can be overwritten by a constant level, enabling flexible
drive of a full bridge in all quadrant configurations.
• Configuration 0x2 distributes compare channel 0 (CC0) to all port pins. With pattern generation, this
configuration can control a stepper motor.
• Configuration 0x3 distributes the compare channel CC0 to the first output, and the channel CC1 to all other
outputs. Together with pattern generation and the fault extension, this configuration can control up to seven LED
strings, with a boost stage.
Table
•
36-5. Example: four compare channels on four outputs
Value
OTMX[3]
OTMX[2]
OTMX[1]
OTMX[0]
0x0
CC3
CC2
CC1
CC0
0x1
CC1
CC0
CC1
CC0
0x2
CC0
CC0
CC0
CC0
0x3
CC1
CC1
CC1
CC0
The dead-time insertion (DTI) unit generates OFF time with the non-inverted low side (LS) and inverted high side
(HS) of the wave generator output forced at low level. This OFF time is called dead time. Dead-time insertion ensures
that the LS and HS will never switch simultaneously.
The DTI stage consists of four equal dead-time insertion generators; one for each of the first four compare channels.
Figure 36-35 shows the block diagram of one DTI generator. The four channels have a common register which
controls the dead time, which is independent of high side and low side setting.
© 2020 Microchip Technology Inc.
DS60001477C-page 727
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Figure 36-35. Dead-Time Generator Block Diagram
DTHS
DTLS
Dead Time Generator
LOAD
EN
Counter
=0
OTMX output
D
"DTLS"
Q
(To PORT)
"DTHS"
Edge Detect
(To PORT)
As shown in Figure 36-36, the 8-bit dead-time counter is decremented by one for each peripheral clock cycle until it
reaches zero. A non-zero counter value will force both the low side and high side outputs into their OFF state. When
the output matrix (OTMX) output changes, the dead-time counter is reloaded according to the edge of the input.
When the output changes from low to high (positive edge) it initiates a counter reload of the DTLS register. When the
output changes from high to low (negative edge) it reloads the DTHS register.
Figure 36-36. Dead-Time Generator Timing Diagram
"dti_cnt"
T
tP
tDTILS
t DTIHS
"OTMX output"
"DTLS"
"DTHS"
The pattern generator unit produces a synchronized bit pattern across the port pins it is connected to. The pattern
generation features are primarily intended for handling the commutation sequence in brushless DC motors (BLDC),
stepper motors, and full bridge control. See also Figure 36-37.
© 2020 Microchip Technology Inc.
DS60001477C-page 728
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Figure 36-37. Pattern Generator Block Diagram
COUNT
UPDATE
BV
PGEB[7:0]
EN
BV
PGE[7:0]
PGVB[7:0]
EN
SWAP output
PGV[7:0]
WOx[7:0]
As with other double-buffered timer/counter registers, the register update is synchronized to the UPDATE condition
set by the timer/counter waveform generation operation. If synchronization is not required by the application, the
software can simply access directly the PATT.PGE, PATT.PGV bits registers.
36.6.4
Master/Slave Operation
Two TCC instances sharing the same GCLK_TCC clock, can be linked to provide more synchronized CC channels.
The operation is enabled by setting the Master Synchronization bit in Control A register (CTRLA.MSYNC) in the
Slave instance. When the bit is set, the slave TCC instance will synchronize the CC channels to the Master counter.
36.6.5
DMA, Interrupts, and Events
Table 36-6. Module Requests for TCC
Condition
Interrupt
request
Event
output
Overflow / Underflow
Yes
Yes
Channel Compare Match or Yes
Capture
Yes
Retrigger
Yes
Yes
Count
Yes
Yes
Capture Overflow Error
Yes
Debug Fault State
Yes
Recoverable Faults
Yes
Non-Recoverable Faults
Yes
Event input DMA
request
Yes(2)
TCCx Event 0 input
Yes(4)
TCCx Event 1 input
Yes(5)
© 2020 Microchip Technology Inc.
DMA request is cleared
Yes(1)
On DMA acknowledge
Yes(3)
For circular buffering: on
DMA acknowledge
For capture channel:
when CCx register is
read
DS60001477C-page 729
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Notes:
1. DMA request set on overflow, underflow or re-trigger conditions.
2. Can perform capture or generate recoverable fault on an event input.
3. In capture or circular modes.
4. On event input, either action can be executed:
– re-trigger counter
– control counter direction
– stop the counter
– decrement the counter
– perform period and pulse width capture
– generate non-recoverable fault
5. On event input, either action can be executed:
– re-trigger counter
– increment or decrement counter depending on direction
– start the counter
– increment or decrement counter based on direction
– increment counter regardless of direction
– generate non-recoverable fault
36.6.5.1 DMA Operation
The TCC can generate the following DMA requests:
Counter
overflow
(OVF)
If the Ones-shot Trigger mode in the control A register (CTRLA.DMAOS) is written to '0', the TCC
generates a DMA request on each cycle when an update condition (overflow, underflow or retrigger) is detected.
When an update condition (overflow, underflow or re-trigger) is detected while CTRLA.DMAOS=1,
the TCC generates a DMA trigger on the cycle following the DMA One-Shot Command written to
the Control B register (CTRLBSET.CMD=DMAOS).
In both cases, the request is cleared by hardware on DMA acknowledge.
Channel
Match (MCx)
A DMA request is set only on a compare match if CTRLA.DMAOS=0. The request is cleared by
hardware on DMA acknowledge.
When CTRLA.DMAOS=1, the DMA requests are not generated.
Channel
Capture
(MCx)
For a capture channel, the request is set when valid data is present in the CCx register, and cleared
once the CCx register is read.
In this operation mode, the CTRLA.DMAOS bit value is ignored.
DMA Operation with Circular Buffer
When circular buffer operation is enabled, the buffer registers must be written in a correct order and synchronized to
the update times of the timer. The DMA triggers of the TCC provide a way to ensure a safe and correct update of
circular buffers.
Note: Circular buffer are intended to be used with RAMP2, RAMP2A and DSBOTH operation only.
DMA Operation with Circular Buffer in RAMP and RAMP2A Mode
When a CCx channel is selected as a circular buffer, the related DMA request is not set on a compare match
detection, but on start of ramp B.
If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of ramp A with an
effective DMA transfer on previous ramp B (DMA acknowledge).
The update of all circular buffer values for ramp A can be done through a DMA channel triggered on a MC trigger.
The update of all circular buffer values for ramp B, can be done through a second DMA channel triggered by the
overflow DMA request.
© 2020 Microchip Technology Inc.
DS60001477C-page 730
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Figure 36-38. DMA Triggers in RAMP and RAMP2 Operation Mode and Circular Buffer Enabled
Ramp
Cycle
A
B
A
B
A
B
N-1
N-2
N
"update"
COUNT
ZERO
STATUS.IDX
DMA_CCx_req
DMA Channel i
Update ramp A
DMA_OVF_req
DMA Channel j
Update ramp B
DMA Operation with Circular Buffer in DSBOTH Mode
When a CC channel is selected as a circular buffer, the related DMA request is not set on a compare match
detection, but on start of down-counting phase.
If at least one circular buffer is enabled, the DMA overflow request is conditioned to the start of up-counting phase
with an effective DMA transfer on previous down-counting phase (DMA acknowledge).
When up-counting, all circular buffer values can be updated through a DMA channel triggered by MC trigger. When
down-counting, all circular buffer values can be updated through a second DMA channel, triggered by the OVF DMA
request.
Figure 36-39. DMA Triggers in DSBOTH Operation Mode and Circular Buffer Enabled
Cycle
N-2
N
N-1
New Parameter Set
Old Parameter Set
"update"
COUNT
ZERO
CTRLB.DIR
DMA_CCx_req
DMA Channel i
Update Rising
DMA_OVF_req
DMA Channel j
Update Rising
36.6.5.2 Interrupts
The TCC has the following interrupt sources:
•
•
•
•
•
Overflow/Underflow (OVF)
Retrigger (TRG)
Count (CNT) - refer also to description of EVCTRL.CNTSEL.
Capture Overflow Error (ERR)
Non-Recoverable Update Fault (UFS)
© 2020 Microchip Technology Inc.
DS60001477C-page 731
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
•
•
•
•
Debug Fault State (DFS)
Recoverable Faults (FAULTn)
Non-recoverable Faults (FAULTx)
Compare Match or Capture Channels (MCx)
These interrupts are asynchronous wake-up sources. See Sleep Mode Entry and Exit Table in PM/Sleep Mode
Controller section for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a
'1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt
flag is cleared, the interrupt is disabled, or the TCC is reset. See 36.8.12 INTFLAG for details on how to clear
interrupt flags. The TCC has one common interrupt request line for all the interrupt sources. The user must read the
INTFLAG register to determine which interrupt condition is present.
Note: Interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for details.
36.6.5.3 Events
The TCC can generate the following output events:
• Overflow/Underflow (OVF)
• Trigger (TRG)
• Counter (CNT) For further details, refer to EVCTRL.CNTSEL description.
• Compare Match or Capture on compare/capture channels: MCx
Writing a '1' ('0') to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables (disables) the
corresponding output event. Refer also to EVSYS – Event System.
The TCC can take the following actions on a channel input event (MCx):
• Capture event
• Generate a recoverable or non-recoverable fault
The TCC can take the following actions on counter Event 1 (TCCx EV1):
• Counter re-trigger
• Counter direction control
• Stop the counter
• Decrement the counter on event
• Period and pulse width capture
• Non-recoverable fault
The TCC can take the following actions on counter Event 0 (TCCx EV0):
• Counter re-trigger
• Count on event (increment or decrement, depending on counter direction)
• Counter start - start counting on the event rising edge. Further events will not restart the counter; the counter will
keep on counting using prescaled GCLK_TCCx, until it reaches TOP or ZERO, depending on the direction.
• Counter increment on event. This will increment the counter, irrespective of the counter direction.
• Count during active state of an asynchronous event (increment or decrement, depending on counter direction).
In this case, the counter will be incremented or decremented on each cycle of the prescaled clock, as long as
the event is active.
• Non-recoverable fault
The counter Event Actions are available in the Event Control registers (EVCTRL.EVACT0 and EVCTRL.EVACT1).
For further details, refer to EVCTRL.
Writing a '1' ('0') to an Event Input bit in the Event Control register (EVCTRL.MCEIx or EVCTRL.TCEIx) enables
(disables) the corresponding action on input event.
© 2020 Microchip Technology Inc.
DS60001477C-page 732
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Note: When several events are connected to the TCC, the enabled action will apply for each of the incoming events.
Refer to EVSYS – Event System for details on how to configure the event system.
36.6.6
Sleep Mode Operation
The TCC can be configured to operate in any sleep mode. To be able to run in standby the RUNSTDBY bit in the
Control A register (CTRLA.RUNSTDBY) must be '1'. The MODULE can in any sleep mode wake up the device using
interrupts or perform actions through the Event System.
36.6.7
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
Software Reset and Enable bits in Control A register (CTRLA.SWRST and CTRLA.ENABLE)
The following registers are synchronized when written:
•
•
•
•
•
•
•
Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
Status register (STATUS)
Pattern and Pattern Buffer registers (PATT and PATTBUF)
Waveform register (WAVE)
Count Value register (COUNT)
Period Value and Period Buffer Value registers (PER and PERBUF)
Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and CCBUFx)
The following registers are synchronized when read:
•
•
•
•
•
•
Control B Clear and Control B Set registers (CTRLBCLR and CTRLBSET)
Count Value register (COUNT): synchronization is done on demand through READSYNC command
(CTRLBSET.CMD)
Pattern and Pattern Buffer registers (PATT and PATTBUF)
Waveform register (WAVE)
Period Value and Period Buffer Value registers (PER and PERBUF)
Compare/Capture Channel x and Channel x Compare/Capture Buffer Value registers (CCx and CCBUFx)
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
Required read-synchronization is denoted by the "Read-Synchronized" property in the register description.
For more information, refer to Register Synchronization.
© 2020 Microchip Technology Inc.
DS60001477C-page 733
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.7
Register Summary
Offset
Name
0x00
CTRLA
0x04
0x05
0x06
...
0x07
CTRLBCLR
CTRLBSET
0x08
0x0C
Bit Pos.
7:0
15:8
23:16
31:24
7:0
7:0
0x14
0x18
0x1C
...
0x1D
0x1E
0x1F
SYNCBUSY
FCTRLA
FCTRLB
WEXCTRL
DRVCTRL
DBGCTRL
Reserved
EVCTRL
0x24
INTENCLR
0x2C
0x30
CPTEN3
IDXCMD[1:0]
IDXCMD[1:0]
CMD[2:0]
CMD[2:0]
ENABLE
SWRST
PRESCALER[2:0]
RUNSTDBY
CPTEN2
ONESHOT
ONESHOT
CPTEN1
LUPD
LUPD
CPTEN0
DIR
DIR
7:0
15:8
23:16
31:24
7:0
15:8
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
PER
RESTART
BLANKPRES
C
WAVE
PATT
BLANK[1:0]
COUNT
STATUS
CC3
CTRLB
CC2
ENABLE
CC1
SWRST
CC0
QUAL
KEEP
CAPTURE[2:0]
SRC[1:0]
CHSEL[1:0]
HALT[1:0]
BLANKVAL[7:0]
FILTERVAL[3:0]
RESTART
BLANKPRES
C
BLANK[1:0]
QUAL
KEEP
CAPTURE[2:0]
SRC[1:0]
CHSEL[1:0]
HALT[1:0]
BLANKVAL[7:0]
FILTERVAL[3:0]
NRE7
NRV7
INVEN7
NRE6
NRE5
NRV6
NRV5
INVEN6
INVEN5
FILTERVAL1[3:0]
DTIEN3
DTLS[7:0]
DTHS[7:0]
NRE4
NRE3
NRV4
NRV3
INVEN4
INVEN3
DTIEN2
OTMX[1:0]
DTIEN1
DTIEN0
NRE2
NRE1
NRV2
NRV1
INVEN2
INVEN1
FILTERVAL0[3:0]
NRE0
NRV0
INVEN0
Reserved
0x20
0x28
RESOLUTION[1:0]
ALOCK
PRESCYNC[1:0]
Reserved
23:16
31:24
7:0
0x10
MSYNC
DMAOS
INTENSET
INTFLAG
STATUS
7:0
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
FDDBD
CNTSEL[1:0]
TCEI1
TCEI0
FAULT1
FAULT1
FAULT1
PERBUFV
FAULT1
© 2020 Microchip Technology Inc.
FAULT0
FAULT0
FAULT0
FAULT0
TCINV1
FAULTB
FAULTB
FAULTB
PATTBUFV
FAULTB
EVACT1[2:0]
TCINV0
FAULTA
FAULTA
FAULTA
FAULTA
DBGRUN
EVACT0[2:0]
TRGEO
MCEI1
MCEO1
TRG
OVFEO
MCEI0
MCEO0
OVF
MC1
MC0
MCEI3
MCEO3
ERR
DFS
MC3
CNTEO
MCEI2
MCEO2
CNT
UFS
MC2
ERR
DFS
MC3
CNT
UFS
MC2
TRG
OVF
MC1
MC0
ERR
DFS
MC3
CNT
UFS
MC2
TRG
OVF
MC1
MC0
DFS
FAULT1IN
CCBUFV3
CMP3
UFS
FAULT0IN
CCBUFV2
CMP2
IDX
FAULTBIN
CCBUFV1
CMP1
STOP
FAULTAIN
CCBUFV0
CMP0
DS60001477C-page 734
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
...........continued
Offset
Name
0x34
COUNT
0x38
PATT
0x3A
...
0x3B
Reserved
0x3C
0x40
0x44
0x48
0x4C
WAVE
PER
CC0
CC1
CC2
0x50
CC3
0x54
...
0x63
Reserved
0x64
PATTBUF
0x66
...
0x67
Reserved
0x68
0x6C
0x70
0x74
WAVEBUF
PERBUF
CCBUF0
CCBUF1
Bit Pos.
7:0
15:8
23:16
31:24
7:0
15:8
PGE7
PGV7
PGE6
PGV6
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CIPEREN
7:0
15:8
PGEB7
PGVB7
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CIPERENB
PGE5
PGV5
COUNT[7:0]
COUNT[15:8]
COUNT[23:16]
COUNT[31:24]
PGE4
PGE3
PGV4
PGV3
RAMP[1:0]
CICCEN3
CICCEN2
POL3
POL2
SWAP3
SWAP2
DITHER[5:0]
PER[9:2]
PER[17:10]
PER[25:18]
DITHER[5:0]
CC[9:2]
CC[17:10]
CC[25:18]
DITHER[5:0]
CC[9:2]
CC[17:10]
CC[25:18]
DITHER[5:0]
CC[9:2]
CC[17:10]
CC[25:18]
DITHER[5:0]
CC[9:2]
CC[17:10]
CC[25:18]
PER[1:0]
CC[1:0]
CC[1:0]
CC[1:0]
CC[1:0]
© 2020 Microchip Technology Inc.
PGE2
PGV2
PGEB6
PGVB6
PERBUF[1:0]
CCBUF[1:0]
CCBUF[1:0]
PGEB5
PGVB5
PGEB4
PGVB4
PGEB3
PGVB3
PGEB2
PGVB2
CICCENB3
CICCENB2
RAMPB[1:0]
SWAPB 3
SWAPB 2
DITHERBUF[5:0]
PERBUF[9:2]
PERBUF[17:10]
PERBUF[25:18]
DITHERBUF[5:0]
CCBUF[9:2]
CCBUF[17:10]
CCBUF[25:18]
DITHERBUF[5:0]
CCBUF[9:2]
CCBUF[17:10]
CCBUF[25:18]
PGE1
PGV1
PGE0
PGV0
WAVEGEN[2:0]
CICCEN1
CICCEN0
POL1
POL0
SWAP1
SWAP0
PGEB1
PGVB1
PGEB0
PGVB0
WAVEGENB[2:0]
CICCENB1
CICCENB0
SWAPB 1
SWAPB 0
DS60001477C-page 735
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
...........continued
Offset
Name
0x78
CCBUF2
0x7C
36.8
CCBUF3
Bit Pos.
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CCBUF[1:0]
CCBUF[1:0]
DITHERBUF[5:0]
CCBUF[9:2]
CCBUF[17:10]
CCBUF[25:18]
DITHERBUF[5:0]
CCBUF[9:2]
CCBUF[17:10]
CCBUF[25:18]
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
© 2020 Microchip Technology Inc.
DS60001477C-page 736
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00000000
PAC Write-Protection, Enable-Protected, Write-Synchronized (ENABLE, SWRST)
31
30
29
28
27
CPTEN3
R/W
0
26
CPTEN2
R/W
0
25
CPTEN1
R/W
0
24
CPTEN0
R/W
0
23
DMAOS
R/W
0
22
21
20
19
18
17
16
15
MSYNC
R/W
0
14
ALOCK
R/W
0
11
RUNSTDBY
R/W
0
10
8
R/W
0
9
PRESCALER[2:0]
R/W
0
R/W
0
3
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
13
12
PRESCYNC[1:0]
R/W
R/W
0
0
6
5
RESOLUTION[1:0]
R/W
R/W
0
0
4
Bits 24, 25, 26, 27 – CPTENx Capture Channel x Enable
These bits are used to select the capture or compare operation on channel x.
Writing a '1' to CPTENx enables capture on channel x.
Writing a '0' to CPTENx disables capture on channel x.
Bit 23 – DMAOS DMA One-Shot Trigger Mode
This bit enables the DMA One-shot Trigger Mode.
Writing a '1' to this bit will generate a DMA trigger on TCC cycle following a TCC_CTRLBSET_CMD_DMAOS
command.
Writing a '0' to this bit will generate DMA triggers on each TCC cycle.
This bit is not synchronized.
Bit 15 – MSYNC Master Synchronization (only for TCC slave instance)
This bit must be set if the TCC counting operation must be synchronized on its Master TCC.
This bit is not synchronized.
Value
Description
0
The TCC controls its own counter.
1
The counter is controlled by its Master TCC.
Bit 14 – ALOCK Auto Lock
This bit is not synchronized.
Value
Description
0
The Lock Update bit in the Control B register (CTRLB.LUPD) is not affected by overflow/underflow, and
re-trigger events
1
CTRLB.LUPD is set to '1' on each overflow/underflow or re-trigger event.
Bits 13:12 – PRESCYNC[1:0] Prescaler and Counter Synchronization
These bits select if on re-trigger event, the Counter is cleared or reloaded on either the next GCLK_TCCx clock, or on
the next prescaled GCLK_TCCx clock. It is also possible to reset the prescaler on re-trigger event.
© 2020 Microchip Technology Inc.
DS60001477C-page 737
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
These bits are not synchronized.
Value
Name
Description
Counter Reloaded
Prescaler
0x0
0x1
GCLK
PRESC
-
0x2
0x3
RESYNC
Reserved
Reload or reset Counter on next GCLK
Reload or reset Counter on next
prescaler clock
Reload or reset Counter on next GCLK
Reset prescaler counter
Bit 11 – RUNSTDBY Run in Standby
This bit is used to keep the TCC running in Standby mode.
This bit is not synchronized.
Value
Description
0
The TCC is halted in standby.
1
The TCC continues to run in standby.
Bits 10:8 – PRESCALER[2:0] Prescaler
These bits select the Counter prescaler factor.
These bits are not synchronized.
Value
Name
Description
0x0
DIV1
Prescaler: GCLK_TCC
0x1
DIV2
Prescaler: GCLK_TCC/2
0x2
DIV4
Prescaler: GCLK_TCC/4
0x3
DIV8
Prescaler: GCLK_TCC/8
0x4
DIV16
Prescaler: GCLK_TCC/16
0x5
DIV64
Prescaler: GCLK_TCC/64
0x6
DIV256
Prescaler: GCLK_TCC/256
0x7
DIV1024
Prescaler: GCLK_TCC/1024
Bits 6:5 – RESOLUTION[1:0] Dithering Resolution
These bits increase the TCC resolution by enabling the dithering options.
These bits are not synchronized.
Table 36-7. Dithering
Value
Name
Description
0x0
0x1
NONE
DITH4
0x2
DITH5
0x3
DITH6
The dithering is disabled.
Dithering is done every 16 PWM frames. PER[3:0] and
CCx[3:0] contain dithering pattern selection.
Dithering is done every 32 PWM frames. PER[4:0] and
CCx[4:0] contain dithering pattern selection.
Dithering is done every 64 PWM frames. PER[5:0] and
CCx[5:0] contain dithering pattern selection.
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value
written to CTRLA.ENABLE will read back immediately and the ENABLE bit in the SYNCBUSY register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value
Description
0
The peripheral is disabled.
1
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the TCC (except DBGCTRL) to their initial state, and the TCC will be
disabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 738
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Writing a '1' to CTRLA.SWRST will always take precedence; all other writes in the same write-operation will be
discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
Value
Description
0
There is no Reset operation ongoing.
1
The Reset operation is ongoing.
© 2020 Microchip Technology Inc.
DS60001477C-page 739
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.2
Control B Clear
Name:
Offset:
Reset:
Property:
CTRLBCLR
0x04
0x00
PAC Write-Protection, Write-Synchronized, Read-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Set (CTRLBSET) register.
Bit
Access
Reset
7
R/W
0
6
CMD[2:0]
R/W
0
5
R/W
0
4
3
IDXCMD[1:0]
R/W
R/W
0
0
2
ONESHOT
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 7:5 – CMD[2:0] TCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a command has
been executed, the CMD bit field will read back zero. The commands are executed on the next prescaled
GCLK_TCC clock cycle.
Writing zero to this bit group has no effect.
Writing a '1' to any of these bits will clear the pending command.
Value
Name
Description
0x0
NONE
No action
0x1
RETRIGGER
Clear start, restart or retrigger
0x2
STOP
Force stop
0x3
UPDATE
Force update of double buffered registers
0x4
READSYNC
Force COUNT read synchronization
Bits 4:3 – IDXCMD[1:0] Ramp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation. On timer/counter
update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command
is cleared.
Writing zero to these bits has no effect.
Writing a '1' to any of these bits will clear the pending command.
Value
Name
Description
0x0
DISABLE
DISABLE Command disabled: IDX toggles between cycles A and B
0x1
SET
Set IDX: cycle B will be forced in the next cycle
0x2
CLEAR
Clear IDX: cycle A will be forced in next cycle
0x3
HOLD
Hold IDX: the next cycle will be the same as the current cycle.
Bit 2 – ONESHOT One-Shot
This bit controls one-shot operation of the TCC. When one-shot operation is enabled, the TCC will stop counting on
the next overflow/underflow condition or on a stop command.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will disable the one-shot operation.
Value
Description
0
The TCC will update the counter value on overflow/underflow condition and continue operation.
1
The TCC will stop counting on the next underflow/overflow condition.
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TCC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed on hardware
UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is
performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable updating.
© 2020 Microchip Technology Inc.
DS60001477C-page 740
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Value
0
1
Description
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are copied into the
corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are not copied into the
corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
© 2020 Microchip Technology Inc.
DS60001477C-page 741
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.3
Control B Set
Name:
Offset:
Reset:
Property:
CTRLBSET
0x05
0x00
PAC Write-Protection, Write-Synchronized, Read-Synchronized
This register allows the user to change this register without doing a read-modify-write operation. Changes in this
register will also be reflected in the Control B Set (CTRLBCLR) register.
Bit
Access
Reset
7
R/W
0
6
CMD[2:0]
R/W
0
5
R/W
0
4
3
IDXCMD[1:0]
R/W
R/W
0
0
2
ONESHOT
R/W
0
1
LUPD
R/W
0
0
DIR
R/W
0
Bits 7:5 – CMD[2:0] TCC Command
These bits can be used for software control of re-triggering and stop commands of the TCC. When a command has
been executed, the CMD bit field will be read back as zero. The commands are executed on the next prescaled
GCLK_TCC clock cycle.
Writing zero to this bit group has no effect
Writing a valid value to this bit group will set the associated command.
Value
Name
Description
0x0
NONE
No action
0x1
RETRIGGER
Force start, restart or retrigger
0x2
STOP
Force stop
0x3
UPDATE
Force update of double buffered registers
0x4
READSYNC
Force a read synchronization of COUNT
Bits 4:3 – IDXCMD[1:0] Ramp Index Command
These bits can be used to force cycle A and cycle B changes in RAMP2 and RAMP2A operation. On timer/counter
update condition, the command is executed, the IDX flag in STATUS register is updated and the IDXCMD command
is cleared.
Writing a zero to these bits has no effect.
Writing a valid value to these bits will set a command.
Value
Name
Description
0x0
DISABLE
Command disabled: IDX toggles between cycles A and B
0x1
SET
Set IDX: cycle B will be forced in the next cycle
0x2
CLEAR
Clear IDX: cycle A will be forced in next cycle
0x3
HOLD
Hold IDX: the next cycle will be the same as the current cycle.
Bit 2 – ONESHOT One-Shot
This bit controls one-shot operation of the TCC. When in one-shot operation, the TCC will stop counting on the next
overflow/underflow condition or a stop command.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will enable the one-shot operation.
Value
Description
0
The TCC will count continuously.
1
The TCC will stop counting on the next underflow/overflow condition.
Bit 1 – LUPD Lock Update
This bit controls the update operation of the TCC buffered registers.
When CTRLB.LUPD is set, no any update of the registers with value of its buffered register is performed on hardware
UPDATE condition. Locking the update ensures that all buffer registers are valid before an hardware update is
performed. After all the buffer registers are loaded correctly, the buffered registers can be unlocked.
This bit has no effect when input capture operation is enabled.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will lock updating.
© 2020 Microchip Technology Inc.
DS60001477C-page 742
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Value
0
1
Description
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are copied into the
corresponding CCx, PER, PGV, PGO and SWAPx registers on hardware update condition.
The CCBx, PERB, PGVB, PGOB, and SWAPBx buffer registers values are not copied into CCx, PER,
PGV, PGO and SWAPx registers on hardware update condition.
Bit 0 – DIR Counter Direction
This bit is used to change the direction of the counter.
Writing a '0' to this bit has no effect
Writing a '1' to this bit will clear the bit and make the counter count up.
Value
Description
0
The timer/counter is counting up (incrementing).
1
The timer/counter is counting down (decrementing).
© 2020 Microchip Technology Inc.
DS60001477C-page 743
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.4
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
SYNCBUSY
0x08
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
CC3
R
0
10
CC2
R
0
9
CC1
R
0
8
CC0
R
0
7
PER
R
0
6
WAVE
R
0
5
PATT
R
0
4
COUNT
R
0
3
STATUS
R
0
2
CTRLB
R
0
1
ENABLE
R
0
0
SWRST
R
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 8, 9, 10, 11 – CC Compare/Capture Channel x Synchronization Busy
This bit is cleared when the synchronization of Compare/Capture Channel x register between the clock domains is
complete.
This bit is set when the synchronization of Compare/Capture Channel x register between clock domains is started.
CCx bit is available only for existing Compare/Capture Channels. For details on CC channels number, refer to each
TCC feature list.
This bit is set when the synchronization of CCx register between clock domains is started.
Bit 7 – PER PER Synchronization Busy
This bit is cleared when the synchronization of PER register between the clock domains is complete.
This bit is set when the synchronization of PER register between clock domains is started.
Bit 6 – WAVE WAVE Synchronization Busy
This bit is cleared when the synchronization of WAVE register between the clock domains is complete.
This bit is set when the synchronization of WAVE register between clock domains is started.
Bit 5 – PATT PATT Synchronization Busy
This bit is cleared when the synchronization of PATTERN register between the clock domains is complete.
This bit is set when the synchronization of PATTERN register between clock domains is started.
Bit 4 – COUNT COUNT Synchronization Busy
This bit is cleared when the synchronization of COUNT register between the clock domains is complete.
This bit is set when the synchronization of COUNT register between clock domains is started.
Bit 3 – STATUS STATUS Synchronization Busy
This bit is cleared when the synchronization of STATUS register between the clock domains is complete.
This bit is set when the synchronization of STATUS register between clock domains is started.
© 2020 Microchip Technology Inc.
DS60001477C-page 744
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Bit 2 – CTRLB CTRLB Synchronization Busy
This bit is cleared when the synchronization of CTRLB register between the clock domains is complete.
This bit is set when the synchronization of CTRLB register between clock domains is started.
Bit 1 – ENABLE ENABLE Synchronization Busy
This bit is cleared when the synchronization of ENABLE bit between the clock domains is complete.
This bit is set when the synchronization of ENABLE bit between clock domains is started.
Bit 0 – SWRST SWRST Synchronization Busy
This bit is cleared when the synchronization of SWRST bit between the clock domains is complete.
This bit is set when the synchronization of SWRST bit between clock domains is started.
© 2020 Microchip Technology Inc.
DS60001477C-page 745
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.5
Fault Control A and B
Name:
Offset:
Reset:
Property:
Bit
FCTRLx
0x0C + x*0x04 [x=0..1]
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
Access
Reset
23
22
21
R/W
0
R/W
0
R/W
0
14
13
CAPTURE[2:0]
R/W
0
Bit
15
BLANKPRESC
Access
R/W
Reset
0
Bit
Access
Reset
26
25
FILTERVAL[3:0]
R/W
R/W
0
0
R/W
0
Bit
Access
Reset
27
7
RESTART
R/W
0
R/W
0
6
5
BLANK[1:0]
R/W
0
R/W
0
20
19
BLANKVAL[7:0]
R/W
R/W
0
0
12
11
24
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
CHSEL[1:0]
8
HALT[1:0]
R/W
0
R/W
0
R/W
0
R/W
0
4
QUAL
R/W
0
3
KEEP
R/W
0
2
1
R/W
0
0
SRC[1:0]
R/W
0
R/W
0
Bits 27:24 – FILTERVAL[3:0] Recoverable Fault n Filter Value
These bits define the filter value applied on MCEx (x=0,1) event input line. The value must be set to zero when MCEx
event is used as synchronous event.
Bits 23:16 – BLANKVAL[7:0] Recoverable Fault n Blanking Value
These bits determine the duration of the blanking of the fault input source. Activation and edge selection of the blank
filtering are done by the BLANK bits (FCTRLn.BLANK).
When enabled, the fault input source is internally disabled for BLANKVAL* prescaled GCLK_TCC periods after the
detection of the waveform edge.
Bit 15 – BLANKPRESC Recoverable Fault n Blanking Value Prescaler
This bit enables a factor 64 prescaler factor on used as base frequency of the BLANKVAL value.
Value
Description
0
Blank time is BLANKVAL* prescaled GCLK_TCC.
1
Blank time is BLANKVAL* 64 * prescaled GCLK_TCC.
Bits 14:12 – CAPTURE[2:0] Recoverable Fault n Capture Action
These bits select the capture and Fault n interrupt/event conditions.
Table 36-8. Fault n Capture Action
Value
Name
0x0
0x1
DISABLE
CAPT
0x2
Description
Capture on valid recoverable Fault n is disabled
On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each new captured value.
CAPTMIN On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0], if COUNT value is lower than the last stored capture value (CC).
INTFLAG.FAULTn flag rises on each local minimum detection.
© 2020 Microchip Technology Inc.
DS60001477C-page 746
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
...........continued
Value
0x3
0x4
0x5
0x6
Name
Description
CAPTMAX On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0], if COUNT value is higher than the last stored capture value (CC).
INTFLAG.FAULTn flag rises on each local maximun detection.
LOCMIN On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local minimum value detection.
LOCMAX On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local maximun detection.
DERIV0 On rising edge of a valid recoverable Fault n, capture counter value on channel selected by
CHSEL[1:0]. INTFLAG.FAULTn flag rises on each local maximun or minimum detection.
Bits 11:10 – CHSEL[1:0] Recoverable Fault n Capture Channel
These bits select the channel for capture operation triggered by recoverable Fault n.
Value
Name
Description
0x0
CC0
Capture value stored into CC0
0x1
CC1
Capture value stored into CC1
0x2
CC2
Capture value stored into CC2
0x3
CC3
Capture value stored into CC3
Bits 9:8 – HALT[1:0] Recoverable Fault n Halt Operation
These bits select the halt action for recoverable Fault n.
Value
Name
Description
0x0
DISABLE
Halt action disabled
0x1
HW
Hardware halt action
0x2
SW
Software halt action
0x3
NR
Non-recoverable fault
Bit 7 – RESTART Recoverable Fault n Restart
Setting this bit enables restart action for Fault n.
Value
Description
0
Fault n restart action is disabled.
1
Fault n restart action is enabled.
Bits 6:5 – BLANK[1:0] Recoverable Fault n Blanking Operation
These bits, select the blanking start point for recoverable Fault n.
Value
Name
Description
0x0
START
Blanking applied from start of the Ramp period
0x1
RISE
Blanking applied from rising edge of the waveform output
0x2
FALL
Blanking applied from falling edge of the waveform output
0x3
BOTH
Blanking applied from each toggle of the waveform output
Bit 4 – QUAL Recoverable Fault n Qualification
Setting this bit enables the recoverable Fault n input qualification.
Value
Description
0
The recoverable Fault n input is not disabled on CMPx value condition.
1
The recoverable Fault n input is disabled when output signal is at inactive level (CMPx == 0).
Bit 3 – KEEP Recoverable Fault n Keep
Setting this bit enables the Fault n keep action.
Value
Description
0
The Fault n state is released as soon as the recoverable Fault n is released.
1
The Fault n state is released at the end of TCC cycle.
Bits 1:0 – SRC[1:0] Recoverable Fault n Source
These bits select the TCC event input for recoverable Fault n.
© 2020 Microchip Technology Inc.
DS60001477C-page 747
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Event system channel connected to MCEx event input, must be configured to route the event asynchronously, when
used as a recoverable Fault n input.
Value
Name
Description
0x0
DISABLE
Fault input disabled
0x1
ENABLE
MCEx (x=0,1) event input
0x2
INVERT
Inverted MCEx (x=0,1) event input
0x3
ALTFAULT
Alternate fault (A or B) state at the end of the previous period.
© 2020 Microchip Technology Inc.
DS60001477C-page 748
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.6
Waveform Extension Control
Name:
Offset:
Reset:
Property:
Bit
31
WEXCTRL
0x14
0x00000000
PAC Write-Protection, Enable-Protected
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
DTHS[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
DTLS[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
11
DTIEN3
R/W
0
10
DTIEN2
R/W
0
9
DTIEN1
R/W
0
8
DTIEN0
R/W
0
7
6
5
4
3
2
1
0
Access
Reset
Bit
OTMX[1:0]
Access
Reset
R/W
0
R/W
0
Bits 31:24 – DTHS[7:0] Dead-Time High Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time high side.
Bits 23:16 – DTLS[7:0] Dead-time Low Side Outputs Value
This register holds the number of GCLK_TCC clock cycles for the dead-time low side.
Bits 8, 9, 10, 11 – DTIENx Dead-time Insertion Generator x Enable
Setting any of these bits enables the dead-time insertion generator for the corresponding output matrix. This will
override the output matrix [x] and [x+WO_NUM/2], with the low side and high side waveform respectively.
Value
Description
0
No dead-time insertion override.
1
Dead time insertion override on signal outputs[x] and [x+WO_NUM/2], from matrix outputs[x] signal.
Bits 1:0 – OTMX[1:0] Output Matrix
These bits define the matrix routing of the TCC waveform generation outputs to the port pins, according to 36.6.3.8
Waveform Extension.
© 2020 Microchip Technology Inc.
DS60001477C-page 749
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.7
Driver Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
R/W
0
DRVCTRL
0x18
0x00000000
PAC Write-Protection, Enable-Protected
30
29
FILTERVAL1[3:0]
R/W
R/W
0
0
28
27
R/W
0
R/W
0
26
25
FILTERVAL0[3:0]
R/W
R/W
0
0
24
R/W
0
23
INVEN7
R/W
0
22
INVEN6
R/W
0
21
INVEN5
R/W
0
20
INVEN4
R/W
0
19
INVEN3
R/W
0
18
INVEN2
R/W
0
17
INVEN1
R/W
0
16
INVEN0
R/W
0
15
NRV7
R/W
0
14
NRV6
R/W
0
13
NRV5
R/W
0
12
NRV4
R/W
0
11
NRV3
R/W
0
10
NRV2
R/W
0
9
NRV1
R/W
0
8
NRV0
R/W
0
7
NRE7
R/W
0
6
NRE6
R/W
0
5
NRE5
R/W
0
4
NRE4
R/W
0
3
NRE3
R/W
0
2
NRE2
R/W
0
1
NRE1
R/W
0
0
NRE0
R/W
0
Bits 31:28 – FILTERVAL1[3:0] Non-Recoverable Fault Input 1 Filter Value
These bits define the filter value applied on TCE1 event input line. When the TCE1 event input line is configured as a
synchronous event, this value must be 0x0.
Bits 27:24 – FILTERVAL0[3:0] Non-Recoverable Fault Input 0 Filter Value
These bits define the filter value applied on TCE0 event input line. When the TCE0 event input line is configured as a
synchronous event, this value must be 0x0.
Bits 16, 17, 18, 19, 20, 21, 22, 23 – INVENx Waveform Output x Inversion
These bits are used to select inversion on the output of channel x.
Writing a '1' to INVENx inverts output from WO[x].
Writing a '0' to INVENx disables inversion of output from WO[x].
Bits 8, 9, 10, 11, 12, 13, 14, 15 – NRVx NRVx Non-Recoverable State x Output Value
These bits define the value of the enabled override outputs, under non-recoverable fault condition.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – NREx Non-Recoverable State x Output Enable
These bits enable the override of individual outputs by NRVx value, under non-recoverable fault condition.
Value
Description
0
Non-recoverable fault tri-state the output.
1
Non-recoverable faults set the output to NRVx level.
© 2020 Microchip Technology Inc.
DS60001477C-page 750
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.8
Debug control
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x1E
0x00
PAC Write-Protection
6
Access
Reset
5
4
3
2
FDDBD
R/W
0
1
0
DBGRUN
R/W
0
Bit 2 – FDDBD Fault Detection on Debug Break Detection
This bit is not affected by software reset and should not be changed by software while the TCC is enabled.
By default this bit is zero, and the on-chip debug (OCD) fault protection is enabled. OCD break request from the OCD
system will trigger non-recoverable fault. When this bit is set, OCD fault protection is disabled and OCD break
request will not trigger a fault.
Value
Description
0
No faults are generated when TCC is halted in debug mode.
1
A non recoverable fault is generated and FAULTD flag is set when TCC is halted in debug mode.
Bit 0 – DBGRUN Debug Running State
This bit is not affected by software reset and should not be changed by software while the TCC is enabled.
Value
Description
0
The TCC is halted when the device is halted in debug mode.
1
The TCC continues normal operation when the device is halted in debug mode.
© 2020 Microchip Technology Inc.
DS60001477C-page 751
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.9
Event Control
Name:
Offset:
Reset:
Property:
Bit
EVCTRL
0x20
0x00000000
PAC Write-Protection, Enable-Protected
31
30
29
28
27
MCEO3
R/W
0
26
MCEO2
R/W
0
25
MCEO1
R/W
0
24
MCEO0
R/W
0
23
22
21
20
19
MCEI3
R/W
0
18
MCEI2
R/W
0
17
MCEI1
R/W
0
16
MCEI0
R/W
0
15
TCEI1
R/W
0
14
TCEI0
R/W
0
13
TCINV1
R/W
0
12
TCINV0
R/W
0
11
10
CNTEO
R/W
0
9
TRGEO
R/W
0
8
OVFEO
R/W
0
5
4
EVACT1[2:0]
R/W
0
3
2
0
R/W
0
R/W
0
1
EVACT0[2:0]
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
7
6
CNTSEL[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bits 24, 25, 26, 27 – MCEOx Match or Capture Channel x Event Output Enable
These bits control if the match/capture event on channel x is enabled and will be generated for every match or
capture.
Value
Description
0
Match/capture x event is disabled and will not be generated.
1
Match/capture x event is enabled and will be generated for every compare/capture on channel x.
Bits 16, 17, 18, 19 – MCEIx Match or Capture Channel x Event Input Enable
These bits indicate if the match/capture x incoming event is enabled
These bits are used to enable match or capture input events to the CCx channel of TCC.
Value
Description
0
Incoming events are disabled.
1
Incoming events are enabled.
Bits 14, 15 – TCEIx Timer/Counter Event Input x Enable
This bit is used to enable input event x to the TCC.
Value
Description
0
Incoming event x is disabled.
1
Incoming event x is enabled.
Bits 12, 13 – TCINVx Timer/Counter Event x Invert Enable
This bit inverts the event x input.
Value
Description
0
Input event source x is not inverted.
1
Input event source x is inverted.
Bit 10 – CNTEO Timer/Counter Event Output Enable
This bit is used to enable the counter cycle event. When enabled, an event will be generated on begin or end of
counter cycle depending of CNTSEL[1:0] settings.
© 2020 Microchip Technology Inc.
DS60001477C-page 752
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Value
0
1
Description
Counter cycle output event is disabled and will not be generated.
Counter cycle output event is enabled and will be generated depend of CNTSEL[1:0] value.
Bit 9 – TRGEO Retrigger Event Output Enable
This bit is used to enable the counter retrigger event. When enabled, an event will be generated when the counter
retriggers operation.
Value
Description
0
Counter retrigger event is disabled and will not be generated.
1
Counter retrigger event is enabled and will be generated for every counter retrigger.
Bit 8 – OVFEO Overflow/Underflow Event Output Enable
This bit is used to enable the overflow/underflow event. When enabled an event will be generated when the counter
reaches the TOP or the ZERO value.
Value
Description
0
Overflow/underflow counter event is disabled and will not be generated.
1
Overflow/underflow counter event is enabled and will be generated for every counter overflow/
underflow.
Bits 7:6 – CNTSEL[1:0] Timer/Counter Interrupt and Event Output Selection
These bits define on which part of the counter cycle the counter event output is generated.
Value
Name
Description
0x0
BEGIN
An interrupt/event is generated at begin of each counter cycle
0x1
END
An interrupt/event is generated at end of each counter cycle
0x2
BETWEEN An interrupt/event is generated between each counter cycle.
0x3
BOUNDARY An interrupt/event is generated at begin of first counter cycle, and end of last counter
cycle.
Bits 5:3 – EVACT1[2:0] Timer/Counter Event Input 1 Action
These bits define the action the TCC will perform on TCE1 event input.
Value
Name
Description
0x0
OFF
Event action disabled.
0x1
RETRIGGER
Start, restart or re-trigger TC on event
0x2
DIR (asynch)
Direction control
0x3
STOP
Stop TC on event
0x4
DEC
Decrement TC on event
0x5
PPW
Period captured into CC0 Pulse Width on CC1
0x6
PWP
Period captured into CC1 Pulse Width on CC0
0x7
FAULT
Non-recoverable Fault
Bits 2:0 – EVACT0[2:0] Timer/Counter Event Input 0 Action
These bits define the action the TCC will perform on TCE0 event input 0.
Value
Name
Description
0x0
OFF
Event action disabled.
0x1
RETRIGGER
Start, restart or re-trigger TC on event
0x2
COUNTEV
Count on event.
0x3
START
Start TC on event
0x4
INC
Increment TC on EVENT
0x5
COUNT (async)
Count on active state of asynchronous event
0x6
STAMP
Capture overflow times (Max value)
0x7
FAULT
Non-recoverable Fault
© 2020 Microchip Technology Inc.
DS60001477C-page 753
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.10 Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x24
0x00000000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
MC3
R/W
0
18
MC2
R/W
0
17
MC1
R/W
0
16
MC0
R/W
0
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
0
12
FAULTA
R/W
0
11
DFS
R/W
0
10
UFS
R/W
0
9
8
7
6
5
4
3
ERR
R/W
0
2
CNT
R/W
0
1
TRG
R/W
0
0
OVF
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19 – MCx Match or Capture Channel x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
disables the Match or Capture Channel x interrupt.
Value
Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 15 – FAULT1 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the NonRecoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 14 – FAULT0 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the NonRecoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 13 – FAULTB Recoverable Fault B Interrupt Enable
Writing a '0' to this bit has no effect.
© 2020 Microchip Technology Inc.
DS60001477C-page 754
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Writing a '1' to this bit will clear the Recoverable Fault B Interrupt Disable/Enable bit, which disables the Recoverable
Fault B interrupt.
Value
Description
0
The Recoverable Fault B interrupt is disabled.
1
The Recoverable Fault B interrupt is enabled.
Bit 12 – FAULTA Recoverable Fault A Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Recoverable Fault A Interrupt Disable/Enable bit, which disables the Recoverable
Fault A interrupt.
Value
Description
0
The Recoverable Fault A interrupt is disabled.
1
The Recoverable Fault A interrupt is enabled.
Bit 11 – DFS Non-Recoverable Debug Fault Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Debug Fault State Interrupt Disable/Enable bit, which disables the Debug Fault
State interrupt.
Value
Description
0
The Debug Fault State interrupt is disabled.
1
The Debug Fault State interrupt is enabled.
Bit 10 – UFS Non-Recoverable Update Fault Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Non-Recoverable Update Fault Interrupt Disable/Enable bit, which disables the
Non-Recoverable Update Fault interrupt.
Value
Description
0
The Non-Recoverable Update Fault interrupt is disabled.
1
The Non-Recoverable Update Fault interrupt is enabled.
Bit 3 – ERR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Error Interrupt Disable/Enable bit, which disables the Compare interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 2 – CNT Counter Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Counter Interrupt Disable/Enable bit, which disables the Counter interrupt.
Value
Description
0
The Counter interrupt is disabled.
1
The Counter interrupt is enabled.
Bit 1 – TRG Retrigger Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Retrigger Interrupt Disable/Enable bit, which disables the Retrigger interrupt.
Value
Description
0
The Retrigger interrupt is disabled.
1
The Retrigger interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overflow Interrupt Disable/Enable bit, which disables the Overflow interrupt
request.
Value
Description
0
The Overflow interrupt is disabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 755
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Value
1
Description
The Overflow interrupt is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 756
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.11 Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x28
0x00000000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
31
30
29
28
27
26
25
24
23
22
21
20
19
MC3
R/W
0
18
MC2
R/W
0
17
MC1
R/W
0
16
MC0
R/W
0
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
0
12
FAULTA
R/W
0
11
DFS
R/W
0
10
UFS
R/W
0
9
8
7
6
5
4
3
ERR
R/W
0
2
CNT
R/W
0
1
TRG
R/W
0
0
OVF
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19 – MCx Match or Capture Channel x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the corresponding Match or Capture Channel x Interrupt Disable/Enable bit, which
enables the Match or Capture Channel x interrupt.
Value
Description
0
The Match or Capture Channel x interrupt is disabled.
1
The Match or Capture Channel x interrupt is enabled.
Bit 15 – FAULT1 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Non-Recoverable Fault x Interrupt Disable/Enable bit, which enables the NonRecoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 14 – FAULT0 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt Disable/Enable bit, which disables the NonRecoverable Fault x interrupt.
Value
Description
0
The Non-Recoverable Fault x interrupt is disabled.
1
The Non-Recoverable Fault x interrupt is enabled.
Bit 13 – FAULTB Recoverable Fault B Interrupt Enable
Writing a '0' to this bit has no effect.
© 2020 Microchip Technology Inc.
DS60001477C-page 757
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Writing a '1' to this bit will set the Recoverable Fault B Interrupt Disable/Enable bit, which enables the Recoverable
Fault B interrupt.
Value
Description
0
The Recoverable Fault B interrupt is disabled.
1
The Recoverable Fault B interrupt is enabled.
Bit 12 – FAULTA Recoverable Fault A Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Recoverable Fault A Interrupt Disable/Enable bit, which enables the Recoverable
Fault A interrupt.
Value
Description
0
The Recoverable Fault A interrupt is disabled.
1
The Recoverable Fault A interrupt is enabled.
Bit 11 – DFS Non-Recoverable Debug Fault Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Debug Fault State Interrupt Disable/Enable bit, which enables the Debug Fault
State interrupt.
Value
Description
0
The Debug Fault State interrupt is disabled.
1
The Debug Fault State interrupt is enabled.
Bit 10 – UFS Non-Recoverable Update Fault Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Non-Recoverable Update Fault Interrupt Disable/Enable bit, which enables the
Non-Recoverable Update Fault interrupt.
Value
Description
0
The Non-Recoverable Update Fault interrupt is disabled.
1
The Non-Recoverable Update Fault interrupt is enabled.
Bit 3 – ERR Error Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Error Interrupt Disable/Enable bit, which enables the Compare interrupt.
Value
Description
0
The Error interrupt is disabled.
1
The Error interrupt is enabled.
Bit 2 – CNT Counter Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Counter interrupt.
Value
Description
0
The Counter interrupt is disabled.
1
The Counter interrupt is enabled.
Bit 1 – TRG Retrigger Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Retrigger Interrupt Disable/Enable bit, which enables the Retrigger interrupt.
Value
Description
0
The Retrigger interrupt is disabled.
1
The Retrigger interrupt is enabled.
Bit 0 – OVF Overflow Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overflow Interrupt Disable/Enable bit, which enables the Overflow interrupt request.
Value
Description
0
The Overflow interrupt is disabled.
1
The Overflow interrupt is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 758
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.12 Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x2C
0x00000000
-
31
30
29
28
27
26
25
24
23
22
21
20
19
MC3
R/W
0
18
MC2
R/W
0
17
MC1
R/W
0
16
MC0
R/W
0
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
0
12
FAULTA
R/W
0
11
DFS
R/W
0
10
UFS
R/W
0
9
8
7
6
5
4
3
ERR
R/W
0
2
CNT
R/W
0
1
TRG
R/W
0
0
OVF
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 16, 17, 18, 19 – MCx Match or Capture Channel x Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a match with the compare condition or once CCx register
contain a valid capture value.
Writing a '0' to one of these bits has no effect.
Writing a '1' to one of these bits will clear the corresponding Match or Capture Channel x interrupt flag
In Capture operation, this flag is automatically cleared when CCx register is read.
Bit 15 – FAULT1 Non-Recoverable Fault x Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Non-Recoverable Fault x occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Non-Recoverable Fault x interrupt flag.
Bit 14 – FAULT0 Non-Recoverable Fault x Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Non-Recoverable Fault x Interrupt flag.
Bit 13 – FAULTB Recoverable Fault B Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Recoverable Fault B interrupt flag.
Bit 12 – FAULTA Recoverable Fault A Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a Recoverable Fault B occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Recoverable Fault B interrupt flag.
Bit 11 – DFS Non-Recoverable Debug Fault State Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after an Debug Fault State occurs.
Writing a '0' to this bit has no effect.
© 2020 Microchip Technology Inc.
DS60001477C-page 759
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Writing a '1' to this bit clears the Debug Fault State interrupt flag.
Bit 10 – UFS Non-Recoverable Update Fault
This flag is set when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD).
Writing a zero to this bit has no effect.
Writing a one to this bit clears the Non-Recoverable Update Fault interrupt flag.
Bit 3 – ERR Error Interrupt Flag
This flag is set if a new capture occurs on a channel when the corresponding Match or Capture Channel x interrupt
flag is one. In which case there is nowhere to store the new capture.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the error interrupt flag.
Bit 2 – CNT Counter Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a counter event occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the CNT interrupt flag.
Bit 1 – TRG Retrigger Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after a counter retrigger occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the re-trigger interrupt flag.
Bit 0 – OVF Overflow Interrupt Flag
This flag is set on the next CLK_TCC_COUNT cycle after an overflow condition occurs.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overflow interrupt flag.
© 2020 Microchip Technology Inc.
DS60001477C-page 760
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.13 Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x30
0x00000001
Read-Synchronized, Write-Synchronized
31
30
29
28
27
CMP3
R/W
0
26
CMP2
R/W
0
25
CMP1
R/W
0
24
CMP0
R/W
0
23
22
21
20
19
CCBUFV3
R/W
0
18
CCBUFV2
R/W
0
17
CCBUFV1
R/W
0
16
CCBUFV0
R/W
0
15
FAULT1
R/W
0
14
FAULT0
R/W
0
13
FAULTB
R/W
0
12
FAULTA
R/W
0
11
FAULT1IN
R
0
10
FAULT0IN
R
0
9
FAULTBIN
R
0
8
FAULTAIN
R
0
7
PERBUFV
R/W
0
6
5
PATTBUFV
R/W
0
4
3
DFS
R/W
0
2
UFS
R/W
0
1
IDX
R
0
0
STOP
R
1
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bits 24, 25, 26, 27 – CMPx Channel x Compare Value
This bit reflects the channel x output compare value.
Value
Description
0
Channel compare output value is 0.
1
Channel compare output value is 1.
Bits 16, 17, 18, 19 – CCBUFVx Channel x Compare or Capture Buffer Valid
For a compare channel, this bit is set when a new value is written to the corresponding CCBUFx register. The bit is
cleared either by writing a '1' to the corresponding location when CTRLB.LUPD is set, or automatically on an
UPDATE condition.
For a capture channel, the bit is set when a valid capture value is stored in the CCBUFx register. The bit is
automatically cleared when the CCx register is read.
Bits 14, 15 – FAULTx Non-recoverable Fault x State
This bit is set by hardware as soon as non-recoverable Fault x condition occurs.
This bit is cleared by writing a one to this bit and when the corresponding FAULTxIN status bit is low.
Once this bit is clear, the timer/counter will restart from the last COUNT value. To restart the timer/counter from
BOTTOM, the timer/counter restart command must be executed before clearing the corresponding STATEx bit. For
further details on timer/counter commands, refer to available commands description (36.8.3 CTRLBSET.CMD).
Bit 13 – FAULTB Recoverable Fault B State
This bit is set by hardware as soon as recoverable Fault B condition occurs.
This bit can be clear by hardware when Fault B action is resumed, or by writing a '1' to this bit when the
corresponding FAULTBIN bit is low. If software halt command is enabled (FAULTB.HALT=SW), clearing this bit will
release the timer/counter.
Bit 12 – FAULTA Recoverable Fault A State
This bit is set by hardware as soon as recoverable Fault A condition occurs.
© 2020 Microchip Technology Inc.
DS60001477C-page 761
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
This bit can be clear by hardware when Fault A action is resumed, or by writing a '1' to this bit when the
corresponding FAULTAIN bit is low. If software halt command is enabled (FAULTA.HALT=SW), clearing this bit will
release the timer/counter.
Bit 11 – FAULT1IN Non-Recoverable Fault 1 Input
This bit is set while an active Non-Recoverable Fault 1 input is present.
Bit 10 – FAULT0IN Non-Recoverable Fault 0 Input
This bit is set while an active Non-Recoverable Fault 0 input is present.
Bit 9 – FAULTBIN Recoverable Fault B Input
This bit is set while an active Recoverable Fault B input is present.
Bit 8 – FAULTAIN Recoverable Fault A Input
This bit is set while an active Recoverable Fault A input is present.
Bit 7 – PERBUFV Period Buffer Valid
This bit is set when a new value is written to the PERBUF register. This bit is automatically cleared by hardware on
UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit.
Bit 5 – PATTBUFV Pattern Generator Value Buffer Valid
This bit is set when a new value is written to the PATTBUF register. This bit is automatically cleared by hardware on
UPDATE condition when CTRLB.LUPD is set, or by writing a '1' to this bit.
Bit 3 – DFS Debug Fault State
This bit is set by hardware in Debug mode when DDBGCTRL.FDDBD bit is set. The bit is cleared by writing a '1' to
this bit and when the TCC is not in Debug mode.
When the bit is set, the counter is halted and the Waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV
registers.
Bit 2 – UFS Non-recoverable Update Fault State
This bit is set by hardware when the RAMP index changes and the Lock Update bit is set (CTRLBSET.LUPD). The bit
is cleared by writing a one to this bit.
When the bit is set, the waveforms state depend on DRVCTRL.NRE and DRVCTRL.NRV registers.
Bit 1 – IDX Ramp Index
In RAMP2 and RAMP2A operation, the bit is cleared during the cycle A and set during the cycle B. In RAMP1
operation, the bit always reads zero. For details on ramp operations, refer to 36.6.3.4 Ramp Operations.
Bit 0 – STOP Stop
This bit is set when the TCC is disabled either on a STOP command or on an UPDATE condition when One-Shot
operation mode is enabled (CTRLBSET.ONESHOT=1).
This bit is clear on the next incoming counter increment or decrement.
Value
Description
0
Counter is running.
1
Counter is stopped.
© 2020 Microchip Technology Inc.
DS60001477C-page 762
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.14 Counter Value
Name:
Offset:
Reset:
Property:
COUNT
0x34
0x00000000
PAC Write-Protection, Write-Synchronized, Read-Synchronized
Note: Prior to any read access, this register must be synchronized by user by writing the according TCC Command
value to the Control B Set register (CTRLBSET.CMD=READSYNC).
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
COUNT[31:24]
R/W
R/W
0
0
20
19
COUNT[23:16]
R/W
R/W
0
0
12
11
COUNT[15:8]
R/W
R/W
0
0
4
3
COUNT[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – COUNT[31:0] Counter Value
These bits hold the value of the counter register.
Note: When the TCC is configured as 24- or 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [31:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [31:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
31:0 (depicted)
31:4
31:5
31:6
© 2020 Microchip Technology Inc.
DS60001477C-page 763
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.15 Pattern
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
PATT
0x38
0x0000
Write-Synchronized
15
PGV7
R/W
0
14
PGV6
R/W
0
13
PGV5
R/W
0
12
PGV4
R/W
0
11
PGV3
R/W
0
10
PGV2
R/W
0
9
PGV1
R/W
0
8
PGV0
R/W
0
7
PGE7
R/W
0
6
PGE6
R/W
0
5
PGE5
R/W
0
4
PGE4
R/W
0
3
PGE3
R/W
0
2
PGE2
R/W
0
1
PGE1
R/W
0
0
PGE0
R/W
0
Bits 8, 9, 10, 11, 12, 13, 14, 15 – PGV Pattern Generation Output Value
This register holds the values of pattern for each waveform output.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PGE Pattern Generation Output Enable
This register holds the enable status of pattern generation for each waveform output. A bit written to '1' will override
the corresponding SWAP output with the corresponding PGVn value.
© 2020 Microchip Technology Inc.
DS60001477C-page 764
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.16 Waveform
Name:
Offset:
Reset:
Property:
Bit
WAVE
0x3C
0x00000000
Write-Synchronized
31
30
29
28
27
SWAP3
R/W
0
26
SWAP2
R/W
0
25
SWAP1
R/W
0
24
SWAP0
R/W
0
23
22
21
20
19
POL3
R/W
0
18
POL2
R/W
0
17
POL1
R/W
0
16
POL0
R/W
0
15
14
13
12
11
CICCEN3
R/W
0
10
CICCEN2
R/W
0
9
CICCEN1
R/W
0
8
CICCEN0
R/W
0
7
CIPEREN
R/W
0
6
5
4
3
2
1
WAVEGEN[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
RAMP[1:0]
R/W
0
R/W
0
R/W
0
R/W
0
Bits 24, 25, 26, 27 – SWAP Swap DTI Output Pair x
Setting these bits enables output swap of DTI outputs [x] and [x+WO_NUM/2]. Note the DTIxEN settings will not
affect the swap operation.
Bits 16, 17, 18, 19 – POL Channel Polarity x
Setting these bits enables the output polarity in single-slope and dual-slope PWM operations.
Value
Name
Description
0
(single-slope PWM waveform
Compare output is initialized to ~DIR and set to DIR when TCC
generation)
counter matches CCx value
1
(single-slope PWM waveform
Compare output is initialized to DIR and set to ~DIR when TCC
generation)
counter matches CCx value.
0
(dual-slope PWM waveform
Compare output is set to ~DIR when TCC counter matches CCx
generation)
value
1
(dual-slope PWM waveform
Compare output is set to DIR when TCC counter matches CCx
generation)
value.
Bits 8, 9, 10, 11 – CICCEN Circular CC Enable x
Setting this bits enables the compare circular buffer option on channel. When the bit is set, CCx register value is
copied-back into the CCx register on UPDATE condition.
Bit 7 – CIPEREN Circular Period Enable
Setting this bits enable the period circular buffer option. When the bit is set, the PER register value is copied-back
into the PERB register on UPDATE condition.
Bits 5:4 – RAMP[1:0] Ramp Operation
These bits select Ramp operation (RAMP). These bits are not synchronized.
Value
Name
Description
0x0
RAMP1
RAMP1 operation
0x1
RAMP2A
Alternative RAMP2 operation
© 2020 Microchip Technology Inc.
DS60001477C-page 765
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Value
0x2
0x3
Name
RAMP2
RAMP2C
Description
RAMP2 operation
Critical RAMP2 operation
Bits 2:0 – WAVEGEN[2:0] Waveform Generation Operation
These bits select the waveform generation operation. The settings impact the top value and control if frequency or
PWM waveform generation should be used. These bits are not synchronized.
Value
Name
Description
Operation
Top
Update
Waveform Output
On Match
Waveform Output
On Update
OVFIF/Event
Up Down
0x0
NFRQ
Normal Frequency
PER
TOP/Zero
Toggle
Stable
TOP
0x1
MFRQ
Match Frequency
CC0
TOP/Zero
Toggle
Stable
TOP
Zero
Zero
0x2
NPWM
Normal PWM
PER
TOP/Zero
Set
Clear
TOP
Zero
0x3
Reserved
–
–
–
–
–
–
–
0x4
DSCRITICAL
Dual-slope PWM
PER
Zero
~DIR
Stable
–
Zero
0x5
DSBOTTOM
Dual-slope PWM
PER
Zero
~DIR
Stable
–
Zero
0x6
DSBOTH
Dual-slope PWM
PER
TOP & Zero
~DIR
Stable
TOP
Zero
0x7
DSTOP
Dual-slope PWM
PER
Zero
~DIR
Stable
TOP
–
© 2020 Microchip Technology Inc.
DS60001477C-page 766
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.17 Period Value
Name:
Offset:
Reset:
Property:
Bit
PER
0x40
0xFFFFFFFF
Write-Synchronized
31
30
29
28
27
26
25
24
R/W
1
R/W
1
R/W
1
R/W
1
19
18
17
16
R/W
1
R/W
1
R/W
1
R/W
1
11
10
9
8
R/W
1
R/W
1
R/W
1
1
0
R/W
1
R/W
1
PER[25:18]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
23
22
21
20
PER[17:10]
Access
Reset
Bit
R/W
1
R/W
1
R/W
1
R/W
1
15
14
13
12
PER[9:2]
Access
Reset
Bit
R/W
1
7
R/W
1
R/W
1
R/W
1
R/W
1
6
5
4
3
R/W
1
R/W
1
R/W
1
PER[1:0]
Access
Reset
R/W
1
2
DITHER[5:0]
R/W
R/W
1
1
Bits 31:6 – PER[25:0] Period Value
These bits hold the value of the period register.
Note: When the TCC is configured as 16- or 24-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register. m is dependent on the Resolution bit in the Control A register
(CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [31:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
31:0
31:4
31:5
31:6 (depicted)
Bits 5:0 – DITHER[5:0] Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse period every 64 PWM frames.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
3:0
4:0
5:0 (depicted)
© 2020 Microchip Technology Inc.
DS60001477C-page 767
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.18 Compare/Capture Channel x
Name:
Offset:
Reset:
Property:
CCx
0x44 + x*0x04 [x=0..3]
0x00000000
Write-Synchronized, Read-Synchronized
The CCx register represents the 16-, 24- or 32-bit value, CCx. The register has two functions, depending of the mode
of operation.
For capture operation, this register represents the second buffer level and access point for the CPU and DMA.
For compare operation, this register is continuously compared to the counter value. Normally, the output form the
comparator is then used for generating waveforms.
CCx register is updated with the buffer value from their corresponding CCBUFx register when an UPDATE condition
occurs.
In addition, in match frequency operation, the CC0 register controls the counter period.
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
R/W
0
R/W
0
19
18
17
16
R/W
0
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
1
0
R/W
0
R/W
0
CC[25:18]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
23
22
21
20
CC[17:10]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
15
14
13
12
CC[9:2]
Access
Reset
Bit
R/W
0
7
R/W
0
R/W
0
R/W
0
R/W
0
6
5
4
3
R/W
0
R/W
0
R/W
0
CC[1:0]
Access
Reset
R/W
0
2
DITHER[5:0]
R/W
R/W
0
0
Bits 23:6 – CC[17:0] Channel x Compare/Capture Value
These bits hold the value of the Channel x compare/capture register.
Note: When the TCC is configured as 16-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the m MSB of the register, [23:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [23:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
23:0
23:4
23:5
23:6 (depicted)
Bits 31:6 – CC[25:0] Channel x Compare/Capture Value
These bits hold the value of the Channel x compare/capture register.
Note: When the TCC is configured as 16- or 24-bit timer/counter, the excess bits are read zero.
© 2020 Microchip Technology Inc.
DS60001477C-page 768
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
Note: This bit field occupies the MSB of the register, [31:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [31:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
31:0
31:4
31:5
31:6 (depicted)
Bits 5:0 – DITHER[5:0] Dithering Cycle Number
These bits hold the number of extra cycles that are added on the PWM pulse width every 64 PWM frames.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
3:0
4:0
5:0 (depicted)
© 2020 Microchip Technology Inc.
DS60001477C-page 769
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.19 Pattern Buffer
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
PATTBUF
0x64
0x0000
Write-Synchronized, Read-Synchronized
15
PGVB7
R/W
0
14
PGVB6
R/W
0
13
PGVB5
R/W
0
12
PGVB4
R/W
0
11
PGVB3
R/W
0
10
PGVB2
R/W
0
9
PGVB1
R/W
0
8
PGVB0
R/W
0
7
PGEB7
R/W
0
6
PGEB6
R/W
0
5
PGEB5
R/W
0
4
PGEB4
R/W
0
3
PGEB3
R/W
0
2
PGEB2
R/W
0
1
PGEB1
R/W
0
0
PGEB0
R/W
0
Bits 8, 9, 10, 11, 12, 13, 14, 15 – PGVB Pattern Generation Output Value Buffer
This register is the buffer for the PGV register. If double buffering is used, valid content in this register is copied to the
PGV register on an UPDATE condition.
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PGEB Pattern Generation Output Enable Buffer
This register is the buffer of the PGE register. If double buffering is used, valid content in this register is copied into
the PGE register at an UPDATE condition.
© 2020 Microchip Technology Inc.
DS60001477C-page 770
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.20 Waveform Buffer
Name:
Offset:
Reset:
Property:
Bit
WAVEBUF
0x68 [ID-00002e48]
0x00000000
Write-Synchronized, Read-Synchronized
31
30
29
28
27
SWAPB 3
R/W
0
26
SWAPB 2
R/W
0
25
SWAPB 1
R/W
0
24
SWAPB 0
R/W
0
23
22
21
20
19
18
17
16
15
14
13
12
11
CICCENB3
R/W
0
10
CICCENB2
R/W
0
9
CICCENB1
R/W
0
8
CICCENB0
R/W
0
7
CIPERENB
R/W
0
6
5
3
2
1
WAVEGENB[2:0]
R/W
0
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
4
RAMPB[1:0]
R/W
R/W
0
0
R/W
0
R/W
0
Bits 24, 25, 26, 27 – SWAPB Swap DTI output pair x Buffer
These register bits are the buffer bits for the SWAP register bits. If double buffering is used, valid content in these bits
is copied to the corresponding SWAPx bits on an UPDATE condition.
Bits 8, 9, 10, 11 – CICCENB Circular CCx Buffer Enable
These register bits are the buffer bits for CICCENx register bits. If double buffering is used, valid content in these bits
is copied to the corresponding CICCENx bits on a UPDATE condition.
Bit 7 – CIPERENB Circular Period Enable Buffer
This register bit is the buffer bit for CIPEREN register bit. If double buffering is used, valid content in this bit is copied
to the corresponding CIPEREN bit on a UPDATE condition.
Bits 5:4 – RAMPB[1:0] Ramp Operation Buffer
These register bits are the buffer bits for RAMP register bits. If double buffering is used, valid content in these bits is
copied to the corresponding RAMP bits on a UPDATE condition.
Bits 2:0 – WAVEGENB[2:0] Waveform Generation Operation Buffer
These register bits are the buffer bits for WAVEGEN register bits. If double buffering is used, valid content in these
bits is copied to the corresponding WAVEGEN bits on a UPDATE condition.
© 2020 Microchip Technology Inc.
DS60001477C-page 771
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.21 Period Buffer Value
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
PERBUF
0x6C
0xFFFFFFFF
Write-Synchronized, Read-Synchronized
31
30
29
R/W
1
R/W
1
R/W
1
23
22
21
R/W
1
R/W
1
R/W
1
15
14
13
R/W
1
R/W
1
R/W
1
7
6
PERBUF[1:0]
R/W
R/W
1
1
28
27
PERBUF[25:18]
R/W
R/W
1
1
20
19
PERBUF[17:10]
R/W
R/W
1
1
12
11
PERBUF[9:2]
R/W
R/W
1
1
5
4
R/W
1
R/W
1
26
25
24
R/W
1
R/W
1
R/W
1
18
17
16
R/W
1
R/W
1
R/W
1
10
9
8
R/W
1
R/W
1
R/W
1
1
0
R/W
1
R/W
1
3
2
DITHERBUF[5:0]
R/W
R/W
1
1
Bits 31:6 – PERBUF[25:0] Period Buffer Value
These bits hold the value of the period buffer register. The value is copied to PER register on UPDATE condition.
Note: When the TCC is configured as 16- or 24-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [31:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [31:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
31:0
31:4
31:5
31:6 (depicted)
Bits 5:0 – DITHERBUF[5:0] Dithering Buffer Cycle Number
These bits represent the PER.DITHER bits buffer. When the double buffering is enabled, the value of this bit field is
copied to the PER.DITHER bits on an UPDATE condition.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
3:0
4:0
5:0 (depicted)
© 2020 Microchip Technology Inc.
DS60001477C-page 772
SAM L21 Family Data Sheet
TCC – Timer/Counter for Control Applications
36.8.22 Channel x Compare/Capture Buffer Value
Name:
Offset:
Reset:
Property:
CCBUF
0x70 + n*0x04 [n=0..3]
0x00000000
Write-Synchronized, Read-Synchronized
CCBUFx is copied into CCx at TCC update time
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
CCBUF[1:0]
R/W
R/W
0
0
28
27
CCBUF[25:18]
R/W
R/W
0
0
20
19
CCBUF[17:10]
R/W
R/W
0
0
12
11
CCBUF[9:2]
R/W
R/W
0
0
5
4
R/W
0
R/W
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
1
0
R/W
0
R/W
0
3
2
DITHERBUF[5:0]
R/W
R/W
0
0
Bits 31:6 – CCBUF[25:0] Channel x Compare/Capture Buffer Value
These bits hold the value of the Channel x Compare/Capture Buffer Value register. The register serves as the buffer
for the associated compare or capture registers (CCx). Accessing this register using the CPU or DMA will affect the
corresponding CCBUFVx status bit.
Note: When the TCC is configured as 16- or 24-bit timer/counter, the excess bits are read zero.
Note: This bit field occupies the MSB of the register, [31:m]. m is dependent on the Resolution bit in the Control A
register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [31:m]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
31:0
31:4
31:5
31:6 (depicted)
Bits 5:0 – DITHERBUF[5:0] Dithering Buffer Cycle Number
These bits represent the CCx.DITHER bits buffer. When the double buffering is enable, DITHERBUF bits value is
copied to the CCx.DITHER bits on an UPDATE condition.
Note: This bit field consists of the n LSB of the register. n is dependent on the value of the Resolution bits in the
Control A register (CTRLA.RESOLUTION):
CTRLA.RESOLUTION
Bits [n:0]
0x0 - NONE
0x1 - DITH4
0x2 - DITH5
0x3 - DITH6
3:0
4:0
5:0 (depicted)
© 2020 Microchip Technology Inc.
DS60001477C-page 773
SAM L21 Family Data Sheet
TRNG – True Random Number Generator
37.
TRNG – True Random Number Generator
37.1
Overview
The True Random Number Generator (TRNG) generates unpredictable random numbers that are not generated by
an algorithm. It passes the American NIST Special Publication 800-22 and Diehard Random Tests Suites.
The TRNG may be used as an entropy source for seeding an NIST approved DRNG (Deterministic RNG) as required
by FIPS PUB 140-2 and 140-3.
37.2
Features
•
•
•
•
37.3
Passed NIST Special Publication 800-22 Tests Suite
Passed Diehard Random Tests Suite
May be used as Entropy Source for seeding an NIST approved DRNG (Deterministic RNG) as required by FIPS
PUB 140-2 and 140-3
Provides a 32-bit random number every 84 clock cycles
Block Diagram
Figure 37-1. TRNG Block Diagram.
TRNG
Control Logic
MCLK
User Interface
Interrupt
Controller
Event
Controller
Entropy Source
APB
37.4
Signal Description
Not applicable.
37.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
37.5.1
I/O Lines
Not applicable.
37.5.2
Power Management
The TRNG will continue to operate in any sleep mode, as long as its source clock is running. The TRNG interrupts
can be used to wake up the device from sleep modes. Events connected to the event system can trigger other
operations in the system without exiting sleep modes.
© 2020 Microchip Technology Inc.
DS60001477C-page 774
SAM L21 Family Data Sheet
TRNG – True Random Number Generator
37.5.3
Clocks
The TRNG bus clock (CLK_TRNG_APB) can be enabled and disabled in the 18. MCLK – Main Clock, and the
default state of CLK_TRNG_APB can be found in Peripheral Clock Masking.
37.5.4
DMA
Not applicable.
37.5.5
Interrupts
The interrupt request line is connected to the interrupt controller. Using the TRNG interrupt(s) requires the interrupt
controller to be configured first. Refer to the 12.2 Nested Vector Interrupt Controller for details.
37.5.6
Events
The events are connected to the Event System. Refer to EVSYS – Event System for details on how to configure the
Event System.
37.5.7
Debug Operation
When the CPU is halted in debug mode the TRNG continues normal operation. If the TRNG is configured in a way
that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss
may result during debugging.
37.5.8
Register Access Protection
All registers with write-access are optionally write-protected by the Peripheral Access Controller (PAC), except the
following register:
Interrupt Flag Status and Clear (INTFLAG) register
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
37.5.9
Analog Connections
Not applicable.
37.6
Functional Description
37.6.1
Principle of Operation
As soon as the TRNG is enabled, the module automatically provides a new 32-bit random number every 84
CLK_TRNG_APB clock cycles. When new data is available, an optional interrupt or event can be generated.
Figure 37-2. TRNG Data Generation Sequence
Clock
trng_cr
enable
84 clock cycles
84 clock cycles
84 clock cycles
trng_int
© 2020 Microchip Technology Inc.
Read TRNG_ISR
Read TRNG_ISR
Read TRNG_ODATA
Read TRNG_ODATA
DS60001477C-page 775
SAM L21 Family Data Sheet
TRNG – True Random Number Generator
37.6.2
Basic Operation
37.6.2.1 Initialization
The following register is enable-protected, meaning that it can only be written when the TRNG is disabled
(CTRLA.ENABLE is zero):
Event Control register (EVCTRL)
Enable-protection is denoted by the Enable-Protected property in the register description.
37.6.2.2 Enabling, Disabling and Resetting
The TRNG is enabled by writing '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The TRNG is
disabled by writing a zero to CTRLA.ENABLE.
37.6.3
Interrupts
The TRNG has the following interrupt source:
•
Data Ready(DATARDY): Indicates that a new random data is available in DATA register and ready to be read.
This interrupt is a synchronous wake-up source. See Sleep Mode Controller for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a
'1' to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a '1' to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register.
An interrupt request is generated when the interrupt flag is set and the corresponding interrupt is enabled. The
interrupt request remains active until the interrupt flag is cleared, or the interrupt is disabled. See 37.8.5 INTFLAG or
details on how to clear interrupt flags. All interrupt requests from the peripheral are ORed together on system level to
generate one combined interrupt request to the NVIC. Refer to the 12.2 Nested Vector Interrupt Controller for details.
The user must read the INTFLAG register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to the 12.2 Nested Vector
Interrupt Controller for details.
37.6.4
Events
The TRNG can generate the following output event:
•
Data Ready (DATARDY): Generated when a new random number is available in the DATA register.
Writing '1' to an Event Output bit in the Event Control Register (EVCTRL.xxEO) enables the corresponding output
event. Writing a '0' to this bit disables the corresponding output event. Refer to EVSYS – Event System for details on
configuring the Event System.
37.6.5
Sleep Mode Operation
The Run in Standby bit in Control A register (CTRLA.RUNSTDBY) controls the behavior of the TRNG during standby
sleep mode:
When this bit is '0', the TRNG is disabled during sleep, but maintains its current configuration.
When this bit is '1', the TRNG continues to operate during sleep and any enabled TRNG interrupt source can wake
up the CPU.
37.6.6
Synchronization
Not applicable.
© 2020 Microchip Technology Inc.
DS60001477C-page 776
SAM L21 Family Data Sheet
TRNG – True Random Number Generator
37.7
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
...
0x03
0x04
0x05
...
0x07
0x08
0x09
0x0A
0x0B
...
0x1F
CTRLA
7:0
0x20
37.8
RUNSTDBY
ENABLE
Reserved
EVCTRL
7:0
DATARDYEO
7:0
7:0
7:0
DATARDY
DATARDY
DATARDY
Reserved
INTENCLR
INTENSET
INTFLAG
Reserved
DATA
7:0
15:8
23:16
31:24
DATA[7:0]
DATA[15:8]
DATA[23:16]
DATA[31:24]
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
Refer to PAC - Peripheral Access Controller and 37.6.6 Synchronizationfor details.
© 2020 Microchip Technology Inc.
DS60001477C-page 777
SAM L21 Family Data Sheet
TRNG – True Random Number Generator
37.8.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRLA
0x00
0x00
PAC Write-Protection
6
RUNSTDBY
R/W
0
5
4
3
2
1
ENABLE
R/W
0
0
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the ADC behaves during standby sleep mode:
Value
Description
0
The TRNG is halted during standby sleep mode.
1
The TRNG is not stopped in standby sleep mode.
Bit 1 – ENABLE Enable
Value
Description
0
The TRNG is disabled.
1
The TRNG is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 778
SAM L21 Family Data Sheet
TRNG – True Random Number Generator
37.8.2
Event Control
Name:
Offset:
Reset:
Property:
Bit
7
EVCTRL
0x04
0x00
PAC Write-Protection
6
Access
Reset
5
4
3
2
1
0
DATARDYEO
R/W
0
Bit 0 – DATARDYEO Data Ready Event Output
This bit indicates whether the Data Ready event output is enabled or not and an output event will be generated when
a new random value is completed.
Value
Description
0
Data Ready event output is disabled and an event will not be generated.
1
Data Ready event output is enabled and an event will be generated.
© 2020 Microchip Technology Inc.
DS60001477C-page 779
SAM L21 Family Data Sheet
TRNG – True Random Number Generator
37.8.3
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x08
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
7
6
Access
Reset
5
4
3
2
1
0
DATARDY
R/W
0
Bit 0 – DATARDY Data Ready Interrupt Enable
Writing a '1' to this bit will clear the Data Ready Interrupt Enable bit, which disables the corresponding interrupt
request.
Value
Description
0
The DATARDY interrupt is disabled.
1
The DATARDY interrupt is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 780
SAM L21 Family Data Sheet
TRNG – True Random Number Generator
37.8.4
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x09
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
7
6
Access
Reset
5
4
3
2
1
0
DATARDY
R/W
0
Bit 0 – DATARDY Data Ready Interrupt Enable
Writing a '1' to this bit will set the Data Ready Interrupt Enable bit, which enables the corresponding interrupt request.
Value
Description
0
The DATARDY interrupt is disabled.
1
The DATARDY interrupt is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 781
SAM L21 Family Data Sheet
TRNG – True Random Number Generator
37.8.5
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x0A
0x00
-
6
5
4
3
2
1
Access
Reset
0
DATARDY
R/W
0
Bit 0 – DATARDY Data Ready
This flag is set when a new random value is generated, and an interrupt will be generated if INTENCLR/
SET.DATARDY=1.
This flag is cleared by writing a '1' to the flag or by reading the DATA register.
Writing a '0' to this bit has no effect.
© 2020 Microchip Technology Inc.
DS60001477C-page 782
SAM L21 Family Data Sheet
TRNG – True Random Number Generator
37.8.6
Output Data
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
DATA
0x20
0x00000000
-
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
DATA[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
20
19
DATA[23:16]
R/W
R/W
0
0
12
DATA[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
DATA[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DATA[31:0] Output Data
These bits hold the 32-bit randomly generated output data.
© 2020 Microchip Technology Inc.
DS60001477C-page 783
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.
AES – Advanced Encryption Standard
38.1
Overview
The Advanced Encryption Standard peripheral (AES) provides a means for symmetric-key encryption of 128-bit
blocks, in compliance to NIST specifications.
A symmetric-key algorithm requires the same key for both encryption and decryption.
Different key sizes are supported. The key size determines the number of repetitions of transformation rounds that
convert the input (called the "plaintext") into the final output ("ciphertext"). The number of rounds of repetition is as
follows:
• 10 rounds of repetition for 128-bit keys
• 12 rounds of repetition for 192-bit keys
• 14 rounds of repetition for 256-bit keys
38.2
Features
•
•
•
•
•
•
•
•
•
•
•
•
Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
128/192/256 bit cryptographic key supported
Encryption time of 57/67/77 cycles with 128-bit/192-bit/256-bit cryptographic key
Five confidentiality modes of operation as recommended in NIST Special Publication 800-38A
Electronic Code Book (ECB)
Cipher Block Chaining (CBC)
Cipher Feedback (CFB)
Output Feedback (OFB)
Counter (CTR)
Supports Counter with CBC-MAC (CCM/CCM*) mode for authenticated encryption
8, 16, 32, 64, 128-bit data sizes possible in CFB mode
Optional (parameter) Galois Counter mode (GCM) encryption and authentication
© 2020 Microchip Technology Inc.
DS60001477C-page 784
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.3
Block Diagram
ENCRYPTION
PLAINTEXT
CIPHERTEXT
ADD ROUND KEY
ADD ROUND KEY
SUBBYTES
INV SHIFT ROWS
SHIFT ROWS
Nr-1 rounds
MIX COLUMNS
ADD ROUND KEY
DECRYPTION ROUND
ENCRYPTION ROUND
Figure 38-1. AES Block Diagram
DECRYPTION
ADD ROUND KEY
INV SHIFT ROWS
FINAL ROUND
FINAL ROUND
38.4
Nr-1 rounds
INV MIX COLUMNS
SUBBYTES
SHIFT ROWS
INV SUBBYTES
INV SUBBYTES
ADD ROUND KEY
ADD ROUND KEY
CIPHERTEXT
PLAINTEXT
Signal Description
Not applicable.
38.5
Product Dependencies
In order to use this AES module, other parts of the system must be configured correctly, as described below.
38.5.1
I/O Lines
Not applicable.
© 2020 Microchip Technology Inc.
DS60001477C-page 785
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.5.2
Power Management
The AES will continue to operate in any sleep mode, if it's source clock is running. The AES interrupts can be used to
wake up the device from sleep modes. Refer to the Power Manager chapter for details on the different sleep modes.
AES is clocked only on the following conditions:
•
•
38.5.3
Whenever there is an APB access for any read and write operation to the AES registers.
When the AES is enabled & encryption/decryption is on.
Clocks
The AES bus clock (CLK_AES_APB) can be enabled and disabled in the 18. MCLK – Main Clock, and the default
state of CLK_AES_APB can be found in Peripheral Clock Masking. The module is fully clocked by CLK_AES_APB.
38.5.4
DMA
The AES has two DMA request lines; one for input data, and one for output data. They are both connected to the
DMA Controller (DMAC). These DMA request triggers will be acknowledged by the DMAC ACK signals. Using the
AES DMA requests requires the DMA Controller to be configured first. Refer to the device DMA documentation.
38.5.5
Interrupts
The interrupt request line is connected to the interrupt controller. Using the AES interrupt requires the interrupt
controller to be configured first. Refer to the Processor and Architecture chapter for details.
All the AES interrupts are synchronous wake-up sources. See Sleep Mode Controller for details.
38.5.6
Events
Not applicable.
38.5.7
Debug Operation
When the CPU is halted in debug mode, the AES module continues normal operation. If the AES module is
configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper
operation or data loss may result during debugging. The AES module can be forced to halt operation during
debugging.
38.5.8
Register Access Protection
All registers with write-access are optionally write-protected by the PAC - Peripheral Access Controller, except the
following register:
•
Interrupt Flag Register (INTFLAG)
Write-protection is denoted by the Write-Protected property in the register description.
Write-protection does not apply to accesses through an external debugger. Refer to the PAC - Peripheral Access
Controller chapter for details.
38.5.9
Analog Connections
Not applicable.
38.6
38.6.1
Functional Description
Principle of Operation
The following is a high level description of the algorithm. These are the steps:
•
•
•
KeyExpansion: Round keys are derived from the cipher key using Rijndael's key schedule.
InitialRound:
– AddRoundKey: Each byte of the state is combined with the round key using bitwise XOR.
Rounds:
© 2020 Microchip Technology Inc.
DS60001477C-page 786
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
•
– SubBytes: A non-linear substitution step where each byte is replaced with another according to a lookup
table.
– ShiftRows: A transposition step where each row of the state is shifted cyclically a certain number of steps.
– MixColumns: A mixing operation which operates on the columns of the state, combining the four bytes in
each column.
– AddRoundKey
Final Round (no MixColumns):
– SubBytes
– ShiftRows
– AddRoundKey
The relationship between the module's clock frequency and throughput (in bytes per second) is given by:
Clock Frequency = (Throughput/2) x (Nr+1) for 2 byte parallel processing
Clock Frequency = (Throughput/4) x (Nr+1) for 4 byte parallel processing
where Nr is the number of rounds, depending on the key length.
38.6.2
Basic Operation
38.6.2.1 Initialization
The following register is enable-protected:
•
Control A (CTRLA)
Enable-protection is denoted by the Enable-Protected property in the register description.
38.6.2.2 Enabling, Disabling, and Resetting
The AES module is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The
module is disabled by writing a zero to CTRLA.ENABLE. The module is reset by writing a one to the Software Reset
bit in the Control A register (CTRLA.SWRST).
38.6.2.3 Basic Programming
The CIPHER bit in the Control A Register (CTRLA.CIPHER) allows selection between the encryption and the
decryption processes. The AES is capable of using cryptographic keys of 128/192/256 bits to encrypt and decrypt
data in blocks of 128 bits. The Key Size (128/192/256) can be programmed in the KEYSIZE field in the Control A
Register (CTRLA.KEYSIZE). This 128-bit/192-bit/256-bit key is defined in the Key Word Registers (KEYWORD). By
setting the XORKEY bit of CTRLA register, keyword can be updated with the resulting XOR value of user keyword
and previous keyword content.
The input data for processing is written to a data buffer consisting of four 32-bit registers through the Data register
address. The data buffer register (note that input and output data shares the same data buffer register) that is written
to when the next write is performed is indicated by the Data Pointer in the Data Buffer Pointer (DATABUFPTR)
register. This field is incremented by one or wrapped by hardware when a write to the DATA register address is
performed. This field can also be programmed, allowing the user direct control over which input buffer register to
write to. Note that when AES module is in the CFB operation mode with the data segment size less than 128 bits, the
input data must be written to the first (DATABUFPTR = 0) and/or second (DATABUFPTR = 1) input buffer registers
(see Table 38-1).
The input to the encryption processes of the CBC, CFB and OFB modes includes, in addition to the plaintext, a 128bit data block called the Initialization Vector (IV), which must be set in the Initialization Vector Registers (INTVECT).
Additionally, the GCM mode 128-bit authentication data needs to be programmed. The Initialization Vector is used in
the initial step in the encryption of a message and in the corresponding decryption of the message. The Initialization
Vector Registers are also used by the Counter mode to set the counter value.
It is necessary to notify AES module whenever the next data block it is going to process is the beginning of a new
message. This is done by writing a one to the New Message bit in the Control B register (CTRLB.NEWMSG).
The AES modes of operation are selected by setting the AESMODE field in the Control A Register
(CTRLA.AESMODE). In Cipher Feedback Mode (CFB), five data sizes are possible (8, 16, 32, 64 or 128 bits),
configurable by means of the CFBS field in the Control A Register (CTRLA.CFBS). In Counter mode, the size of the
block counter embedded in the module is 16 bits. Therefore, there is a rollover after processing 1 megabyte of data.
© 2020 Microchip Technology Inc.
DS60001477C-page 787
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
The data pre-processing, post-processing and data chaining for the concerned modes are automatically performed
by the module.
When data processing has completed, the Encryption Complete bit in the Interrupt Flag register (INTFLAG.ENCCMP)
is set by hardware (which triggers an interrupt request if the corresponding interrupt is enabled). The processed
output data is read out through the Output Data register (DATA) address from the data buffer consisting of four 32-bit
registers. The data buffer register that is read from when the next read is performed is indicated by the Data Pointer
field in the Data Buffer Pointer register (DATABUFPTR). This field is incremented by one or wrapped by hardware
when a read from the DATA register address is performed. This field can also be programmed, giving the user direct
control over which output buffer register to read from. Note that when AES module is in the CFB operation mode with
the data segment size less than 128 bits, the output data must be read from the first (DATABUFPTR = 0) and/or
second (DATABUFPTR = 1) output buffer registers (see Table 38-1). The Encryption Complete bit
(INTFLAG.ENCCMP) is cleared by hardware after the processed data has been read from the relevant output buffer
registers.
Table 38-1. Relevant Input/Output Data Registers for Different Confidentiality Modes
Confidentiality Mode
Relevant Input / Output Data Registers
ECB
All
CBC
All
OFB
All
128-bit CFB
All
64-bit CFB
First and Second
32-bit CFB
First
16-bit CFB
First
8-bit CFB
First
CTR
All
38.6.2.4 Start Modes
The Start mode field in the Control A Register (CTRLA.STARTMODE) allows the selection of encryption start mode.
1.
2.
3.
Manual Start Mode
In the Manual Start Mode the sequence is as follows:
1.1.
Write the 128/192/256 bit key in the Key Register (KEYWORD)
1.2.
Write the initialization vector or counter in the Initialization Vector Register (INTVECT). The
initialization vector concerns all modes except ECB
1.3.
Enable interrupts in Interrupt Enable Set Register (INTENSET), depending on whether an interrupt is
required or not at the end of processing.
1.4.
Write the data to be encrypted or decrypted in the Data Registers (DATA).
1.5.
Set the START bit in Control B Register (CTRLB.START) to begin the encryption or the decryption
process.
1.6.
When the processing completes, the Encryption Complete bit in the Interrupt Flag Register
(INTFLAG.ENCCMP) raises. If Encryption Complete interrupt has been enabled, the interrupt line of
the AES is activated.
1.7.
When the software reads one of the Output Data Registers (DATA), INTFLAG.ENCCMP bit is
automatically cleared.
Auto start Mode
The Auto Start Mode is similar to the manual one, except in this mode, as soon as the correct number of input
data registers is written, processing is automatically started without setting the START bit in the Control B
Register. DMA operation uses this mode.
Last Output Data Mode (LOD)
This mode is used to generate message authentication code (MAC) on data in CCM mode of operation. The
CCM mode combines counter mode for encryption and CBC-MAC generation for authentication.
© 2020 Microchip Technology Inc.
DS60001477C-page 788
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
When LOD is disabled in CCM mode then counter mode of encryption is performed on the input data block.
When LOD is enabled in CCM mode then CBC-MAC generation is performed. Zero block is used as the initialization
vector by the hardware. Also software read from the Output Data Register (DATA) is not required to clear the
ENCCMP flag. The ENCCMP flag is automatically cleared by writing into the Input Data Register (DATA). This allows
retrieval of only the last data in several encryption/decryption processes. No output data register reads are necessary
between each block of encryption/decryption process.
Note that assembling message depending on the security level identifier in CCM* has to be done in software.
38.6.2.5 Computation of last Nk words of expanded key
The AES algorithm takes the cryptographic key provided by the user and performs a Key Expansion routine to
generate an expanded key. The expanded key contains a total of 4(Nr + 1) 32-bit words, where the first Nk (4/6/8 for
a 128-/192-/256-bit key) words are the user-provided key. For data encryption, the expanded key is used in the
forward direction, i.e., the first four words are used in the initial round of data processing, the second four words in the
first round, the third four words in the second round, and so on. On the other hand, for data decryption, the expanded
key is used in the reverse direction, i.e.,the last four words are used in the initial round of data processing, the last
second four words in the first round, the last third four words in the second round, and so on.
To reduce gate count, the AES module does not generate and store the entire expanded key prior to data processing.
Instead, it computes on-the-fly the round key (four 32-bit words) required for the current round of data processing. In
general, the round key for the current round of data processing can be computed from the Nk words of the expanded
key generated in the previous rounds. When AES module is operating in the encryption mode, the round key for the
initial round of data processing is simply the user-provided key written to the KEY registers. On the other hand, when
AES module is operating in the decryption mode, the round key for the initial round of data processing is the last four
words of the expanded key, which is not available unless AES module has performed at least one encryption process
prior to operating in the decryption mode.
In general, the last Nk words of the expanded key must be available before decryption can start. If desired, AES
module can be instructed to compute the last Nk words of the expanded key in advance by writing a one to the Key
Generate (KEYGEN) bit in the CTRLA register (CTRLA.KEYGEN). The computation takes Nr clock cycles.
Alternatively, the last Nk words of the expanded key can be automatically computed by AES module when a
decryption process is initiated if they have not been computed in advance or have become invalid. Note that this will
introduce a latency of Nr clock cycles to the first decryption process.
38.6.2.6 Hardware Countermeasures against Differential Power Analysis Attacks
The AES module features four types of hardware countermeasures that are useful for protecting data against
differential power analysis attacks:
•
•
•
•
Type 1: Randomly add one cycle to data processing
Type 2: Randomly add one cycle to data processing (other version)
Type 3: Add a random number of clock cycles to data processing, subject to a maximum of 11/13/15 clock
cycles for key sizes of 128/192/256 bits
Type 4: Add random spurious power consumption during data processing
By default, all countermeasures are enabled, but require a write in the DRNGSEED register to be effective. One or
more of the countermeasures can be disabled by programming the Countermeasure Type field in the Control A
(CTRLA.CTYPE) register. The countermeasures use random numbers generated by a deterministic random number
generator embedded in AES module. The seed for the random number generator is written to the RANDSEED
register. Note also that a new seed must be written after a change in the keysize. Note that enabling
countermeasures reduces AES module’s throughput. In short, the throughput is highest with all the countermeasures
disabled. On the other hand, with all of the countermeasures enabled, the best protection is achieved but the
throughput is worst.
38.6.3
Galois Counter Mode (GCM)
GCM is comprised of the AES engine in CTR mode along with a universal hash function (GHASH engine) that is
defined over a binary Galois field to produce a message authentication tag. The GHASH engine processes data
packets after the AES operation. GCM provides assurance of the confidentiality of data through the AES Counter
mode of operation for encryption. Authenticity of the confidential data is assured through the GHASH engine. Refer to
the NIST Special Publication 800-38D Recommendation for more complete information.
© 2020 Microchip Technology Inc.
DS60001477C-page 789
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
Counter 0
Incr32
CIPH(K)
Counter 1
Incr32
CIPH(K)
Plaintext 1
Encryption
GF128Mult(H)
Auth Data 1
+
Counter 2
CIPH(K)
Plaintext 2
+
Ciphertext 1
Ciphertext 2
+
+
GF128Mult(H)
GF128Mult(H)
Len (A) || Len (C)
+
GF128Mult(H)
+
Authentication
© 2020 Microchip Technology Inc.
Auth Tag
DS60001477C-page 790
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.6.3.1 GCM Operation
Hashkey Generation
• Configure CTRLA register as follows:
1. CTRLA.STARTMODE as Manual (Auto for DMAC)
2. CTRLA.CIPHER as Encryption
3. CTRLA.KEYSIZE as per the key used
4. CTRLA.AESMODE as ECB
5. CTRLA.CTYPE as per the countermeasures required.
• Set CTRLA.ENABLE
• Write zero to CIPLEN reg.
• Write the key in KEYWORD register
• Write the zeros to DATA reg
• Set CTRLB.Start.
• Wait for INTFLAG.ENCCMP to be set
• AES Hardware generates Hash Subkey in HASHKEY register.
Authentication Header Processing
• Configure CTRLA register as follows:
1. CTRLA.STARTMODE as Manual
2. CTRLA.CIPHER as Encryption
3. CTRLA.KEYSIZE as per the key used
4. CTRLA.AESMODE as GCM
5. CTRLA.CTYPE as per the countermeasures required.
• Set CTRLA.ENABLE
• Write the key in KEYWORD register
• Set CTRLB.GFMUL
• Write the Authdata to DATA reg
• Set CTRLB.START as1
• Wait for INTFLAG.GFMCMP to be set.
• AES Hardware generates output in GHASH register
• Continue steps 4 to 7 for remaining Authentication Header.
Note: If the Auth data is less than 128 bit, it has to be padded with zero to make it 128 bit aligned.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
GHASH
AUTHDAT
+
GF128Mult(H)
GHASH
Plain Text Processing
• Set CTRLB.NEWMSG for the new set of plain text processing.
• Load CIPLEN reg.
• Load (J0+1) in INTVECT register.
• As described in NIST documentation J 0 = IV || 0 31 || 1 when len(IV)=96 and J0 =GHASHH (IV || 0 s+64 ||
[len(IV)] 64 ) (s is the minimum number of zeroes that should be padded with the Initialization Vector to make it a
multiple of 128) if len(IV) != 96.
• Load plain text in DATA register.
• Set CTRLB.START as 1.
• Wait for INTFLAG.ENCCMP to be set.
• AES Hardware generates output in DATA register.
• Intermediate GHASH is stored in GHASH register and Cipher Text available in DATA register.
• Continue 3 to 6 till the input of plain text to get the cipher text and the Hash keys.
• At the last input, set CTRLB.EOM.
• Write last in-data to DATA reg.
• Set CTRLB.START as 1.
• Wait for INTFLAG.ENCCMP to be set.
• AES Hardware generates output in DATA register and final Hash key in GHASH register.
• Load [LEN(A)]64||[LEN(C)]64 in DATA register and set CTRLB.GFMUL and CTRLB.START as 1.
• Wait for INTFLAG.GFMCMP to be set.
• AES Hardware generates final GHASH value in GHASH register.
Plain text processing with DMAC
• Set CTRLB.NEWMSG for the new set of plain text processing.
• Load CIPLEN reg.
• Load (J0+1) in INTVECT register.
• Load plain text in DATA register.
• Wait for INTFLAG.ENCCMP to be set.
• AES Hardware generates output in DATA register.
• Intermediate GHASH is stored in GHASH register and Cipher Text available in DATA register.
• Continue 3 to 5 till the input of plain text to get the cipher text and the Hash keys.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
•
•
•
•
•
•
•
At the last input, set CTRLB.EOM.
Write last in-data to DATA reg.
Wait for INTFLAG.ENCCMP to be set.
AES Hardware generates output in DATA register and final Hash key in GHASH register.
Load [LEN(A)]64||[LEN(C)]64 in DATA register and set CTRLB.GFMUL and CTRLB.START as 1.
Wait for INTFLAG.GFMCMP to be set.
AES Hardware generates final GHASH value in GHASH register.
Tag Generation
• Configure CTRLA
1. Set CTRLA.ENABLE to 0
2. Set CTRLA.AESMODE as CTR
3. Set CTRLA.ENABLE to 1
• Load J0 value to INITVECTV reg.
• Load GHASH value to DATA reg.
• Set CTRLB.NEWMSG and CTRLB.START to start the Counter mode operation.
• Wait for INTFLAG.ENCCMP to be set.
• AES Hardware generates the GCM Tag output in DATA register.
38.6.4
Synchronization
Not applicable.
© 2020 Microchip Technology Inc.
DS60001477C-page 793
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.7
Register Summary
Offset
Name
0x00
CTRLA
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
...
0x0B
CTRLB
INTENCLR
INTENSET
INTFLAG
DATABUFPTR
DBGCTRL
Bit Pos.
7:0
15:8
23:16
31:24
7:0
7:0
7:0
7:0
7:0
7:0
CFBS[2:0]
XORKEY
KEYGEN
LOD
AESMODE[2:0]
STARTMODE
GFMUL
ENABLE
SWRST
CIPHER
KEYSIZE[1:0]
CTYPE[3:0]
EOM
NEWMSG
START
GFMCMP
ENCCMP
GFMCMP
ENCCMP
GFMCMP
ENCCMP
INDATAPTR[1:0]
DBGRUN
Reserved
0C
KEYWORD0
10
KEYWORD1
14
KEYWORD2
18
KEYWORD3
1C
KEYWORD4
20
KEYWORD5
24
KEYWORD6
28
KEYWORD7
0x2C
...
0x37
Reserved
0x38
INDATA
3C
INTVECT0
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
KEYWORD[7:0]
KEYWORD[15:8]
KEYWORD[23:16]
KEYWORD[31:24]
KEYWORD[7:0]
KEYWORD[15:8]
KEYWORD[23:16]
KEYWORD[31:24]
KEYWORD[7:0]
KEYWORD[15:8]
KEYWORD[23:16]
KEYWORD[31:24]
KEYWORD[7:0]
KEYWORD[15:8]
KEYWORD[23:16]
KEYWORD[31:24]
KEYWORD[7:0]
KEYWORD[15:8]
KEYWORD[23:16]
KEYWORD[31:24]
KEYWORD[7:0]
KEYWORD[15:8]
KEYWORD[23:16]
KEYWORD[31:24]
KEYWORD[7:0]
KEYWORD[15:8]
KEYWORD[23:16]
KEYWORD[31:24]
KEYWORD[7:0]
KEYWORD[15:8]
KEYWORD[23:16]
KEYWORD[31:24]
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
INDATA[7:0]
INDATA[15:8]
INDATA[23:16]
INDATA[31:24]
INTVECT[7:0]
INTVECT[15:8]
INTVECT[23:16]
INTVECT[31:24]
© 2020 Microchip Technology Inc.
DS60001477C-page 794
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
...........continued
Offset
Name
40
INTVECT1
44
INTVECT2
48
INTVECT3
0x4C
...
0x5B
Reserved
0x5C
HASHKEY0
0x60
HASHKEY1
0x64
HASHKEY2
0x68
HASHKEY3
0x6C
GHASH0
0x70
GHASH1
0x74
GHASH2
0x78
GHASH3
0x7C
...
0x7F
Reserved
80
CIPLEN
0x84
RANDSEED
Bit Pos.
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
INTVECT[7:0]
INTVECT[15:8]
INTVECT[23:16]
INTVECT[31:24]
INTVECT[7:0]
INTVECT[15:8]
INTVECT[23:16]
INTVECT[31:24]
INTVECT[7:0]
INTVECT[15:8]
INTVECT[23:16]
INTVECT[31:24]
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
HASHKEY[7:0]
HASHKEY[15:8]
HASHKEY[23:16]
HASHKEY[31:24]
HASHKEY[7:0]
HASHKEY[15:8]
HASHKEY[23:16]
HASHKEY[31:24]
HASHKEY[7:0]
HASHKEY[15:8]
HASHKEY[23:16]
HASHKEY[31:24]
HASHKEY[7:0]
HASHKEY[15:8]
HASHKEY[23:16]
HASHKEY[31:24]
GHASH[7:0]
GHASH[15:8]
GHASH[23:16]
GHASH[31:24]
GHASH[7:0]
GHASH[15:8]
GHASH[23:16]
GHASH[31:24]
GHASH[7:0]
GHASH[15:8]
GHASH[23:16]
GHASH[31:24]
GHASH[7:0]
GHASH[15:8]
GHASH[23:16]
GHASH[31:24]
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
CIPLEN[7:0]
CIPLEN[15:8]
CIPLEN[23:16]
CIPLEN[31:24]
RANDSEED[7:0]
RANDSEED[15:8]
RANDSEED[23:16]
RANDSEED[31:24]
© 2020 Microchip Technology Inc.
DS60001477C-page 795
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
Refer to PAC - Peripheral Access Controller and 37.6.6 Synchronizationfor details.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.1
Control A
Name:
Offset:
Reset:
Property:
Bit
CTRLA
0x00
0x00000000
PAC Write-Protection, Enable-protected
31
30
29
28
27
26
23
22
21
20
19
18
25
24
17
16
R/W
0
Access
Reset
Bit
CTYPE[3:0]
Access
Reset
Bit
Access
Reset
R/W
0
R/W
0
9
15
14
XORKEY
R/W
0
13
KEYGEN
R/W
0
12
LOD
R/W
0
11
STARTMODE
R/W
0
10
CIPHER
R/W
0
7
6
CFBS[2:0]
R/W
0
5
4
2
R/W
0
R/W
0
3
AESMODE[2:0]
R/W
0
Access
Reset
Bit
R/W
0
R/W
0
Bits 19:16 – CTYPE[3:0] Countermeasure type
Value
Name
XXX0
CTYPE1 disabled
XXX1
CTYPE1 enabled
XX0X
CTYPE2 disabled
XX1X
CTYPE2 enabled
X0XX
CTYPE3 disabled
X1XX
CTYPE3 enabled
0XXX
CTYPE4 disabled
1XXX
CTYPE4 enabled
R/W
0
8
KEYSIZE[1:0]
R/W
R/W
0
0
1
ENABLE
R/W
0
0
SWRST
R/W
0
Description
Countermeasure1 disabled
Countermeasure1 enabled
Countermeasure2 disabled
Countermeasure2 enabled
Countermeasure3 disabled
Countermeasure3 enabled
Countermeasure4 disabled
Countermeasure4 enabled
Bit 14 – XORKEY XOR Key
Value
Description
0
No effect
1
The user keyword gets XORed with the previous keyword register content.
Bit 13 – KEYGEN Key Generation
Value
Description
0
No effect
1
Start Computation of the last NK words of the expanded key
Bit 12 – LOD Last Output Data Mode
Value
Description
0
No effect
1
Start encryption in Last Output Data mode
Bit 11 – STARTMODE Start Mode Select
© 2020 Microchip Technology Inc.
DS60001477C-page 797
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
Value
0
1
Name
Manual Mode
Auto Mode
Description
Start Encryption / Decryption in Manual mode
Start Encryption / Decryption in Auto mode
Bit 10 – CIPHER Encryption/ Decryption
Value
Description
0
Decryption
1
Encryption
Bits 9:8 – KEYSIZE[1:0] Encryption Key Size
Value
Name
Description
0
128-bit Key
128-bit Key for Encryption / Decryption
1
192-bit Key
192-bit Key for Encryption / Decryption
2
256-bit Key
256-bit Key for Encryption / Decryption
3
Reserved
Reserved
Bits 7:5 – CFBS[2:0] Cipher Feedback Block Size
Value
Name
Description
0
128-bit data block 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode
1
64-bit data block
64-bit Input data block for Encryption/Decryption in Cipher Feedback mode
2
32-bit data block
32-bit Input data block for Encryption/Decryption in Cipher Feedback mode
3
16-bit data block
16-bit Input data block for Encryption/Decryption in Cipher Feedback mode
4
8-bit data block
8-bit Input data block for Encryption/Decryption in Cipher Feedback mode
5-7
Reserved
Reserved
Bits 4:2 – AESMODE[2:0] AES Modes of Operation
Value
Name
Description
0
ECB
Electronic code book mode
1
CBC
Cipher block chaining mode
2
OFB
Output feedback mode
3
CFB
Cipher feedback mode
4
Counter
Counter mode
5
CCM
CCM mode
6
GCM
Galois counter mode
7
Reserved
Reserved
Bit 1 – ENABLE Enable
Value
Description
0
The peripheral is disabled
1
The peripheral is enabled
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the AES module to their initial state, and the module will be disabled.
Writing a '1' to SWRST will always take precedence, meaning that all other writes in the same write operation will be
discarded.
Value
Description
0
There is no reset operation ongoing
1
The reset operation is ongoing
© 2020 Microchip Technology Inc.
DS60001477C-page 798
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.2
Control B
Name:
Offset:
Reset:
Property:
Bit
7
CTRLB
0x04
0x00
PAC Write-Protection
6
5
4
Access
Reset
3
GFMUL
R/W
0
2
EOM
R/W
0
1
NEWMSG
R/W
0
0
START
R/W
0
Bit 3 – GFMUL GF Multiplication
This bit is applicable only to GCM mode.
Value
Description
0
No action
1
Setting this bit calculates GF multiplication with data buffer content and hashkey register content.
Bit 2 – EOM End of Message
This bit is applicable only to GCM mode.
Value
Description
0
No action
1
Setting this bit generates final GHASH value for the message.
Bit 1 – NEWMSG New Message
This bit is used in cipher block chaining (CBC), cipher feedback (CFB) and output feedback (OFB), counter (CTR)
modes to indicate the hardware to use Initialization vector for encrypting the first block of message.
Value
Description
0
No action
1
Setting this bit indicates start of new message to the module.
Bit 0 – START Start Encryption/Decryption
Value
Description
0
No action
1
Start encryption / decryption in manual mode.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.3
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x05
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
7
6
Access
Reset
5
4
3
2
1
GFMCMP
R/W
0
0
ENCCMP
R/W
0
Bit 1 – GFMCMP GF Multiplication Complete Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the GF Multiplication Complete Interrupt Enable bit, which disables the GF
Multiplication Complete interrupt.
Value
Description
0
The GF Multiplication Complete interrupt is disabled.
1
The GF Multiplication Complete interrupt is enabled.
Bit 0 – ENCCMP Encryption Complete Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Encryption Complete Interrupt Enable bit, which disables the Encryption Complete
interrupt.
Value
Description
0
The Encryption Complete interrupt is disabled.
1
The Encryption Complete interrupt is enabled.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.4
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x06
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
7
6
Access
Reset
5
4
3
2
1
GFMCMP
R/W
0
0
ENCCMP
R/W
0
Bit 1 – GFMCMP GF Multiplication Complete Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the GF Multiplication Complete Interrupt Enable
bit, which enables the GF Multiplication Complete interrupt.
Value
Description
0
The GF Multiplication Complete interrupt is disabled.
1
The GF Multiplication Complete interrupt is enabled.
Bit 0 – ENCCMP Encryption Complete Interrupt Enable
Writing a '0' to this bit has no effect. Writing a '1' to this bit will clear the Encryption Complete Interrupt Enable bit,
which enables the Encryption Complete interrupt.
Value
Description
0
The Encryption Complete interrupt is disabled.
1
The Encryption Complete interrupt is enabled.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.5
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Bit
7
INTFLAG
0x07
0x00
6
5
4
Access
Reset
3
2
1
GFMCMP
R/W
0
0
ENCCMP
R/W
0
Bit 1 – GFMCMP GF Multiplication Complete
This flag is cleared by writing a '1' to it.
This flag is set when GHASH value is available on the Galois Hash Registers (GHASHx) in GCM mode.
Writing a '0' to this bit has no effect.
This flag is also automatically cleared in the following cases.
1. Manual encryption/decryption occurs (START in CTRLB register).
2.
Reading from the GHASHx register.
Bit 0 – ENCCMP Encryption Complete
This flag is cleared by writing a '1' to it.
This flag is set when encryption/decryption is complete and valid data is available on the Data Register.
Writing a '0' to this bit has no effect.
This flag is also automatically cleared in the following cases:
1. Manual encryption/decryption occurs (START in CTRLA register). (This feature is needed only if we do not
support double buffering of DATA registers).
2.
Reading from the data register (DATAx) when LOD = 0.
3.
Writing into the data register (DATAx) when LOD = 1.
4.
Reading from the Hash Key register (HASHKEYx).
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.6
Data Buffer Pointer
Name:
Offset:
Reset:
Property:
Bit
7
DATABUFPTR
0x08
0x00
PAC Write-Protection
6
Access
Reset
5
4
3
2
1
0
INDATAPTR[1:0]
R/W
R/W
0
0
Bits 1:0 – INDATAPTR[1:0] Input Data Pointer
Writing to this field changes the value of the input data pointer, which determines which of the four data registers is
written to/read from when the next write/read to the DATA register address is performed.
© 2020 Microchip Technology Inc.
DS60001477C-page 803
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.7
Debug
Name:
Offset:
Reset:
Property:
Bit
7
DBGCTRL
0x09
0x00
PAC Write-Protection
6
Access
Reset
5
4
3
2
1
0
DBGRUN
W
0
Bit 0 – DBGRUN Debug Run
Writing a '0' to this bit causes the AES to halt during debug mode.
Writing a '1' to this bit allows the AES to continue normal operation during debug mode. This bit can only be changed
while the AES is disabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 804
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.8
Keyword
Name:
Offset:
Reset:
Property:
KEYWORD
0x0C + n*0x04 [n=0..7]
0x00000000
PAC Write-Protection
Bit
31
30
29
Access
Reset
W
0
W
0
W
0
Bit
23
22
21
Access
Reset
W
0
W
0
W
0
Bit
15
14
13
Access
Reset
W
0
W
0
W
0
Bit
7
6
5
Access
Reset
W
0
W
0
W
0
28
27
KEYWORD[31:24]
W
W
0
0
26
25
24
W
0
W
0
W
0
20
19
KEYWORD[23:16]
W
W
0
0
18
17
16
W
0
W
0
W
0
12
11
KEYWORD[15:8]
W
W
0
0
10
9
8
W
0
W
0
W
0
4
3
KEYWORD[7:0]
W
W
0
0
2
1
0
W
0
W
0
W
0
Bits 31:0 – KEYWORD[31:0] Key Word Value
The four/six/eight 32-bit Key Word registers set the 128-bit/192-bit/256-bit cryptographic key used for encryption/
decryption. KEYWORD0.KEYWORD corresponds to the first word of the key and KEYWORD3/KEYWORD5/
KEYWORD7.KEYWORD to the last one.
Note: By setting the XORKEY bit of CTRLA register, keyword will update with the resulting XOR value of user
keyword and previous keyword content.
© 2020 Microchip Technology Inc.
DS60001477C-page 805
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.9
Data
Name:
Offset:
Reset:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
INDATA
0x38
0x00000000
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
INDATA[31:24]
R/W
R/W
0
0
20
19
INDATA[23:16]
R/W
R/W
0
0
12
11
INDATA[15:8]
R/W
R/W
0
0
4
3
INDATA[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – INDATA[31:0] Data Value
A write to or read from this register corresponds to a write to or read from one of the four data registers. The four 32bit Data registers set the 128-bit data block used for encryption/decryption. The data register that is written to or read
from is given by the DATABUFPTR.DATPTR field.
Note: Both input and output shares the same data buffer. Reading DATA register will return 0’s when AES is
performing encryption or decryption operation.
© 2020 Microchip Technology Inc.
DS60001477C-page 806
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.10 Initialization Vector Register
Name:
Offset:
Reset:
Property:
INTVECT
0x3C + n*0x04 [n=0..3]
0x00000000
PAC Write-Protection
Bit
31
30
29
28
27
INTVECT[31:24]
W
W
0
0
26
25
24
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
Bit
23
22
21
20
19
INTVECT[23:16]
W
W
0
0
18
17
16
Access
Reset
W
0
W
0
W
0
W
0
W
0
W
0
Bit
15
14
13
10
9
8
W
0
12
11
INTVECT[15:8]
W
W
0
0
Access
Reset
W
0
W
0
W
0
W
0
W
0
Bit
7
6
5
4
3
2
1
0
W
0
W
0
W
0
W
0
INTVECT[7:0]
Access
Reset
W
0
W
0
W
0
W
0
Bits 31:0 – INTVECT[31:0] Initialization Vector Value
The four 32-bit Initialization Vector registers INTVECT set the 128-bit Initialization Vector data block that is used by
some modes of operation as an additional initial input. INTVECT0.INTVECT corresponds to the first word of the
Initialization Vector, INTVECT3.INTVECT to the last one. These registers are write-only to prevent the Initialization
Vector from being read by another application. For CBC, OFB, and CFB modes, the Initialization Vector corresponds
to the initialization vector. For CTR mode, it corresponds to the counter value.
© 2020 Microchip Technology Inc.
DS60001477C-page 807
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.11 Hash Key (GCM mode only)
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
HASHKEY
0x5C + n*0x04 [n=0..3]
0x00000000
PAC Write-protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
HASHKEY[31:24]
R/W
R/W
0
0
20
19
HASHKEY[23:16]
R/W
R/W
0
0
12
11
HASHKEY[15:8]
R/W
R/W
0
0
4
3
HASHKEY[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – HASHKEY[31:0] Hash Key Value
The four 32-bit HASHKEY registers contain the 128-bit Hash Key value computed from the AES KEY. The Hash Key
value can also be programmed offering single GF128 multiplication possibilities.
© 2020 Microchip Technology Inc.
DS60001477C-page 808
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.12 Galois Hash (GCM mode only)
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
GHASH
0x6C + n*0x04 [n=0..3]
0x00000000
PAC Write-Protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
GHASH[31:24]
R/W
R/W
0
0
20
19
GHASH[23:16]
R/W
R/W
0
0
12
11
GHASH[15:8]
R/W
R/W
0
0
4
3
GHASH[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – GHASH[31:0] Galois Hash Value
The four 32-bit Hash Word registers GHASHcontain the GHASH value after GF128 multiplication in GCM mode. Writing
a new key to KEYWORD registers causes GHASH to be initialized with zeroes. These registers can also be
programmed.
© 2020 Microchip Technology Inc.
DS60001477C-page 809
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.13 Galois Hash x (GCM mode only)
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
CIPLEN
0X80
0x00000000
PAC Write-Protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
CIPLEN[31:24]
R/W
R/W
0
0
20
19
CIPLEN[23:16]
R/W
R/W
0
0
12
11
CIPLEN[15:8]
R/W
R/W
0
0
4
3
CIPLEN[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – CIPLEN[31:0] Cipher Length
This register contains the length in bytes of the Cipher text that is to be processed. This is programmed by the user in
GCM mode for Tag generation.
© 2020 Microchip Technology Inc.
DS60001477C-page 810
SAM L21 Family Data Sheet
AES – Advanced Encryption Standard
38.8.14 Random Seed
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
RANDSEED
0x84
0x00000000
PAC Write-Protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
RANDSEED[31:24]
R/W
R/W
0
0
20
19
RANDSEED[23:16]
R/W
R/W
0
0
12
11
RANDSEED[15:8]
R/W
R/W
0
0
4
3
RANDSEED[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – RANDSEED[31:0] Random Seed
A write to this register corresponds to loading a new seed into the Random number generator.
© 2020 Microchip Technology Inc.
DS60001477C-page 811
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.
USB – Universal Serial Bus
39.1
Overview
The Universal Serial Bus interface (USB) module complies with the Universal Serial Bus (USB) 2.1 specification
supporting both device and embedded host modes.
The USB device mode supports 8 endpoint addresses. All endpoint addresses have one input and one output
endpoint, for a total of 16 endpoints. Each endpoint is fully configurable in any of the four transfer types: control,
interrupt, bulk or isochronous. The USB host mode supports up to 8 pipes. The maximum data payload size is
selectable up to 1023 bytes.
Internal SRAM is used to keep the configuration and data buffer for each endpoint. The memory locations used for
the endpoint configurations and data buffers is fully configurable. The amount of memory allocated is dynamic
according to the number of endpoints in use, and the configuration of these. The USB module has a built-in Direct
Memory Access (DMA) and will read/write data from/to the system RAM when a USB transaction takes place. No
CPU or DMA Controller resources are required.
To maximize throughput, an endpoint can be configured for ping-pong operation. When this is done the input and
output endpoint with the same address are used in the same direction. The CPU or DMA Controller can then read/
write one data buffer while the USB module writes/reads from the other buffer. This gives double buffered
communication.
Multi-packet transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as
multiple packets without any software intervention. This reduces the number of interrupts and software intervention
needed for USB transfers.
For low power operation the USB module can put the microcontroller in any sleep mode when the USB bus is idle
and a suspend condition is given. Upon bus resume, the USB module can wake the microcontroller from any sleep
mode.
39.2
Features
•
•
•
•
•
•
•
•
•
Compatible with the USB 2.1 specification
USB Embedded Host and Device mode
Supports full (12Mbit/s) and low (1.5Mbit/s) speed communication
Supports Link Power Management (LPM-L1) protocol
On-chip transceivers with built-in pull-ups and pull-downs
On-Chip USB serial resistors
1kHz SOF clock available on external pin
Device mode
– Supports 8 IN endpoints and 8 OUT endpoints
– No endpoint size limitations
– Built-in DMA with multi-packet and dual bank for all endpoints
– Supports feedback endpoint
– Supports crystal less clock
Host mode
– Supports 8 physical pipes
– No pipe size limitations
– Supports multiplexed virtual pipe on one physical pipe to allow an unlimited USB tree
– Built-in DMA with multi-packet support and dual bank for all pipes
– Supports feedback endpoint
– Supports the USB 2.0 Phase-locked SOFs feature
© 2020 Microchip Technology Inc.
DS60001477C-page 812
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.3
USB Block Diagram
The USB 2.0 Transceiver Macrocell Interface (UTMI) requires an external 12 MHz clock as a reference to its internal
480 MHz phase locked loop (PLL). The PLL is used to clock an internal digital locked loop (DLL) module to retrieve
USB differential data at 480 Mbit/s.
Figure 39-1. LS/FS Implementation: USB Block Diagram
USB
SRAM Controller
AHB Slave
dedicated bus
APB
device-wide bus
AHB Master
User
Interface
DP
USB interrupts
NVIC
SOF 1kHz
GCLK_USB
GCLK
System clock domain
39.4
DM
USB 2.0
Core
USB clock domain
Signal Description
Pin Name
Pin Description
Type
DM
Data -: Differential Data Line - Port
Input/Output
DP
Data +: Differential Data Line + Port
Input/Output
SOF 1kHZ
SOF Output
Output
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped on several pins.
39.5
Product Dependencies
In order to use this peripheral module, other parts of the system must be configured correctly, as described below.
39.5.1
I/O Lines
The USB pins may be multiplexed with the I/O lines Controller. The user must first configure the I/O Controller to
assign the USB pins to their peripheral functions.
A 1kHz SOF clock is available on an external pin. The user must first configure the I/O Controller to assign the 1kHz
SOF clock to the peripheral function. The SOF clock is available for device and host mode.
39.5.2
Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. The interrupts can wake
up the device from sleep modes. Events connected to the event system can trigger other operations in the system
without exiting sleep modes.
© 2020 Microchip Technology Inc.
DS60001477C-page 813
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.5.3
Clocks
The USB bus clock (CLK_USB_AHB) can be enabled and disabled in the Power Manager, and the default state of
CLK_USB_AHB can be found in the Peripheral Clock Masking.
A generic clock (GCLK_USB) is required to clock the USB. This clock must be configured and enabled in the Generic
Clock Controller before using the USB. Refer to GCLK - Generic Clock Controller for further details.
This generic clock is asynchronous to the bus clock (CLK_USB_AHB). Due to this asynchronicity, writes to certain
registers will require synchronization between the clock domains. Refer to GCLK Synchronization for further details.
The USB module requires a GCLK_USB of 48 MHz ± 0.25% clock for low speed and full speed operation. To follow
the USB data rate at 12Mbit/s in full-speed mode, the CLK_USB_AHB clock should be at minimum 8MHz.
Clock recovery is achieved by a digital phase-locked loop in the USB module, which complies with the USB jitter
specifications. If crystal-less operation is used in USB device mode, refer to USB Clock Recovery Module.
39.5.4
DMA
The USB has a built-in Direct Memory Access (DMA) and will read/write data to/from the system RAM when a USB
transaction takes place. No CPU or DMA Controller resources are required.
39.5.5
Interrupts
The interrupt request line is connected to the Interrupt Controller. In order to use interrupt requests of this peripheral,
the Interrupt Controller (NVIC) must be configured first. Refer to Nested Vector Interrupt Controller for details.
39.5.6
Events
Not applicable.
39.5.7
Debug Operation
When the CPU is halted in debug mode the USB peripheral continues normal operation. If the USB peripheral is
configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper
operation or data loss may result during debugging.
39.5.8
Register Access Protection
Registers with write-access can be optionally write-protected by the Peripheral Access Controller (PAC), except for
the following:
•
•
•
•
Device Interrupt Flag (INTFLAG) register
Endpoint Interrupt Flag (EPINTFLAG) register
Host Interrupt Flag (INTFLAG) register
Pipe Interrupt Flag (PINTFLAG) register
Note: Optional write-protection is indicated by the "PAC Write-Protection" property in the register description.
When the CPU is halted in debug mode, all write-protection is automatically disabled. Write-protection does not apply
for accesses through an external debugger.
39.5.9
Analog Connections
Not applicable.
39.5.10 Calibration
The output drivers for the DP/DM USB line interface can be fine tuned with calibration values from production tests.
The calibration values must be loaded from the NVM Software Calibration Area into the USB Pad Calibration register
(PADCAL) by software, before enabling the USB, to achieve the specified accuracy. Refer to NVM Software
Calibration Area Mapping for further details.
For details on Pad Calibration, refer to Pad Calibration (39.8.6 PADCAL) register.
© 2020 Microchip Technology Inc.
DS60001477C-page 814
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.6
Functional Description
39.6.1
USB General Operation
39.6.1.1 Initialization
After a hardware reset, the USB is disabled. The user should first enable the USB (CTRLA.ENABLE) in either device
mode or host mode (CTRLA.MODE).
Figure 39-2. General States
HW RESET | CTRLA.SWRST
Any state
Idle
CTRLA.ENABLE = 1
CTRLA.MODE
=0
CTRLA.ENABLE = 0
CTRLA.ENABLE = 1
CTRLA.MODE
=1
Device
CTRLA.ENABLE = 0
Host
After a hardware reset, the USB is in the idle state. In this state:
•
•
•
The module is disabled. The USB Enable bit in the Control A register (CTRLA.ENABLE) is reset.
The module clock is stopped in order to minimize power consumption
The internal states and registers of the device and host are reset
Before using the USB, the Pad Calibration register (PADCAL) must be loaded with production calibration values from
the NVM Software Calibration Area.
The USB is enabled by writing a '1' to CTRLA.ENABLE. The USB is disabled by writing a '0' to CTRLA.ENABLE.
The USB is reset by writing a '1' to the Software Reset bit in CTRLA (CTRLA.SWRST). All registers in the USB will
be reset to their initial state, and the USB will be disabled. Refer to the CTRLA register for details.
© 2020 Microchip Technology Inc.
DS60001477C-page 815
SAM L21 Family Data Sheet
USB – Universal Serial Bus
The user can configure pads and speed before enabling the USB by writing to the Operating Mode bit in the Control
A register (CTRLA.MODE) and the Speed Configuration field in the Control B register (CTRLB.SPDCONF). These
values are taken into account once the USB has been enabled by writing a '1' to CTRLA.ENABLE.
After writing a '1' to CTRLA.ENABLE, the USB enters device mode or host mode (according to CTRLA.MODE).
The USB can be disabled at any time by writing a '0' to CTRLA.ENABLE.
Refer to 39.6.2 USB Device Operations for the basic operation of the device mode.
Refer to 39.6.3 Host Operations for the basic operation of the host mode.
39.6.2
USB Device Operations
This section gives an overview of the USB module device operation during normal transactions. For more details on
general USB and USB protocol, refer to the Universal Serial Bus specification revision 2.1.
39.6.2.1 Initialization
To attach the USB device to start the USB communications from the USB host, a zero should be written to the Detach
bit in the Device Control B register (CTRLB.DETACH). To detach the device from the USB host, a one must be
written to the CTRLB.DETACH.
After the device is attached, the host will request the USB device descriptor using the default device address zero.
On successful transmission, it will send a USB reset. After that, it sends an address to be configured for the device.
All further transactions will be directed to this device address. This address should be configured in the Device
Address field in the Device Address register (DADD.DADD) and the Address Enable bit in DADD (DADD.ADDEN)
should be written to one to accept communications directed to this address. DADD.ADDEN is automatically cleared
on receiving a USB reset.
39.6.2.2 Endpoint Configuration
Endpoint data can be placed anywhere in the device RAM. The USB controller accesses these endpoints directly
through the AHB master (built-in DMA) with the help of the endpoint descriptors. The base address of the endpoint
descriptors needs to be written in the Descriptor Address register (DESCADD) by the user. Refer also to the Endpoint
Descriptor structure in 39.13 Endpoint Descriptor Structure.
Before using an endpoint, the user should configure the direction and type of the endpoint in Type of Endpoint field in
the Device Endpoint Configuration register (EPCFG.EPTYPE0/1). The endpoint descriptor registers should be
initialized to known values before using the endpoint, so that the USB controller does not read random values from
the RAM.
The Endpoint Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported to
the host for that endpoint. The Address of Data Buffer register (ADDR) should be set to the data buffer used for
endpoint transfers.
The RAM Access Interrupt bit in Device Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM access
underflow error occurs during IN data stage.
When an endpoint is disabled, the following registers are cleared for that endpoint:
•
•
•
•
Device Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register
Device Endpoint Interrupt Flag (EPINTFLAG) register
Transmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0)
Transmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1)
39.6.2.3 Multi-Packet Transfers
Multi-packet transfer enables a data payload exceeding the endpoint maximum transfer size to be transferred as
multiple packets without software intervention. This reduces the number of interrupts and software intervention
required to manage higher level USB transfers. Multi-packet transfer is identical to the IN and OUT transactions
described below unless otherwise noted in this section.
The application software provides the size and address of the RAM buffer to be proceeded by the USB module for a
specific endpoint, and the USB module will split the buffer in the required USB data transfers without any software
intervention.
© 2020 Microchip Technology Inc.
DS60001477C-page 816
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Figure 39-3. Multi-Packet Feature - Reduction of CPU Overhead
Data Payload
Without Multi-packet support
Transfer Complete Interrupt
&
Data Processing
Maximum Endpoint size
With Multi-packet support
39.6.2.4 USB Reset
The USB bus reset is initiated by a connected host and managed by hardware.
During USB reset the following registers are cleared:
•
•
•
•
•
•
•
•
•
Device Endpoint Configuration (EPCFG) register - except for Endpoint 0
Device Frame Number (FNUM) register
Device Address (DADD) register
Device Endpoint Interrupt Enable Clear/Set (EPINTENCLR/SET) register
Device Endpoint Interrupt Flag (EPINTFLAG) register
Transmit Stall 0 bit in the Endpoint Status register (EPSTATUS.STALLRQ0)
Transmit Stall 1 bit in the Endpoint Status register (EPSTATUS.STALLRQ1)
Endpoint Interrupt Summary (EPINTSMRY) register
Upstream resume bit in the Control B register (CTRLB.UPRSM)
At the end of the reset process, the End of Reset bit is set in the Interrupt Flag register (INTFLAG.EORST).
39.6.2.5 Start-of-Frame
When a Start-of-Frame (SOF) token is detected, the frame number from the token is stored in the Frame Number
field in the Device Frame Number register (FNUM.FNUM), and the Start-of-Frame interrupt bit in the Device Interrupt
Flag register (INTFLAG.SOF) is set. If there is a CRC or bit-stuff error, the Frame Number Error status flag
(FNUM.FNCERR) in the FNUM register is set.
39.6.2.6 Management of SETUP Transactions
When a SETUP token is detected and the device address of the token packet does not match DADD.DADD, the
packet is discarded and the USB module returns to idle and waits for the next token packet.
When the address matches, the USB module checks if the endpoint is enabled in EPCFG. If the addressed endpoint
is disabled, the packet is discarded and the USB module returns to idle and waits for the next token packet.
When the endpoint is enabled, the USB module then checks on the EPCFG of the addressed endpoint. If the
EPCFG.EPTYPE0 is not set to control, the USB module returns to idle and waits for the next token packet.
When the EPCFG.EPTYPE0 matches, the USB module then fetches the Data Buffer Address (ADDR) from the
addressed endpoint's descriptor and waits for a DATA0 packet. If a PID error or any other PID than DATA0 is
detected, the USB module returns to idle and waits for the next token packet.
When the data PID matches and if the Received Setup Complete interrupt bit in the Device Endpoint Interrupt Flag
register (EPINTFLAG.RXSTP) is equal to zero, ignoring the Bank 0 Ready bit in the Device Endpoint Status register
(EPSTATUS.BK0RDY), the incoming data is written to the data buffer pointed to by the Data Buffer Address (ADDR).
If the number of received data bytes exceeds the endpoint's maximum data payload size as specified by the
PCKSIZE.SIZE, the remainders of the received data bytes are discarded. The packet will still be checked for bit-stuff
and CRC errors. Software must never report a endpoint size to the host that is greater than the value configured in
PCKSIZE.SIZE. If a bit-stuff or CRC error is detected in the packet, the USB module returns to idle and waits for the
next token packet.
If data is successfully received, an ACK handshake is returned to the host, and the number of received data bytes,
excluding the CRC, is written to the Byte Count (PCKSIZE.BYTE_COUNT). If the number of received data bytes is
© 2020 Microchip Technology Inc.
DS60001477C-page 817
SAM L21 Family Data Sheet
USB – Universal Serial Bus
the maximum data payload specified by PCKSIZE.SIZE, no CRC data is written to the data buffer. If the number of
received data bytes is the maximum data payload specified by PCKSIZE.SIZE minus one, only the first CRC data is
written to the data buffer. If the number of received data is equal or less than the data payload specified by
PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer.
Finally the EPSTATUS is updated. Data Toggle OUT bit (EPSTATUS.DTGLOUT), the Data Toggle IN bit
(EPSTATUS.DTGLIN), the current bank bit (EPSTATUS.CURRBK) and the Bank Ready 0 bit (EPSTATUS.BK0RDY)
are set. Bank Ready 1 bit (EPSTATUS.BK1RDY) and the Stall Bank 0/1 bit (EPSTATUS.STALLQR0/1) are cleared on
receiving the SETUP request. The RXSTP bit is set and triggers an interrupt if the Received Setup Interrupt Enable
bit is set in Endpoint Interrupt Enable Set/Clear register (EPINTENSET/CLR.RXSTP).
39.6.2.7 Management of OUT Transactions
Figure 39-4. OUT Transfer: Data Packet Host to USB Device
Memory Map
HOST
I/O Register
USB I/O Registers
BULK OUT
EPT 2
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
BULK OUT
EPT 3
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
BULK OUT
EPT 1
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
Internal RAM
USB Module
USB Endpoints
Descriptor Table
D
A
T
A
0
DESCADD
ENDPOINT 1 DATA
ENDPOINT 3 DATA
DP
DM
USB Buffers
time
ENDPOINT 2 DATA
When an OUT token is detected, and the device address of the token packet does not match DADD.DADD, the
packet is discarded and the USB module returns to idle and waits for the next token packet.
If the address matches, the USB module checks if the endpoint number received is enabled in the EPCFG of the
addressed endpoint. If the addressed endpoint is disabled, the packet is discarded and the USB module returns to
idle and waits for the next token packet.
When the endpoint is enabled, the USB module then checks the Endpoint Configuration register (EPCFG) of the
addressed output endpoint. If the type of the endpoint (EPCFG.EPTYPE0) is not set to OUT, the USB module returns
to idle and waits for the next token packet.
The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor, and waits
for a DATA0 or DATA1 packet. If a PID error or any other PID than DATA0 or DATA1 is detected, the USB module
returns to idle and waits for the next token packet.
If EPSTATUS.STALLRQ0 in EPSTATUS is set, the incoming data is discarded. If the endpoint is not isochronous, a
STALL handshake is returned to the host and the Transmit Stall Bank 0 interrupt bit in EPINTFLAG
(EPINTFLAG.STALL0) is set.
For isochronous endpoints, data from both a DATA0 and DATA1 packet will be accepted. For other endpoint types
the PID is checked against EPSTATUS.DTGLOUT. If a PID mismatch occurs, the incoming data is discarded, and an
ACK handshake is returned to the host.
If EPSTATUS.BK0RDY is set, the incoming data is discarded, the bit Transmit Fail 0 interrupt bit in EPINTFLAG
(EPINTFLAG.TRFAIL0) and the status bit STATUS_BK.ERRORFLOW are set. If the endpoint is not isochronous, a
NAK handshake is returned to the host.
© 2020 Microchip Technology Inc.
DS60001477C-page 818
SAM L21 Family Data Sheet
USB – Universal Serial Bus
The incoming data is written to the data buffer pointed to by the Data Buffer Address (ADDR). If the number of
received data bytes exceeds the maximum data payload specified as PCKSIZE.SIZE, the remainders of the received
data bytes are discarded. The packet will still be checked for bit-stuff and CRC errors. If a bit-stuff or CRC error is
detected in the packet, the USB module returns to idle and waits for the next token packet.
If the endpoint is isochronous and a bit-stuff or CRC error in the incoming data, the number of received data bytes,
excluding CRC, is written to PCKSIZE.BYTE_COUNT. Finally the EPINTFLAG.TRFAIL0 and CRC Error bit in the
Device Bank Status register (STATUS_BK.CRCERR) is set for the addressed endpoint.
If data was successfully received, an ACK handshake is returned to the host if the endpoint is not isochronous, and
the number of received data bytes, excluding CRC, is written to PCKSIZE.BYTE_COUNT. If the number of received
data bytes is the maximum data payload specified by PCKSIZE.SIZE no CRC data bytes are written to the data
buffer. If the number of received data bytes is the maximum data payload specified by PCKSIZE.SIZE minus one,
only the first CRC data byte is written to the data buffer If the number of received data is equal or less than the data
payload specified by PCKSIZE.SIZE minus two, both CRC data bytes are written to the data buffer.
Finally in EPSTATUS for the addressed output endpoint, EPSTATUS.BK0RDY is set and EPSTATUS.DTGLOUT is
toggled if the endpoint is not isochronous. The flag Transmit Complete 0 interrupt bit in EPINTFLAG
(EPINTFLAG.TRCPT0) is set for the addressed endpoint.
39.6.2.8 Multi-Packet Transfers for OUT Endpoint
The number of data bytes received is stored in endpoint PCKSIZE.BYTE_COUNT as for normal operation. Since
PCKSIZE.BYTE_COUNT is updated after each transaction, it must be set to zero when setting up a new transfer.
The total number of bytes to be received must be written to PCKSIZE.MULTI_PACKET_SIZE. This value must be a
multiple of PCKSIZE.SIZE, otherwise excess data may be written to SRAM locations used by other parts of the
application.
EPSTATUS.DTGLOUT management for non-isochronous packets and EPINTFLAG.BK1RDY/BK0RDY management
are as for normal operation.
If a maximum payload size packet is received, PCKSIZE.BYTE_COUNT will be incremented by PCKSIZE.SIZE after
the transaction has completed, and EPSTATUS.DTGLOUT will be toggled if the endpoint is not isochronous. If the
updated PCKSIZE.BYTE_COUNT is equal to PCKSIZE.MULTI_PACKET_SIZE (i.e. the last transaction),
EPSTATUS.BK1RDY/BK0RDY, and EPINTFLAG.TRCPT0/TRCPT1 will be set.
© 2020 Microchip Technology Inc.
DS60001477C-page 819
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.6.2.9 Management of IN Transactions
Figure 39-5. IN Transfer: Data Packet USB Device to Host After Request from Host
Memory Map
I/O Register
HOST
CPU
USB I/O Registers
Internal RAM
EPT 2
D
A
T
A
0
D
A
T
A
1
EPT 3
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
D
A
T
A
0
D
A
T
A
1
USB Module
EPT 1
D
A
T
A
0
D
A
T
A
0
D
A
T
A
1
DP
DM
ENDPOINT 2 DATA
DESCADD
USB Endpoints
Descriptor Table
D
A
T
A
0
ENDPOINT 3 DATA
USB Buffers
EPT 2
I
N
T
O
K
E
N
I
N
EPT 3 T
O
K
E
N
I
N
EPT 1 T
O
K
E
N
ENDPOINT 1 DATA
time
When an IN token is detected, and if the device address of the token packet does not match DADD.DADD, the
packet is discarded and the USB module returns to idle and waits for the next token packet.
When the address matches, the USB module checks if the endpoint received is enabled in the EPCFG of the
addressed endpoint and if not, the packet is discarded and the USB module returns to idle and waits for the next
token packet.
When the endpoint is enabled, the USB module then checks on the EPCFG of the addressed input endpoint. If the
EPCFG.EPTYPE1 is not set to IN, the USB module returns to idle and waits for the next token packet.
If EPSTATUS.STALLRQ1 in EPSTATUS is set, and the endpoint is not isochronous, a STALL handshake is returned
to the host and EPINTFLAG.STALL1 is set.
If EPSTATUS.BK1RDY is cleared, the flag EPINTFLAG.TRFAIL1 is set. If the endpoint is not isochronous, a NAK
handshake is returned to the host.
The USB module then fetches the Data Buffer Address (ADDR) from the addressed endpoint's descriptor. The data
pointed to by the Data Buffer Address (ADDR) is sent to the host in a DATA0 packet if the endpoint is isochronous.
For non-isochronous endpoints a DATA0 or DATA1 packet is sent depending on the state of EPSTATUS.DTGLIN.
When the number of data bytes specified in endpoint PCKSIZE.BYTE_COUNT is sent, the CRC is appended and
sent to the host.
For isochronous endpoints, EPSTATUS.BK1RDY is cleared and EPINTFLAG.TRCPT1 is set.
For all non-isochronous endpoints the USB module waits for an ACK handshake from the host. If an ACK handshake
is not received within 16 bit times, the USB module returns to idle and waits for the next token packet. If an ACK
handshake is successfully received EPSTATUS.BK1RDY is cleared, EPINTFLAG.TRCPT1 is set and
EPSTATUS.DTGLIN is toggled.
© 2020 Microchip Technology Inc.
DS60001477C-page 820
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.6.2.10 Multi-Packet Transfers for IN Endpoint
The total number of data bytes to be sent is written to PCKSIZE.BYTE_COUNT as for normal operation. The Multipacket size register (PCKSIZE.MULTI_PACKET_SIZE) is used to store the number of bytes that are sent, and must
be written to zero when setting up a new transfer.
When an IN token is received, PCKSIZE.BYTE_COUNT and PCKSIZE.MULTI_PACKET_SIZE are fetched. If
PCKSIZE.BYTE_COUNT minus PCKSIZE.MULTI_PACKET_SIZE is less than the endpoint PCKSIZE.SIZE, endpoint
BYTE_COUNT minus endpoint PCKSIZE.MULTI_PACKET_SIZE bytes are transmitted, otherwise PCKSIZE.SIZE
number of bytes are transmitted. If endpoint PCKSIZE.BYTE_COUNT is a multiple of PCKSIZE.SIZE, the last packet
sent will be zero-length if the AUTOZLP bit is set.
If a maximum payload size packet was sent (i.e. not the last transaction), MULTI_PACKET_SIZE will be incremented
by the PCKSIZE.SIZE. If the endpoint is not isochronous the EPSTATUS.DTLGIN bit will be toggled when the
transaction has completed. If a short packet was sent (i.e. the last transaction), MULTI_PACKET_SIZE is
incremented by the data payload. EPSTATUS.BK0/1RDY will be cleared and EPINTFLAG.TRCPT0/1 will be set.
39.6.2.11 Ping-Pong Operation
When an endpoint is configured for ping-pong operation, it uses both the input and output data buffers (banks) for a
given endpoint in a single direction. The direction is selected by enabling one of the IN or OUT direction in
EPCFG.EPTYPE0/1 and configuring the opposite direction in EPCFG.EPTYPE1/0 as Dual Bank.
When ping-pong operation is enabled for an endpoint, the endpoint in the opposite direction must be configured as
dual bank. The data buffer, data address pointer and byte counter from the enabled endpoint are used as Bank 0,
while the matching registers from the disabled endpoint are used as Bank 1.
Figure 39-6. Ping-Pong Overview
Without Ping Pong
Endpoint
single bank
t
Endpoint
dual bank
Bank0
With Ping Pong
t
Bank1
USB data packet
Available time for data processing by CPU
to avoid NACK
The Bank Select flag in EPSTATUS.CURBK indicates which bank data will be used in the next transaction, and is
updated after each transaction. According to EPSTATUS.CURBK, EPINTFLAG.TRCPT0 or EPINTFLAG.TRFAIL0 or
EPINTFLAG.TRCPT1 or EPINTFLAG.TRFAIL1 in EPINTFLAG and Data Buffer 0/1 ready (EPSTATUS.BK0RDY and
EPSTATUS.BK1RDY) are set. The EPSTATUS.DTGLOUT and EPSTATUS.DTGLIN are updated for the enabled
endpoint direction only.
39.6.2.12 Feedback Operation
Feedback endpoints are endpoints with same the address but in different directions. This is usually used in explicit
feedback mechanism in USB Audio, where a feedback endpoint is associated to one or more isochronous data
endpoints to which it provides feedback service. The feedback endpoint always has the opposite direction from the
data endpoint.
The feedback endpoint always has the opposite direction from the data endpoint(s). The feedback endpoint has the
same endpoint number as the first (lower) data endpoint. A feedback endpoint can be created by configuring an
endpoint with different endpoint size (PCKSIZE.SIZE) and different endpoint type (EPCFG.EPTYPE0/1) for the IN
and OUT direction.
© 2020 Microchip Technology Inc.
DS60001477C-page 821
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Example Configuration for Feedback Operation:
• Endpoint n / IN: EPCFG.EPTYPE1 = Interrupt IN, PCKSIZE.SIZE = 64.
• Endpoint n / OUT: EPCFG.EPTYPE0= Isochronous OUT, PCKSIZE.SIZE = 512.
39.6.2.13 Suspend State and Pad Behavior
The following figure, Pad Behavior, illustrates the behavior of the USB pad in device mode.
Figure 39-7. Pad Behavior
Idle
CTRLA.ENABLE = 1
|
CTRLB.DETACH = 0
| INTFLAG.SUSPEND = 0
CTRLA.ENABLE = 0
|
CTRLB.DETACH = 1
| INTFLAG.SUSPEND = 1
Active
In Idle state, the pad is in low power consumption mode.
In Active state, the pad is active.
The following figure, Pad Events, illustrates the pad events leading to a PAD state change.
Figure 39-8. Pad Events
Suspend detected
Cleared on Wakeup
Wakeup detected
Active
© 2020 Microchip Technology Inc.
Idle
Cleared by software to acknowledge the interrupt
Active
DS60001477C-page 822
SAM L21 Family Data Sheet
USB – Universal Serial Bus
The Suspend Interrupt bit in the Device Interrupt Flag register (INTFLAG.SUSPEND) is set when a USB Suspend
state has been detected on the USB bus. The USB pad is then automatically put in the Idle state. The detection of a
non-idle state sets the Wake Up Interrupt bit in INTFLAG(INTFLAG.WAKEUP) and wakes the USB pad.
The pad goes to the Idle state if the USB module is disabled or if CTRLB.DETACH is written to one. It returns to the
Active state when CTRLA.ENABLE is written to one and CTRLB.DETACH is written to zero.
39.6.2.14 Remote Wakeup
The remote wakeup request (also known as upstream resume) is the only request the device may send on its own
initiative. This should be preceded by a DEVICE_REMOTE_WAKEUP request from the host.
First, the USB must have detected a “Suspend” state on the bus, i.e. the remote wakeup request can only be sent
after INTFLAG.SUSPEND has been set.
The user may then write a one to the Remote Wakeup bit in CTRLB(CTRLB.UPRSM) to send an Upstream Resume
to the host initiating the wakeup. This will automatically be done by the controller after 5 ms of inactivity on the USB
bus.
When the controller sends the Upstream Resume INTFLAG.WAKEUP is set and INTFLAG.SUSPEND is cleared.
The CTRLB.UPRSM is cleared at the end of the transmitting Upstream Resume.
In case of a rebroadcast resume initiated by the host, the End of Resume bit in INTFLAG(INTFLAG.EORSM) flag is
set when the rebroadcast resume is completed.
In the case where the CTRLB.UPRSM bit is set while a host initiated downstream resume is already started, the
CTRLB.UPRSM is cleared and the upstream resume request is ignored.
39.6.2.15 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Device
The LPM Handshake bit in CTRLB.LPMHDSK should be configured to accept the LPM transaction.
When a LPM transaction is received on any enabled endpoint n and a handshake has been sent in response by the
controller according to CTRLB.LPMHDSK, the Device Link Power Manager (EXTREG) register is updated in the
bank 0 of the addressed endpoint's descriptor. It contains information such as the Best Effort Service Latency
(BESL), the Remote Wake bit (bRemoteWake), and the Link State parameter (bLinkState). Usually, the LPM
transaction uses only the endpoint number 0.
If the LPM transaction was positively acknowledged (ACK handshake), USB sets the Link Power Management
Interrupt bit in INTFLAG(INTFLAG.LPMSUSP) bit which indicates that the USB transceiver is suspended, reducing
power consumption. This suspend occurs 9 microseconds after the LPM transaction according to the specification.
To further reduce consumption, it is recommended to stop the USB clock while the device is suspended.
The MCU can also enter in one of the available sleep modes if the wakeup time latency of the selected sleep mode
complies with the host latency constraint (see the BESL parameter in 39.15.3 EXTREG register).
Recovering from this LPM-L1 suspend state is exactly the same as the Suspend state (see Section 39.6.2.13
Suspend State and Pad Behavior) except that the remote wakeup duration initiated by USB is shorter to comply with
the Link Power Management specification.
If the LPM transaction is responded with a NYET, the Link Power Management Not Yet Interrupt Flag
INTFLAG(INTFLAG.LPMNYET) is set. This generates an interrupt if the Link Power Management Not Yet Interrupt
Enable bit in INTENCLR/SET (INTENCLR/SET.LPMNYET) is set.
If the LPM transaction is responded with a STALL or no handshake, no flag is set, and the transaction is ignored.
© 2020 Microchip Technology Inc.
DS60001477C-page 823
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.6.2.16 USB Device Interrupt
Figure 39-9. Device Interrupt
EPINTFLAG7.STALL
EPINTENSET7.STALL0/STALL1
EPINTFLAG7.TRFAIL1
EPINTENSET7.TRFAIL1
EPINTFLAG7.TRFAIL0
EPINTENSET7.TRFAIL0
EPINTFLAG7.RXSTP
ENDPOINT7
EPINTSMRY
EPINT7
EPINTENSET7.RXSTP
EPINT6
EPINTFLAG7.TRCPT1
EPINTENSET7.TRCPT1
EPINTFLAG7.TRCPT0
EPINTENSET7.TRCPT0
USB EndPoint
Interrupt
EPINTFLAG0.STALL
EPINTENSET0.STALL0/STALL1
EPINTFLAG0.TRFAIL1
EPINTENSET0.TRFAIL1
EPINTFLAG0.TRFAIL0
EPINTENSET0.TRFAIL0
EPINTFLAG0.RXSTP
ENDPOINT0
EPINT1
EPINT0
EPINTENSET0.RXSTP
EPINTFLAG0.TRCPT1
EPINTENSET0.TRCPT1
EPINTFLAG0.TRCPT0
USB
Interrupt
EPINTENSET0.TRCPT0
INTFLAG.LPMSUSP
INTENSET.LPMSUSP
INTFLAG.LPMNYET
INTENSET.DDISC
INTFLAG.RAMACER
INTENSET.RAMACER
INTFLAG.UPRSM
INTFLAG
INTENSET.UPRSM
INTFLAG.EORSM
USB Device Interrupt
INTENSET.EORSM
INTFLAG.WAKEUP
*
INTENSET.WAKEUP
INTFLAG.EORST
INTENSET.EORST
INTFLAG.SOF
INTENSET.SOF
INTFLAGA.SUSPEND
INTENSET.SUSPEND
* Asynchronous interrupt
© 2020 Microchip Technology Inc.
DS60001477C-page 824
SAM L21 Family Data Sheet
USB – Universal Serial Bus
The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
39.6.3
Host Operations
This section gives an overview of the USB module Host operation during normal transactions. For more details on
general USB and USB protocol, refer to Universal Serial Bus Specification revision 2.1.
39.6.3.1 Device Detection and Disconnection
Prior to device detection the software must set the VBUS is OK bit in CTRLB (CTRLB.VBUSOK) register when the
VBUS is available. This notifies the USB host that USB operations can be started. When the bit CTRLB.VBUSOK is
zero and even if the USB HOST is configured and enabled, host operation is halted. Setting the bit CTRLB.VBUSOK
will allow host operation when the USB is configured.
The Device detection is managed by the software using the Line State field in the Host Status (STATUS.LINESTATE)
register. The device connection is detected by the host controller when DP or DM is pulled high, depending of the
speed of the device.
The device disconnection is detected by the host controller when both DP and DM are pulled down using the
STATUS.LINESTATE registers.
The Device Connection Interrupt bit in INTFLAG (INTFLAG.DCONN) is set if a device connection is detected.
The Device Disconnection Interrupt bit in INTFLAG (INTFLAG.DDISC) is set if a device disconnection is detected.
39.6.3.2 Host Terminology
In host mode, the term pipe is used instead of endpoint. A host pipe corresponds to a device endpoint, refer to
"Universal Serial Bus Specification revision 2.1." for more information.
39.6.3.3 USB Reset
The USB sends a USB reset signal when the user writes a one to the USB Reset bit in CTRLB (CTRLB.BUSRESET).
When the USB reset has been sent, the USB Reset Sent Interrupt bit in the INTFLAG (INTFLAG.RST) is set and all
pipes will be disabled.
If the bus was previously in a suspended state (Start of Frame Generation Enable bit in CTRLB (CTRLB.SOFE) is
zero) the USB will switch it to the Resume state, causing the bus to asynchronously set the Host Wakeup Interrupt
flag (INTFLAG.WAKEUP). The CTRLB.SOFE bit will be set in order to generate SOFs immediately after the USB
reset.
During USB reset the following registers are cleared:
•
•
•
•
•
•
•
All Host Pipe Configuration register (PCFG)
Host Frame Number register (FNUM)
Interval for the Bulk-Out/Ping transaction register (BINTERVAL)
Host Start-of-Frame Control register (HSOFC)
Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET)
Pipe Interrupt Flag register (PINTFLAG)
Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)
After the reset the user should check the Speed Status field in the Status register (STATUS.SPEED) to find out the
current speed according to the capability of the peripheral.
39.6.3.4 Pipe Configuration
Pipe data can be placed anywhere in the RAM. The USB controller accesses these pipes directly through the AHB
master (built-in DMA) with the help of the pipe descriptors. The base address of the pipe descriptors needs to be
written in the Descriptor Address register (DESCADD) by the user. Refer also to 39.20 Pipe Descriptor Structure.
Before using a pipe, the user should configure the direction and type of the pipe in Type of Pipe field in the Host Pipe
Configuration register (PCFG.PTYPE). The pipe descriptor registers should be initialized to known values before
using the pipe, so that the USB controller does not read the random values from the RAM.
The Pipe Size field in the Packet Size register (PCKSIZE.SIZE) should be configured as per the size reported by the
device for the endpoint associated with this pipe. The Address of Data Buffer register (ADDR) should be set to the
data buffer used for pipe transfers.
© 2020 Microchip Technology Inc.
DS60001477C-page 825
SAM L21 Family Data Sheet
USB – Universal Serial Bus
The Pipe Bank bit in PCFG (PCFG.BK) should be set to one if dual banking is desired. Dual bank is not supported for
Control pipes.
The Ram Access Interrupt bit in Host Interrupt Flag register (INTFLAG.RAMACER) is set when a RAM access
underflow error occurs during an OUT stage.
When a pipe is disabled, the following registers are cleared for that pipe:
•
•
•
•
Interval for the Bulk-Out/Ping transaction register (BINTERVAL)
Pipe Interrupt Enable Clear/Set register (PINTENCLR/SET)
Pipe Interrupt Flag register (PINTFLAG)
Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE)
39.6.3.5 Pipe Activation
A disabled pipe is inactive, and will be reset along with its context registers (pipe registers for the pipe n). Pipes are
enabled by writing Type of the Pipe in PCFG (PCFG.PTYPE) to a value different than 0x0 (disabled).
When a pipe is enabled, the Pipe Freeze bit in Pipe Status register (PSTATUS.FREEZE) is set. This allow the user to
complete the configuration of the pipe, without starting a USB transfer.
When starting an enumeration, the user retrieves the device descriptor by sending an GET_DESCRIPTOR USB
request. This descriptor contains the maximal packet size of the device default control endpoint (bMaxPacketSize0)
which the user should use to reconfigure the size of the default control pipe.
39.6.3.6 Pipe Address Setup
Once the device has answered the first host requests with the default device address 0, the host assigns a new
address to the device. The host controller has to send a USB reset to the device and a SET_ADDRESS(addr)
SETUP request with the new address to be used by the device. Once this SETUP transaction is complete, the user
writes the new address to the Pipe Device Address field in the Host Control Pipe register (CTRL_PIPE.PDADDR) in
Pipe descriptor. All following requests by this pipe will be performed using this new address.
39.6.3.7 Suspend and Wakeup
Setting CTRLB.SOFE to zero when in host mode will cause the USB to cease sending Start-of-Frames on the USB
bus and enter the Suspend state. The USB device will enter the Suspend state 3ms later.
Before entering suspend by writing CTRLB.SOFE to zero, the user must freeze the active pipes by setting their
PSTATUS.FREEZE bit. Any current on-going pipe will complete its transaction, and then all pipes will be inactive. The
user should wait at least 1 complete frame before entering the suspend mode to avoid any data loss.
The device can awaken the host by sending an Upstream Resume (Remote Wakeup feature). When the host detects
a non-idle state on the USB bus, it sets the INTFLAG.WAKEUP. If the non-idle bus state corresponds to an Upstream
Resume (K state), the Upstream Resume Received Interrupt bit in INTFLAG (INTFLAG.UPRSM) is set and the user
must generate a Downstream Resume within 1 ms and for at least 20 ms. It is required to first write a one to the Send
USB Resume bit in CTRLB (CTRLB.RESUME) to respond to the upstream resume with a downstream resume.
Alternatively, the host can resume from a suspend state by sending a Downstream Resume on the USB bus
(CTRLB.RESUME set to 1). In both cases, when the downstream resume is completed, the CTRLB.SOFE bit is
automatically set and the host enters again the active state.
39.6.3.8 Phase-locked SOFs
To support the Synchronous Endpoints capability, the period of the emitted Start-of-Frame is maintained while the
USB connection is not in the active state. This does not apply for the disconnected/connected/reset states. It applies
for active/idle/suspend/resume states. The period of Start-of-Frame will be 1ms when the USB connection is in active
state and an integer number of milli-seconds across idle/suspend/resume states.
To ensure the Synchronous Endpoints capability, the GCLK_USB clock must be kept running. If the GCLK_USB is
interrupted, the period of the emitted Start-of-Frame will be erratic.
39.6.3.9 Management of Control Pipes
A control transaction is composed of three stages:
•
•
•
SETUP
Data (IN or OUT)
Status (IN or OUT)
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
The user has to change the pipe token according to each stage using the Pipe Token field in PCFG
(PCFG.PTOKEN).
For control pipes only, the token is assigned a specific initial data toggle sequence:
•
•
•
SETUP: Data0
IN: Data1
OUT: Data1
39.6.3.10 Management of IN Pipes
IN packets are sent by the USB device controller upon IN request reception from the host. All the received data from
the device to the host will be stored in the bank provided the bank is empty. The pipe and its descriptor in RAM must
be configured.
The host indicates it is able to receive data from the device by clearing the Bank 0/1 Ready bit in PSTATUS
(PSTATUS.BK0/1RDY), which means that the memory for the bank is available for new USB transfer.
The USB will perform IN requests as long as the pipe is not frozen by the user.
The generation of IN requests starts when the pipe is unfrozen (PSTATUS.PFREEZE is set to zero).
When the current bank is full, the Transmit Complete 0/1 bit in PINTFLAG (PINTFLAG.TRCPT0/1) will be set and
trigger an interrupt if enabled and the PSTATUS.BK0/1RDY bit will be set.
PINTFLAG.TRCPT0/1 must be cleared by software to acknowledge the interrupt. This is done by writing a one to the
PINTFLAG.TRCPT0/1 of the addressed pipe.
The user reads the PCKSIZE.BYTE_COUNT to know how many bytes should be read.
To free the bank the user must read the IN data from the address ADDR in the pipe descriptor and clear the
PKSTATUS.BK0/1RDY bit. When the IN pipe is composed of multiple banks, a successful IN transaction will switch to
the next bank. Another IN request will be performed by the host as long as the PSTATUS.BK0/1RDY bit for that bank
is set. The PINTFLAG.TRCPT0/1 and PSTATUS.BK0/1RDY will be updated accordingly.
The user can follow the current bank looking at Current Bank bit in PSTATUS (PSTATUS.CURBK) and by looking at
Data Toggle for IN pipe bit in PSTATUS (PSTATUS.DTGLIN).
When the pipe is configured as single bank (Pipe Bank bit in PCFG (PCFG.BK) is 0), only PINTFLAG.TRCPT0 and
PSTATUS.BK0 are used. When the pipe is configured as dual bank (PCFG.BK is 1), both PINTFLAG.TRCPT0/1 and
PSTATUS.BK0/1 are used.
39.6.3.11 Management of OUT Pipes
OUT packets are sent by the host. All the data stored in the bank will be sent to the device provided the bank is filled.
The pipe and its descriptor in RAM must be configured.
The host can send data to the device by writing to the data bank 0 in single bank or the data bank 0/1 in dual bank.
The generation of OUT packet starts when the pipe is unfrozen (PSTATUS.PFREEZE is zero).
The user writes the OUT data to the data buffer pointer by ADDR in the pipe descriptor and allows the USB to send
the data by writing a one to the PSTATUS.BK0/1RDY. This will also cause a switch to the next bank if the OUT pipe is
part of a dual bank configuration.
PINTFLAGn.TRCPT0/1 must be cleared before setting PSTATUS.BK0/1RDY to avoid missing an
PINTFLAGn.TRCPT0/1 event.
39.6.3.12 Alternate Pipe
The user has the possibility to run sequentially several logical pipes on the same physical pipe. It allows addressing
of any device endpoint of any attached device on the bus.
Before switching pipe, the user should save the pipe context (Pipe registers and descriptor for pipe n).
After switching pipe, the user should restore the pipe context (Pipe registers and descriptor for pipe n) and in
particular PCFG, and PSTATUS.
39.6.3.13 Data Flow Error
This error exists only for isochronous and interrupt pipes for both IN and OUT directions. It sets the Transmit Fail bit
in PINTFLAG (PINTFLAG.TRFAIL), which triggers an interrupt if the Transmit Fail bit in PINTENCLR/
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
SET(PINTENCLR/SET.TRFAIL) is set. The user must check the Pipe Interrupt Summary register (PINTSMRY) to find
out the pipe which triggered the interrupt. Then the user must check the origin of the interrupt’s bank by looking at the
Pipe Bank Status register (STATUS_BK) for each bank. If the Error Flow bit in the STATUS_BK
(STATUS_BK.ERRORFLOW) is set then the user is able to determine the origin of the data flow error. As the user
knows that the endpoint is an IN or OUT the error flow can be deduced as OUT underflow or as an IN overflow.
An underflow can occur during an OUT stage if the host attempts to send data from an empty bank. If a new
transaction is successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
An overflow can occur during an IN stage if the device tries to send a packet while the bank is full. Typically this
occurs when a CPU is not fast enough. The packet data is not written to the bank and is lost. If a new transaction is
successful, the relevant bank descriptor STATUS_BK.ERRORFLOW will be cleared.
39.6.3.14 CRC Error
This error exists only for isochronous IN pipes. It sets the PINTFLAG.TRFAIL, which triggers an interrupt if
PINTENCLR/SET.TRFAIL is set. The user must check the PINTSMRY to find out the pipe which triggered the
interrupt. Then the user must check the origin of the interrupt’s bank by looking at the bank descriptor STATUS_BK
for each bank and if the CRC Error bit in STATUS_BK (STATUS_BK.CRCERR) is set then the user is able to
determine the origin of the CRC error. A CRC error can occur during the IN stage if the USB detects a corrupted
packet. The IN packet will remain stored in the bank and PINTFLAG.TRCPT0/1 will be set.
39.6.3.15 PERR Error
This error exists for all pipes. It sets the PINTFLAG.PERR Interrupt, which triggers an interrupt if PINTFLAG.PERR is
set. The user must check the PINTSMRY register to find out the pipe which can cause an interrupt.
A PERR error occurs if one of the error field in the STATUS_PIPE register in the Host pipe descriptor is set and the
Error Count field in STATUS_PIPE (STATUS_PIPE.ERCNT) exceeds the maximum allowed number of Pipe error(s)
as defined in Pipe Error Max Number field in CTRL_PIPE (CTRL_PIPE.PERMAX). Refer to section 39.22.6
STATUS_PIPE register.
If one of the error field in the STATUS_PIPE register from the Host Pipe Descriptor is set and the
STATUS_PIPE.ERCNT is less than the CTRL_PIPE.PERMAX, the STATUS_PIPE.ERCNT is incremented.
39.6.3.16 Link Power Management L1 (LPM-L1) Suspend State Entry and Exit as Host.
An EXTENDED LPM transaction can be transmitted by any enabled pipe. The PCFGn.PTYPE should be set to
EXTENDED. Other fields as PCFG.PTOKEN, PCFG.BK and PCKSIZE.SIZE are irrelevant in this configuration. The
user should also set the EXTREG.VARIABLE in the descriptor as described in 39.22.3 EXTREG register.
When the pipe is configured and enabled, an EXTENDED TOKEN followed by a LPM TOKEN are transmitted. The
device responds with a valid HANDSHAKE, corrupted HANDSHAKE or no HANDSHAKE (TIME-OUT).
If the valid HANDSHAKE is an ACK, the host will immediately proceed to L1 SLEEP and the PINTFLAG.TRCT0 is
set. The minimum duration of the L1 SLEEP state will be the TL1RetryAndResidency as defined in the reference
document "ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum". When entering the L1
SLEEP state, the CTRLB.SOFE is cleared, avoiding Start-of-Frame generation.
If the valid HANDSHAKE is a NYET PINTFLAG.TRFAIL is set.
If the valid HANDSHAKE is a STALL the PINTFLAG.STALL is set.
If there is no HANDSHAKE or corrupted HANDSHAKE, the EXTENDED/LPM pair of TOKENS will be transmitted
again until reaching the maximum number of retries as defined by the CTRL_PIPE.PERMAX in the pipe descriptor.
If the last retry returns no valid HANDSHAKE, the PINTFLAGn.PERR is set, and the STATUS_BK is updated in the
pipe descriptor.
All LPM transactions, should they end up with a ACK, a NYET, a STALL or a PERR, will set the PSTATUS.PFREEZE
bit, freezing the pipe before a succeeding operation. The user should unfreeze the pipe to start a new LPM
transaction.
To exit the L1 STATE, the user initiate a DOWNSTREAM RESUME by setting the bit CTRLB.RESUME or a L1
RESUME by setting the Send L1 Resume bit in CTRLB (CTRLB.L1RESUME). In the case of a L1 RESUME, the K
STATE duration is given by the BESL bit field in the EXTREG.VARIABLE field. See 39.22.3 EXTREG.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
When the host is in the L1 SLEEP state after a successful LPM transmitted, the device can initiate an UPSTREAM
RESUME. This will set the Upstream Resume Interrupt bit in INTFLAG (INTFLAG.UPRSM). The host should proceed
then to a L1 RESUME as described above.
After resuming from the L1 SLEEP state, the bit CTRLB.SOFE is set, allowing Start-of-Frame generation.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.6.3.17 Host Interrupt
Figure 39-10. Host Interrupt
PINTFLAG7.STALL
PINTENSET.STALL
PINTFLAG7.PERR
PINTENSET.PERR
PINTFLAG7.TRFAIL
PINTENSET.TRFAIL
PIPE7
PINTFLAG7.TXSTP
PINTSMRY
PINT7
PINTENSET.TXSTP
PINT6
PINTFLAG7.TRCPT1
PINTENSET.TRCPT1
PINTFLAG7.TRCPT0
PINTENSET.TRCPT0
USB PIPE
Interrupt
PINTFLAG0.STALL
PINTENSET.STALL
PINTFLAG0.PERR
PINTENSET.PERR
PINTFLAG0.TRFAIL
PINTENSET.TRFAIL
PINTFLAG0.TXSTP
PIPE0
PINT1
PINT0
PINTENSET.TXSTP
PINTFLAG0.TRCPT1
PINTENSET.TRCPT1
PINTFLAG0.TRCPT0
USB
Interrupt
PINTENSET.TRCPT0
INTFLAG.DDISC *
INTENSET.DDISC
INTFLAG.DCONN *
INTENSET.DCONN
INTFLAG.RAMACER
INTFLAGA
INTENSET.RAMACER
INTFLAG.UPRSM
USB Host Interrupt
INTENSET.UPRSM
INTFLAG.DNRSM
INTENSET.DNRSM
INTFLAG.WAKEUP *
INTENSET.WAKEUP
INTFLAG.RST
INTENSET.RST
INTFLAG.HSOF
INTENSET.HSOF
* Asynchronous interrupt
The WAKEUP is an asynchronous interrupt and can be used to wake-up the device from any sleep mode.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.7
Communication Device Host Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
...
0x0C
0x0D
0x0E
...
0x23
CTRLA
Reserved
SYNCBUSY
QOSCTRL
7:0
RUNSTDBY
7:0
7:0
DQOS[1:0]
ENABLE
SWRST
ENABLE
SWRST
CQOS[1:0]
Reserved
FSMSTATUS
7:0
FSMSTATE[6:0]
Reserved
0x24
DESCADD
0x28
PADCAL
39.8
MODE
7:0
15:8
23:16
31:24
7:0
15:8
DESCADD[7:0]
DESCADD[15:8]
DESCADD[23:16]
DESCADD[31:24]
TRANSN[1:0]
TRANSP[4:0]
TRIM[2:0]
TRANSN[4:2]
Communication Device Host Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
Refer to PAC - Peripheral Access Controller and 37.6.6 Synchronizationfor details.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.8.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
MODE
R/W
0
CTRLA
0x00
0x00
PAC Write-Protection, Write-Synchronised
6
5
4
3
2
RUNSTDBY
R/W
0
1
ENABLE
R/W
0
0
SWRST
R/W
0
Bit 7 – MODE Operating Mode
This bit defines the operating mode of the USB.
Value
Description
0
USB Device mode
1
USB Host mode
Bit 2 – RUNSTDBY Run in Standby Mode
This bit is Enable-Protected.
Value
Description
0
USB clock is stopped in standby mode.
1
USB clock is running in standby mode
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value
written to CTRLA.ENABLE will read back immediately and the Synchronization status enable bit in the
Synchronization Busy register (SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the
operation is complete.
This bit is Write-Synchronized.
Value
Description
0
The peripheral is disabled or being disabled.
1
The peripheral is enabled or being enabled.
Bit 0 – SWRST Software Reset
Writing a zero to this bit has no effect.
Writing a '1' to this bit resets all registers in the USB, to their initial state, and the USB will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
This bit is Write-Synchronized.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.8.2
Synchronization Busy
Name:
Offset:
Reset:
Property:
Bit
7
SYNCBUSY
0x02
0x00
-
6
Access
Reset
5
4
3
2
1
ENABLE
R
0
0
SWRST
R
0
Bit 1 – ENABLE Synchronization Enable status bit
This bit is cleared when the synchronization of ENABLE register between the clock domains is complete.
This bit is set when the synchronization of ENABLE register between clock domains is started.
Bit 0 – SWRST Synchronization Software Reset status bit
This bit is cleared when the synchronization of SWRST register between the clock domains is complete.
This bit is set when the synchronization of SWRST register between clock domains is started.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.8.3
QOS Control
Name:
Offset:
Reset:
Property:
Bit
7
QOSCTRL
0x03
0x000x0F
PAC Write-Protection
6
5
4
3
2
1
DQOS[1:0]
Access
Reset
R/W
0
0
CQOS[1:0]
R/W
0
R/W
0
R/W
0
Bits 3:2 – DQOS[1:0] Data Quality of Service
These bits define the memory priority access during the endpoint or pipe read/write data operation. Refer to SRAM
Quality of Service.
Bits 1:0 – CQOS[1:0] Configuration Quality of Service
These bits define the memory priority access during the endpoint or pipe read/write configuration operation. Refer to
SRAM Quality of Service.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.8.4
Finite State Machine Status
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
FSMSTATUS
0x0D
0xXXXX
Read only
6
5
4
R
0
R
0
R
0
3
FSMSTATE[6:0]
R
0
2
1
0
R
0
R
0
R
1
Bits 6:0 – FSMSTATE[6:0] Fine State Machine Status
These bits indicate the state of the finite state machine of the USB controller.
Value
Name
Description
0x01
OFF (L3)
Corresponds to the powered-off, disconnected, and disabled state.
0x02
ON (L0)
Corresponds to the Idle and Active states.
0x04
SUSPEND (L2)
0x08
SLEEP (L1)
0x10
DNRESUME
Down Stream Resume.
0x20
UPRESUME
Up Stream Resume.
0x40
RESET
USB lines Reset.
Others
Reserved
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.8.5
Descriptor Address
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
DESCADD
0x24
0x00000000
PAC Write-Protection
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
28
27
DESCADD[31:24]
R/W
R/W
0
0
20
19
DESCADD[23:16]
R/W
R/W
0
0
12
11
DESCADD[15:8]
R/W
R/W
0
0
4
3
DESCADD[7:0]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
10
9
8
R/W
0
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – DESCADD[31:0] Descriptor Address Value
These bits define the base address of the main USB descriptor in RAM. The two least significant bits must be written
to zero.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.8.6
Pad Calibration
Name:
Offset:
Reset:
Property:
PADCAL
0x28
0x0000
PAC Write-Protection
The Pad Calibration values must be loaded from the NVM Software Calibration Area into the USB Pad Calibration
register by software, before enabling the USB, to achieve the specified accuracy.
Refer to NVM Software Calibration Area Mapping for further details.
Refer to for further details.
Bit
15
Access
Reset
Bit
Access
Reset
14
R/W
0
7
6
TRANSN[1:0]
R/W
R/W
0
0
13
TRIM[2:0]
R/W
0
12
11
R/W
0
5
4
3
R/W
0
R/W
0
10
R/W
0
2
TRANSP[4:0]
R/W
0
9
TRANSN[4:2]
R/W
0
8
R/W
0
1
0
R/W
0
R/W
0
Bits 14:12 – TRIM[2:0] Trim bits for DP/DM
These bits calibrate the matching of rise/fall of DP/DM.
Bits 10:6 – TRANSN[4:0] Trimmable Output Driver Impedance N
These bits calibrate the NMOS output impedance of DP/DM drivers.
Bits 4:0 – TRANSP[4:0] Trimmable Output Driver Impedance P
These bits calibrate the PMOS output impedance of DP/DM drivers.
© 2020 Microchip Technology Inc.
DS60001477C-page 837
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.9
Device Registers - Common -Register Summary
Offset
Name
0x00
...
0x07
Reserved
0x08
CTRLB
0x0A
0x0B
0x0C
0x0D
...
0x0F
DADD
Reserved
STATUS
7:0
15:8
7:0
7:0
TSTPCKT
NREPLY
ADDEN
LINESTATE[1:0]
SPDCONF[1:0]
LPMHDSK[1:0]
DADD[6:0]
UPRSM
GNAK
DETACH
OPMODE2
LPMSUSP
SUSPEND
LPMNYET
LPMSUSP
SUSPEND
LPMNYET
LPMSUSP
SUSPEND
LPMNYET
EPINT1
EPINT0
SPEED[1:0]
Reserved
0x10
FNUM
0x12
...
0x13
Reserved
0x14
INTENCLR
0x16
...
0x17
Reserved
0x18
INTENSET
0x1A
...
0x1B
Reserved
0x1C
INTFLAG
0x1E
...
0x1F
Reserved
0x20
EPINTSMRY
39.10
Bit Pos.
7:0
15:8
FNUM[4:0]
FNCERR
7:0
15:8
RAMACER
7:0
15:8
RAMACER
7:0
15:8
RAMACER
7:0
15:8
EPINT7
FNUM[10:5]
UPRSM
UPRSM
UPRSM
EPINT6
EORSM
EORSM
EORSM
EPINT5
WAKEUP
WAKEUP
WAKEUP
EPINT4
EORST
EORST
EORST
EPINT3
SOF
SOF
SOF
EPINT2
Device Registers - Common
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
Refer to PAC - Peripheral Access Controller and 37.6.6 Synchronizationfor details.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.10.1 Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x08
0x0000
PAC Write-Protection
15
14
13
12
11
10
LPMHDSK[1:0]
R/W
R/W
0
0
9
GNAK
R/W
0
8
OPMODE2
R/W
0
7
TSTPCKT
R/W
0
6
5
4
NREPLY
R
0
3
2
SPDCONF[1:0]
R/W
R/W
0
0
1
UPRSM
R/W
0
0
DETACH
R/W
0
Access
Reset
Bit
Access
Reset
Bits 11:10 – LPMHDSK[1:0] Link Power Management Handshake
These bits select the Link Power Management Handshake configuration.
Value
Description
0x0
No handshake. LPM is not supported.
0x1
ACK
0x2
NYET
0x3
Reserved
Bit 9 – GNAK Global NAK
This bit configures the operating mode of the NAK.
This bit is not synchronized.
Value
Description
0
The handshake packet reports the status of the USB transaction
1
A NAK handshake is answered for each USB transaction regardless of the current endpoint memory
bank status
Bit 8 – OPMODE2 Specific Operational Mode
Value
Description
0
The UTMI transceiver is in normal operation Mode.
1
The UTMI transceiver is in the “disabled bit stuffing and NRZI encoding” operational mode for test
purpose.
Bit 7 – TSTPCKT Test Packet Mode
Value
Description
0
The UTMI transceiver is in normal operation Mode.
1
The UTMI transceiver generates test packets for test purpose.
Bit 4 – NREPLY No reply excepted SETUP Token
This bit is cleared by hardware when receiving a SETUP packet.
This bit has no effect for any other endpoint but endpoint 0.
Value
Description
0
Disable the “NO_REPLY” feature: Any transaction to endpoint 0 will be handled according to the
USB2.0 standard.
1
Enable the “NO_REPLY” feature: Any transaction to endpoint 0 will be ignored except SETUP.
Bits 3:2 – SPDCONF[1:0] Speed Configuration
These bits select the speed configuration.
Value
Description
0x0
FS: Full-speed
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
Value
0x1
Description
LS: Low-speed
Bit 1 – UPRSM Upstream Resume
This bit is cleared when the USB receives a USB reset or once the upstream resume has been sent.
Value
Description
0
Writing a zero to this bit has no effect.
1
Writing a one to this bit will generate an upstream resume to the host for a remote wakeup.
Bit 0 – DETACH Detach
Value
Description
0
The device is attached to the USB bus so that communications may occur.
1
It is the default value at reset. The internal device pull-ups are disabled, removing the device from the
USB bus.
© 2020 Microchip Technology Inc.
DS60001477C-page 840
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.10.2 Device Address
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
ADDEN
R/W
0
DADD
0x0A
0x00
PAC Write-Protection
6
5
4
R/W
0
R/W
0
R/W
0
3
DADD[6:0]
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bit 7 – ADDEN Device Address Enable
This bit is cleared when a USB reset is received.
Value
Description
0
Writing a zero will deactivate the DADD field (USB device address) and return the device to default
address 0.
1
Writing a one will activate the DADD field (USB device address).
Bits 6:0 – DADD[6:0] Device Address
These bits define the device address. The DADD register is reset when a USB reset is received.
© 2020 Microchip Technology Inc.
DS60001477C-page 841
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.10.3 Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x0C
0x40
-
7
6
LINESTATE[1:0]
R
R
0
1
Access
Reset
5
4
3
2
1
0
SPEED[1:0]
R/W
0
R/W
1
Bits 7:6 – LINESTATE[1:0] USB Line State Status
These bits define the current line state DP/DM.
LINESTATE[1:0]
USB Line Status
0x0
0x1
0x2
SE0/RESET
FS-J or LS-K State
FS-K or LS-J State
Bits 3:2 – SPEED[1:0] Speed Status
These bits define the current speed used of the device
.
SPEED[1:0]
SPEED STATUS
0x0
0x1
0x2
0x3
Low-speed mode
Full-speed mode
Reserved
Reserved
© 2020 Microchip Technology Inc.
DS60001477C-page 842
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.10.4 Device Frame Number
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
FNUM
0x10
0x0000
Read only
15
FNCERR
R/W
0
14
7
6
R/W
0
R/W
0
13
12
11
10
FNUM[10:5]
R/W
R/W
0
0
R/W
0
R/W
0
5
FNUM[4:0]
R/W
0
4
3
R/W
0
R/W
0
2
9
8
R/W
0
R/W
0
1
0
Bit 15 – FNCERR Frame Number CRC Error
This bit is cleared upon receiving a USB reset.
This bit is set when a corrupted frame number is received.
This bit and the SOF interrupt bit are updated at the same time.
Bits 13:3 – FNUM[10:0] Frame Number
These bits are cleared upon receiving a USB reset.
These bits are updated with the frame number information as provided from the last SOF packet even if a corrupted
SOF is received.
© 2020 Microchip Technology Inc.
DS60001477C-page 843
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.10.5 Device Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x14
0x0000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
15
14
13
12
11
10
9
LPMSUSP
R/W
0
8
LPMNYET
R/W
0
7
RAMACER
R/W
0
6
UPRSM
R/W
0
5
EORSM
R/W
0
4
WAKEUP
R/W
0
3
EORST
R/W
0
2
SOF
R/W
0
1
0
SUSPEND
R/W
0
Access
Reset
Bit
Access
Reset
Bit 9 – LPMSUSP Link Power Management Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Suspend Interrupt Enable bit and disable the
corresponding interrupt request.
Value
Description
0
The Link Power Management Suspend interrupt is disabled.
1
The Link Power Management Suspend interrupt is enabled and an interrupt request will be generated
when the Link Power Management Suspend interrupt Flag is set.
Bit 8 – LPMNYET Link Power Management Not Yet Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Link Power Management Not Yet interrupt Enable bit and disable the
corresponding interrupt request.
Value
Description
0
The Link Power Management Not Yet interrupt is disabled.
1
The Link Power Management Not Yet interrupt is enabled and an interrupt request will be generated
when the Link Power Management Not Yet interrupt Flag is set.
Bit 7 – RAMACER RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access
interrupt Flag is set.
Bit 6 – UPRSM Upstream Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Upstream Resume interrupt is disabled.
1
The Upstream Resume interrupt is enabled and an interrupt request will be generated when the
Upstream Resume interrupt Flag is set.
© 2020 Microchip Technology Inc.
DS60001477C-page 844
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Bit 5 – EORSM End Of Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End Of Resume interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The End Of Resume interrupt is disabled.
1
The End Of Resume interrupt is enabled and an interrupt request will be generated when the End Of
Resume interrupt Flag is set.
Bit 4 – WAKEUP Wake-Up Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Wake Up interrupt is disabled.
1
The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up
interrupt Flag is set.
Bit 3 – EORST End of Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the End of Reset interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The End of Reset interrupt is disabled.
1
The End of Reset interrupt is enabled and an interrupt request will be generated when the End of
Reset interrupt Flag is set.
Bit 2 – SOF Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Start-of-Frame interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Start-of-Frame interrupt is disabled.
1
The Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Start-ofFrame interrupt Flag is set.
Bit 0 – SUSPEND Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Suspend Interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Suspend interrupt is disabled.
1
The Suspend interrupt is enabled and an interrupt request will be generated when the Suspend
interrupt Flag is set.
© 2020 Microchip Technology Inc.
DS60001477C-page 845
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.10.6 Device Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x18
0x0000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
15
14
13
12
11
10
9
LPMSUSP
R/W
0
8
LPMNYET
R/W
0
7
RAMACER
R/W
0
6
UPRSM
R/W
0
5
EORSM
R/W
0
4
WAKEUP
R/W
0
3
EORST
R/W
0
2
SOF
R/W
0
1
0
SUSPEND
R/W
0
Access
Reset
Bit
Access
Reset
Bit 9 – LPMSUSP Link Power Management Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Link Power Management Suspend Enable bit and enable the corresponding
interrupt request.
Value
Description
0
The Link Power Management Suspend interrupt is disabled.
1
The Link Power Management Suspend interrupt is enabled.
Bit 8 – LPMNYET Link Power Management Not Yet Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Link Power Management Not Yet interrupt bit and enable the corresponding
interrupt request.
Value
Description
0
The Link Power Management Not Yet interrupt is disabled.
1
The Link Power Management Not Yet interrupt is enabled.
Bit 7 – RAMACER RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access Enable bit and enable the corresponding interrupt request.
Value
Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled.
Bit 6 – UPRSM Upstream Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume Enable bit and enable the corresponding interrupt request.
Value
Description
0
The Upstream Resume interrupt is disabled.
1
The Upstream Resume interrupt is enabled.
Bit 5 – EORSM End Of Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the End Of Resume interrupt Enable bit and enable the corresponding interrupt
request.
Value
Description
0
The End Of Resume interrupt is disabled.
1
The End Of Resume interrupt is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 846
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Bit 4 – WAKEUP Wake-Up Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the corresponding interrupt request.
Value
Description
0
The Wake Up interrupt is disabled.
1
The Wake Up interrupt is enabled.
Bit 3 – EORST End of Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the End of Reset interrupt Enable bit and enable the corresponding interrupt request.
Value
Description
0
The End of Reset interrupt is disabled.
1
The End of Reset interrupt is enabled.
Bit 2 – SOF Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Start-of-Frame interrupt Enable bit and enable the corresponding interrupt request.
Value
Description
0
The Start-of-Frame interrupt is disabled.
1
The Start-of-Frame interrupt is enabled.
Bit 0 – SUSPEND Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Suspend interrupt Enable bit and enable the corresponding interrupt request.
Value
Description
0
The Suspend interrupt is disabled.
1
The Suspend interrupt is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 847
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.10.7 Device Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x01C
0x0000
-
15
14
13
12
11
10
9
LPMSUSP
R/W
0
8
LPMNYET
R/W
0
7
RAMACER
R/W
0
6
UPRSM
R/W
0
5
EORSM
R/W
0
4
WAKEUP
R/W
0
3
EORST
R/W
0
2
SOF
R/W
0
1
0
SUSPEND
R/W
0
Access
Reset
Bit
Access
Reset
Bit 9 – LPMSUSP Link Power Management Suspend Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB module acknowledge a Link Power Management Transaction (ACK handshake) and
has entered the Suspended state and will generate an interrupt if INTENCLR/SET.LPMSUSP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the LPMSUSP Interrupt Flag.
Bit 8 – LPMNYET Link Power Management Not Yet Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB module acknowledges a Link Power Management Transaction (handshake is NYET)
and will generate an interrupt if INTENCLR/SET.LPMNYET is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the LPMNYET Interrupt Flag.
Bit 7 – RAMACER RAM Access Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a RAM access underflow error occurs during IN data stage. This bit will generate an interrupt if
INTENCLR/SET.RAMACER is one.
Writing a zero to this bit has no effect.
Bit 6 – UPRSM Upstream Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB sends a resume signal called “Upstream Resume” and will generate an interrupt if
INTENCLR/SET.UPRSM is one.
Writing a zero to this bit has no effect.
Bit 5 – EORSM End Of Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB detects a valid “End of Resume” signal initiated by the host and will generate an
interrupt if INTENCLR/SET.EORSM is one.
Writing a zero to this bit has no effect.
Bit 4 – WAKEUP Wake Up Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB is reactivated by a filtered non-idle signal from the lines and will generate an interrupt if
INTENCLR/SET.WAKEUP is one.
Writing a zero to this bit has no effect.
© 2020 Microchip Technology Inc.
DS60001477C-page 848
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Bit 3 – EORST End of Reset Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “End of Reset” has been detected and will generate an interrupt if INTENCLR/
SET.EORST is one.
Writing a zero to this bit has no effect.
Bit 2 – SOF Start-of-Frame Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Start-of-Frame” has been detected (every 1 ms) and will generate an interrupt if
INTENCLR/SET.SOF is one.
The FNUM is updated.
Writing a zero to this bit has no effect.
Bit 0 – SUSPEND Suspend Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Suspend” idle state has been detected for 3 frame periods (J state for 3 ms) and will
generate an interrupt if INTENCLR/SET.SUSPEND is one.
Writing a zero to this bit has no effect.
© 2020 Microchip Technology Inc.
DS60001477C-page 849
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.10.8 Endpoint Interrupt Summary
Name:
Offset:
Reset:
Property:
Bit
EPINTSMRY
0x20
0x0000
-
15
14
13
12
11
10
9
8
7
EPINT7
R
0
6
EPINT6
R
0
5
EPINT5
R
0
4
EPINT4
R
0
3
EPINT3
R
0
2
EPINT2
R
0
1
EPINT1
R
0
0
EPINT0
R
0
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – EPINT EndPoint Interrupt
The flag EPINT[n] is set when an interrupt is triggered by the EndPoint n. See 39.12.5 EPINTFLAGn register in the
device EndPoint section.
This bit will be cleared when no interrupts are pending for EndPoint n.
© 2020 Microchip Technology Inc.
DS60001477C-page 850
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.11
Offset
0x00
...
0xFF
0x0100
0x0101
...
0x0103
0x0104
0x0105
0x0106
0x0107
0x0108
0x0109
39.12
Device Endpoint Register Summary
Name
Bit Pos.
Reserved
EPCFGn
7:0
EPTYPE1[2:0]
EPTYPE0[2:0]
Reserved
EPSTATUSCLRn
EPSTATUSSETn
EPSTATUSn
EPINTFLAGn
EPINTENCLRn
EPINTENSETn
7:0
7:0
7:0
7:0
7:0
7:0
BK1RDY
BK1RDY
BK1RDY
BK0RDY
BK0RDY
BK0RDY
STALL1
STALL1
STALL1
STALLRQ1
STALLRQ1
STALLRQ1
STALL0
STALL0
STALL0
STALLRQ0
STALLRQ0
STALLRQ0
RXSTP
RXSTP
RXSTP
TRFAIL1
TRFAIL1
TRFAIL1
CURBK
CURBK
CURBK
TRFAIL0
TRFAIL0
TRFAIL0
DTGLIN
DTGLIN
DTGLIN
TRCPT1
TRCPT1
TRCPT1
DTGLOUT
DTGLOUT
DTGLOUT
TRCPT0
TRCPT0
TRCPT0
Device Endpoint Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
Refer to PAC - Peripheral Access Controller and 37.6.6 Synchronizationfor details.
© 2020 Microchip Technology Inc.
DS60001477C-page 851
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.12.1 Device Endpoint Configuration register n
Name:
Offset:
Reset:
Property:
Bit
7
Access
Reset
EPCFGn
0x100 [+ (n x 0x20)]
0x00
PAC Write-Protection
6
R/W
0
5
EPTYPE1[2:0]
R/W
0
4
3
R/W
0
2
R/W
0
1
EPTYPE0[2:0]
R/W
0
0
R/W
0
Bits 6:4 – EPTYPE1[2:0] Endpoint Type for IN direction
These bits contains the endpoint type for IN direction.
Upon receiving a USB reset EPCFGn.EPTYPE1 is cleared except for endpoint 0 which is unchanged.
Value
Description
0x0
Bank1 is disabled.
0x1
Bank1 is enabled and configured as Control IN.
0x2
Bank1 is enabled and configured as Isochronous IN.
0x3
Bank1 is enabled and configured as Bulk IN.
0x4
Bank1 is enabled and configured as Interrupt IN.
0x5
Bank1 is enabled and configured as Dual-Bank OUT
0x6-0x7
(Endpoint type is the same as the one defined in EPTYPE0)
Reserved
Bits 2:0 – EPTYPE0[2:0] Endpoint Type for OUT direction
These bits contains the endpoint type for OUT direction.
Upon receiving a USB reset EPCFGn.EPTYPE0 is cleared except for endpoint 0 which is unchanged.
Value
Description
0x0
Bank0 is disabled.
0x1
Bank0 is enabled and configured as Control SETUP / Control OUT.
0x2
Bank0 is enabled and configured as Isochronous OUT.
0x3
Bank0 is enabled and configured as Bulk OUT.
0x4
Bank0 is enabled and configured as Interrupt OUT.
0x5
Bank0 is enabled and configured as Dual Bank IN
0x6-0x7
(Endpoint type is the same as the one defined in EPTYPE1)
Reserved
© 2020 Microchip Technology Inc.
DS60001477C-page 852
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.12.2 EndPoint Status Clear n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
BK1RDY
W
0
EPSTATUSCLRn
0x104 [+ (n * 0x20)]
0x00
PAC Write-Protection
6
BK0RDY
W
0
5
STALLRQ1
W
0
4
STALLRQ0
W
0
3
2
CURBK
W
0
1
DTGLIN
W
0
0
DTGLOUT
W
0
Bit 7 – BK1RDY Bank 1 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.BK1RDY bit.
Bit 6 – BK0RDY Bank 0 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.BK0RDY bit.
Bit 5 – STALLRQ1 STALL bank 1 Request Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.STALLRQ1 bit.
Bit 4 – STALLRQ0 STALL bank 0 Request Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.STALLRQ0 bit.
Bit 2 – CURBK Current Bank Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.CURBK bit.
Bit 1 – DTGLIN Data Toggle IN Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear EPSTATUS.DTGLIN bit.
Bit 0 – DTGLOUT Data Toggle OUT Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the EPSTATUS.DTGLOUT bit.
© 2020 Microchip Technology Inc.
DS60001477C-page 853
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.12.3 EndPoint Status Set n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
BK1RDY
W
0
EPSTATUSSETn
0x105 [+ (n x 0x20)]
0x00
PAC Write-Protection
6
BK0RDY
W
0
5
STALLRQ1
W
0
4
STALLRQ0
W
0
3
2
CURBK
W
0
1
DTGLIN
W
0
0
DTGLOUT
W
0
Bit 7 – BK1RDY Bank 1 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.BK1RDY bit.
Bit 6 – BK0RDY Bank 0 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.BK0RDY bit.
Bit 5 – STALLRQ1 STALL Request bank 1 Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.STALLRQ1 bit.
Bit 4 – STALLRQ0 STALL Request bank 0 Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.STALLRQ0 bit.
Bit 2 – CURBK Current Bank Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.CURBK bit.
Bit 1 – DTGLIN Data Toggle IN Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set EPSTATUS.DTGLIN bit.
Bit 0 – DTGLOUT Data Toggle OUT Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the EPSTATUS.DTGLOUT bit.
© 2020 Microchip Technology Inc.
DS60001477C-page 854
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.12.4 EndPoint Status n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
BK1RDY
R
0
EPSTATUSn
0x106 [ + (n x 0x20)]
0x00
PAC Write-Protection
6
BK0RDY
R
0
5
STALLRQ1
R
0
4
STALLRQ0
R
2
3
2
CURBK
R
0
1
DTGLIN
R
0
0
DTGLOUT
R
0
Bit 7 – BK1RDY Bank 1 is ready
For Control/OUT direction Endpoints, the bank is empty.
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
Value
Description
0
The bank number 1 is not ready : For IN direction Endpoints, the bank is not yet filled in.
1
The bank number 1 is ready: For IN direction Endpoints, the bank is filled in. For Control/OUT direction
Endpoints, the bank is full.
Bit 6 – BK0RDY Bank 0 is ready
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
Value
Description
0
The bank number 0 is not ready : For IN direction Endpoints, the bank is not yet filled in. For
Control/OUT direction Endpoints, the bank is empty.
1
The bank number 0 is ready: For IN direction Endpoints, the bank is filled in. For Control/OUT direction
Endpoints, the bank is full.
Bits 4, 5 – STALLRQ STALL bank x request
Writing a zero to the bit EPSTATUSCLR.STALLRQ will clear this bit.
Writing a one to the bit EPSTATUSSET.STALLRQ will set this bit.
This bit is cleared by hardware when receiving a SETUP packet.
Value
Description
0
Disable STALLRQx feature.
1
Enable STALLRQx feature: a STALL handshake will be sent to the host in regards to bank x.
Bit 2 – CURBK Current Bank
Writing a zero to the bit EPSTATUSCLR.CURBK will clear this bit.
Writing a one to the bit EPSTATUSSET.CURBK will set this bit.
Value
Description
0
The bank0 is the bank that will be used in the next single/multi USB packet.
1
The bank1 is the bank that will be used in the next single/multi USB packet.
Bit 1 – DTGLIN Data Toggle IN Sequence
Writing a zero to the bit EPSTATUSCLR.DTGLINCLR will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGLINSET will set this bit.
Value
Description
0
The PID of the next expected IN transaction will be zero: data 0.
1
The PID of the next expected IN transaction will be one: data 1.
Bit 0 – DTGLOUT Data Toggle OUT Sequence
Writing a zero to the bit EPSTATUSCLR.DTGLOUTCLR will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGLOUTSET will set this bit.
© 2020 Microchip Technology Inc.
DS60001477C-page 855
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Value
0
1
Description
The PID of the next expected OUT transaction will be zero: data 0.
The PID of the next expected OUR transaction will be one: data 1.
© 2020 Microchip Technology Inc.
DS60001477C-page 856
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.12.5 Device EndPoint Interrupt Flag n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
EPINTFLAGn
0x107 [+ (n x 0x20)]
0x00
-
6
STALL1
R/W
0
5
STALL0
R/W
2
4
RXSTP
R/W
0
3
TRFAIL1
R/W
0
2
TRFAIL0
R/W
2
1
TRCPT1
R/W
0
0
TRCPT0
R/W
2
Bits 5, 6 – STALL Transmit Stall x Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transmit Stall occurs and will generate an interrupt if EPINTENCLR/SET.STALL is one.
EPINTFLAG.STALL is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is "0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the STALL Interrupt Flag.
Bit 4 – RXSTP Received Setup Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Received Setup occurs and will generate an interrupt if EPINTENCLR/SET.RXSTP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the RXSTP Interrupt Flag.
Bits 2, 3 – TRFAIL Transfer Fail x Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a transfer fail occurs and will generate an interrupt if EPINTENCLR/SET.TRFAIL is one.
EPINTFLAG.TRFAIL is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is
"0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRFAIL Interrupt Flag.
Bits 0, 1 – TRCPT Transfer Complete x interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer complete occurs and will generate an interrupt if EPINTENCLR/SET.TRCPT is one.
EPINTFLAG.TRCPT is set for a single bank OUT endpoint or double bank IN/OUT endpoint when current bank is "0".
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRCPT0 Interrupt Flag.
© 2020 Microchip Technology Inc.
DS60001477C-page 857
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.12.6 Device EndPoint Interrupt Enable n
Name:
Offset:
Reset:
Property:
EPINTENCLRn
0x108 [+ (n x 0x20)]
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENSET) register.
Bit
Access
Reset
7
6
STALL1
R/W
0
5
STALL0
R/W
2
4
RXSTP
R/W
0
3
TRFAIL1
R/W
0
2
TRFAIL0
R/W
2
1
TRCPT1
R/W
0
0
TRCPT0
R/W
2
Bits 5, 6 – STALL Transmit STALL x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmit Stall x Interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transmit Stall x interrupt is disabled.
1
The Transmit Stall x interrupt is enabled and an interrupt request will be generated when the Transmit
Stall x Interrupt Flag is set.
Bit 4 – RXSTP Received Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Setup Interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Received Setup interrupt is disabled.
1
The Received Setup interrupt is enabled and an interrupt request will be generated when the Received
Setup Interrupt Flag is set.
Bits 2, 3 – TRFAIL Transfer Fail x Interrupt Enable
The user should look into the descriptor table status located in ram to be informed about the error condition :
ERRORFLOW, CRC.
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail x Interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transfer Fail bank x interrupt is disabled.
1
The Transfer Fail bank x interrupt is enabled and an interrupt request will be generated when the
Transfer Fail x Interrupt Flag is set.
Bits 0, 1 – TRCPT Transfer Complete x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete x interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transfer Complete bank x interrupt is disabled.
1
The Transfer Complete bank x interrupt is enabled and an interrupt request will be generated when the
Transfer Complete x Interrupt Flag is set.
© 2020 Microchip Technology Inc.
DS60001477C-page 858
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.12.7 Device Interrupt EndPoint Set n
Name:
Offset:
Reset:
Property:
EPINTENSETn
0x109 [+ (n x 0x20)]
0x0000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENCLR) register. This register is cleared by
USB reset or when EPEN[n] is zero.
Bit
Access
Reset
7
6
STALL1
R/W
0
5
STALL0
R/W
2
4
RXSTP
R/W
0
3
TRFAIL1
R/W
0
2
TRFAIL0
R/W
2
1
TRCPT1
R/W
0
0
TRCPT0
R/W
2
Bits 5, 6 – STALL Transmit Stall x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmit bank x Stall interrupt.
Value
Description
0
The Transmit Stall x interrupt is disabled.
1
The Transmit Stall x interrupt is enabled.
Bit 4 – RXSTP Received Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Received Setup interrupt.
Value
Description
0
The Received Setup interrupt is disabled.
1
The Received Setup interrupt is enabled.
Bits 2, 3 – TRFAIL Transfer Fail bank x Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Value
Description
0
The Transfer Fail interrupt is disabled.
1
The Transfer Fail interrupt is enabled.
Bits 0, 1 – TRCPT Transfer Complete bank x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete x interrupt.
0.2.4 Device Registers - Endpoint RAM
Value
Description
0
The Transfer Complete bank x interrupt is disabled.
1
The Transfer Complete bank x interrupt is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 859
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Endpoint Descriptor Structure
Data Buffers
EPn BK1
EPn BK0
Endpoint
descriptors
Reserved
Bank1
Reserved
PCKSIZE
ADDR
(2 x 0xn0) + 0x10
Reserved
STATUS_BK
Bank0
EXTREG
PCKSIZE
ADDR
2 x 0xn0
Reserved
+0x01B
+0x01A
+0x018
+0x014
+0x010
+0x00B
+0x00A
+0x008
+0x004
+0x000
STATUS_BK
Bank1
Reserved
PCKSIZE
ADDR
Bank0
Reserved
STATUS_BK
EXTREG
PCKSIZE
ADDR
© 2020 Microchip Technology Inc.
Growing Memory Addresses
Descriptor En
STATUS_BK
Descriptor E0
39.13
DESCADD
DS60001477C-page 860
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.14
Device Endpoint RAM Register Summary
Offset
Name
0x00
ADDR
0x04
PCKSIZE
0x08
EXTREG
0x0A
STATUS_BK
39.15
Bit Pos.
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
7:0
MULTI_PACKET_SIZE[1:0]
AUTO_ZLP
SIZE[2:0]
VARIABLE[3:0]
ADDR[7:0]
ADDR[15:8]
ADDR[23:16]
ADDR[31:24]
BYTE_COUNT[7:0]
BYTE_COUNT[13:8]
MULTI_PACKET_SIZE[9:2]
MULTI_PACKET_SIZE[13:10]
SUBPID[3:0]
VARIABLE[10:4]
ERRORFLOW
CRCERR
Device Endpoint RAM Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
Refer to PAC - Peripheral Access Controller and 37.6.6 Synchronizationfor details.
© 2020 Microchip Technology Inc.
DS60001477C-page 861
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.15.1 Address of Data Buffer
Name:
Offset:
Reset:
Property:
ADDR
0x00
0xXXXXXXX
NA
Old address offset 0x00 and 0x10
Bit
Access
Reset
Bit
Access
Reset
Bit
31
30
29
R/W
x
R/W
x
R/W
x
23
22
21
R/W
x
R/W
x
R/W
x
15
14
13
28
27
ADDR[31:24]
R/W
R/W
x
x
26
25
24
R/W
x
R/W
x
R/W
x
18
17
16
R/W
x
R/W
x
R/W
x
11
10
9
8
R/W
x
R/W
x
R/W
x
R/W
x
3
2
1
0
R/W
x
R/W
x
R/W
x
R/W
x
20
19
ADDR[23:16]
R/W
R/W
x
x
12
ADDR[15:8]
Access
Reset
Bit
R/W
x
R/W
x
R/W
x
R/W
x
7
6
5
4
ADDR[7:0]
Access
Reset
R/W
x
R/W
x
R/W
x
R/W
x
Bits 31:0 – ADDR[31:0] Data Pointer Address Value
These bits define the data pointer address as an absolute word address in RAM. The two least significant bits must
be zero to ensure the start address is 32-bit aligned.
© 2020 Microchip Technology Inc.
DS60001477C-page 862
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.15.2 Packet Size
Name:
Offset:
Reset:
Property:
PCKSIZE
0x04
0xXXXXXXXX
NA
Original offset 0x04 & 0x14
Bit
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
31
AUTO_ZLP
R/W
x
R/W
0
29
SIZE[2:0]
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
MULTI_PACKET_SIZE[1:0]
R/W
R/W
0
x
Bit
Access
Reset
30
28
27
R/W
x
R/W
0
20
19
MULTI_PACKET_SIZE[9:2]
R/W
R/W
0
0
13
12
R/W
0
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
26
25
MULTI_PACKET_SIZE[13:10]
R/W
R/W
0
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
9
8
R/W
0
R/W
0
2
1
0
R/W
0
R/W
0
R/W
x
11
10
BYTE_COUNT[13:8]
R/W
R/W
0
0
4
3
BYTE_COUNT[7:0]
R/W
R/W
0
0
24
Bit 31 – AUTO_ZLP Automatic Zero Length Packet
This bit defines the automatic Zero Length Packet mode of the endpoint.
When enabled, the USB module will manage the ZLP handshake by hardware. This bit is for IN endpoints only. When
disabled the handshake should be managed by firmware.
Value
Description
0
Automatic Zero Length Packet is disabled.
1
Automatic Zero Length Packet is enabled.
Bits 30:28 – SIZE[2:0] Endpoint size
These bits contains the maximum packet size of the endpoint.
Value
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
(1) for Isochronous endpoints only.
8 Byte
16 Byte
32 Byte
64 Byte
128 Byte(1)
256 Byte(1)
512 Byte(1)
1023 Byte(1)
Bits 27:14 – MULTI_PACKET_SIZE[13:0] Multiple Packet Size
These bits define the 14-bit value that is used for multi-packet transfers.
For IN endpoints, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be
written to zero when setting up a new transfer.
For OUT endpoints, MULTI_PACKET_SIZE holds the total data size for the complete transfer. This value must be a
multiple of the maximum packet size.
© 2020 Microchip Technology Inc.
DS60001477C-page 863
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Bits 13:0 – BYTE_COUNT[13:0] Byte Count
These bits define the 14-bit value that is used for the byte count.
For IN endpoints, BYTE_COUNT holds the number of bytes to be sent in the next IN transaction.
For OUT endpoint or SETUP endpoints, BYTE_COUNT holds the number of bytes received upon the last OUT or
SETUP transaction.
© 2020 Microchip Technology Inc.
DS60001477C-page 864
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.15.3 Extended Register
Name:
Offset:
Reset:
Property:
Bit
EXTREG
0x08
0xXXXXXXX
NA
15
Access
Reset
Bit
7
Access
Reset
R/W
0
14
13
12
R/W
0
R/W
0
6
5
VARIABLE[3:0]
R/W
R/W
0
0
10
9
8
R/W
0
11
VARIABLE[10:4]
R/W
0
R/W
0
R/W
0
R/W
0
4
3
2
R/W
x
R/W
0
1
SUBPID[3:0]
R/W
R/W
0
0
0
R/W
x
Bits 14:4 – VARIABLE[10:0] Variable field send with extended token
These bits define the VARIABLE field of a received extended token. These bits are updated when the USB has
answered by an handshake token ACK to a LPM transaction. See Section 2.1.1 Protocol Extension Token in the
reference document “ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”.
To support the USB2.0 Link Power Management addition the VARIABLE field should be read as described below.
VARIABLES
Description
VARIABLE[3:0]
VARIABLE[7:4]
VARIABLE[8]
VARIABLE[10:9]
bLinkState (1)
BESL (2)
bRemoteWake (1)
Reserved
1.
2.
For a definition of LPM Token bRemoteWake and bLinkState fields, refer to "Table 2-3 in the reference
document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum".
For a definition of LPM Token BESL field, refer to "Table 2-3 in the reference document ENGINEERING
CHANGE NOTICE, USB 2.0 Link Power Management Addendum" and "Table X-X1 in Errata for ECN USB 2.0
Link Power Management.
Bits 3:0 – SUBPID[3:0] SUBPID field send with extended token
These bits define the SUBPID field of a received extended token. These bits are updated when the USB has
answered by an handshake token ACK to a LPM transaction. See Section 2.1.1 Protocol Extension Token in the
reference document “ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”.
© 2020 Microchip Technology Inc.
DS60001477C-page 865
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.15.4 Device Status Bank
Name:
Offset:
Reset:
Property:
STATUS_BK
0x0A
0xXXXXXXX
NA
Original offset 0x0A & 0x1A
Bit
7
6
Access
Reset
5
4
3
2
1
ERRORFLOW
R/W
x
0
CRCERR
R/W
x
Bit 1 – ERRORFLOW Error Flow Status
This bit defines the Error Flow Status.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For OUT transfer, a NAK handshake has been sent.
For Isochronous OUT transfer, an overrun condition has occurred.
For IN transfer, this bit is not valid. EPSTATUS.TRFAIL0 and EPSTATUS.TRFAIL1 should reflect the flow errors.
Value
Description
0
No Error Flow detected.
1
A Error Flow has been detected.
Bit 0 – CRCERR CRC Error
This bit defines the CRC Error Status.
This bit is set when a CRC error has been detected in an isochronous OUT endpoint bank.
0.2.5 Host Registers - Common
Value
Description
0
No CRC Error.
1
CRC Error detected.
© 2020 Microchip Technology Inc.
DS60001477C-page 866
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.16
Host Registers - Common - Register Summary
Offset
Name
0x00
...
0x07
Reserved
0x08
CTRLB
0x0A
0x0B
0x0C
0x0D
...
0x0F
HSOFC
Reserved
STATUS
AUTORESUM
E
7:0
15:8
7:0
7:0
SPDCONF[1:0]
L1RESUME
FLENCE
LINESTATE[1:0]
RESUME
VBUSOK
BUSRESET
FLENC[3:0]
SOFE
SPEED[1:0]
Reserved
0x10
FNUM
0x12
0x13
FLENHIGH
Reserved
0x14
INTENCLR
0x16
...
0x17
Reserved
0x18
INTENSET
0x1A
...
0x1B
Reserved
0x1C
INTFLAG
0x1E
...
0x1F
Reserved
0x20
PINTSMRY
39.17
Bit Pos.
7:0
15:8
7:0
FNUM[4:0]
FNUM[10:5]
FLENHIGH[7:0]
7:0
15:8
RAMACER
7:0
15:8
RAMACER
7:0
15:8
RAMACER
7:0
15:8
PINT7
UPRSM
UPRSM
UPRSM
PINT6
DNRSM
DNRSM
DNRSM
PINT5
WAKEUP
WAKEUP
WAKEUP
PINT4
RST
RST
RST
PINT3
HSOF
DDISC
DCONN
DDISC
DCONN
DDISC
DCONN
PINT1
PINT0
HSOF
HSOF
PINT2
Host Registers - Common - Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
Refer to PAC - Peripheral Access Controller and 37.6.6 Synchronizationfor details.
© 2020 Microchip Technology Inc.
DS60001477C-page 867
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.17.1 Control B
Name:
Offset:
Reset:
Property:
Bit
CTRLB
0x08
0x0000
PAC Write-Protection
15
14
13
12
7
6
5
4
AUTORESUME
R/W
0
Access
Reset
Bit
Access
Reset
11
L1RESUME
R/W
0
10
VBUSOK
R/W
0
3
2
SPDCONF[1:0]
R/W
R/W
0
0
9
BUSRESET
R/W
0
8
SOFE
R/W
0
1
RESUME
R/W
0
0
Bit 11 – L1RESUME Send USB L1 Resume
Writing 0 to this bit has no effect.
1: Generates a USB L1 Resume on the USB bus. This bit should only be set when the Start-of-Frame generation is
enabled (SOFE bit set). The duration of the USB L1 Resume is defined by the EXTREG.VARIABLE[7:4] bits field also
known as BESL (See LPM ECN).See also 39.22.3 EXTREG Register.
This bit is cleared when the USB L1 Resume has been sent or when a USB reset is requested.
Bit 10 – VBUSOK VBUS is OK
This notifies the USB HOST that USB operations can be started. When this bit is zero and even if the USB HOST is
configured and enabled, HOST operation is halted. Setting this bit will allow HOST operation when the USB is
configured and enabled.
Value
Description
0
The USB module is notified that the VBUS on the USB line is not powered.
1
The USB module is notified that the VBUS on the USB line is powered.
Bit 9 – BUSRESET Send USB Reset
Value
Description
0
Reset generation is disabled. It is written to zero when the USB reset is completed or when a device
disconnection is detected. Writing zero has no effect.
1
Generates a USB Reset on the USB bus.
Bit 8 – SOFE Start-of-Frame Generation Enable
Value
Description
0
The SOF generation is disabled and the USB bus is in suspend state.
1
Generates SOF on the USB bus in full speed and keep it alive in low speed mode. This bit is
automatically set at the end of a USB reset (INTFLAG.RST) or at the end of a downstream resume
(INTFLAG.DNRSM) or at the end of L1 resume.
Bit 4 – AUTORESUME Auto Resume Enable
Value
Description
0
The Auto Resume is disabled.
1
Enable Auto Resume
Bits 3:2 – SPDCONF[1:0] Speed Configuration for Host
These bits select the host speed configuration as shown below
Value
Description
0x0
Low and Full Speed capable
0x1
Reserved
0x2
Reserved
© 2020 Microchip Technology Inc.
DS60001477C-page 868
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Value
0x3
Description
Low and Full Speed capable
Bit 1 – RESUME Send USB Resume
Writing 0 to this bit has no effect.
1: Generates a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
© 2020 Microchip Technology Inc.
DS60001477C-page 869
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.17.2 Host Start-of-Frame Control
Name:
Offset:
Reset:
Property:
HSOFC
0x0A
0x00
PAC Write-Protection
During a very short period just before transmitting a Start-of-Frame, this register is locked. Thus, after writing, it is
recommended to check the register value, and write this register again if necessary. This register is cleared upon a
USB reset.
Bit
7
FLENCE
R/W
0
Access
Reset
6
5
4
3
2
1
0
R/W
0
R/W
0
FLENC[3:0]
R/W
0
R/W
0
Bit 7 – FLENCE Frame Length Control Enable
When this bit is '1', the time between Start-of-Frames can be tuned by up to +/-0.06% using FLENC[3:0].
Note: In Low Speed mode, FLENCE must be '0'.
FLENCE Frame Timing
Internal Frame Length Down-Counter Load Value
0
0
1
11999 (1ms frame rate at 12MHz)
59999 (1ms frame rate at 60MHz)
FLENC[3:0]
11999 + FLENC[3:0] at all speeds.
Value
0
1
Internal Frame Length (Full Speed)
Internal Frame Length in Low and Full speed
Beginning of Frame
Internal Frame Length with Frame correction
Description
Start-of-Frame is generated every 1ms.
Start-of-Frame generation depends on the signed value of FLENC[3:0].
USB Start-of-Frame period equals 1ms + (FLENC[3:0]/12000)ms
Bits 3:0 – FLENC[3:0] Frame Length Control
These bits define the signed value of the 4-bit FLENC that is added to the Internal Frame Length when FLENCE is
'1'. The internal Frame length is the top value of the frame counter when FLENCE is zero.
© 2020 Microchip Technology Inc.
DS60001477C-page 870
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.17.3 Status
Name:
Offset:
Reset:
Property:
Bit
STATUS
0x0C
0x00
Read only
7
6
LINESTATE[1:0]
R
R
0
0
Access
Reset
5
4
3
2
1
0
SPEED[1:0]
R/W
0
R/W
0
Bits 7:6 – LINESTATE[1:0] USB Line State Status
These bits define the current line state DP/DM.
LINESTATE[1:0]
USB Line Status
0x0
0x1
0x2
SE0/RESET
FS-J or LS-K State
FS-K or LS-J State
Bits 3:2 – SPEED[1:0] Speed Status
These bits define the current speed used by the host.
SPEED[1:0]
Speed Status
0x0
0x1
0x2
0x3
Full-speed mode
Reserved
Low-speed mode
Reserved
© 2020 Microchip Technology Inc.
DS60001477C-page 871
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.17.4 Host Frame Number
Name:
Offset:
Reset:
Property:
Bit
15
FNUM
0x10
0x0000
PAC Write-Protection
14
Access
Reset
Bit
Access
Reset
7
6
R/W
0
R/W
0
13
12
11
10
FNUM[10:5]
R/W
R/W
0
0
R/W
0
R/W
0
5
FNUM[4:0]
R/W
0
4
3
R/W
0
R/W
0
2
9
8
R/W
0
R/W
0
1
0
Bits 13:3 – FNUM[10:0] Frame Number
These bits contains the current SOF number.
These bits can be written by software to initialize a new frame number value. In this case, at the next SOF, the FNUM
field takes its new value.
As the FNUM register lies across two consecutive byte addresses, writing byte-wise (8-bits) to the FNUM register
may produce incorrect frame number generation. It is recommended to write FNUM register word-wise (32-bits) or
half-word-wise (16-bits).
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.17.5 Host Frame Length
Name:
Offset:
Reset:
Property:
FLENHIGH
0x12
0x00
Read-Only
Bit
7
6
5
Access
Reset
R
0
R
0
R
0
4
3
FLENHIGH[7:0]
R
R
0
0
2
1
0
R
0
R
0
R
0
Bits 7:0 – FLENHIGH[7:0] Frame Length
These bits contains the 8 high-order bits of the internal frame counter.
Table 39-1. Counter Description vs. Speed
Host Register
Description
STATUS.SPEED
Full Speed
Full Speed
With a USB clock running at 12MHz, counter length is 12000 to ensure a SOF generation every
1 ms.
With a USB clock running at 60MHz, counter length is 60000 to ensure a SOF generation every
1 ms.
© 2020 Microchip Technology Inc.
DS60001477C-page 873
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.17.6 Host Interrupt Enable Register Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x14
0x0000
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
15
14
13
12
11
10
9
DDISC
R/W
0
8
DCONN
R/W
0
7
RAMACER
R/W
0
6
UPRSM
R/W
0
5
DNRSM
R/W
0
4
WAKEUP
R/W
0
3
RST
R/W
0
2
HSOF
R/W
0
1
0
Access
Reset
Bit
Access
Reset
Bit 9 – DDISC Device Disconnection Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Disconnection interrupt Enable bit and disable the corresponding
interrupt request.
Value
Description
0
The Device Disconnection interrupt is disabled.
1
The Device Disconnection interrupt is enabled and an interrupt request will be generated when the
Device Disconnection interrupt Flag is set.
Bit 8 – DCONN Device Connection Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Device Connection interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Device Connection interrupt is disabled.
1
The Device Connection interrupt is enabled and an interrupt request will be generated when the Device
Connection interrupt Flag is set.
Bit 7 – RAMACER RAM Access Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the RAM Access interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled and an interrupt request will be generated when the RAM Access
interrupt Flag is set.
Bit 6 – UPRSM Upstream Resume from Device Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Upstream Resume interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Upstream Resume interrupt is disabled.
1
The Upstream Resume interrupt is enabled and an interrupt request will be generated when the
Upstream Resume interrupt Flag is set.
© 2020 Microchip Technology Inc.
DS60001477C-page 874
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Bit 5 – DNRSM Down Resume Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Down Resume interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Down Resume interrupt is disabled.
1
The Down Resume interrupt is enabled and an interrupt request will be generated when the Down
Resume interrupt Flag is set.
Bit 4 – WAKEUP Wake Up Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Wake Up interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Wake Up interrupt is disabled.
1
The Wake Up interrupt is enabled and an interrupt request will be generated when the Wake Up
interrupt Flag is set.
Bit 3 – RST BUS Reset Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Bus Reset interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Bus Reset interrupt is disabled.
1
The Bus Reset interrupt is enabled and an interrupt request will be generated when the Bus Reset
interrupt Flag is set.
Bit 2 – HSOF Host Start-of-Frame Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Host Start-of-Frame interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Host Start-of-Frame interrupt is disabled.
1
The Host Start-of-Frame interrupt is enabled and an interrupt request will be generated when the Host
Start-of-Frame interrupt Flag is set.
© 2020 Microchip Technology Inc.
DS60001477C-page 875
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.17.7 Host Interrupt Enable Register Set
Name:
Offset:
Reset:
Property:
INTENSET
0x18
0x0000
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
15
14
13
12
11
10
9
DDISC
R/W
0
8
DCONN
R/W
0
7
RAMACER
R/W
0
6
UPRSM
R/W
0
5
DNRSM
R/W
0
4
WAKEUP
R/W
0
3
RST
R/W
0
2
HSOF
R/W
0
1
0
Access
Reset
Bit
Access
Reset
Bit 9 – DDISC Device Disconnection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Disconnection interrupt bit and enable the DDSIC interrupt.
Value
Description
0
The Device Disconnection interrupt is disabled.
1
The Device Disconnection interrupt is enabled.
Bit 8 – DCONN Device Connection Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Device Connection interrupt bit and enable the DCONN interrupt.
Value
Description
0
The Device Connection interrupt is disabled.
1
The Device Connection interrupt is enabled.
Bit 7 – RAMACER RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access interrupt bit and enable the RAMACER interrupt.
Value
Description
0
The RAM Access interrupt is disabled.
1
The RAM Access interrupt is enabled.
Bit 6 – UPRSM Upstream Resume from the device Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume interrupt bit and enable the UPRSM interrupt.
Value
Description
0
The Upstream Resume interrupt is disabled.
1
The Upstream Resume interrupt is enabled.
Bit 5 – DNRSM Down Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Down Resume interrupt Enable bit and enable the DNRSM interrupt.
Value
Description
0
The Down Resume interrupt is disabled.
1
The Down Resume interrupt is enabled.
Bit 4 – WAKEUP Wake Up Interrupt Enable
Writing a zero to this bit has no effect.
© 2020 Microchip Technology Inc.
DS60001477C-page 876
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the WAKEUP interrupt request.
Value
Description
0
The WakeUp interrupt is disabled.
1
The WakeUp interrupt is enabled.
Bit 3 – RST Bus Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Bus Reset interrupt Enable bit and enable the Bus RST interrupt.
Value
Description
0
The Bus Reset interrupt is disabled.
1
The Bus Reset interrupt is enabled.
Bit 2 – HSOF Host Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Host Start-of-Frame interrupt Enable bit and enable the HSOF interrupt.
Value
Description
0
The Host Start-of-Frame interrupt is disabled.
1
The Host Start-of-Frame interrupt is enabled.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.17.8 Host Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
INTFLAG
0x1C
0x0000
-
15
14
13
12
11
10
9
DDISC
R/W
0
8
DCONN
R/W
0
7
RAMACER
R/W
0
6
UPRSM
R/W
0
5
DNRSM
R/W
0
4
WAKEUP
R/W
0
3
RST
R/W
0
2
HSOF
R/W
0
1
0
Access
Reset
Bit
Access
Reset
Bit 9 – DDISC Device Disconnection Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the device has been removed from the USB Bus and will generate an interrupt if INTENCLR/
SET.DDISC is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DDISC Interrupt Flag.
Bit 8 – DCONN Device Connection Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a new device has been connected to the USB BUS and will generate an interrupt if INTENCLR/
SET.DCONN is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the DCONN Interrupt Flag.
Bit 7 – RAMACER RAM Access Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a RAM access error occurs during an OUT stage and will generate an interrupt if INTENCLR/
SET.RAMACER is one.
Writing a zero to this bit has no effect.
Bit 6 – UPRSM Upstream Resume from the Device Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB has received an Upstream Resume signal from the Device and will generate an
interrupt if INTENCLR/SET.UPRSM is one.
Writing a zero to this bit has no effect.
Bit 5 – DNRSM Down Resume Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when the USB has sent a Down Resume and will generate an interrupt if INTENCLR/SET.DRSM is
one.
Writing a zero to this bit has no effect.
Bit 4 – WAKEUP Wake Up Interrupt Flag
This flag is cleared by writing a one.
This flag is set when:
l The host controller is in suspend mode (SOFE is zero) and an upstream resume from the device is detected.
l The host controller is in suspend mode (SOFE is zero) and an device disconnection is detected.
l The host controller is in operational state (VBUSOK is one) and an device connection is detected.
In all cases it will generate an interrupt if INTENCLR/SET.WAKEUP is one.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
USB – Universal Serial Bus
Writing a zero to this bit has no effect.
Bit 3 – RST Bus Reset Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Bus “Reset” has been sent to the Device and will generate an interrupt if INTENCLR/SET.RST
is one.
Writing a zero to this bit has no effect.
Bit 2 – HSOF Host Start-of-Frame Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a USB “Host Start-of-Frame” in Full Speed or a keep-alive in Low Speed has been sent (every 1
ms) and will generate an interrupt if INTENCLR/SET.HSOF is one.
The value of the FNUM register is updated.
Writing a zero to this bit has no effect.
© 2020 Microchip Technology Inc.
DS60001477C-page 879
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.17.9 Pipe Interrupt Summary
Name:
Offset:
Reset:
Property:
Bit
PINTSMRY
0x20
0x0000
Read-only
15
14
13
12
11
10
9
8
7
PINT7
R
0
6
PINT6
R
0
5
PINT5
R
0
4
PINT4
R
0
3
PINT3
R
0
2
PINT2
R
0
1
PINT1
R
0
0
PINT0
R
0
Access
Reset
Bit
Access
Reset
Bits 0, 1, 2, 3, 4, 5, 6, 7 – PINT
The flag PINTn is set when an interrupt is triggered by the pipe n. See 39.19.6 PINTFLAG register in the Host Pipe
Register section.
This bit will be cleared when there are no interrupts pending for Pipe n.
Writing to this bit has no effect.
© 2020 Microchip Technology Inc.
DS60001477C-page 880
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.18
Offset
0x00
...
0xFF
0x0100
0x0101
...
0x0102
0x0103
0x0104
0x0105
0x0106
0x0107
0x0108
0x0109
39.19
Host Registers - Pipe - Register Summary
Name
Bit Pos.
Reserved
PCFGn
7:0
PTYPE[2:0]
BK
PTOKEN[1:0]
Reserved
BINTERVAL
PSTATUSCLR
PSTATUSSET
PSTATUS
PINTFLAG
PINTENCLR
PINTENSET
7:0
7:0
7:0
7:0
7:0
7:0
7:0
BK1RDY
BK1RDY
BK1RDY
BK0RDY
BK0RDY
BK0RDY
STALL
STALL
STALL
BINTERVAL[7:0]
PFREEZE
PFREEZE
PFREEZE
TXSTP
PERR
TXSTP
PERR
TXSTP
PERR
CURBK
CURBK
CURBK
TRFAIL
TRFAIL
TRFAIL
TRCPT1
TRCPT1
TRCPT1
DTGL
DTGL
DTGL
TRCPT0
TRCPT0
TRCPT0
Host Registers - Pipe - Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
Refer to PAC - Peripheral Access Controller and 37.6.6 Synchronizationfor details.
© 2020 Microchip Technology Inc.
DS60001477C-page 881
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.19.1 Host Pipe n Configuration
Name:
Offset:
Reset:
Property:
Bit
PCFGn
0x100 [ + (n x 0x20)]
0x00
PAC Write-Protection
7
6
5
Access
Reset
R/W
0
4
PTYPE[2:0]
R/W
0
3
R/W
0
2
BK
R/W
0
1
0
PTOKEN[1:0]
R/W
R/W
0
0
Bits 5:3 – PTYPE[2:0] Type of the Pipe
These bits contains the pipe type.
PTYPE[2:0]
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x06-0x7
Pipe is disabled
Pipe is enabled and configured as CONTROL
Pipe is enabled and configured as ISO
Pipe is enabled and configured as BULK
Pipe is enabled and configured as INTERRUPT
Pipe is enabled and configured as EXTENDED
Reserved
These bits are cleared upon sending a USB reset.
Bit 2 – BK Pipe Bank
This bit selects the number of banks for the pipe.
For control endpoints writing a zero to this bit is required as only Bank0 is used for Setup/In/Out transactions.
This bit is cleared when a USB reset is sent.
BK(1)
Description
0x0
0x1
Single-bank endpoint
Dual-bank endpoint
1.
Value
0
1
Bank field is ignored when PTYPE is configured as EXTENDED.
Description
A single bank is used for the pipe.
A dual bank is used for the pipe.
Bits 1:0 – PTOKEN[1:0] Pipe Token
These bits contains the pipe token.
PTOKEN[1:0](1)
Description
0x0
0x1
0x2
0x3
SETUP(2)
IN
OUT
Reserved
1.
2.
PTOKEN field is ignored when PTYPE is configured as EXTENDED.
Available only when PTYPE is configured as CONTROL
Theses bits are cleared upon sending a USB reset.
© 2020 Microchip Technology Inc.
DS60001477C-page 882
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.19.2 Interval for the Bulk-Out/Ping Transaction
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
BINTERVAL
0x103 [ + (n x 0x20)]
0x00
PAC Write-Protection
7
6
5
R/W
0
R/W
0
R/W
0
4
3
BINTERVAL[7:0]
R/W
R/W
0
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 7:0 – BINTERVAL[7:0] BINTERVAL
These bits contains the Ping/Bulk-out period.
These bits are cleared when a USB reset is sent or when PEN[n] is zero.
BINTERVAL
Description
=0
>0
Multiple consecutive OUT token is sent in the same frame until it is acked by the peripheral
One OUT token is sent every BINTERVAL frame until it is acked by the peripheral
PCFGn.PINGEN BINTERVAL Description
0
=0
0
>0
1
=0
1
>0
Multiple consecutive OUT token is sent in the same frame until it is acked by the
peripheral
One OUT token is sent every BINTERVAL micro frame until it is acked by the
peripheral
Multiple consecutive PING token is sent in the same frame until it is acked by the
peripheral
One PING token is sent every BINTERVAL frame until it is acked by the peripheral
Depending from the type of pipe the desired period is defined as:
PTYPE
Description
Interrupt
Isochronous
Bulk or control
EXT LPM
1 ms to 255 ms
2^(Binterval) * 1 ms
1 ms to 255 ms
bInterval ignored. Always 1 ms when a NYET is received.
© 2020 Microchip Technology Inc.
DS60001477C-page 883
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.19.3 Pipe Status Clear n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
BK1RDY
W
0
PSTATUSCLR
0x104 [ + (n x 0x20)]
0x00
PAC Write-Protection
6
BK0RDY
W
0
5
4
PFREEZE
W
0
3
2
CURBK
W
0
1
0
DTGL
W
0
Bit 7 – BK1RDY Bank 1 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.BK1RDY bit.
Bit 6 – BK0RDY Bank 0 Ready Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.BK0RDY bit.
Bit 4 – PFREEZE Pipe Freeze Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.PFREEZE bit.
Bit 2 – CURBK Current Bank Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.CURBK bit.
Bit 0 – DTGL Data Toggle Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear PSTATUS.DTGL bit.
© 2020 Microchip Technology Inc.
DS60001477C-page 884
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.19.4 Pipe Status Set Register n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
BK1RDY
W
0
PSTATUSSET
0x105 [ + (n x 0x20)]
0x00
PAC Write-Protection
6
BK0RDY
W
0
5
4
PFREEZE
W
0
3
2
CURBK
W
0
1
0
DTGL
W
0
Bit 7 – BK1RDY Bank 1 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the bit PSTATUS.BK1RDY.
Bit 6 – BK0RDY Bank 0 Ready Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set the bit PSTATUS.BK0RDY.
Bit 4 – PFREEZE Pipe Freeze Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.PFREEZE bit.
Bit 2 – CURBK Current Bank Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.CURBK bit.
Bit 0 – DTGL Data Toggle Set
Writing a zero to this bit has no effect.
Writing a one to this bit will set PSTATUS.DTGL bit.
© 2020 Microchip Technology Inc.
DS60001477C-page 885
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.19.5 Pipe Status Register n
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
BK1RDY
R
0
PSTATUS
0x106 [ + (n x 0x20)]
0x00
PAC Write-Protection
6
BK0RDY
R
0
5
4
PFREEZE
R
0
3
2
CURBK
R
0
1
0
DTGL
R
0
Bit 7 – BK1RDY Bank 1 is ready
Writing a one to the bit EPSTATUSCLR.BK1RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK1RDY will set this bit.
This bank is not used for Control pipe.
Value
Description
0
The bank number 1 is not ready: For IN the bank is empty. For Control/OUT the bank is not yet fill in.
1
The bank number 1 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in.
Bit 6 – BK0RDY Bank 0 is ready
Writing a one to the bit EPSTATUSCLR.BK0RDY will clear this bit.
Writing a one to the bit EPSTATUSSET.BK0RDY will set this bit.
This bank is the only one used for Control pipe.
Value
Description
0
The bank number 0 is not ready: For IN the bank is not empty. For Control/OUT the bank is not yet fill
in.
1
The bank number 0 is ready: For IN the bank is filled full. For Control/OUT the bank is filled in.
Bit 4 – PFREEZE Pipe Freeze
Writing a one to the bit EPSTATUSCLR.PFREEZE will clear this bit.
Writing a one to the bit EPSTATUSSET.PFREEZE will set this bit.
This bit is also set by the hardware:
• When a STALL handshake has been received.
• After a PIPE has been enabled (rising of bit PEN.N).
• When an LPM transaction has completed whatever handshake is returned or the transaction was timed-out.
• When a pipe transfer was completed with a pipe error. See 39.19.6 PINTFLAG register.
When PFREEZE bit is set while a transaction is in progress on the USB bus, this transaction will be properly
completed. PFREEZE bit will be read as “1” only when the ongoing transaction will have been completed.
Value
Description
0
The Pipe operates in normal operation.
1
The Pipe is frozen and no additional requests will be sent to the device on this pipe address.
Bit 2 – CURBK Current Bank
Value
Description
0
The bank0 is the bank that will be used in the next single/multi USB packet.
1
The bank1 is the bank that will be used in the next single/multi USB packet.
Bit 0 – DTGL Data Toggle Sequence
Writing a one to the bit EPSTATUSCLR.DTGL will clear this bit.
Writing a one to the bit EPSTATUSSET.DTGL will set this bit.
This bit is toggled automatically by hardware after a data transaction.
This bit will reflect the data toggle in regards of the token type (IN/OUT/SETUP).
Value
Description
0
The PID of the next expected transaction will be zero: data 0.
© 2020 Microchip Technology Inc.
DS60001477C-page 886
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Value
1
Description
The PID of the next expected transaction will be one: data 1.
© 2020 Microchip Technology Inc.
DS60001477C-page 887
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.19.6 Host Pipe Interrupt Flag Register
Name:
Offset:
Reset:
Property:
Bit
7
PINTFLAG
0x107 [ + (n x 0x20)]
0x00
-
6
Access
Reset
5
STALL
R/W
0
4
TXSTP
R/W
0
3
PERR
R/W
0
2
TRFAIL
R/W
0
1
TRCPT1
R/W
0
0
TRCPT0
R/W
2
Bit 5 – STALL STALL Received Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a stall occurs and will generate an interrupt if PINTENCLR/SET.STALL is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the STALL Interrupt Flag.
Bit 4 – TXSTP Transmitted Setup Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer Complete occurs and will generate an interrupt if PINTENCLR/SET.TXSTP is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TXSTP Interrupt Flag.
Bit 3 – PERR Pipe Error Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a pipe error occurs and will generate an interrupt if PINTENCLR/SET.PERR is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the PERR Interrupt Flag.
Bit 2 – TRFAIL Transfer Fail Interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer Fail occurs and will generate an interrupt if PINTENCLR/SET.TRFAIL is one.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRFAIL Interrupt Flag.
Bits 0, 1 – TRCPT Transfer Complete x interrupt Flag
This flag is cleared by writing a one to the flag.
This flag is set when a Transfer complete occurs and will generate an interrupt if PINTENCLR/SET.TRCPT is one.
PINTFLAG.TRCPT is set for a single bank IN/OUT pipe or a double bank IN/OUT pipe when current bank is 0.
Writing a zero to this bit has no effect.
Writing a one to this bit clears the TRCPT Interrupt Flag.
© 2020 Microchip Technology Inc.
DS60001477C-page 888
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.19.7 Host Pipe Interrupt Clear Register
Name:
Offset:
Reset:
Property:
PINTENCLR
0x108 [ + (n x 0x20)]
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Pipe Interrupt Enable Set (PINTENSET) register.
This register is cleared by USB reset or when PEN[n] is zero.
Bit
7
6
Access
Reset
5
STALL
R/W
0
4
TXSTP
R/W
0
3
PERR
R/W
0
2
TRFAIL
R/W
0
1
TRCPT1
R/W
0
0
TRCPT0
R/W
2
Bit 5 – STALL Received Stall Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Received Stall interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The received Stall interrupt is disabled.
1
The received Stall interrupt is enabled and an interrupt request will be generated when the received
Stall interrupt Flag is set.
Bit 4 – TXSTP Transmitted Setup Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transmitted Setup interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transmitted Setup interrupt is disabled.
1
The Transmitted Setup interrupt is enabled and an interrupt request will be generated when the
Transmitted Setup interrupt Flag is set.
Bit 3 – PERR Pipe Error Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Pipe Error interrupt Enable bit and disable the corresponding interrupt request.
Value
Description
0
The Pipe Error interrupt is disabled.
1
The Pipe Error interrupt is enabled and an interrupt request will be generated when the Pipe Error
interrupt Flag is set.
Bit 2 – TRFAIL Transfer Fail Interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Fail interrupt Enable bit and disable the corresponding interrupt
request.
Value
Description
0
The Transfer Fail interrupt is disabled.
1
The Transfer Fail interrupt is enabled and an interrupt request will be generated when the Transfer Fail
interrupt Flag is set.
Bits 0, 1 – TRCPT Transfer Complete Bank x interrupt Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transfer Complete interrupt Enable bit x and disable the corresponding interrupt
request.
Value
Description
0
The Transfer Complete Bank x interrupt is disabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 889
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Value
1
Description
The Transfer Complete Bank x interrupt is enabled and an interrupt request will be generated when the
Transfer Complete interrupt x Flag is set.
© 2020 Microchip Technology Inc.
DS60001477C-page 890
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.19.8 Host Interrupt Pipe Set Register
Name:
Offset:
Reset:
Property:
PINTENSET
0x109 [ + (n x 0x20)]
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Pipe Interrupt Enable Set (PINTENCLR) register.
This register is cleared by USB reset or when PEN[n] is zero.
Bit
7
6
Access
Reset
5
STALL
R/W
0
4
TXSTP
R/W
0
3
PERR
R/W
0
2
TRFAIL
R/W
0
1
TRCPT1
R/W
0
0
TRCPT0
R/W
2
Bit 5 – STALL Stall Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Stall interrupt.
Value
Description
0
The Stall interrupt is disabled.
1
The Stall interrupt is enabled.
Bit 4 – TXSTP Transmitted Setup Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transmitted Setup interrupt.
Value
Description
0
The Transmitted Setup interrupt is disabled.
1
The Transmitted Setup interrupt is enabled.
Bit 3 – PERR Pipe Error Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Pipe Error interrupt.
Value
Description
0
The Pipe Error interrupt is disabled.
1
The Pipe Error interrupt is enabled.
Bit 2 – TRFAIL Transfer Fail Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Fail interrupt.
Value
Description
0
The Transfer Fail interrupt is disabled.
1
The Transfer Fail interrupt is enabled.
Bits 0, 1 – TRCPT Transfer Complete x interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Transfer Complete interrupt Enable bit x.
0.2.7 Host Registers - Pipe RAM
Value
Description
0
The Transfer Complete x interrupt is disabled.
1
The Transfer Complete x interrupt is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 891
SAM L21 Family Data Sheet
USB – Universal Serial Bus
Pipe Descriptor Structure
Data Buffers
Pn BK1
Pn BK0
Pipe descriptors
Reserved
STATUS _PIPE
Bank1
CTRL_BK
Reserved
Descriptor Pn
Reserved
PCKSIZE
ADDR
(2 x 0xn0) + 0x10
Reserved
STATUS _PIPE
Bank0
CTRL_PIPE
STATUS_BK
EXTREG
PCKSIZE
Reserved
STATUS _PIPE
Bank1
CTRL_BK
Reserved
Reserved
PCKSIZE
ADDR
Reserved
STATUS _PIPE
Bank0
CTRL_PIPE
STATUS_BK
EXTREG
PCKSIZE
ADDR
© 2020 Microchip Technology Inc.
2 x 0xn0
+0x01F
+0x01E
+0x01C
+0x01A
+0x018
+0x014
+0x010
+0x00F
+0x00E
+0x00C
+0x00A
+0x008
+0x004
+0x000
Growing Memory Addresses
ADDR
Descriptor P0
39.20
DESCADD
DS60001477C-page 892
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.21
Host Registers - Pipe RAM - Register Summary
Offset
Name
0x00
ADDR
0x04
PCKSIZE
0x08
EXTREG
0x0A
0x0B
STATUS_BK
Reserved
0x0C
CTRL_PIPE
0x0E
39.22
STATUS_PIPE
Bit Pos.
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
7:0
ADDR[7:0]
ADDR[15:8]
ADDR[23:16]
ADDR[31:24]
MULTI_PACKET_SIZE[1:0]
AUTO_ZLP
7:0
15:8
7:0
15:8
SIZE[2:0]
VARIABLE[3:0]
BYTE_COUNT[5:0]
MULTI_PACKET_SIZE[9:2]
MULTI_PACKET_SIZE[13:10]
SUBPID[3:0]
VARIABLE[10:4]
ERRORFLOW
CRCERR
PDADDR[6:0]
PERMAX[3:0]
ERCNT[2:0]
CRC16ER
TOUTER
PEPNUM[3:0]
PIDER
DAPIDER
DTGLER
Host Registers - Pipe RAM - Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
Refer to PAC - Peripheral Access Controller and 37.6.6 Synchronizationfor details.
© 2020 Microchip Technology Inc.
DS60001477C-page 893
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.22.1 Address of the Data Buffer
Name:
Offset:
Reset:
Property:
ADDR
0x00
0xxxxxxxx
NA
Original offset 0x00 & 0x10
Bit
Access
Reset
Bit
Access
Reset
Bit
31
30
29
R/W
0
R/W
0
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
15
14
13
28
27
ADDR[31:24]
R/W
R/W
0
0
26
25
24
R/W
0
R/W
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
11
10
9
8
R/W
0
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
x
20
19
ADDR[23:16]
R/W
R/W
0
0
12
ADDR[15:8]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
7
6
5
4
ADDR[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 31:0 – ADDR[31:0] Data Pointer Address Value
These bits define the data pointer address as an absolute double word address in RAM. The two least significant bits
must be zero to ensure the descriptor is 32-bit aligned.
© 2020 Microchip Technology Inc.
DS60001477C-page 894
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.22.2 Packet Size
Name:
Offset:
Reset:
Property:
PCKSIZE
0x04
0xXXXXXXX
NA
Original offset 0x04 & 0x14
Bit
Access
Reset
31
AUTO_ZLP
R/W
x
R/W
0
29
SIZE[2:0]
R/W
0
23
22
21
R/W
0
R/W
0
R/W
0
Bit
Access
Reset
Bit
Access
Reset
30
15
14
MULTI_PACKET_SIZE[1:0]
R/W
R/W
0
x
Bit
7
6
28
27
R/W
x
R/W
0
20
19
MULTI_PACKET_SIZE[9:2]
R/W
R/W
0
0
13
12
R/W
0
R/W
0
5
4
26
25
MULTI_PACKET_SIZE[13:10]
R/W
R/W
0
0
R/W
0
18
17
16
R/W
0
R/W
0
R/W
0
9
8
R/W
0
R/W
x
1
0
11
10
BYTE_COUNT[5:0]
R/W
R/W
0
0
3
24
2
Access
Reset
Bit 31 – AUTO_ZLP Automatic Zero Length Packet
This bit defines the automatic Zero Length Packet mode of the pipe.
When enabled, the USB module will manage the ZLP handshake by hardware. This bit is for OUT pipes only. When
disabled the handshake should be managed by firmware.
Value
Description
0
Automatic Zero Length Packet is disabled.
1
Automatic Zero Length Packet is enabled.
Bits 30:28 – SIZE[2:0] Pipe size
These bits contains the size of the pipe.
Theses bits are cleared upon sending a USB reset.
SIZE[2:0]
Description
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
8 Byte
16 Byte
32 Byte
64 Byte
128 Byte(1)
256 Byte(1)
512 Byte(1)
1024 Byte in HS mode(1)
1023 Byte in FS mode(1)
Note:
1. For Isochronous pipe only.
Bits 27:14 – MULTI_PACKET_SIZE[13:0] Multi Packet IN or OUT size
These bits define the 14-bit value that is used for multi-packet transfers.
© 2020 Microchip Technology Inc.
DS60001477C-page 895
SAM L21 Family Data Sheet
USB – Universal Serial Bus
For IN pipes, MULTI_PACKET_SIZE holds the total number of bytes sent. MULTI_PACKET_SIZE should be written
to zero when setting up a new transfer.
For OUT pipes, MULTI_PACKET_SIZE holds the total data size for the complete transfer. This value must be a
multiple of the maximum packet size.
Bits 13:8 – BYTE_COUNT[5:0] Byte Count
These bits define the 14-bit value that contains number of bytes sent in the last OUT or SETUP transaction for an
OUT pipe, or of the number of bytes to be received in the next IN transaction for an input pipe.
© 2020 Microchip Technology Inc.
DS60001477C-page 896
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.22.3 Extended Register
Name:
Offset:
Reset:
Property:
Bit
EXTREG
0x08
0xXXXXXXX
NA
15
Access
Reset
Bit
Access
Reset
7
R/W
0
14
13
12
R/W
0
R/W
0
6
5
VARIABLE[3:0]
R/W
R/W
0
0
10
9
8
R/W
0
11
VARIABLE[10:4]
R/W
0
R/W
0
R/W
0
R/W
0
4
3
2
R/W
x
R/W
0
1
SUBPID[3:0]
R/W
R/W
0
0
0
R/W
x
Bits 14:4 – VARIABLE[10:0] Variable field send with extended token
These bits define the VARIABLE field sent with extended token. See “Section 2.1.1 Protocol Extension Token in the
reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum.”
To support the USB2.0 Link Power Management addition the VARIABLE field should be set as described below.
VARIABLE
Description
VARIABLE[3:0]
VARIABLE[7:4]
VARIABLE[8]
VARIABLE[10:9]
bLinkState(1)
BESL (See LPM ECN)(2)
bRemoteWake(1)
Reserved
Note:
1. For a definition of LPM Token bRemoteWake and bLinkState fields, refer to "Table 2-3 in the reference
document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum".
2. For a definition of LPM Token BESL field, refer to "Table 2-3 in the reference document ENGINEERING
CHANGE NOTICE, USB 2.0 Link Power Management Addendum" and "Table X-X1 in Errata for ECN USB 2.0
Link Power Management.
Bits 3:0 – SUBPID[3:0] SUBPID field send with extended token
These bits define the SUBPID field sent with extended token. See “Section 2.1.1 Protocol Extension Token in the
reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management Addendum”.
To support the USB2.0 Link Power Management addition the SUBPID field should be set as described in “Table 2.2
SubPID Types in the reference document ENGINEERING CHANGE NOTICE, USB 2.0 Link Power Management
Addendum”.
© 2020 Microchip Technology Inc.
DS60001477C-page 897
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.22.4 Host Status Bank
Name:
Offset:
Reset:
Property:
STATUS_BK
0x0A
0xXXXXXXX
NA
Original offset 0x0A & 0x1A
Bit
7
6
5
4
3
2
Access
Reset
1
ERRORFLOW
R/W
x
0
CRCERR
R/W
x
Bit 1 – ERRORFLOW Error Flow Status
This bit defines the Error Flow Status.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For IN transfer, a NAK handshake has been received. For OUT transfer, a NAK handshake has been received. For
Isochronous IN transfer, an overrun condition has occurred. For Isochronous OUT transfer, an underflow condition
has occurred.
Value
Description
0
No Error Flow detected.
1
A Error Flow has been detected.
Bit 0 – CRCERR CRC Error
This bit defines the CRC Error Status.
This bit is set when a CRC error has been detected in an isochronous IN endpoint bank.
Value
Description
0
No CRC Error.
1
CRC Error detected.
© 2020 Microchip Technology Inc.
DS60001477C-page 898
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.22.5 Host Control Pipe
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
Access
Reset
15
R/W
0
7
CTRL_PIPE
0x0C
0xXXXX
PAC Write-Protection, Write-Synchronized, Read-Synchronized
14
13
PERMAX[3:0]
R/W
R/W
0
0
12
11
R/W
x
R/W
0
3
PDADDR[6:0]
R/W
0
6
5
4
R/W
0
R/W
0
R/W
0
10
9
PEPNUM[3:0]
R/W
R/W
0
0
8
R/W
x
2
1
0
R/W
0
R/W
0
R/W
x
Bits 15:12 – PERMAX[3:0] Pipe Error Max Number
These bits define the maximum number of error for this Pipe before freezing the pipe automatically.
Bits 11:8 – PEPNUM[3:0] Pipe EndPoint Number
These bits define the number of endpoint for this Pipe.
Bits 6:0 – PDADDR[6:0] Pipe Device Address
These bits define the Device Address for this pipe.
© 2020 Microchip Technology Inc.
DS60001477C-page 899
SAM L21 Family Data Sheet
USB – Universal Serial Bus
39.22.6 Host Status Pipe
Name:
Offset:
Reset:
Property:
STATUS_PIPE
0x0E
0xXXXXXXX
PAC Write-Protection, Write-Synchronized, Read-Synchronized
Original offset 0x0E & 0x1E
Bit
15
14
13
12
11
10
9
8
7
6
ERCNT[2:0]
R/W
0
5
4
CRC16ER
R/W
x
3
TOUTER
R/W
x
2
PIDER
R/W
x
1
DAPIDER
R/W
x
0
DTGLER
R/W
x
Access
Reset
Bit
Access
Reset
R/W
0
R/W
x
Bits 7:5 – ERCNT[2:0] Pipe Error Counter
These bits define the number of errors detected on the pipe.
Bit 4 – CRC16ER CRC16 ERROR
This bit defines the CRC16 Error Status.
This bit is set when a CRC 16 error has been detected during a IN transactions.
Value
Description
0
No CRC 16 Error detected.
1
A CRC 16 error has been detected.
Bit 3 – TOUTER TIME OUT ERROR
This bit defines the Time Out Error Status.
This bit is set when a Time Out error has been detected during a USB transaction.
Value
Description
0
No Time Out Error detected.
1
A Time Out error has been detected.
Bit 2 – PIDER PID ERROR
This bit defines the PID Error Status.
This bit is set when a PID error has been detected during a USB transaction.
Value
Description
0
No PID Error detected.
1
A PID error has been detected.
Bit 1 – DAPIDER Data PID ERROR
This bit defines the PID Error Status.
This bit is set when a Data PID error has been detected during a USB transaction.
Value
Description
0
No Data PID Error detected.
1
A Data PID error has been detected.
Bit 0 – DTGLER Data Toggle Error
This bit defines the Data Toggle Error Status.
This bit is set when a Data Toggle Error has been detected.
Value
Description
0
No Data Toggle Error.
1
Data Toggle Error detected.
© 2020 Microchip Technology Inc.
DS60001477C-page 900
SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
40.
40.1
CCL – Configurable Custom Logic
Overview
The Configurable Custom Logic (CCL) is a programmable logic peripheral which can be connected to the device
pins, to events, or to other internal peripherals. This allows the user to eliminate logic gates for simple glue logic
functions on the PCB.
Each LookUp Table (LUT) consists of three inputs, a truth table, and as options synchronizer, filter and edge detector.
Each LUT can generate an output as a user programmable logic expression with three inputs. Inputs can be
individually masked.
The output can be combinatorially generated from the inputs, and can be filtered to remove spikes. Optional
sequential logic can be used. The inputs of the sequential module are individually controlled by two independent,
adjacent LUT (LUT0/LUT1, LUT2/LUT3 etc.) outputs, enabling complex waveform generation.
40.2
Features
•
•
•
•
•
•
•
Glue logic for general purpose PCB design
Up to 4 programmable LookUp Tables (LUTs)
Combinatorial logic functions:
AND, NAND, OR, NOR, XOR, XNOR, NOT
Sequential logic functions:
Gated D Flip-Flop, JK Flip-Flop, gated D Latch, RS Latch
Flexible LUT inputs selection:
– I/Os
– Events
– Internal peripherals
– Subsequent LUT output
Output can be connected to the I/O pins or the Event System
Optional synchronizer, filter, or edge detector available on each LUT output
© 2020 Microchip Technology Inc.
DS60001477C-page 901
SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
40.3
Block Diagram
Figure 40-1. Configurable Custom Logic
LUT0
LUTCTRL0
(INSEL)
Internal
LUTCTRL0
(FILTSEL)
Events
LUTCTRL0
(EDGESEL)
SEQCTRL
(SEQSEL0)
CTRL
(ENABLE)
Event System
I/O
Truth Table
8
Peripherals
Filter / Synch
Edge Detector
CLR
CLR
OUT0
Sequential
Peripherals
I/O
CLR
LUTCTRL0
(ENABLE)
CLK_CCL_APB
GCLK_CCL
D Q
LUT1
LUTCTRL1
(INSEL)
Internal
LUTCTRL1
(FILTSEL)
Events
CTRL
(ENABLE)
Event System
I/O
Truth Table
8
Peripherals
CLK_CCL_APB
GCLK_CCL
LUTCTRL1
(EDGESEL)
LUTCTRL1
(ENABLE)
Filter / Synch
Edge Detector
CLR
CLR
OUT1
Peripherals
I/O
D Q
UNIT 0
...
.
.
Event System
40.4
UNIT x
OUT2x-1
Peripherals
I/O
Signal Description
Pin Name
Type
Description
OUT[n:0]
Digital output
Output from lookup table
IN[3n+2:0]
Digital input
Input to lookup table
1.
n is the number of CCL groups.
Refer to I/O Multiplexing and Considerations for details on the pin mapping for this peripheral. One signal can be
mapped on several pins.
40.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
40.5.1
I/O Lines
Using the CCL I/O lines requires the I/O pins to be configured. Refer to PORT - I/O Pin Controller for details.
40.5.2
Power Management
This peripheral can continue to operate in any sleep mode where its source clock is running. Events connected to the
event system can trigger other operations in the system without exiting sleep modes.
40.5.3
Clocks
The CCL bus clock (CLK_CCL_APB) can be enabled and disabled in the power manager, and the default state of
CLK_CCL_APB can be found in the Peripheral Clock Masking.
A generic clock (GCLK_CCL) is optionally required to clock the CCL. This clock must be configured and enabled in
the Generic Clock Controller (GCLK) before using input events, filter, edge detection or sequential logic. GCLK_CCL
is required when input events, a filter, an edge detector, or a sequential sub-module is enabled. Refer to 17. GCLK Generic Clock Controller for details.
© 2020 Microchip Technology Inc.
DS60001477C-page 902
SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
This generic clock is asynchronous to the user interface clock (CLK_CCL_APB).
40.5.4
DMA
Not applicable.
40.5.5
Interrupts
Not applicable.
40.5.6
Events
The events are connected to the Event System. Refer to EVSYS – Event System for details on how to configure the
Event System.
40.5.7
Debug Operation
When the CPU is halted in debug mode the CCL continues normal operation. If the CCL is configured in a way that
requires it to be periodically serviced by the CPU, improper operation or data loss may result during debugging.
40.5.8
Register Access Protection
All registers with write-access can be write-protected optionally by the PAC - Peripheral Access Controller.
Optional write-protection by the PAC - Peripheral Access Controller is denoted by the "PAC Write-Protection" property
in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
40.5.9
Analog Connections
Not applicable.
40.6
Functional Description
40.6.1
Principle of Operation
Configurable Custom Logic (CCL) is a programmable logic block that can use the device port pins, internal
peripherals, and the internal Event System as both input and output channels. The CCL can serve as glue logic
between the device and external devices. The CCL can eliminate the need for external logic component and can also
help the designer overcome challenging real-time constrains by combining core independent peripherals in clever
ways to handle the most time critical parts of the application independent of the CPU.
40.6.2
Operation
40.6.2.1 Initialization
The following bits are enable-protected, meaning that they can only be written when the corresponding even LUT is
disabled (LUTCTRLx.ENABLE=0):
•
Sequential Selection bits in the Sequential Control x (SEQCTRLx.SEQSEL) register
The following registers are enable-protected, meaning that they can only be written when the corresponding LUT is
disabled (LUTCTRLx.ENABLE=0):
•
LUT Control x (LUTCTRLx) register, except the ENABLE bit
Enable-protected bits in the LUTCTRLx registers can be written at the same time as LUTCTRLx.ENABLE is written to
'1', but not at the same time as LUTCTRLx.ENABLE is written to '0'.
Enable-protection is denoted by the Enable-Protected property in the register description.
40.6.2.2 Enabling, Disabling, and Resetting
The CCL is enabled by writing a '1' to the Enable bit in the Control register (CTRL.ENABLE). The CCL is disabled by
writing a '0' to CTRL.ENABLE.
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
Each LUT is enabled by writing a '1' to the Enable bit in the LUT Control x register (LUTCTRLx.ENABLE). Each LUT
is disabled by writing a '0' to LUTCTRLx.ENABLE.
The CCL is reset by writing a '1' to the Software Reset bit in the Control register (CTRL.SWRST). All registers in the
CCL will be reset to their initial state, and the CCL will be disabled. Refer to 40.8.1 CTRL for details.
40.6.2.3 Lookup Table Logic
The lookup table in each LUT unit can generate any logic expression OUT as a function of three inputs (IN[2:0]), as
shown in Figure 40-2. One or more inputs can be masked. The truth table for the expression is defined by TRUTH
bits in LUT Control x register (LUTCTRLx.TRUTH).
Figure 40-2. Truth Table Output Value Selection
LUT
TRUTH[0]
TRUTH[1]
TRUTH[2]
TRUTH[3]
TRUTH[4]
TRUTH[5]
TRUTH[6]
TRUTH[7]
OUT
LUTCTRL
(ENABLE)
IN[2:0]
Table 40-1. Truth Table of LUT
IN[2]
IN[1]
IN[0]
OUT
0
0
0
TRUTH[0]
0
0
1
TRUTH[1]
0
1
0
TRUTH[2]
0
1
1
TRUTH[3]
1
0
0
TRUTH[4]
1
0
1
TRUTH[5]
1
1
0
TRUTH[6]
1
1
1
TRUTH[7]
40.6.2.4 Truth Table Inputs Selection
Input Overview
The inputs can be individually:
•
•
•
•
Masked
Driven by peripherals:
– Analog comparator output (AC)
– Timer/Counters waveform outputs (TC)
– Serial Communication output transmit interface (SERCOM)
Driven by internal events from Event System
Driven by other CCL sub-modules
The Input Selection for each input y of LUT x is configured by writing the Input y Source Selection bit in the LUT x
Control register (LUTCTRLx.INSELy).
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
Masked Inputs (MASK)
When a LUT input is masked (LUTCTRLx.INSELy=MASK), the corresponding TRUTH input (IN) is internally tied to
zero, as shown in this figure:
Figure 40-3. Masked Input Selection
Internal Feedback Inputs (FEEDBACK)
When selected (LUTCTRLx.INSELy=FEEDBACK), the Sequential (SEQ) output is used as input for the
corresponding LUT.
The output from an internal sequential sub-module can be used as input source for the LUT, see figure below for an
example for LUT0 and LUT1. The sequential selection for each LUT follows the formula:
IN 2N � = SEQ �
IN 2N+1 � = SEQ �
With N representing the sequencer number and i=0,1,2 representing the LUT input index.
For details, refer to 40.6.2.7 Sequential Logic.
Figure 40-4. Feedback Input Selection
Linked LUT (LINK)
When selected (LUTCTRLx.INSELy=LINK), the subsequent LUT output is used as the LUT input (e.g., LUT2 is the
input for LUT1), as shown in this figure:
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
Figure 40-5. Linked LUT Input Selection
LUT0
SEQ 0
CTRL
(ENABLE)
LUT1
LUT2
SEQ 1
CTRL
(ENABLE)
LUT3
LUT(2n – 2)
SEQ n
CTRL
(ENABLE)
LUT(2n-1)
Internal Events Inputs Selection (EVENT)
Asynchronous events from the Event System can be used as input selection, as shown in Figure 40-6. For each LUT,
one event input line is available and can be selected on each LUT input. Before enabling the event selection by
writing LUTCTRLx.INSELy=EVENT, the Event System must be configured first.
By default CCL includes an edge detector. When the event is received, an internal strobe is generated when a rising
edge is detected. The pulse duration is one GCLK_CCL clock cycle. Writing the LUTCTRLx.INSELy=ASYNCEVENT
will disable the edge detector. In this case, it is possible to combine an asynchronous event input with any other input
source. This is typically useful with event levels inputs (external IO pin events, as example). The following steps
ensure proper operation:
1.
2.
3.
4.
5.
Enable the GCLK_CCL clock.
Configure the Event System to route the event asynchronously.
Select the event input type (LUTCTRLx.INSEL).
If a strobe must be generated on the event input falling edge, write a '1' to the Inverted Event Input Enable bit
in LUT Control register (LUTCTRLx.INVEI) .
Enable the event input by writing the Event Input Enable bit in LUT Control register (LUTCTRLx.LUTEI) to '1'.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
Figure 40-6. Event Input Selection
I/O Pin Inputs (IO)
When the IO pin is selected as LUT input (LUTCTRLx.INSELy=IO), the corresponding LUT input will be connected to
the pin, as shown in the figure below.
Figure 40-7. I/O Pin Input Selection
Analog Comparator Inputs (AC)
The AC outputs can be used as input source for the LUT (LUTCTRLx.INSELy=AC).
The analog comparator outputs are distributed following the formula:
IN[N][i]=AC[N % ComparatorOutput_Number]
With N representing the LUT number and i=[0,1,2] representing the LUT input index.
Before selecting the comparator output, the AC must be configured first.
The output of comparator 0 is available on even LUTs ("LUT(2x)": LUT0, LUT2) and the comparator 1 output is
available on odd LUTs ("LUT(2x+1)": LUT1, LUT3), as shown in the figure below.
Figure 40-8. AC Input Selection
Timer/Counter Inputs (TC)
The TC waveform output WO[0] can be used as input source for the LUT (LUTCTRLx.INSELy=TC). Only consecutive
instances of the TC, i.e. TCx and the subsequent TC(x+1), are available as default and alternative TC selections
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
(e.g., TC0 and TC1 are sources for LUT0, TC1 and TC2 are sources for LUT1, etc). See the figure below for an
example for LUT0. More general, the Timer/Counter selection for each LUT follows the formula:
IN � � = ��������� � % TC_Instance_Number
IN � � = ������������� � + 1 % TC_Instance_Number
Where N represents the LUT number and i represents the LUT input index (i=0,1,2).
For devices with more than four TC instances, it is also possible to enable a second alternative option
(LUTCTRLx.INSEL=ALT2TC). This option is intended to relax the alternative pin function or PCB design constraints
when the default or the alternative TC instances are used for other purposes. When enabled, the Timer/Counter
selection for each LUT follows the formula:
IN � � = ������������������� � + 4 % TC_Instance_Number
Note that for not implemented TC_Instance_Number, the corresponding input is tied to ground.
Before selecting the waveform outputs, the TC must be configured first.
Figure 40-9. TC Input Selection
TC0
(default)
WO[0]
TC1
(alternative)
WO[0]
TC4
(second alternative)
WO[0]
Timer/Counter for Control Application Inputs (TCC)
The TCC waveform outputs can be used as input source for the LUT. Only WO[2:0] outputs can be selected and
routed to the respective LUT input (i.e., IN0 is connected to WO0, IN1 to WO1, and IN2 to WO2), as shown in the
figure below.
Note:
The TCC selection for each LUT follows the formula:
IN � � = ��� � % ��C_Instance_Number
Where N represents the LUT number.
Before selecting the waveform outputs, the TCC must be configured first.
Figure 40-10. TCC Input Selection
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
Serial Communication Output Transmit Inputs (SERCOM)
The serial engine transmitter output from Serial Communication Interface (SERCOM TX, TXd for USART, MOSI for
SPI) can be used as input source for the LUT. The figure below shows an example for LUT0 and LUT1. The
SERCOM selection for each LUT follows the formula:
IN � � = ������[� % SERCOM_Instance_Number
With N representing the LUT number and i=0,1,2 representing the LUT input index.
Before selecting the SERCOM as input source, the SERCOM must be configured first: the SERCOM TX signal must
be output on SERCOMn/pad[0], which serves as input pad to the CCL.
Figure 40-11. SERCOM Input Selection
40.6.2.5 Filter
By default, the LUT output is a combinatorial function of the LUT inputs. This may cause some short glitches when
the inputs change value. These glitches can be removed by clocking through filters, if demanded by application
needs.
The Filter Selection bits in LUT Control register (LUTCTRLx.FILTSEL) define the synchronizer or digital filter options.
When a filter is enabled, the OUT output will be delayed by two to five GCLK cycles. One APB clock after the
corresponding LUT is disabled, all internal filter logic is cleared.
Note: Events used as LUT input will also be filtered, if the filter is enabled.
Figure 40-12. Filter
FILTSEL
Input
OUT
Q
D
R
Q
D
R
Q
D
R
D
G
Q
R
GCLK_CCL
CLR
40.6.2.6 Edge Detector
The edge detector can be used to generate a pulse when detecting a rising edge on its input. To detect a falling edge,
the TRUTH table should be programmed to provide the opposite levels.
The edge detector is enabled by writing '1' to the Edge Selection bit in LUT Control register (LUTCTRLx.EDGESEL).
In order to avoid unpredictable behavior, a valid filter option must be enabled as well.
Edge detection is disabled by writing a '0' to LUTCTRLx.EDGESEL. After disabling a LUT, the corresponding internal
Edge Detector logic is cleared one APB clock cycle later.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
Figure 40-13. Edge Detector
40.6.2.7 Sequential Logic
Each LUT pair can be connected to internal sequential logic: D flip flop, JK flip flop, gated D-latch or RS-latch can be
selected by writing the corresponding Sequential Selection bits in Sequential Control x register
(SEQCTRLx.SEQSEL). Before using sequential logic, the GCLK clock and optionally each LUT filter or edge
detector, must be enabled.
Gated D Flip-Flop (DFF)
When the DFF is selected, the D-input is driven by the even LUT output (LUT2x), and the G-input is driven by the odd
LUT output (LUT2x+1), as shown in Figure 40-14.
Figure 40-14. D Flip Flop
When the even LUT is disabled (LUTCTRL2x.ENABLE=0), the flip-flop is asynchronously cleared. The reset
command (R) is kept enabled for one APB clock cycle. In all other cases, the flip-flop output (OUT) is refreshed on
rising edge of the GCLK_CCL, as shown in Table 40-2.
Table 40-2. DFF Characteristics
R
G
D
OUT
1
X
X
Clear
0
1
1
Set
0
Clear
X
Hold state (no change)
0
JK Flip-Flop (JK)
When this configuration is selected, the J-input is driven by the even LUT output (LUT2x), and the K-input is driven by
the odd LUT output (LUT2x+1), as shown in Figure 40-15.
Figure 40-15. JK Flip Flop
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
When the even LUT is disabled (LUTCTRL2x.ENABLE=0), the flip-flop is asynchronously cleared. The reset
command (R) is kept enabled for one APB clock cycle. In all other cases, the flip-flop output (OUT) is refreshed on
rising edge of the GCLK_CCL, as shown in Table 40-3.
Table 40-3. JK Characteristics
R
J
K
OUT
1
X
X
Clear
0
0
0
Hold state (no change)
0
0
1
Clear
0
1
0
Set
0
1
1
Toggle
Gated D-Latch (DLATCH)
When the DLATCH is selected, the D-input is driven by the even LUT output (LUT2x), and the G-input is driven by
the odd LUT output (LUT2x+1), as shown in Figure 40-14.
Figure 40-16. D-Latch
even LUT
D
odd LUT
G
Q
OUT
When the even LUT is disabled (LUTCTRL2x.ENABLE=0), the latch output will be cleared. The G-input is forced
enabled for one more APB clock cycle, and the D-input to zero. In all other cases, the latch output (OUT) is refreshed
as shown in Table 40-4.
Table 40-4. D-Latch Characteristics
G
D
OUT
0
X
Hold state (no change)
1
0
Clear
1
1
Set
RS Latch (RS)
When this configuration is selected, the S-input is driven by the even LUT output (LUT2x), and the R-input is driven
by the odd LUT output (LUT2x+1), as shown in Figure 40-17.
Figure 40-17. RS-Latch
even LUT
S
odd LUT
R
Q
OUT
When the even LUT is disabled (LUTCTRL2x.ENABLE=0), the latch output will be cleared. The R-input is forced
enabled for one more APB clock cycle and S-input to zero. In all other cases, the latch output (OUT) is refreshed as
shown in Table 40-5.
Table 40-5. RS-latch Characteristics
S
R
OUT
0
0
Hold state (no change)
0
1
Clear
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
...........continued
40.6.3
S
R
OUT
1
0
Set
1
1
Forbidden state
Events
The CCL can generate the following output events:
•
LUTOUTx: Lookup Table Output Value
Writing a '1' to the LUT Control Event Output Enable bit (LUTCTRL.LUTEO) enables the corresponding output event.
Writing a '0' to this bit disables the corresponding output event. Refer to EVSYS – Event System for details on
configuration.
The CCL can take the following actions on an input event:
•
INx: The event is used as input for the TRUTH table. For further details refer to 40.5.6 Events.
Writing a '1' to the LUT Control Event Input Enable bit (LUTCTRL.LUTEI) enables the corresponding action on input
event. Writing a '0' to this bit disables the corresponding action on input event. Refer to EVSYS – Event System for
details on configuration.
40.6.4
Sleep Mode Operation
When using the GCLK_CCL internal clocking, writing the Run In Standby bit in the Control register
(CTRL.RUNSTDBY) to '1' will allow GCLK_CCL to be enabled in all sleep modes.
If CTRL.RUNSTDBY=0, the GCLK_CCL will be disabled. If the Filter, Edge Detector or Sequential logic are enabled,
the LUT output will be forced to zero in STANDBY mode. In all other cases, the TRUTH table decoder will continue
operation and the LUT output will be refreshed accordingly.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
40.7
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
...
0x03
0x04
0x05
0x06
...
0x07
CTRL
7:0
0x08
0x0C
0x10
0x14
40.8
RUNSTDBY
ENABLE
SWRST
Reserved
SEQCTRL0
SEQCTRL1
7:0
7:0
SEQSEL[3:0]
SEQSEL[3:0]
Reserved
LUTCTRL0
LUTCTRL1
LUTCTRL2
LUTCTRL3
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
7:0
15:8
23:16
31:24
EDGESEL
EDGESEL
EDGESEL
EDGESEL
FILTSEL[1:0]
INSEL1[3:0]
LUTEO
LUTEI
INVEI
TRUTH[7:0]
FILTSEL[1:0]
INSEL1[3:0]
LUTEO
LUTEI
INVEI
TRUTH[7:0]
FILTSEL[1:0]
INSEL1[3:0]
LUTEO
LUTEI
INVEI
TRUTH[7:0]
FILTSEL[1:0]
INSEL1[3:0]
LUTEO
LUTEI
INVEI
TRUTH[7:0]
ENABLE
INSEL0[3:0]
INSEL2[3:0]
ENABLE
INSEL0[3:0]
INSEL2[3:0]
ENABLE
INSEL0[3:0]
INSEL2[3:0]
ENABLE
INSEL0[3:0]
INSEL2[3:0]
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
Refer to PAC - Peripheral Access Controller and 37.6.6 Synchronizationfor details.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
40.8.1
Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
CTRL
0x00
0x00
PAC Write-Protection
6
RUNSTDBY
R/W
0
5
4
3
2
1
ENABLE
R/W
0
0
SWRST
W
0
Bit 6 – RUNSTDBY Run in Standby
This bit indicates if the GCLK_CCL clock must be kept running in standby mode. The setting is ignored for
configurations where the generic clock is not required. For details refer to 40.6.4 Sleep Mode Operation.
Value
Description
0
Generic clock is not required in standby sleep mode.
1
Generic clock is required in standby sleep mode.
Bit 1 – ENABLE Enable
Value
Description
0
The peripheral is disabled.
1
The peripheral is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the CCL to their initial state.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
40.8.2
Sequential Control x
Name:
Offset:
Reset:
Property:
SEQCTRL
0x04 + n*0x01 [n=0..1]
0x00
PAC Write-Protection, Enable-Protected
Note: SEQCTRLx register is Enable-protected when LUTCTRLx.ENABLE = 1.
Bit
7
6
Access
Reset
5
4
3
R/W
0
2
1
SEQSEL[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 3:0 – SEQSEL[3:0] Sequential Selection
These bits select the sequential configuration:
Sequential Selection
Value
Name
Description
0x0
DISABLE
Sequential logic is disabled
0x1
DFF
D flip flop
0x2
JK
JK flip flop
0x3
LATCH
D latch
0x4
RS
RS latch
0x5 Reserved
0xF
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DS60001477C-page 915
SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
40.8.3
LUT Control x
Name:
Offset:
Reset:
Property:
LUTCTRL
0x08 + n*0x04 [n=0..3]
0x00000000
PAC Write-Protection, Enable-Protected
Note: The LUTCTRLx register is enable-protected when CCL.LUTCTRLx.ENABLE = 1.
Bit
31
30
29
28
27
26
25
24
R/W
0
R/W
0
TRUTH[7:0]
Access
Reset
Bit
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
23
22
LUTEO
R/W
0
21
LUTEI
R/W
0
20
INVEI
R/W
0
19
18
R/W
0
12
11
R/W
0
R/W
0
Access
Reset
Bit
Access
Reset
Bit
Access
Reset
15
R/W
0
7
EDGESEL
R/W
0
14
13
INSEL1[3:0]
R/W
R/W
0
0
6
5
4
FILTSEL[1:0]
R/W
R/W
0
0
3
17
INSEL2[3:0]
R/W
R/W
0
0
10
9
INSEL0[3:0]
R/W
R/W
0
0
2
1
ENABLE
R/W
0
16
R/W
0
8
R/W
0
0
Bits 31:24 – TRUTH[7:0] Truth Table
These bits define the value of truth logic as a function of inputs IN[2:0].
Bit 22 – LUTEO LUT Event Output Enable
Value
Description
0
LUT event output is disabled.
1
LUT event output is enabled.
Bit 21 – LUTEI LUT Event Input Enable
Value
Description
0
LUT incoming event is disabled.
1
LUT incoming event is enabled.
Bit 20 – INVEI Inverted Event Input Enable
Value
Description
0
Incoming event is not inverted.
1
Incoming event is inverted.
Bits 8:11, 12:15, 16:19 – INSELx LUT Input x Source Selection
These bits select the LUT input x source:
Value
Name
Description
0x0
MASK
Masked input
0x1
FEEDBACK
Feedback input source
0x2
LINK
Linked LUT input source
0x3
EVENT
Event input source
0x4
IO
I/O pin input source
0x5
AC
AC input source: CMP[0] (LUT0) / CMP[1] (LUT1)
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
CCL – Configurable Custom Logic
Value
0x6
0x7
0x8
0x9
0xA 0xF
Name
TC
ALTTC
Reserved
SERCOM
-
Description
TC input source: TC0 (LUT0) / TC1 (LUT1)
Alternative TC input source: TC1 (LUT0) / TC2 (LUT1)
Reserved
SERCOM input source: SERCOM0 (LUT0) / SERCOM1 (LUT1)
Reserved
Bit 7 – EDGESEL Edge Selection
Value
Description
0
Edge detector is disabled.
1
Edge detector is enabled.
Bits 5:4 – FILTSEL[1:0] Filter Selection
These bits select the LUT output filter options:
Filter Selection
Value
Name
0x0
DISABLE
0x1
SYNCH
0x2
FILTER
0x3
-
Description
Filter disabled
Synchronizer enabled
Filter enabled
Reserved
Bit 1 – ENABLE LUT Enable
Value
Description
0
The LUT is disabled.
1
The LUT is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 917
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
41.
Operational Amplifier Controller (OPAMP)
41.1
Overview
The Operational Amplifier (OPAMP) Controller configures and controls three low-power, general purpose operational
amplifiers offering a high degree of flexibility and rail-to-rail inputs.
Most common inverting or non-inverting programmable gain and hysteresis configurations can be selected by
software, no external components are required for these configurations.
The OPAMPs can be cascaded for both Standalone mode and built-in configurations.
Each OPAMP can be used as a standalone amplifier. External pins are available for filter configurations or other
applications. A reference can be generated from the DAC to be used as selectable reference for inverting PGA
(programmable gain amplifier) or instrumentation amplifier. Each OPAMP can be used as buffer or PGA for the ADC
or an AC. The OPAMP offset voltage can be compensated when it is used in combination with the ADC.
Four modes are available to select the trade-off between speed and power consumption to best fit the application
requirements and optimize the power consumption.
41.2
Features
•
•
•
•
•
•
•
•
Three individually configurable low-power OPAMPs
Rail-to-rail inputs
Configurable resistor ladders for internal feedback
Selectable configurations
– Standalone OPAMP with flexible inputs
– Unity gain amplifier
– Non-inverting or inverting Programmable Gain Amplifier (PGA)
– Cascaded PGAs
– Instrumentation amplifier
– Comparator with programmable hysteresis
OPAMP output:
– On I/O pins
– As input for AC or ADC
Flexible input selection:
– I/O pins
– DAC
– Ground
Low-power options:
– Selectable voltage doubler and propagation delay versus current consumption
– On demand start-up for ADC and AC operations
Offset/Gain measurement for calibration when used with the ADC
© 2020 Microchip Technology Inc.
DS60001477C-page 918
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
41.3
Block Diagram
Figure 41-1. OPAMP Block Diagram
+
V2
Vs
V1
Vdiff = Vs - V2 = (V2-V1)R2/R1
OPAMP1
-
+
OPAMP0
R1
R2
-
41.4
Signal Description
Signal
Description
Type
OA0POS
OPAMP0 positive input
Analog input
OA0NEG
OPAMP0 negative input
Analog input
OA1POS
OPAMP1 positive input
Analog input
OA1NEG
OPAMP1 negative input
Analog input
OA2POS
OPAMP2 positive input
Analog input
OA2NEG
OPAMP2 negative input
Analog input
OA0OUT
OPAMP0 output
Analog output
OA1OUT
OPAMP1 output
Analog output
OA2OUT
OPAMP2 output
Analog output
One signal can be mapped on several pins.
Important: When an analog peripheral is enabled, the analog output of the peripheral will interfere with
the alternative functions of the output pads. This is also true even when the peripheral is used for internal
purposes. Analog inputs do not interfere with alternative pad functions.
41.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
© 2020 Microchip Technology Inc.
DS60001477C-page 919
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
41.5.1
I/O Lines
Using the OPAMP I/O lines requires the I/O pins to be configured. Refer to the PORT - I/O Pin Controller chapter for
details.
41.5.2
Power Management
The OPAMP can operate in idle and standby sleep mode, according to the settings of the Run in Standby and On
Demand bits in the OPAMP Control x registers (OPAMPCTRLx.RUNSTDBY and OPAMPCTRLx.ONDEMAND), as
well as the Enable bit in the Control A register (CTRLA.ENABLE). Refer to PM – Power Manager for details on the
different sleep modes.
41.5.3
Clocks
The OPAMP bus clock (CLK_OPAMP_APB) can be enabled and disabled in the Power Manager, and the default
state of CLK_OPAMP_APB can be found in the 18.6.2.6 Peripheral Clock Masking.
A clock (CLK_ULP32K) is required by the voltage doubler for low voltage operation (VCC < 2.5V). The CLK_ULP32K
is a 32KHz clock which is provided by the OSCULP32K oscillator in the OSC32KCTRL module.
41.5.4
DMA
Not applicable.
41.5.5
Interrupts
Not applicable.
41.5.6
Events
Not applicable.
41.5.7
Debug Operation
When the CPU is halted in debug mode the OPAMP continues normal operation. If the OPAMP is configured in a way
that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss
may result during debugging.
41.5.8
Register Access Protection
All registers with write-access can be write-protected optionally by the Peripheral Access Controller (PAC).
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
41.5.9
Analog Connections
Each OPAMP has two I/O pins that can be used as analog inputs. These pins must be configured for analog
operation before using them as OPAMP inputs.
If the DAC is to be used as OPAMP input, the DAC must be configured and enabled first.
Each OPAMP has one I/O pin that can be used as analog output. This pin must be configured for analog operation
before using it as OPAMP output.
The analog signals of AC, ADC, DAC and OPAMP can be interconnected. The AC and ADC peripheral can request
the OPAMP using an analog ONDEMAND functionality.
See Analog Connections of Peripherals for details.
41.5.10 Other dependencies
Not applicable.
© 2020 Microchip Technology Inc.
DS60001477C-page 920
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
41.6
41.6.1
Functional Description
Principle of Operation
Each OPAMP has one positive and one negative input. Each input may be chosen from either a selection of analog
input pins, or internal inputs such as the DAC, the resistor ladder, and the ground and output of another OPAMP.
Each OPAMP can be configured with built-in feedback to support various functions with programmable or unity gain.
I/O pins are externally accessible so that the operational amplifier can be configured with external feedback.
All OPAMPs can be cascaded to support circuits such as differential amplifiers.
41.6.2
Basic Operation
Each operational amplifier can be configured in different modes, selected by the OPAMP Control x register
(OPAMPCTRLx):
•
•
Standalone operational amplifier
Operational amplifier with built-in feedback
After being enabled, a start-up delay is added before the output of the operational amplifier is available. This start-up
time is measured internally to account for environmental changes such as temperature or voltage supply level.
When the OPAMP is ready, the respective Ready x bit in the Status register is set (STATUS.READYx=1).
If the supply voltage is below 2.5V, the start-up time is also dependent on the voltage doubler. If the supply voltage is
always above 2.5V, the voltage doubler can be disabled by setting the Low-Power Mux bit in the Control A Register
(CTRLA.LPMUX).
41.6.2.1 Initialization
The OPAMP must be configured with the desired properties and inputs before it is enabled.
The asynchronous clocks CLK_OPAMP must be configured in the OSC32KCTRL module before enabling individual
OPAMPs. See OSC32KCTRL – 32KHz Oscillators Controller for further details.
41.6.2.2 Enabling, Disabling, and Resetting
The OPAMP is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The OPAMP is
disabled by writing a '0' to CTRLA.ENABLE.
Each OPAMP sub-module is enabled by writing a '1' to the Enable bit in the OPAMP Control x register
(OPAMPCTRLx.ENABLE). Each OPAMP sub-module is disabled by writing a '0'to OPAMPCTRLx.ENABLE.
The OPAMP module is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All
registers in the OPAMP will be reset to their initial state, and the OPAMP will be disabled. Refer to 41.8.1 CTRLA for
details.
41.6.3
DMA Operation
Not applicable.
41.6.4
Interrupts
Not applicable.
41.6.5
Events
Not applicable.
41.6.6
Sleep Mode Operation
The OPAMPs can also be used during sleep modes. The 32KHz clock source used by the voltage doubler must
remain active. See Voltage Doubler for more details.
Each OPAMP x can be configured to behave differently in different sleep modes. The behavior is determined by the
individual Run in Standby and On Demand bits in the OPAMP Control x registers (OPAMPCTRLx.RUNSTDBY, and
OPAMPCTRLx.ONDEMAND), as well as the common Enable bit in the Control A register (CTRLA.ENABLE).
© 2020 Microchip Technology Inc.
DS60001477C-page 921
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
Table 41-1. Individual OPAMP Sleep Mode Operation
OPAMPCTRLx.RUNSTDBY
OPAMPCTRLx.ONDEMAND
CTRLA.ENABLE
Sleep Behavior
-
-
0
Disabled
0
0
1
Always run in all sleep modes
except STANDBY sleep
mode
0
1
1
Only run in all sleep modes
except STANDBY sleep
mode if requested by a
peripheral.
1
0
1
Always run in all sleep mode
1
1
1
Only run in all sleep modes if
requested by a peripheral.
Note:
When OPAMPCTRLx.ONDEMAND=1, the analog block is powered off for the lowest power consumption if it is not
requested.
When requested, a start-up time delay is necessary when the system returns from sleep. The start-up time is
depending on the Bias Selection bits in the OPAMP Control x register (OPAMPCTRLx.BIAS) and the corresponding
speed/current consumption requirements.
41.6.7
Synchronization
Not applicable.
41.6.8
Configuring the Operational Amplifiers
Each individual operational amplifier is configured by its respective Operational Amplifier Control x register
(OPAMPCTRLx). These settings must be configured before the amplifier is started.
•
•
•
•
•
•
•
•
41.6.9
Select the positive input in OPAMPCTRLx.MUXPOS.
Select the negative input in OPAMPCTRLx.MUXNEG.
Select RES1EN if resistor ladder is used.
Select the input for the resistor ladder in OPAMPCTRLx.RES1MUX.
Select the potentiometer selection of the resistor ladder in OPAMPCTRLx.POTMUX.
Select the VCC input for the resistor ladder in OPAMPCTRLx.RES2VCC.
Connect the operational amplifier output to the resistor ladder using OPAMPCTRLx.RES2OUT.
Select the trade-off between speed and energy consumption in OPAMPCTRLx.BIAS.
Standalone Mode
Each operational amplifier can be used as standalone amplifier. In this mode, positive input, negative input and the
output are routed from/to external I/Os, requiring external feedback. OPAMPs can also be cascaded to support
multiple OPAMP configurations. Refer to Operational Amplifier Control x register (OPAMPCTRLx) for further details
on how to configure OPAMP I/Os.
41.6.10 Built-in Modes
41.6.10.1 Voltage Follower
In this mode the unity gain path is selected for the negative input. The OPAMPCTRLx register can be configured as
follows:
Table 41-2. Configuration - Three Independent Unitary Gain Followers
MUXPOS
MUXNEG
© 2020 Microchip Technology Inc.
RES1MUX
POTMUX
RES2VCC
RES2OUT
RES1EN
ANAOUT
DS60001477C-page 922
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
OPAMP0
000
010
11
000
0
0
0
0
OPAMP1
000
010
11
000
0
0
0
0
OPAMP2
000
010
11
000
0
0
0
0
Figure 41-2. Voltage follower
Vin
+
Vout
OPAMP0
-
41.6.10.2 Inverting PGA
For inverting programmable gain amplifier operation, the OPAMPCTRLx registers can be configured as follows:
Table 41-3. Configuration - Three Independent Inverting PGAs
MUXPOS
MUXNEG
RES1MUX
POTMUX
RES2VCC
RES2OUT
RES1EN
ANAOUT
OPAMP0
011
001
01
100
0
1
1
0
OPAMP1
011
001
01
100
0
1
1
0
OPAMP2
011
001
01
100
0
1
1
0
Inverting PGA (Example: Vout=-3.Vin, R1=4R, R2=12R)
Figure 41-3. Inverting PGA
Vout = -(Vin-Ref)R2/R1 + Ref
Ref
+
OPAMP0
Vin
© 2020 Microchip Technology Inc.
Vout
-
DS60001477C-page 923
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
41.6.10.3 Non-Inverting PGA
For non-inverting programmable gain amplifier operation, the OPAMPCTRLx registers can be configured as follows:
Table 41-4. Configuration - Three Independent Non-Inverting PGAs (Example: Vout=4.Vin, R1=4R, R2=12R)
MUXPOS
MUXNEG
RES1MUX
POTMUX
RES2VCC
RES2OUT
RES1EN
ANAOUT
OPAMP0
000
001
11
100
0
1
1
0
OPAMP1
000
001
11
100
0
1
1
0
OPAMP2
000
001
11
100
0
1
1
0
Figure 41-4. Non-Inverting PGA
Vout = Vin(1+R2/R1)
Vin
Vout
OPAMP0
R2
R1
41.6.10.4 Cascaded Inverting PGA
The OPAMPs can be configured as three cascaded, inverting PGAs using these settings in OPAMPCTRLx:
Table 41-5. Cascade of three inverting PGAs (Example: R1=4R, R2=12R)
MUXPOS
MUXNEG
RES1MUX
POTMUX
RES2VCC
RES2OUT
RES1EN
ANAOUT
OPAMP0
011
001
01
100
0
1
1
0
OPAMP1
011
001
10
100
0
1
1
0
OPAMP2
011
001
10
100
0
1
1
0
Figure 41-5. Cascaded Inverting PGA
POS2=Gnd
+
OPAMP2
Vout
OA2OUT = -(OA1OUT-POS2)R2/R1 + POS2
POS1=Gnd
-
+
OPAMP1
R1
POS0=Gnd
+
R2
OA1OUT = -(OA0OUT-POS1)R2/R1 + POS1
-
OPAMP0
R1
R2
OA0OUT = -(Vin-POS0)R2/R1 + POS0
Vin
R1
R2
© 2020 Microchip Technology Inc.
DS60001477C-page 924
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
41.6.10.5 Cascaded Non-Inverting PGA
The OPAMPs can be configured as three cascaded, non-inverting PGAs using these settings in OPAMPCTRLx:
Table 41-6. Cascaded Non-Inverting PGA (Exemple: R1=4R, R2=12R)
MUXPOS
MUXNEG
RES1MUX
POTMUX
RES2VCC
RES2OUT
RES1EN
ANAOUT
OPAMP0
000
001
11
100
0
1
1
0
OPAMP1
010
001
11
100
0
1
1
0
OPAMP2
010
001
11
100
0
1
1
0
Figure 41-6. Cascaded Non-Inverting PGA
Vin
OA0OUT = Vin(1+R2/R1)
OA1OUT = OA0OUT(1+R2/R1)
OPAMP0
OA2OUT = OA1OUT(1+R2/R1)
OPAMP1
Vout
OPAMP2
R2
R1
R2
R1
R2
R1
41.6.10.6 Two OPAMPs Differential Amplifier
In this mode, OPAMP0 can be coupled with OPAMP1 or OPAMP1 with OPAMP2 in order to amplify a differtial signal.
To configure OPAMP0 and OPAMP1 as differential amplifier, the OPAMPCTRLx register can be configured as
follows:
Table 41-7. OPAMP0 OPAMP1 Differential Amplifier (Example: R1=4R, R2=12R)
MUXPOS
MUXNEG
RES1MUX
POTMUX
RES2VCC
RES2OUT
RES1EN
ANAOUT
OPAMP0
000
010
00
000
0
0
0
0
OPAMP1
000
001
10
100
0
1
1
0
OPAMP2
000
000
00
000
0
0
0
0
To configure OPAMP1 and OPAMP2 as differential amplifier, the OPAMPCTRLx register can be configured as
follows:
Table 41-8. OPAMP1 OPAMP2 Differential Amplifier (Example: R1=4R, R2=12R)
MUXPOS
MUXNEG
RES1MUX
POTMUX
RES2VCC
RES2OUT
RES1EN
ANAOUT
OPAMP0
000
000
00
000
0
0
0
0
OPAMP1
000
010
00
000
0
1
0
0
OPAMP2
000
001
10
100
0
1
1
0
© 2020 Microchip Technology Inc.
DS60001477C-page 925
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
Figure 41-7. OPAMP0 OPAMP1 Differential Amplifier
+
V2
Vdiff = (V2-V1)R2/R1
OPAMP1
V1
-
+
OPAMP0
R2
R1
-
41.6.10.7 Instrumentation Amplifier
In this mode, OPAMP0 and OPAMP1 are configured as voltage followers. The OPAMPCTRLx register can be
configured as follows:
Table 41-9. Instrumentation Amplifier Configuration
MUXPOS
MUXNEG
RES1MUX
POTMUX
RES2VCC
RES2OUT
RES1EN
ANAOUT
OPAMP0
000
010
11
010
0
1
1
0
OPAMP1
000
010
11
000
0
0
0
0
OPAMP2
110
001
10
010
0
1
1
0
The resistor ladders associated with OPAMP0 and OPAMP2 must be configured as follows in order to select the
appropriate gain:
Table 41-10. Instrumentation Amplifier Gain Selection
OPAMPCTRL0.POTMUX
OPAMPCTRL2.POTMUX
GAIN
0x7
Reserved
Reserved
0x6
0x0
1/7
0x5
Reserved
Reserved
0x4
0x1
1/3
0x3
Reserved
Reserved
0x2
0x2
1
0x1
0x4
3
0x0
0x6
7
Note: Either the DAC or GND must be the reference, selected by the OPAMPCTRL0.RES1MUX bits. Refer to
OPAMPCTRL0, OPAMPCTRL1 and OPAMPCTRL2 for details.
© 2020 Microchip Technology Inc.
DS60001477C-page 926
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
Figure 41-8. Instrumentation amplifier
V2
DAC
OPAMP0
GND
Vout = (V2-V1).Gain + Ref
OPAMP2
V1
OPAMP1
41.6.10.8 Transimpedance amplifier
Each OPAMP can be configured as a transimpedance amplifier (current to voltage converter). In this mode the
positive input is connected to ground. The negative input is connected to the output through the resistor ladder. The
OPAMPCTRLx register can be configured as follows:
Table 41-11. Transimpedance Amplifier
MUXPOS
MUXNEG
RES1MUX
POTMUX
RES2VCC
RES2OUT
RES1EN
ANAOUT
OPAMP0
011
000
01
000
0
1
1
0
OPAMP1
011
000
01
000
0
1
1
0
OPAMP2
011
000
01
000
0
1
1
0
Figure 41-9. Transimpedance Amplifier
+
OPAMPn
Vout = -Iin(R1+R2)
Iin
R1
R2
41.6.10.9 Programmable Hysteresis
Each OPAMP can be configured as an inverting or non-inverting comparator with programmable hysteresis. Applying
hysteresis will prevent constant toggling of the output, caused by noise when the input signals are close to each
other.
© 2020 Microchip Technology Inc.
DS60001477C-page 927
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
In both inverting and non-inverting comparator configurations the positive input is connected to the resistor ladder.
When OPAMP is configured as an inverting comparator with programmable hysteresis, the input voltage must be
applied to the negative input and RES1MUX must be connected to the ground. When an OPAMP is configured as a
non-inverting comparator with programmable hysteresis, the input voltage must be applied to RES1MUX and the
negative input must be connected to the ground.
To configure an OPAMP as an inverting comparator with programmable hysteresis, the OPAMPCTRLx register can
be configured as follows:
Table 41-12. Configuration of Input Muxes for OPAMP0 and OPAMP1 (Example: Vth = 3/4*Vcc, Ref = GND)
MUXPOS
MUXNEG
RES1MUX
POTMUX
RES2VCC
RES2OUT
RES1EN
ANAOUT
OPAMP0
001
000
11
001
0
1
1
0
OPAMP1
001
000
11
001
0
1
1
0
OPAMP2
001
000
11
001
0
1
1
0
Table 41-13. POTMUX [2:0]: Potentiometer Selection
Value
R1
R2
Threshold = Vcc * R1 / (R1 + R2)
0x0
14R
2R
7/8 * Vcc
0x1
12R
4R
3/4 * Vcc
0x2
8R
8R
1/2 * Vcc
0x3
6R
10R
3/8 * Vcc
0x4
4R
12R
1/4 * Vcc
0x5
3R
13R
3/16 * Vcc
0x6
2R
14R
1/8 * Vcc
0x7
R
15R
1/16 * Vcc
Figure 41-10. Inverting comparator with programmable hysteresis
R2
Ref
R1
+
Vout
OPAMPn
Vin
Threshold = Vcc*R1/(R1+R2)+Ref
To configure an OPAMP as a non-inverting comparator with programmable hysteresis, the OPAMPCTRLx register
can be configured as follows:
Table 41-14. Configuration of input muxes for OPAMP0 and OPAMP1 (Example: Vth = 1/3*Vcc, Ref = Gnd)
MUXPOS
MUXNEG
© 2020 Microchip Technology Inc.
RES1MUX
POTMUX
RES2VCC
RES2OUT
RES1EN
ANAOUT
DS60001477C-page 928
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
OPAMP0
001
000
00
100
0
1
1
0
OPAMP1
001
000
00
100
0
1
1
0
OPAMP2
001
000
00
100
0
1
1
0
Table 41-15. POTMUX [2:0]: Potentiometer Selection
Value
R1
R2
Threshold = Vcc * R1 / R2
0x0
14R
2R
Vcc * 7 (unused)
0x1
12R
4R
Vcc * 3 (unused)
0x2
8R
8R
Vcc (unused)
0x3
6R
10R
0.6* Vcc
0x4
4R
12R
1/3 * Vcc
0x5
3R
13R
3/13 *Vcc
0x6
2R
14R
1/7 * Vcc
0x7
R
15R
1/15 * Vcc
Figure 41-11. Non-Inverting comparator with programmable hysteresis
R2
Vin
R1
+
OPAMPn
Ref
Vout
Threshold = Vcc*R1/R2+Ref
41.6.11 ADC Driver
41.6.11.1 Buffer/PGA for ADC
Each OPAMP can be configured as a buffer or a PGA for the other modules (such as ADC or AC). OPAMPs can also
be cascaded to increase the programmable gain.
The output to the OPAMP must be enabled by writing a '1' to the Analog Output bit in the Operational Amplifier x
Control register (OPAMPCTRLx.ANAOUT). The ADC input mux must be configured to select OPAMP as input. Refer
to ADC – Analog-to-Digital Converter for details on configuring the ADC.
41.6.11.2 Offset and Gain Compensation
When the OPAMP is used in combination with the ADC, the OPAMP offset and gain errors can be compensated. To
calculate offset and gain error compensation values
1.
2.
Configure OPAMP as Voltage Follower
Route the OPAMP output to the ADC:
© 2020 Microchip Technology Inc.
DS60001477C-page 929
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
3.
4.
– Write a '1' to the Analog Output bit in the Operational Amplifier x Control register
(OPAMPCTRLx.ANAOUT)
– Select the OPAMP as input for the ADC, see ADC – Analog-to-Digital Converter.
Measure and set the Offset Correction value for the ADC OFFSETCORR register as in 41.6.11.3 Offset
Compensation.
Measure and set the Gain Correction value for the ADC GAINCORR register as in 41.6.11.4 Gain
Compensation.
The offset error compensation must be determined before gain error compensation.
The relation for offset and gain error compensation is shown in this equation:
Result = (converted value + OFFSETCORR)*GAINCORR
41.6.11.3 Offset Compensation
To determine the offset compensation value, the positive input must be tied to ground. The result of the ADC
conversion gives directly the offset compensation value that must be written in the ADC OFFSETCORR register.
Figure 41-12. Offset Compensation
OFFSETCORR
OPAn
ADC
RESULT
41.6.11.4 Gain Compensation
To perform gain compensation positive input must be close to VDD, but less (e.g. 0.8*Vref for instance) to avoid ADC
saturation. The value for gain error compensation is obtained by dividing the theoretical ADC conversion result by the
result from measurement. The obtained value for gain error compensation must be written in the ADC GAINCORR
register.
Figure 41-13. Gain Compensation
OFFSETCORR
0.8*Vcc
RESULTth/RESULT
OPAn
ADC
RESULT
41.6.12 AC Driver
One or several OPAMPs can be configured as input for the AC. The AC input mux must be appropriately configured
to select OPAMP as input.
© 2020 Microchip Technology Inc.
DS60001477C-page 930
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
41.6.13 Input Connection to DAC
The DAC can be used as a reference. This is configured by the corresponding OPAMPCTRLx.MUXPOS and
OPAMPCTRLx.RES1MUX bits.
41.6.14 Voltage Doubler
The OPAMP peripheral contains a voltage doubler for the analog multiplexer switches to ensure proper operation for
a supply voltage below 2.5V. Aside from the multiplexers, no other supply voltages are affected by the voltage
doubler.
The voltage doubler is normally switched on/off automatically, based on the supply level. If the supply voltage is
guaranteed to be above 2.5V, the voltage doubler can be completely disabled by writing the Low-Power Mux bit in the
Control Register (CTRLA.LPMUX).
When enabling OPAMPs, additional start-up time is required for the voltage doubler to settle. Disabling the voltage
doubler saves power and reduces the startup time.
41.6.15 Performance vs. Power Consumption
It is possible to tradeoff speed versus power efficiency to get the shortest possible propagation delay or the lowest
power consumption.
The speed setting is configured for each amplifier individually by the Bias Control field in the Operational Amplifier x
Control register (OPAMPCTRLx.BIAS). The BIAS bits select the amount of bias current provided to the operational
amplifiers. This will also affect the start-up time.
© 2020 Microchip Technology Inc.
DS60001477C-page 931
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
41.7
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
...
0x0403FF
CTRLA
Reserved
STATUS
7:0
0x040400
41.8
LPMUX
7:0
ENABLE
SWRST
READYx
READYx
READYx
ANAOUT
RES1EN
ENABLE
RES2VCC
MUXPOS[2:0]
RES2OUT
Reserved
OPAMPCTRLx0
7:0
15:8
23:16
31:24
ONDEMAND RUNSTDBY
POTMUX[2:0]
BIAS[1:0]
RES1MUX[1:0]
MUXNEG[2:0]
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
Refer to PAC - Peripheral Access Controller and 37.6.6 Synchronizationfor details.
© 2020 Microchip Technology Inc.
DS60001477C-page 932
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
41.8.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
LPMUX
R/W
0
CTRLA
0x00 [ID-000005dd]
0x00
PAC Write-Protection
6
5
4
3
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
Bit 7 – LPMUX Low-Power Mux
Value
Description
0
The analog input muxes have low resistance, but consume more power at lower voltages (e.g., are
driven by the voltage doubler).
1
The analog input muxes have high resistance, but consume less power at lower voltages (e.g., the
voltage doubler is disabled).
Bit 1 – ENABLE Enable
Value
Description
0
The peripheral is disabled.
1
The peripheral is enabled. Each OPAMP must also be enabled individually by the Enable bit in the
corresponding OPAMP Control register (OPAMPCTRLx.ENABLE).
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the MODULE to their initial state, and the OPAMP will be disabled.
Writing a '1' to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
© 2020 Microchip Technology Inc.
DS60001477C-page 933
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
41.8.2
Status
Name:
Offset:
Reset:
Property:
Bit
7
STATUS
0x02 [ID-000005dd]
0x00
–
6
5
4
Access
Reset
3
2
READYx
R
0
1
READYx
R
0
0
READYx
R
0
Bits 2,1,0 – READYx OPAMP x Ready
This bit is set when the OPAMPx output is ready.
This bit is cleared when the output of OPAMPx is not ready.
© 2020 Microchip Technology Inc.
DS60001477C-page 934
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
41.8.3
OPAMP Control x
Name:
Offset:
Reset:
Property:
Bit
OPAMPCTRLx
0x04+4*x, [x=0..2] [ID-000005dd]
0x00000080
PAC Write-Protection
31
30
29
28
27
26
25
24
23
22
21
MUXNEG[2:0]
R/W
0
20
19
18
16
R/W
0
17
MUXPOS[2:0]
R/W
0
R/W
0
10
RES1EN
R/W
0
9
RES2VCC
R/W
0
8
RES2OUT
R/W
0
2
ANAOUT
R/W
0
1
ENABLE
R/W
0
0
Access
Reset
Bit
Access
Reset
R/W
0
Bit
15
R/W
0
14
POTMUX[2:0]
R/W
0
7
ONDEMAND
R/W
0
6
RUNSTDBY
R/W
0
Access
Reset
Bit
Access
Reset
13
R/W
0
12
11
RES1MUX[1:0]
R/W
R/W
0
0
R/W
0
5
4
3
BIAS[1:0]
R/W
0
R/W
0
Bits 22:20 – MUXNEG[2:0] Negative Input Mux Selection
Selection on negative input for operational amplifier x.
Value
OPAMPx
Name
Description
0x0
0x1
0x2
0x3
x=0,1,2
x=0,1,2
x=0,1,2
x=0,1
x=2
x=0,1
x=2
x=0,1
x=2
x=0,1,2
x=0,1,2
OAxNEG
OAxTAP
OAxOUT
DAC
OA0NEG
Reserved
OA1NEG
Reserved
DAC
Reserved
Reserved
Negative I/O pin
Resistor ladder x taps
OPAMPx output
DAC output
Negative I/O pin OPA0
0x4
0x5
0x6
0x7
Negative I/O pin OPA1
DAC output
Bits 18:16 – MUXPOS[2:0] Positive Input Mux Selection
Selection on positive input for operational amplifier x.
Value
OPAMPx
Name
Description
0x0
0x1
0x2
x=0,1,2
x=0,1,2
x=0
x=1
x=2
x=0,1,2
x=0,1
x=2
OAxPOS
OAxTAP
DAC
OA0OUT
OA1OUT
GND
Reserved
OA0POS
Positive I/O pin
Resistor ladder x taps
DAC output
OPAMP0 output
OPAMP1 output
Ground
0x3
0x4
© 2020 Microchip Technology Inc.
Positive I/O pin OPA0
DS60001477C-page 935
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
...........continued
Value
OPAMPx
Name
0x5
x=0,1
x=2
x=0,1
x=2
x=0,1,2
Reserved
OA1POS
Reserved
OA0TAP
Reserved
0x6
0x7
Description
Positive I/O pin OPA1
Resistor ladder 0 taps
Bits 15:13 – POTMUX[2:0] Potentiometer selection
Resistor selection bits control a numeric potentiometer with eight fixed values.
Value
R1
R2
Gain = R2/R1
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
14R
12R
8R
6R
4R
3R
2R
R
2R
4R
8R
10R
12R
13R
14R
15R
1/7
1/3
1
1 + 2/3
3
4 + 1/3
7
15
Bits 12:11 – RES1MUX[1:0] Resistor 1 Mux
These bits select the connection of R1 resistor of the potentiometer.
Value
OPAMPx
Name
Description
0x0
0x1
0x2
x=0,1,2
x=0,1,2
x=0
x=1
x=2
x=0,1,2
OAxPOS
OAxNEG
DAC
OA0OUT
OA1OUT
GND
Positive inout of OPAMPx
Negative input of OPAMPx
DAC output
OPAMP0 output
OPAMP1 output
0x3
Bit 10 – RES1EN Resistor 1 Enable
Value
Description
0
R1 disconnected from RES1MUX.
1
R1 connected to RES1MUX.
Bit 9 – RES2VCC Resistor ladder To VCC
Value
Description
0
Swith open.
1
Switch closed.
Bit 8 – RES2OUT Resistor ladder To Output
Value
Description
0
Swith open.
1
Switch closed.
Bit 7 – ONDEMAND On Demand Control
The On Demand operation mode allows the OPAMPx to be enabled or disabled, depending on other peripheral
requests.
Value
Description
0
The OPAMPx is always on, if enabled.
1
The OPAMPx is enabled when a peripheral is requesting the OPAMPx to be used as an input. The
OPAMPx is disabled if no peripheral is requesting it as an input.
© 2020 Microchip Technology Inc.
DS60001477C-page 936
SAM L21 Family Data Sheet
Operational Amplifier Controller (OPAMP)
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the OPAMPx behaves during standby sleep mode:
Value
Description
0
The OPAMPx is disabled in standby sleep mode.
1
The OPAMPx is not stopped in standby sleep mode. If OPAMPCTRLx.ONDEMAND=1, the OPAMPx
will be running when a peripheral is requesting it as an input. If OPAMPCTRLx.ONDEMAND=0,
OPAMPx will always be running in standby sleep mode.
Bits 4:3 – BIAS[1:0] Bias Selection
These bits are used to select the bias mode.
Value
Name
Description
0x0
Mode 0
Minimum current consumption, but the slowest mode
0x1
Mode 1
Low current consumption, slow speed
0x2
Mode 2
High current consumption, fast speed
0x3
Mode 3
Maximum current consumption but the fastest mode
Bit 2 – ANAOUT Analog Output
This bit controls a switch connected to the OPAMP output.
Value
Description
0
Swith open. No ADC or AC connection.
1
Switch closed. OPAMP output is connected to the ADC or AC input.
Bit 1 – ENABLE Operational Amplifier Enable
Value
Description
0
The OPAMPx is disabled
1
The OPAMPx is enabled
© 2020 Microchip Technology Inc.
DS60001477C-page 937
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.
ADC – Analog-to-Digital Converter
42.1
Overview
The Analog-to-Digital Converter (ADC) converts analog signals to digital values. The ADC has up to 12-bit resolution,
and is capable of a sampling rate of up to 1MSPS. The input selection is flexible, and both differential and singleended measurements can be performed. In addition, several internal signal inputs are available. The ADC can
provide both signed and unsigned results.
ADC measurements can be started by either application software or an incoming event from another peripheral in the
device. ADC measurements can be started with predictable timing, and without software intervention.
Both internal and external reference voltages can be used.
An integrated temperature sensor is available for use with the ADC. The bandgap voltage as well as the scaled I/O
and core voltages can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user-defined thresholds, with minimum software
intervention required.
The ADC can be configured for 8-, 10- or 12-bit results. ADC conversion results are provided left- or right-adjusted,
which eases calculation when the result is represented as a signed value. It is possible to use DMA to move ADC
results directly to memory or peripherals when conversions are done.
The SAM L21 has two ADC instances, ADC0 and ADC1. The two inputs can be sampled simultaneously, as each
ADC includes sample and hold circuits.
Note: When the Peripheral Touch Controller (PTC) is enabled, ADC0 is serving the PTC exclusively. In this case,
ADC0 cannot be used by the user application.
42.2
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Two Analog to Digital Converters (ADC) ADC0 and ADC1
8-, 10- or 12-bit resolution
Up to 1,000,000 samples per second (1MSPS)
Differential and single-ended inputs
– Up to 20 analog inputs per ADC (20 unique channels total)
28 positive and 10 negative, including internal and external
Internal inputs:
– Internal temperature sensor
– Bandgap voltage
– Scaled core supply
– Scaled I/O supply
– Scaled VBAT supply
– DAC
Single, continuous and sequencing options
Windowing monitor with selectable channel
Conversion range: Vref = [1.0V to VDDANA ]
Built-in internal reference and external reference options
Event-triggered conversion for accurate timing (one event input)
Optional DMA transfer of conversion settings or result
Hardware gain and offset compensation
Averaging and oversampling with decimation to support up to 16-bit result
Selectable sampling time
Flexible Power / Throughput rate management
© 2020 Microchip Technology Inc.
DS60001477C-page 938
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
ADC0 can be configured to serve the Peripheral Touch Controller (PTC). This setup features:
• Low-power, high-sensitivity, environmentally robust capacitive touch elements:
– Buttons
– Sliders
– Wheels
– Proximity sensing
• Supports mutual capacitance and self-capacitance sensing:
– Up to buttons in self-capacitance mode
– Up to buttons in mutual-capacitance mode
– Mix-and-match mutual-and self-capacitance sensors
• One pin per electrode – no external components
• Load compensating charge sensing - Parasitic capacitance compensation and adjustable gain for superior
sensitivity
• Zero drift over temperature and supply voltage range
• Auto calibration and re-calibration of sensors
• Selectable channel change delay - Allows choosing the settling time on a new channel, as required
• Supported by the Atmel® QTouch® Composer development tool, which comprises QTouch Library project
builder and QTouch analyzer
42.3
Block Diagram
Figure 42-1. ADC Block Diagram
CTRLB
SEQCTRL
AVGCTRL
WINLT
SAMPCTRL
WINUT
EVCTRL
OFFSETCORR
SWTRIG
GAINCORR
INPUTCTRL
AIN0
...
AINn
INT.SIG
ADC
POST
PROCESSING
RESULT
AIN0
...
AINn
INTREF
INTVCC0
INTVCC1
INTVCC2
CTRLA
VREFA
VREFB
SEQSTATUS
PRESCALER
REFCTRL
© 2020 Microchip Technology Inc.
DS60001477C-page 939
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.4
Signal Description
Signal
Description
Type
VREFA/B
Analog input
External reference voltage
AIN[19..0]
Analog input
Analog input channels
Note: One signal can be mapped on several pins.
42.5
Product Dependencies
In order to use this peripheral, other parts of the system must be configured correctly, as described below.
42.5.1
I/O Lines
Using the ADC's I/O lines requires the I/O pins to be configured using the port configuration (PORT).
42.5.2
Power Management
The ADC will continue to operate in any sleep mode where the selected source clock is running. The ADC interrupts,
RESRDY and WINMON can be used to wake up the device from sleep modes. Events connected to the event
system can trigger other operations in the system without exiting sleep modes.
42.5.3
Clocks
The ADC bus clocks (CLK_APB_ADCx) bus clock (CLK_APB_ADCx) can be enabled in the Main Clock, which also
defines the default state.
The ADC requires a generic clock (GCLK_ADC). This clock must be configured and enabled in the Generic Clock
Controller (GCLK) before using the ADC.
A generic clock is asynchronous to the bus clock. Due to this asynchronicity, writes to certain registers will require
synchronization between the clock domains. Refer to 42.6.8 Synchronization for further details.
42.5.4
DMA
The DMA request line is connected to the DMA Controller (DMAC). Using the ADC DMA requests requires the DMA
Controller to be configured first.
42.5.5
Interrupts
The interrupt request line is connected to the interrupt controller. Using the ADC interrupt requires the interrupt
controller to be configured first.
42.5.6
Events
The events are connected to the Event System.
42.5.7
Debug Operation
When the CPU is halted in debug mode the ADC will halt normal operation. The ADC can be forced to continue
operation during debugging. Refer to DBGCTRL register for details.
42.5.8
Register Access Protection
All registers with write-access are optionally write-protected by the peripheral access controller (PAC), except the
following register:
•
Interrupt Flag Status and Clear (INTFLAG) register
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
PAC write-protection does not apply to accesses through an external debugger.
© 2020 Microchip Technology Inc.
DS60001477C-page 940
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.5.9
Analog Connections
I/O-pins (AINx), as well as the VREF A/B reference voltage pins are analog inputs to the ADC.
The analog signals of AC, ADC, DAC and OPAMP can be interconnected. The AC and ADC peripheral can request
the OPAMP using an analog ONDEMAND functionality.
See Analog Connections of Peripherals for details.
42.5.10 Calibration
The BIAS and LINEARITY calibration values from the production test must be loaded from the NVM Software
Calibration Area into the ADC Calibration register (CALIB) by software to achieve specified accuracy.
42.6
Functional Description
42.6.1
Principle of Operation
By default, the ADC provides results with 12-bit resolution. 8-bit or 10-bit results can be selected in order to reduce
the conversion time, see 42.6.2.8 Conversion Timing and Sampling Rate.
The ADC has an oversampling with decimation option that can extend the resolution to 16 bits. The input values can
be either internal (e.g., an internal temperature sensor) or external (connected I/O pins). The user can also configure
whether the conversion should be single-ended or differential.
42.6.2
Basic Operation
42.6.2.1 Initialization
The following registers are enable-protected, meaning that they can only be written when the ADC is disabled
(CTRLA.ENABLE=0):
•
•
•
•
Control B register (CTRLB)
Reference Control register (REFCTRL)
Event Control register (EVCTRL)
Calibration register (CALIB)
Enable-protection is denoted by the "Enable-Protected" property in the register description.
42.6.2.2 Enabling, Disabling and Resetting
The ADC is enabled by writing a '1' to the Enable bit in the Control A register (CTRLA.ENABLE). The ADC is disabled
by writing CTRLA.ENABLE=0.
The ADC is reset by writing a '1' to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in
the ADC, except DBGCTRL, will be reset to their initial state, and the ADC will be disabled. Refer to 42.8.1 CTRLA
for details.
42.6.2.3 Operation
In the most basic configuration, the ADC samples values from the configured internal or external sources
(INPUTCTRL register). The rate of the conversion depends on the combination of the GCLK_ADC frequency and the
clock prescaler.
To convert analog values to digital values, the ADC needs to be initialized first, as described in the Initialization
section. Data conversion can be started either manually by setting the Start bit in the Software Trigger register
(SWTRIG.START=1), or automatically by configuring an automatic trigger to initiate the conversions. A free-running
mode can be used to continuously convert an input channel. When using free-running mode the first conversion must
be started, while subsequent conversions will start automatically at the end of previous conversions.
The result of the conversion is stored in the Result register (RESULT) overwriting the result from the previous
conversion.
To avoid data loss if more than one channel is enabled, the conversion result must be read as soon as it is available
(INTFLAG.RESRDY). Failing to do so will result in an overrun error condition, indicated by the OVERRUN bit in the
Interrupt Flag Status and Clear register (INTFLAG.OVERRUN).
© 2020 Microchip Technology Inc.
DS60001477C-page 941
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
To enable one of the available interrupts sources, the corresponding bit in the Interrupt Enable Set register
(INTENSET) must be written to '1'.
42.6.2.4 Prescaler Selection
The ADC is clocked by GCLK_ADC. There is also a prescaler in the ADC to enable conversion at lower clock rates.
Refer to CTRLB for details on prescaler settings. Refer to 42.6.2.8 Conversion Timing and Sampling Rate for details
on timing and sampling rate.
Figure 42-2. ADC Prescaler
GCLK_ADC
DIV256
DIV128
DIV64
DIV32
DIV16
DIV8
DIV4
DIV2
9-BIT PRESCALER
CTRLB.PRESCALER[2:0]
CLK_ADC
Note: The minimum prescaling factor is DIV2.
42.6.2.5 Reference Configuration
The ADC has various sources for its reference voltage VREF. The Reference Voltage Selection bit field in the
Reference Control register (REFCTRL.REFSEL) determines which reference is selected. By default, the internal
voltage reference INTREF is selected. Based on customer application requirements, the external or internal
reference can be selected. Refer to REFCTRL.REFSEL for further details on available selections.
42.6.2.6 ADC Resolution
The ADC supports 8-bit, 10-bit or 12-bit resolution. Resolution can be changed by writing the Resolution bit group in
the Control C register (CTRLC.RESSEL). By default, the ADC resolution is set to 12 bits. The resolution affects the
propagation delay, see also 42.6.2.8 Conversion Timing and Sampling Rate.
42.6.2.7 Differential and Single-Ended Conversions
The ADC has two conversion options: differential and single-ended:
If the positive input is always positive, the single-ended conversion should be used in order to have full 12-bit
resolution in the conversion.
If the positive input may go below the negative input, the differential mode should be used in order to get correct
results.
The differential mode is enabled by setting DIFFMODE bit in the Control C register (CTRLC.DIFFMODE). Both
conversion types could be run in single mode or in free-running mode. When the free-running mode is selected, an
ADC input will continuously sample the input and performs a new conversion. The INTFLAG.RESRDY bit will be set
at the end of each conversion.
42.6.2.8 Conversion Timing and Sampling Rate
The following figure shows the ADC timing for one single conversion. A conversion starts after the software or event
start are synchronized with the GCLK_ADC clock. The input channel is sampled in the first half CLK_ADC period.
© 2020 Microchip Technology Inc.
DS60001477C-page 942
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
Figure 42-3. ADC Timing for One Conversion in 12-bit Resolution
CLK_ADC
START
STATE
SAMPLING
MSB
10
9
8
7
6
5
4
3
2
1
LSB
INT
The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control
register (SAMPCTRL.SAMPLEN). As example, the next figure is showing the timing conversion with sampling time
increased to six CLK_ADC cycles.
Figure 42-4. ADC Timing for One Conversion with Increased Sampling Time, 12-bit
CLK_ADC
START
STATE
SAMPLING
MSB
10
9
8
7
6
5
4
3
2
1
LSB
INT
The ADC provides also offset compensation, see the following figure. The offset compensation is enabled by the
Offset Compensation bit in the Sampling Control register (SAMPCTRL.OFFCOMP).
Note: If offset compensation is used, the sampling time must be set to one cycle of CLK_ADC.
In free running mode, the sampling rate RS is calculated by
RS = fCLK_ADC / ( nSAMPLING + nOFFCOMP + nDATA)
Here, nSAMPLING is the sampling duration in CLK_ADC cycles, nOFFCOMP is the offset compensation duration in clock
cycles, and nDATA is the bit resolution. fCLK_ADC is the ADC clock frequency from the internal prescaler: fCLK_ADC =
fGCLK_ADC / 2^(1 + CTRLB.PRESCALER)
Figure 42-5. ADC Timing for One Conversion with Offset Compensation, 12-bit
CLK_ADC
START
STATE
Offset Compensation
SAMPLING
MSB
10
9
8
7
6
5
4
3
2
1
LSB
INT
The impact of resolution on the sampling rate is seen in the next two figures, where free-running sampling in 12-bit
and 8-bit resolution are compared.
Figure 42-6. ADC Timing for Free Running in 12-bit Resolution
CLK_ADC
CONVERT
STATE
LSB
SAMPLING
MSB
10
9
8
7
6
5
4
3
2
1
LSB
SAMPLING
MSB
10
9
8
7
6
INT
© 2020 Microchip Technology Inc.
DS60001477C-page 943
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
Figure 42-7. ADC Timing for Free Running in 8-bit Resolution
CLK_ADC
CONVERT
STATE
LSB
SAMPLING
MSB
6
5
4
3
2
1
LSB
SAMPLING
MSB
6
5
4
3
2
1
LSB
SAMPLING
MSB
INT
The propagation delay of an ADC measurement is given by:
PropagationDelay =
1 + Resolution
�ADC
Example. In order to obtain 1MSPS in 12-bit resolution with a sampling time length of four
CLK_ADC cycles, fCLK_ADC must be 1MSPS * (4 + 12) = 16MHz. As the minimal division factor of
the prescaler is 2, GCLK_ADC must be 32MHz.
42.6.2.9 Accumulation
The result from multiple consecutive conversions can be accumulated. The number of samples to be accumulated is
specified by the Sample Number field in the Average Control register (AVGCTRL.SAMPLENUM). When accumulating
more than 16 samples, the result will be too large to match the 16-bit RESULT register size. To avoid overflow, the
result is right shifted automatically to fit within the available register size. The number of automatic right shifts is
specified in the table below.
Note: To perform the accumulation of two or more samples, the Conversion Result Resolution field in the Control C
register (CTRLC.RESSEL) must be set.
Table 42-1. Accumulation
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Number of
Automatic Right
Shifts
Final Result
Precision
Automatic
Division Factor
1
0x0
0
12 bits
0
2
0x1
0
13 bits
0
4
0x2
0
14 bits
0
8
0x3
0
15 bits
0
16
0x4
0
16 bits
0
32
0x5
1
16 bits
2
64
0x6
2
16 bits
4
128
0x7
3
16 bits
8
256
0x8
4
16 bits
16
512
0x9
5
16 bits
32
1024
0xA
6
16 bits
64
Reserved
0xB –0xF
12 bits
0
42.6.2.10 Averaging
Averaging is a feature that increases the sample accuracy, at the cost of a reduced sampling rate. This feature is
suitable when operating in noisy conditions.
Averaging is done by accumulating m samples, as described in 42.6.2.9 Accumulation, and dividing the result by m.
The averaged result is available in the RESULT register. The number of samples to be accumulated is specified by
writing to AVGCTRL.SAMPLENUM as shown in Table 42-2.
© 2020 Microchip Technology Inc.
DS60001477C-page 944
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
The division is obtained by a combination of the automatic right shift described above, and an additional right shift
that must be specified by writing to the Adjusting Result/Division Coefficient field in AVGCTRL (AVGCTRL.ADJRES),
as described in Table 42-2.
Note: To perform the averaging of two or more samples, the Conversion Result Resolution field in the Control C
register (CTRLC.RESSEL) must be set.
Averaging AVGCTRL.SAMPLENUM samples will reduce the un-averaged sampling rate by a factor
1
.
AVGCTRL.SAMPLENUM
When the averaged result is available, the INTFLAG.RESRDY bit will be set.
Table 42-2. Averaging
Number of
Accumulated
Samples
AVGCTRL.
SAMPLENUM
Intermediate
Result
Precision
Number of
Automatic
Right Shifts
Division
Factor
AVGCTRL.ADJRES Total
Number
of Right
Shifts
Final Result
Precision
Automatic
Division
Factor
1
0x0
12 bits
0
1
0x0
12 bits
0
2
0x1
13
0
2
0x1
1
12 bits
0
4
0x2
14
0
4
0x2
2
12 bits
0
8
0x3
15
0
8
0x3
3
12 bits
0
16
0x4
16
0
16
0x4
4
12 bits
0
32
0x5
17
1
16
0x4
5
12 bits
2
64
0x6
18
2
16
0x4
6
12 bits
4
128
0x7
19
3
16
0x4
7
12 bits
8
256
0x8
20
4
16
0x4
8
12 bits
16
512
0x9
21
5
16
0x4
9
12 bits
32
1024
0xA
22
6
16
0x4
10
12 bits
64
Reserved
0xB –0xF
12 bits
0
0x0
42.6.2.11 Oversampling and Decimation
By using oversampling and decimation, the ADC resolution can be increased from 12 bits up to 16 bits, for the cost of
reduced effective sampling rate.
To increase the resolution by n bits, 4n samples must be accumulated. The result must then be right-shifted by n bits.
This right-shift is a combination of the automatic right-shift and the value written to AVGCTRL.ADJRES. To obtain the
correct resolution, the ADJRES must be configured as described in the table below. This method will result in n bit
extra LSB resolution.
Table 42-3. Configuration Required for Oversampling and Decimation
Result
Resolution
Number of
Samples to
Average
AVGCTRL.SAMPLENUM[3:0]
Number of
Automatic
Right Shifts
AVGCTRL.ADJRES[2:0]
13 bits
41 = 4
0x2
0
0x1
14 bits
42
= 16
0x4
0
0x2
15 bits
43 = 64
0x6
2
0x1
16 bits
44 = 256
0x8
4
0x0
© 2020 Microchip Technology Inc.
DS60001477C-page 945
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.6.2.12 Automatic Sequences
The ADC has the ability to automatically sequence a series of conversions. This means that each time the ADC
receives a start-of-conversion request, it can perform multiple conversions automatically. All of the 32 positive inputs
can be included in a sequence by writing to corresponding bits in the Sequence Control register (SEQCTRL). The
order of the conversion in a sequence is the lower positive MUX selection to upper positive MUX (AIN0, AIN1,
AIN2 ...). In differential mode, the negative inputs selected by MUXNEG field, will be used for the entire sequence.
When a sequence starts, the Sequence Busy status bit in Sequence Status register (SEQSTATUS.SEQBUSY) will be
set. When the sequence is complete, the Sequence Busy status bit will be cleared.
Each time a conversion is completed, the Sequence State bit in Sequence Status register (SEQSTATUS.SEQSTATE)
will store the input number from which the conversion is done. The result will be stored in the RESULT register, and
the Result Ready Interrupt Flag (INTFLAG.RESRDY) is set.
If additional inputs must be scanned, the ADC will automatically start a new conversion on the next input present in
the sequence list.
Note that if SEQCTRL register has no bits set to '1', the conversion is done with the selected MUXPOS input.
42.6.2.13 Window Monitor
The window monitor feature allows the conversion result in the RESULT register to be compared to predefined
threshold values. The window mode is selected by setting the Window Monitor Mode bits in the Control C register
(CTRLC.WINMODE). Threshold values must be written in the Window Monitor Lower Threshold register (WINLT) and
Window Monitor Upper Threshold register (WINUT).
If differential input is selected, the WINLT and WINUT are evaluated as signed values. Otherwise they are evaluated
as unsigned values. The significant WINLT and WINUT bits are given by the precision selected in the Conversion
Result Resolution bit group in the Control C register (CTRLC.RESSEL). This means that for example in 8-bit mode,
only the eight lower bits will be considered. In addition, in differential mode, the eighth bit will be considered as the
sign bit, even if the ninth bit is zero.
The INTFLAG.WINMON interrupt flag will be set if the conversion result matches the window monitor condition.
42.6.2.14 Offset and Gain Correction
Inherent gain and offset errors affect the absolute accuracy of the ADC.
The offset error is defined as the deviation of the actual ADC transfer function from an ideal straight line at zero input
voltage. The offset error cancellation is handled by the Offset Correction register (OFFSETCORR). The offset
correction value is subtracted from the converted data before writing the Result register (RESULT).
The gain error is defined as the deviation of the last output step’s midpoint from the ideal straight line, after
compensating for offset error. The gain error cancellation is handled by the Gain Correction register (GAINCORR).
To correct these two errors, the Digital Correction Logic Enabled bit in the Control C register (CTRLC.CORREN) must
be set.
Offset and gain error compensation results are both calculated according to:
Result = Conversion value+ − OFFSETCORR ⋅ GAINCORR
The correction will introduce a latency of 13 CLK_ADC clock cycles. In free running mode this latency is introduced
on the first conversion only, since its duration is always less than the propagation delay. In single conversion mode
this latency is introduced for each conversion.
© 2020 Microchip Technology Inc.
DS60001477C-page 946
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
Figure 42-8. ADC Timing Correction Enabled
START
CONV0
CONV1
CORR0
42.6.3
CONV2
CORR1
CONV3
CORR2
CORR3
Additional Features
42.6.3.1 Double Buffering
The following registers are double buffered:
•
•
•
•
•
•
•
•
Input Control (INPUTCTRL)
Control C (CTRLC)
Average Control (AVGCTRL)
Sampling Time Control (SAMPCTRL)
Window Monitor Lower Threshold (WINLT)
Window Monitor Upper Threshold (WINUT)
Gain Correction (GAINCORR)
Offset Correction (OFFSETCORR)
When one of these registers is written, the data is stored in the corresponding buffer as long as the current
conversion is not impacted, and the corresponding busy status will be set in the Synchronization Busy register
(SYNCBUSY). When a new RESULT is available, data stored in the buffer registers will be transfered to the ADC and
a new conversion can start.
42.6.3.2 Device Temperature Measurement
Principle
The device has an integrated temperature sensor which is part of the Supply Controller (SUPC). The analog signal of
that sensor can be converted into a digital value by the ADC. The digital value can be converted into a temperature in
°C by following the steps in this section.
Configuration and Conditions
In order to conduct temperature measurements, configure the device according to these steps.
1. Configure the clocks and device frequencies according to the Electrical Characteristics.
2. Configure the Voltage References System of the Supply Controller (SUPC):
2.1.
Enable the temperature sensor by writing a '1' to the Temperature Sensor Enable bit in the VREF
Control register (SUPC.VREF.TSEN).
2.2.
Select the required voltage for the internal voltage reference INTREF by writing to the Voltage
Reference Selection bits (SUPC.VREF.SEL). The required value can be found in the Electrical
Characteristics.
3. Configure the ADC:
3.1.
Select the internal voltage reference INTREF as ADC reference voltage by writing to the Reference
Control register (ADC.REFCTRL.REFSEL).
© 2020 Microchip Technology Inc.
DS60001477C-page 947
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
3.2.
3.3.
3.4.
Select the temperature sensor vs. internal GND as input by writing TEMP and GND to the positive
and negative MUX Input Selection bit fields (ADC.INPUTCTRL.MUXNEG and .MUXPOS,
respectively).
Configure the remaining ADC parameters according to the Electrical Characteristics.
Enable the ADC and acquire a value, ADCm.
Calculation Parameter Values
The temperature sensor behavior is linear, but it is sensitive to several parameters such as the internal voltage
reference - which itself depends on the temperature. To take this into account, each device contains a Temperature
Log row with individual calibration data measured and written during the production tests. These calibration values
are read by software to infer the most accurate temperature readings possible.
The Temperature Log Row basically contains the following parameter set for two different temperatures ("ROOM"
and "HOT"):
• Calibration temperatures in °C. One at room temperature tempR, one at a higher temperature tempH:
– ROOM_TEMP_VAL_INT and ROOM_TEMP_VAL_DEC contain the measured temperature at room
insertion, tempR, in °C, separated in integer and decimal value.
Example: For ROOM_TEMP_VAL_INT=0x19=25 and ROOM_TEMP_VAL_DEC=2, the measured
temperature at room insertion is 25.2°C.
– HOT_TEMP_VAL_INT and HOT_TEMP_VAL_DEC contain the measured temperature at hot insertion,
tempH, in °C. The integer and decimal value are also separated.
• For each temperature, the corresponding sensor value at the ADC in 12-bit, ADCR and ADCH:
– ROOM_ADC_VAL contains the 12-bit ADC value, ADCR, corresponding to tempR. Its conversion to Volt is
denoted VADCR.
– HOT_ADC_VAL contains the 12-bit ADC value, ADCH, corresponding to tempH. Its conversion to Volt is
denoted VADCH.
• Actual reference voltages at each calibration temperature in Volt, INT1VR and INT1VH, respectively:
– ROOM_INT1V_VAL is the 2’s complement of the internal 1V reference value at tempR: INT1VR.
– HOT_INT1V_VAL is the 2’s complement of the internal 1V reference value at tempH: INT1VH.
– Both ROOM_INT1V_VAL and HOT_INT1V_VAL values are centered around 1V with a 0.001V step. In
other words, the range of values [0,127] corresponds to [1V, 0.873V] and the range of values [-1, -127]
corresponds to [1.001V, 1.127V]. INT1V == 1 - (VAL/1000) is valid for both ranges.
Calculating the Temperature by Linear Interpolation
Using the data pairs (tempR, VADCR) and (tempH, VADCH) for a linear interpolation, we have the following equation:
(
���� − �����
����� − �����
)=(
)
���� − �����
����� − �����
The voltages Vx are acquired as 12-bit ADC values ADCx, with respect to an internal reference voltage INT1Vx:
[Equation 1]
INT1V�
����� = ���� ⋅ 12
2 −1
For the measured value of the temperature sensor, ADCm, the reference voltage is assumed to be perfect, i.e.,
INT1Vm=INT1Vc=1V. These substitutions yield a coarse value of the measured temperature tempC:
[Equation 2]
����� = ����� +
���� ⋅
INT1V�
212 − 1
���� ⋅
− ���� ⋅
INT1V�
212 − 1
INT1V�
212 − 1
− ���� ⋅
Or, after eliminating the 12-bit scaling factor (212-1):
⋅ ����� − �����
INT1V�
212 − 1
[Equation 3]
© 2020 Microchip Technology Inc.
DS60001477C-page 948
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
����� = ����� +
���� ⋅ INT1V� − ���� ⋅ INT1V� ⋅ ����� − �����
���� ⋅ INT1V� − ���� ⋅ INT1V�
Equations 3 is a coarse value, because we assumed that INT1Vc=1V. To achieve a more accurate result, we replace
INT1Vc with an interpolated value INT1Vm. We use the two data pairs (tempR, INT1VR) and (tempH, INT1VH) and
yield:
(
INT1V� − INT1V�
INT1V� − INT1V��
)
)=(
����� − �����
����� − �����
Using the coarse temperature value tempc, we can infer a more precise INT1Vm value during the ADC conversion as:
[Equation 4]
INT1V� = INT1V� + (
(INT1V� − INT1V�) ⋅ (����� − �����)
)
(����� − �����)
Back to Equation 3, we replace the simple INT1Vc=1V by the more precise INT1Vm of Equation 4, and find a more
accurate temperature value tempf:
[Equation 5]
����� = ����� +
42.6.4
DMA Operation
���� ⋅ INT1V� − ���� ⋅ INT1V� ⋅ ����� − �����
���� ⋅ INT1V� − ���� ⋅ INT1V�
The ADC generates the following DMA request:
•
42.6.5
Result Conversion Ready (RESRDY): the request is set when a conversion result is available and cleared when
the RESULT register is read. When the averaging operation is enabled, the DMA request is set when the
averaging is completed and result is available.
Interrupts
The ADC has the following interrupt sources:
•
•
•
Result Conversion Ready: RESRDY
Window Monitor: WINMON
Overrun: OVERRUN
The RESRDY and WINMON interrupts are asynchronous wake-up sources. See Sleep Mode Controller for details.
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
(INTFLAG) register is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a
one to the corresponding bit in the Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear (INTENCLR) register. An interrupt request is generated when the
interrupt flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt
flag is cleared, the interrupt is disabled, or the ADC is reset. See INTFLAG register for details on how to clear
interrupt flags. All interrupt requests from the peripheral are ORed together on system level to generate one
combined interrupt request to the NVIC. Refer to Nested Vector Interrupt Controller for details. The user must read
the INTFLAG register to determine which interrupt condition is present.
Note that interrupts must be globally enabled for interrupt requests to be generated. Refer to Nested Vector Interrupt
Controller for details.
42.6.6
Events
The ADC can generate the following output events:
•
•
Result Ready (RESRDY): Generated when the conversion is complete and the result is available. Refer to
42.8.4 EVCTRL for details.
Window Monitor (WINMON): Generated when the window monitor condition match. Refer to 42.8.10 CTRLC for
details.
© 2020 Microchip Technology Inc.
DS60001477C-page 949
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
Setting an Event Output bit in the Event Control Register (EVCTRL.xxEO=1) enables the corresponding output event.
Clearing this bit disables the corresponding output event. Refer to the Event System chapter for details on configuring
the event system.
The ADC can take the following actions on an input event:
•
•
Start conversion (START): Start a conversion. Refer to 42.8.17 SWTRIG for details.
Conversion flush (FLUSH): Flush the conversion. Refer to 42.8.17 SWTRIG for details.
Setting an Event Input bit in the Event Control register (EVCTRL.xxEI=1) enables the corresponding action on input
event. Clearing this bit disables the corresponding action on input event.
The ADC uses only asynchronous events, so the asynchronous Event System channel path must be configured. By
default, the ADC will detect a rising edge on the incoming event. If the ADC action must be performed on the falling
edge of the incoming event, the event line must be inverted first. This is done by setting the corresponding Event
Invert Enable bit in Event Control register (EVCTRL.xINV=1).
Note: If several events are connected to the ADC, the enabled action will be taken on any of the incoming events. If
FLUSH and START events are available at the same time, the FLUSH event has priority.
42.6.7
Sleep Mode Operation
The ONDEMAND and RUNSTDBY bits in the Control A register (CTRLA) control the behavior of the ADC during
standby sleep mode, in cases where the ADC is enabled (CTRLA.ENABLE = 1). For further details on available
options, refer to Table 42-4.
Note: When CTRLA.ONDEMAND=1, the analog block is powered-off when the conversion is complete. When a
start request is detected, the system returns from sleep and starts a new conversion after the start-up time delay.
Table 42-4. ADC Sleep Behavior
CTRLA.RUNSTDBY CTRLA.ONDEMAND CTRLA.ENABLE Description
42.6.8
x
x
0
Disabled
0
0
1
Run in all sleep modes except STANDBY.
0
1
1
Run in all sleep modes on request, except
STANDBY.
1
0
1
Run in all sleep modes.
1
1
1
Run in all sleep modes on request.
Synchronization
Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be
synchronized when written or read.
The following bits are synchronized when written:
•
•
Software Reset bit in Control A register (CTRLA.SWRST)
Enable bit in Control A register (CTRLA.ENABLE)
The following registers are synchronized when written:
•
•
•
•
•
•
•
•
•
Input Control register (INPUTCTRL)
Control C register (CTRLC)
Average control register (AVGCTRL)
Sampling time control register (SAMPCTRL)
Window Monitor Lower Threshold register (WINLT)
Window Monitor Upper Threshold register (WINUT)
Gain correction register (GAINCORR)
Offset Correction register (OFFSETCORR)
Software Trigger register (SWTRIG)
© 2020 Microchip Technology Inc.
DS60001477C-page 950
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
Required write-synchronization is denoted by the "Write-Synchronized" property in the register description.
© 2020 Microchip Technology Inc.
DS60001477C-page 951
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.7
Register Summary
Offset
Name
Bit Pos.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
CTRLA
CTRLB
REFCTRL
EVCTRL
INTENCLR
INTENSET
INTFLAG
SEQSTATUS
0x08
INPUTCTRL
0x0A
CTRLC
0x0C
0x0D
AVGCTRL
SAMPCTRL
0x0E
WINLT
0x10
WINUT
0x12
GAINCORR
0x14
OFFSETCORR
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
15:8
7:0
15:8
7:0
7:0
7:0
15:8
7:0
15:8
7:0
15:8
7:0
15:8
0x16
...
0x17
0x18
0x19
...
0x1B
0x1C
0x1D
...
0x1F
REFCOMP
SEQBUSY
OFFCOMP
ENABLE
SWRST
PRESCALER[2:0]
REFSEL[3:0]
WINMONEO RESRDYEO STARTINV
FLUSHINV
STARTEI
FLUSHEI
WINMON
OVERRUN
RESRDY
WINMON
OVERRUN
RESRDY
WINMON
OVERRUN
RESRDY
SEQSTATE[4:0]
MUXPOS[4:0]
MUXNEG[4:0]
RESSEL[1:0]
CORREN
FREERUN
LEFTADJ
DIFFMODE
WINMODE[2:0]
ADJRES[2:0]
SAMPLENUM[3:0]
SAMPLEN[5:0]
WINLT[7:0]
WINLT[15:8]
WINUT[7:0]
WINUT[15:8]
GAINCORR[7:0]
GAINCORR[11:8]
OFFSETCORR[7:0]
OFFSETCORR[11:8]
Reserved
SWTRIG
7:0
START
FLUSH
Reserved
DBGCTRL
7:0
DBGRUN
Reserved
7:0
0x20
SYNCBUSY
0x22
...
0x23
Reserved
0x24
RESULT
0x26
...
0x27
Reserved
0x28
SEQCTRL
0x2C
CALIB
42.8
ONDEMAND RUNSTDBY
WINUT
WINLT
SAMPCTRL
AVGCTRL
CTRLC
15:8
INPUTCTRL
SWTRIG
7:0
15:8
RESULT[7:0]
RESULT[15:8]
7:0
15:8
23:16
31:24
7:0
15:8
SEQEN[7:0]
SEQEN[15:8]
SEQEN[23:16]
SEQEN[31:24]
ENABLE
SWRST
OFFSETCOR
GAINCORR
R
BIASCOMP[2:0]
BIASREFBUF[2:0]
Register Description
Registers can be 8, 16, or 32 bits wide. Atomic 8-, 16-, and 32-bit accesses are supported. In addition, the 8-bit
quarters and 16-bit halves of a 32-bit register, and the 8-bit halves of a 16-bit register can be accessed directly.
© 2020 Microchip Technology Inc.
DS60001477C-page 952
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
Some registers require synchronization when read and/or written. Synchronization is denoted by the "ReadSynchronized" and/or "Write-Synchronized" property in each individual register description.
Optional write-protection by the Peripheral Access Controller (PAC) is denoted by the "PAC Write-Protection"
property in each individual register description.
Some registers are enable-protected, meaning they can only be written when the module is disabled. Enableprotection is denoted by the "Enable-Protected" property in each individual register description
Refer to PAC - Peripheral Access Controller and 37.6.6 Synchronizationfor details.
© 2020 Microchip Technology Inc.
DS60001477C-page 953
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.1
Control A
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
ONDEMAND
R/W
0
CTRLA
0x00
0x00
PAC Write-Protection, Write-Synchronized
6
RUNSTDBY
R/W
0
5
4
3
2
1
ENABLE
R/W
0
0
SWRST
R/W
0
Bit 7 – ONDEMAND On Demand Control
The On Demand operation mode allows the ADC to be enabled or disabled, depending on other peripheral requests.
In On Demand operation mode, i.e., if the ONDEMAND bit has been previously set, the ADC will only be running
when requested by a peripheral. If there is no peripheral requesting the ADC will be in a disable state.
If On Demand is disabled the ADC will always be running when enabled.
In standby sleep mode, the On Demand operation is still active if the CTRLA.RUNSTDBY bit is '1'. If
CTRLA.RUNSTDBY is '0', the ADC is disabled.
This bit is not synchronized.
Value
Description
0
The ADC is always on , if enabled.
1
The ADC is enabled, when a peripheral is requesting the ADC conversion. The ADC is disabled if no
peripheral is requesting it.
Bit 6 – RUNSTDBY Run in Standby
This bit controls how the ADC behaves during standby sleep mode.
This bit is not synchronized.
Value
Description
0
The ADC is halted during standby sleep mode.
1
The ADC is not stopped in standby sleep mode. If CTRLA.ONDEMAND=1, the ADC will be running
when a peripheral is requesting it. If CTRLA.ONDEMAND=0, the ADC will always be running in
standby sleep mode.
Bit 1 – ENABLE Enable
Due to synchronization there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The value
written to CTRL.ENABLE will read back immediately and the ENABLE bit in the SYNCBUSY register
(SYNCBUSY.ENABLE) will be set. SYNCBUSY.ENABLE will be cleared when the operation is complete.
Value
Description
0
The ADC is disabled.
1
The ADC is enabled.
Bit 0 – SWRST Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets all registers in the ADC, except DBGCTRL, to their initial state, and the ADC will be
disabled.
Writing a '1' to CTRL.SWRST will always take precedence, meaning that all other writes in the same write-operation
will be discarded.
Due to synchronization there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST and
SYNCBUSY.SWRST will both be cleared when the reset is complete.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
© 2020 Microchip Technology Inc.
DS60001477C-page 954
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.2
Control B
Name:
Offset:
Reset:
Property:
Bit
7
CTRLB
0x01
0x00
PAC Write-Protection, Enable-Protected
6
5
4
3
Access
Reset
2
R/W
0
1
PRESCALER[2:0]
R/W
0
0
R/W
0
Bits 2:0 – PRESCALER[2:0] Prescaler Configuration
This field defines the ADC clock relative to the peripheral clock.
This field is not synchronized.
Value
Name
Description
0x0
DIV2
Peripheral clock divided by 2
0x1
DIV4
Peripheral clock divided by 4
0x2
DIV8
Peripheral clock divided by 8
0x3
DIV16
Peripheral clock divided by 16
0x4
DIV32
Peripheral clock divided by 32
0x5
DIV64
Peripheral clock divided by 64
0x6
DIV128
Peripheral clock divided by 128
0x7
DIV256
Peripheral clock divided by 256
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.3
Reference Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
REFCOMP
R/W
0
REFCTRL
0x02
0x00
PAC Write-Protection, Enable-Protected
6
5
4
3
R/W
0
2
1
REFSEL[3:0]
R/W
R/W
0
0
0
R/W
0
Bit 7 – REFCOMP Reference Buffer Offset Compensation Enable
The gain error can be reduced by enabling the reference buffer offset compensation. This will decrease the input
impedance and thus increase the start-up time of the reference.
Value
Description
0
Reference buffer offset compensation is disabled.
1
Reference buffer offset compensation is enabled.
Bits 3:0 – REFSEL[3:0] Reference Selection
These bits select the reference for the ADC.
Value
Name
Description
0x0
INTREF
internal variable reference voltage
x01
INTVCC0
1/1.6 VDDANA
0x2
INTVCC1
1/2 VDDANA (only for VDDANA > 2.0V)
0x3
VREFA
External reference
0x4
VREFB
External reference
0x5
INTVCC2
VDDANA
0x6 Reserved
0xF
© 2020 Microchip Technology Inc.
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SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.4
Event Control
Name:
Offset:
Reset:
Property:
Bit
7
EVCTRL
0x03
0x00
PAC Write-Protection, Enable-Protected
6
Access
Reset
5
WINMONEO
R/W
0
4
RESRDYEO
R/W
0
3
STARTINV
R/W
0
2
FLUSHINV
R/W
0
1
STARTEI
R/W
0
0
FLUSHEI
R/W
0
Bit 5 – WINMONEO Window Monitor Event Out
This bit indicates whether the Window Monitor event output is enabled or not and an output event will be generated
when the window monitor detects something.
Value
Description
0
Window Monitor event output is disabled and an event will not be generated.
1
Window Monitor event output is enabled and an event will be generated.
Bit 4 – RESRDYEO Result Ready Event Out
This bit indicates whether the Result Ready event output is enabled or not and an output event will be generated
when the conversion result is available.
Value
Description
0
Result Ready event output is disabled and an event will not be generated.
1
Result Ready event output is enabled and an event will be generated.
Bit 3 – STARTINV Start Conversion Event Invert Enable
Value
Description
0
Start event input source is not inverted.
1
Start event input source is inverted.
Bit 2 – FLUSHINV Flush Event Invert Enable
Value
Description
0
Flush event input source is not inverted.
1
Flush event input source is inverted.
Bit 1 – STARTEI Start Conversion Event Input Enable
Value
Description
0
A new conversion will not be triggered on any incoming event.
1
A new conversion will be triggered on any incoming event.
Bit 0 – FLUSHEI Flush Event Input Enable
Value
Description
0
A flush and new conversion will not be triggered on any incoming event.
1
A flush and new conversion will be triggered on any incoming event.
© 2020 Microchip Technology Inc.
DS60001477C-page 957
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.5
Interrupt Enable Clear
Name:
Offset:
Reset:
Property:
INTENCLR
0x04
0x00
PAC Write-Protection
This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Bit
7
6
Access
Reset
5
4
3
2
WINMON
R/W
0
1
OVERRUN
R/W
0
0
RESRDY
R/W
0
Bit 2 – WINMON Window Monitor Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Window Monitor Interrupt Enable bit, which disables the corresponding interrupt
request.
Value
Description
0
The window monitor interrupt is disabled.
1
The window monitor interrupt is enabled, and an interrupt request will be generated when the Window
Monitor interrupt flag is set.
Bit 1 – OVERRUN Overrun Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Overrun Interrupt Enable bit, which disables the corresponding interrupt request.
Value
Description
0
The Overrun interrupt is disabled.
1
The Overrun interrupt is enabled, and an interrupt request will be generated when the Overrun interrupt
flag is set.
Bit 0 – RESRDY Result Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will clear the Result Ready Interrupt Enable bit, which disables the corresponding interrupt
request.
Value
Description
0
The Result Ready interrupt is disabled.
1
The Result Ready interrupt is enabled, and an interrupt request will be generated when the Result
Ready interrupt flag is set.
© 2020 Microchip Technology Inc.
DS60001477C-page 958
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.6
Interrupt Enable Set
Name:
Offset:
Reset:
Property:
INTENSET
0x05
0x00
PAC Write-Protection
This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this
register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.
Bit
7
6
Access
Reset
5
4
3
2
WINMON
R/W
0
1
OVERRUN
R/W
0
0
RESRDY
R/W
0
Bit 2 – WINMON Window Monitor Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Window Monitor Interrupt bit, which enables the Window Monitor interrupt.
Value
Description
0
The Window Monitor interrupt is disabled.
1
The Window Monitor interrupt is enabled.
Bit 1 – OVERRUN Overrun Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Overrun Interrupt bit, which enables the Overrun interrupt.
Value
Description
0
The Overrun interrupt is disabled.
1
The Overrun interrupt is enabled.
Bit 0 – RESRDY Result Ready Interrupt Enable
Writing a '0' to this bit has no effect.
Writing a '1' to this bit will set the Result Ready Interrupt bit, which enables the Result Ready interrupt.
Value
Description
0
The Result Ready interrupt is disabled.
1
The Result Ready interrupt is enabled.
© 2020 Microchip Technology Inc.
DS60001477C-page 959
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.7
Interrupt Flag Status and Clear
Name:
Offset:
Reset:
Property:
Bit
7
INTFLAG
0x06
0x00
–
6
Access
Reset
5
4
3
2
WINMON
R/W
0
1
OVERRUN
R/W
0
0
RESRDY
R/W
0
Bit 2 – WINMON Window Monitor
This flag is cleared by writing a '1' to the flag or by reading the RESULT register.
This flag is set on the next GCLK_ADC cycle after a match with the window monitor condition, and an interrupt
request will be generated if INTENCLR/SET.WINMON is '1'.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Window Monitor interrupt flag.
Bit 1 – OVERRUN Overrun
This flag is cleared by writing a '1' to the flag.
This flag is set if RESULT is written before the previous value has been read by CPU, and an interrupt request will be
generated if INTENCLR/SET.OVERRUN=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Overrun interrupt flag.
Bit 0 – RESRDY Result Ready
This flag is cleared by writing a '1' to the flag or by reading the RESULT register.
This flag is set when the conversion result is available, and an interrupt will be generated if INTENCLR/
SET.RESRDY=1.
Writing a '0' to this bit has no effect.
Writing a '1' to this bit clears the Result Ready interrupt flag.
© 2020 Microchip Technology Inc.
DS60001477C-page 960
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.8
Sequence Status
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
SEQBUSY
R
0
SEQSTATUS
0x07
0x00
-
6
5
4
3
R
0
R
0
2
SEQSTATE[4:0]
R
0
1
0
R
0
R
0
Bit 7 – SEQBUSY Sequence busy
This bit is set when the sequence start.
This bit is clear when the last conversion in a sequence is done.
Bits 4:0 – SEQSTATE[4:0] Sequence State
These bit fields are the pointer of sequence. This value identifies the last conversion done in the sequence.
© 2020 Microchip Technology Inc.
DS60001477C-page 961
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.9
Input Control
Name:
Offset:
Reset:
Property:
Bit
15
INPUTCTRL
0x08
0x0000
PAC Write-Protection, Write-Synchronized
14
13
Access
Reset
Bit
7
6
Access
Reset
5
12
11
R/W
0
R/W
0
4
3
R/W
0
R/W
0
10
MUXNEG[4:0]
R/W
0
2
MUXPOS[4:0]
R/W
0
9
8
R/W
0
R/W
0
1
0
R/W
0
R/W
0
Bits 12:8 – MUXNEG[4:0] Negative MUX Input Selection
These bits define the MUX selection for the negative ADC input.
Value
Name
Description
0x00
AIN0
ADC AIN0 pin
0x01
AIN1
ADC AIN1 pin
0x02
AIN2
ADC AIN2 pin
0x03
AIN3
ADC AIN3 pin
0x04
AIN4
ADC AIN4 pin
0x05
AIN5
ADC AIN5 pin
0x06
AIN6
ADC AIN6 pin
0x07
AIN7
ADC AIN7 pin
0x08 Reserved
0x17
0x18
GND
Internal ground
0x19 Reserved
0x1F
Bits 4:0 – MUXPOS[4:0] Positive MUX Input Selection
These bits define the MUX selection for the positive ADC input. If the internal bandgap voltage or temperature sensor
input channel is selected, then the Sampling Time Length bit group in the Sampling Control register must be written
with a corresponding value.
Value
Name
Description
0x00
AIN0
ADC AIN0 pin
0x01
AIN1
ADC AIN1 pin
0x02
AIN2
ADC AIN2 pin
0x03
AIN3
ADC AIN3 pin
0x04
AIN4
ADC AIN4 pin
0x05
AIN5
ADC AIN5 pin
0x06
AIN6
ADC AIN6 pin
0x07
AIN7
ADC AIN7 pin
0x08
AIN8
ADC AIN8 pin
0x09
AIN9
ADC AIN9 pin
0x0A
AIN10
ADC AIN10 pin
0x0B
AIN11
ADC AIN11 pin
0x0C
AIN12
ADC AIN12 pin
0x0D
AIN13
ADC AIN13 pin
0x0E
AIN14
ADC AIN14 pin
0x0F
AIN15
ADC AIN15 pin
© 2020 Microchip Technology Inc.
DS60001477C-page 962
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
Value
0x10
0x11
0x12
0x13
0x14 0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Name
AIN16
AIN17
AIN18
AIN19
-
Description
ADC AIN16 pin
ADC AIN17 pin
ADC AIN18 pin
ADC AIN19 pin
Reserved
TEMP
BANDGAP
SCALEDCOREVCC
SCALEDIOVCC
DAC
SCALEDVBAT
OPAMP01
OPAMP2
Temperature Sensor
Bandgap Voltage
1/4 Scaled Core Supply
1/4 Scaled I/O Supply
DAC Output
1/4 Scaled VBAT Supply
OPAMP0 or OPAMP1 output
OPAMP2 output
© 2020 Microchip Technology Inc.
DS60001477C-page 963
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.10 Control C
Name:
Offset:
Reset:
Property:
Bit
15
CTRLC
0x0A
0x0000
PAC Write-Protection, Write-Synchronized
14
13
12
11
Access
Reset
Bit
7
6
Access
Reset
5
4
RESSEL[1:0]
R/W
R/W
0
0
3
CORREN
R/W
0
10
R/W
0
9
WINMODE[2:0]
R/W
0
8
R/W
0
2
FREERUN
R/W
0
1
LEFTADJ
R/W
0
0
DIFFMODE
R/W
0
Bits 10:8 – WINMODE[2:0] Window Monitor Mode
These bits enable and define the window monitor mode.
Value
Name
Description
0x0
DISABLE
No window mode (default)
0x1
MODE1
RESULT > WINLT
0x2
MODE2
RESULT < WINUT
0x3
MODE3
WINLT < RESULT < WINUT
0x4
MODE4
WINUT < RESULT < WINLT
0x5 Reserved
0x7
Bits 5:4 – RESSEL[1:0] Conversion Result Resolution
These bits define whether the ADC completes the conversion 12-, 10- or 8-bit result resolution.
Value
Name
Description
0x0
12BIT
12-bit result
0x1
16BIT
For averaging mode output
0x2
10BIT
10-bit result
0x3
8BIT
8-bit result
Bit 3 – CORREN Digital Correction Logic Enabled
Value
Description
0
Disable the digital result correction.
1
Enable the digital result correction. The ADC conversion result in the RESULT register is then
corrected for gain and offset based on the values in the GAINCORR and OFFSETCORR registers.
Conversion time will be increased by 13 cycles according to the value in the Offset Correction Value bit
group in the Offset Correction register.
Bit 2 – FREERUN Free Running Mode
Value
Description
0
The ADC run in single conversion mode.
1
The ADC is in free running mode and a new conversion will be initiated when a previous conversion
completes.
Bit 1 – LEFTADJ Left-Adjusted Result
Value
Description
0
The ADC conversion result is right-adjusted in the RESULT register.
1
The ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result
will be present in the upper part of the result register. Writing this bit to zero (default) will right-adjust
the value in the RESULT register.
© 2020 Microchip Technology Inc.
DS60001477C-page 964
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
Bit 0 – DIFFMODE Differential Mode
Value
Description
0
The ADC is running in singled-ended mode.
1
The ADC is running in differential mode. In this mode, the voltage difference between the MUXPOS
and MUXNEG inputs will be converted by the ADC.
© 2020 Microchip Technology Inc.
DS60001477C-page 965
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.11 Average Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
AVGCTRL
0x0C
0x00
PAC Write-Protection, Write-Synchronized
6
R/W
0
5
ADJRES[2:0]
R/W
0
4
3
R/W
0
R/W
0
2
1
SAMPLENUM[3:0]
R/W
R/W
0
0
0
R/W
0
Bits 6:4 – ADJRES[2:0] Adjusting Result / Division Coefficient
These bits define the division coefficient in 2n steps.
Bits 3:0 – SAMPLENUM[3:0] Number of Samples to be Collected
These bits define how many samples are added together. The result will be available in the Result register
(RESULT). Note: if the result width increases, CTRLC.RESSEL must be changed.
Value
Description
0x0
1 sample
0x1
2 samples
0x2
4 samples
0x3
8 samples
0x4
16 samples
0x5
32 samples
0x6
64 samples
0x7
128 samples
0x8
256 samples
0x9
512 samples
0xA
1024 samples
0xB Reserved
0xF
© 2020 Microchip Technology Inc.
DS60001477C-page 966
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.12 Sampling Time Control
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
7
OFFCOMP
R/W
0
SAMPCTRL
0x0D
0x00
PAC Write-Protection, Write-Synchronized
6
5
4
R/W
0
R/W
0
3
2
SAMPLEN[5:0]
R/W
R/W
0
0
1
0
R/W
0
R/W
0
Bit 7 – OFFCOMP Comparator Offset Compensation Enable
Setting this bit enables the offset compensation for each sampling period to ensure low offset and immunity to
temperature or voltage drift. This compensation increases the sampling time by three clock cycles.
This bit must be set to zero to validate the SAMPLEN value. It’s not possible to use OFFCOMP=1 and SAMPLEN>0.
Bits 5:0 – SAMPLEN[5:0] Sampling Time Length
These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus
controlling the ADC input impedance. Sampling time is set according to the equation:
Sampling time = SAMPLEN+1 ⋅ CLKADC
© 2020 Microchip Technology Inc.
DS60001477C-page 967
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.13 Window Monitor Lower Threshold
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
WINLT
0x0E [ID-0000120e]
0x0000
PAC Write-Protection, Write-Synchronized
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
WINLT[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
WINLT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WINLT[15:0] Window Lower Threshold
If the window monitor is enabled, these bits define the lower threshold value.
© 2020 Microchip Technology Inc.
DS60001477C-page 968
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.14 Window Monitor Upper Threshold
Name:
Offset:
Reset:
Property:
Bit
Access
Reset
Bit
WINUT
0x10
0x0000
PAV Write-Protection, Write-Synchronized
15
14
13
R/W
0
R/W
0
R/W
0
7
6
5
12
11
WINUT[15:8]
R/W
R/W
0
0
4
10
9
8
R/W
0
R/W
0
R/W
0
3
2
1
0
R/W
0
R/W
0
R/W
0
R/W
0
WINUT[7:0]
Access
Reset
R/W
0
R/W
0
R/W
0
R/W
0
Bits 15:0 – WINUT[15:0] Window Upper Threshold
If the window monitor is enabled, these bits define the upper threshold value.
© 2020 Microchip Technology Inc.
DS60001477C-page 969
SAM L21 Family Data Sheet
ADC – Analog-to-Digital Converter
42.8.15 Gain Correction
Name:
Offset:
Reset:
Property:
Bit
15
GAINCORR
0x12
0x0000
PAC Write-Protection, Write-Synchronized
14
13
Access
Reset
Bit
Access
Reset
12
11
R/W
0
7
6
5
R/W
0
R/W
0
R/W
0
4
3
GAINCORR[7:0]
R/W
R/W
0
0
10
9
GAINCORR[11:8]
R/W
R/W
0
0
8
R/W
0
2
1
0
R/W
0
R/W
0
R/W
0
Bits 11:0 – GAINCORR[11:0] Gain Correction Value
If CTRLC.CORREN=1, these bits define how the ADC conversion result is compensated for gain error before being
written to the result register. The gain correction is a fractional value, a 1-bit integer plus an 11-bit fraction, and
therefore ½ IOBUS without jumping in an interrupt handler (Cortex
M0+ register PRIMASK=1). The wake-up time is measured between the edge of the wake-up input signal and the
edge of the GPIO pin.
For Backup, the exit of mode is done through RTC wake-up. The wake-up time is measured between the toggle of
the RTC pin and the set of the IO done by the first executed instructions after reset.
For OFF mode, the exit of mode is done through reset pin, the time is measured between the rising edge of the
RESETN signal and the set of the IO done by the first executed instructions after reset.
Table 46-9. Wake-Up Timing
46.8
Sleep Mode Condition
Typ. Unit
IDLE
PL2 or PL0
1.2
µs
STANDBY
PL0
PM.PLSEL.PLDIS=1 (see errata 13674 for revision A)
PDCFG default
5.1
µs
PD012 forced active
PDCFG=3
2.1
PL2
Voltage scaling at default values: SUPC>VREG.VSVSTEP=0 SUPC->VREG.VSPER=0
PDCFG default
76
PD012 forced active
PDCFG=3
75
PL2 Voltage scaling at fastest setting: SUPC>VREG.VSVSTEP=15 SUPC->VREG.VSPER=0
PDCFG default
16
µs
PD012 forced active
PDCFG=3
15
µs
BACKUP
90
µs
OFF
2200 µs
µs
I/O Pin Characteristics
There are three different pin types with three different speeds: Backup, Normal, and High Sink(3,4).
© 2020 Microchip Technology Inc.
DS60001477C-page 1047
SAM L21 Family Data Sheet
Electrical Characteristics
The Drive Strength bit is located in the Pin Configuration register of the PORT (PORT.PINCFG.DRVSTR).
Table 46-10. I/O Pins Common Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
VIL
Input low-level voltage
VDD=1.62V-2.7V
-
-
0.25*VDD
V
VDD=2.7V-3.63V
-
-
0.3*VDD
VDD=1.62V-2.7V
0.7*VDD
-
-
VDD=2.7V-3.63V
0.55*VDD
-
-
VIH
Input high-level voltage
VOL
Output low-level voltage
VDD>1.6V, IOL max
-
0.1*VDD
0.2*VDD
VOH
Output high-level voltage
VDD>1.6V, IOH max
0.8*VDD
0.9*VDD
-
RPULL
Pull-up - Pull-down resistance
All pins except PA24, PA25
20
40
60
PA24, PA25(1)
50
100
150
Pull-up resistors disabled
-1
+/-0.015
1
ILEAK
Input leakage current
kΩ
µA
Table 46-11. I/O Pins Maximum Output Current
Symbol Parameter
Conditions
Backup Pins in Backup and
Backup
Normal
Mode(4)
Pins(4)
High Sink
Pins(3)
DRVSTR=0
IOL
IOH
Maximum Output lowlevel current
Backup and
Normal
Pins(4)
High Sink
Pins(3)
Units
mA
DRVSTR=1
VDD=1.62V-3V 0.005
1
2
2
4
VDD=3V-3.63V 0.008
2.5
6
6
12
Maximum Output high- VDD=1.62V-3V 0.005
level current
VDD=3V-3.63V 0.008
0.7
1.5
1.5
3
2
5
5
10
Backup and
Normal
Pins(4)
High Sink
Pins(3)
Units
ns
Table 46-12. I/O Pins Dynamic Characteristics(1)
Symbol Parameter
Conditions
Backup Pins in
Backup Mode(4)
Backup and
Normal
Pins(4)
High Sink
Pins(3)
DRVSTR=0
DRVSTR=1
tRISE
Maximum Rise
time
VDD=3.3V,
load=20pF
2000
13
6
6
4.5
tFALL
Maximum Fall
time
VDD=3.3V,
load=20pF
2000
12
7
7
4.5
The pins with I2C alternative mode available are compliant(2) with I2C norms. All I2C pins support Standard mode
(Sm), Fast mode (Fm), Fast plus mode (Fm+), and High speed mode (Hs, up to 3.4MHz). The available I2C pins are
listed in the I/O Multiplexing section.
© 2020 Microchip Technology Inc.
DS60001477C-page 1048
SAM L21 Family Data Sheet
Electrical Characteristics
Note:
1. These values are based on simulation. They are not covered by production test limits or characterization.
2. The pins PA12, PA13, PB12, PB13, PB16, PB17, PB30, PB31 are limited on output low-level current in I2C
Standard mode (Sm) and Fast mode (Fm). The limitation is 2.5mA instead of 3mA for VOL=0.4V, and 3mA
instead of 6mA for VOL=0.6V.
3. The following pins are High Sink pins and have different properties than normal pins:
PA08, PA09, PA16, PA17, PA22, PA23, PA27, PA31.
4. The following pins are Backup pins and have different properties than normal pins:
PA00, PA01, PB00, PB01, PB02, PB03.
46.9
Injection Current
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Table 46-13. Injection Current(1,2)
Symbol
Description
min
max
Unit
(3)
IO pin injection current
-1
+1
mA
Iinj2 (4)
IO pin injection current
-15
+15
mA
Iinjtotal
Sum of IO pins injection current
-45
+45
mA
Iinj1
Note:
1. Injecting current may have an effect on the accuracy of Analog blocks
2. Injecting current on Backup IOs is not allowed
3. Conditions for Vpin: Vpin < GND-0.6V or 3.6V2.4V, VCC=3.3V
Max.85°C Typ.25°C
fs=10ksps, CCTRL=0x0,
VREF2.4V, VCC=3.3V
-
297
395
fs=10ksps, CCTRL=0x0,
VREF30°C
-5
-
5
°C
Note:
1. These values are based on characterization.
2. Measuring conditions as in Table Configuration for Temperature Measurements.
Table 46-34. Configuration for Temperature Measurements
Parameter
Configuration
Supply voltages
VDDIN = VDDIO = VDDANA = 3.3V
ADC Clock conversion rate
100kSa/s
Offset compensation
ADC.SAMPCTRL.OFFCOMP=0
Fext
3.2MHz
FADC
Fext/2 = 1.6MHz
Sampling time
(63+1)/FADC = 40µs
ADC voltage reference
1.0V internal reference (INTREF,
SUPC.VREF.SEL=1V0)
ADC input
Temperature sensor
(ADC.INPUTCTRL.MUXPOS=TEMP)
46.10.10 OPAMP
Table 46-35. Operating Conditions
Symbol
Parameters
Conditions
Min.
Typ.
Max.
Unit
VCC
Power Supply
All power modes
1.6
3
3.63
V
Vin
Input voltage range
0
-
Vcc
V
Vout
Output voltage range
0.15
-
Vcc-0.15
V
Cload
Maximum capacitance load
-
-
50
pF
Rload (1)
Minimum resistive load
Output Range[0.15V;Vcc-0.15V]
3.5
-
-
kΩ
Output Range[0.3V;Vcc-0.3V]
0.5
-
-
Output Range[0.15V;Vcc-0.15V]
-
-
1
Output Range[0.3V;Vcc-0.3V]
-
-
6.9
-
5.5
-
Iload(1)
R
DC output current load
Each resistor value in resistor Ladder
Note: 1. These values are based on simulation. They are not covered by production test limits or characterization.
© 2020 Microchip Technology Inc.
DS60001477C-page 1062
mA
kΩ
SAM L21 Family Data Sheet
Electrical Characteristics
Table 46-36. Power Consumption(1)
Symbol Parameters
Conditions
Ta
IDD
Mode 3,VCC =3.3V
Max 85°C Typ 25°C -
Mode 2,VCC =3.3V
DC supply current (Voltage Doubler
OFF)
Voltage Doubler consumption
Min. Typ. Max. Unit
184
312
-
72
127
Mode 1,VCC =3.3V
-
21
33
Mode 0 ,VCC =3.3V
-
6
9
VCC =3.3V
-
0,69 1,5
uA
Note: 1. These values are based on characterization.
Table 46-37. Static Characteristics in 1X Gain(1)
Symbol
Parameters
Conditions
Min.
Typ.
Max.
Unit
G0
Open loop gain
Mode 3
-
114.5
-
dB
Mode 2
-
117.6
-
Mode 1
-
116.8
-
Mode 0
-
108.5
-
Mode 3
-
7.1
-
Mode 2
-
2.8
-
Mode 1
-
0.85
-
Mode 0
-
0.2
-
Mode 3
-
71.5
-
Mode 2
-
64
-
Mode 1
-
56
-
Mode 0
-
52
-
Mode 3
-
1.3
-
Mode 2
-
3.3
-
Mode 1
-
13
-
Mode 0
-
52
-
Mode 3
-
100
-
Mode 2
-
-
-
Mode 1
-
-
-
Mode 0
-
-
-
Mode 3
-
2.7
-
Mode 2
-
6.35
-
Mode 1
-
21.5
-
Mode 0
-
88.5
-
-
-
+-3.5
GBW
фm
Tr1
∆Tr1
Tstart
Oe
Gain Bandwidth
Phase margin
Response Time at 240µV (X1 gain)
Response Time Variation for 10mV
Start-up time (Enable to Ready), (Voltage Doubler OFF)
Input Offset Voltage
© 2020 Microchip Technology Inc.
MHz
deg
µs
ns
µs
mV
DS60001477C-page 1063
SAM L21 Family Data Sheet
Electrical Characteristics
...........continued
Symbol
Parameters
Conditions
Min.
Typ.
Max.
Unit
SR
Slew rate
Mode 3
-2.8
-
2.6
V/µs
Mode 2
-1.2
-
1.1
Mode 1
-0.3
-
0.3
Mode 0
-0.09
-
0.07
Mode 3
-
83
-
Mode 2
-
84
-
Mode 1
-
84
-
Mode 0
-
83
-
Mode 3
-
76
-
Mode 2
-
76
-
Mode 1
-
76
-
Mode 0
-
75
-
Mode 3
-
7.9
-
Mode 2
-
8.3
-
Mode 1
-
9.9
-
Mode 0
-
12.7
-
Mode 3
-
18.2
-
Mode 2
-
22.8
-
Mode 1
-
36.7
-
Mode 0
-
44.4
-
CMRR
PSRR
1X gain
1X gain
Integrated Noise, BW=[0.1Hz-10kHz], x1 gain - VOUT=1V
Integrated Noise, BW=[0.1Hz-1MHz], x1 gain - VOUT=1V
dB
dB
µVRMS
µVRMS
Note: 1.These values are based on simulation. They are not covered by production test limits or characterization.
Table 46-38. PGA Electrical Characteristics(1)
Symbol
THD
Parameters
Conditions
Min.
Typ.
Max.
Unit
Gain accuracy
16X Gain
-
-
-1.43
%
4X Gain
-
-
+-0.4
1X Gain
-
-
+/-0.25
16X Gain
-
-77
-
4X Gain
-
-72.8
-
1X Gain
-
-82.6
-
Mode 3
-
147
-
Mode 2
-
147
-
Mode 1
-
162
-
Mode 0
-
191
-
Total Harmonic Distortion @ 10kHz - mode 3
Integrated Noise, BW=[0.1Hz-10 kHz], 16X gain - VOUT=1V
© 2020 Microchip Technology Inc.
dB
µVrms
DS60001477C-page 1064
SAM L21 Family Data Sheet
Electrical Characteristics
...........continued
Symbol
Parameters
Conditions
Min.
Typ.
Max.
Unit
Integrated Noise, BW=[0.1Hz-1MHz], 16X gain - VOUT=1V
Mode 3
-
262
-
µVrms
Mode 2
-
247
-
Mode 1
-
235
-
Mode 0
-
235
-
Note: 1.These values are based on simulation. They are not covered by production test limits or characterization.
46.11
NVM Characteristics
Table 46-39. NVM Max Speed Characteristics
Conditions
PL0 (-40/85°C)
PL2 (-40/85°C)
CPU Fmax (MHz)
0WS
1WS
2WS
3WS
VDDIN>1.6 V
6
12
12
12
VDDIN>2.7 V
7.5
12
12
12
VDDIN>1.6 V
14
28
42
48
VDDIN>2.7 V
24
45
48
48
Table 46-40. NVM Timing Characteristics
Symbol
Timings
Max
Units
tFPP
Page Write(1)
2.5
ms
tFRE
erase(1)
Row
6
Note:
1. These values are based on simulation. They are not covered by production test limits or characterization.
2. For this Flash technology, a maximum number of 8 consecutive writes is allowed per row. Once this number is
reached, a row erase is mandatory.
Table 46-41. NVM Reliability Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
RetNVM25k
Retention after up to 25k
Average ambient 55°C
10
50
-
Years
RetNVM2.5k
Retention after up to 2.5k
Average ambient 55°C
20
100
-
Years
RetNVM100
Retention after up to 100
Average ambient 55°C
25
>100
-
Years
-40°C < Ta < 85°C
25K
100K
-
Cycles
CycNVM
Cycling
Endurance(1)
Note: 1. An endurance cycle is a write and an erase operation.
Table 46-42. EEPROM Emulation(1) Reliability Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
RetEE100k
Retention after up to 100k
Average ambient 55°C
10
50
-
Years
RetEE10k
Retention after up to 10k
Average ambient 55°C
20
100
-
Years
CycEE
Cycling Endurance(2)
-40°C < Ta < 85°C
100K
400K
-
Cycles
© 2020 Microchip Technology Inc.
DS60001477C-page 1065
SAM L21 Family Data Sheet
Electrical Characteristics
Note:
(1) The EEPROM emulation is a software emulation described in the App note AT03265.
(2) An endurance cycle is a write and an erase operation.
Table 46-43. Flash Erase and Programming Current
46.12
Symbol
Parameter
Typ.
Units
IDDNVM
Maximum current (peak)
during whole programming
or erase operation
10
mA
Oscillators Characteristics
46.12.1 Crystal Oscillator (XOSC) Characteristics
Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table 46-44. Digital Clock Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Units
FXIN
XIN clock frequency
-
-
24
MHz
DCXIN
XIN clock duty cycle
40
50
60
%
Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT as shown in the figure Oscillator Connection.
Figure 46-3. Oscillator Connection
DEVICE
XIN
Crystal
CLEXT
LM
RM
CSTRAY
CSHUNT
CM
XOUT
CLEXT
The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table.
The exact value of CL can be found in the crystal data sheet. The capacitance of the external capacitors (CLEXT) can
then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification.
CXIN = XOSC XIN pin data sheet specification.
CXOUT = XOSC XOUT pin data sheet specification.
CLEXT = Required external crystal load capacitor.
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T = 113 μm).
© 2020 Microchip Technology Inc.
DS60001477C-page 1066
SAM L21 Family Data Sheet
Electrical Characteristics
Table 46-45. Multi Crystal Oscillator Electrical Characteristics
Symbol
Parameter
FOUT
Crystal oscillator frequency
ESR
Crystal Equivalent Series Resistance - SF=3
CXIN
Conditions
Min.
Typ.
Max.
Units
0.4
-
32
MHz
F=0.4MHz, CL=100pF XOSC, GAIN=0
-
-
5.6K
Ω
F=2MHz, CL=20pF XOSC,GAIN=0
-
-
416
F=4MHz, CL=20pF XOSC, GAIN=1
-
-
243
F=8MHz, CL=20pF XOSC, GAIN=2
-
-
138
F=16MHz, CL=20pF XOSC, GAIN=3
-
-
66
F=32MHz, CL=20pF XOSC, GAIN=4
-
-
56
-
5.8
-
-
3.2
-
F=2MHz, CL=20pF XOSC, GAIN=0
-
14k
48k
F=4MHz, CL=20pF XOSC, GAIN=1
-
6.8k
19.5k
F=8MHz, CL=20pF XOSC, GAIN=2
-
5.6k
13k
F=16MHz, CL=20pF XOSC, GAIN=3
-
6.8k
14.5k
F=32MHz, CL=20pF XOSC, GAIN=4
-
5.3K
9.6k
Parasitic load capacitor
CXOUT
TSTART
Startup time
pF
Cycles
Note: (1) These values are based on characterization.
Table 46-46. Power Consumption(1)
Symbol Parameter
Conditions
IDD
F=2MHz - CL=20pF
XOSC,GAIN=0, VCC=3.3V
AGC=OFF Max 85°C Typ 25°C
AGC=ON
-
89
133
82
130
F=4MHz - CL=20pF
XOSC,GAIN=1, VCC=3.3V
AGC=OFF
-
140
194
AGC=ON
-
102
156
F=8MHz - CL=20pF
XOSC,GAIN=2, VCC=3.3V
AGC=OFF
-
243
313
AGC=ON
-
166
232
F=16MHz - CL=20pF
XOSC,GAIN=3, VCC=3.3V
AGC=OFF
-
493
605
AGC=ON
-
293
393
F=32MHz - CL=20pF
XOSC,GAIN=4, VCC=3.3V
AGC=OFF
-
1467 1777
AGC=ON
-
651
Current
consumption
Ta
Min. Typ. Max. Units
µA
1045
Note: (1) These values are based on characterization.
46.12.2 External 32KHz Crystal Oscillator (XOSC32K) Characteristics
Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 46-47. Digital Clock Characteristics(1)
Symbol
Parameter
fCPXIN32
XIN32 clock frequency
© 2020 Microchip Technology Inc.
Min.
Typ.
Max.
Units
32.768
1000
kHz
DS60001477C-page 1067
SAM L21 Family Data Sheet
Electrical Characteristics
...........continued
Symbol
Parameter
Min.
Typ.
Max.
Units
DCXIN
XIN32 clock duty cycle
40
50
60
%
Note: 1. These values are based on characterization.
Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT as shown in the figure Oscillator Connection.
Figure 46-4. Oscillator Crystal Connection
DEVICE
XIN32
Crystal
CLEXT
LM
RM
CSTRAY
CSHUNT
CM
XOUT32
CLEXT
The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table.
The exact value of CL can be found in the crystal data sheet. The capacitance of the external capacitors (CLEXT) can
then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification.
CXIN = XOSC XIN pin data sheet specification.
CXOUT = XOSC XOUT pin data sheet specification.
CLEXT = Required external crystal load capacitor.
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
Table 46-48. 32KHz Crystal Oscillator Electrical Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOUT
Crystal oscillator frequency
-
-
32.768
-
kHz
CL
Crystal load capacitance
-
7
9
12.5
pF
CSHUNT
Crystal shunt capacitance
-
0.6
-
2
pF
CM
Motional capacitance
-
0.6
-
3
fF
ESR
Crystal Equivalent Series Resistance - SF=3
f=32.768kHz,
CL=12.5pF
-
50
70
kΩ
CXIN32k
Parasitic load capacitor(2)
-
-
2.31
-
pF
-
-
2.53
-
CXOUT32k
tSTARTUP
Startup time
f=32.768kHz,
CL=12.5pF
-
25k
82k
Cycles
Pon
Drive Level (1)
-
-
-
0.1
µW
© 2020 Microchip Technology Inc.
DS60001477C-page 1068
SAM L21 Family Data Sheet
Electrical Characteristics
Note:
1. These values are based on simulation. They are not covered by production test limits or characterization.
2. For device revision A, see Erratum 13425.
Table 46-49. Power Consumption(1)
Symbol
Parameter
Conditions
Ta
Min.
Typ.
Max.
Units
IDD
Current consumption
VCC=3.3V
Max 85°C
Typ 25°C
-
311
723
nA
Note: (1) These values are based on characterization.
46.12.3 32.768kHz Internal Oscillator (OSC32K) Characteristics
Table 46-50. 32KHz RC Oscillator Electrical Characteristics(1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOUT
Output frequency
at 25°C, at VDDIO=3.3V
32.572
32.768
33.044
kHz
at 25°C, over [1.62, 3.63]V
31.425
32.768
33.603
kHz
over[-40,+85]°C, over [1.62, 3.63]V
28.581
32.768
34.716
kHz
IOSC32k
Current consumption
-
0.54
µA
TSTARTUP
Startup time
-
1
2
cycles
Duty
Duty Cycle
-
50
-
%
Note: 1. These values are based on characterization.
Table 46-51. Power Consumption(1)
Symbol
Parameter
Conditions
Ta
Min.
Typ.
Max.
Units
IDD
Current consumption
VCC=3.3V
Max 85°C
Typ 25°C
-
0.54
1.10
µA
Note: (1) These values are based on characterization.
46.12.4 Internal Ultra Low Power 32KHz RC Oscillator (OSCULP32K) Characteristics
Table 46-52. Ultra Low Power Internal 32KHz RC Oscillator Electrical Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOUT
Output frequency
at 25°C, at VDDIO=3.3V
31.775
32.768
34.033
kHz
at 25°C, over [1.62, 3.63]V
31.848
32.768
34.202
kHz
over[-40,+85]°C, over [1.62, 3.63]V
26.296
32.768
38.384
kHz
-
50
-
%
Duty
Duty Cycle
46.12.5 Digital Frequency Locked Loop (DFLL48M) Characteristics
Table 46-53. DFLL48M Characteristics - Open Loop Mode(1,2)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOpenOUT
Output frequency
DFLLVAL.COARSE=DFLL48M_COARSE_CAL
DFLLVAL.FINE=512
46.6
47.8
49
MHz
© 2020 Microchip Technology Inc.
DS60001477C-page 1069
SAM L21 Family Data Sheet
Electrical Characteristics
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
TOpenSTARTUP
Startup time
DFLLVAL.COARSE=DFLL48M_COARSE_CAL
DFLLVAL.FINE=512
-
8.3
9.1
µs
FOUT within 90% of final value
Note:
1. DFLL48 in open loop can be used only with LDO regulator.
2. These values are based on characterization.
Table 46-54. DFLL48M Characteristics - Closed Loop Mode
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FCloseOUT
Average Output frequency
fREF = XTAL, 32.768kHz, 100ppm
47.963
47.972
47.981
MHz
732
32768
33000
Hz
-
-
0.51
ns
200
700
µs
DFLLMUL=1464
FREF(2,3)
Input reference frequency
FCloseJitter
(1)
Period Jitter
fREF = XTAL, 32.768kHz, 100ppm
DFLLMUL=1464
TLock(1)
Lock time
FREF = XTAL, 32.768kHz, 100ppm
DFLLMUL=1464
DFLLVAL.COARSE=DFLL48M_COARSE_CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
Note:
1. These values are based on characterization.
2. To insure that the device stays within the maximum allowed clock frequency, any reference clock for the DFLL
in close loop must be within a 2% error accuracy.
3. These values are based on simulation. They are not covered by production test limits or characterization.
Table 46-55. DFLL48M Power Consumption(1)
Symbol Parameter
Conditions
Ta
Min. Typ. Max. Units
IDD
Power consumption Open Loop
DFLLVAL.COARSE=DFLL48M_COARSE_CAL
IDD
Power consumption Closed Loop
FREF = 32.768kHz, VCC=3.3V
Max.85°C Typ.25°C
-
286
-
µA
362
-
µA
Note:
1. These values are based on characterization.
© 2020 Microchip Technology Inc.
DS60001477C-page 1070
SAM L21 Family Data Sheet
Electrical Characteristics
46.12.6 16MHz RC Oscillator (OSC16M) Characteristics
Table 46-56. Multi RC Oscillator Electrical Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOUT
Output frequency
VCC=3.3V, T=25°C
3.953
4
4.062
MHz
7.877
8
8.112
11.857
12
12.139
15.754
16
16.235
TempDrift
Freq vs. temperature drift
-4
4
SupplyDrift
Freq vs. supply drift
-2
2
TWUP(2)
Wake up time - 1st clock edge after enable
TSTARTUP(2)
Duty(1)
Startup time
Duty Cycle
%
FOUT = 4MHz
-
0.12
0.27
FOUT = 8MHz
-
0.12
0.25
FOUT = 12MHz
-
0.12
0.27
FOUT = 16MHz
-
0.12
0.25
FOUT = 4MHz
-
1.2
2.9
FOUT = 8MHz
-
1.3
2.6
FOUT = 12MHz
-
1.3
2.8
FOUT = 16MHz
-
1.4
3.1
-
45
50
55
µs
µs
%
Note:
1. These values are based on simulation. They are not covered by production test limits or characterization.
2. These values are based on characterization.
Table 46-57. Power Consumption(1)
Symbol
Parameter
Conditions
Ta
Min.
Typ.
Max.
Units
IDD
Current
consumption
Fout=4MHz,
VCC=3.3V
Max.85°C
Typ.25°C
-
64
96
µA
Fout=8MHz,
VCC=3.3V
-
91
122
Fout=12MHz,
VCC=3.3V
-
114
144
Fout=16MHz,
VCC=3.3V
-
141
169
Note:
1. These values are based on characterization.
46.12.7 Digital Phase Lock Loop (DPLL) Characteristics
Table 46-58. Fractional Digital Phase Lock Loop Characteristics
Symbol
Parameter
FIN
Input Clock Frequency
© 2020 Microchip Technology Inc.
Conditions
Min.
Typ.
Max.
Units
32
-
2000
kHz
DS60001477C-page 1071
SAM L21 Family Data Sheet
Electrical Characteristics
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOUT
Output frequency
PL0
48
-
48
MHz
PL2
48
-
96
MHz
PL0, FIN=32kHz @ FOUT=48MHz
-
1.9
5.0
%
PL2, FIN=32kHz @ FOUT=48MHz
-
1.9
4.0
PL2, FIN=32kHz @ FOUT=96MHz
-
3.3
7.0
PL0, FIN=2MHz @ FOUT=48MHz
-
2.0
8.0
PL2, FIN=2MHz @ FOUT=48MHz
-
2.0
4.0
PL2, FIN=2MHz @ FOUT=96MHz
-
4.2
7.0
After startup, time to get lock signal,
FIN=32kHz @ FOUT=96MHz
-
1
2
ms
After startup, time to get lock signal,
FIN=2MHz @ FOUT=96MHz
-
25
35
µs
40
50
60
%
JP(2)
TLOCK(2)
Duty(1)
Period Jitter
Lock Time
Duty Cycle
Note:
1. These values are based on simulation. They are not covered by production test limits or characterization.
2. These values are based on characterization.
Table 46-59. Power Consumption(1)
Symbol
Parameter
Conditions
TA
Min.
Typ.
Max.
Units
IDD
Current Consumption
Ck=48MHz (PL0)
Max.85°C
Typ.25°C
-
454
548
µA
-
934
1052
Ck=96MHz (PL2)
Note:
1. These values are based on characterization.
46.13
Timing Characteristics
46.13.1 External Reset Pin
Table 46-60. External Reset Characteristics(1)
Symbol
Parameter
tEXT
Minimum reset pulse width
© 2020 Microchip Technology Inc.
Conditions
Min.
Typ.
Max.
Units
1
-
-
µs
DS60001477C-page 1072
SAM L21 Family Data Sheet
Electrical Characteristics
46.13.2 SERCOM in SPI Mode in PL0
Table 46-61. SPI Timing Characteristics and Requirements(1)
Symbol
Parameter
Conditions
Min.
Typ.
tSCK
SCK period
Master, VDD>2.70V
141
153
Master, VDD>1.62V
147
159
Master
-
0.5*tSCK
-
Master
-
0.25*tSCK
-
0.25*tSCK
-
tSCKW
SCK high/low width
time(2)
tSCKR
SCK rise
tSCKF
SCK fall time(2)
Master
-
tMIS
MISO setup to SCK
Master, VDD>2.70V
141
Master, VDD>1.62V
147
Master, VDD>2.70V
0
Master, VDD>1.62V
0
tMIH
tMOS
tMOH
tSSCK
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
Slave SCK Period
Max.
ns
Master, VDD>2.70V
30
Master, VDD>1.62V
30.6
Master, VDD>2.70V
-9
Master, VDD>1.62V
-8.5
Slave, VDD>2.70V
220
250
Slave, VDD>1.62V
230
250
-
tSSCKW
SCK high/low width
Slave
-
0.5*tSCK
-
tSSCKR
SCK rise time(2)
Slave
-
0.25*tSCK
-
tSSCKF
SCK fall time(2)
Slave
-
0.25*tSCK
-
tSIS
MOSI setup to SCK
Slave, VDD>2.70V
42
-
-
Slave, VDD>1.62V
42
Slave, VDD>2.70V
0
Slave, VDD>1.62V
0
tSIH
tSSS
MOSI hold after SCK
SS setup to SCK
Slave
Units
PRELOADEN=1
PRELOADEN=0
tSSH
SS hold after SCK
Slave
tSOS
MISO setup before SCK
Slave, VDD>2.70V
109
Slave, VDD>1.62V
115
tSOH
tSOSS
tSOSH
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
© 2020 Microchip Technology Inc.
Slave, VDD>2.70V
17.3
Slave, VDD>1.62V
17.3
Slave, VDD>2.70V
95
Slave, VDD>1.62V
102
Slave, VDD>2.70V
10.2
Slave, VDD>1.62V
10.2
ns
DS60001477C-page 1073
SAM L21 Family Data Sheet
Electrical Characteristics
Note: 1. These values are based on simulation. They are not covered by production test limits or characterization.
Figure 46-5. SPI Timing Requirements in Master Mode
Figure 46-6. SPI Timing Requirements in Slave Mode
Maximum SPI Frequency
• Master Mode
fSCKmax = 1/2*(tMIS + tvalid), where tvalid is the slave time response to output data after detecting an SCK edge.
For a non-volatile memory with tvalid = 12ns Max, fSPCKMax = 3.7MHz @ VDDIO > 2.7V
• Slave Mode
fSCKmax = 1/2*(tSOV + tsu), where tsu is the setup time from the master before sampling data. With a perfect
master (tsu=0), fSPCKMax = 6MHz @ VDDIO > 2.7V
© 2020 Microchip Technology Inc.
DS60001477C-page 1074
SAM L21 Family Data Sheet
Electrical Characteristics
46.13.3 SERCOM in SPI Mode in PL2
Table 46-62. SPI Timing Characteristics and Requirements(1)
Symbol
Parameter
Conditions
Min.
Typ.
tSCK
SCK period
Master, VDD>2.70V
41.1
53
Master, VDD>1.62V
52.6
65
Master
-
0.5*tSCK
-
Master
-
0.25*tSCK
-
0.25*tSCK
-
tSCKW
SCK high/low width
time(2)
tSCKR
SCK rise
tSCKF
SCK fall time(2)
Master
-
tMIS
MISO setup to SCK
Master, VDD>2.70V
41.1
Master, VDD>1.62V
52.6
Master, VDD>2.70V
0
Master, VDD>1.62V
0
tMIH
tMOS
tMOH
tSSCK
tSSCKW
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
Slave SCK Period
SCK high/low width
time(2)
Max.
ns
Master, VDD>2.70V
8.5
Master, VDD>1.62V
13.1
Master, VDD>2.70V
0.5
Master, VDD>1.62V
1
Slave, VDD>2.70V
74
90
-
Slave, VDD>1.62V
95
110
-
Slave
-
0.5*tSCK
-
Slave
-
0.25*tSCK
-
tSSCKR
SCK rise
tSSCKF
SCK fall time(2)
Slave
-
0.25*tSCK
-
tSIS
MOSI setup to SCK
Slave, VDD>2.70V
10.3
-
-
Slave, VDD>1.62V
11.8
-
-
Slave, VDD>2.70V
0
-
-
Slave, VDD>1.62V
0
-
-
tSIH
tSSS
MOSI hold after SCK
SS setup to SCK
Slave
Units
PRELOADEN=1
PRELOADEN=0
tSSH
SS hold after SCK
Slave
tSOS
MISO setup before SCK
Slave, VDD>2.70V
-
-
36.9
Slave, VDD>1.62V
-
-
47.5
Slave, VDD>2.70V
11.5
-
-
Slave, VDD>1.62V
11.5
-
-
Slave, VDD>2.70V
-
-
31
Slave, VDD>1.62V
-
-
41.3
Slave, VDD>2.70V
6.2
-
-
Slave, VDD>1.62V
6.2
-
-
tSOH
tSOSS
tSOSH
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
© 2020 Microchip Technology Inc.
ns
DS60001477C-page 1075
SAM L21 Family Data Sheet
Electrical Characteristics
Note: 1. These values are based on simulation. They are not covered by production test limits or characterization.
Figure 46-7. SPI Timing Requirements in Master Mode
Figure 46-8. SPI Timing Requirements in Slave Mode
Maximum SPI Frequency
• Master Mode
fSCKmax = 1/2*(tMIS + tvalid), where tvalid is the slave time response to output data after detecting an SCK edge.
For a non-volatile memory with tvalid = 12ns Max, fSPCKMax = 9.8MHz @ VDDIO > 2.7V
• Slave Mode
fSCKmax = 1/2*(tSOV + tsu), where tsu is the setup time from the master before sampling data. With a perfect
master (tsu=0), fSPCKMax = 16.3MHz @ VDDIO > 2.7V
46.14
USB Characteristics
The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to
these buffers can be found within the USB 2.0 electrical specifications.
The USB interface is USB-IF certified:
• TID 40001709 - Peripheral Silicon > Low/Full Speed > Silicon Building Blocks
• TID 120000459 - Embedded Hosts > Full Speed
Electrical configuration required to be USB-compliant:
• the performance level must be PL2 only
• the CPU frequency must be higher 8MHz when USB is active (No constraint for USB suspend mode)
• the operating voltages must be 3.3V (Min. 3.0V, Max. 3.6V).
• the GCLK_USB frequency accuracy source must be less than:
– in USB device mode, 48MHz +/-0.25%
© 2020 Microchip Technology Inc.
DS60001477C-page 1076
SAM L21 Family Data Sheet
Electrical Characteristics
– in USB host mode, 48MHz +/-0.05%
Table 46-63. GCLK_USB Clock Setup Recommendations
Clock setup
DFLL48M
FDPLL
USB Device
USB Host
Open loop
No
No
Close loop, Ref. internal OSC source
No
No
Close loop, Ref. external XOSC source
Yes
No
Close loop, Ref. SOF (USB recovery mode)(1)
Yes(2)
N/A
internal OSC (32K, 8M…)
No
No
external OSC (1MHz)
Yes(3)
Yes
Note:
1. When using DFLL48M in USB recovery mode, the Fine Step value must be 0xA to guarantee a USB clock at
+/-0.25% before 11ms after a resume. Only usable in LDO regulator mode.
2. Very high signal quality and crystal less. It is the best setup for USB Device mode.
3. FDPLL lock time is short when the clock frequency source is high (> 1 MHz). Thus, FDPLL and external OSC
can be stopped during USB suspend mode to reduce consumption and guarantee a USB wake-up time (See
TDRSMDN in USB specification).
© 2020 Microchip Technology Inc.
DS60001477C-page 1077
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
47.
Electrical Characteristics - Extended Temperature Range 105°C
This section lists only device components and properties that are deviating from the performance of the standard
temperature range device.
47.1
Disclaimer
All typical values are measured at T = 25°C unless otherwise specified. All minimum and maximum values are valid
across operating temperature and voltage unless otherwise specified.
47.2
General Operating Ratings - 105°C
The device must operate within the ratings listed below in order for all other electrical characteristics and typical
characteristics of the device to be valid.
Table 47-1. General Operating Conditions - 105°C
Symbol
Description
Min.
Typ.
Max.
Units
VDDIN
Power supply voltage
1.62
3.3
3.63
V
VDDIO
IO Supply Voltage
1.62
3.3
3.63
V
VDDANA
Analog supply voltage
1.62
3.3
3.63
V
TA
Temperature range
-40
25
105
°C
TJ
Junction temperature
-
-
120
°C
CAUTION
47.3
In debugger cold-plugging mode, NVM erase operations are not protected by the BOD33 and BOD12.
NVM erase operation at supply voltages below specified minimum can cause corruption of NVM areas that
are mandatory for correct device behavior.
Power Consumption
The values in this section are measured values of power consumption under the following conditions, except where
noted:
• Operating Conditions
– VVDDIN = 3.3V or 1.8V
– For VDDIN=1.8V, CPU is running on Flash with 3 wait states
– For VDDIN=3.3V, CPU is running on Flash with 1 wait state in PL0 and 2 wait states in PL2.
– Low power cache is enabled
– BOD33 is disabled
• Oscillators
– XOSC (crystal oscillator) stopped
– XOSC32K (32KHz crystal oscillator) running with external 32KHz crystal
– When in active Performance Level 2 (PL2) mode, DFLL48M is running at 48MHz and using XOSC32K as
reference
– When in active PL0 mode, the internal Multi RC Oscillator is running at specified frequency
• Clocks
– DFLL48M used as main clock source when in PL2 mode. In PL0 mode, OSC16M used at 4, 8, or 12MHz
– Clock masks and dividers at reset values: All AHB & APB clocks enabled, CPUDIV=1, BUPDIV=8,
LPDIV=1
© 2020 Microchip Technology Inc.
DS60001477C-page 1078
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
– I/Os are configured in Digital Functionality Disabled mode
Table 47-2. Active Current Consumption - 105°C(1)
Mode
Conditions
Regulator
PL
Clock
Vcc
Ta
Typ.
Max.
Units
ACTIVE
COREMARK
LDO
PL0
OSC 12MHz
1.8V
Max at 105°C
Typ at 25°C
77
118
µA/MHz
79
125
1.8V
80
149
3.3V
82
154
1.8V
89
231
3.3V
92
238
1.8V
93
105
3.3V
95
109
1.8V
47
75
3.3V
32
52
1.8V
50
95
3.3V
34
66
1.8V
57
146
3.3V
42
105
1.8V
67
79
3.3V
40
48
1.8V
76
121
3.3V
78
125
1.8V
79
149
3.3V
81
153
1.8V
89
230
3.3V
91
238
1.8V
94
107
3.3V
95
108
1.8V
47
77
3.3V
31
52
1.8V
50
94
3.3V
34
65
1.8V
57
146
3.3V
42
104
1.8V
67
80
3.3V
40
48
3.3V
OSC 8MHz
OSC 4MHz
PL2
BUCK
PL0
DFLL 48MHz
OSC 12MHz
OSC 8MHz
OSC 4MHz
PL2
FIBO
LDO
PL0
DFLL 48MHz
OSC 12MHz
OSC 8MHz
OSC 4MHz
PL2
BUCK
PL0
DFLL 48MHz
OSC 12MHz
OSC 8MHz
OSC 4MHz
PL2
© 2020 Microchip Technology Inc.
DFLL 48MHz
DS60001477C-page 1079
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
...........continued
Mode
Conditions
Regulator
PL
Clock
Vcc
Ta
Typ.
Max.
Units
ACTIVE
WHILE1
LDO
PL0
OSC 12MHz
1.8V
Max at 105°C
Typ at 25°C
60
105
µA/MHz
62
108
1.8V
63
133
3.3V
65
137
1.8V
72
214
3.3V
75
221
1.8V
73
86
3.3V
73
87
1.8V
38
67
3.3V
26
46
1.8V
40
84
3.3V
29
60
1.8V
47
136
3.3V
36
99
1.8V
52
63
3.3V
31
39
1.8V
17
45
3.3V
13
33
3.3V
OSC 8MHz
OSC 4MHz
PL2
BUCK
PL0
DFLL 48MHz
OSC 12MHz
OSC 8MHz
OSC 4MHz
PL2
IDLE
PL0
DFLL 48MHz
OSC 12MHz
Note: 1. These values are based on characterization.
© 2020 Microchip Technology Inc.
DS60001477C-page 1080
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
Table 47-3. Standby, Backup and Off Mode Current Consumption(1)
Mode
Conditions
STANDBY PD0, PD1, PD2 in retention state
Regulator Mode
Vcc
Ta
LPEFF Disable
1.8V 25°C
105°C
LPEFF Enable
3.3V 25°C
105°C
BUCK with STDBPL0 1.8V 25°C
105°C
3.3V 25°C
105°C
PD0, PD1, PD2 in retention state with
RTC running on OSCULP32K
LPEFF Disable
1.8V 25°C
105°C
LPEFF Enable
3.3V 25°C
105°C
BUCK with STDBPL0 1.8V 25°C
105°C
3.3V 25°C
105°C
PD1, PD2 in retention state and PD0 in
active state
LPEFF Disable
1.8V 25°C
105°C
LPEFF Enable
3.3V 25°C
105°C
BUCK with STDBPL0 1.8V 25°C
105°C
3.3V 25°C
105°C
PD2 in retention state and PD0, PD1 in
active state
LPEFF Disable
1.8V 25°C
105°C
LPEFF Enable
3.3V 25°C
105°C
BUCK with STDBPL0 1.8V 25°C
105°C
3.3V 25°C
105°C
© 2020 Microchip Technology Inc.
Typ.
Max.
Units
1.3
3.1
µA
65.8
142
1.2
2.7
46.7
99.3
1.3
2.7
45.0
95.8
1.1
2.3
34.0
74.1
1.5
3.2
66.0
142
1.4
2.9
46.7
99.6
1.4
2.8
45.0
95.8
1.2
2.4
34.0
74.2
1.6
3.6
76.2
166
1.4
3.2
52.7
113
1.4
3.1
51.4
112
1.3
2.6
38.1
85
2.3
5.6
129
279
2.0
4.8
80.0
250
2.0
4.7
84.5
176
1.6
3.5
56.7
125
DS60001477C-page 1081
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
...........continued
Mode
Conditions
STANDBY PD0, PD1, PD2 in active state
Regulator Mode
Vcc
Ta
LPEFF Disable
1.8V 25°C
105°C
LPEFF Enable
3.3V 25°C
105°C
BUCK with STDBPL0 1.8V 25°C
105°C
Typ.
Max.
Units
3.3
7.9
µA
194
412
2.8
6.3
165
391
2.7
6.4
120
254
3.3V 25°C2.0
105°C
BACKUP
powered by VDDIN VDDIN+VDDANA+VDDIO consumption
1.8V 25°C
105°C
3.3V 25°C
105°C
powered by VDDIN VBAT consumption
1.8V 25°C
105°C
3.3V 25°C
105°C
powered by VDDIN with RTC running VDDIN+VDDANA+VDDIO
consumption
1.8V 25°C
105°C
3.3V 25°C
105°C
powered by VDDIN with RTC running VBAT consumption
1.8V 25°C
105°C
3.3V 25°C
105°C
powered by VBAT VDDIN+VDDANA+VDDIO consumption
1.8V 25°C
105°C
3.3V 25°C
105°C
powered by VBAT VBAT consumption
1.8V 25°C
105°C
3.3V 25°C
105°C
© 2020 Microchip Technology Inc.
4.6
79.5
169
0.5
0.9
10.0
23.2
0.6
1.2
13.2
31.8
µA
-0.002 0.004
0.03
0.07
0.01
0.03
0.06
0.16
0.5
0.9
10.1
23.3
0.7
1.2
13.3
31.9
0.000
0.005
0.03
0.07
0.008
0.018
0.05
0.15
0.1
0.3
6.3
13.2
0.2
0.5
9.6
21.4
0.4
0.6
4.3
10.1
0.4
0.6
4.4
10.5
DS60001477C-page 1082
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
...........continued
Mode
Conditions
Regulator Mode
BACKUP
powered by VBAT with RTC running VDDIN+VDDANA+VDDIO
consumption
Vcc
Ta
1.8V 25°C
105°C
3.3V 25°C
105°C
powered by VBAT with RTC running VBAT consumption
1.8V 25°C
105°C
3.3V 25°C
105°C
OFF
1.8V 25°C
105°C
3.3V 25°C
105°C
Typ.
Max.
Units
0.14
0.25
µA
6.4
13.2
0.2
0.5
9.5
21.4
0.4
0.7
4.3
10.2
0.5
0.7
4.5
10.6
0.16
0.29
6.6
13.7
0.2
0.5
9.9
22.2
µA
Note: 1. These values are based on characterization.
47.4
I/O Pin Characteristics
Three are three different pin types with three different speeds: Backup, Normal, and High Sink(3,4). The Drive
Strength bit is located in the Pin Configuration register PORT (PORT.PINCFG.DRVSTR).
Table 47-4. I/O Pins - Common Characteristics
Symbol
Parameters
Conditions
Min.
Typ.
Max.
Unit
VIL
Input low-level voltage
VDD=1.62-2.7V
-
-
0.25×VDD
V
VDD=2.7V-3.63V
-
-
0.3×VDD
VDD=1.62-2.7V
0.7×VDD
-
-
VDD=2.7V-3.63V
0.55×VDD
-
-
VIH
Input high-level voltage
VOL
Output low-level voltage
VDD>1.6V, IOL max
-
0.1×VDD
0.2×VDD
VOH
Output high-level voltage
VDD>1.6V, IOH max
0.8×VDD
0.9×VDD
-
RPULL
Pull-up - Pull-down resistance
All pins excepted PA24, PA25
20
40
60
PA24, PA25(1)
50
100
150
Pull-up resistors disabled
-1
+/-0.015
1
ILEAK
Input leakage current
© 2020 Microchip Technology Inc.
DS60001477C-page 1083
kΩ
µA
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
Table 47-5. I/O Pins - Maximum Output Current
Symbol Parameter
Conditions
Backup pins Backup
in Backup
and
mode
Normal
pins
High
Sink
pins
Backup
and
Normal
pins
DRVSTR=0
IOL
IOH
High
Sink
pins
Unit
mA
DRVSTR=1
Maximum Output
low-level current
VDD=1.62V-3V 0.005
1
2
2
4
VDD=3V-3.63V 0.008
2.5
6
6
12
Maximum Output
high-level current
VDD=1.62V-3V 0.005
0.7
1.5
1.5
3
VDD=3V-3.63V 0.008
2
5
5
10
Table 47-6. I/O Pins - Dynamic Characteristics(1)
Symbol Parameter
Conditions
Backup pins
in Backup
mode
Backup
High
and Normal Sink
pins
pins
Backup
High
and Normal Sink
pins
pins
DRVSTR=0
DRVSTR=1
tRISE
Maximum Rise
time
VDD=3.3V,
load=20pF
2000
13
6
6
4.5
tFALL
Maximum Fall
time
VDD=3.3V,
load=20pF
2000
12
7
7
4.5
Unit
nS
Note:
1. These values are based on simulation. They are not covered by production test limits or characterization.
2. 2. The pins PA12, PA13, PB12, PB13, PB16, PB17, PB30, PB31 are limited on output low-level current in
I2C standard mode (Sm) and Fast mode (Fm). The limitation is:
– 2.5mA instead of 3mA for a VOL=0.4V
– 3mA instead of 6mA for a VOL=0.6V.
3. The following pins are High Sink pins, and have different properties than normal pins: PA08, PA09, PA16,
PA17, PA22, PA23, PA27, PA31.
4. The following pins are Backups pins and have different properties than normal pins: PA00, PA01, PB00,
PB01, PB02, PB03.
47.5
Injection Current - 105°C
Stresses beyond those listed in the table below may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or other conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
Table 47-7. Injection Current(1,2) - 105°C
Symbol
Description
min
max
Unit
(3)
IO pin injection current
-1
+1
mA
Iinj2 (4)
IO pin injection current
-15
+15
mA
Iinjtotal
Sum of IO pins injection current
-45
+45
mA
Iinj1
© 2020 Microchip Technology Inc.
DS60001477C-page 1084
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
Note:
1. Injecting current may have an effect on the accuracy of Analog blocks
2. Injecting current on Backup IOs is not allowed
3. Conditions for Vpin: Vpin < GND-0.6V or 3.6V2.7 V
7.5
12
12
12
VDDIN>1.6 V
14
28
42
48
VDDIN>2.7 V
24
45
48
48
Table 47-24. NVM Timing Characteristics
Symbol
Timings
Max
Units
tFPP
Page Write(1)
2.5
ms
tFRE
erase(1)
Row
6
Note:
1. These values are based on simulation. They are not covered by production test limits or characterization.
2. For this Flash technology, a maximum number of 8 consecutive writes is allowed per row. Once this number is
reached, a row erase is mandatory.
Table 47-25. NVM Reliability Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
RetNVM25k
Retention after up to 25k
Average ambient 55°C
10
50
-
Years
RetNVM2.5k
Retention after up to 2.5k
Average ambient 55°C
20
100
-
Years
RetNVM100
Retention after up to 100
Average ambient 55°C
25
>100
-
Years
-40°C < Ta < 85°C
25K
100K
-
Cycles
CycNVM
Cycling
Endurance(1)
© 2020 Microchip Technology Inc.
DS60001477C-page 1094
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
Note: 1. An endurance cycle is a write and an erase operation.
Table 47-26. EEPROM Emulation(1) Reliability Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
RetEE100k
Retention after up to 100k
Average ambient 55°C
10
50
-
Years
RetEE10k
Retention after up to 10k
Average ambient 55°C
20
100
-
Years
-40°C < Ta < 85°C
100K
400K
-
Cycles
CycEE
Cycling
Endurance(2)
Note:
(1) The EEPROM emulation is a software emulation described in the App note AT03265.
(2) An endurance cycle is a write and an erase operation.
Table 47-27. Flash Erase and Programming Current
Symbol
Parameter
Typ.
Units
IDDNVM
Maximum current (peak)
during whole programming
or erase operation
10
mA
47.8
Oscillators Characteristics
47.8.1
Crystal Oscillator (XOSC) Characteristics
Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN.
Table 47-28. Digital Clock Characteristics
Symbol
Parameter
Min.
Typ.
Max.
Units
FXIN
XIN clock frequency
-
-
24
MHz
DCXIN
XIN clock duty cycle
40
50
60
%
Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT as shown in the figure Oscillator Connection.
Figure 47-2. Oscillator Connection
DEVICE
XIN
Crystal
CLEXT
LM
RM
CSTRAY
CSHUNT
CM
XOUT
CLEXT
The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table.
The exact value of CL can be found in the crystal data sheet. The capacitance of the external capacitors (CLEXT) can
then be computed as follows:
Load Capacitance Equation
© 2020 Microchip Technology Inc.
DS60001477C-page 1095
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification
CXIN = XOSC XIN pin data sheet specification
CXOUT = XOSC XOUT pin data sheet specification
CLEXT = Required external crystal load capacitor
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
Table 47-29. Multi Crystal Oscillator Electrical Characteristics
Symbol
Parameter
FOUT
Crystal oscillator frequency
ESR
Crystal Equivalent Series Resistance - SF=3
CXIN
Conditions
Min.
Typ.
Max.
Units
0.4
-
32
MHz
F=0.4MHz, CL=100pF XOSC, GAIN=0
-
-
5.6K
Ω
F=2MHz, CL=20pF XOSC,GAIN=0
-
-
416
F=4MHz, CL=20pF XOSC, GAIN=1
-
-
243
F=8MHz, CL=20pF XOSC, GAIN=2
-
-
138
F=16MHz, CL=20pF XOSC, GAIN=3
-
-
66
F=32MHz, CL=20pF XOSC, GAIN=4
-
-
56
-
5.8
-
-
3.2
-
F=2MHz, CL=20pF XOSC, GAIN=0
-
14k
48k
F=4MHz, CL=20pF XOSC, GAIN=1
-
6.8k
19.5k
F=8MHz, CL=20pF XOSC, GAIN=2
-
5.6k
13k
F=16MHz, CL=20pF XOSC, GAIN=3
-
6.8k
14.5k
F=32MHz, CL=20pF XOSC, GAIN=4
-
5.3K
9.6k
Parasitic load capacitor
CXOUT
TSTART
Startup time
pF
Cycles
Note:
1. These values are based on characterization.
Table 47-30. Power Consumption(1)
Symbol Parameter
Conditions
IDD
F=2MHz - CL=20pF
XOSC,GAIN=0, VCC=3.3V
AGC=OFF Max 105°C Typ 25°C
AGC=ON
-
89
177
82
173
F=4MHz - CL=20pF
XOSC,GAIN=1, VCC=3.3V
AGC=OFF
-
140
242
AGC=ON
-
102
203
F=8MHz - CL=20pF
XOSC,GAIN=2, VCC=3.3V
AGC=OFF
-
243
365
AGC=ON
-
166
282
F=16MHz - CL=20pF
XOSC,GAIN=3, VCC=3.3V
AGC=OFF
-
493
669
AGC=ON
-
293
459
F=32MHz - CL=20pF
XOSC,GAIN=4, VCC=3.3V
AGC=OFF
-
1467 1890
AGC=ON
-
651
Current
consumption
© 2020 Microchip Technology Inc.
Ta
Min. Typ. Max. Units
µA
1080
DS60001477C-page 1096
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
Note:
1. These values are based on characterization.
47.8.2
External 32KHz Crystal Oscillator (XOSC32K) Characteristics - 105°C
Digital Clock Characteristics
The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32 pin.
Table 47-31. Digital Clock Characteristics(1)
Symbol
Parameter
fCPXIN32
XIN32 clock frequency
DCXIN
XIN32 clock duty cycle
Min.
40
Typ.
Max.
Units
32.768
1000
kHz
50
60
%
Note: 1. These values are based on characterization.
Crystal Oscillator Characteristics
The following table describes the characteristics for the oscillator when a crystal is connected between XIN and
XOUT as shown in the figure Oscillator Connection.
Figure 47-3. Oscillator Crystal Connection
DEVICE
XIN32
Crystal
CLEXT
LM
RM
CSTRAY
CSHUNT
CM
XOUT32
CLEXT
The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table.
The exact value of CL can be found in the crystal data sheet. The capacitance of the external capacitors (CLEXT) can
then be computed as follows:
Load Capacitance Equation
CLOAD = ([CXIN + CLEXT] * [CXOUT + CLEXT]) / ([CXIN + CLEXT + CLEXT + CXOUT]) + CSTRAY
Where:
CLOAD = Crystal Mfg. CLOAD specification
CXIN = XOSC XIN pin data sheet specification
CXOUT = XOSC XOUT pin data sheet specification
CLEXT = Required external crystal load capacitor
CSTRAY (Osc PCB capacitance) = 1.5 pf per 12.5 mm (0.5 inches) (TRACE W = 0.175 mm, H = 36 μm, T = 113 μm)
Table 47-32. 32KHz Crystal Oscillator Electrical Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOUT
Crystal oscillator frequency
-
-
32.768
-
kHz
CL
Crystal load capacitance
-
7
9
12.5
pF
CSHUNT
Crystal shunt capacitance
-
0.6
-
2
pF
CM
Motional capacitance
-
0.6
-
3
fF
© 2020 Microchip Technology Inc.
DS60001477C-page 1097
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
...........continued
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
ESR
Crystal Equivalent Series Resistance - SF=3
f=32.768kHz,
CL=12.5pF
-
50
70
kΩ
CXIN32k
Parasitic load capacitor(2)
-
-
2.31
-
pF
-
-
2.53
-
CXOUT32k
tSTARTUP
Startup time
f=32.768kHz,
CL=12.5pF
-
25k
82k
Cycles
Pon
Drive Level (1)
-
-
-
0.1
µW
Note:
1. These values are based on characterization.
Table 47-33. Power Consumption(1)
Symbol
Parameter
Conditions
Ta
Min.
Typ.
Max.
Units
IDD
Current consumption
VCC=3.3V
Max 105°C
Typ 25°C
-
0.311
755
nA
Note: (1) These values are based on characterization.
47.8.3
32.768kHz Internal Oscillator (OSC32K) Characteristics - 105°C
Table 47-34. 32KHz RC Oscillator Electrical Characteristics(1)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOUT
Output frequency
at 25°C, at VDDIO=3.3V
32.572
32.768
33.044
kHz
at 25°C, over [1.62, 3.63]V
31.425
32.768
33.603
kHz
over[-40,+105]°C, over [1.62, 3.63]V
28.220
32.768
35.870
kHz
TSTARTUP
Startup time
-
1
2
cycles
Duty
Duty Cycle
-
50
-
%
Note: 1. These values are based on characterization.
Table 47-35. Power Consumption(1)
Symbol
Parameter
Conditions
Ta
Min.
Typ.
Max.
Units
IDD
Current consumption
VCC=3.3V
Max 105°C
Typ 25°C
-
0.54
1.15
µA
Note: (1) These values are based on characterization.
47.8.4
Internal Ultra Low Power 32KHz RC Oscillator (OSCULP32K) Characteristics - 105°C
Table 47-36. Ultra Low Power Internal 32KHz RC Oscillator Electrical Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOUT
Output frequency
at 25°C, at VDDIO=3.3V
31.775
32.768
34.033
kHz
at 25°C, over [1.62, 3.63]V
31.848
32.768
34.202
kHz
over[-40,+105]°C, over [1.62, 3.63]V
26.296
32.768
39.675
kHz
© 2020 Microchip Technology Inc.
DS60001477C-page 1098
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
...........continued
Symbol
Parameter
Duty
Duty Cycle
47.8.5
Conditions
Min.
Typ.
Max.
Units
-
50
-
%
16MHz RC Oscillator (OSC16M) Characteristics - 105°C
Table 47-37. Multi RC Oscillator Electrical Characteristics
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
FOUT
Output frequency
VCC=3.3V, T=25°C
3.953
4
4.062
MHz
7.877
8
8.112
11.857
12
12.139
15.754
16
16.235
TempDrift
Freq vs. temperature drift
-4
4
SupplyDrift
Freq vs. supply drift
-2
2
TWUP(2)
Wake up time - 1st clock edge after enable
TSTARTUP(2)
Duty(1)
Startup time
Duty Cycle
%
FOUT = 4MHz
-
0.12
0.27
FOUT = 8MHz
-
0.12
0.25
FOUT = 12MHz
-
0.12
0.27
FOUT = 16MHz
-
0.12
0.25
FOUT = 4MHz
-
1.2
2.9
FOUT = 8MHz
-
1.3
2.6
FOUT = 12MHz
-
1.3
2.8
FOUT = 16MHz
-
1.4
3.1
-
45
50
55
µs
µs
%
Note:
1. These values are based on simulation. They are not covered by production test limits or characterization.
2. These values are based on characterization.
Table 47-38. Power Consumption(1)
Symbol
Parameter
Conditions
Ta
Min.
Typ.
Max.
Unit
IDDT
Current
consumption
Fout=4MHz,
VCC=3.3V
Max.105°C
Typ.25°C
-
64
140
µA
Fout=8MHz,
VCC=3.3V
-
91
165
Fout=12MHz,
VCC=3.3V
-
114
187
Fout=16MHz,
VCC=3.3V
-
141
212
Note:
1. These values are based on characterization.
© 2020 Microchip Technology Inc.
DS60001477C-page 1099
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
47.8.6
Digital Frequency Locked Loop (DFLL48M) Characteristics - 105°C
Table 47-39. DFLL48M Characteristics - Open Loop Mode(1,2)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FOpenOUT
Output frequency
DFLLVAL.COARSE=DFLL48M_COARSE_CAL
DFLLVAL.FINE=512
46.6
47.8
49
MHz
TOpenSTARTUP
Startup time
DFLLVAL.COARSE=DFLL48M_COARSE_CAL
DFLLVAL.FINE=512
-
8.3
9.1
µs
FOUT within 90% of final value
Note:
1. DFLL48 in open loop can be used only with LDO regulator.
2. These values are based on characterization.
Table 47-40. DFLL48M Characteristics - Closed Loop Mode
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
FCloseOUT
Average Output frequency
fREF = XTAL, 32.768kHz, 100ppm
47.963
47.972
47.981
MHz
732
32768
33000
Hz
-
-
0.51
ns
200
700
µs
DFLLMUL=1464
FREF(2,3)
Input reference frequency
FCloseJitter(1)
Period Jitter
fREF = XTAL, 32.768kHz, 100ppm
DFLLMUL=1464
TLock(1)
Lock time
FREF = XTAL, 32.768kHz, 100ppm
DFLLMUL=1464
DFLLVAL.COARSE=DFLL48M_COARSE_CAL
DFLLVAL.FINE = 512
DFLLCTRL.BPLCKC = 1
DFLLCTRL.QLDIS = 0
DFLLCTRL.CCDIS = 1
DFLLMUL.FSTEP = 10
Note:
1. These values are based on characterization.
2. To insure that the device stays within the maximum allowed clock frequency, any reference clock for the DFLL
in close loop must be within a 2% error accuracy.
3. These values are based on simulation. They are not covered by production test limits or characterization.
Table 47-41. DFLL48M Power Consumption(1)
Symbol Parameter
Conditions
Ta
Min. Typ. Max. Units
IDD
Power consumption Open Loop
DFLLVAL.COARSE=DFLL48M_COARSE_CAL
IDD
Power consumption Closed Loop
FREF = 32.768kHz, VCC=3.3V
Max.105°C Typ.25°C
-
286
-
µA
362
-
µA
Note:
1. These values are based on characterization.
© 2020 Microchip Technology Inc.
DS60001477C-page 1100
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
47.8.7
Digital Phase Lock Loop (DPLL) Characteristics - 105°C
Table 47-42. Fractional Digital Phase Lock Loop Characteristics
Symbol
Parameter
FIN
Input Clock Frequency
FOUT
Output frequency
JP(2)
TLOCK(2)
Duty(1)
Period Jitter
Lock Time
Conditions
Min.
Typ.
Max.
Units
32
-
2000
kHz
PL2
48
-
96
MHz
PL0
48
-
48
MHz
PL0, FIN=32kHz @ FOUT=48MHz
-
1.9
5.0
%
PL2, FIN=32kHz @ FOUT=48MHz
-
1.9
4.0
PL2, FIN=32kHz @ FOUT=96MHz
-
3.3
7.0
PL0, FIN=2MHz @ FOUT=48MHz
-
2.0
8.0
PL2, FIN=2MHz @ FOUT=48MHz
-
2.0
4.0
PL2, FIN=2MHz @ FOUT=96MHz
-
4.2
7.0
After startup, time to get lock signal,
FIN=32kHz @ FOUT=96MHz
-
1
2
ms
After startup, time to get lock signal,
FIN=2MHz @ FOUT=96MHz
-
25
35
µs
40
50
60
%
Duty Cycle
Note:
1. These values are based on simulation. They are not covered by production test limits or characterization.
2. These values are based on characterization.
Table 47-43. Power Consumption(1)
Symbol
Parameter
Conditions
TA
Min.
Typ.
Max.
Units
IDD
Current Consumption
Ck=48MHz (PL0)
Max.105°C
Typ.25°C
-
454
600
µA
-
934
1099
Ck=96MHz (PL2)
Note:
1. These values are based on characterization.
© 2020 Microchip Technology Inc.
DS60001477C-page 1101
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
47.9
Timing Characteristics
47.9.1
SERCOM in SPI Mode in PL2 - 105°C
Table 47-44. SPI Timing Characteristics and Requirements for all SERCOM and all Configurations(1)
Symbol Parameter
Conditions
Min.
tSCK
Master, VDD>2.70V
88.4
Master, VDD>1.62V
109.4
SCK period when tSOV=0 on the slave side
Typ.
ns
tSCKW
SCK high/low width
Master
0.5*tSCK
tSCKR
SCK rise time(2)
Master
0.25*tSCK
Master
0.25*tSCK
time(2)
tSCKF
SCK fall
tMIS
MISO setup to SCK
tMIH
tMOS
tMOH
tSSCK
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
Slave SCK Period
Master, VDD>2.70V
44.2
Master, VDD>1.62V
54.7
Master, VDD>2.70V
0
Master, VDD>1.62V
0
Master, VDD>2.70V
11.5
Master, VDD>1.62V
16.6
Master, VDD>2.70V
1.5
Master, VDD>1.62V
1.5
Slave, VDD>2.70V
76
Slave, VDD>1.62V
98
tSSCKW
SCK high/low width
Slave
0.5*tSCK
tSSCKR
SCK rise time(2)
Slave
0.25*tSCK
Slave
0.25*tSCK
time(2)
tSSCKF
SCK fall
tSIS
MOSI setup to SCK
tSIH
tSSS
MOSI hold after SCK
SS setup to SCK
Max. Unit
Slave, VDD>2.70V
10.6
Slave, VDD>1.62V
12.2
Slave, VDD>2.70V
4.7
Slave, VDD>1.62V
8.4
Slave PRELOADEN=1
PRELOADEN=0
tSSH
SS hold after SCK
© 2020 Microchip Technology Inc.
Slave
DS60001477C-page 1102
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
...........continued
Symbol Parameter
Conditions
tSOS
Slave, VDD>2.70V
38
Slave, VDD>1.62V
49.2
tSOH
tSOSS
tSOSH
MISO setup before SCK
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
© 2020 Microchip Technology Inc.
Min.
Slave, VDD>2.70V
11.6
Slave, VDD>1.62V
11.6
Typ.
Max. Unit
Slave, VDD>2.70V
32.1
Slave, VDD>1.62V
42.9
Slave, VDD>2.70V
6.2
Slave, VDD>1.62V
6.2
ns
DS60001477C-page 1103
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
Table 47-45. SPI Timing Characteristics and Requirements for SERCOM1 with DOPO=0x0 and DIPO=0x3(1)
Symbol
Parameter
Conditions
Min. Typ.
tSCK
SCK period when tSOV=0 on the slave side
Master, VDD>2.70V
79.6
Master, VDD>1.62V
97.8
tSCKW
SCK high/low width
time(2)
0.5*tSCK
Master
0.25*tSCK
0.25*tSCK
SCK rise
tSCKF
SCK fall time(2)
Master
tMIS
MISO setup to SCK
Master, VDD>2.70V
39.8
Master, VDD>1.62V
48.9
Master, VDD>2.70V
0
Master, VDD>1.62V
0
tMIH
tMOS
tMOH
tSSCK
tSSCKW
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
Slave SCK Period
SCK high/low width
time(2)
Master, VDD>2.70V
6.2
Master, VDD>1.62V
12.7
Master, VDD>2.70V
2.5
Master, VDD>1.62V
2.5
Slave, VDD>2.70V
63
Slave, VDD>1.62V
81.6
Slave
0.5*tSCK
Slave
0.25*tSCK
0.25*tSCK
tSSCKR
SCK rise
tSSCKF
SCK fall time(2)
Slave
tSIS
MOSI setup to SCK
Slave, VDD>2.70V
8.5
Slave, VDD>1.62V
11.3
Slave, VDD>2.70V
4.3
Slave, VDD>1.62V
5
tSIH
tSSS
MOSI hold after SCK
SS setup to SCK
ns
Master
tSCKR
Max. Unit
Slave PRELOADEN=1
PRELOADEN=0
tSSH
SS hold after SCK
Slave
tSOS
MISO setup before SCK
Slave, VDD>2.70V
31.7
Slave, VDD>1.62V
40.8
tSOH
tSOSS
tSOSH
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
Slave, VDD>2.70V
11.6
Slave, VDD>1.62V
11.6
Slave, VDD>2.70V
29
Slave, VDD>1.62V
38.1
Slave, VDD>2.70V
7.8
Slave, VDD>1.62V
7.8
ns
Note: 1. These values are based on simulation. They are not covered by production test limits or characterization.
© 2020 Microchip Technology Inc.
DS60001477C-page 1104
SAM L21 Family Data Sheet
Electrical Characteristics - Extended Temperat...
Figure 47-4. SPI Timing Requirements in Master Mode
Figure 47-5. SPI Timing Requirements in Slave Mode
Maximum SPI Frequency
• Master Mode
fSCKmax = 1/2*(tMIS + tvalid), where tvalid is the slave time response to output data after detecting an SCK edge.
For a non-volatile memory with tvalid = 12ns Max, fSPCKMax = 9.8MHz @ VDDIO > 2.7V
• Slave Mode
fSCKmax = 1/2*(tSOV + tsu), where tsu is the setup time from the master before sampling data. With a perfect
master (tsu=0), fSPCKMax = 16.3MHz @ VDDIO > 2.7V
© 2020 Microchip Technology Inc.
DS60001477C-page 1105
SAM L21 Family Data Sheet
Typical Characteristics
48.
Typical Characteristics
48.1
Power Consumption over Temperature in Sleep Modes
Power Consumption in Standby Sleep Mode with RTC
Operating conditions:
• VDDIN = 3.3V or 1.8V
• ULPVERG LPEFF Enable
• RTC running on external 32KHz crystal
• PD0, PD1, PD2 in retention state
• BOD33 is disabled
Figure 48-1. Power Consumption over Temperature in STANDBY Sleep Mode with RTC
30
VDD=3.3V
VDD=1.8V
25
ICC in µA
20
15
10
5
0
−40
−20
0
20
40
60
80
Temperature in °C
Power Consumption in BACKUP Sleep Mode with RTC
Operating conditions:
• VDDIN =0V
• VBAT = 3.3V or 1.8V
• RTC running on external 32KHz crystal
• BOD33 is disabled
© 2020 Microchip Technology Inc.
DS60001477C-page 1106
SAM L21 Family Data Sheet
Typical Characteristics
Figure 48-2. Power Consumption over Temperature in Standby Sleep Mode with RTC
3
VBAT=3.3V
VBAT=1.8V
2.5
ICC in µA
2
1.5
1
0.5
0
−40
−20
0
20
40
60
80
Temperature in °C
© 2020 Microchip Technology Inc.
DS60001477C-page 1107
SAM L21 Family Data Sheet
Appendix A
49.
Appendix A
49.1
SIL 2-Enabled Functional Safety Devices
Microchip offers IEC 61508 SIL 2-enabled devices which can utilize the self-test library available on request from
Microchip Sales Office. The download includes the library binary, library user’s manual, and user’s checklist for
integration of the library. Refer to the “Embex SIL 2 Library User’s Manual” for additional information on using the IEC
61508 SIL 2-enabled Microchip devices.
Contact Microchip Sales Office for additional information on the IEC 61508 SIL 2-enabled devices, or to request a
part number which is not shown in the following Ordering Information.
49.1.1
Ordering Information
The following tables list the IEC 61508 SIL 2-enabled devices which can utilize the SIL 2 certified self-test library
(STL).
Table 49-1. SAM L21J
Ordering Code
FLASH (bytes)
SRAM (bytes)
Temperature Grade
Package
Carrier Type
ATSAML21J18B-AUT-SLL
256K
32K
-40°C to 85°C
TQFP64
Tape & Reel
ATSAML21J18B-MUT-SLL
256K
32K
-40°C to 85°C
QFN64
Tape & Reel
ATSAML21J17B-MUT-SLL
128K
16K
-40°C to 85°C
QFN64
Tape & Reel
Ordering Code
FLASH (bytes)
SRAM (bytes)
Temperature Grade
Package
Carrier Type
ATSAML21G18B-AUT-SLL
256K
32K
-40°C to 85°C
TQFP48
Tape & Reel
ATSAML21G18B-MUT-SLL
256K
32K
-40°C to 85°C
QFN48
Tape & Reel
ATSAML21G17B-MNT-SLL
128K
16K
-40°C to 105°C
QFN48
Tape & Reel
Ordering Code
FLASH (bytes)
SRAM (bytes)
Temperature Grade
Package
Carrier Type
ATSAML21E18B-AUT-SLL
256K
32K
-40°C to 85°C
TQFP32
Tape & Reel
ATSAML21E18B-MUT-SLL
256K
32K
-40°C to 85°C
QFN32
Tape & Reel
ATSAML21E16B-MNT-SLL
64K
8K
-40°C to 105°C
QFN32
Tape & Reel
Table 49-2. SAM L21G
Table 49-3. SAM L21E
© 2020 Microchip Technology Inc.
DS60001477C-page 1108
SAM L21 Family Data Sheet
Packaging Information
50.
Packaging Information
50.1
Thermal Considerations
50.1.1
Thermal Resistance Data
The following table summarizes the thermal resistance data depending on the package.
Table 50-1. Thermal Resistance Data
50.1.2
Package Type
θJA
θJC
Dummy value
dummy value
dummy value
Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1.
2.
TJ = TA + (PD x θJA)
TJ = TA + (PD x (θHEATSINK + θJC))
where:
•
•
•
•
•
θJA = Package thermal resistance, Junction-to-ambient (°C/W), see Thermal Resistance Data
θJC = Package thermal resistance, Junction-to-case thermal resistance (°C/W), see Thermal Resistance Data
θHEATSINK = Thermal resistance (°C/W) specification of the external cooling device
PD = Device power consumption (W)
TA = Ambient temperature (°C)
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is
necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the
resulting average chip-junction temperature TJ in °C.
© 2020 Microchip Technology Inc.
DS60001477C-page 1109
SAM L21 Family Data Sheet
Packaging Information
50.2
Package Drawings
50.2.1
64-Ball WLCSP
Table 50-2. Device and Package Maximum Weight
10
mg
Table 50-3. Package Characteristics
Moisture Sensitivity Level
© 2020 Microchip Technology Inc.
MSL1
DS60001477C-page 1110
SAM L21 Family Data Sheet
Packaging Information
Table 50-4. Package Reference
50.2.2
JEDEC Drawing Reference
N/A
JESD97 Classification
E1
64 pin TQFP
Table 50-5. Device and Package Maximum Weight
300
© 2020 Microchip Technology Inc.
mg
DS60001477C-page 1111
SAM L21 Family Data Sheet
Packaging Information
Table 50-6. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 50-7. Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
© 2020 Microchip Technology Inc.
DS60001477C-page 1112
SAM L21 Family Data Sheet
Packaging Information
50.2.3
64 pin QFN
Note: The exposed die attach pad is not connected electrically inside the device.
Table 50-8. Device and Package Maximum Weight
200
© 2020 Microchip Technology Inc.
mg
DS60001477C-page 1113
SAM L21 Family Data Sheet
Packaging Information
Table 50-9. Package Charateristics
Moisture Sensitivity Level
MSL3
Table 50-10. Package Reference
50.2.4
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
48 pin TQFP
© 2020 Microchip Technology Inc.
DS60001477C-page 1114
SAM L21 Family Data Sheet
Packaging Information
Table 50-11. Device and Package Maximum Weight
140
mg
Table 50-12. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 50-13. Package Reference
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
© 2020 Microchip Technology Inc.
DS60001477C-page 1115
SAM L21 Family Data Sheet
Packaging Information
50.2.5
48 pin QFN
Note: The exposed die attach pad is not connected electrically inside the device.
Table 50-14. Device and Package Maximum Weight
140
mg
Table 50-15. Package Characteristics
Moisture Sensitivity Level
© 2020 Microchip Technology Inc.
MSL3
DS60001477C-page 1116
SAM L21 Family Data Sheet
Packaging Information
Table 50-16. Package Reference
50.2.6
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
32 pin TQFP
Table 50-17. Device and Package Maximum Weight
100
© 2020 Microchip Technology Inc.
mg
DS60001477C-page 1117
SAM L21 Family Data Sheet
Packaging Information
Table 50-18. Package Charateristics
Moisture Sensitivity Level
MSL3
Table 50-19. Package Reference
50.2.7
JEDEC Drawing Reference
MS-026
JESD97 Classification
E3
32 pin QFN
Note: The exposed die attach pad is connected inside the device to GND and GNDANA.
© 2020 Microchip Technology Inc.
DS60001477C-page 1118
SAM L21 Family Data Sheet
Packaging Information
Table 50-20. Device and Package Maximum Weight
90
mg
Table 50-21. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 50-22. Package Reference
50.3
JEDEC Drawing Reference
MO-220
JESD97 Classification
E3
Soldering Profile
The following table gives the recommended soldering profile from J-STD-20.
Table 50-23.
Profile Feature
Green Package
Average Ramp-up Rate (217°C to peak)
3°C/s max.
Preheat Temperature 175°C ±25°C
150-200°C
Time Maintained Above 217°C
60-150s
Time within 5°C of Actual Peak Temperature
30s
Peak Temperature Range
260°C
Ramp-down Rate
6°C/s max.
Time 25°C to Peak Temperature
8 minutes max.
A maximum of three reflow passes is allowed per component.
© 2020 Microchip Technology Inc.
DS60001477C-page 1119
SAM L21 Family Data Sheet
Schematic Checklist
51.
Schematic Checklist
51.1
Introduction
This chapter describes a common checklist which should be used when starting and reviewing the schematics for a
SAM L21 design. This chapter illustrates the recommended power supply connections, how to connect external
analog references, programmer, debugger, oscillator and crystal.
51.1.1
Operation in Noisy Environment
If the device is operating in an environment with much electromagnetic noise it must be protected from this noise to
ensure reliable operation. In addition to following best practice EMC design guidelines, the recommendations listed in
the schematic checklist sections must be followed. In particular placing decoupling capacitors very close to the power
pins, a RC-filter on the RESET pin, and a pull-up resistor on the SWCLK pin is critical for reliable operations. It is also
relevant to eliminate or attenuate noise in order to avoid that it reaches supply pins, I/O pins and crystals.
51.2
Power Supply
The SAM L21 supports a single or dual power supply from 1.62V to 3.63V. The same voltage must be applied to both
VDDIN and VDDANA.
The internal voltage regulator has four different modes:
•
•
•
•
Linear mode: this mode does not require any external inductor. This is the default mode when CPU and
peripherals are running
Switching mode (Buck): the most efficient mode when the CPU and peripherals are running.
Low Power (LP) mode: This is the default mode used when the chip is in standby mode
Shutdown mode: When the chip is in backup mode, the internal regulator is turned off
Selecting between switching mode and linear mode can be done by software on the fly, but the power supply must be
designed according to which mode is to be used.
51.2.1
Power Supply Connections
The following figures shows the recommended power supply connections for switched/linear mode, linear mode only
and with battery backup.
© 2020 Microchip Technology Inc.
DS60001477C-page 1120
SAM L21 Family Data Sheet
Schematic Checklist
Figure 51-1. Power Supply Connection for Switching/Linear Mode
Close to device
(for every pin)
IO Supply
(1.62V — 3.63V)
SAM L21
VBAT (PB03)
VDDIO
Main Supply
(1.62V — 3.63V)
VDDANA
VDDIN
100nF
10µH
100nF
100nF
10µF
10µF
VSW
10µF
VDDCORE
1µF
100nF
GND
GNDANA
Figure 51-2. Power Supply Connection for Linear Mode Only
Close to device
(for every pin)
IO Supply
(1.62V — 3.63V)
SAM L21
VDDIO
VBAT (PB03)
Main Supply
(1.62V — 3.63V)
VDDANA
VDDIN
100nF
10µF
10µF
10µF
100nF
VSW
100nF
VDDCORE
1µF
100nF
GND
GNDANA
© 2020 Microchip Technology Inc.
DS60001477C-page 1121
SAM L21 Family Data Sheet
Schematic Checklist
Figure 51-3. Power Supply Connection for Battery Backup
Close to device
(for every pin)
IO Supply
(1.62V — 3.63V)
SAM L21
VBAT (PB03)
VDDIO
Main Supply
(1.62V — 3.63V)
VDDANA
VDDIN
100nF
10µH
100nF
100nF
10µF
10µF
VSW
10µF
VDDCORE
1µF
100nF
GND
GNDANA
Table 51-1. Power Supply Connections, VDDCORE or VSW From Internal Regulator
Signal Name Recommended Pin Connection
Description
VDDIO
Digital supply voltage
1.6V to 3.6V
Decoupling/filtering capacitors 100nF(1)(2) and 10µF(1)
Decoupling/filtering inductor 10µH(1)(3)
VDDANA
1.6V to 3.6V
Decoupling/filtering capacitors 100nF(1)(2) and 10µF(1)
Analog supply voltage
Ferrite bead(4) prevents the VDD noise interfering with VDDANA
VDDIN
1.6V to 3.6V
Decoupling/filtering capacitors 100nF(1)(2) and 10µF(1)
Digital supply voltage
Decoupling/filtering inductor 10µH(1)(3)
VBAT
1.6V to 3.6V when connected
External battery supply input
VDDCORE
0.9V to 1.2V typical
Decoupling/filtering capacitors 100nF(1)(2) and 1µF(1)
Linear regulator mode: Core supply
voltage output/ external decoupling
pin
Switched regulator mode: Core
supply voltage input, must be
connected to VSW via inductor
VSW
Switching regulator mode: 10 µH inductor with saturation
current above 150mA and DCR
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