HV98100/HV98101
Non-Dimmable, Off-Line, LED Driver with Low Total
Harmonic Distortions
Features
Description
• Good LED Current Regulation
- Better than 5% accuracy
• Valley Switching Buck-Boost Converter with
Power Factor Correction (PFC)
- 0.97 Power Factor (typical)
- 5% Total Harmonic Distortion (THD) (typical)
• Uses a Standard Off-the-Shelf Inductor
- No auxiliary winding required
• Single Input Voltage Range
- HV98100: 110 VAC ±15%
- HV98101: 230 VAC ±15%
• Supports 5W-15W Output Power
• Space-saving SOT-23-6L Package
The HV98100/HV98101 LED driver integrated circuit
(IC) is an off-line, high-power factor, buck-boost
controller targeted at general LED lighting products,
such as LED lamps and LED lighting fixtures with a
maximum power rating of about 15W.
Applications
• LED Lamps
• LED Lighting Fixtures
Valley-switching buck-boost converters are preferred in
off-line applications since they reduce switching losses.
A typical solution is to pair a constant on-time control
scheme with valley switching to achieve both a
high-power factor and good efficiency. However, this
control scheme results in a higher total harmonic distortion, and the actual value is dependent on the input and
output voltages. The HV98100/HV98101 uses a unique
control scheme to achieve a high-power factor and low
THD simultaneously under all line and load conditions,
while maximizing efficiency utilizing valley switching.
The average LED current is also controlled in a closedloop manner to achieve high LED accuracy.
Other unique features of the ICs are the bootstrap of
the IC supply voltage from the output, as well as the
unique valley-sensing scheme that allows the use of a
standard off-the-shelf inductor to minimize the overall
system cost.
Applications with low-output voltage
accommodated using a coupled inductor.
can
be
Package Types
HV98100/HV98101
6-Lead SOT-23
IND 1
6 GATE
GND 2
5 PVDD
COMP 3
4 CS
See Table 3-1 for pin description.
2016 Microchip Technology Inc.
DS20005640A-page 1
HV98100/HV98101
Typical Application Circuit
RHV
DHV
PVDD
MBBT
CPVDD
HV98100/1
COMP
GND
IND
GT
CS
CREC
RPVDD
CCOMP
DBBT
RCS
RVD
DPVDD
CO
LBBT
LED
DVD
VAC
Internal Block Diagram
OCP
Gate
PVDD
PVDD
I_VO
Fault
Protection
FLT
I_VO
POR
I_V O
AVDD
Valley Detect
Gate
GATE
GT_ON
fsta rt
Startup
clock
Gate
Vton_ref
Monoshot
Max F req
Clock
Monoshot
POR
STRT_UP
RES E T
RESET
Reg
IND
IN
Valley_Det
DET _V AL
VDDon /VDDof f
PVDD
GATE
Q
R
Q FLT
V_TON
THD
control
GT_R
REF
S
Gate
GND
OCP_REF
COMP
Gate
POR
Gate
LEB
OCP
CS_REF
CS
DS20005640A-page 2
2016 Microchip Technology Inc.
HV98100/HV98101
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Supply Voltage PVDD to GND ..................................................................................................................... -0.3V to +20V
GATE to GND.................................................................................................................................-0.3V to (PVDD +0.5V)
CS, COMP, IND to GND............................................................................................................................... -0.3V to 4.5V
Operating Junction Temperature.............................................................................................................-40°C to +125°C
Storage Temperature ..............................................................................................................................-65°C to +150°C
Power Dissipation at +25°C for 6L-SOT-23 .........................................................................................................800 mW
ESD Protection on all pins (HBM) ..............................................................................................................................2 kV
ESD Protection on all pins (MM) ...............................................................................................................................175V
* Based on JEDEC JESD51 testing and reporting standards
†
Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all specifications are for TA = TJ = +25°C, PVDD = 12V. Boldface
specifications apply over the full temperature range TA = TJ = -40°C to +125°C.
Parameter
Conditions
Symbol
Min.
Typ.
Max.
Units
PVDD,clamp
15.5
17
18.5
V
Current into PVDD = 4.0 mA;
CGATE = 500 pF;
fsw = 100 kHz;
VDD Start Voltage
VDD,ON
14.5
16
17.5
V
GATE starts switching
VDD Stop Voltage
VDD,OFF
6.5
8
9.5
V
Current into clamp
IDD,max
—
—
5
mA
Note 1
Current drawn by IC before start
IDD,Q
—
—
200
μA
Measured at PVDD = 12V
after PVDD rises from 0V to
12V
Current drawn by IC during operation
IDD,OP
—
—
4.3
mA
CGATE = 500 pF;
fsw = 100 kHz; COMP = 3V;
I_INDSINK = 200 μA;
I_INDSOURCE = 250 μA
Power Supply (PVDD)
PVDD Clamp Voltage
GATE stops switching
Gate Driver
ISOURCE
0.3
—
—
A
Note 2
Gate Driver Sinking Current
ISINK
0.6
—
—
A
Note 2
Gate Rise Time (10%-90%)
TRISE
—
—
45
ns
CGATE = 500 pF
Gate Fall Time (10%-90%)
TFALL
—
—
23
ns
CGATE = 500 pF
CSREF
194
204
214
mV
Note 2
OTA Offset Voltage
VOFFSET
-7.5
—
7.5
mV
Note 2
Open Loop DC Gain
AV
55
—
—
dB
1V COMP 4V; Output
open Note 1
GATE Driver Sourcing Current
Output Current Control
Internal Reference Voltage
Small Signal Transconductance
Gain Bandwidth Product
2016 Microchip Technology Inc.
gm
160
230
300
μA/V
1V COMP 4V; Note 1
GBW
0.16
0.24
—
MHz
CCOMP = 150 pF
(Note 2)
DS20005640A-page 3
HV98100/HV98101
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all specifications are for TA = TJ = +25°C, PVDD = 12V. Boldface
specifications apply over the full temperature range TA = TJ = -40°C to +125°C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Conditions
RON of COMP Reset FET
RCOMP
300
400
500
Start-up Clock
Fstart
6.25
10
15
kHz
Maximum Frequency Limit
Fmax
217
320
480
kHz
Note 1
Internal Clocks
Valley Detect
Current into IND pin
IIND
—
—
600
μA
Note 2
Voltage at IND pin
VIND
3.87
4.3
4.73
V
IIND = 250 μA
Comparator Delay Time
Tdelay
—
—
50
ns
Note 2
KT
—
1.25
—
μs
VTref
—
2
—
V
HV98100
Control Circuit
Internal Timing Constant
Internal Voltage for Timing
GATE On-time
—
2.5
—
V
HV98101
6.83
7.35
7.89
μs
HV98100
Ext Clk = 50 kHz
COMP = 2V
6.11
6.7
7.05
μs
HV98101
Ext CSlk = 50 kHz
COMP = 2V
350
450
550
μA
GATE = LOW
TON
TON
Protection
Over Voltage Protection Current
Threshold
IOVP
OCPREF
2.2
2.35
2.5
V
Over Current Protection Blanking Time
TBLNKOCP
150
—
250
ns
Note 2
Detect time for Over Current Protection
TDETOCP
150
—
250
ns
After TBLNKOCP (Note 2)
Over Current Comparator Delay
OCPDLY
—
50
100
ns
100 mV overdrive (Note 2)
Over Current Protection Reference
Note 1:
2:
Obtained by Design and Characterization; not 100% tested in production.
Design Guidance only.
TABLE 1-1:
TEMPERATURE SPECIFICATIONS
Parameter
Symbol
Min.
Typ.
Max.
Units
Storage Temperature
TA
-65
—
+150
°C
Operating Junction Temperature
TJ
-40
—
+125
°C
JA
—
124
—
°C/W
JC
—
74
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistance
Thermal Resistance, 6L-SOT-23
DS20005640A-page 4
2016 Microchip Technology Inc.
HV98100/HV98101
2.0
TYPICAL OPERATING CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Note: Unless otherwise indicated, TA = TJ = +25°C, PVDD = 12V. Boldface specifications apply over the full temperature
range TA = TJ = -40°C to +125°C.
16.1
460
16.05
455
16
450
15.9
IOVP (uA)
VDD,ON (V)
15.95
15.85
15.8
15.75
15.7
-55
-35
-15
5
25 45
Temperature (°C)
65
85
430
105 125
FIGURE 2-1:
VDD Start Voltage vs.
Junction Temperature.
-35
5
25
45
Temperature (°C)
65
85
105
125
OCPREF (V)
2.39
8
7.95
-55
-35
-15
5
25
45
65
85
105
2.38
2.37
125
-55
-35
Temperature (°C)
FIGURE 2-2:
VDD Stop Voltage vs.
Junction Temperature.
% of Units
200.5
200
199.5
199
-55
-35
-15
5
25 45 65
Temperature (°C)
85
105 125
FIGURE 2-3:
Internal Reference Voltage
vs. Junction Temperature.
2016 Microchip Technology Inc.
-15
5
25
45
Temperature (°C)
65
85
105
125
FIGURE 2-5:
Over Current Protection
Reference vs. Junction Temperature.
201
CSREF (mV)
-15
2.4
8.05
VDD,ON (V)
-55
FIGURE 2-4:
Over Voltage Protection
Current Threshold vs. Junction Temperature.
8.1
7.9
440
435
15.65
15.6
445
50
45
40
35
30
25
20
15
10
5
0
7
7.5
FIGURE 2-6:
Histogram.
8
8.5 9 9.5 10 10.5 11 11.5 12
FSTART (kHz)
Startup Clock Frequency
DS20005640A-page 5
HV98100/HV98101
80
70
% of Units
60
50
40
30
20
10
0
125
135
145
FIGURE 2-7:
Histogram.
155 165
IDD,Q (uA)
175
185
195
205
Quiescent Current
60
50
% of Units
40
30
20
10
0
90
92
94 96 98 100 102 104 106 108 110
Output Current (mA)
FIGURE 2-8:
Application.
DS20005640A-page 6
Output Current Accuracy in
2016 Microchip Technology Inc.
HV98100/HV98101
3.0
PIN DESCRIPTION
The description of the pins are listed in Table 3-1.
TABLE 3-1:
PIN DESCRIPTION
HV98100/HV98101
SOT-23
Symbol
1
IND
Input from LED String Anode for both valley detection and over-voltage protection
Pin
2
GND
Common connection for all circuits Pin
3
COMP
4
CS
3.1
Description
Loop compensation for stable response Pin
Current sense input for sensing inductor current Pin
5
PVDD
Supply Voltage for the IC Pin
6
GATE
Gate driver for driving the external MOSFET Pin
IND
3.2
This pin is used for detecting the valley, as well as for
over-voltage protection. The voltage at pin is maintained at approximately 4.3V. When the switching FET
is off, current is sourced out of this pin. If this current
exceeds 450 μA, then over voltage is detected and the
IC shuts down. This current sourced out of the pin is
also used to detect the valley, using a patented method.
For proper operation, the IND pin should be shielded to
prevent mis-triggering due to the large voltage slew
rates present in application. A recommended layout is
shown in Figure 3-1.
FIGURE 3-1:
Power Ground Pin (GND)
This is the ground pin of the IC. The VDD capacitor and
COMP network should be connected to this pin and the
GND pin should be connected to the sense resistor, as
shown in the Typical Application Circuit for proper
functioning of the IC. Figure 3-2 shows a
recommended layout. Red traces in the layout are on
the top layer, whereas blue traces on the layout are on
the bottom layer.
Shielding the IND Pin.
FIGURE 3-2:
2016 Microchip Technology Inc.
Connection to the GND Pin.
DS20005640A-page 7
HV98100/HV98101
3.3
COMP
This pin is the output of the internal transconductance
amplifier. A compensation network connected between
COMP and GND pins is used to stabilize the closed
loop control of the LED current.
3.4
CS
This pin is used to sense the inductor current. The
inductor current information is used to derive the output
LED current, as well as to protect the inductor from
saturation.
DS20005640A-page 8
3.5
PVDD
This pin is the power supply pin for the IC. A minimum
of 4.7 μF capacitor needs to be connected between
PVDD and GND for stability of the internal shunt regulator. The CPVDD capacitor needs to be placed physically close to the IC to minimize the trace length
between the PVDD pin and the capacitor.
3.6
GATE
This pin is the gate drive output of the IC and is used to
control the switching of the external FET.
2016 Microchip Technology Inc.
HV98100/HV98101
4.0
FUNCTIONAL DESCRIPTION
4.1
Introduction
The HV98100/HV98101 control ICs provide constant
average LED current for LED lamps and fixtures with a
single-stage, valley-switching, buck-boost powersupply topology.
The IC is targeted at designs at a single-line voltage,
such as 110 VAC (HV98100) or 230 VAC (HV98101)
and does not support designs for universal input voltage range.
4.2
Principle of Operation
The IC adopts a novel control mechanism to vary both
on-time and switching period at the same instant over
the line cycle in a way that forces the average input current to be proportional to the input voltage, realizing
high-power factor and low THD which is independent of
the load voltage (VO) (unlike a constant on-time control
where the THD is dependent on the LED string voltage).
In order to determine the LED current regulation, power
balancing is used to maintain the mean programmable
LED current (IO) in a closed-loop manner by means of
the adaptive VCOMP swing upon the defined input/output voltage variation, as shown in Equation 4-1.
EQUATION 4-1:
I
2
V in,rms K V
T
COMP
= --------------------------------------------------------------O
V
O
Assume a VCOMP variation from 1.2V to 3.8V, an input
voltage (VIN,rms) variation of ±15% and the internal timing constant (KT) variation of ±12%. With these
assumptions, the maximum variation in the LED string
voltage (to maintain constant LED current) cannot
exceed ±18% approximately.
2016 Microchip Technology Inc.
DS20005640A-page 9
HV98100/HV98101
5.0
APPLICATION INFORMATION
5.1
Introduction
This section describes the operation of the various
blocks in the IC. Detailed design information, along with
a design example, is provided in Section 6.0 “Design
Example”.
The IC includes an internal VDD clamp circuit. The
clamp limits the voltage on the VDD supply pin to the
maximum value (PVDD,clamp). If the maximum current
supplied through the external resistors minus the current consumption of the IC is lower than the maximum
value that the Zener clamp can sustain (IDD,MAX), no
external Zener diode is required.
5.3
5.2
PVDD Regulator
The supply current is initially fed from the rectified AC
input directly via an external start-up resistor (RHV) to
peak charge a hold-up capacitor (CPVDD) connected at
this pin. Note that a switching diode (DHV) is required in
series to prevent the capacitor from discharging when
the buck-boost converter FET (MBBT) turns on. As the
voltage on the VDD capacitor increases, the IC is held
in a Stand-by mode and draws minimum current
(200 μA max.). Once the voltage at VDD reaches
VDD,ON, the IC turns on and starts switching at an internally fixed switching frequency of 10 kHz, until the valley can be detected. Once the valley is detected, the
converter starts working in the normal Valley-Switching
mode and tries to regulate the LED current. In this
mode, the current drawn by the IC from VDD increases
causing the voltage across the VDD capacitor to start
dropping (since the current supplied by the external
start-up resistor is not sufficient).
If the VDD voltage drops below VDD,OFF, the IC enters
into Stand-by mode and the process starts again. If the
bootstrap from the output capacitor (CO) is available to
prevent the VDD voltage from going below VDD,OFF,
then the LED driver operates normally. In this way, as
shown in Figure 5-1, the PVDD voltage bounces
between VDD,ON and VDD,OFF within a hysteresis band
for the IC to start GATE switching, until the energy
stored in the output capacitor can be partially delivered
to PVDD through the bootstrapping resistor-diode network (RPVDD-DPVDD).
LED Current Regulator
The LED current (IO) is sensed directly using an external sense resistor RCS and compared to an internal
fixed reference (CSREF). An internal transconductance
amplifier is used to close the loop on the LED current
with an external compensation capacitor. The LED current can be programmed as in Equation 5-1.
EQUATION 5-1:
I
5.4
LED
CS
REF= ------------------R
CS
Valley Switching
The driver incorporates valley switching (quasi-resonant switching), a technique for reducing switching loss
at the turn-on event of the buck-boost converter FET.
Valley detect is accomplished by sensing the current
sunk into the IND pin when the GATE is low. The operation is illustrated in Figure 5-2. When the inductor current IL has decreased to zero at t2, the positive LED
voltage VL starts to oscillate around the 0V level (with
respect to the IC GND), with an amplitude VO. The
GATE turns on again when the first lowest level (valley)
is detected.
Gate
0
VL
+Vo
0
valley
VIN
-VIN
magne tization demag netization
IL,max
0
IL
VDDON
PVDD
VDDOF F
0
Toff
Ton
0
t0
3
t1
t2
t00
TS
GT
FIGURE 5-2:
0
However, in case the valley is not detected (during
startup, output short circuit and input voltage zero
crossings), a 10 kHz internal clock is used to start the
next cycle.
VO
0
FIGURE 5-1:
DS20005640A-page 10
Valley Detect Waveforms.
Typical Startup Waveforms.
2016 Microchip Technology Inc.
HV98100/HV98101
5.5
Over-Voltage and Short-Circuit
Protection
5.5.1
OVER-VOLTAGE PROTECTION
Apart from the valley detect, measuring the current
sunk into the IND pin when the GATE is low can be
used to sense an output over voltage or open circuit.
The IND triggering level is IOVP.
When the current into the IND pin exceeds IOVP, the
gate driver shuts down. The PVDD capacitor starts discharging (since there is no bootstrap and the current
through the input start-up resistor is insufficient to
charge the capacitor). Once the voltage at PVDD drops
to VDD,OFF, the IC goes into a low-current mode and the
start-up procedure starts. This process keeps repeating until the over-voltage condition disappears.
5.5.2
SHORT-CIRCUIT PROTECTION
Output short circuit (or input under voltage) causes the
converter to go into Continuous Conduction mode
(CCM) by sensing the inductor current when MBBT is
on.
When the GATE turns on, a leading edge blanking circuit is activated within the IC. The blanking circuit has
two functions:
1.
2.
Gate
Blank the first TBLNKOCP of the GATE on-time.
During this time, RCS will detect the leading
edge spike, and the edge spike is not allowed to
propagate to the comparator since it might
cause false triggering of the OCP comparator.
Allow the OCP comparator to see the next
TDETOCP of the inductor current. Since the
converter is assumed to be in Boundary
Conduction mode during normal operation,
when the GATE turns on, the inductor current
will start at zero and start ramping up. The IC
compares the second voltage across RCS in the
detect window after the GATE turns on and
determines if the converter is operating in CCM.
0
CS
Voltage +Vo
0.2Vo
0
OCP
+ve
input
OCP_Ref
TDET
0
TDET
OCP
TBLANK
TBLANK
0
FIGURE 5-3:
Operation.
Waveforms During Normal
Gate
0
CS
Voltage +Vo
0.2Vo
0
OCP
+ve
input
OCP_Ref
0
TDET
TDET
OCP
TBLANK
TBLANK
0
FIGURE 5-4:
Circuit.
Waveforms During Short
If the IC detects four consecutive cycles of CCM, the
GATE is turned off and the IC goes through a POR.
Typical waveforms are shown in Figures 5-3 and 5-4.
2016 Microchip Technology Inc.
DS20005640A-page 11
HV98100/HV98101
6.0
DESIGN EXAMPLE
This section describes the procedure to design an
HV98100/HV98101 LED driver. The specifications
used for this example are:
EQUATION 6-4:
T ON,max
1
1
----------------------- = ---------------------------------------------------- = --------------------------------------- = 0.31
T S,max
2 V IN,min,rms
2 195.5V1
+
----------------------------1 + ------------------------------------------122V
V O,max
• Input: 230 VAC r.m.s ±15%, 50 Hz
• Output Current: 150 mA
• LED String Voltage: 88V - 122V
Combining Equations 6-2, 6-3 and 6-4:
6.1
EQUATION 6-5:
Power stage design
6.1.1
CALCULATING INPUT CURRENT
T S ,max
I L,max,pk = 2 I IN,max,peak ------------------------T ON ,max
1
= 2 156 mA ---------- = 1 A
0.31
The maximum output power (POmax) can be computed
as:
EQUATION 6-1:
P
O max
= V
O max
I
O
= 122V 150 mA = 18.3W
Assuming a sinusoidal input current wave-shape, the
peak input current at the minimum input voltage and
maximum output power can be computed to be:
EQUATION 6-2:
2 P O max
2 18.3W - = 156 mA
I IN , max, pk = ---------------------------------------- = -------------------------------V IN ,min,rms
195.5V 0.85
Assuming a minimum switching frequency of 30 kHz,
the inductor value can be computed as:
EQUATION 6-6:
T S max
33.33 s - = 10.2 s
- = --------------------------------------T ON,max = ---------------------------------------------------2 V IN,min,rms
2 195.5V1
+
----------------------------1 + ------------------------------------------122V
V O,max
EQUATION 6-7:
2 V IN,min,rms T ON,max
L BBT = ---------------------------------------------------------------------I L,max,pk
where:
ƞ = the assumed efficiency of the converter
6.1.2
SELECTING THE INDUCTOR
The typical inductor current waveform for a Boundary
Conduction mode buck-boost converter is shown in
Figure 5-2. Ignoring the dead-time, the peak input current can be expressed as a function of the peak inductor current.
EQUATION 6-3:
T ON , max
1
I IN , max, peak = --- I L, max, pk -------------------------2
T S , max
Since a Boundary Conduction mode converter has the
same DC transfer function as a Continuous Conduction
mode (CCM) converter, the ratio of the on-time to the
switching frequency can be expressed as:
DS20005640A-page 12
2 195.5V 10.2 s- = 2.79 mH
= ---------------------------------------------------1A
The inductor peak current has already been computed
in Equation 6-5. The r.m.s current can be computed
using:
EQUATION 6-8:
K IL =
=
2
2 V IN,min,rms
8 2 V IN,min,rms 1
--------------------------------------------------- + -------------------------------------------------+ --2
9 V O,max
6
8 V O,max
2
------------------------------------2 195.5V - + 8----------------------------------- 2 195.5V- + 1--2
9 122V
6
8 122V
= 1.204
2016 Microchip Technology Inc.
HV98100/HV98101
EQUATION 6-9:
EQUATION 6-13:
4 V O,max I O
I L,rms = K IL -------------------------------------------------n 2 V IN,min,rms
4 122V 0.15 A
= 1.204 ------------------------------------------------0.85 2 195.5V
= 0.375 A
6.1.3
SELECTING THE SWITCHING FET
The voltage rating of the switching FET should be:
I DBBT avg = I O = 0.15 A
EQUATION 6-14:
2 V IN min rms 3 2 V IN min rms
4
------------------------------------------------ -------------------------------------------------------- + ---------
3 V O max
8 V O max
3
K ID =
=
2 195.5V- 3---------------------------------------- 2 195.5V - + ---------4
----------------------------
3 122V
8 122V
3
= 0.981
EQUATION 6-10:
BV DSS,min = 1.3 2 V IN,max,rms + V O,max
EQUATION 6-15:
= 1.3 2 264.5V + 122V = 645V
4 V O,max I O
I DBBT ,max,rms = ---------------------------------------------------- K ID
n 2 V IN ,min,rms
A 650V rated switching FET should be chosen for this
application.
4 122V 0.15 A- 0.981 = 0.306 A
= -------------------------------------------0.85 2 195.5V
The r.m.s current through the FET is:
EQUATION 6-11:
EQUATION 6-16:
I Q,rms,max =
4 122V 0.15 A- 1--- 4 2 195.5V 1
-------------------------------------------
------------------------------------------ + --2
0.85 2 195.5 3 3 122V
= 217.48 mA
The Rdson of the FET can be computed assuming a 3%
power loss at maximum output power and minimum
input voltage.
EQUATION 6-12:
0.03 P O,max
18.3W- = 7.77
Rds on 25C = ---------------------------------= 0.03
-----------------------------2
2
1.5 I Q,rms
1.5 0.217
The 1.5 factor in the denominator is used to account for
the higher FET resistance in actual operation due to
higher junction temperature.
6.1.4
SELECTING THE SWITCHING
DIODE
The voltage rating of the switching diode should match
or exceed the voltage rating of the switching FET. A
high-speed diode with reverse recovery time in the
order of 50 ns should be chosen for this application.
The peak, r.m.s and average current through the diode
can be computed using the following equations:
2016 Microchip Technology Inc.
6.1.5
CHOOSING THE OUTPUT
CAPACITOR
The output capacitor is chosen based on the maximum
allowable line frequency ripple in the LED current. This
can be computed if the desired flicker index is known.
Light Output (lm)
4 V O,max I O
4 2 V IN ,min,rms 1
------------------------------------------------------- 1--- ------------------------------------------------------- + --- =
3
3 V O,max
2
n 2 V IN ,min,rms
I DBBT peak = I L ,max , pk = 1.0 A
Area 1
Avg Light
Output
Area 2
Time (s)
FIGURE 6-1:
Flicker Index.
For a given instantaneous light output waveform
(shown in Figure 6-1), the flicker index can be computed to be:
DS20005640A-page 13
HV98100/HV98101
EQUATION 6-17:
EQUATION 6-23:
Area1
FI = ------------------------------------------------ Area1 + Area2
I Co rms =
2
2
I DBBT max rms – I O =
2
2
0.305 A – 0.15 A = 0.265A
where:
Area1 = the area of the curve above the average
Area2 = the area of the curve below the average
Assuming that the instantaneous light output is directly
proportional to the instantaneous LED current, the
flicker index can be computed from the instantaneous
LED current waveform shown in Figure 6-1.
EQUATION 6-18:
IO
FI = --------------------2 IO
6.1.6
The input capacitor is selected to reduce the input
ripple voltage. A simple first-pass selection can be
computed as:
EQUATION 6-24:
0.5 I L ,max , pk T ON max
C REC = -----------------------------------------------------------------------0.1 2 V IN min rms
0.5 1 A 10.2s
= ---------------------------------------------- = 0.185F
0.1 2 195.5V
I O = 2 FI I O = 2 0.15 0.15 A = 0.14 A
The typical LED string dynamic resistance can be
computed as:
EQUATION 6-19:
V O max
122V
R LED = 0.05 ---------------------- = 0.05 -------------= 40.67
IO
0.15 A
The corresponding line frequency peak-to-peak ripple
in the output voltage is:
EQUATION 6-20:
V O = I O R LED = 0.14 A 40.67 = 5.69V
SELECTING THE INPUT
CAPACITOR
This capacitor will need to be adjusted in once a prototype is built. A large value will increase the THD where
as a low value will affect the EMI performance.
6.2
6.2.1
Control Stage Design
SELECTING THE CURRENT SENSE
RESISTOR
The current sense resistor value is set by the output
current. The resistor’s power rating is set by the
inductor current.
EQUATION 6-25:
The output capacitor is usually dominated by the
low-frequency ripple component. It can be computed
using the following equation:
C S REF
0.2V = 1.33
R CS = ------------------- = -------------IO
0.15 A
EQUATION 6-21:
2
2
P Rcs = I L rms R CS = 0.375 A 1.33 = 0.187W
IO
0.15 A
C O = ---------------------------------------- = ------------------------------------------------ = 42F
4 f L V O 4 50 Hz 5.69V
Voltage rating of the output capacitor should be about
20% higher than the maximum output voltage.
EQUATION 6-22:
V CO = 1.2 V O max = 1.2 122V = 146V
6.2.2
SELECTING THE VALLEY SENSE
COMPONENTS
The resistor used for detecting the valley is also used
for over-voltage protection. Hence, the resistor should
be chosen based on the over-voltage setting desired.
Assume a 10% headroom over the maximum output
voltage to set the minimum over-voltage threshold.
Then, the resistor is:
The r.m.s current through the output capacitor is:
EQUATION 6-26:
1.1 V O max – V IND
1.1 122V – 4.3V
R VD = -------------------------------------------------------- = ------------------------------------------- = 371k
I OCP, min
350A
DS20005640A-page 14
2016 Microchip Technology Inc.
HV98100/HV98101
Then maximum output voltage that can occur during
over-voltage conditions is:
EQUATION 6-27:
OV P max = I OCP,max R VD + V IND = 550A 371 k + 4.3V
= 208V
Note that since this is not a continuous operation, the
voltage rating of the output capacitor should be chosen
to withstand this voltage, but not to operate at this voltage continuously.
start-up time will cause higher losses in the resistor
during operation. The start-up time and power loss
should be iterated until a reasonable compromise is
achieved for both parameters.
The minimum capacitor at PVDD required is 4.7 μF. In
most cases this capacitor value is sufficient for hold-up.
Assuming a 100 ms start-up time (TSTRT), the start-up
resistor can be computed as shown in Equation 6-28.
EQUATION 6-28:
The diode in series with this resistor should be a
500 μA switching diode with a breakdown voltage of at
least 400V (250V for a HV98100 design).
2 V in min rms – V DD ON
2 195.5V – 16V R HV = ------------------------------------------------------------------------------ = -----------------------------------------------------4.7F 16V- + 200A
C PVDD V DD ON
--------------------------------------------------------------------------------- + 200A
100ms
T STRT
6.2.3
= 273k
SELECTING THE START-UP
NETWORK
The start-up resistor should be chosen based on the
maximum start-up time that is allowable before the
GATE starts switching. Note that selecting a shorter
The maximum power loss in the resistor occurs at high
line and is shown in Equation 6-29.
EQUATION 6-29:
2 V in max rms 4 V O max + 2 V in max rms
P RHV max = ---------------------------------------------------------------------------------------------------------------------------------------------------2 R HV
2 264.5V 4 122V + 2 264.5V
= --------------------------------------------------------------------------------------------------------- = 0.363W
2 273k
The minimum average current supplied by RHV during
operation is shown in Equation 6-30.
EQUATION 6-30:
2 2 V in min rms
I RHV min avg = ---------------------------------------------------- R HV
2 195.5V= 2----------------------------------- 273k
= 645A
The diode in the start-up network (DHV) can be a simple
1N4148.
6.2.4
SELECTING BOOTSTRAP
COMPONENTS
The total current required by the IC during normal
operation comes from two sources
• Current through RHV
• Current through RPVDD
The current through RHV resistor has been computed in
Equation 6-28. The average current supplied through
RPVDD is:
2016 Microchip Technology Inc.
EQUATION 6-31:
Vˆ IN sin
1 V O – PV DD
- d
I RPVDD,AVG = --- --------------------------------- ----------------------------------------- R PVDD
V O + Vˆ IN sin
0
However, the closed form solution for the integral in
Equation 6-31 is very complex. The equation can be
simplified using a curve fit solution.
EQUATION 6-32:
I RPVD D
=
AVG
ˆ
V O – PV DD
V IN
--------------------------------- 0.193 ln ---------- + 0.3801
R PVDD
VO
This approximation is valid as long as
ˆ
V IN
- 10
2 ---------VO
DS20005640A-page 15
HV98100/HV98101
Assuming we need a total current of about 4 mA during
normal operation, the RPVDD resistor can be chosen
as:
EQUATION 6-33:
R PVDD =
ˆ
V O ,min – PV DD
V IN
---------------------------------------------- 0.193 ln ------------------- + 0.3801
I PVDD – I RHV
VO,min
88V – 16V
2 195.5V- + 0.3801
= ---------------------------------------- 0.193 ln ----------------------------
88V
4 mA – 645 A
= 12 k
The power dissipated in the RPVDD resistor can be
computed as:
EQUATION 6-34:
ˆ
V O – PV DD
V IN
- + 0.3801
I RPVDD,rms = --------------------------------- 0.193 ln ---------R PVDD
Vo
2 195.5V- + 0.3801
– 16V- 0.193 ln ----------------------------= 88V
-------------------------
88V
12.9k
= 4.33 mA
2
P RPVDD = I RPVDD rms R PVDD
2
= 4.33 mA 12.9 k = 0.242W
The average current drawn by the IC is not easy to estimate. It is recommended to start with an assumed
higher value for the current consumed by the IC
(4 mA-5 mA) and increase RPVDD by trial and error.
The bootstrap diode should have a voltage rating of at
least 400V (at least 250V for an HV98100 design) and
an average current rating of about 5 mA. This should
be a switching diode with a very low-junction capacitance (< 10 pF preferable).
6.2.5
CHOOSING THE COMPENSATION
CAPACITOR
The compensation capacitor serves two functions in a
power factor correction circuit:
• maintain loop stability
• reduce third harmonic distortion in the input current.
The capacitor can be chosen based on either criteria.
For this design example, the capacitor is chosen based
on the third harmonic distortion criterion. This criterion
leads to a larger compensation capacitor value which
also ensures stability in most cases.
The second harmonic component of the COMP voltage
causes third harmonic distortion in the input current.
The criterion used to design the compensation capacitor is that the second harmonic peak-to-peak voltage in
COMP voltage is 2% of the DC component of the
COMP voltage.
Equation 6-35 shows the relation between the input
current and the DC component of the COMP voltage.
EQUATION 6-35:
1 V IN rms min 2 K T COMP
I IN rms max = --- ------------------------------------- --------------------------------------2
L
V TREF
Substituting values in Equation 6-35:
EQUATION 6-36:
2 2.79mH 110 mA 2.5V- = 3.14V
COMP = -----------------------------------------------------------------2 195.5V 1.25 s
The compensation capacitor can be computed as:
EQUATION 6-37:
I O R CS g m
C COMP = -----------------------------------------------------------------=
2 2 f L V COMP
A0.14 A 1.3 230 --V - = 1.11F
-----------------------------------------------------------2 2 50 Hz 0.06V
Note:
DS20005640A-page 16
The design of the EMI filter is beyond the
scope of this design example. The design
example is intended to provide a first pass
design that can be further optimized in
hardware.
2016 Microchip Technology Inc.
HV98100/HV98101
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
6-Lead, SOT-23
(HV98100/HV98101)
XXNN
2016 Microchip Technology Inc.
Example
Product Number
Code
HV98100T-E/CH
S6NN
HV98101T-E/CH
S7NN
S625
DS20005640A-page 17
HV98100/HV98101
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