HV9930
Hysteretic Boost-Buck (Ćuk) LED Driver IC
Features
General Description
•
•
•
•
•
•
•
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The HV9930 is a variable frequency PWM controller IC
designed to control an LED lamp driver using a
low-noise boost-buck (Ćuk) topology. The HV9930
uses a patented Hysteretic Current-mode control to
regulate both the input and output currents. This
enables superior input surge immunity without the
necessity for complex loop compensation. Input
current control enables current limiting during Startup,
Input Undervoltage, and Output Overload conditions.
The HV9930 provides a low-frequency PWM dimming
input that can accept an external control signal with a
duty cycle of 0% to 100% and a high dimming ratio.
Constant Output Current LED Driver
Steps Output Voltage Up or Down
Low EMI
Variable Frequency Operation
Internal 8V to 200V Linear Regulator
Input and Output Current Sensing
Input Current Limit
Enable and Pulse-Width Modulation (PWM)
Dimming
Applications
• RGB Backlight Applications
• Battery-Powered LED Lamps
• Other Low-Voltage AC/DC or DC/DC LED Drivers
The HV9930-based LED driver is ideal for LED lamps
and RGB backlight applications with low-voltage DC
inputs. The HV9930-based LED Lamp drivers can
achieve efficiency in excess of 80%.
Package Type
8-lead SOIC
(Top view)
VIN
1
8
REF
CS1
2
7
CS2
GND
3
6
VDD
GATE
4
5
PWMD
See Table 2-1 for pin information.
2019 Microchip Technology Inc.
DS20005682A-page 1
HV9930
Functional Block Diagram
Regulator
VIN
VDD
7.5V
Input
Comparator
CS1
L
GATE
H
105mV 20mV
CS2
Output
Comparator
REF
PWMD
1.25V
HV9930
DS20005682A-page 2
GND
2019 Microchip Technology Inc.
HV9930
Typical Application Circuit
C1
D2
L1
RD
CD
L2
VDC
RCS1
Q1
D1
D3
VO
+
RCS2
RS2A
C2
RS1
VIN
GATE
RREF1
2019 Microchip Technology Inc.
VDD
PWMD
CS1
CS2
GND
REF
HV9930
RS2B
RREF2
C3
DS20005682A-page 3
HV9930
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VIN to GND ..............................................................................................................................................–0.5V to +200V
VDD to GND...............................................................................................................................................–0.3V to +12V
CS1, CS2, PWMD, GATE, REF to GND .......................................................................................–0.3V to (VDD + 0.3V)
Junction Temperature, TJ .................................................................................................................... –40°C to +150°C
Storage Temperature, TS ..................................................................................................................... –65°C to +150°C
Continuous Power Dissipation (TA = +25°C):
8-lead SOIC ............................................................................................................................................ 650 mW
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Specifications are at TA = 25°C. VIN = 12V unless otherwise noted.
Parameter
Sym.
Min.
Typ.
Max.
Unit
Conditions
INPUT
Input DC Supply Voltage Range
VINDC
8
—
200
V
Shutdown Mode Supply Current
IINSD
—
0.5
1
mA
VDD
7
7.5
9
V
VDD Current available
for External Circuitry
IDD(EXT)
—
—
1
mA
VDD Undervoltage Lockout Upper
Threshold
UVLOR
6.45
6.7
6.95
V
VDD Undervoltage Lockout
Hysteresis
∆UVLO
—
500
—
mV
Steady State External Voltage
which can be applied at the VDD
pin
VDD(EXT)
—
—
12
V
INTERNAL REGULATOR
VDD Internally Regulated Voltage
DC input voltage (Note 1)
PWMD connected to GND (Note 1)
VIN = 8V to 200V, IDD(EXT) = 0 mA,
GATE open
VIN = 8V to 200V (Note 2)
VDD rising
REFERENCE
REF Pin Voltage
Line Regulation of Reference
Voltage
Load Regulation of Reference
Voltage
VREF
∆VREF,LN
1.212
0
∆VREF,LD
0
PWMD Input Low Voltage
VPWMD(LO)
PWMD Input High Voltage
VPWMD(HI)
1.25
—
1.288
20
V
REF bypassed with a 0.1 µF
capacitor to GND, IREF = 0 µA,
VDD = 7.5V, VPWMD = 5V,
VIN = open (Note 1)
mV
REF bypassed with a 0.1 µF capacitor to GND, IREF = 0 µA,
VDD = 7V to 10V, VPWMD = 5V,
VIN = open
REF bypassed with a 0.1 µF capacitor to GND, IREF = 0 µA to 500 µA,
VDD = 7.5V, VPWMD = 5V,
VIN = open
—
25
mV
—
—
0.8
V
2
—
—
V
PWM DIMMING
VIN = 10V to 200V (Note 1)
VIN = 10V to 200V (Note 1)
Note 1: Specifications apply over the full operating ambient temperature range of –40ºC < TA < +125ºC.
2:
Also limited by package power dissipation limit, whichever is lower
DS20005682A-page 4
2019 Microchip Technology Inc.
HV9930
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Specifications are at TA = 25°C. VIN = 12V unless otherwise noted.
Parameter
Sym.
Min.
Typ.
Max.
Unit
RPWMD
50
100
150
kΩ
ISOURCE
0.165
—
—
A
VGATE = 0V, VDD = 7.5V, VIN = open
GATE Sinking Current
ISINK
0.165
—
—
A
VGATE = VDD, VDD = 7.5V,
VIN = open
GATE Output Rise Time
tRISE
—
30
50
ns
CGATE = 500 pF, VDD = 7.5V,
VIN = open
GATE Output Fall Time
tFALL
—
30
50
ns
CGATE = 500 pF, VDD = 7.5V,
VIN = open
PWMD Pull-Down Resistance
GATE DRIVER
GATE Short Circuit Sourcing
Current
INPUT CURRENT SENSE COMPARATOR
Conditions
VPWMD = 5V
Voltage Threshold
for GATE Turn-On
VON1
90
105
120
mV
VCS2 = 200 mV, VCS1 increasing,
GATE goes LOW to HIGH (Note 1)
Voltage Threshold
for GATE Turn-Off
VOFF1
0
20
40
mV
VCS2 = 200 mV, VCS1 decreasing,
GATE goes HIGH to LOW (Note 1)
Delay to Output (Turn-On)
tD,ON1
—
80
150
ns
VCS2 = 200 mV,
VCS1 = 50 mV to +200 mV step
Delay to Output (Turn-Off)
tD,OFF1
—
80
150
ns
VCS2 = 200 mV,
VCS1 = 50 mV to –100 mV step
OUTPUT CURRENT SENSE COMPARATOR
Voltage Threshold
for GATE Turn-On
VON2
90
105
120
mV
VCS1 = 200 mV, VCS2 increasing,
GATE goes LOW to HIGH (Note 1)
Voltage Threshold
for GATE Turn-Off
VOFF2
0
20
40
mV
VCS1 = 200 mV, VCS2 decreasing,
GATE goes HIGH to LOW (Note 1)
Delay to Output (Turn-On)
tD,ON2
—
80
150
ns
VCS1 = 200 mV,
VCS2 = 50 mV to +200 mV step
Delay to Output (Turn-Off)
tD,OFF2
—
80
150
ns
VCS1 = 200 mV,
VCS2 = 50 mV to –100 mV step
Note 1: Specifications apply over the full operating ambient temperature range of –40ºC < TA < +125ºC.
2:
Also limited by package power dissipation limit, whichever is lower
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
Operating Ambient Temperature
TA
–40
—
+125
°C
Maximum Junction Temperature
TJ(ABSMAX)
—
—
+150
°C
TS
–65
—
+150
°C
JA
—
+101
—
°C/W
Conditions
TEMPERATURE RANGE
Storage Temperature
PACKAGE THERMAL RESISTANCE
8-lead SOIC
2019 Microchip Technology Inc.
DS20005682A-page 5
HV9930
2.0
PIN DESCRIPTION
The details on the pins of HV9930 are listed in
Table 2-1. Refer to Package Type for the location of
the pins.
TABLE 2-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
1
VIN
This pin is the input of an 8V to 200V voltage regulator.
2
CS1
This pin is used to sense the input current of the boost-buck converter. It is the
non-inverting input of the internal input comparator.
3
GND
This is the ground return for all the internal circuitry. This pin must be electrically
connected to the ground of the power train.
4
GATE
This pin is the gate driver output for an external N-channel power Metal-oxide
Semiconductor Field-effect Transistor (MOSFET).
5
PWMD
When this pin is left open or pulled to GND, the gate driver is disabled. Pulling the pin to
a voltage greater than 2V will enable the gate drive output.
6
VDD
This is a power supply pin for all internal circuits. It must be bypassed to GND with a
low-ESR capacitor to GND.
7
CS2
This pin is used to sense the output current of the boost-buck converter. It is the
non-inverting input of the internal output comparator.
8
REF
This pin provides accurate reference voltage. It must be bypassed with a
0.01 µF to 0.1 µF capacitor to GND.
DS20005682A-page 6
Description
2019 Microchip Technology Inc.
HV9930
3.0
DETAILED DESCRIPTION
3.1
Power Topology
The HV9930 is optimized to drive a Continuous
Conduction Mode (CCM) boost-buck DC/DC converter
topology commonly referred to as Ćuk converter. (See
Typical Application Circuit.) This power converter
topology offers numerous advantages useful for driving
high-brightness light-emitting diodes (HB LED). These
advantages include step-up or step-down voltage
conversion ratio and low input and output current
ripple. The input and output inductors can also share a
common core to achieve ripple current cancellation.
The output load is decoupled from the input voltage
with a capacitor, making the driver inherently
failure-safe for the output load.
The HV9930 offers a simple and effective control
technique for a boost-buck LED driver. It uses two
Hysteretic mode controllers—one for the input and one
for the output. The outputs of these two hysteretic
comparators are logically being AND together and are
used to drive the external FET. This control scheme
gives accurate current control and constant output
current in the presence of input voltage transients
without the need for complicated loop design.
3.2
Input Voltage Regulator
The HV9930 can be powered directly from its VIN pin
that takes voltage from 8V up to the maximum of 200V.
When voltage is applied to the VIN pin, the HV9930
attempts to regulate a constant 7.5V (typical) at the
VDD pin. The regulator also has a built-in undervoltage
lockout which shuts off the IC when the voltage at the
VDD pin falls below the UVLO lower threshold.
The VDD pin must be bypassed by a low-ESR capacitor
(≥0.1 μF) to provide a low-impedance path for the
high-frequency current of the output gate driver.
The IC can also be operated by supplying a voltage at
the VDD pin greater than the internally regulated
voltage. This will turn off the internal linear regulator
and the IC will function by drawing power from the
external voltage source connected to the VDD pin.
In case of input transients that reduce the input voltage
below 8V (e.g. Cold Crank condition in an automotive
system), the VIN pin of the HV9930 can be connected
to the external MOSFET drain through a diode. Since
the drain of the FET is at a voltage equal to the sum of
the input and output voltages, the IC will still be
operational when the input goes below 8V. In these
cases, a larger capacitor is needed for the VDD pin to
supply power to the IC when the MOSFET switches on.
2019 Microchip Technology Inc.
3.3
Reference
An internally trimmed voltage reference of 1.25V
(± 3%) is provided at the REF pin. The reference can
supply a maximum output current of 1 mA to drive
external circuitry. This reference can be used to set the
current-sense voltage thresholds of the two
comparators as shown in the Typical Application
Circuit.
3.4
Current Comparators
The HV9930 features two identical comparators with a
built-in 85 mV hysteresis. When the GATE is low, the
inverting terminal is connected to 105 mV, but when the
GATE is high, it is connected to 20 mV. One comparator
is used for the input current control and the other is
used for the output current control.
The input side hysteretic controller is in operation only
during Start-up and Overload conditions. This ensures
that the input current never exceeds the designed
value. During normal operation, the input current will be
less than the programmed current. Therefore, the
output of the input side comparator will be high. The
output of the AND gate will then be dictated by the
output current controller.
The output side hysteretic comparator will be in
operation during the Steady state operation of the
circuit. This comparator turns the MOSFET on and off
based on the LED current.
The use of these comparators in a boost-buck topology
is a patented technique, which eliminates the need for
compensation components.
3.5
PWM Dimming
PWM dimming can be achieved by applying a PWM
signal to the PWMD pin. When the PWMD pin is pulled
high, the gate driver is enabled and the circuit operates
normally. When the PWMD pin is left open or
connected to GND, the gate driver is disabled and the
external MOSFET turns off. The signal at the PWMD
pin inhibits the driver only and the IC need not go
through the entire start-up cycle each time, ensuring a
quick response time for the output current.
The flying capacitor in the Ćuk converter (C1) is initially
charged to the input voltage VDC (through diodes D1
and D2). When the circuit is turned on and reaches
Steady state, the voltage across C1 will be VDC+VO. In
the absence of diode D2, when the circuit is turned off,
capacitor C1 will discharge through the LEDs and the
input voltage source VDC. Thus, during PWM dimming,
if capacitor C1 has to be charged and discharged each
cycle, the transient response of the circuit will be
limited. By adding diode D2, the voltage across
capacitor C1 is held at VDC+VO even when the circuit is
turned off, enabling the circuit to return quickly to its
Steady state (and bypassing the start-up stage) upon
being enabled.
DS20005682A-page 7
HV9930
4.0
APPLICATION INFORMATION
4.1
Overvoltage Protection
Overvoltage protection can be added by splitting the
output side resistor RS2 into two components (RS2A
and RS2B) and adding a Zener diode D3. When there is
an Open LED condition, the diode D3 will clamp the
output voltage, and the Zener diode current will be
sensed by the sum of RS2A and RCS2. The current will
also be regulated by the converter.
4.2
Damping Circuit
The Ćuk converter is inherently unstable when the
output current is being controlled. An uncontrolled input
current will lead to an undamped oscillation between L1
and C1, causing excessively high voltages across
capacitor C1. To prevent these oscillations, a damping
circuit consisting of RD and CD is applied across the
capacitor C1. This damping circuit will stabilize the
circuit and help maintain the proper operation of the
converter.
The values of the damping network can be computed
with Equation 4-1 and Equation 4-2.
EQUATION 4-1:
D MAX 3
IO 2
C D = 9 ----------------------- L 1 -------
1 – D MAX
V O
Where DMAX is the maximum switching duty cycle, L1 is the
inductance of the input inductor, IO is the output LED current,
and VO is the voltage across the output LED string.
EQUATION 4-2:
3 D MAX
L1 IO
R D = ------------------------------2 -------------------CD VO
1 – D MAX
The maximum switching duty cycle is calculated with
Equation 4-3.
EQUATION 4-3:
VO
D MAX = ---------------------------------------------------------------------V O + MIN V IN MIN – V D
Where ηMIN is the minimum efficiency, and VIN,MIN is the
minimum input voltage.VD is the input diode forward voltage.
RMS current of the damping capacitor is determined
with Equation 4-4.
EQUATION 4-4:
V C1
I CD RMS = ----------------------12 R D
Where ΔVC1 is the peak-to-peak ripple voltage of the flying
capacitor C1 and it is 10% of the average voltage across C1.
DS20005682A-page 8
The power dissipation in RD is calculated with
Equation 4-5.
EQUATION 4-5:
2
V C1
P RD = -------------------12 R D
4.3
Output Current Level and Input
Current Limit
The current sense resistor RCS2, combined with the
other resistors RS2 and RREF2, determines the output
current level at undimmed full brightness. On the other
hand, the current sense resistor RCS1, combined with
the other resistors RS1 and RREF1, determines the input
average current limit.
Each set of resistors for the output side or the input side
can be chosen using Equation 4-6 and Equation 4-7.
EQUATION 4-6:
RS
V ON + V OFF
V ON + V OFF
I R CS = V REF – ----------------------------------- ------------ – ------------------------------
R REF
2
2
Where I is the average current (either IO or IIN), VREF
(1.25V typical) is the reference voltage, VON (0.105V
typical) is the threshold voltage for the GATE On, and VOFF
(0.02V typical) is the threshold voltage for the GATE Off.
EQUATION 4-7:
RS
I R CS = V ON – V OFF ------------ + V ON – V OFF
R REF
Where ΔI is the peak-to-peak ripple in the current
(either ΔIO or ΔIIN).
By solving the Equation 4-6 and Equation 4-7, the
value of RS/RREF can be obtained from Equation 4-8.
EQUATION 4-8:
I V ON + V OFF
------ ----------------------------------- + V ON – V OFF
RS
2
I
------------ = ----------------------------------------------------------------------------------------------------------------R REF
V ON + V OFF
I
------ V REF – ----------------------------------- – V ON – V OFF
2
I
The value of RREF can be set as 10 kΩ for
convenience. Then, the value of RS can be chosen
from the calculated value of RS/RREF. The value of RCS
is then computed from Equation 4-9.
EQUATION 4-9:
R CS
RS
V ON + V OFF
V ON + V OFF
V REF – ----------------------------------- ------------ – ----------------------------------2
2
R REF
= -----------------------------------------------------------------------------------------------------------------------I
2019 Microchip Technology Inc.
HV9930
4.4
Design and Operation of the
Boost-buck Converter
For details on the design for a boost-buck converter
using the HV9930 and the calculation of the damping
components, refer to application notes AN-H51
Designing a Boost-Buck (Ĉuk) Converter with the
HV9930/AT9933 and AN-H58 Improving the Efficiency
of a HV9930/AT9933 Controlled Boost-Buck
Converter.
4.5
Design Example
The choice of the resistor dividers to set the input and
output current levels is illustrated by means of the
design example given below.
The parameters of the power circuit are:
V IN MIN = 9V
V IN MAX = 16V
V O = 28V
I O = 0.35A
f S MIN = 300kHz
Using these parameters, the values of the power stage
inductors and capacitor can be computed. (See figures
below.) Refer to Application Note AN-H51 for more
details.
L 1 = 82H
L 2 = 150H
C 1 = 0.22F
The input and output currents for this design are:
I IN MAX = 1.6A
I IN = 0.21A
I O = 350mA
I O = 87.5mA
For the input side, the average current limit level used
in the equations should be larger than the operating
maximum average input current, so it does not interfere
with the normal operation of the circuit. The peak input
current can be computed as shown in Equation 4-10.
Setting
I LIN MIN = 0.85 I IN LIM
I LIN MIN = 1.05 I IN PK
The average input current limit of the converter can
then be computed. See Equation 4-12.
EQUATION 4-12:
1.05
I IN LIM = ---------- I IN PK
0.85
= 2.1A
Using IO = 0.35A and ΔIO = 0.25 × IO = 0.0875A for the
output side in Equation 4-8 and Equation 4-9,
RS2/RREF2 = 0.475 and RCS2 = 1.43Ω are obtained.
Before the design of the output side is complete,
overvoltage protection has to be included in the design.
For this application, choose a 33V Zener diode. This is
the voltage at which the output will clamp in case of an
Open LED condition. For a 350 mW diode, the
maximum current rating at 33V works out to about
10 mA. Using a 2.5 mA current level during Open LED
conditions, and assuming the same RS2/RREF2 ratio,
and splitting RS2 into RS2A and RS2B, the Zener current
limiting resistor can be determined as illustrated in
Equation 4-13.
EQUATION 4-13:
R CS2 Z = R CS2 + R S2A = 120
Choose the following values for the resistors on the
output side:
RCS2 = 1.43Ω, 1/4W, 1%
RREF2 = 10 kΩ, 1/8W, 1%
RS2A = 110Ω, 1/8W, 1%
RS2B = 4.64 kΩ, 1/8W, 1%
The current sense resistor needs to be at least a 1/4W,
1% resistor. Similarly, using IIN,LIM = 2.1A and ΔIIN,LIM
= 0.3 x IIN,LIM = 0.63A for the input side in Equation 4-8
and Equation 4-9, the following values can be
determined:
R S1
-------------- = 0.382
R REF1
R CS1 = 0.187
EQUATION 4-10:
I IN PK
EQUATION 4-11:
I IN
= I IN MAX + -----------
2
= 1.705A
Assuming a 30% peak-to-peak input current ripple to
average input current ratio when the converter is in
Input Current Limit mode, the minimum value of the
input current in the Input Current Limit mode is
calculated as shown in Equation 4-11.
2019 Microchip Technology Inc.
P RCS1 = I
2
IN LIM
R CS1
= 0.825W
Choose the following values for the resistors on the input
side:
RCS1 = parallel combination of three 0.56Ω, 1/2W, 5%
resistors
RREF1 = 10kΩ, 1/8W, 1%
RS1 = 3.82kΩ, 1/8W, 1%
DS20005682A-page 9
HV9930
5.0
PACKAGING INFORMATION
5.1
Package Marking Information
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005682A-page 10
8-lead SOIC
Example
XXXXXXXX
e3 YYWW
NNN
HV9930LG
e3 1912
236
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2019 Microchip Technology Inc.
HV9930
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
2019 Microchip Technology Inc.
DS20005682A-page 11
HV9930
NOTES:
DS20005682A-page 12
2019 Microchip Technology Inc.
HV9930
APPENDIX A:
REVISION HISTORY
Revision A (November 2019)
• Converted Supertex Doc# DSFP-HV9930 to
Microchip DS20005682A
• Changed the quantity of the 8-lead SOIC LG
package from 2500/Reel to 3300/Reel
• Made minor text changes throughout the document
2019 Microchip Technology Inc.
DS20005682A-page 13
HV9930
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
Device
-
Package
Options
X
-
Environmental
X
Media Type
Device:
HV9930
=
Hysteretic Boost-Buck (Ćuk) LED Driver IC
Package:
LG
=
8-lead SOIC
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Type:
(blank)
=
3300/Reel for an LG Package
DS20005682A-page 14
Example:
a)
HV9930LG-G:
Hysteretic Boost-Buck (Ćuk) LED
Driver IC, 8-lead SOIC Package,
3300/Reel
2019 Microchip Technology Inc.
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chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
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LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2019 Microchip Technology Inc.
ISBN: 978-1-5224-5218-8
DS20005682A-page 15
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DS20005682A-page 16
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2019 Microchip Technology Inc.
05/14/19
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