LAN7430/LAN7431
Low Power PCIe to Gigabit Ethernet Controller with Integrated Ethernet MAC / PHY
Highlights
Product Features
• Single Chip PCIe to 10/100/1000 Ethernet Controller with integrated:
• Gigabit Ethernet PHY (LAN7430)
-
PCIe 3.1 PHY supporting 1 Lane at 2.5GT/s
PCIe 3.1 Endpoint Controller
Gigabit Ethernet PHY (LAN7430)
RGMII v1.3 and v2.0 / MII (LAN7431)
-
Master and Slave Ordinary clock support
End-to-end or peer-to-peer support
PTP multicast and unicast message support
PTP message transport over IPv4/v6, IEEE
802.3
• IEEE Std 1588TM-2008 PTP
• Power Management
- PCI-PM and ASPM L0s and L1
- L1.1 and L1.2 PCIe sub-states support
- D3 hot / cold with VAUX detection for PME
wakeup
- Wake on LAN support (WoL, AOAC)
- IEEE 802.3az Energy Efficient Ethernet (EEE)
with 100BASE-TX/1000BASE-T Low Power Idle
and 10BASE-Te TX Amplitude Reduction
(LAN7430)
Target Applications
•
•
•
•
•
•
•
•
Automotive Infotainment / Telematics
PCIe to Gigabit Ethernet Adapter / Bridge
PCIe to Gigabit Ethernet on Embedded System
Gigabit Backplane
LTE Modem
Networked Cameras
Industrial PC (IPC)
Test Instrumentation / Industrial
System Considerations
• Power and I/Os
- Single 3.3V supply operation with on-chip
Switching and LDO Regulators for core and I/
Os
- GPIOs: 4 (LAN7430), 12 (LAN7431)
- Variable voltage I/O supply (1.8V, 2.5V, or 3.3V)
• Software Support
-
Windows 7, 8, 8.1, 10, and OneCore drivers
Linux driver
Android driver
Windows command line OTP / EEPROM
programming and testing utility
• Packaging
- LAN7430: 48-pin SQFN (7 x 7 mm)
- LAN7431: 72-pin SQFN (10 x 10 mm)
• Environmental
- Commercial temp. range (0°C to +70°C)
- Industrial temp. range (-40°C to +85°C)
- AEC-Q100 Grade 2 Automotive Qualified temp.
range (-40°C to +105°C)
2018-2019 Microchip Technology Inc.
- Auto-Negotiation and Auto-MDIX support
- On-chip termination resistors for differential
pairs
- LinkMD® TDR-Based cable diagnostic to identify faulty copper cabling
- Signal Quality Indicator
- Quiet-WIRE® technology to reduce line emissions and enhance immunity for 100BASE-TX
- Programmable LED Outputs for Link, Activity,
Speed
- Signal Quality Indicator (SQI) support
- IEEE 802.3az Energy Efficient Ethernet (EEE)
• MAC with External Ethernet PHY (LAN7431)
- RGMII supporting Internal Delay, Non-Internal
Delay and Hybrid modes
- MII supporting Fast Ethernet PHY
- Flexibility to operate at 1.8V, 2.5V, or 3.3V
- 9220 Byte Maximum Frame Size
• Gigabit Ethernet MAC includes
- 10/100/1000Mbps half/full-duplex operation
(only full-duplex operation at 1000Mbps)
- Flow control with pause frame for full-duplex
mode
- 100/1000Mbps Low Power Idle for EEE
- MDC/MDIO management for external PHY
- RX frame, link status, EEE wakeup for WoL
• DMA Controller
- Scatter-gather based for efficient data transfer
to/from multiple on-chip RAM locations
- Multi-channel for RX prioritization
• FIFO Controller
- Utilize internal SRAMs to buffer RX and TX traffic between PCIe and Ethernet
- TX LSO and TX Checksum Offload
• Receive Ethernet Packet Filtering
- IP, TCP/UDP, L3, ICMP/IGMP Checksum offload
- IEEE 802.1Q VLAN
- Unicast, Multicast, Broadcast
- Perfect / Hash Address
- Priority based channel selection
- Receive Side Scaling (RSS)
• PME Support
- PCIe WAKE# and Beaconing
- PCIe PME Messaging
- GPIO, Link Change, Ethernet Frame for wakeup
• EEPROM / OTP
- External EEPROM support for MAC address
and PCIe configuration
- Integrated OTP memory for EEPROM displacement
• 1149.1 (JTAG) boundary scan
DS00002631D-page 1
LAN7430/LAN7431
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Errata
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature
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DS00002631D-page 2
2018-2019 Microchip Technology Inc.
LAN7430/LAN7431
Table of Contents
1.0 Preface ............................................................................................................................................................................................ 4
2.0 Introduction ..................................................................................................................................................................................... 8
3.0 Pin Descriptions and Configuration ............................................................................................................................................... 12
4.0 Power Connectivity ....................................................................................................................................................................... 26
5.0 Device Configuration ..................................................................................................................................................................... 30
6.0 Functional Descriptions ................................................................................................................................................................. 31
7.0 Operational Characteristics ........................................................................................................................................................... 48
8.0 Package Information ..................................................................................................................................................................... 69
Appendix A: Data Sheet Revision History ........................................................................................................................................... 73
Product Identification System ............................................................................................................................................................. 74
The Microchip Web Site ...................................................................................................................................................................... 75
Customer Change Notification Service ............................................................................................................................................... 75
Customer Support ............................................................................................................................................................................... 75
2018-2019 Microchip Technology Inc.
DS00002631D-page 3
LAN7430/LAN7431
1.0
PREFACE
1.1
General Terms
TABLE 1-1:
GENERAL TERMS
Term
Description
1000BASE-T
1 Gbps Ethernet over twisted pair, IEEE 802.3 compliant
100BASE-TX
100 Mbps Ethernet over twisted pair, IEEE 802.3 compliant
10BASE-T
10 Mbps Ethernet over twisted pair, IEEE 802.3 compliant
ADC
Analog-to-Digital Converter
AFE
Analog Front End
AN, ANEG
Auto-Negotiation
AOAC
Always on Always Connected
ARP
Address Resolution Protocol
BELT
Best Effort Latency Tolerance
BYTE
8-bits
CSMA/CD
Carrier Sense Multiple Access/Collision Detect
CSR
Control and Status Register
DA
Destination Address
DWORD
32-bits
EC
Embedded Controller
EEE
Energy Efficient Ethernet
FCS
Frame Check Sequence
FIFO
First In First Out buffer
FSM
Finite State Machine
FW
Firmware
GMII
Gigabit Media Independent Interface
GPIO
General Purpose I/O
HOST
External system (Includes processor, application software, etc.)
HW
Hardware. Refers to function implemented by digital logic.
IGMP
Internet Group Management Protocol
LDO
Linear Drop-Out Regulator
Level-Triggered Sticky Bit
This type of status bit is set whenever the condition that it represents is asserted. The
bit remains set until the condition is no longer true, and the status bit is cleared by
writing a zero.
LFSR
Linear Feedback Shift Register
LPM
Link Power Management
lsb
Least Significant Bit
LSB
Least Significant Byte
LTM
Latency Tolerance Messaging
MAC
Media Access Controller
MDI
Medium Dependent Interface
MDIX
Media Independent Interface with Crossover
MEF
Multiple Ethernet Frames
MII
Media Independent Interface
MLT-3
Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a
change in the logic level represents a code bit “1” and the logic output remaining at
the same level represents a code bit “0”.
DS00002631D-page 4
2018-2019 Microchip Technology Inc.
LAN7430/LAN7431
TABLE 1-1:
GENERAL TERMS (CONTINUED)
Term
Description
MSI / MSI-X
Message Signaled Interrupt
N/A
Not Applicable
OTP
One Time Programmable
PCS
Physical Coding Sublayer
PLL
Phase Locked Loop
PMIC
Power Management IC
POR
Power on Reset.
PTP
Precision Time Protocol
QWORD
64-bits
RESERVED
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaranteed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
RGMII
Reduced Gigabit Media Independent Interface
RMII
Reduced Media Independent Interface
RMON
Remote Monitoring
SA
Source Address
SCSR
System Control and Status Registers
SEF
Single Ethernet Frame
SFD
Start of Frame Delimiter - The 8-bit value indicating the end of the preamble of an
Ethernet frame
SMNP
Simple Network Management Protocol
TMII
Turbo Media Independent Interface
UDP
User Datagram Protocol - A connectionless protocol run on top of IP networks
WORD
16-bits
2018-2019 Microchip Technology Inc.
DS00002631D-page 5
LAN7430/LAN7431
1.2
Buffer Types
TABLE 1-2:
BUFFER TYPE DESCRIPTIONS
Buffer
Description
AI
Analog input
AO
Analog output
AIO
Analog bi-directional
ICLK
Crystal oscillator input pin
OCLK
Crystal oscillator output pin
RGMII_I
RGMII compliant input
RGMII_O
RGMII compliant output
IS
Input with Schmitt trigger
OD4
Open-drain output with 4 mA sink
VIS
Variable voltage input with Schmitt trigger
VO8
Variable voltage output with 8 mA sink and 8 mA source
VOD8
Variable voltage open-drain output with 8 mA sink
VO12
Variable voltage output with 12 mA sink and 12 mA source
VOD12
Variable voltage open-drain output with 12 mA sink
VOS12
Variable voltage open-source output with 12 mA source
PU
Internal pull-up with 47μA (typical @ 3.3V). Unless otherwise noted in the pin description,
internal pull-ups are always enabled.
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal
resistors to drive signals external to the device. When connected to a load that must be
pulled high, an external resistor must be added.
PD
Internal pull-down with 47μA (typical @ 3.3V). Unless otherwise noted in the pin
description, internal pull-downs are always enabled.
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load that
must be pulled low, an external resistor must be added.
P
DS00002631D-page 6
Power pin
2018-2019 Microchip Technology Inc.
LAN7430/LAN7431
1.3
Register Bit Types
Table 1-3 describes the register but attributes used throughout this document.
TABLE 1-3:
REGISTER BIT TYPES
Register Bit Type Notation
1.4
1.
2.
3.
4.
5.
6.
7.
8.
Register Bit Description
R
Read: A register or bit with this attribute can be read.
W
Write: A register or bit with this attribute can be written.
RO
Read only: Read only. Writes have no effect.
WO
Write only: If a register or bit is write-only, reads will return unspecified data.
W1S
Write One to Set: Writing a one sets the value. Writing a zero has no effect.
W1C
Write One to Clear: Writing a one clears the value. Writing a zero has no effect.
WAC
Write Anything to Clear: Writing anything clears the value.
RC
Read to Clear: Contents is cleared after the read. Writes have no effect.
LL
Latch Low: Clear on read of register.
LH
Latch High: Clear on read of register.
SC
Self-Clearing: Contents is self-cleared after being set. Writes of zero have no effect.
Contents can be read.
RO/LH
Read Only, Latch High: This mode is used by the Ethernet PHY registers. Bits with
this attribute will stay high until the bit is read. After it a read, the bit will remain high, but
will change to low if the condition that caused the bit to go high is removed. If the bit has
not been read the bit will remain high regardless of if its cause has been removed.
NALR
Not Affected by Lite Reset. The state of NALR bits does not change on assertion of a
lite reset.
NASR
Not Affected by Software Reset. The state of NASR bits does not change on assertion of a software reset.
STKY
This field is “Sticky” in that it is neither initialized nor modified by hot reset or Function
Level Reset.
RESERVED
Reserved Field: Reserved fields must be written with zeros, unless otherwise indicated, to ensure future compatibility. The value of reserved bits is not guaranteed on a
read.
Reference Documents
IEEE 802.3TM-2015 IEEE Standard for Ethernet, http://standards.ieee.org/about/get/802/802.3.html
IEEE 802.1DTM-2004 IEEE Standard for Local and Metropolitan Area Networks - Media Access Control (MAC)
Bridges, http://standards.ieee.org/about/get/802/802.1.html
IEEE 802.1QTM-2014 IEEE Standard for Local and Metropolitan Area Networks - Bridges and Bridged Networks,
http://standards.ieee.org/about/get/802/802.1.html
IEEE 1149.1-2013 IEEE Standard for Test Access Port and Boundary-Scan Architecture,
https://standards.ieee.org/findstds/standard/1149.1-2013.html
IEEE 1588-2008 IEEE Standard for Precision Clock Synchronization Protocol for Networked Measurement and
Control Systems, https://standards.ieee.org/findstds/standard/1588-2008.html
Reduced Gigabit Media Independent Interface (RGMII) Specification Version 2.0,
https://web.archive.org/web/20160303171328/http://www.hp.com/rnd/pdfs/RGMIIv2_0_final_hp.pdf
PCI Express® Base Specification Revision 3.1a, https://pcisig.com/specifications
PCI Bus Power Management Interface Specification Revision 1.2, https://pcisig.com/specifications
2018-2019 Microchip Technology Inc.
DS00002631D-page 7
LAN7430/LAN7431
2.0
INTRODUCTION
2.1
General Description
The LAN7430/LAN7431 is a highly integrated PCIe to Gigabit Ethernet Controller, with IEEE Std 1588TM-2008 and
advanced power management features, that provides a high performance and cost effective PCIe/Ethernet bridging
solution for automotive and industrial applications.
The PCIe 3.1 PHY supports 1 Lane at 2.5GT/s for chip-to-chip and card-to-card connectivity across a combination of
printed circuit boards, connectors, backplane wirings, and cables.
The LAN7430 has an integrated 10/100/1000 Ethernet PHY port with IEEE 802.3az Energy Efficient Ethernet (EEE)
and 10BASE-Te support, while the LAN7431 supports either a RGMII (v1.3 and v2.0) or a MII MAC port for direct connectivity to transceivers, such as 100BASE-T1 or HDBaseT.
The LAN7430/LAN7431 further integrates PCIe Endpoint Controller, DMA Controller, Receive Filtering Engine, FIFO
Controller, Ethernet MAC, EEPROM Controller, OTP Memory, TAP Controller, PME, and Clock/Reset/Power Management functions.
The IEEE1588-2008 PTP functions provide hardware support for the IEEE Std 1588-2008 (v2) Precision Time Protocol
(PTP), allowing clock synchronization with remote Ethernet devices, packet time stamping, and time driven event generation. The device may function as a master or a slave clock per the IEEE Std 1588-2008 specification. End-to-end
and peer-to-peer link delay mechanisms are supported as are one-step and two-step operations.
Power Management functions include:
• Enabling the host to place the device in a reduced power state, by selectively disabling internal clocks, placing it
into EEE Low Power Idle mode, and powering down the Ethernet PHY (LAN7430 only).
• Providing for detection of various wakeup events.
• Providing a host-readable READY flag which is set when the device is fully operational.
• Controlling the loading of OTP or EEPROM values after a system reset.
• Supporting D0 and D3hot and D3cold states
• Supporting L0s, L1 states and L1.1 and L1.2 Sub-states
Single 3.3V supply operation is achieved by enabling the on-chip Switching and LDO Regulators to supply the core and
I/O voltages.
An internal EEPROM controller exists to load PCIe and MAC Address configuration parameters. For EEPROM-less
applications, the LAN7430/LAN7431 provides 1K Bytes of OTP memory that can be used to preload this same configuration data before enumeration.
The integrated IEEE 1149.1 compliant TAP controller provides boundary scan via JTAG.
Device specific features that do not pertain to the entire LAN7430/LAN7431 family are called out independently throughout this document. Table 2-1 provides a summary of the feature differences between family members:
LAN7431
72-SQFN
X
X
DS00002631D-page 8
X
X
X
Automotive Temp.
(-40o to 105oC)
X
Industrial Temp.
(-40o to 85oC)
X
Commercial Temp.
(0o to 70oC)
X
IEEE 1588-2008
Integrated Gigabit
Ethernet MAC
X
RGMII Support
Integrated Gigabit
Ethernet PHY
48-SQFN
MII Support
Integrated PCIe
Endpoint Controller
LAN7430
Part
Number
Integrated PCIe PHY
LAN7430/LAN7431 FAMILY FEATURE MATRIX
Package
TABLE 2-1:
X
X
X
X
X
X
X
X
2018-2019 Microchip Technology Inc.
LAN7430/LAN7431
An internal block diagram of the LAN7430/LAN7431 is shown in Figure 2-1.
FIGURE 2-1:
LAN7430/LAN7431 BLOCK DIAGRAM
MII / RGMII + 0',2
(LAN7431)
25 MHz
LAN7430//$11
PCIe v3.1
2.5 GT / s PHY
++L1SS
1v2 Switching
Regulator
Integrated
Clock Tree
PCIe
Endpoint
Controller
Ethernet MAC with IEEE15882008
DMA & FIFO
Controller
Tx Ch0
RxCh 0...3
Rx Filtering Engine
Checksum Offload
VLAN
Priority | RSS
NS / ARP
2v5 LDO
Regulator
VDDVARIO
Tx Offload
Engine
Ethernet PHY
++802.3az (EEE)
/$1
GPIO
1588
JTAG
TAP
AOAC
OTP
Memory
EEPROM
Loader
Single 3v3 Supply
The following system-level block diagrams detail the LAN7430/LAN7431 in typical applications.
2018-2019 Microchip Technology Inc.
DS00002631D-page 9
LAN7430/LAN7431
Figure 2-2 details the LAN7430’s integrated Ethernet PHY port connected across a backplane to an application processor.
FIGURE 2-2:
LAN7430 CONNECTED ACROSS BACKPLANE TO APPLICATION PROCESSOR
Plug-in Board
Application Processor
GbE
PHY
Backplane Connector
GbE
PHY
LAN7430
PCIe PHY
PCIe
Host
Processor
Main System Board
DS00002631D-page 10
2018-2019 Microchip Technology Inc.
LAN7430/LAN7431
Figure 2-3 details the LAN7431’s RGMII MAC port connected to the RGMII MAC of an application processor.
FIGURE 2-3:
LAN7431 CONNECTED VIA RGMII TO APPLICATION PROCESSOR
Application Processor
RGMII MAC
RGMII MAC
LAN7431
PCIe PHY
PCIe
Host
Processor
System Board
2018-2019 Microchip Technology Inc.
DS00002631D-page 11
LAN7430/LAN7431
3.0
PIN DESCRIPTIONS AND CONFIGURATION
The pin assignments for the LAN7430 are detailed in Section 3.1, "LAN7430 Pin Assignments". The pin assignments
for the LAN7431 are detailed in Section 3.2, "LAN7431 Pin Assignments". Pin descriptions are provided in Section 3.3,
"Pin Descriptions".
3.1
LAN7430 Pin Assignments
The device pin diagram for the LAN7430 can be seen in Figure 3-1. Table 3-1 provides a LAN7430 pin assignments
table. Pin descriptions are provided in Section 3.3, "Pin Descriptions".
ISET
XI
XO
AVDD12
PERST#
WAKE#
CLKREQ#
VDD_OTP
VDD12CORE
VDDVARIO
EECS/GPIO0/LED0/TDI
EEDIO/GPIO1/LED1/TDO
48
47
46
45
44
43
42
41
40
39
38
37
LAN7430 PIN ASSIGNMENTS
AVDDH_1
1
36
EECLK/GPIO2/LED2/TMS/ADV_PM_DISABLE
TXRXP_A
2
35
VAUX_DET/GPIO3/LED3/TCK
TXRXM_A
3
34
VDD12_SW_FB
AVDDL_1
4
33
VDD_SW_IN
TXRXP_B
5
32
VDD12_SW_OUT
TXRXM_B
6
LAN7430
31
VDD12CORE
TXRXP_C
7
4 8- S Q FN
30
TEST
TXRXM_C
8
29
RESET_N
AVDDL_2
9
28
VDD_REG_IN
TXRXP_D
10
27
VDD25_REG_OUT
26
PCIE_CLK_M
25
PCIE_CLK_P
VSS
15
16
17
18
19
20
21
22
23
24
GD_1
PCIE_RX_P
PCIE_RX_M
GD_2
PCIE_TX_P
VPTX
PCIE_TX_M
GD_3
VPH
RESREF
12
14
AVDDH_2
(Connect exposed pad to ground with a via field )
VP
11
13
TXRXM_D
VDD12CORE
FIGURE 3-1:
Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field .
Note:
Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
DS00002631D-page 12
2018-2019 Microchip Technology Inc.
LAN7430/LAN7431
TABLE 3-1:
LAN7430 PIN ASSIGNMENTS
Pin
Pin Name
Pin
Pin Name
1
AVDDH_1
25
PCIE_CLK_P
2
TXRXP_A
26
PCIE_CLK_M
3
TXRXM_A
27
VDD25_REG_OUT
4
AVDDL_1
28
VDD_REG_IN
5
TXRXP_B
29
RESET_N
6
TXRXM_B
30
TEST
7
TXRXP_C
31
VDD12CORE
8
TXRXM_C
32
VDD12_SW_OUT
9
AVDDL_2
33
VDD_SW_IN
10
TXRXP_D
34
VDD12_SW_FB
11
TXRXM_D
35
VAUX_DET/GPIO3/LED3/TCK
12
AVDDH_2
36
EECLK/GPIO2/LED2/TMS/
ADV_PM_DISABLE
13
VDD12CORE
37
EEDIO/GPIO1/LED1/TDO
14
VP
38
EECS/GPIO0/LED0/TDI
15
GD_1
39
VDDVARIO
16
PCIE_RX_P
40
VDD12CORE
17
PCIE_RX_M
41
VDD_OTP
18
GD_2
42
CLKREQ#
19
PCIE_TX_P
43
WAKE#
20
VPTX
44
PERST#
21
PCIE_TX_M
45
AVDD12
22
GD_3
46
XO
23
VPH
47
XI
24
RESREF
48
ISET
Exposed Pad (VSS) must be connected to ground.
2018-2019 Microchip Technology Inc.
DS00002631D-page 13
LAN7430/LAN7431
3.2
LAN7431 Pin Assignments
The device pin diagram for the LAN7431 can be seen in Figure 3-2. Table 3-2 provides a LAN7431 pin assignments
table. Pin descriptions are provided in Section 3.3, "Pin Descriptions".
ISET
XI
XO
AVDD12
PERST#
WAKE#
CLKREQ#
VDD_OTP
MDC
MDIO
VDD12CORE
VDDVARIO
EECS/GPIO0
EEDIO/GPIO1
EECLK/GPIO2/ADV_PM_DISABLE
VAUX_DET/GPIO3
GPIO4
GPIO5
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
LAN7431 PIN ASSIGNMENTS
72
FIGURE 3-2:
AVDDH_1
1
54
GPIO6/TDO
AVDDL_1
2
53
VDD12_SW_FB
VDDVARIO_B
3
52
VDD_SW_IN
TXD3
4
51
VDD12_SW_OUT
TXD2
5
50
GPIO7/TMS
TXD1
6
49
GPIO8/TDI
VDDVARIO_B
7
48
VDDVARIO
TXD0
8
47
GPIO9/TCK
TX_ER/MII_EN
9
46
VDD12CORE
45
TEST
LAN7431
72- SQFN
TX_CTL/TX_EN
10
TXC/TX_CLK
11
44
RESET_N
VDDVARIO_B
12
43
VDDVARIO
RXC/RX_CLK
13
42
PHY_RESET_N
RX_CTL/RX_DV
14
41
PHY_INT_N
VSS
(Connect exposed pad to ground with a via field )
Note:
26
27
28
29
30
31
32
33
34
35
36
PCIE_RX_P
PCIE_RX_M
GD_2
PCIE_TX_P
VPTX
PCIE_TX_M
GD_3
VPH
RESREF
PCIE_CLK_P
PCIE_CLK_M
GD_1
37
25
18
VP
RXD3
24
VDD25_REG_OUT
VDD12CORE
38
23
17
CRS
RXD2
22
VDD_REG_IN
COL/GPIO10
39
21
16
REFCLK_25/GPIO11
RXD1
20
DUPLEX
CLK125/RX_ER
40
19
15
VDDVARIO_B
RXD0
NOTE: Exposed pad (VSS) on bottom of package must be connected to ground
Configuration straps are identified by an underlined symbol name. Signals that function as configuration
straps must be augmented with an external resistor when connected to a load.
DS00002631D-page 14
2018-2019 Microchip Technology Inc.
LAN7430/LAN7431
TABLE 3-2:
LAN7431 PIN ASSIGNMENTS
Pin
Pin Name
Pin
Pin Name
1
AVDDH_1
37
PCIE_CLK_M
2
AVDDL_1
38
VDD25_REG_OUT
3
VDDVARIO_B
39
VDD_REG_IN
4
TXD3
40
DUPLEX
5
TXD2
41
PHY_INT_N
6
TXD1
42
PHY_RESET_N
7
VDDVARIO_B
43
VDDVARIO
8
TXD0
44
RESET_N
9
TX_ER/MII_EN
45
TEST
10
TX_CTL/TX_EN
46
VDD12CORE
11
TXC/TX_CLK
47
GPIO9/TCK
12
VDDVADIO_B
48
VDDVARIO
13
RXC/RX_CLK
49
GPIO8/TDI
14
RX_CTL/RX_DV
50
GPIO7/TMS
15
RXD0
51
VDD12_SW_OUT
16
RXD1
52
VDD_SW_IN
17
RXD2
53
VDD12_SW_FB
18
RXD3
54
GPIO6/TDO
19
VDDVARIO_B
55
GPIO5
20
CLK125/RX_ER
56
GPIO4
21
REFCLK_25/GPIO11
57
VAUX_DET/GPIO3
22
COL/GPIO10
58
EECLK/GPIO2/ADV_PM_DISABLE
23
CRS
59
EEDIO/GPIO1
24
VDD12CORE
60
EECS/GPIO0
25
VP
61
VDDVARIO
26
GD_1
62
VDD12CORE
27
PCIE_RX_P
63
MDIO
28
PCIE_RX_M
64
MDC
29
GD_2
65
VDD_OTP
30
PCIE_TX_P
66
CLKREQ#
31
VPTX
67
WAKE#
32
PCIE_TX_M
68
PERST#
33
GD_3
69
AVDD12
34
VPH
70
XO
35
RESREF
71
XI
36
PCIE_CLK_P
72
ISET
Exposed Pad (VSS) must be connected to ground.
2018-2019 Microchip Technology Inc.
DS00002631D-page 15
LAN7430/LAN7431
3.3
Pin Descriptions
This section provides descriptions of each individual pin function. Buffer type definitions are detailed in Table 1-2.
TABLE 3-3:
PIN DESCRIPTIONS
Name
Symbol
Ethernet TX/RX
Positive
Channel A
TXRXP_A
Buffer
Type
Description
Gigabit Ethernet PHY Interface (LAN7430 only)
AIO
Media Dependent Interface[0], positive signal of differential pair
1000BT mode: TXRXP_A corresponds to BI_DA+ for
MDI configuration and BI_DB+ for MDI-X configuration,
respectively.
10BT/100BT mode: TXRXP_A is the positive transmit
signal (TX+) for MDI configuration and the positive
receive signal (RX+) for MDI-X configuration, respectively.
Ethernet TX/RX
Negative
Channel A
TXRXM_A
AIO
Media Dependent Interface[0], negative signal of differential pair
1000BT mode: TXRXM_A corresponds to BI_DA- for
MDI configuration and BI_DB- for MDI-X configuration,
respectively.
10BT/100BT-TX mode: TXRXM_A is the negative transmit signal (TX-) for MDI configuration and the negative
receive signal (RX-) for MDI-X configuration, respectively.
Ethernet TX/RX
Positive
Channel B
TXRXP_B
AIO
Media Dependent Interface[1], positive signal of differential pair
1000BT mode: TXRXP_B corresponds to BI_DB+ for
MDI configuration and BI_DA+ for MDI-X configuration,
respectively.
10BT/100BT mode: TXRXP_B is the positive receive signal (RX+) for MDI configuration and the positive transmit
signal (TX+) for MDI-X configuration, respectively.
Ethernet TX/RX
Negative
Channel B
TXRXM_B
AIO
Media Dependent Interface[1], negative signal of differential pair
1000BT mode: TXRXM_B corresponds to BI_DB- for
MDI configuration and BI_DA- for MDI-X configuration,
respectively.
10BT/100BT mode: TXRXP_B is the negative receive
signal (RX-) for MDI configuration and the negative transmit signal (TX-) for MDI-X configuration, respectively.
Ethernet TX/RX
Positive
Channel C
TXRXP_C
AIO
Media Dependent Interface[2], positive signal of differential pair
1000BT mode: TXRXP_C corresponds to BI_DC+ for
MDI configuration and BI_DD+ for MDI-X configuration,
respectively.
10BT/100BT mode: TXRXP_C is not used.
DS00002631D-page 16
2018-2019 Microchip Technology Inc.
LAN7430/LAN7431
TABLE 3-3:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Ethernet TX/RX
Negative
Channel C
TXRXM_C
AIO
Description
Media Dependent Interface[2], negative signal of differential pair
1000BT mode: TXRXM_C corresponds to BI_DC- for
MDI configuration and BI_DD- for MDI-X configuration,
respectively.
10BT/100BT mode: TXRXM_C is not used.
Ethernet TX/RX
Positive
Channel D
TXRXP_D
AIO
Media Dependent Interface[3], positive signal of differential pair
1000BT mode: TXRXP_D corresponds to BI_DD+ for
MDI configuration and BI_DC+ for MDI-X configuration,
respectively.
10BT/100BT mode: TXRXP_D is not used.
Ethernet TX/RX
Negative
Channel D
TXRXM_D
AIO
Media Dependent Interface[3], negative signal of differential pair
1000BT mode: TXRXM_D corresponds to BI_DD- for
MDI configuration and BI_DC- for MDI-X configuration,
respectively.
10BT/100BT mode: TXRXM_D is not used.
External Gigabit Ethernet PHY RGMII (LAN7431 only)
Transmit Data
TXD3
TXD2
TXD1
TXD0
RGMII_O
The MAC transmits data to the external Ethernet PHY
using these signals.
Transmit Control
TX_CTL
RGMII_O
Indicates both the transmit data enable (TXEN) and
transmit error (TXER) functions per the RGMII specification.
RGMII Transmit
Clock
TXC
RGMII_O
Used to latch data from the MAC into the external Ethernet PHY in RGMII mode.
1000BASE-T: 125MHz
100BASE-TX: 25MHz
10BASE-T: 2.5MHz
Receive Data
RXD3
RXD2
RXD1
RXD0
RGMII_I
The external Ethernet PHY transfers data to the MAC
using these signals.
Receive Control
RX_CTL
RGMII_I
Indicates both the receive data valid (RXDV) and receive
error (RXER) functions per the RGMII specification.
RGMII Receive
Clock
RXC
RGMII_I
Used to transfer data from the external Ethernet PHY to
the MAC in RGMII mode.
1000BASE-T: 125MHz
100BASE-TX: 25MHz
10BASE-T: 2.5MHz
25 MHz Reference Clock
REFCLK_25
2018-2019 Microchip Technology Inc.
VO12
25 MHz reference clock to be provided to and used as a
reference by the external Gigabit Ethernet PHY.
DS00002631D-page 17
LAN7430/LAN7431
TABLE 3-3:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
CLK125 MHz
CLK125
VIS
Used as an input from external Ethernet PHY. This signal
may be used by the controller to generate the RGMII TX
clock.
PHY Interrupt
PHY_INT_N
VIS
Interrupt from external Ethernet PHY.
PHY Reset
PHY_RESET_N
VO12
Duplex Mode
DUPLEX
VIS
Description
Reset to external Ethernet PHY.
Duplex Mode. This signal connects to the Duplex Mode
output from external Ethernet PHY.
When set the external Ethernet PHY is in Full Duplex
mode.
Note:
Management
Interface Data
Management
Interface Clock
MDIO
MDC
VIS/
VO8
(PU)
VO8
If the Ethernet PHY does not have a duplex
output signal, then it is recommended that this
signal should be tied to VDDVARIO to force full
duplex operation
This is the management data to/from an external Ethernet PHY.
Note:
An external pull-up is required when the MII
management interface is used, to ensure that
the IDLE state of the MDIO signal is a logic
one.
Note:
An external pull-up is recommended when the
MII management interface is not used, to avoid
a floating signal.
This is the management clock output to an external
Ethernet PHY
External Fast Ethernet PHY MII (LAN7431 only)
Transmit Data
TXD3
TXD2
TXD1
TXD0
VO12
The MAC transmits data to the external Ethernet PHY
using these signals.
Transmit Enable
TX_EN
VO12
Indicates the presence of valid data on TXD[3:0]
Transmit Error
TX_ER
VO12
Indicates a transmit error condition.
Transmit Clock
TX_CLK
VIS
Used to transfer data from the MAC to the external Ethernet PHY in MII mode.
100BASE-TX: 25MHz
10BASE-T: 2.5MHz
Collision Detect
COL
VIS
Carrier Sense
CRS
VIS
Asserted by external Ethernet PHY to indicate detection
of a collision condition.
Note:
Used in half-duplex mode only.
Indicates detection of carrier by external Ethernet PHY.
Note:
Used in half-duplex mode only.
Receive Data
RXD3
RXD2
RXD1
RXD0
VIS
The external Ethernet PHY transfers data to the MAC
using these signals.
Receive Data
Valid
RX_DV
VIS
Indicates that recovered and decoded data is being presented on the receive data pins.
DS00002631D-page 18
2018-2019 Microchip Technology Inc.
LAN7430/LAN7431
TABLE 3-3:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Receive Error
RX_ER
VIS
Asserted to indicate an error has been detected in the
frame presently being transferred from the external
Ethernet PHY.
Receive Clock
RX_CLK
VIS
Used to transfer data from the external Ethernet PHY to
the MAC in MII mode.
Description
100BASE-TX: 25MHz
10BASE-T: 2.5MHz
25 MHz Reference Clock
REFCLK_25
VO12
PHY Interrupt
PHY_INT_N
VIS
PHY Reset
PHY_RESET_N
VO12
Duplex Mode
DUPLEX
VIS
25 MHz reference clock to be provided to and used as a
reference by the external Fast Ethernet PHY.
Interrupt from external Ethernet PHY.
Reset to external Ethernet PHY.
Duplex Mode. This signal connects to the Duplex Mode
output from external Ethernet PHY.
When set the external Ethernet PHY is in Full Duplex
mode.
Note:
Management
Interface Data
MDIO
VIS/
VO8
(PU)
If the external Ethernet PHY does not have a
duplex output signal, then it is recommended
that this signal should be tied to VDDVARIO to
force full duplex operation
This is the management data to/from an external Ethernet PHY.
Note:
An external pull-up is required when the MII
management interface is used, to ensure that
the IDLE state of the MDIO signal is a logic
one.
Note:
An external pull-up is recommended when the
MII management interface is not used, to avoid
a floating signal.
APPLICATION NOTE: A pull-up (internal or external)
will result in a return value of
FFFFh when a non-existent or
non-addressed PHY is read. If a
value of 0000h is desired
instead, a pull-down may be
used.
Management
Interface Clock
MDC
VO8
TX Positive
PCIE_TX_P
AO
This is the management clock output to an external
Ethernet PHY
PCIe
PCIe Serial Data Output positive.
Serial differential output link in the PCIe interface running
at 2.5 GT/s.
A series capacitor in the range of 100nF to 200nF is
required.
2018-2019 Microchip Technology Inc.
DS00002631D-page 19
LAN7430/LAN7431
TABLE 3-3:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
TX Negative
PCIE_TX_M
AO
Description
PCIe Serial Data Output negative.
Serial differential output link in the PCIe interface running
at 2.5 GT/s.
A series capacitor in the range of 100nF to 200nF is
required.
RX Positive
PCIE_RX_P
AI
PCIe Serial Data Input positive.
Serial differential input link in the PCIe interface running
at 2.5 GT/s.
RX Negative
PCIE_RX_M
AI
PCIe Serial Data Input negative.
Serial differential input link in the PCIe interface running
at 2.5 GT/s.
External Reference Clock
Positive
PCIE_CLK_P
AI
External Reference Clock
Negative
PCIE_CLK_M
AI
External Reference Resistor
RESREF
AI
Wake up
WAKE#
IS / OD4
PCIe Differential Reference Clock In positive
This pin receives a 100 MHz differential clock input.
PCIe Differential Reference Clock In negative
This pin receives a 100 MHz differential clock input.
This pin should be connect to ground through a 200 ohm
1% 100 ppm / C resistor.
Wake
This signal is driven low when the device detects a
wakeup.
In OBFF mode, OBFF events are signaled using the
WAKE# pin as an input.
Note:
PCIe Reset
PERST#
IS
When the device is powered down, this pin is
isolated from the PCIe bus and does not
present any significant loading or provide any
drive.
Power and Clock Good Indication
The PERST# signal indicates that both PCIe power and
clock are available.
Note:
Clock Request
CLKREQ#
IS / OD4
When the device is powered down, this pin is
isolated from the PCIe bus and does not
present any significant loading or provide any
drive.
Clock Request
The CLKREQ# signal is used to power manage the Link
clock. It is also used for L1 power management Sub state
control.
Note:
DS00002631D-page 20
When the device is powered down, this pin is
isolated from the PCIe bus and does not
present any significant loading or provide any
drive.
2018-2019 Microchip Technology Inc.
LAN7430/LAN7431
TABLE 3-3:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Auxiliary Voltage
Detect
VAUX_DET
Buffer
Type
VIS
(PD)
Description
Auxiliary Voltage Detection
The VAUX_DET is used to indicate when PME from
D3cold is supported.
When tied to VSS, PME from D3cold is not supported.
The weak pull-down will create a logic low when plugged
into a system board that does not support the delivery of
the auxiliary voltage (the auxiliary voltage connection is
floating).
When the device is powered exclusively from auxiliary
voltage, this pin is tied to the auxiliary voltage (3.3V) to
indicate PME from D3cold is supported.
When the device is powered from a multiplexed main
voltage / auxiliary voltage, this pin is tied to the auxiliary
voltage (3.3V) to indicate PME from D3cold is supported
and to monitor the presence of the auxiliary voltage.
If alternate usage of this pin (GPIO3, LED3 or
TCK) is enabled, the pull-down is disabled and
the input value of the pin is overridden to a low
value.
Since this pin is shared with GPIO3, LED3 and TCK, a
series resistor is recommended to prevent an accidental
conflict with the auxiliary voltage. This resistor must be
low enough in value to override the on chip pull-down.
Note:
Crystal / Oscillator / External Reference Clock
Crystal / Oscillator / External Reference Clock
Input
XI
ICLK
When using a 25MHz crystal, this input is connected to
one lead of the crystal.
When using a 3.3V oscillator or external reference clock,
this is the input from the clock source.
The crystal, oscillator, or external reference clock should
have a tolerance of ±50ppm.
Crystal Output
XO
OCLK
When using a 25MHz crystal, this output is connected to
one lead of the crystal.
When using an oscillator or external clock source, this pin
is not connected.
EEPROM
EEPROM Chip
Select
EECS
VO12
(PD)
This pin drives the chip select input of the external
EEPROM.
Note:
2018-2019 Microchip Technology Inc.
The internal pull-down holds a low on the
output pin during reset.
DS00002631D-page 21
LAN7430/LAN7431
TABLE 3-3:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
EEPROM Data In
/ Out
EEDIO
EEPROM Clock
EECLK
Buffer
Type
Description
VIS / VO12 This bidirectional pin is used for the EEPROM data. This
(PD)
pin directly drives the data input of the external EEPROM.
The data output of the external EEPROM drives this pin
through an external resistor.
VO12
(PD)
Note:
The internal pull-down holds a low on the pin
during reset and provides a low on the input if
an EEPROM is not connected.
Note:
An external resistor, on the EEPROM’s data
output, must be used to prevent contention
during data read operations.
This pin drives the clock input of the external EEPROM.
Note:
The internal pull-down holds a low on the
output pin during reset.
Miscellaneous
General
Purpose I/O x
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
VIS/
VO8/
VOD8
(PU)
Each of these general purpose I/O pins is fully programmable as either a push-pull output, an open-drain output,
or a Schmitt-triggered input with pull-up.
Test Pin
TEST
VIS
(PD)
This pin is used to enable test modes and must be connected to ground for proper functional operation.
System Reset
RESET_N
VIS
System reset. This pin is active low.
Note:
The pull-up is only enabled if the pin is set as
a GPIO.
Note:
GPIO0 through GPIO3 are available for the
LAN7430 and LAN7431.
Note:
GPIO4 through GPIO11 are available only for
the LAN7431.
Note:
Indicator LEDs
External PHY Bias
Resistor
LED0
LED1
LED2
LED3
VOD12
VOS12
ISET
AI
If this signal is unused it must be pulled up to
VDDVARIO.
(LAN7430 only)
LED signal sourced from Gigabit Ethernet PHY.
Note:
When enabled as LED outputs, the pins are
either open-Drain or open-Source drivers.
This pin should be connect to ground through a 6.04K 1%
resistor.
JTAG
JTAG Test Mux
Select
TMS
VIS
JTAG test mode select.
JTAG Test Clock
TCK
VIS
JTAG test clock.
Note:
JTAG Test Data
Input
TDI
VIS
JTAG Test Data
Output
TDO
VO12
DS00002631D-page 22
The maximum operating frequency of this clock
is half of the system clock.
JTAG data input
JTAG data output.
2018-2019 Microchip Technology Inc.
LAN7430/LAN7431
TABLE 3-3:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
MII Enable
Configuration
Strap
MII_EN
Buffer
Type
Description
Configuration Straps
Advance Power
Management Disable
Configuration
Strap
ADV_PM_DISABLE
VIS
(PD)
VIS
(PD)
(LAN7431 only)
When pulled high, the port operates in MII mode. When
pulled low or floated, the port operates in RGMII mode.
See Section 3.4, "Configuration Straps" for additional
information.
Note:
The internal pull-down is disabled once the
strap is latched.
Note:
If an external pull-up is used, it should be
connected to VDDVARIO_B.
When pulled high, the following bits default low. When
pulled low or floated, the register bits default high.
• Clock Power Management in Link Capabilities
• L1 PM Substates Supported in L1 PM Substates
Capabilities
• ASPM L1.1 Supported in L1 PM Substates Capabilities
• ASPM L1.2 Supported in L1 PM Substates Capabilities
• PCI-PM L1.1 Supported in L1 PM Substates Capabilities
• PCI-PM L1.2 Supported in L1 PM Substates Capabilities
Note:
Regardless of the strap default, the bits may be
loaded from OTP or EEPROM. The default is
used in the absence of a programmed OTP or
EEPROM.
Note:
The internal pull-down is disabled once the
strap is latched.
Note:
If an external pull-up is used, it should be
connected to VDDVARIO.
Power / Ground
Ethernet PHY
+1.2V Analog
Power Supply
AVDD12
P
1.2V power for PLL/DLL
Ethernet PHY
+2.5V / 3.3V Analog Power Supply
AVDDH_1
P
2.5V or 3.3V power for analog IO
LAN7430 only
This pin provides power for Gigabit PHY transmitter,
bandgap reference, and crystal oscillator amplifier.
LAN7431 only
This pin provides power for bandgap reference and crystal oscillator amplifier.
Ethernet PHY
+2.5V / 3.3V Analog Power Supply
AVDDH_2
2018-2019 Microchip Technology Inc.
P
2.5V or 3.3V power for analog IO
(LAN7430 only)
This pin provides power for Gigabit PHY transmitter.
DS00002631D-page 23
LAN7430/LAN7431
TABLE 3-3:
PIN DESCRIPTIONS (CONTINUED)
Name
Symbol
Buffer
Type
Ethernet PHY
+1.2V Analog
Power Supply
AVDDL_1
P
1.2V power for analog core
Ethernet PHY
+1.2V Analog
Power Supply
AVDDL_2
P
1.2V power for analog core
PCIe PHY High
Voltage Supply
VPH
P
2.5V PCIe PHY power
PCIe PHY Transmit Supply
VPTX
P
1.2V PCIe PHY TX power
PCIe PHY Analog
and Digital Supply
VP
P
1.2V PCIe PHY power
Variable I/O
Power Supply
Input Group A
VDDVARIO
P
1.8V - 3.3V variable supply for IOs
Variable I/O
Power Supply
Input Group B
VDDVARIO_B
P
1.8V - 3.3V variable supply for RGMII and MII related IOs
OTP Power
VDD_OTP
Description
(LAN7430 only)
This is an additional power pin for the 1.2V analog core.
(LAN7431 only)
This is the power pin for the RGMII and MII related IOs
(TXD3, TXD2, TXD1, TXD0, TX_ER/MII_EN, TX_CTL/
TX_EN, TXC/TX_CLK, RXC/RX_CLK, RX_CTL/RX_DV,
RXD0, RXD1, RXD2, RXD3, CLK125/RX_ER, REFCLK_25/GPIO11, COL/GPIO10, CRS).
P
3.3V to OTP charge pump
3.3V supply voltage for PCIe I/Os
(CLKREQ#, WAKE#, PERST#)
Switcher Input
Voltage
VDD_SW_IN
P
1.8V - 3.3V input voltage for switching regulator
Switcher Feedback
VDD12_SW_FB
P
Feedback pin for the integrated switching regulator
Switcher +1.2V
Unfiltered Output
Voltage
VDD12_SW_OUT
P
1.2V output voltage from switching regulator
LDO Input Voltage
VDD_REG_IN
P
3.3V input supply to the integrated LDO
Note:
Note:
LDO Output
VDD25_REG_OUT
P
Tie this pin to VDD_SW_IN to disable the
switching regulator.
If this supply is set to 2.5V than it shall be
externally connected to VDD25_REG_OUT.
See Section 4.0, "Power Connectivity" for
details.
2.5V output supply from the integrated LDO
This is used to supply power to the PCIE PHY and
optionally to the Gigabit Ethernet PHY AFE.
Digital Core +1.2V
Power Supply
Input
DS00002631D-page 24
VDD12CORE
P
1.2V digital core power.
2018-2019 Microchip Technology Inc.
LAN7430/LAN7431
TABLE 3-3:
PIN DESCRIPTIONS (CONTINUED)
Buffer
Type
Name
Symbol
Description
PCIe Ground
GD_1
GD_2
GD_3
P
PCIe ground.
Ground
VSS
P
Common ground.
This exposed pad must be connected to the ground plane
with a via array.
3.4
Configuration Straps
Configuration straps are latched on Power-On Reset (POR) and External Chip Reset (RESET_N) and are identified by
an underlined symbol name. Configuration straps are multi-function pins that are driven as outputs during normal operation. During a Power-On Reset (POR) or an External Chip Reset (RESET_N), these outputs are not driven. The high
or low state of the signal is latched following deassertion of the reset and is used to determine the default configuration
of a particular feature. The following configuration strap signals are available:
• ADV_PM_DISABLE
• MII_EN (LAN7431 only)
Configuration straps include internal resistors in order to prevent the signal from floating when unconnected. If a particular configuration strap is connected to a load, an external pull-up or pull-down should be used to augment the internal
resistor to ensure that it reaches the required voltage level prior to latching. The internal resistor can also be overridden
by the addition of an external resistor. When externally pulling configuration straps high, the strap should be tied to
VDDVARIO or VDDVARIO_B as indicated in the pin descriptions.
The system designer must ensure that configuration straps meet the timing requirements specified in Section 7.6.3,
"Power-On Configuration Strap Timing" and Section 7.6.4, "Reset Pin Configuration Strap Timing". If configuration
straps are not at the correct voltage level prior to being latched, the device may capture incorrect strap values.
Note:
Configuration straps must never be driven as inputs. If required, configuration straps can be augmented,
or overridden with external resistors.
2018-2019 Microchip Technology Inc.
DS00002631D-page 25
LAN7430/LAN7431
4.0
POWER CONNECTIVITY
This section details the power connectivity of the LAN7430 and LAN7431 in various configurations. Power sequence
timing is detailed in Section 7.6.2, "Power Sequence Timing".
4.1
LAN7430 Power Connectivity
The following diagrams illustrate the power connectivity for LAN7430 with on-chip regulators enabled and disabled.
FIGURE 4-1:
LAN7430 POWER CONNECTIVITY ON-CHIP REGULATORS ENABLED
+1.8 V to
+3.3 V
VDDVARIO
(1 pin)
VDD12CORE
(3 pins)
IO Pads
Core Logic &
Ethernet PHY
digital
+3.3 V
VDD_OTP
(1 pin)
3.3 / 1.2 OTP
Ethernet PHY
Analog
AVDDL
(2 pins)
AVDDH
(2 pins)
+3.3 V
optional 3.3V
PHY
operation
Ethernet PHY
Bandgap and Osc
Ethernet PHY PLL
AVDD12
(1 pin)
VP
(1 pin)
VPTX
(1 pin)
PCIe PHY
VPH
(1 pin)
+1.8 V to
+3.3 V
VDD_SW_IN
(1 pin)
VDD_REG_IN
(1 pin)
Internal 1.2 V
Switching Regulator
OUT
IN
REF
FEEDBACK
Internal 2.5 V LDO
Regulator
IN
OUT
ENABLE
3.3 uH
VDD12_SW_OUT
(1 pin)
VDD12_SW_FB
(1 pin)
0.1uF
10 µF
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