LND01
Lateral N-Channel Depletion-Mode MOSFET
Features
General Description
•
•
•
•
•
•
•
The LND01 is a low-threshold, Depletion-mode
(normally-on) transistor that uses an advanced lateral
DMOS structure and a well-proven silicon gate
manufacturing process. This combination produces a
device with the power handling capabilities of bipolar
transistors as well as the high input impedance and
positive
temperature
coefficient
inherent
in
MOS devices. Characteristic of all MOS structures, this
device is free from thermal runaway and thermally
induced secondary breakdown.
Bi-directional
Low On-resistance
Low Input Capacitance
Fast Switching Speeds
High Input Impedance and High Gain
Low Power Drive Requirement
Ease of Paralleling
Applications
•
•
•
•
•
The body of the transistor is connected to the gate pin.
The channel is therefore being pinched off by both the
gate and body. The gate pin has a diode connected to
the drain terminal and another diode connected to the
source terminal.
Normally-on Switches
Solid-state Relays
Converters
Constant Current Sources
Analog Switches
Package Type
5-lead SOT-23
DRAIN
SOURCE
N/C
GATE
N/C
See Table 2-1 for pin information.
2017 Microchip Technology Inc.
DS20005696A-page 1
LND01
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
Drain-to-source Voltage ....................................................................................................................................... BVDSX
Source-to-drain Voltage........................................................................................................................................ BVSDX
Gate-to-source Voltage ............................................................................................................................ –12V to +0.6V
Gate-to-drain Voltage ............................................................................................................................... –12V to +0.6V
Operating Ambient Temperature, TA ................................................................................................... –25°C to +125°C
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. (Note 1)
Parameter
Sym.
Min.
Typ.
Max.
Unit
9
—
—
V
Drain-to-source Breakdown Voltage
BVDSX
9
—
—
V
Source-to-drain Breakdown Voltage
BVSDX
Gate-to-source Off Voltage
VGS(OFF) –0.8
—
–3
V
—
–3
V
Source-to-gate Off Voltage
VSG(OFF) –0.8
–12
—
0.6
V
Gate-to-source Diode
VGS
Gate-to-drain Diode
VGD
–12
—
0.6
V
—
—
1
µA
Drain-to-source Leakage Current
IDS(OFF)
—
—
1
µA
Source-to-drain Leakage Current
ISD(OFF)
Saturated Drain-to-source Current
IDSS
300
—
—
mA
300
—
—
mA
Saturated Source-to-drain Current
ISDD
Static Drain-to-source On-state
—
0.9
1.4
Ω
RDS(ON)
Resistance
Static Source-to-drain On-state
—
0.9
1.4
Ω
RSD(ON)
Resistance
Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated.
(Pulse test: 300 µs pulse, 2% duty cycle)
2: Specification is obtained by characterization and is not 100% tested.
Conditions
VGS = –3V, IDS = 10 µA
VGD = –3V, ISD = 10 µA
VDS = 9V, IDS = 1 µA
VSD = 9V, ISD = 1 µA
IGS = ±1 µA
IGD = ±1 µA
VGS = –3V, VDS = 9V
VGD = –3V, VSD = 9V
VGS = 0V, VDS = 9V
VGD = 0V, VSD = 9V
VGS = 0V, IDS = 100 mA
VGD = 0V, ISD = 100 mA
AC ELECTRICAL CHARACTERISTICS
Electrical Specifications: TA = 25°C unless otherwise specified. (Note 2)
Parameter
Sym.
Min.
Typ.
Max.
Unit
200
—
—
mmho
Forward Transconductance
GFS
Input Capacitance
CISS
—
46
—
pF
—
32
—
pF
Common Source Output Capacitance
COSS
—
23
—
pF
Reverse Transfer Capacitance
CRSS
Turn-on Delay Time
td(ON)
—
3.8
—
ns
—
11
—
ns
Rise Time
tr
—
1
—
ns
Turn-off Delay Time
td(OFF)
—
6.4
—
ns
Fall Time
tf
Note 1: All DC parameters are 100% tested at 25°C unless otherwise stated.
(Pulse test: 300 µs pulse, 2% duty cycle)
2: Specification is obtained by characterization and is not 100% tested.
DS20005696A-page 2
Conditions
VDS = 9V, IDS = 50 mA
VGS = –3V, VDS = 5V,
f = 1 MHz
VDD = 9V, IDS = 100 mA,
RGEN = 25Ω
2017 Microchip Technology Inc.
LND01
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise specified, for all specifications TA =TJ = +25°C.
Parameter
Sym.
Min.
Typ.
Max.
Unit
TA
–25
—
+125
°C
JA
—
253
—
°C/W
Conditions
TEMPERATURE RANGE
Operating Ambient Temperature
PACKAGE THERMAL RESISTANCE
5-lead SOT-23
THERMAL CHARACTERISTICS
Package
5-lead SOT-23
Note 1:
ID ( 1)
(Continuous)
(mA)
ID
(Pulsed)
(mA)
Power Dissipation at TC = 25°C
(W)
330
600
0.36
ID (continuous) is limited by maximum TJ.
2017 Microchip Technology Inc.
DS20005696A-page 3
LND01
2.0
PIN DESCRIPTION
Table 2-1 shows the description of pins in LND01.
Refer to Package Type for the location of pins.
TABLE 2-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
N/C
Not connected
2
Gate
Gate
3
N/C
Not connected
4
Drain
5
Source
DS20005696A-page 4
Drain
Source
2017 Microchip Technology Inc.
LND01
3.0
FUNCTIONAL DESCRIPTION
Figure 3-1 illustrates the switching waveforms and test
circuit for LND01.
VDD
0V
90%
RL
INPUT
-3.0V
Pulse
Generator
10%
t(ON)
t(OFF)
tr
td(ON)
VDD
td(OFF)
RGEN
tf
GATE
10%
10%
D.U.T.
INPUT
SOURCE
OUTPUT
90%
0V
FIGURE 3-1:
TABLE 3-1:
OUTPUT
DRAIN
90%
Switching Waveforms and Test Circuit.
PRODUCT SUMMARY
BVDSX/BVSDX
(V)
RDS(ON)/RSD(ON)
(Maximum)
(Ω)
IDSS/ISSD
(Maximum)
(mA)
9
1.4
300
2017 Microchip Technology Inc.
DS20005696A-page 5
LND01
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
5-lead SOT-23
XXXXY
WWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20005696A-page 6
Example
NDU7
15241
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Pre-plated
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2017 Microchip Technology Inc.
LND01
5-Lead SOT-23 Package Outline (K1)
2.90x1.60mm body, 1.45mm height (max), 0.95mm pitch
D
θ1
e1
5
E1 E
Note 1
(Index Area
D/2 x E1/2)
1
e
L2
Gauge
Plane
θ
Seating
Plane
L
b
L1
Top View
View B
View B
A
A
A2
A1
Seating
Plane
A
Side View
View A - A
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Note:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU
a printed indicator.
Symbol
MIN
Dimension
NOM
(mm)
MAX
A
A1
A2
b
0.90*
0.00
0.90
0.30
1.45
0.15
1.15
1.30
0.50
D
E
E1
e
e1
2.75* 2.60* 1.45*
2.90
2.80
1.60
3.05* 3.00* 1.75*
L
L1
L2
0.30
0.95
BSC
1.90
BSC
0.45
0.60
0.60
REF
0.25
BSC
ș
ș
0O
5O
4
O
10O
8
O
15O
JEDEC Registration MO-178, Variation AA, Issue C, Feb. 2000.
7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ
Drawings not to scale.
2017 Microchip Technology Inc.
DS20005696A-page 7
LND01
NOTES:
DS20005696A-page 8
2017 Microchip Technology Inc.
LND01
APPENDIX A:
REVISION HISTORY
Revision A (June 2017)
• Converted Supertex Doc# DSFP-LND01
to Microchip DS20005696A
• Changed the package marking format
• Changed the quantity of the 5-lead SOT-23 K1
package from 2500/Reel to 3000/Reel
• Made minor text changes throughout the document
2017 Microchip Technology Inc.
DS20005696A-page 9
LND01
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
XX
PART NO.
-
Package
Options
Device
X
-
Environmental
X
Media Type
Device:
LND01
=
Lateral N-Channel Depletion-Mode MOSFET
Package:
K1
=
5-lead SOT-23
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Type:
(blank)
=
3000/Reel for a K1 Package
DS20005696A-page 10
Example:
a) LND01K1-G:
Lateral N‐Channel Depletion‐Mode
MOSFET, 5‐lead SOT‐23,
3000/Reel
2017 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
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and may be superseded by updates. It is your responsibility to
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OTHERWISE, RELATED TO THE INFORMATION,
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are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
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CERTIFIED BY DNV
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© 2017, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-1820-7
== ISO/TS 16949 ==
2017 Microchip Technology Inc.
DS20005696A-page 11
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DS20005696A-page 12
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11/07/16