MCP19117-E/MQ

MCP19116/7 Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller with Improved 8k Word Core Features Microcontroller Features • Input Voltage: +4.5V to +42V • Can be configured with multiple topologies including but not limited to: - Flyback - Ćuk - Boost - SEPIC (Single-Ended Primary-Inductor Converter) • Capable of Quasi-Resonant or Fixed-Frequency Operation • Low Quiescent Current: 5 mA Typical • Low Sleep Current: 50 µA Typical • Low-Side Gate Drivers: - +5V gate drive with 0.5A sink/source current - +10V gate drive with 1A sink/source current • Peak Current Mode Control • Differential Remote Output Sense • Multiple Output Systems: - Master or Slave • AEC-Q100 Qualified • Configurable Parameters: - VREF, Precision IOUT/VOUT Set Point (DAC) - ADC Reference Switch (VDD or AVDD) - Input Undervoltage Lockout (UVLO) - Input Overvoltage Lockout (OVLO) - Detection and protection - Primary current leading edge blanking (0 ns, 50 ns, 100 ns and 200 ns) - Gate drive dead time (16 ns to 256 ns) - Fixed switching frequency range: 31.25 kHz to 2.0 MHz - Slope compensation - Quasi-Resonant configuration with built-in comparator and programmable offset voltage adjustment - Primary current offset adjustment - GPIO pin options • Integrated Low-Side Differential Current-Sense Amplifier • Better than 5% Current Regulation • Thermal Shutdown • Precision 8 MHz Internal Oscillator Block: - Factory-calibrated to ±1%, typical • Interrupt-Capable: - Firmware - Interrupt-on-change pins • Only 35 Instructions to Learn • 8192 Words On-Chip Program Memory • High-Endurance Flash: - 100,000 write Flash endurance - Flash retention: > 40 years • Watchdog Timer (WDT) with Independent Oscillator for Reliable Operation • Programmable Code Protection • In-Circuit Serial Programming™ (ICSP™) via Two Pins • Eight I/O Pins and One Input-Only Pin: - Two open-drain pins • Analog-to-Digital Converter (ADC): - 10-bit resolution - Five external channels • Timer0: 8-bit Timer/Counter with 8-bit Prescaler • Enhanced Timer1: - 16-bit timer with prescaler - Two selectable clock sources • Timer2: 8-Bit Timer with Prescaler: - 8-bit period register • I2C Communication: - 7-bit address masking - Two dedicated address registers • Addressable Universal Synchronous Receiver Transmitter (AUSART) Modes - Asynchronous (Full Duplex) - Synchronous - Master (Half Duplex) - Synchronous - Slave (Half Duplex)  2015-2020 Microchip Technology Inc. DS20005479D-page 1 MCP19116/7 22 21 VDD IFB 23 VIN ICOMP 24 VS GPB1/AN4/VREF2/TX/CK Pin Diagram – 24-Pin QFN (MCP19116) 20 19 GPA0/AN0/TEST_OUT 1 18 VDR GPA1/AN1/CLKPIN 2 17 PDRV GPA2/AN2/T0CKI/INT 3 16 SDRV 4 15 PGND GPA7/SCL/ICSPCLK 5 14 AGND GPA6/CCD/ICSPDAT/RX/DT 6 13 IP MCP19116 GPA3/AN3 DS20005479D-page 2 9 10 GPB0/SDA DESATN DESATP/ISOUT 11 12 ISN 8 ISP 7 GPA5/MCLR/TEST_EN EXP-25  2015-2020 Microchip Technology Inc. MCP19116/7 24-PIN QFN (MCP19116) SUMMARY I/O 24-Pin QFN ANSEL A/D Timers MSSP/AUSART Interrupt Pull-Up TABLE 1: Basic GPA0 1 Y AN0 — — IOC Y — Analog/Digital Debug Output (1) GPA1 2 Y AN1 — — IOC Y — Sync Signal In/Out (2) GPA2 3 Y AN2 T0CKI — IOC INT Y — — GPA3 4 Y AN3 — — IOC Y — — GPA5 7 N — — — IOC (3) Y (4) MCLR GPA6 6 N — — RX/DT IOC Y ICSPDAT Dual Capture Input / Single Compare 1 Output GPA7 5 N — — SCL IOC N ICSPCLK — GPB0 8 N — — SDA IOC N — — GPB1 24 Y AN4 — TX/CK IOC Y — VREF2 (5) Additional Test Enable Input DESATN 9 N — — — — — — DESAT Negative Input DESATP/ ISOUT 10 N — — — — — — DESATP Input or ISOUT ISP 11 N — — — — Y — Current Sense Amplifier Positive Input ISN 12 N — — — — — — Current Sense Amplifier Negative Input IP 13 N — — — — — — Primary Input Current Sense AGND 14 N — — — — — AGND Small Signal Ground PGND 15 N — — — — — PGND Large Signal Ground SDRV 16 N — — — — — — Secondary LS Gate Drive Output PDRV 17 N — — — — — — Primary LS Gate Drive Output VDR 18 N — — — — — VDR Gate Drive Supply Voltage VDD 19 N — — — — — VDD VDD Output VIN 20 N — — — — — VIN Input Supply Voltage VS 21 N — — — — — — Output Voltage Sense IFB 22 N — — — — — — Error Amplifier Feedback Input 23 N — — — — — — Error Amplifier Output ICOMP Note 1: 2: 3: 4: 5: 6: Output (6) The Analog/Digital Debug Output is selected through the control of the ABECON register. Selected when functioning as master or slave by proper configuration of the MSC bits in the MODECON register. The IOC is disabled when MCLR is enabled. Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. VREF2 output selected when configured as master by proper configuration of the MSC bits in the MODECON register. When RFB of MODECON = 0, the internal feedback resistor and DESATP input are enabled. When RFB = 1, ISOUT is enabled.  2015-2020 Microchip Technology Inc. DS20005479D-page 3 MCP19116/7 GPB6/AN7/TX/CK GPB5/AN6/ICSPCLK GPB1/AN4/VREF2 ICOMP IFB VS VIN Pin Diagram – 28-Pin QFN (MCP19117) 28 27 26 25 24 23 22 GPA0/AN0/TEST_OUT 1 21 VDD GPA1/AN1/CLKPIN 2 20 VDR GPA2/AN2/T0CKI/INT 3 19 PDRV GPB4/AN5/ICSPDAT 4 18 SDRV GPA3/AN3 5 17 PGND GPA7/SCL 6 16 AGND GPA6/CCD 7 15 IP DS20005479D-page 4 MCP19117 10 11 12 GPB7CCD/RX/DT GPB0/SDA DESATN DESATP/ISOUT 13 14 ISN 9 ISP 8 GPA5/MCLR/TEST_EN EXP-29  2015-2020 Microchip Technology Inc. MCP19116/7 28-PIN QFN (MCP19117) SUMMARY I/O 28-Pin QFN ANSEL A/D Timers MSSP/AUSART Interrupt Pull-Up TABLE 2: Basic GPA0 1 Y AN0 — — IOC Y — Analog/Digital Debug Output (1) GPA1 2 Y AN1 — — IOC Y — Sync Signal In/Out (2) GPA2 3 Y AN2 T0CKI — IOC INT Y — — GPA3 5 Y AN3 — — IOC Y — — GPA5 8 N — — — GPA6 7 N — — — IOC Y — Dual Capture Input / Single Compare 1 Output IOC (3) Y (4) MCLR Additional Test Enable Input GPA7 6 N — — SCL IOC N — — GPB0 10 N — — SDA IOC N — — GPB1 26 Y AN4 — — IOC Y — VREF2 (5) GPB4 4 Y AN5 — — IOC Y ICSPDAT — GPB5 27 Y AN6 — — IOC Y ICSPCLK — GPB6 28 Y AN7 — TX/CK IOC Y — — GPB7 9 Y — — RX/DT IOC Y — Single Compare 2 Output DESATP/ ISOUT 12 N — — — — — — DESATP Input or ISOUT Output (6) DESATN 11 N — — — — — — DESAT Negative Input ISP 13 N — — — — Y — Current Sense Amplifier Non-inverting Input ISN 14 N — — — — — — Current Sense Amplifier Inverting Input Primary Input Current Sense IP 15 N — — — — — — AGND 16 N — — — — — AGND Small Signal Ground Large Signal Ground PGND 17 N — — — — — PGND SDRV 18 N — — — — — — Secondary LS Gate Drive Output PDRV 19 N — — — — — — Primary LS Gate Drive Output VDR 20 N — — — — — VDR Gate Drive Supply Voltage VDD 21 N — — — — — VDD VDD Output VIN 22 N — — — — — VIN Input Supply Voltage VS 23 N — — — — — — Output Voltage Sense IFB 24 N — — — — — — Error Amplifier Feedback input ICOMP 25 N — — — — — — Error Amplifier Output Note 1: 2: 3: 4: 5: 6: The Analog/Digital Debug Output is selected through the control of the ABECON register. Selected when functioning as master or slave by proper configuration of the MSC bits in the MODECON register. The IOC is disabled when MCLR is enabled. Weak pull-up always enabled when MCLR is enabled, otherwise the pull-up is under user control. VREF2 output selected when configured as master by proper configuration of the MSC bits in the MODECON register. When RFB of MODECON = 0, the internal feedback resistor is enabled allow with DESATP input. When RFB = 1, ISOUT is enabled.  2015-2020 Microchip Technology Inc. DS20005479D-page 5 MCP19116/7 Table of Contents Features ................................................................................................................................................................................................ 1 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Pin Description ........................................................................................................................................................................... 13 3.0 Functional Description................................................................................................................................................................ 19 4.0 Electrical Characteristics............................................................................................................................................................ 22 5.0 Digital Electrical Characteristics................................................................................................................................................. 31 5.0 Digital Electrical Characteristics................................................................................................................................................. 39 6.0 Configuring the MCP19116/7 ..................................................................................................................................................... 39 7.0 Typical Performance Curves ...................................................................................................................................................... 53 8.0 System Bench Testing................................................................................................................................................................ 57 9.0 Device Calibration ...................................................................................................................................................................... 59 10.0 Addressable USART Module...................................................................................................................................................... 69 11.0 Memory Organization ................................................................................................................................................................. 81 12.0 Device Configuration.................................................................................................................................................................. 93 13.0 Oscillator Modes ........................................................................................................................................................................ 95 14.0 Resets ........................................................................................................................................................................................ 97 15.0 Interrupts .................................................................................................................................................................................. 105 16.0 Power-Down Mode (Sleep) .......................................................................................................................................................115 17.0 Watchdog Timer (WDT).............................................................................................................................................................117 18.0 Flash Program Memory Control ................................................................................................................................................119 19.0 I/O Ports ................................................................................................................................................................................... 125 20.0 Interrupt-On-Change ................................................................................................................................................................ 133 21.0 Internal Temperature Indicator Module .................................................................................................................................... 137 22.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 139 23.0 Timer0 Module ......................................................................................................................................................................... 149 24.0 Timer1 Module ......................................................................................................................................................................... 151 25.0 Timer2 Module ......................................................................................................................................................................... 155 26.0 Enhanced PWM Module .......................................................................................................................................................... 157 28.0 Dual Capture/Compare (CCD) Module .................................................................................................................................... 163 27.0 PWM Control Logic .................................................................................................................................................................. 161 29.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 167 30.0 Instruction Set Summary...........................................................................................................................................................211 31.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 221 32.0 Development Support .............................................................................................................................................................. 223 33.0 Packaging Information ............................................................................................................................................................. 227 Appendix A: Revision History ............................................................................................................................................................. 233 INDEX ............................................................................................................................................................................................... 235 The Microchip Web Site ..................................................................................................................................................................... 241 Customer Change Notification Service .............................................................................................................................................. 241 Customer Support .............................................................................................................................................................................. 241 Product Identification System............................................................................................................................................................. 243 Trademarks ........................................................................................................................................................................................ 245 Worldwide Sales and Service ............................................................................................................................................................ 246 DS20005479D-page 6  2015-2020 Microchip Technology Inc. MCP19116/7 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2015-2020 Microchip Technology Inc. DS20005479D-page 7 MCP19116/7 NOTES: DS20005479D-page 8  2015-2020 Microchip Technology Inc. MCP19116/7 1.0 DEVICE OVERVIEW The MCP19116/7 devices are highly integrated, mixed-signal low-side synchronous controllers that operate from +4.5V to +42V. The family features an analog PWM controller with an integrated microcontroller core used for LED lighting systems, battery chargers and other low-side switch PWM applications. The MCP19116/7 devices are derived from the MCP19114/5, which share the same features and characteristics except for the addition of larger program memory (8k words vs. 4k words) and several design enhancements. These enhancements were added to the MCP19116/7 devices to improve calibration, increase accuracy and provide greater flexibility. The devices feature an analog internal PWM controller similar to the MCP1631, and a standard PIC® microcontroller similar to the PIC12F617. Complete customization of device operating parameters, start-up or shutdown profiles, protection levels and fault handling procedures are accomplished by setting digital registers using Microchip’s MPLAB® X Integrated Development Environment software and one of Microchip’s many in-circuit debugger and device programmers. The MCP19116/7 mixed-signal low-side synchronous controllers feature integrated programmable input UVLO/OVLO, programmable output overvoltage (OV), two low-side gate drive outputs with independent programmable dead time, programmable leading edge blanking (four steps), programmable 6-bit slope compensation and an integrated internal programmable oscillator for fixed-frequency applications. An integrated 8-bit reference voltage (VREF) is used for setting output current or voltage. An internal comparator supports quasi-resonant applications. Additional Capture and Compare modules are integrated for increased control, including enhanced dimming capability. The MCP19116/7 devices contain two internal LDOs. A 5V LDO (VDD) is used to power the internal processor and provide 5V externally. A 4V LDO (AVDD) is used to power the internal analog circuitry. Either VDD or AVDD can be connected internally to the 10-bit Analog-to-Digital Converter reference input. The 5V external output can be used to supply the gate drive. An analog filter between the VDD output and the VDR input is recommended when implementing a 5V gate drive supplied from VDD. Two 4.7 µF capacitors are recommended with one placed as close as possible to VDD and one as close as possible to VDR, separated by a 10 isolation resistor. DO NOT exceed 10 µF on the VDD. An external supply is required to implement higher gate drive voltages. A 4V LDO is used to power the internal analog circuitry. The two low-side drivers can be used to operate the power converter in bidirectional mode, enabling the “shaping” of LED dimming current in LED applications or developing bidirectional power converters for battery-powered applications. The MCP19116 is packaged in a 24-lead 4 mm x 4 mm QFN. The MCP19117 is packaged in a 28-lead 5 mm x 5 mm QFN. The ability for system designers to configure application-specific features allows users of the MCP19116/7 devices to save costly board real estate and additional component costs. The General Purpose Input/Output (GPIO) of the MCP19116/7 can be configured to offer a status output: • a device enable, to control an external switch • a switching frequency synchronization output or input • and even a device status or "heartbeat" indicator With integrated features like output current adjustment and dynamic output voltage positioning, the MCP19116/7 family has the best in-class performance and highest integration level currently available. Power trains supported by this architecture include but are not limited to boost, flyback, quasi-resonant flyback, SEPIC, Ćuk, etc. Two low-side gate drivers are capable of sinking and sourcing 1A at 10V VDR. With a 5V gate drive, the driver is capable of 0.5A sink and source. The user has the option to allow the VIN UVLO to shut down the drivers by setting the UVLOEN bit. When this bit is not set, the device drivers will ride through the UVLO condition and continue to operate until VDR reaches the gate drive UVLO value. This value is selectable at 2.7V or 5.4V and is always enabled. An internal reset for the microcontroller core is set to 2.0V. An internal comparator module is used to sense the desaturation of the flyback transformer to synchronize switching for quasi-resonant applications. The operating input voltage for normal device operation ranges from +4.5V to +42V with an absolute maximum of 44V. The maximum transient voltage is 48V for 500 ms. An I2C serial bus is used for device communications from the PWM controller to the system. By utilizing a Microchip Technology Incorporated TC1240A voltage doubler supplied from VDD to provide VDR, a 10V gate drive can be achieved.  2015-2020 Microchip Technology Inc. DS20005479D-page 9 MCP19116/7 FLYBACK SYNCHRONOUS QUASI-RESONANT BLOCK DIAGRAM VIN VS 4.5V to 42V VIN 8 OV OV_REF OV REF Bias Gen Lin 8 VREF2 VREF2 Lin 8 VZC VREF + RFB_INT 5K BGAP OVLO_REF - VZC 6 Icomp PWM Logic BGAP EA_SC ISP A = 10 A2 A2 PWM Comp RFB MUX Interrupt and Logic to PWM & PIC VDR UVLO DESATP VDR Gate Drive Timing IP_COMP PGND 4 DESATN QRS Place recommended VDD and VDR 4.7 µF Capacitors as close to respective pins as possible VDR Gate Drive Timing OV VZC PDRV PWM PGND BGAP AMUX ADC REF OSC PIC CORE ccd DMUX  2015-2020 Microchip Technology Inc. OV UVLO OVLO VDD_OK VDD VDD or AVDD AGND AGND PGND PGND 4.7 µF ISP ISN 4 ADJ Offset Lin I/O 10Ÿ SDRV SDRV 2 DESATP/ ISOUT 4.7 µF 2.7V or 5.4V LEB DESAT MUX VDD 4 ISN IP VDD DESATN 8.8V to 44V 5V to 10V VDR OVLO + Slope Comp Log VZC 2 lsb 4 msb OC 4 msb Clamp BG VDD 4V to 20V UVLO - A1 Icomp IP UVLO_REF See elec specs for clamp voltages IFB PDRV BGAP EN BGAP IFB VDD AVDD 2 lsb BGAP Lin VREF VDD (5V) AVDD (4V) LDO1 LDO2 VREF2 MUX to GPB1 MCLR SDA TEMP DIMI EN1 EN2 I/O x 3 BIN (x7 MCP19117) GPIO GPIO MCP19116/7 DS20005479D-page 10 FIGURE 1-1: MCP19116/7 FIGURE 1-2: MCP19116 ĆUK SYNCHRONOUS POSITIVE OUTPUT APPLICATION DIAGRAM VIN TC1240 VOLTAGE DOUBLER 5V 10V EN VIN MCLR DIMI CCD VDR VDD PDRV IP MCP19116 I/O TEMP SNS 2 DESATN 4x4 24-LD QFN VDD I/O DESATP SDRV ISN ISP IFB VDD ICOMP VS BIN 2 I/O I/O AGND FIGURE 1-3: PGND I/O MCP19116 BOOST QUASI-RESONANT APPLICATION DIAGRAM VIN DESATN DESATP 5V VDR VIN EN VDD MCLR DIMI PDRV CCD IP I/O SW2 I/O 2 TEMP SNS DESATN DESATP I MCP19116 SOUT IFB I/O VDD BIN 2 4x4 24-LD QFN VDD SW1 ICOMP DESATP SW1 SW2 ISP ISN VS SDRV I/O AGND DESATN PGND  2015-2020 Microchip Technology Inc. DS20005479D-page 11 MCP19116/7 FIGURE 1-4: MICROCONTROLLER CORE BLOCK DIAGRAM Configuration 13 Flash 8 Data Bus Program Counter PORTA GPA0 GPA1 8000 x 14 Program Memory GPA2 RAM 336 bytes 8 Level Stack (13-bit) GPA3 File Registers GPA5 Program 14 Bus RAM Addr 9 GPA6 Addr MUX Instruction reg Direct Addr 7 8 GPA7 Indirect Addr PORTB FSR reg GPB0 GPB1 STATUS reg 8 GPB4 (MCP19117) 3 Instruction Decode & Control TESTCLKIN Timing Generation GPB5 (MCP19117) MUX Power-up Timer GPB6 (MCP19117) GPB7 (MCP19117) ALU Power-on Reset 8 AUSART W reg TX/CK RX/DA Watchdog Timer SDA 8 MHz Internal Ocillator I2C SCL MCLR VIN PMDATL AGND Self read/write flash memory Timer0 Timer1 Timer2 T0CKI Analog Interface Registers Enhanced CCD EEADDR Enhanced PWM GPA6 GPB7 (MCP19117) DS20005479D-page 12  2015-2020 Microchip Technology Inc. MCP19116/7 2.0 PIN DESCRIPTION The 24-lead MCP19116 and 28-lead MCP19117 devices feature pins that have multiple functions associated with each pin. Table 2-1 provides a description of the different functions. Refer to Section 2.1 “Detailed Pin Functional Description” for detailed information. TABLE 2-1: MCP19116/7 PINOUT DESCRIPTION Name Function Input Type GPA0 TTL AN0 AN — A/D Channel 0 input TEST_OUT — — Internal analog/digital signal multiplexer output (1) GPA1 TTL AN1 AN CLKPIN ST CMOS Switching-frequency clock input or output (2) GPA2 ST CMOS General purpose I/O AN2 AN — A/D Channel 2 input T0CKI ST — Timer0 clock input INT ST — External interrupt GPA3 TTL AN3 AN — A/D Channel 3 input GPA0/AN0/TEST_OUT GPA1/AN1/CLKPIN GPA2/AN2/T0CKI/INT GPA3/AN3 — A/D Channel 1 input CMOS General purpose I/O — General purpose input only ST — Master Clear with internal pull-up GPA6 ST CMOS General purpose I/O ICSPDAT ST CMOS Serial Programming Data I/O (MCP19116 only) CCD ST CMOS Dual Capture Input. CCD1 Single Compare output RX ST — USART asynchronous serial receive (MCP19116 only) DT ST GPA7 ST OD General purpose open drain I/O SCL 2 OD I2C clock I C CMOS USART synchronous serial data (MCP19116 only) ICSPCLK ST — Serial Programming Clock (MCP19116 only) GPB0 TTL OD General purpose I/O SDA I2C OD I2C data input/output GPB1 TTL AN4 AN — A/D Channel 4 input VREF2 — AN VREF2 DAC Output (3) TX — CMOS USART asynchronous serial transmit (MCP19116 only) CK ST CMOS USART synchronous serial clock (MCP19116 only) GPB0/SDA GPB1/AN4/VREF2/TX/CK TX/CK (MCP19116 Only) Legend: AN = Analog input or output TTL = TTL compatible input 2: 3: CMOS General purpose I/O TTL GPA7/SCL/ICSPCLK Note 1: CMOS General purpose I/O GPA5 GPA6/CCD/ICSPDAT/RX/DT ICSPCLK (MCP19116 only) Description MCLR GPA5/MCLR ICSPDAT/RX/DT (MCP19116 Only) Output Type CMOS General-purpose I/O CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels OD = Open-Drain I2C = Schmitt Trigger input with I2C The Analog/Digital Debug Output is selected through the control of the ABECON register. Selected when functioning as master or slave by proper configuration of the MSC bits in the MODECON register. VREF2 output selected when configured as master by proper configuration of the MSC bits in the MODECON register.  2015-2020 Microchip Technology Inc. DS20005479D-page 13 MCP19116/7 TABLE 2-1: MCP19116/7 PINOUT DESCRIPTION (CONTINUED) Name GPB4/AN5/ICSPDAT (MCP19117 Only) GPB5/AN6/ICSPCLK (MCP19117 Only) GPB6/AN7/TX/CK (MCP19117 Only) GPB7/CCD/RX/DT (MCP19117 Only) Function Input Type GPB4 TTL Output Type Description CMOS General purpose I/O AN5 AN ICSPDAT ST CMOS Primary Serial Programming Data I/O — A/D Channel 5 input GPB5 TTL CMOS General purpose I/O AN6 AN — A/D Channel 6 input — Primary Serial Programming Clock ISCPCLK ST GPB6 TTL AN7 AN TX — CMOS USART asynchronous serial transmit CK ST CMOS USART synchronous serial clock GPB7 TTL CMOS General purpose I/O CCD ST CMOS CCD2 Single Compare output. RX ST CMOS General purpose I/O — — A/D Channel 7 input USART asynchronous serial receive DT ST VIN VIN — CMOS USART synchronous serial data — Device input supply voltage VDD VDD — — Internal +5V LDO output pin VDR VDR — — Gate drive supply voltage AGND AGND — — Small signal quiet ground PGND PGND — — Large signal power ground PDRV PDRV — — Primary low-side MOSFET gate drive SDRV SDRV — — Secondary low-side MOSFET gate drive IP IP — — Primary input current sense ISN ISN — — Secondary-current sense-amplifier negative input ISP ISP — — Secondary-current sense-amplifier positive input VS VS — — Sense voltage compared to overvoltage DAC IFB IFB — — Error amplifier feedback input ICOMP — — Error amplifier output DESATP/ISOUT — — DESATP: DESAT detect comparator positive input ISOUT: Secondary-current sense-amplifier output DESATN — — DESATN: DESAT detect comparator negative input ICOMP DESATP/ISOUT DESATN Legend: AN = Analog input or output TTL = TTL compatible input Note 1: 2: 3: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels OD = Open-Drain I2C = Schmitt Trigger input with I2C The Analog/Digital Debug Output is selected through the control of the ABECON register. Selected when functioning as master or slave by proper configuration of the MSC bits in the MODECON register. VREF2 output selected when configured as master by proper configuration of the MSC bits in the MODECON register. DS20005479D-page 14  2015-2020 Microchip Technology Inc. MCP19116/7 2.1 2.1.1 Detailed Pin Functional Description GPA0 PIN 2.1.5 GPA5 PIN GPA5 is a general purpose TTL input only pin. An internal weak pull-up and interrupt-on-change are also available. GPA0 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPA. An internal weak pull-up and interrupt-on-change are also available. For programming purposes, this pin is to be connected to the MCLR pin of the serial programmer. Refer to Section 31.0 “In-Circuit Serial Programming™ (ICSP™)” for more information. AN0 is an input to the A/D. To configure this pin to be read by the A/D on channel 0, bits TRISA0 and ANSA0 must be set. This pin is MCLR when the MCLRE bit is set in the CONFIG register. The ABECON register can be configured to set this pin to the TEST_OUT function. It is a buffered output of the internal analog or digital signal multiplexers. Analog signals present on this pin are controlled by the ADCON0 register. Digital signals present on this pin are controlled by the ABECON register. 2.1.6 2.1.2 MCP19116 Only: RX is the USART Asynchronous serial receive. GPA1 PIN GPA1 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPA. An internal weak pull-up and interrupt-on-change are also available. AN1 is an input to the A/D. To configure this pin to be read by the A/D on channel 1, bits TRISA1 and ANSA1 must be set. When the MCP19116/7 are configured as a master or slave, this pin is configured to be the switching-frequency synchronization input or output (CLKPIN). 2.1.3 GPA2 PIN GPA2 is a general-purpose ST input or CMOS output pin whose data direction is controlled in TRISGPA. An internal weak pull-up and interrupt-on-change are also available. AN2 is an input to the A/D. To configure this pin to be read by the A/D on channel 2, bits TRISA2 and ANSA2 must be set. When bit T0CS is set in the OPTION_REG register, the T0CKI function is enabled. Refer to Section 23.0 “Timer0 Module” for more information. GPA6 PIN GPA6 is a general-purpose CMOS output ST input pin whose data direction is controlled in TRISGPA. ICSPDAT is a serial programming data I/O function. This can be used in conjunction with ICSPCLK to serial-program the device. MCP19116 Only: DT is the USART Synchronous serial clock. GPA6 is the Dual Capture input and CCD1 output compare. For more information, refer to Section 28.0 “Dual Capture/Compare (CCD) Module”. 2.1.7 GPA7 PIN GPA7 is a true open-drain general purpose pin whose data direction is controlled in TRISGPA. There is no internal connection between this pin and device VDD. This pin does not have a weak pull-up, but interrupt-on-change is available. This pin is the primary ICSPCLK input. This can be used in conjunction with ICSPDAT to serial program the device. When the MCP19116/7 is configured for I2C communication, GPA7 functions as the I2C clock (SCL). This pin must be configured as an input to allow proper operation. For more information, refer to Section 29.2 “I2C Mode Overview” GPA2 can also be configured as an external interrupt by setting the INTE bit. Refer to Section 15.2 “GPA2/INT Interrupt” for more information. 2.1.4 GPA3 PIN GPA3 is a general purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPA. An internal weak pull-up and interrupt-on-change are also available. AN3 is an input to the A/D. To configure this pin to be read by the A/D on channel 3, bits TRISA3 and ANSA3 must be set.  2015-2020 Microchip Technology Inc. DS20005479D-page 15 MCP19116/7 2.1.8 GPB0 PIN GPB0 is a true open-drain general-purpose pin whose data direction is controlled in TRISGPB. There is no internal connection between this pin and device VDD. This pin does not have a weak pull-up, but interrupt-on-change is available. When the MCP19116/7 are configured for I2C communication, GPB0 functions as the I2C data (SDA). This pin must be configured as an input to allow proper operation. For more information, refer to Section 29.2 “I2C Mode Overview”. 2.1.9 GPB1 PIN GPB1 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPB. An internal weak pull-up and interrupt-on-change are also available. AN4 is an input to the A/D. To configure this pin to be read by the A/D on channel 4, bits TRISB1 and ANSB1 must be set. MCP19116 Only: TX is the USART Asynchronous serial transmit. MCP19116 Only: CK is the USART Synchronous serial clock. 2.1.12 GPB6 PIN (MCP19117 ONLY) GPB6 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPB. An internal weak pull-up and interrupt-on-change are also available. AN7 is an input to the A/D. To configure this pin to be read by the A/D on channel 7, bits TRISB6 and ANSB6 must be set. MCP19117 Only: TX is the USART Asynchronous serial transmit. MCP19117 Only: CK is the USART Synchronous serial clock. 2.1.13 GPB7 PIN (MCP19117 ONLY) GPB7 is a general purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPB. An internal weak pull-up and interrupt-on-change are also available. RX is the USART Asynchronous serial receive. DT is the USART Synchronous serial clock. For more information, refer to Section 10.0 “Addressable USART Module” When the MCP19116/7 are configured as a master, this pin is configured to be the VREF2 DAC output. GPB7 is the CCD2 output Compare. For more information, refer to Section 28.0 “Dual Capture/Compare (CCD) Module”. 2.1.10 2.1.14 GPB4 PIN (MCP19117 ONLY) DESATN PIN GPB4 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPB. An internal weak pull-up and interrupt-on-change are also available. Internal comparator inverting input. Used during Quasi-Resonant operation for desaturation detection. AN5 is an input to the A/D. To configure this pin to be read by the A/D on channel 5, bits TRISB4 and ANSB4 must be set. When using the internal comparator for desaturation detection during Quasi-Resonant operation, this pin connects to the comparator’s noninverting input. The output of the remote sense current-sense amplifier gets configured to utilize the 5 k internal feedback resistor. When not utilizing the internal comparator and not configured to use the 5 k internal feedback resistor, the current sense amplifier gets connected to this pin and is ISOUT. ICSPDAT is the primary serial-programming data I/O function. This is used in conjunction with ICSPCLK to serial program the device. 2.1.11 GPB5 PIN (MCP19117 ONLY) GPB5 is a general-purpose TTL input or CMOS output pin whose data direction is controlled in TRISGPB. An internal weak pull-up and interrupt-on-change are also available. AN6 is an input to the A/D. To configure this pin to be read by the A/D on channel 6, bits TRISB5 and ANSB5 must be set. ICSPCLK is the primary serial-programming clock function. This is used in conjunction with ICSPDAT to serial program the device. DS20005479D-page 16 2.1.15 2.1.16 DESATP/ISOUT PIN ISP PIN The noninverting input to internal current-sense amplifier, typically used to differentially remote-sense secondary current. This pin can be internally pulled-up to VDD by setting the bit in the PE1 register. 2.1.17 ISN PIN The inverting input to internal current-sense amplifier, typically used to differentially remote-sense secondary current.  2015-2020 Microchip Technology Inc. MCP19116/7 2.1.18 IP PIN Primary input current-sense for current mode control and peak current limit. For voltage mode control, this pin can be connected to an artificial ramp. 2.1.19 AGND PIN AGND is the small signal ground connection pin. This pin should be connected to the exposed pad on the bottom of the package. 2.1.20 2.1.27 IFB PIN Error-amplifier inverting feedback connection. 2.1.28 ICOMP PIN Error-amplifier output signal. 2.1.29 EXPOSED PAD (EP) It is recommended to connect the exposed pad to AGND. PGND PIN Connect all large-signal level ground returns to PGND. These large-signal level ground traces should have a small loop area and minimal length to prevent coupling of switching noise to sensitive traces. 2.1.21 SDRV PIN The gate of the low-side secondary MOSFET is connected to SDRV. The PCB trace connecting SDRV to the gate must be of minimal length and appropriate width to handle the high-peak drive current and fast voltage transitions. 2.1.22 PDRV PIN The gate of the low-side primary MOSFET is connected to PDRV. The PCB tracing connecting PDRV to the gate must be of minimal length and appropriate width to handle the high-peak drive currents and fast voltage transitions. 2.1.23 VDR PIN The supply for the low-side drivers is connected to this pin and has an absolute maximum rating of +13.5V. This pin can be connected by an RC filter to the VDD pin. 2.1.24 VDD PIN The output of the internal +5.0V regulator is connected to this pin. It is recommended that a 1.0 µF minimum/ 10 µF maximum bypass capacitor be connected between this pin and the GND pin of the device. The bypass capacitor should be physically placed close to the device. 2.1.25 VIN PIN Input power connection pin of the device. It is recommended that capacitance be placed between this pin and the GND pin of the device. 2.1.26 VS PIN Analog input connected to the non-inverting input of the overvoltage comparator. Typically used as output-voltage overvoltage protection. The inverting input of the overvoltage comparator is controlled by the OV REF DAC.  2015-2020 Microchip Technology Inc. DS20005479D-page 17 MCP19116/7 NOTES: DS20005479D-page 18  2015-2020 Microchip Technology Inc. MCP19116/7 3.0 3.1 FUNCTIONAL DESCRIPTION Linear Regulators The operating input voltage for the MCP19116/7 ranges from +4.5V to +42V. There are two internal Low Dropout (LDO) voltage regulators. A 5V LDO is used to power the internal processor and provide a 5V output for external usage. A second LDO (AVDD) is a 4V regulator and is used to power the remaining analog internal circuitry. AVDD is factory calibrated and is the default ADC reference voltage. The ADC reference is switchable between AVDD and VDD. Using an LDO to power the MCP19116/7, the input voltage is monitored using a resistor divider. The MCP19116/7 also incorporate brown-out protection. Refer to Section 14.3 “Brown-Out Reset (BOR)” for details. The PIC core will reset at 2.0V VDD. 3.2 Output Drive Circuitry The MCP19116/7 integrate two low-side drivers used to drive the external low-side N-Channel power MOSFETs for synchronous applications, such as synchronous flyback and synchronous Ćuk converters. Both converter types can be configured for non-synchronous control by replacing the synchronous FET with a diode. The flyback is also capable of quasi-resonant operation. The MCP19116/7 can also be configured as a Boost or SEPIC switch-mode power supply (SMPS). In Boost mode, nonsynchronous fixed-frequency or nonsynchronous quasi-resonant control can be utilized. This device can also be used as a SEPIC SMPS in fixed-frequency nonsynchronous mode. The low-side drive is capable of switching the MOSFET at high frequency in typical SMPS applications. The gate drive (VDR) can be supplied from 5V to 10V. The drive strength is capable of up to 1A sink/source with 10V gate drive and down to 0.5A sink/source with 5V gate drive. A programmable delay is used to set the gate turn-on dead time. This prevents overlap and shoot-through currents that can decrease the converter efficiency. Each driver has its own EN input controlled by the microcontroller core. 3.3 Current Sense The output current is differentially sensed by the MCP19116/7. In low-current applications, this helps maintain high system efficiency by minimizing power dissipation in current-sense resistors. Differential current sensing also minimizes external ground-shift errors. The internal differential amplifier has a typical gain of 10 V/V and is factory trimmed.  2015-2020 Microchip Technology Inc. 3.4 Peak Current Mode The MCP19116/7 is a peak current mode controlled device with the current-sensing element in series with the primary side MOSFET. Programmable leading edge blanking can be implemented to blank current spikes resulting from turn on. The blank time is controlled from the ICLEBCON register. Primary-input current-offset adjust is also available via user programmability, thus limiting peak primary input current. This offset adjustment is controlled by the ICOACON register. 3.5 Magnetic Desaturation Detection An internal comparator module is used to detect power train magnetic desaturation for quasi-resonant applications. The comparator output is used as a signal to synchronize the start of the next switching cycle. This operation differs from the traditional fixed-frequency application. The DESAT comparator output can be enabled and routed into the PWM circuitry or disabled for fixed-frequency applications. During Quasi-Resonant (QR) operation, the DESAT comparator output is enabled and combined with a pair of one-shot timers and a flip-flop to sustain PWM operation. Timer2 (TMR2) must be initialized and set to run at a frequency lower than the minimum QR operating frequency. When the CDSWDE bit is set in the DESATCON register, TMR2 serves as a watchdog. An example of the order of events for a Flyback SMPS in synchronous QR operation is as follows: • the primary gate drive (PDRV) goes high • the output of the DESAT comparator is high • the primary current increases until IP reaches the level of the Error Amp and causes PWM comparator output to go low • the PDRV goes low and the secondary gate drive (SDRV) goes high (after programmed dead time). This triggers the first one-shot to send a 200 ns pulse that resets the flip-flop and TMR2 (WDM_RESET) • the 200 ns one-shot pulse design is implemented to mask any spurious transitions at the DESAT comparator output caused by switching noise • the SDRV stays high until the secondary winding completely runs out of energy, at which time the output capacitance begins to source current back through the winding and secondary MOSFET • the DESAT comparator detects this and its output goes low. This sets the flip-flop and triggers the second one-shot to send a 33 ns pulse to the control logic, causing the SDRV to go low and the PDRV to go high (after programmed dead time) • the cycle then repeats. If, for any reason, the reset one-shot does not fire, the WDM_RESET signal stays low and TMR2 is allowed to run until the PWM signal kicks off a new cycle DS20005479D-page 19 MCP19116/7 The desaturation comparator module is controlled by the DESATCON register. terminated and the external PDRV switch is latched off until the beginning of the next cycle which begins at the next clock cycle. 3.6 To improve current regulation at low levels, a pedestal voltage (VZC) set to the BG (1.23V) is implemented. This virtual ground serves as the reference for the error amplifier (A1), slope compensation, current sense amplifier (A2) and the IP offset adjustment. Start-Up To control the output current during start-up, the MCP19116/7 devices have the capability to monotonically increase system current at the user’s discretion. This is accomplished through the control of the reference voltage DAC (VREF). Users also have firmware control over the switching frequency through Timer2 and the PR2 register. Maximum duty-cycle control is established through the PWMRL register. Refer to Section 26.0, Enhanced PWM Module for details. The entire start-up profile is under user control via software. 3.7 Driver Control Circuitry The internal driver control circuitry of the MCP19116/7 is comprised of an error amplifier (EA), a high-speed comparator and a latch similar to the MCP1631. The error amplifier generates the control voltage used by the high-speed PWM comparator. There is an internally generated reference voltage, VREF. The difference or error between this internal reference voltage and the actual feedback voltage is the control voltage. Some applications will implement parked times where the gate drives are not active. For example, when changing between LED strings and after voltage repositioning, the user can disable the gate drives and park the error amplifier output low. During the time when the EA is parked, its output will be clamped low (1 * BG) such that it is in a known state when reactivated. Before the output switches are re-enabled, it may be necessary to re-enable the EA some time prior to enabling the output drivers. This prior-EA enable time will allow the EA to slew towards the intended target and prevent the secondary switch from turning on for an extensive period of time, unintentionally discharging the output capacitance and pulling the output voltage down. External compensation is used to stabilize the control system. Since the MCP19116/7 devices are peak current mode controlled, the comparator compares the primary peak current waveform (IP) that is based upon the current flowing in the primary side with the error amplifier control output voltage. This error amplifier control output voltage also has user-programmable slope compensation subtracted from it. In fixed-frequency applications, the slope compensation signal is generated to be greater than 1/2 the down slope of the inductor current waveform and is controlled by the SLPCRCON register. Offset adjust ability is also available to set the peak current limit of the primary switch for overcurrent protection. The range of the slope compensation ramp is specified. When the current sense signal reaches the level of the control voltage minus slope compensation, the ON cycle is DS20005479D-page 20 An S-R latch (Set-Rest-Flip-Flop) is used to prevent the PWM circuitry from turning the external switch on until the beginning of the next clock cycle. 3.8 Fixed PWM Frequency The switching frequency of the MCP19116/7 while not controlled by the DESAT comparator output is generated by using a single edge of the 8 MHz internal clock. The user sets the MCP19116/7 switching frequency by configuring the PR2 register. The maximum allowable PDRV duty cycle is adjustable and is controlled by the PWMRL register. The programmable range of the switching frequency will be 31.25 kHz to 2 MHz. The available switching frequency below 2 MHz is defined as FSW = 8 MHz/N, where N is a whole number between 4  N  256. Refer to Section 26.0 “Enhanced PWM Module” for details. 3.9 VREF This reference is used to generate the voltage connected to the noninverting input of the error amplifier. The entire analog control loop is raised to a virtual ground pedestal equal to the Band Gap voltage (1.23V). 3.10 OV REF This reference is used to set the output overvoltage set point. It is compared to the VS input pin, which is typically proportional to the output voltage based on a resistor divider. OV protection, when enabled, can be set to a value for the protection of system circuitry, or it can be used to “ripple” regulate the converter output voltage for repositioning purposes. For details, refer to Register 6-4. 3.11 Independent Gate Drive with Programmable Delay Two independent low-side gate drives are integrated for synchronous applications. Programmable delay has been implemented to improve efficiency and prevent shoot-through currents. Each gate drive has an independent enable input controlled by the PE1 register and programmable dead time controlled by the DEADCON register.  2015-2020 Microchip Technology Inc. MCP19116/7 3.12 3.12.1 Temperature Management THERMAL SHUTDOWN To protect the MCP19116/7 from overtemperature conditions, a 150°C junction temperature thermal shutdown has been implemented. When the junction temperature reaches this limit, the device disables the output drivers. In Shutdown mode, both PDRV and SDRV outputs are disabled and the overtemperature flag (OTIF) is set in the PIR2 register. When the junction temperature is reduced by 20°C to 130°C, the MCP19116/7 can resume normal output drive switching. 3.12.2 TEMPERATURE REPORTING The MCP19116/7 devices have a second on-chip temperature monitoring circuit that can be read by the ADC through the analog test MUX. Refer to Section 21.0 “Internal Temperature Indicator Module” for details on this internal temperature monitoring circuit.  2015-2020 Microchip Technology Inc. DS20005479D-page 21 MCP19116/7 4.0 ELECTRICAL CHARACTERISTICS 4.1 ABSOLUTE MAXIMUM RATINGS † VIN - VGND (DC).......................................................................................................................................... –0.3V to +44V VIN (transient < 500 ms) ............................................................................................................................................+48V PDRV ..................................................................................................................................(GND - 0.3V) to (VDR + 0.3V) SDRV ................................................................................................................................. (GND - 0.3V) to (VDR + 0.3V) VDD Internally Generated .........................................................................................................................................+6.5V VDR Externally Generated ......................................................................................................................................+13.5V Voltage on MCLR with respect to GND .................................................................................................... -0.3V to +13.5V Maximum voltage: any other pin ......................................................................................+(VGND - 0.3V) to (VDD + 0.3V) Maximum output current sunk by any single I/O pin ...............................................................................................25 mA Maximum output current sourced by any single I/O pin ..........................................................................................25 mA Maximum current sunk by all GPIO.........................................................................................................................90 mA Maximum current sourced by all GPIO .................................................................................................................. 35 mA Storage Temperature..............................................................................................................................–65°C to +150°C Maximum Junction Temperature ........................................................................................................................... +150°C Operating Junction Temperature ............................................................................................................–40°C to +125°C ESD protection on all pins (HBM)........................................................................................................................... 1.0 kV CDM protection on corner pins............................................................................................................................. +/-750V CDM protection on other pins............................................................................................................................... +/-500V † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 4.2 Electrical Characteristics Electrical Specifications: Unless otherwise noted, VIN = 12V, FSW = 150 kHz, TA = +25°C. Boldface specifications apply over the TA range of –40°C to +125°C. Parameters Sym. Min. Typ. Max. Units Conditions VIN 4.5 — 42 V IQ — 6 7.5 mA — 6 7.5 — 50 80 µA VIN = 12V (Note 1) VDD 4.75 5.1 5.5 V VIN = 6.0V to 42V IDD_OUT 35 — — mA VIN = 6.0V to 42V (Note 2) Internal Circuitry Bias Voltage during SLEEP VDD_SLEEP 2.4 — 4 V VIN = 4.5V to 42V IDD_OUT = 1mA Maximum Available External VDD Output Current During SLEEP IDD_OUT_SLEEP 1 — — mA VIN = 6.0V to 42V VDD = VDD_SLEEP Input Input Voltage Input Quiescent Current Shutdown Current ISHDN VIN = 12V, Not switching VIN = 20V, Not switching Linear Regulator VDD Internal Circuitry Bias Voltage Maximum External VDD Output Current Note 1: 2: 3: 4: 5: 6: Refer to Section 16.0, Power-Down Mode (Sleep). VDD is the voltage present at the VDD pin. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential between VIN and VDD. Ensured by design, not production tested. These parameters are characterized, but not production tested. The VDD LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a maximum of 15 mA. DS20005479D-page 22  2015-2020 Microchip Technology Inc. MCP19116/7 4.2 Electrical Characteristics (Continued) Electrical Specifications: Unless otherwise noted, VIN = 12V, FSW = 150 kHz, TA = +25°C. Boldface specifications apply over the TA range of –40°C to +125°C. Parameters Sym. Min. Typ. Max. Units Line Regulation VDD-OUT/ (VDD-OUT * VIN) –0.1 0.002 0.1 %/V (VDD + 1.0V)  VIN  20V (Note 2) Load Regulation VDD-OUT/ VDD-OUT –1.0 0.1 1.0 % IDD_OUT = 1 mA to 20 mA (Note 2) IDD_SC — 50 — mA Dropout Voltage VIN – VDD — 0.3 0.5 V IDD_OUT = 20 mA (Notes 2 and 3) Power Supply Rejection Ratio PSRRLDO — 60 — dB f  1000 Hz IDD_OUT = 25 mA CIN = 0 µF, CDD = 1 µF Internal Analog Supply Voltage AVDD — 4.096 — V AVDD Tolerance AVDD_TOL –2.5 ±0.5 2.5 % Trimmed at 25°C, 0°C to 125°C Output Short-Circuit Current Conditions VIN = (VDD + 1.0V) (Note 2) Linear Regulator AVDD Band Gap Voltage Band Gap Tolerance –3.3 — 3.3 % -40°C to 0°C BG — 1.23 — V Trimmed at 1.0% tolerance BGTOL –2.5 — 2.5 % Input UVLO Voltage UVLO Range UVLOON 4 — 20 V VIN Falling UVLOON Trip Tolerance UVLOTOL –14 — 14 % VIN Falling UVLO trip set to 9V VINUVLO = 0x21h UVLO Hysteresis UVLOHYS 1 4 8 % Hysteresis is based upon the UVLOON setting UVLO trip set to 9V VINUVLO = 0x21h nbits — 6 — bits Logarithmic Steps TD — 5 — µs 100 ns rise time to 1V overdrive on VIN VIN > UVLO to flag set OVLO Range OVLOON 8.8 — 44 V VIN Rising OVLOON Trip Tolerance OVLOTOL –14 — 14 % VIN Rising OVLO trip set to 18V VINOVLO = 0x1Fh Resolution UVLO Comparator Input-to-Output Delay Input OVLO Voltage Note 1: 2: 3: 4: 5: 6: Refer to Section 16.0, Power-Down Mode (Sleep). VDD is the voltage present at the VDD pin. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential between VIN and VDD. Ensured by design, not production tested. These parameters are characterized, but not production tested. The VDD LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a maximum of 15 mA.  2015-2020 Microchip Technology Inc. DS20005479D-page 23 MCP19116/7 4.2 Electrical Characteristics (Continued) Electrical Specifications: Unless otherwise noted, VIN = 12V, FSW = 150 kHz, TA = +25°C. Boldface specifications apply over the TA range of –40°C to +125°C. Parameters OVLO Hysteresis Resolution Sym. Min. Typ. Max. Units Conditions OVLOHYS 1 5 8 % nbits — 6 — bits Logarithmic Steps TD — 5 — µs 100 ns rise time to 1V overdrive on VIN VIN > OVLO to flag set nbits — 8 — bits Linear DAC Hysteresis is based upon the OVLOON setting OVLO trip set to 18V VINOVLO = 0x1Fh OVLO Comparator Input-to-Output Delay Output OV DAC Resolution Full-Scale Range FSR 0 — 2 * BG V OVREFTOL –2.0 ±0.3 2.0 % Trimmed @ code = 0xCC at 25°C, 0°C to 125°C –3.3 — 3.3 % –40°C to 0°C OVHYS — 50 — mV Input Bias Current IBIAS — ±1 — µA Common-Mode Input Voltage Range VCMR 0 — 3.0 V Note 4 Input-to-Output Delay TD — 200 — ns 100 ns rise time to 1V overdrive on VS VS > OV to flag set (Note 4) Linear DAC Tolerance Output OV Comparator OV Hysteresis Voltage Reference DAC (VREF) Resolution nbits — 8 — bits Full-Scale Range FSR BG — 2 * BG V Pedestal set to BG VREF_TOL –2.0 ±0.2 2.0 % Trimmed @ code = 0xCC at 25°C, 0°C to 125°C –3.3 — 3.3 % –40°C to 0°C Tolerance Note 1: 2: 3: 4: 5: 6: Refer to Section 16.0, Power-Down Mode (Sleep). VDD is the voltage present at the VDD pin. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential between VIN and VDD. Ensured by design, not production tested. These parameters are characterized, but not production tested. The VDD LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a maximum of 15 mA. DS20005479D-page 24  2015-2020 Microchip Technology Inc. MCP19116/7 4.2 Electrical Characteristics (Continued) Electrical Specifications: Unless otherwise noted, VIN = 12V, FSW = 150 kHz, TA = +25°C. Boldface specifications apply over the TA range of –40°C to +125°C. Parameters Sym. Min. Typ. Max. Units — 8 — bits Conditions Voltage Reference DAC (VREF2) Resolution nbits Full-Scale Range Tolerance Sink Current Source Current Linear DAC FSR 0 — BG V VREF2_TOL –2.2 ±0.2 2.2 % Trimmed @ code = 0xCC at 25°C, 0°C to 125°C –3.3 — 3.3 % –40°C to 0°C ISINK –3.0 — — mA VREF2 = 0x29 ISINK = 3 mA VREF2 < 60 mV ISOURCE 3.0 — — mA VREF2 = 0xFF ISOURCE = 3 mA VREF2 < 60mV — 2 — mV Trimmed Current Sense Amplifier (A2) Input Offset Voltage VOS Amplifier PSRR PSRR — 65 — dB VCM = 2 * BG Closed-Loop Voltage Gain A2VCL — 10 — V/V RL = 5 k to 2.048V, 100 mV < A2 < AVDD – 100 mV, VCM = BG Closed Loop Voltage Gain Tolerance A2VCL_TOL –2.0 0.5 2.0 % VOL — 300 — mV RL = 5 k to 2.048V Gain-Bandwidth Product GBWP — 10 — MHz AVDD = 4V Input Impedance RIN — 10 — k ISINK –3.0 — — mA ISP = ISN = GND RL = 300 to 2 * BG Source Current ISOURCE 3.0 — — mA ISP = ISN = GND RL = 300 to GND Common-Mode Range VCMR GND–0.3 — VBG+0.3 V Common-Mode Rejection Ratio CMRR — 70 — dB Internal Feedback Resistor RFB_INT — 5 — k Internal Feedback Resistor Tolerance RFB_INT_TOL — 2 — % Low-Level Output Sink Current Note 1: 2: 3: 4: 5: 6: Trimmed Note 4 Trimmed Refer to Section 16.0, Power-Down Mode (Sleep). VDD is the voltage present at the VDD pin. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential between VIN and VDD. Ensured by design, not production tested. These parameters are characterized, but not production tested. The VDD LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a maximum of 15 mA.  2015-2020 Microchip Technology Inc. DS20005479D-page 25 MCP19116/7 4.2 Electrical Characteristics (Continued) Electrical Specifications: Unless otherwise noted, VIN = 12V, FSW = 150 kHz, TA = +25°C. Boldface specifications apply over the TA range of –40°C to +125°C. Parameters Sym. Min. Typ. Max. Units Conditions VZC — VBG — V VOS — 2 — mV Trimmed CMRR — 65 — dB VCM = 0V to BG Open-Loop Voltage Gain AVOL — 70 — dB Note 4 Low-Level Clamp Value VOL BG – 0.35 V RL = 5 k to 2.048V GBWP — 3.5 — MHz ISINK –3 — — mA VREF = BG, IFB = ICOMP RL = 150 to 1.5 * BG Error Amplifier Source Current ISOURCE 3 — — mA VREF = 2 * BG IFB = ICOMP RL = 150 to 1.5 * BG Maximum Error Amplifier Output High-Level Clamp VEA_MAX — 2 x BG — V EA Output clamped to 2 x BG Voltage VIP_MAX — BG 1.5 V Note 4 TD — 11 20 ns Note 4 Pedestal Voltage Pedestal Voltage Level Error Amplifier (EA) Input Offset Voltage Common-Mode Rejection Ratio Gain-Bandwidth Product Error Amplifier Sink Current BG - 0.22 BG – 0.1 Peak Current Sense Input Maximum Primary Current Sense Signal Voltage PWM Comparator Input-to-Output Delay Peak Current Leading Edge Blanking Resolution LEB — 2 — bits LEBRANGE 0 — 256 ns OSADJ — 4 — bits Offset Adjustment Range OSADJ_RANGE 0 — 750 mV Offset Adjustment Step Size OSADJ_STEP — 50 — mV Blanking Time Adjustable Range 4-Step Programmable Range: 0, 50,100, and 200 ns (Note 4) Offset Adjustment (IP Sense) Resolution Note 1: 2: 3: 4: 5: 6: Linear Steps Refer to Section 16.0, Power-Down Mode (Sleep). VDD is the voltage present at the VDD pin. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential between VIN and VDD. Ensured by design, not production tested. These parameters are characterized, but not production tested. The VDD LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a maximum of 15 mA. DS20005479D-page 26  2015-2020 Microchip Technology Inc. MCP19116/7 4.2 Electrical Characteristics (Continued) Electrical Specifications: Unless otherwise noted, VIN = 12V, FSW = 150 kHz, TA = +25°C. Boldface specifications apply over the TA range of –40°C to +125°C. Parameters Sym. Min. Typ. Max. Units SCRES — 6 — bits Conditions Adjustable Slope Compensation Resolution Slope Log Steps m 3.14 — 432.5 mV/µs Slope Step Size SCSTEP — 8 — % Log Steps Ramp Set Point Tolerance mTOL — ±1 ±30 % Code 16d at 15.4mV/us Code 32d at 52.8mV/us Desaturation Detection Comparator Input Offset Voltage VOS — ±1 — mV Trimmed, 5-bits adjustable Input Bias Current IBIAS — ±1 — µA Internal Circuit Dependent Common-Mode Input Voltage Range VCMR GND – 0.3V — 2.7 V Note 4 Input-to-Output Delay TD — 20 — ns VDR_RIN — 220 — k VDR_UVLO (2.7V VDR Falling) VDR_UVLO_2.7_F 2.45 — 2.9 V VDR_UVLO (2.7 VDR Rising) VDR_UVLO_2.7_R 2.68 — 3.23 V VDR_UVLO (2.7V Hysteresis) VDR_UVLO 2.7 HYS 190 — 415 mV VDR_UVLO (5.4V VDR Falling) VDR_UVLO_5.4_F 4.7 — 5.96 V VDR_UVLO (5.4V VDR Rising) VDR_UVLO_5.4_R 5.15 — 6.56 V VDR_UVLO (5.4V Hysteresis) VDR_UVLO 5.4 HYS 380 — 830 mV VDR_UVLO VDR Resistance Output Driver (PDRV and SDRV) PDRV/SDRV Gate Drive Source Resistance RDR-SRC — — 13.5  VDR = 4.5V (Note 4) PDRV/SDRV Gate Drive Sink Resistance RDR-SINK — — 12  VDR = 4.5V (Note 4) PDRV/SDRV Gate Drive Source Current IDR-SRC — 0.5 — A — 1.0 — VDR = 5V VDR = 10V (Note 4) PDRV/SDRV Gate Drive Sink Current IDR-SINK — 0.5 — A — 1.0 — VDR = 5V VDR = 10V (Note 4) Note 1: 2: 3: 4: 5: 6: Refer to Section 16.0, Power-Down Mode (Sleep). VDD is the voltage present at the VDD pin. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential between VIN and VDD. Ensured by design, not production tested. These parameters are characterized, but not production tested. The VDD LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a maximum of 15 mA.  2015-2020 Microchip Technology Inc. DS20005479D-page 27 MCP19116/7 4.2 Electrical Characteristics (Continued) Electrical Specifications: Unless otherwise noted, VIN = 12V, FSW = 150 kHz, TA = +25°C. Boldface specifications apply over the TA range of –40°C to +125°C. Parameters Sym. Min. Typ. Max. Units DTRES — 4 — bits Dead-Time Adjustable Range DTRANGE 16 — 256 ns Dead-Time Step Size DTSTEP — 16 — ns Dead-Time Tolerance DTTOL — ±8 — ns Internal Oscillator Frequency FOSC 7.60 8.00 8.40 MHz Switching Frequency FSW — FOSC/N — MHz Switching Frequency Range Select N 4 — 255 — Conditions Dead-Time Adjustment Resolution Linear Steps Oscillator/PWM FMAX = 2 MHz A/D Converter (ADC) Characteristics Resolution NR — — 10 bits Integral Error EIL — — ±1 LSb VREF_ADC = AVDD VREF_ADC = VDD Differential Error EDL — — ±1 LSb No missing code in 10 bits VREF_ADC = AVDD VREF_ADC = VDD (Note 5) Offset Error EOFF — +3.0 +7 LSb VREF_ADC = AVDD VREF_ADC = VDD Gain Error EGN — ±2 ±6 LSb VREF_ADC = AVDD VREF_ADC = VDD VREF_ADC — AVDD — V AVDD = 4V ADCON1 VDD — V VDD = 5V ADCON1 GND — AVDD V AVDD selected as ADC Reference GND — VDD V VDD selected as ADC Reference Selectable ADC Reference Voltage Full-Scale Range Note 1: 2: 3: 4: 5: 6: FSRA/D Refer to Section 16.0, Power-Down Mode (Sleep). VDD is the voltage present at the VDD pin. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential between VIN and VDD. Ensured by design, not production tested. These parameters are characterized, but not production tested. The VDD LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a maximum of 15 mA. DS20005479D-page 28  2015-2020 Microchip Technology Inc. MCP19116/7 4.2 Electrical Characteristics (Continued) Electrical Specifications: Unless otherwise noted, VIN = 12V, FSW = 150 kHz, TA = +25°C. Boldface specifications apply over the TA range of –40°C to +125°C. Parameters Sym. Min. Typ. Max. Units Conditions ISINK_GPIO — — 90 mA Note 6 Maximum GPIO Source Current ISOURCE_GPIO — — 35 mA Note 6 GPIO Weak Pull-Up Current IPULL-UP_GPIO 50 250 400 µA VGPIO_IL GND — 0.8 V I/O Port with TTL buffer VDD = 5V GND — 0.2 VDD V I/O Port with Schmitt Trigger buffer, VDD = 5V GND — 0.2 VDD V MCLR 2.0 — VDD V I/O Port with TTL buffer, VDD = 5V 0.8VDD — VDD V I/O Port with Schmitt Trigger buffer, VDD = 5V GPIO Pins Maximum GPIO Sink Current GPIO Input Low Voltage GPIO Input High Voltage VGPIO_IH 0.8VDD — VDD V MCLR GPIO Output Low Voltage VGPIO_OL — — 0.12 VDD V IOL = 7 mA, VDD = 5V GPIO Output High Voltage VGPIO_OH VDD – 0.7 — — V IOH = 2.5 mA VDD = 5V GPIO Input Leakage Current GPIO_IIL — ±0.1 ±1 µA Negative current is defined as current sourced by the pin. VPOR — 2.13 — V VDD Rising VPOR_HYS — 100 — mV Thermal Shutdown TSHD — 150 — °C Thermal Shutdown Hysteresis TSHD_HYS — 20 — °C POR Power-on Reset Voltage Power-on Reset Voltage Hysteresis Thermal Shutdown Note 1: 2: 3: 4: 5: 6: Refer to Section 16.0, Power-Down Mode (Sleep). VDD is the voltage present at the VDD pin. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential between VIN and VDD. Ensured by design, not production tested. These parameters are characterized, but not production tested. The VDD LDO will limit the total source current to a maximum of 35 mA. Individually each pin can source a maximum of 15 mA.  2015-2020 Microchip Technology Inc. DS20005479D-page 29 MCP19116/7 4.3 Thermal Specifications Parameters Sym. Min. Typ. Max. Units TA -40 — +125 °C Operating Junction Temperature Range TJ -40 — +125 °C Maximum Junction Temperature TJ — — +150 °C TA -65 — +150 °C Thermal Resistance, 24L-QFN 4x4 JA — 42 — °C/W Thermal Resistance, 28L-QFN 5x5 JA — 35.3 — °C/W Temperature Ranges Specified Temperature Range Storage Temperature Range Thermal Package Resistances DS20005479D-page 30  2015-2020 Microchip Technology Inc. MCP19116/7 5.0 DIGITAL ELECTRICAL CHARACTERISTICS 5.1 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only) T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKOUT cs CS di SDI do SDO dt Data in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (high-impedance) L Low I2C only AA BUF T Time osc rd rw sc ss t0 wr OSC1 RD RD or WR SCK SS T0CKI WR P R V Z Period Rise Valid High-Impedance High Low High Low Hold SU Setup DATA Input Hold START Condition STO STOP Condition Output Access Bus Free TCC:ST (I2C specifications only) CC HD ST DAT STA  2015-2020 Microchip Technology Inc. DS20005479D-page 31 MCP19116/7 FIGURE 5-1: LOAD CONDITIONS Load Condition 1 Load Condition 2 VDD/2 RL CL Pin CL Pin AGND AGND RL = 464 CL = 50 pF for all GPIO pins 5.2 AC Characteristics: MCP19116 (Industrial, Extended) FIGURE 5-2: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC 1 2 TABLE 5-1: EXTERNAL CLOCK TIMING REQUIREMENTS Param. No. Sym. Characteristic 1 FOSC Oscillator Frequency 2 TOSC Oscillator Period (1) 3 TCY (1) Instruction Cycle Time (1, 2) Min. Typ.† Max. Units — 8 — MHz — 250 — ns — TCY  ns Conditions TCY = 4 * TOSC * These parameters are characterized but not tested. † Data in “Typ.” column is at VIN = 12V (VDD = 5V), 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. 2: Instruction cycle period (TCY) equals four times the input oscillator time base period. DS20005479D-page 32  2015-2020 Microchip Technology Inc. MCP19116/7 FIGURE 5-3: I/O TIMING Q1 Q4 Q2 Q3 OSC 22 23 19 18 I/O Pin (input) 17 I/O Pin (output) new value old value 20, 21 TABLE 5-2: I/O TIMING REQUIREMENTS Param. No. Sym. 17 TosH2ioV 18 Min. Typ.† Max. Units OSC1 (Q1 cycle) to Port out valid — 50 70* ns TosH2ioI OSC1(Q2 cycle) to Port input invalid (I/O in hold time) 50 — — ns 19 TioV2osH Port input valid to OSC1 (I/O in setup time) 20 — — ns 20 TioR Port output rise time — 32 40 ns Characteristic 21 TioF Port output fall time — 15 30 ns 22* Tinp INT pin high or low time 25 — — ns 23* TRABP TCY — — ns GPIO interrupt-on-change new input level time Conditions † Data in “Typ” column is at VIN = 12V (VDD = 5V), 25C unless otherwise stated. * These parameters are characterized but not tested.  2015-2020 Microchip Technology Inc. DS20005479D-page 33 MCP19116/7 FIGURE 5-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time Out 32 OSC Time Out Internal Reset Watchdog Timer Reset 34 31 34 I/O Pins FIGURE 5-5: BROWN-OUT RESET TIMING AND CHARACTERISTICS VDD VBOR BVHY VBOR + BVHY 35 Reset (due to BOR) (device not in Brown-out Reset) DS20005479D-page 34 (device in Brown-out Reset) 64 ms Time Out (if PWRTE)  2015-2020 Microchip Technology Inc. MCP19116/7 TABLE 5-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER REQUIREMENTS Param. No. Sym. 30 TMCL 31 Min. Typ.† Max. Units MCLR Pulse Width (low) 2 — — µs VDD = 5V –40°C to +85°C TWDT Watchdog Timer Time-Out Period (No Prescaler) 7 18 33 ms VDD = 5V –40°C to +85°C 32 TOST Oscillation Start-Up Timer Period — 1024TOSC — — TOSC = OSC1 period 33* TPWRT Power-up Timer Period (4 x TWDT) 28 72 132 ms VDD = 5V –40°C to +85°C 34 TIOZ I/O high impedance from MCLR Low or Watchdog Timer Reset — — 2.0 µs VBOR Brown-Out Reset voltage — 2.7 — V BVHY Brown-Out Hysteresis — 100 — mV TBCR Brown-Out Reset pulse width 100* — — µs 2TOSC — 7TOSC 35 48 Characteristic TCKEZ-TMR Delay from clock edge to timer increment Conditions VDD  VBOR (D005) * These parameters are characterized but not tested. † Data in “Typ.” column is at VIN = 12V (VDD = 5V, AVDD = 4V), 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 5-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMING T0CKI 41 40 42 48 TMR0  2015-2020 Microchip Technology Inc. DS20005479D-page 35 MCP19116/7 TABLE 5-4: TIMER0 EXTERNAL CLOCK REQUIREMENTS Param. Sym No. . 40* Tt0H 41* Tt0L 42* Tt0P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width Typ.† Min. Max. Units No Prescaler 0.5TCY + 20 — — ns With Prescaler 10 — — ns No Prescaler 0.5TCY + 20 — — ns 10 — — ns Greater of: 20 or — — ns With Prescaler T0CKI Period N = prescale value (2, 4, ..., 256) TCY + 40 ----------------------N * † Conditions These parameters are characterized but not tested. Data in “Typ.” column is at VIN = 12V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. FIGURE 5-7: PWM TIMINGS PWM (CLKPIN) 53 Note: TABLE 5-5: 54 Refer to Figure 5-1 for load conditions. PWM REQUIREMENTS Param. Sym. No. Characteristic Min. Typ.† Max. Units 53* TccR PWM (CLKPIN) output rise time — 10 25 ns 54* TccF PWM (CLKPIN) output fall time — 10 25 ns Conditions * These parameters are characterized but not tested. † Data in “Typ” column is at VIN = 12V (AVDD = 4V), 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS20005479D-page 36  2015-2020 Microchip Technology Inc. MCP19116/7 TABLE 5-6: MCP19116/7 A/D CONVERTER (ADC) CHARACTERISTICS (1) Electrical Specifications: Unless otherwise noted, operating temperature = -40°C  TA  +125°C Param. Sym. No. Characteristic Min. Typ.† Max. Units Conditions AD01 NR Resolution — — 10 bits bit AD02 EIL Integral Error (2) — — 1 LSb VREF_ADC = AVDD VREF_ADC = VDD AD03 EDL Differential Error (2) — — 1 LSb No missing codes to 10 bits (3) VREF_ADC = AVDD VREF_ADC = VDD AD04 EOFF Offset Error (2) — +3.0 +7 LSb VREF_ADC = AVDD VREF_ADC = VDD AD07 EGN — 2 6 LSb VREF_ADC = AVDD VREF_ADC = VDD AD07 VAIN Full-Scale Range Gain Error (2) ZAIN Recommended Impedance of Analog Voltage Source AD08 AGND — AVDD V AVDD selected as ADC reference AGND — VDD V VDD selected as ADC reference — — 10 k * These parameters are characterized but not tested. † Data in ‘Typ.’ column is at VIN = 12V (VDD = 5V, AVDD = 4V), 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note 1: When ADC is off, it will not consume any current other than leakage current. The power-down current specification includes any such leakage from the ADC module. To minimize Sleep current, the ADC reference must be set to the default AVDD. 2: Total Absolute Error includes integral, differential, offset and gain errors. 3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes. TABLE 5-7: MCP19116/7 A/D CONVERSION REQUIREMENTS Electrical Specifications: Unless otherwise noted, operating temperature = -40°C  TA  +125°C Param. Sym. No. Typ.† Max. Units 1.6 — 9.0 µs TOSC-based 1.6 4.0 6.0 µs ADCS = 11 (ADRC mode) Conversion Time (not including Acquisition Time) (1) — 11 — TAD AD132* TACQ Acquisition Time — 11.5 — µs AD133* TAMP Amplifier Settling Time — — 5 µs Q4 to A/D Clock Start — TOSC/2 — — AD130* TAD AD131 TCNV AD134 TGO Characteristic Min. A/D Clock Period A/D Internal RC Oscillator Period Conditions Set GO/DONE bit to new data in A/D Result registers † Data in ‘Typ.’ column is at VIN = 12V (VDD = 5V, AVDD = 4V), 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. * These parameters are characterized but not tested. Note 1: ADRESH and ADRESL registers may be read on the following TCY cycle.  2015-2020 Microchip Technology Inc. DS20005479D-page 37 MCP19116/7 FIGURE 5-8: A/D CONVERSION TIMING BSF ADCON0, GO 134 1/2 TCY 131 Q4 130 A/D CLK 9 A/D DATA 8 7 6 3 OLD_DATA ADRES 2 1 0 NEW_DATA ADIF DONE GO SAMPLE 132 SAMPLING STOPPED Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. DS20005479D-page 38  2015-2020 Microchip Technology Inc. MCP19116/7 6.0 CONFIGURING THE MCP19116/7 The MCP19116/7 devices are analog controllers with a digital peripheral. This means that device configuration is handled through register settings instead of adding external components. There are several internal configurable comparator modules used to interface analog circuits to digital processing that are very similar to a standard comparator module found in many PIC processors today (i.e., PIC16F1824/1828). The following sections detail how to set the analog control registers for all the configurable parameters. 6.1 Input Undervoltage and Overvoltage Lockout (UVLO and OVLO) VINCON is the comparator control register for both the VINUVLO and VINOVLO registers. It contains the enable bits, the polarity edge detection bits and the status output bits for both protection circuits. The interrupt flags and in the PIR2 register are independent of the enable and bits in the VINCON register. The Undervoltage Lockout Status Output bit in the VINCON register indicates if an UVLO event has occurred. The Overvoltage Lockout Status Output bit in the VINCON register indicates if an OVLO event has occurred. REGISTER 6-1: The VINUVLO register contains the digital value that sets the input undervoltage lockout. UVLO has a range of 4V to 20V. For VIN values below this range and above processor come-alive (VDD = 2V), the UVLO comparator and the UVLOOUT Status bit will indicate an undervoltage condition. If using UVLO to determine power-up VIN, it is recommended to poll the UVLOOUT bit for status. When the input voltage on the VIN pin to the MCP19116/7 is below this programmed level and the bit in the VINCON register is set, both PDRV and SDRV gate drivers are disabled. This bit is automatically cleared when the MCP19116/7 VIN voltage rises above this programmed level. The VINOVLO register contains the digital value that sets the input overvoltage lockout. OVLO has a range of 8.8V to 44V. When the input voltage on the VIN pin to the MCP19116/7 is above this programmed level and the bit in the VINCON register is set, both PDRV and SDRV gate drivers are disabled. This bit is automatically cleared when the MCP19116/7 VIN voltage drops below this programmed level. Note: The UVLOIF and OVLOIF interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit (GIE) in the INTCON register. VINCON: UVLO AND OVLO COMPARATOR CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 UVLOEN UVLOOUT UVLOINTP UVLOINTN OVLOEN OVLOOUT OVLOINTP OVLOINTN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 UVLOEN: UVLO Comparator Module Logic Enable bit 1 = UVLO Comparator Module Logic enabled 0 = UVLO Comparator Module Logic disabled bit 6 UVLOOUT: Undervoltage Lockout Status Output 1 = UVLO event has occurred 0 = No UVLO event has occurred bit 5 UVLOINTP: UVLO Comparator Interrupt on Positive Going Edge Enable bit 1 = The UVLOIF interrupt flag will be set upon a positive going edge of the UVLO 0 = No UVLOIF interrupt flag will be set upon a positive going edge of the UVLO bit 4 UVLOINTN: UVLO Comparator Interrupt on Negative Going Edge Enable bit 1 = The UVLOIF interrupt flag will be set upon a negative going edge of the UVLO 0 = No UVLOIF interrupt flag will be set upon a negative going edge of the UVLO  2015-2020 Microchip Technology Inc. DS20005479D-page 39 MCP19116/7 REGISTER 6-1: VINCON: UVLO AND OVLO COMPARATOR CONTROL REGISTER (CONTINUED) bit 3 OVLOEN: OVLO Comparator Module Logic enable bit 1 = OVLO Comparator Module Logic enabled 0 = OVLO Comparator Module Logic disabled bit 2 OVLOOUT: Overvoltage Lockout Status Output bit 1 = OVLO event has occurred 0 = No OVLO event has occurred bit 1 OVLOINTP: OVLO Comparator Interrupt on Positive Going Edge Enable bit 1 = The OVLOIF interrupt flag will be set upon a positive going edge of the OVLO 0 = No OVLOIF interrupt flag will be set upon a positive going edge of the OVLO bit 0 OVLOINTN: OVLO Comparator Interrupt on Negative Going Edge Enable bit 1 = The OVLOIF interrupt flag will be set upon a negative going edge of the OVLO 0 = No OVLOIF interrupt flag will be set upon a negative going edge of the OVLO REGISTER 6-2: VINUVLO: INPUT UNDERVOLTAGE LOCKOUT REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — UVLO5 UVLO4 UVLO3 UVLO2 UVLO1 UVLO0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 UVLO: Undervoltage Lockout Configuration bits UVLO(V) = 3.5472 * (1.0285N) where N = the decimal value written to the VINUVLO Register from 0 to 63 REGISTER 6-3: VINOVLO: INPUT OVERVOLTAGE LOCKOUT REGISTER U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — OVLO5 OVLO4 OVLO3 OVLO2 OVLO1 OVLO0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 OVLO: Overvoltage Lockout Configuration bits OVLO(V) = 7.4847 * (1.0286N) where N = the decimal value written to the VINOVLO Register from 0 to 63 DS20005479D-page 40  2015-2020 Microchip Technology Inc. MCP19116/7 6.2 Output Overvoltage Protection The OVCON register contains the interrupt flag polarity and OV enable bits along with the Output Status bit just as VINCON does for the input voltage UVLO and OVLO. When bit in the OVCON register is set and an overvoltage occurs, the control logic automatically sets the secondary gate drive output (SDRV) high and the primary gate drive output (PDRV) low. The MCP19116/7 devices feature output overvoltage protection. This feature also utilizes a comparator module similar to the standard PIC comparator module. This is used to prevent the power system from being damaged when the load is disconnected. The OVREFCON register contains the digital value that sets the analog DAC voltage at the inverting input of the comparator. By comparing the divided down power train output voltage connected to the noninverting input (VS) of the comparator with the OVREF reference voltage, the user can determine when an overvoltage event has occurred and can automatically take action. REGISTER 6-4: Note: The OVIF Interrupt Flag bit is set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit (GIE) in the INTCON register. OVCON: OUTPUT OVERVOLTAGE COMPARATOR CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 — — — — OVEN OVOUT OVINTP OVINTN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 OVEN: OV Comparator Output Enable bit 1 = OV Comparator output is enabled 0 = OV Comparator output is not enabled bit 2 OVOUT: Output Overvoltage Status Output bit 1 = Output Overvoltage has occurred 0 = No Output Overvoltage has occurred bit 1 OVINTP: OV Comparator Interrupt on Positive Going Edge Enable bit 1 = The OVIF interrupt flag will be set upon a positive going edge of the OV 0 = No OVIF interrupt flag will be set upon a positive going edge of the OV bit 0 OVINTN: OV Comparator Interrupt on Negative Going Edge Enable bit 1 = The OVIF interrupt flag will be set upon a negative going edge of the OV 0 = No OVIF interrupt flag will be set upon a negative going edge of the OV  2015-2020 Microchip Technology Inc. DS20005479D-page 41 MCP19116/7 REGISTER 6-5: OVREFCON: OUTPUT OVERVOLTAGE DETECT LEVEL REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x OOV7 OOV6 OOV5 OOV4 OOV3 OOV2 OOV1 OOV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 OOV: Output Overvoltage Detect Level Configuration bits VOV_REF(V) = 2 * VBG * N/255 where N is the decimal value written to the OVREFCON Register from 0 to 255. DS20005479D-page 42  2015-2020 Microchip Technology Inc. MCP19116/7 6.3 Desaturation Detection for Quasi-Resonant Operation The MCP19116/7 have been designed with a built-in desaturation detection comparator module custom made for quasi-resonant topologies. This is especially useful for LED-type applications. Through the use of the MCP19116/7, both synchronous and asynchronous quasi-resonant topologies can be implemented. The DESAT comparator module has the same features as the UVLO/OVLO and OV comparator modules, except that it includes some additional programmable parameters. REGISTER 6-6: The DESATCON register holds the setup control bits for this module. Common control bits are the polarity edge trigger for the interrupt flag , comparator output polarity control , output enable and output status bits. As with the other comparator modules, the CDSIF is independent of the CDSOE enable bit. On the front end connected to the DESAT comparator non-inverting input, there is a two-channel MUX that connects either to the DESATP pin or to the fixed internally generated band gap voltage. Additionally, the input offset voltage of the DESAT comparator is factory-trimmed to within ±1 mV typically. These factory-trimmed values are stored in the CALWD2 register at address 2081h. Firmware must read these values into the DSTCAL register (196h). If more offset is desired, the user can adjust the values written to the DSTCAL per their implementation. DESATCON: DESATURATION COMPARATOR CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CDSMUX CDSWDE Reserved CDSPOL CDSOE CDSOUT CDSINTP CDSINTN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CDSMUX: DESAT Comparator Module Multiplexer Channel Selection bit 1 = BG Selected 0 = DESATP Selected (Default) bit 6 CDSWDE: DESAT Comparator Watch Dog Enable bit 1 = Watch Dog signal enables PWM Reset 0 = Watch Dog signal does not allow PWM reset bit 5 Reserved bit 4 CDSPOL: DESAT Comparator Polarity Select bit 1 = DESAT Comparator output is inverted 0 = DESAT Comparator output is not inverted bit 3 CDSOE: DESAT Comparator output enable bit 1 = DESAT Comparator output PWM is enabled 0 = DESAT Comparator output PWM is not enabled bit 2 CDSOUT: DESAT Comparator Output Status bit If CDSPOL = 1 (inverted polarity) 1 = CDSVP < CDSVN (DESAT detected) 0 = CDSVP > CDSVN (DESAT not detected) If CDSPOL = 0 (non-inverted polarity) 1 = CDSVP > CDSVN (DESAT not detected) 0 = CDSVP < CDSVN (DESAT detected) bit 1 CDSINTP: CDSIF Comparator Interrupt on Positive Going Edge Enable bit 1 = The CDSIF interrupt flag will be set upon a positive going edge 0 = No CDSIF interrupt flag will be set upon a positive going edge bit 0 CDSINTN: CDSIF Comparator Interrupt on Negative Going Edge Enable bit 1 = The CDSIF interrupt flag will be set upon a negative going edge 0 = No CDSIF interrupt flag will be set upon a negative going edge  2015-2020 Microchip Technology Inc. DS20005479D-page 43 MCP19116/7 6.4 Primary Input Current Offset Adjust Primary input current offset adjust provides the ability to add offset to the primary input current signal, thus setting a peak primary current limit. This offset adjust is controlled by means of the four bits in the ICOACON register. REGISTER 6-7: ICOACON: INPUT CURRENT OFFSET ADJUST CONTROL REGISTER U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x — — — — ICOAC3 ICOAC2 ICOAC1 ICOAC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 ICOAC: Input Current Offset Adjustment Configuration bits 0000 = 0 mV 0001 = 50 mV 0010 = 100 mV 0011 = 150 mV 0100 = 200 mV 0101 = 250 mV 0110 = 300 mV 0111 = 350 mV 1000 = 400 mV 1001 = 450 mV 1010 = 500 mV 1011 = 550 mV 1100 = 600 mV 1101 = 650 mV 1110 = 700 mV 1111 = 750 mV DS20005479D-page 44  2015-2020 Microchip Technology Inc. MCP19116/7 6.5 Leading Edge Blanking The adjustable Leading Edge Blanking (LEB) is used to blank primary current spikes resulting from primary switch turn-on. Implementing adjustable LEB allows the system to ignore turn-on noise to best suit the application without primary current sense distortion from RC filtering. There are four settings available for LEB, including zero. These settings are controlled via two bits in the ICLEBCON register. REGISTER 6-8: ICLEBCON: INPUT CURRENT LEADING EDGE BLANKING CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x — — — — — — ICLEBC1 ICLEBC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 ICLEBC: Input current Leading Edge Blanking Configuration bits 00 = 0 ns 01 = 50 ns 10 = 100 ns 11 = 200 ns  2015-2020 Microchip Technology Inc. DS20005479D-page 45 MCP19116/7 6.6 Slope Compensation A negative voltage slope is added to the output of the error amplifier. This is done to prevent subharmonic instability when: 1. 2. the operating duty cycle is greater than 50% wide changes in duty cycle occur The amount of negative slope added to the error amplifier output is controlled by the slope compensation slew rate control bits. The slope compensation is enabled by clearing the SLPBY bit in the SLPCRCON register. REGISTER 6-9: SLPCRCON: SLOPE COMPENSATION RAMP CONTROL REGISTER U-0 R/W-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SLPBY SLPS5 SLPS4 SLPS3 SLPS2 SLPS1 SLPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6 SLPBY: Slope Compensation Bypass Control bit 1 = Slope compensation is bypassed 0 = Slope compensation is not bypassed (Default) bit 5-0 SLPS: Slope Compensation Slew Rate Control bits SLPS (mV/µs) = 4.5 * 1.08N where N is the decimal value written to the SLPCRCON Register from 0 to 63. DS20005479D-page 46  2015-2020 Microchip Technology Inc. MCP19116/7 6.7 MOSFET Driver Programmable Dead Time FIGURE 6-1: The turn-on dead time of both PDRV and SDRV low-side drive signals can be configured independently to allow different MOSFETs and circuit board layouts to be used to construct an optimized system (refer to Figure 6-1). PDRV PDT SDT Clearing the PDRVBY and SDRVBY bits in the PE1 register enables the PDRV and SDRV low-side dead timers, respectively. The amount of dead time added is controlled in the DEADCON register. REGISTER 6-10: MOSFET DRIVER DEAD TIME SDRV DEADCON: DRIVER DEAD TIME CONTROL REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x PDRVDT3 PDRVDT2 PDRVDT1 PDRVDT0 SDRVDT3 SDRVDT2 SDRVDT1 SDRVDT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 PDRVDT: PDRV Dead Time Configuration bits (tTD_1) 0000 = 16 ns delay 0001 = 32 ns delay 0010 = 48 ns delay 0011 = 64 ns delay 0100 = 80 ns delay 0101 = 96 ns delay 0110 = 112 ns delay 0111 = 128 ns delay 1000 = 144 ns delay 1001 = 160 ns delay 1010 = 176 ns delay 1011 = 192 ns delay 1100 = 208 ns delay 1101 = 224 ns delay 1110 = 240 ns delay 1111 = 256 ns delay  2015-2020 Microchip Technology Inc. DS20005479D-page 47 MCP19116/7 REGISTER 6-10: bit 3-0 6.8 DEADCON: DRIVER DEAD TIME CONTROL REGISTER (CONTINUED) SDRVDT: SDRV Dead Time Configuration bits (tTD_2) 0000 = 16 ns delay 0001 = 32 ns delay 0010 = 48 ns delay 0011 = 64 ns delay 0100 = 80 ns delay 0101 = 96 ns delay 0110 = 112 ns delay 0111 = 128 ns delay 1000 = 144 ns delay 1001 = 160 ns delay 1010 = 176 ns delay 1011 = 192 ns delay 1100 = 208 ns delay 1101 = 224 ns delay 1110 = 240 ns delay 1111 = 256 ns delay Output Regulation Reference Voltage Configuration The VREFCON register controls the error amplifier reference voltage. This reference is used to set the current or voltage regulation set point. VREFCON holds the digital value used by an 8-bit linear DAC, setting the analog equivalent that gets summed with the pedestal voltage (VZC) at the noninverting node of the error amplifier. VZC is equal to the band gap voltage (1.23V). The output of the current sense amplifier A2 is also raised on the pedestal voltage, effectively canceling its effect on the input. The pedestal is implemented throughout the analog control loop to improve accuracy at low levels. The VREF DAC can be adjusted in 255 steps of 4.8 mV/step. REGISTER 6-11: VREFCON: CURRENT/VOLTAGE REGULATION SET POINT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VREF7 VREF6 VREF5 VREF4 VREF3 VREF2 VREF1 VREF0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 VREF: Voltage-Controlling Current Regulation Set Point bits VREF(V) = VBG * N/255 where N is the decimal value written to the VREFCON Register from 0 to 255 DS20005479D-page 48  2015-2020 Microchip Technology Inc. MCP19116/7 6.9 VREF2 Voltage Reference The VREF2CON register controls a second reference DAC that can be used externally. For example, it can be sent off-chip and used to set the current regulation set point for a MCP1631 Pulse-Width Modulator. The MCP19116/7 must be configured in Master Mode with bits MSC = 01 in the MODECON register to REGISTER 6-12: connect VREF2 to GPB1. In Stand-Alone mode, VREF2 is not accessible. VREFCON2 holds the digital value used to set the VREF2 DAC. Since this reference is intended to go off-chip, there is no pedestal offset associated with it and it is referenced to GND. It is an 8-bit linear DAC and has a range from 0V to 1.23V (BG) equating to 255 steps at 4.8 mV/step. VREF2CON: VREF2 VOLTAGE SET POINT REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VREF27 VREF26 VREF25 VREF24 VREF23 VREF22 VREF21 VREF20 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 6.10 VREF2: Voltage Controlling Current Regulation Set Point bits VREF2(V) = VBG * N/255 where N is the decimal value written to the VREF2CON Register from 0 to 255 Analog Peripheral Control The MCP19116/7 devices have several analog peripherals, such as the PDRV and SDRV peripherals, and a weak pull-up on the ISP input. PDRV and SDRV peripherals are enabled using single bits, PDRVEN and SDRVEN. The weak pull-up on the ISP input is enabled using the ISPUEN bit. These peripherals can be configured to allow customizable operation. Refer to Register 6-13 for more information. 6.10.1 MOSFET GATE DRIVER ENABLES The MCP19116/7 can enable and/or disable the MOSFET gate driver outputs for the primary drive (PDRV) and the secondary drive (SDRV) independently. Setting the bit in the PE1 register enables the primary drive. Setting the bit in the PE1 register enables the secondary drive. Refer to Register 6-13 for details. 6.10.2 MOSFET DRIVER DEAD TIME The MOSFET drive dead time can be adjusted as described in Section 6.7 “MOSFET Driver Programmable Dead Time”. The dead time can be set independently for each driver from 16 ns to 256 ns in increments of 16 ns using the DEADCON register. Dead time can also be disabled for each driver independently by setting the bypass bits and in the PE1 register.  2015-2020 Microchip Technology Inc. 6.10.3 SECONDARY CURRENT POSITIVE SENSE PULL-UP A high-impedance pull-up on the ISP pin can be configured by setting the bit in the PE1 register. When set, the ISP pin is internally pulled-up to VDD. Refer to Register 6-13 for details. 6.10.4 PWM STEERING The MCP19116/7 devices have additional control circuitry to allow open-loop repositioning of the output. The PWMSTR_PEN bit enables a primary-only PWM signal of fixed frequency and duty cycle to reposition the output voltage up. The PWMSTR_SEN bit enables a secondary-only PWM signal of fixed frequency and duty cycle to reposition the output voltage down. When repositioning output voltage down, the output overvoltage protection must be active along with PWMSTR_SEN for the PWM to pulse the SDRV. Frequency and duty cycle are controlled through TMR2 registers PR2 and TMR1L. PWMSTPR_PEN and PWMSTR_SEN should never be active at the same time, therefore PWMSTPR_PEN is the dominant bit. For quasi-resonant operation during open-loop repositioning, the DESAT comparator output should be disabled with the bit in the DEADCON register. DS20005479D-page 49 MCP19116/7 REGISTER 6-13: PE1: ANALOG PERIPHERAL ENABLE1 CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 PDRVEN SDRVEN PDRVBY SDRVBY — ISPUEN R/W-0 R/W-0 PWMSTR_PEN PWMSTR_SEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PDRVEN: PDRV Gate Drive Enable bit 1 = PDRV gate drive is enabled 0 = PDRV gate drive is disabled bit 6 SDRVEN: SDRV Gate Drive Enable bit 1 = SDRV gate drive is enabled 0 = SDRV gate drive is disabled bit 5 PDRVBY: PDRV Dead Time Bypass bit 1 = PDRV dead time is bypassed 0 = PDRV dead time is not bypassed bit 4 SDRVBY: SDRV Dead Time Bypass bit 1 = SDRV dead time is bypassed 0 = SDRV dead time is not bypassed. bit 3 Unimplemented: Read as ‘0’ bit 2 ISPUEN: ISP Weak Pull-Up Enable bit 1 = ISP weak pull-up is enabled 0 = ISP weak pull-up is disabled bit 1 PWMSTR_PEN: PDRV PWM Steering bit 1 = Enables open-loop PWM control to the PDRV 0 = Disables open-loop PWM control to the PDRV bit 0 PWMSTR_SEN: SDRV PWM Steering bit 1 = Enables open-loop PWM control to the SDRV 0 = Disables open-loop PWM control to the SDRV 6.11 Analog and Digital Test Signal Enable and Control Various analog and digital test signals can be enabled or disabled, as shown in Register 6-14. These signals can be configured to GPA0. Setting the bit enables the digital test signals to be connected to GPA0. selects the digital channels. Setting enables the analog test signals to be connected to GPA0. If and both get set, the DIGOEN bit takes priority. When ANAOEN is set and DIGOEN is not set, the analog test signals are connected to the internal ADC. The analog test channel selections are controlled through the ADCON0 register. DS20005479D-page 50 6.11.1 MOSFET DRIVER UNDERVOLTAGE LOCKOUT SELECTION The MOSFET gate drivers have internal undervoltage protection that is controlled by the bit in Register 6-14. Since the gate drive supply is provided externally through the VDR pin, the drivers are capable of driving logic level FETs or higher 10V (13.5V maximum) FETs. defaults to clear, therefore selecting a gate drive UVLO of 2.7V. Setting selects the higher 5.4V gate drive UVLO. Refer to Section 4.2 “Electrical Characteristics” for additional electrical specifications.  2015-2020 Microchip Technology Inc. MCP19116/7 6.11.2 ERROR AMPLIFIER DISABLE The error amplifier can be disabled such that its output is parked to a known state. The bit defaults to zero and the error amp is enabled during normal operation. In case the user wants to disable the error amplifier, setting the EADIS bit parks the error amplifier output to just below the low clamp voltage. Under normal operation, the error amplifier output runs between 2 * BG (upper clamp value) and 1 * BG – 150 mV (lower clamp value). The analog feedback circuitry utilizes an offset pedestal (1 * BG) to improve accuracy at low levels. REGISTER 6-14: ABECON: ANALOG BLOCK ENABLE CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 DIGOEN DSEL2 DSEL1 DSEL0 DRUVSEL — EADIS ANAOEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 DIGOEN: DIG Test MUX to GPA0 connection control 1 = DIG Test MUX output is connected to external pin GPA0 0 = DIG Test MUX output is not connected to external pin GPA0 bit 6-4 DSEL Digital Test Signals 000 = QRS (output of DESAT comparator) 001 = PWM_L (PWM output after monostable) 010 = PWM (oscillator output from the microcontroller) 011 = TMR2EQ (when TMR2 equals PR2) 100 = OV (overvoltage comparator output) 101 = SWFRQ (switching frequency output) 110 = SDRV_ON_ONESHOT (200 ns one-shot signal to reset WDM logic) 111 = Unimplemented bit 3 DRUVSEL: Selects gate drive undervoltage lockout level 1 = Gate Drive UVLO set to 5.4V 0 = Gate Drive UVLO set to 2.7V bit 2 Unimplemented: Read as ‘0’ bit 1 EADIS: Error Amplifier Disable bit 1 = Disables the error amplifier (Output parked low, clamped to 1 * BG) 0 = Enables the error amplifier (Normal operation) bit 0 ANAOEN: Analog MUX Output Control bit 1 = Analog MUX output is connected to external pin GPA0 0 = Analog MUX output is not connected to external pin GPA0  2015-2020 Microchip Technology Inc. DS20005479D-page 51 MCP19116/7 6.12 Mode and RFB MUX Control The RFB MUX selects the output of A2 current sense amplifier to be connected to the internal 5 k feedback resistor or to the ISOUT pin. The MODECON register controls the Master/Slave configuration and the internal resistor feedback MUX for the current sense amplifier while in quasi-resonant mode. In Master mode, it allows the VREF2 signal of the Master MCP19116/7 device to be buffered and connected to a GPIO pin. This output signal can be connected to a Slave PWM driver (MCP1631) at the VREF input to regulate current via the Slave PWM Controller. In Master mode, the CLKOUT sync signal is routed to GPA1. In Semi-Master Mode, users have the option to implement VREF2 and CLKOUT independently. In Stand-Alone mode, the VREF2 unity gain buffer and CLKOUT signals are not connected to GPIO Pins. REGISTER 6-15: MODECON: MASTER/SLAVE AND RFB MUX CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 MSC1 MSC0 RFB — MSC2 — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 MSC: Master/Slave Configuration bits 00 = Device set as stand-alone unit (VREF2 disabled, Switching frequency internally generated) 01 = Device set as MASTER (VREF2 to GPB1, CLKOUT sync to GPA1) 10 = Device set as SLAVE MODE (CLKIN switching frequency sync signal to GPA1) 11 = Device set to SEMI-MASTER MODE bit 5 RFB: Current Sense Amplifier (A2) Output Resistor Feedback MUX Configuration bit 0 = RFB_INT 5 k 1 = ISOUT bit 4 Unimplemented: Read as ‘0’ bit 3 MSC: Semi-Master mode options 0 = GPB1 is VREF2 Output, GPA1 is general purpose I/O 1 = GPB1 is general purpose output, GPA1 is CLKOUT bit 2-0 Unimplemented: Read as ‘0’ DS20005479D-page 52  2015-2020 Microchip Technology Inc. MCP19116/7 7.0 TYPICAL PERFORMANCE CURVES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. Note: Unless otherwise indicated, VIN = 12V, FSW = 150 kHz, TA = +25°C. 5.17 5.16 6.6 VIN = 32V 5.15 VIN = 25V 5.14 6.5 -40°C VDD (V) Quiescent Current (mA) 6.7 6.4 +25°C 5.13 6.3 5.12 VIN = 12V 5.11 6.2 6.1 +125°C 5.10 VIN = 6V 5.09 6.0 -40 -25 -10 5 FIGURE 7-1: 20 35 50 65 80 Temperature (°C) 0 95 110 125 IQ vs. Temperature. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Current (mA) FIGURE 7-4: Load Regulation. 0.6 140 VIN = 32V 100 0.4 80 VIN = 20V 60 VIN = 12V 40 0.3 +25°C 0.2 -40°C 0.1 VIN = 6V 20 0.0 0 -40 -25 -10 FIGURE 7-2: Mode. 5 0 20 35 50 65 80 95 110 125 Temperature (°C) IQ vs. Temperature in Sleep 0.45 5.12 0.40 5.10 5.09 VDD Dropout (V) -40°C IDD = 1 mA 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Current (mA) FIGURE 7-5: VDD Dropout Voltage vs. Output Current (mA). 5.13 5.11 VDD (V) +125°C 0.5 VDD Dropout (V) Sleep Current (uA) 120 IDD = 20 mA 0.35 0.30 0.25 0.20 +25°C 5.08 0.15 +125°C 5.07 0.10 6 8 10 12 14 16 18 20 22 24 26 28 30 32 VIN (V) FIGURE 7-3: Line Regulation.  2015-2020 Microchip Technology Inc. -40 -25 -10 FIGURE 7-6: Temperature. 5 20 35 50 65 80 95 110 125 Temperature (°C) VDD Dropout Voltage vs. DS20005479D-page 53 MCP19116/7 Note: Unless otherwise indicated, VIN = 12V, FSW = 150 kHz, TA = +25°C. 9.5 -40°C 8.5 200.0 +125°C 8.0 +25°C 150.0 VDR = 5V 9.0 RDS(ON) (Ÿ) PDRV/SDRV Dead Time (ns) 250.0 7.5 7.0 RSDRV-SOURCE 6.5 100.0 6.0 RPDRV-SOURCE 5.5 50.0 5.0 4.5 0.0 0 2 4 6 8 Code (d) 10 12 14 16 FIGURE 7-7: Output Driver Dead Time vs. Code and Temperature. 7.0 4.5 4.0 7.0 RSDRV-SOURCE RPDRV-SOURCE 20 35 50 65 80 Temperature (°C) 95 110 125 VDR = 10V 5.0 RDS(ON) (Ÿ) RSDRV-SINK RPDRV-SINK 4.0 RSDRV-SINK -40 -25 -10 5 20 35 50 65 80 Temperature (°C) 95 110 125 FIGURE 7-11: Sinking Output Driver RDS(ON) vs. Temperature. 8.08 Oscillator Frequency (MHz) 5 5.5 3.0 RPDRV-SINK 5.5 4.0 -40 -25 -10 6.0 3.5 6.0 4.5 FIGURE 7-8: Sourcing Output Driver RDS(ON) vs. Temperature. 4.5 6.5 5.0 3.5 3.0 95 110 125 VDR = 5V 7.5 RDS(ON) (Ÿ) RDS(ON) (Ÿ) 5.0 20 35 50 65 80 Temperature (°C) 8.0 6.0 5.5 5 FIGURE 7-10: Sourcing Output Driver RDS(ON) vs. Temperature. VDR = 10V 6.5 -40 -25 -10 8.06 8.04 8.02 8.00 7.98 7.96 7.94 -40 -25 -10 5 20 35 50 65 80 Temperature (°C) 95 110 125 FIGURE 7-9: Sinking Output Driver RDS(ON) vs. Temperature. DS20005479D-page 54 -40 -25 -10 FIGURE 7-12: Temperature. 5 20 35 50 65 80 95 110 125 Temperature (°C) Oscillator Frequency vs.  2015-2020 Microchip Technology Inc. MCP19116/7 Note: Unless otherwise indicated, VIN = 12V, FSW = 150 kHz, TA = +25°C. 4.95 1.01 Maximum 1.00 GPIO VOUT (V) 1.02 4.90 -40°C 4.85 4.80 +25°C 4.75 Typical 0.99 +125°C 4.70 Minimum 0.98 -40 -25 -10 5 FIGURE 7-13: vs. Temperature. 4.65 0 20 35 50 65 80 95 110 125 Temperature (°C) Normalized Output Demand 1.03 Normalized Output Demand 5.00 Output Demand = 0.984V 1 2 3 Load Current (mA) 4 5 FIGURE 7-16: Average GPIO Output Voltage vs. Current. 3.70 Output Demand = 0.492V -40°C VIN = 12V 3.65 1.02 3.60 Maximum 1.01 1.00 Typical 0.99 SLEEP VDD (V) Normalized Output Demand 1.03 +25°C 3.55 3.50 +125°C 3.45 3.40 3.35 Minimum 0.98 -40 -25 -10 5 FIGURE 7-14: vs. Temperature. 20 35 50 65 80 95 110 125 Temperature (°C) Normalized Output Demand 3.30 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 VIN (V) 2 FIGURE 7-17: Average SLEEP VDD Output Voltage vs. Current. 1.50 ǻ%VDD-ǻ%AVDD 1.00 Maximum 0.50 0.00 Typical -0.50 -1.00 Minimum -40 -25 -10 FIGURE 7-15: Drift Tracking. 5 20 35 50 65 80 95 110 125 Temperature (°C) VDD vs. AVDD Temperature  2015-2020 Microchip Technology Inc. DS20005479D-page 55 MCP19116/7 NOTES: DS20005479D-page 56  2015-2020 Microchip Technology Inc. MCP19116/7 8.0 SYSTEM BENCH TESTING To allow for easier system design and bench testing, the MCP19116/7 devices feature a multiplexer used to output various internal analog signals. These signals can be measured on the GPA0 pin through a unity gain buffer. The configuration control of the GPA0 pin is found in the ABECON register (Register 6-14). Control of the signals present at the output of the unity gain analog buffer is found in the ADCON0 register (Register 8-1). . REGISTER 8-1: ADCON0: ANALOG-TO-DIGITAL CONTROL REGISTER U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS: Analog Channel Select bits 00000 = VIN/n analog voltage measurement (VIN/15.5) 00001 = VREF + VZC (DAC reference voltage + VZC pedestal setting current regulation level) 00010 = OV_REF (reference for overvoltage comparator) 00011 = VBGR (band gap reference) 00100 = VS (voltage proportional to VOUT) 00101 = EA_SC (error amplifier after slope compensation output) 00110 = A2 (secondary current sense amplifier output at RFB_INT connection) 00111 = Pedestal (Pedestal Voltage) 01000 = Reserved 01001 = Reserved 01010 = IP_ADJ (IP after Pedestal and Offset Adjust (at PWM Comparator)) 01011 = IP_OFF_REF (IP Offset Reference) 01100 = VDR/n (VDR/n analog driver voltage measurement = 0.23V/V * VDR) 01101 = TEMP_SNS (analog voltage representing internal temperature) 01110 = DLL_VCON (Delay Locked Loop Voltage Reference - control voltage for dead time) 01111 = SLPCMP_REF (slope compensation reference) 10000 = Unimplemented 10001 = Unimplemented 10010 = Unimplemented 10011 = Unimplemented 10100 = Unimplemented 10101 = Unimplemented 10110 = Unimplemented 10111 = Unimplemented 11000 = GPA0/AN0 11001 = GPA1/AN1 11010 = GPA2/AN2 11011 = GPA3/AN3 11100 = GPB1/AN4 11101 = GPB4/AN5 (MCP19117 only) 11110 = GPB5/AN6 (MCP19117 only) 11111 = GPB6/AN7 (MCP19117 only)  2015-2020 Microchip Technology Inc. DS20005479D-page 57 MCP19116/7 REGISTER 8-1: ADCON0: ANALOG-TO-DIGITAL CONTROL REGISTER (CONTINUED) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion has completed. 0 = A/D conversion completed/not in progress bit 0 ADON: A/D Conversion Enable bit 1 = A/D converter module is operating 0 = A/D converter is shut off and consumes no operating current DS20005479D-page 58  2015-2020 Microchip Technology Inc. MCP19116/7 9.0 DEVICE CALIBRATION Read-only memory locations 2080h through 208Fh contain factory calibration data. Refer to Section 18.0 “Flash Program Memory Control” for information on how to read from these memory locations. 9.1 Calibration Word 1 Calibration Word 1 is at memory location 2080h. The DCSRFB bits set the offset calibration for the current sense differential amplifier (A2) when configured using the internal feedback resistor. A calibration range of ±30 mV is provided with 20h and 00h being midscale (no offset). The MSB is polarity only. Firmware must read these values and copy them into the DCSCAL Special Function Register located in Bank 3 at 199h. REGISTER 9-1: CALWD1: CALIBRATION WORD 1 REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — bit 13 bit 8 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — DCSRFB6 DCSRFB5 DCSRFB4 DCSRFB3 DCSRFB2 DCSRFB1 DCSRFB0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unused bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 13-7 Unimplemented: Read as ‘0’ bit 6-0 DCSRFB: Input Differential Current Sense Calibration bits when configured using internal feedback resistor  2015-2020 Microchip Technology Inc. DS20005479D-page 59 MCP19116/7 9.2 Calibration Word 2 Calibration Word 2 is at memory location 2081h. It contains the calibration bits for the desaturation comparator current measurement input offset voltage. Firmware must read these values and write them into the DSTCAL register to implement the factory offset calibration. The factory offset calibration will minimize offset voltage. The desaturation comparator is one of the few examples where the user may want to implement their own offset voltage values. Writing user-defined values to the DSTCAL register provides this flexibility. Firmware must read these values and copy into the DSTCAL Special Function Register located in Bank 3 at 196h. REGISTER 9-2: This register also contains the trim bits needed to trim the internal 5 k feedback resistor to within 2% using the bits. Firmware must read these values and copy them into the RFBTCAL Special Function Register located in Bank 3 at 197h. CALWD2: CALIBRATION WORD 2 REGISTER U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — DST4 DST3 DST2 DST1 DST0 bit 13 bit 8 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — RFBT5 RFBT4 RFBT3 RFBT2 RFBT1 RFBT0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unused bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 13 Unimplemented: Read as ‘0’ bit 12-8 DST: Desaturation Comparator Current Measure Offset calibration bits 11111 = Maximum negative offset calibration (-30 mV) • • • 10000 = Mid scale (0 mV) 00000 = Mid scale (0 mV) • • • 01111 = Maximum positive offset calibration (+30 mV) bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RFBT: Internal Feedback Resistor Trim bits DS20005479D-page 60  2015-2020 Microchip Technology Inc. MCP19116/7 9.3 Calibration Word 3 The BGR bits at memory location 2082h calibrate the band gap reference. Firmware must read these values and copy them into the BGRCAL Special Function Register located in Bank 3 at 19Bh. REGISTER 9-3: CALWD3: CALIBRATION WORD 3 REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — bit 13 bit 8 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — BGR4 BGR3 BGR2 BGR1 BGR0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unused bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13-5 Unused: Read as ‘0’ bit 4-0 BGR: Band Gap Reference Calibration bits 9.4 x = Bit is unknown Calibration Word 4 The TTA bits at memory location 2083h contain the calibration bits for the factory-set overtemperature threshold. Firmware must read these values and copy them into the TTACAL Special Function Register located in Bank 3 at 19Ah. REGISTER 9-4: CALWD4: CALIBRATION WORD 4 REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — bit 13 bit 8 U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — TTA3 TTA2 TTA1 TTA0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unused bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13-4 Unimplemented: Read as ‘0’ bit 3-0 TTA: Over-Temperature Threshold Calibration bits  2015-2020 Microchip Technology Inc. x = Bit is unknown DS20005479D-page 61 MCP19116/7 9.5 Calibration Word 5 The TANA bits at memory location 2084h contain the ADC reading from the internal temperature sensor when the silicon temperature is at 30°C. This 10-bit reading can be used to calibrate the ADC reading at any temperature. The temperature coefficient of the internal temperature sensor is 14.0 mV/°C. REGISTER 9-5: CALWD5: CALIBRATION WORD 5 REGISTER U-0 U-0 U-0 U-0 R/P-1 R/P-1 — — — — TANA9 TANA8 bit 13 bit 8 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 TANA7 TANA6 TANA5 TANA4 TANA3 TANA2 TANA1 TANA0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unused bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 13-10 Unimplemented: Read as ‘0’ bit 9-0 TANA: ADC reading of internal silicon temperature at 30°C Calibration bits 9.6 Calibration Word 6 The FCAL bits at memory location 2085h set the internal oscillator calibration. Firmware must read these values and copy them into the OSCCAL Special Function Register located in Bank 3 at 198h. REGISTER 9-6: CALWD6: CALIBRATION WORD 6 REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — bit 13 bit 8 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — FCAL6 FCAL5 FCAL4 FCAL3 FCAL2 FCAL1 FCAL0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unused bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13-7 Unimplemented: Read as ‘0’ bit 6-0 FCAL: Internal Oscillator Calibration bits DS20005479D-page 62 x = Bit is unknown  2015-2020 Microchip Technology Inc. MCP19116/7 9.7 Calibration Word 7 The DCS bits at memory location 2086h store the factory-set offset calibration for the current sense differential amplifier (A2) when configured using ISOUT. Firmware must read these values and copy them into the DCSCAL Special Function Register located in Bank 3 at 199h. If using the internal feedback resistor, refer to Register 9-1. REGISTER 9-7: CALWD7: CALIBRATION WORD 7 REGISTER U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — bit 13 bit 8 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — DCS6 DCS5 DCS4 DCS3 DCS2 DCS1 DCS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 13-7 Unimplemented: Read as ‘0’ bit 6-0 DCS: Differential Current Sense Amplifier Calibration bits when used with ISOUT.  2015-2020 Microchip Technology Inc. DS20005479D-page 63 MCP19116/7 9.8 Calibration Word 8 Calibration Word 8 is at memory location 2087h and contains the calibration bits for the Error Amplifier Offset Voltage EAOFFCAL and for the Current Sense Amplifier (A2) Gain while configured using the Internal Feedback Resistor A2GRFBCAL. A2 Gain calibration trim bits set the 10V/V gain of the current sense amplifier (A2). If the user has configured the device using the internal Feedback Resistor, the A2GRFBCAL calibration value must be read via firmware and copied into the A2GCAL Special Function Register located in Bank 3 at 19Eh. Firmware must also read the EAOFFCAL values and copy them into the EAOFFCAL Special Function Register located in Bank 3 at 19Ch. REGISTER 9-8: CALWD8: CALIBRATION WORD 8 REGISTER U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — A2GRFBCAL3 A2GRFBCAL2 A2GRFBCAL1 A2GRFBCAL0 bit 13 bit 8 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — EAOFFCAL4 EAOFFCAL3 EAOFFCAL2 EAOFFCAL1 EAOFFCAL0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13-12 x = Bit is unknown Unimplemented: Read as ‘0’ bit 11-8 A2GRFBCAL: A2 Current Sense Amplifier Gain Calibration bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 EAOFFCAL: Error Amplifier Offset Voltage Calibration bits DS20005479D-page 64  2015-2020 Microchip Technology Inc. MCP19116/7 9.9 Calibration Word 9 Calibration Word 9 is at memory location 2088h and contains the calibration bits for the OVREF DAC span trim OVRSPCAL and the Current Sense Amplifier while configured using ISOUT A2GCAL. The OVRSPCAL is an individual adjustment specific to calibrating the OVREF DAC span. Firmware must read these values and copy them into the OVRSPCAL Special Function Register located in Bank 3 at 19Fh. REGISTER 9-9: If the user has configured the device using the external feedback path utilizing ISOUT, the A2GCAL value must be read via firmware and copied into the A2GCAL Special Function Register located in Bank 3 at 19Eh. CALWD9: CALIBRATION WORD 9 REGISTER U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — OVRSPCAL4 OVRSPCAL3 OVRSPCAL2 OVRSPCAL1 OVRSPCAL0 bit 13 bit 8 U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — A2GCAL3 A2GCAL2 A2GCAL1 A2GCAL0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13 Unimplemented: Read as ‘0’ bit 12-8 OVRSPCAL: OVREF Span Adjustment bits bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 A2GCAL: A2 Current Sense Amplifier Gain Calibration bits  2015-2020 Microchip Technology Inc. x = Bit is unknown DS20005479D-page 65 MCP19116/7 9.10 Calibration Word 10 DAC span. Firmware must read these values and copy them into the VR2SPCAL Special Function Register located in Bank 2 at 11Ah. Calibration word 10 at memory location 2089h contains the calibration bits for VREF2 DAC span trim VR2SPCAL and the VREF DAC span trim VRSPCAL. The VR2SPCAL is an individual adjustment specific to calibrating the VREF2 REGISTER 9-10: The VRSPCAL is an individual adjustment specific to calibrating the VREF DAC span. Firmware must read these values and copy them into the VRSPCAL Special Function Register located in Bank 2 at 119h. CALWD10: CALIBRATION WORD 10 REGISTER U-0 — R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 VR2SPCAL4 VR2SPCAL3 VR2SPCAL2 VR2SPCAL1 VR2SPCAL0 bit 13 bit 8 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — VRSPCAL4 VRSPCAL3 VRSPCAL2 VRSPCAL1 VRSPCAL0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13 Unimplemented: Read as ‘0’ bit 12-8 VR2SPCAL: VREF2 Span Adjustment bits bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 VRSPCAL: VREF Span Adjustment bits DS20005479D-page 66 x = Bit is unknown  2015-2020 Microchip Technology Inc. MCP19116/7 9.11 Calibration Word 11 Also stored at address 208Ah is the Analog test MUX buffer offset value. This is an 8-bit, two’s complement word that represents the buffer’s offset voltage in units of mV. This value can be used to correct for buffer offset of the analog test signal measurements. See Section 8.0, System Bench Testing for test signal details. Calibration word 11 at memory location 208Ah contains the calibration bits for the 4V LDO (AVDD) trim AVDDCAL and the offset voltage of the analog test buffer BUFF. AVDD supplies the internal analog circuitry and is the default ADC Reference voltage. Firmware must read these values and copy them into the AVDDCAL Special Function Register located in Bank 3 at 19Dh. REGISTER 9-11: CALWD11: CALIBRATION WORD 11 REGISTER U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — AVDDCAL3 AVDDCAL2 AVDDCAL1 AVDDCAL0 bit 13 bit 8 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 BUFF7 BUFF6 BUFF5 BUFF4 BUFF3 BUFF2 BUFF1 BUFF0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 AVDDCAL: AVDD 4.096V LDO Trim bits bit 7-0 BUFF: Analog Test MUX Buffer Offset bits 11111111 = Mid scale (-1mV) • • 10000000 = Largest negative offset (-128 mV) 01111111 = Largest positive offset (+128 mV) • • 00000000 = Mid scale (0 mV)  2015-2020 Microchip Technology Inc. x = Bit is unknown DS20005479D-page 67 MCP19116/7 9.12 Calibration Word 12 The ADCCAL bits at memory location 208Bh contain the calibration bits for the A/D Converter. Calibration Word 12 (ADCCAL) contains the factory measurement of the full-scale ADC Reference. The value represents the number of A/D converter counts per volt. ADCC bits represent the fraction of an A/D converter count, which can provide additional precision when oversampling the ADC for enhanced resolution. This calibration word can be used to calibrate signals read by the Analog-to-Digital Converter. REGISTER 9-12: CALWD12: CALIBRATION WORD 12 REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 ADCC13 ADCC12 ADCC11 ADCC10 ADCC9 ADCC8 bit 13 bit 8 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 ADCC7 ADCC6 ADCC5 ADCC4 ADCC3 ADCC2 ADCC1 ADCC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 13-5 ADCC: Whole number of A/D converter count 111111111 = 511 • • • 000000000 = 0 bit 4-0 ADCC: Fraction number of A/D converter count 11111 = 0.96875 • • • 00001 = 0.03125 00000 = 0.00000 DS20005479D-page 68 x = Bit is unknown  2015-2020 Microchip Technology Inc. MCP19116/7 10.0 ADDRESSABLE USART MODULE The Addressable USART module described in this document is designed into the PIC16F91x. The features of that module include: • Asynchronous and Synchronous modes: - Asynchronous (full duplex) - Synchronous - Master (half duplex) - Synchronous - Slave (half duplex) • 8- and 9-bit data operations • Single and Continuous Receive modes • Address detect • Two-byte FIFOs for Transmit and Receive operations • Majority bit detection in Asynchronous mode • 8-bit Baud Rate generator with speed selection - Fosc/16 or Fosc/64 for Asynchronous mode - Fosc/4 for Synchronous mode • Status bits for - Framing Error - Overrun Error - Transmit Shift Register Status In addition, the existing USART features are altered. These features are changed as previous modules did not exhibit the desired behavior. These alterations include: • Holding all USART state machines in Reset while SPEN (RCSTA) = 0 • Clarification on the TRMT (TXSTA) status bit 10.1 Module Reset When the SPEN (RCSTA) is cleared, all USART state machines are held in Reset. This allows for software re-initialization of the module by toggling the SPEN bit. This also causes all status bits to be reset. All other R/W bits are available to the user, which allows them to pre-configure the module prior to setting the SPEN bit. 10.2 Pin Placement and Port Interaction The bidirectional TX/CK pin is located on GPB6. The bidirectional RX/DT pin is located on GPB7. If TRISC and TRISC are configured as inputs (‘1’), the USART control will automatically reconfigure the pin from input to output as needed.  2015-2020 Microchip Technology Inc. 10.3 USART Asynchronous mode In this mode, the USART uses standard non-return-to-zero (NRZ) format (one Start bit, eight or nine data bits, and one Stop bit). The BRG is used to derive the baud rate frequencies from the system clock. The USART transmits and receives the LSB first. The transmitter and receiver are functionally independent, but use the same data format and baud rate. The BRG produces a clock, either x4, x16 or x64 of the bit shift rate, depending on its configuration (see Section 10.3.2, Asynchronous Receive Mode). Parity is not supported by the hardware, but can be implemented in software using the ninth data bit option. Asynchronous mode is stopped during Sleep. Asynchronous mode is selected by clearing the SYNC (TXSTA) bit. 10.3.1 ASYNCHRONOUS TRANSMIT MODE The USART transmitter block diagram is shown in Figure 10-1. The heart of the transmitter is the transmit (serial) shift register (TSR). The shift register obtains its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data via software. The TSR register is not loaded until the Stop bit has been transmitted from the previous load. As soon as the Stop bit is transmitted, TSR is loaded with new data from the TXREG register (if available). The transmit register (TXREG) is double buffered. As the user writes to TXREG, the data is transferred from the buffer to the transmit shift register (TSR), thus freeing up the buffer register. The interrupt flag TXIF is set as long as the TXEN (TXSTA) bit is set and TXREG is empty, indicating that the transmit buffer register (TXREG) is enabled and free to accept another word. Flag bit TXIF (Transmit Buffer Empty) is read-only and will be set, regardless of the state of the TXIE bit, and cannot be cleared in software. It will be reset only when new data is loaded into TXREG. Transmission is enabled by setting the enable bit TXEN. The actual transmission will not occur until the TXREG register has been loaded with data and the BRG has produced a shift clock (Figure 10-2). The transmission can also be started by first loading TXREG and then setting the enable bit TXEN. Normally, when transmission is first started, TSR is empty. At that point, transfer to TXREG will result in an immediate transfer to TSR, resulting in an empty TXREG. A back-to-back transfer is thus possible (Figure 10-3). Clearing the enable bit TXEN during a transmission will cause the transmission to be aborted and will reset the transmitter. As a result, the GPB6/TX/CK/AN7 pin will revert to hi-impedance. DS20005479D-page 69 MCP19116/7 If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. 2. While TXIF indicates the status of the transmit buffer register, the TRMT (TXSTA) bit indicates the status of the transmit operation. The TRMT bit is cleared automatically upon a byte transfer from TXREG to the Shift register, and is set at the end of a stop bit. A ‘1’ value in the TRMT bit signifies that the transmit state machine is idle. The TRMT bit is read-only and is valid for both Asynchronous and Synchronous transmissions. No interrupt is associated with the TRMT bit. 3. 4. 5. 6. 7. When setting up an Asynchronous Transmission, follow these steps: 1. 8. Initialize the SPBRG register for the appropriate FIGURE 10-1: baud rate. If a high-speed baud rate is desired, set bit BRGH. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). If using interrupts, set GIE (INTCON) and PEIE (INTCON) bits. USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXREG register TXIE 8 MSb (8) LSb 0 2 2 2 Pin Buffer and Control TSR register Interrupt TXEN GPB6/TX/CK pin Baud Rate CLK TRMT SPEN SPBRG Baud Rate Generator TX9 TX9D FIGURE 10-2: Write to TXREG ASYNCHRONOUS MASTER TRANSMISSION Write Word 1 BRG output (shift clock) TX (pin) Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit WORD 1 TXIF bit (Transmit buffer reg. empty flag) TRMT bit (Transmit shift reg. empty flag) DS20005479D-page 70 WORD 1 Transmit Shift Reg  2015-2020 Microchip Technology Inc. MCP19116/7 FIGURE 10-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG BRG output (shift clock) WORD 1 TX (pin) TXIF bit (Transmit buffer reg. empty flag) TRMT bit (Transmit shift reg. empty flag) WORD 2 Start Bit Bit 0 Bit 1 WORD 1 WORD 1 Transmit Shift Reg. Bit 7/8 Stop Bit Start Bit Bit 0 WORD 2 WORD 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. 10.3.2 ASYNCHRONOUS RECEIVE MODE The receiver block diagram is shown in Figure 10-4. The data is received on the GPB7/RX/DT/CCD pin and drives the data recovery block. The data recovery block is a shifter operating at x64, x16 or x4 times the baud rate. The main receive serial shifter operates at the bit rate or at Fosc. Once asynchronous mode is selected, reception is enabled by setting the CREN (RCSTA) bit. The heart of the receiver is the receive (serial) shift register (RSR). After sampling the Stop bit, the received data in the RSR is transferred to RCREG (if empty). If the transfer is complete, flag bit RCIF (PIR1) is set. The interrupt can be enabled by setting the RCIE (PIE1) bit. Flag bit RCIF is read-only and cleared by hardware. It is cleared when RCREG has been read and is empty. RCREG is double buffered (two deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR. On detection of the Stop bit of the third byte, if RCREG is full, the overrun error bit OERR (RCSTA) will be set. The word in RSR will be lost. RCREG can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cleared in software. This is done by resetting the receive logic (CREN is cleared and then set). If bit OERR is set, transfers from the RSR register to RCREG are inhibited, and no further data will be received. The OERR bit can then be cleared in software. Framing error bit FERR (RCSTA) is set if a Stop bit is detected as clear. The FERR bit and the ninth receive bit are buffered the same way as the receive data. Reading the RCREG will load bits RX9D and FERR with new values. The user will need to read the RCSTA register before reading RCREG in order to not lose the old FERR and RX9D data.  2015-2020 Microchip Technology Inc. The USART module has a special provision for multi-processor communication. When the RX9 bit is set in the RCSTA register, nine bits are received and the ninth bit is placed in the RX9D status bit of the RSTA register. The port can be programmed such that when the Stop bit is received, the serial port interrupt will only activate if the RX9D bit is set. This feature is enabled by setting the ADDEN bit in the RCSTA register and can be used in a multi-processor system as indicated in this section. To transmit a block of data in a multi-processor system, the master processor must first send an address byte that identifies the target slave. An address byte is identified by the RX9D bit being a ‘1’ (instead of a ‘0’ for a data byte). If the ADDEN bit is set in the slave’s RCSTA register, all data bytes will be ignored. However, if the ninth received bit is equal to a ‘1’, indicating that the received byte is an address, the slave will be interrupted and the contents of the Receive Shift Register (RSR) will be transferred into the receive buffer. This allows the slave to be interrupted only by addresses, so that the slave can examine the received byte to see if it is addressed. The addressed slave will then clear its ADDEN bit and prepare to receive data bytes from the master. When the ADDEN bit is set, all data bytes are ignored. Following the Stop bit, the data will not be loaded into the receive buffer and no interrupt will occur. If another byte is shifted into the RSR, the previous data byte will be lost. The ADDEN bit will only take affect when the receiver is configured in 9-bit mode. To indicate that a reception is in progress, the RCIDL bit (BAUDCTL) reflects the current state of the receive operation. This bit is cleared (‘0’) on the leading edge of a start bit and set (‘1’) upon the end of a Stop bit. A ‘1’ value in the RCIDL bit signifies that the receive state machine is idle. The RCIDL bit is read-only and is valid for both Asynchronous and Synchronous receptions. No interrupt is associated with the RCIDL bit. See Figures 10-5, 10-6 and 10-7 for timing details of the RCIDL signal. DS20005479D-page 71 MCP19116/7 When setting up an Asynchronous Reception, follow these steps: 1. 2. 3. 4. 5. 6. 7. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing enable bit CREN. 11. If using interrupts, set GIE (INTCON) and PEIE (INTCON) bits. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit RCIE. If 9-bit reception is desired, then set bit RX9. Set ADDEN if address detect is needed. Enable the reception by setting bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE is set. FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM Baud Rate CLK FERR OERR CREN SPBRG x 64 or x 16 or x4 Baud Rate Generator MSb Stop (8) RSR register LSb 1 0 Start 7 RC7/RX/DT Pin Buffer and Control Data Recovery RX9 8 SPEN RX9 ADDEN Enable Load of RX9 ADDEN RSR Receive Buffer 8 RX9D RCREG register RX9D RCREG register FIFO 8 Interrupt RCIF Data Bus RCIE DS20005479D-page 72  2015-2020 Microchip Technology Inc. MCP19116/7 FIGURE 10-5: RX (pin) ASYNCHRONOUS RECEPTION START bit bit0 bit1 bit7/8 STOP bit START bit bit0 bit7/8 STOP bit START bit bit7/8 STOP bit Rcv Shift Reg & Rcv Buffer Reg Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG RCIF (interrupt flag) OERR bit CREN RCIDL Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. FIGURE 10-6: RX (pin) ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT Start bit bit0 bit1 bit8 Stop bit Start bit bit0 bit8 Stop bit Rcv Shift Reg & Rcv Buffer Reg Bit8 = 0, Data Byte Bit8 = 1, Address Byte Read Rcv buffer reg RCREG WORD 1 RCREG RCIF (interrupt flag) RCIDL Note: This timing diagram shows a data byte followed by an address byte.The data byte is not read into the RCREG (receive buffer) because ADDEN = 0. FIGURE 10-7: RX (pin) ASYNCHRONOUS RECEPTION WITH ADDRESS BYTE FIRST Start bit bit0 bit1 bit8 Stop bit Start bit bit0 bit8 Stop bit Rcv Shift Reg & Rcv Buffer Reg Bit8 = 1, Address Byte Read Rcv buffer reg RCREG Bit8 = 0, Data Byte WORD 1 RCREG RCIF (interrupt flag) RCIDL Note: This timing diagram shows an address byte followed by an data byte. The data byte is not read into the RCREG (receive buffer) because ADDEN was not updated and still = 0.  2015-2020 Microchip Technology Inc. DS20005479D-page 73 MCP19116/7 10.4 USART Synchronous Master Mode hi-impedance state (for a reception). The CK pin remains an output if bit CSRC (TXSTA) is set (internal clock). In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA). In addition, enable bit SPEN (RCSTA) is set in order to configure the GPB6/TX/CK/AN7 and the GPB7/RX/DT/CCD I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA). 10.4.1 SYNCHRONOUS MASTER TRANSMIT MODE The transmitter logic, however, is not reset, although it is disconnected from the pins. In order to reset the transmitter, the user has to clear bit TXEN. If bit SREN is set (to interrupt an on-going transmission and receive a single word), then after the single word is received, bit SREN is cleared and the serial port reverts back to transmitting, since bit TXEN is still set. The DT line immediately switches from high-impedance Receive mode to transmit and start driving. To avoid this, it is recommended that the bit TXEN be cleared. Steps to follow when setting up a Synchronous Master Transmission: 1. Synchronous Master Transmit mode works similarly to Asynchronous Transmit mode, see Section 10.3.1 “Asynchronous Transmit Mode”. In Synchronous Transmit mode, the first data byte is shifted out on the next available rising edge of the CK line. Data out is stable relative to the falling edge of the synchronous clock. Clearing enable bit TXEN (TXSTA) during a transmission causes the transmission to be aborted and resets the transmitter. The DT and CK pins revert to high-impedance. If either bit CREN (RCSTA) or bit SREN (RCSTA) is set during a transmission, the transmission is aborted and the DT pin reverts to a 2. 3. 4. 5. 6. 7. 8. Initialize the SPBRG register for the appropriate baud rate. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INT-CON register are set. FIGURE 10-1: SYNCHRONOUS TRANSMISSION Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2Q3 Q4Q1Q2 Q3 Q4Q1 Q2 Q3 Q4 DT pin bit 0 bit 1 Word 1 bit 2 Q3 Q4 Q1 Q2 Q3Q4 Q1Q2 Q3 Q4 Q1 Q2Q3 Q4Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 bit 7/8 bit 0 bit 1 Word 2 bit 7 CK pin Write to TXREG reg Write Word 1 TXIF bit (Interrupt Flag) Write Word 2 TRMT bit TXEN bit '1' '1' Note: Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words. DS20005479D-page 74  2015-2020 Microchip Technology Inc. MCP19116/7 FIGURE 10-2: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) DT pin bit0 bit1 bit2 bitn bit7/8 CK pin Write to TXREG Reg TXIF bit TRMT bit TXEN bit 10.4.2 SYNCHRONOUS MASTER RECEIVE MODE Synchronous Master Receive mode works similarly to Asynchronous Receive mode; see Section 10.3.2 “Asynchronous Receive Mode”. In Synchronous Receive mode, reception is enabled by setting either enable bit SREN (RCSTA) or enable bit CREN (RCSTA). Data is sampled on the GPB7/RX/DT/CCD pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, CREN takes precedence. When setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate. 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. CREN and SREN bits are clear. 4. If interrupts are desired, then set enable bit RCIE. 5. If 9-bit reception is desired, then set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF is set when reception is complete and an interrupt is generated if enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. 11. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.  2015-2020 Microchip Technology Inc. DS20005479D-page 75 MCP19116/7 FIGURE 10-3: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7/8 CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (Interrupt) Read RXREG RCIDL bit Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRG = '0'. 10.5 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the GPB6/TX/CK/AN7 pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in Sleep mode. Slave mode is entered by clearing bit CSRC (TXSTA). 10.5.1 SYNCHRONOUS SLAVE TRANSMIT MODE The operation of the Synchronous Master and Slave modes is identical, except in the case of the Sleep mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following occurs: a) b) c) d) e) The first word immediately transfers to the TSR register and transmits. The second word remains in TXREG register. Flag bit TXIF is not set. When the first word has been shifted out of TSR, the TXREG register transfers the second word to the TSR and flag bit TXIF is not set. If enable bit TXIE is set, the interrupt wakes the chip from Sleep and if the global interrupt is enabled, the program branches to the interrupt vector (0004h). DS20005479D-page 76 When setting up a Synchronous Slave Transmission, follow these steps: 1. 2. 3. 4. 5. 6. 7. 8. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.  2015-2020 Microchip Technology Inc. MCP19116/7 10.5.2 SYNCHRONOUS SLAVE RECEIVE MODE The operation of the Synchronous Master and Slave modes is identical, except in the case of the Sleep mode. Bit SREN is a “don't care” in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during Sleep. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrupt generated will wake the chip from Sleep. If the global interrupt is enabled, the program will branch to the interrupt vector (0004h). When setting up a Synchronous Slave Reception, follow these steps: 1. 2. 3. 4. 5. 6. 7. 8. 9. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated, if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. If using interrupts, ensure that GIE and PEIE (bits 7 and 6) of the INTCON register are set.  2015-2020 Microchip Technology Inc. DS20005479D-page 77 MCP19116/7 REGISTER 10-1: RCSTA – RECEIVE STATUS AND CONTROL REGISTER R/W-0 SPEN bit 7 R/W-0 RX9 Legend: R = Readable bit -n = Value at POR R/W-0 SREN R/W-0 CREN W = Writable bit ‘1’ = Bit is set R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN (1): Serial Port Enable bit 1 = Serial port enabled - configures GPB7/RX/DT/CCD and GPB6/TX/CK/AN7 pins as serial port pins 0 = Serial port disabled - module and its state machines held in Reset bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Unused in this mode - value ignored Synchronous mode - master: 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - slave: Unused in this mode - value ignored bit 4 CREN: Continuous Receive Enable bit Asynchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared 0 = Disables continuous receive Synchronous mode: 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit RX9 = 1: 1 = Enables address detection - enable interrupt and load of the receive buffer when the ninth bit in the receive buffer is set 0 = Disables address detection - all bytes are received, and ninth bit can be used as parity bit RX9 = 0: Unused in this mode bit 2 FERR: Framing Error bit 1 = Framing error (can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1 OERR: Overrun Error bit 1 = Overrun error (can be cleared by clearing bit CREN) 0 = No overrun error bit 0 RX9D: 9th bit of received data (can be parity bit) Note 1: The USART module automatically changes the pin from tri-state to drive as needed. Configure TRISC = 1 and TRISC = 1. DS20005479D-page 78  2015-2020 Microchip Technology Inc. MCP19116/7 REGISTER 10-2: TXSTA – TRANSMIT STATUS AND CONTROL REGISTER R/W-0 CSRC bit 7 R/W-0 TX9 Legend: R = Readable bit -n = Value at POR R/W-0 TXEN R/W-0 SYNC W = Writable bit ‘1’ = Bit is set U-0 — R-1 TRMT R/W-0 TX9D bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 7 CSRC: Clock Source Select bit Asynchronous mode: Unused in this mode - value ignored Synchronous mode: 1 = Master mode - Clock generated internally from BRG 0 = Slave mode - Clock from external source bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5 TXEN (1): Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled bit 4 SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3 Unimplemented: Read as ‘0’ bit 2 BRGH: High Baud Rate Select bit Asynchronous mode: 1 = High speed 0 = Low speed Synchronous mode: Unused in this mode - value ignored bit 1 TRMT: Transmit Operation Idle Status bit 1 = Transmit Operation Idle 0 = Transmit Operation Active bit 0 TX9D: 9th bit of transmit data; can be used as parity bit Note 1: SREN/CREN overrides TXEN in Synchronous mode.  2015-2020 Microchip Technology Inc. R/W-0 BRGH DS20005479D-page 79 MCP19116/7 NOTES: DS20005479D-page 80  2015-2020 Microchip Technology Inc. MCP19116/7 11.0 MEMORY ORGANIZATION There are two types of memory in the MCP19116/7: • Program Memory • Data Memory - Special Function Registers (SFRs) - General Purpose RAM 11.1 Program Memory Organization The MCP19116/7 devices have a 13-bit program counter capable of addressing an 8000 x 14 program memory space. The Reset vector is at 0000h and the Interrupt vector is at 0004h (refer to Figure 11-1). The width of the program memory bus (instruction word) is 14 bits. Since all instructions are a single word, the MCP19116/7 devices have space for 8000 instructions. FIGURE 11-1: PROGRAM MEMORY MAP AND STACK FOR MCP19116/7 PC CALL, RETURN RETFIE, RETLW 13 Stack Level 1 Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h 0005h On-Chip Program Memory 1FFFh User IDs (1) 2000h 2003h ICD Instruction (1) 2004h Revision ID (hardcoded) (1) 2005h Device ID (hardcoded) (1) 2006h Config Word (1) 2007h Reserved 2008h 200Ah 200Bh Reserved for Manufacturing & Test (1) Calibration Words (1) 207Fh 2080h 208Fh 2090h Unimplemented 20FFh 2100h Shadows 2000-20FFh 3FFFh Note 1: Not code-protected.  2015-2020 Microchip Technology Inc. DS20005479D-page 81 MCP19116/7 11.1.1 READING PROGRAM MEMORY AS DATA There are two methods of accessing constants in program memory: • using tables of RETLW instructions. • setting a Files Select Register (FSR) to point to the program memory. 11.1.1.1 RETLW Instruction The RETLW instruction can be used to provide access to the tables of constants. The recommended way to create such tables is shown in Example 11-1. EXAMPLE 11-1: constants BRW RETLW RETLW RETLW RETLW DATA0 DATA1 DATA2 DATA3 RETLW INSTRUCTION ;Add Index in W to ;program counter to ;select data ;Index0 data ;Index1 data my_function ;… LOTS OF CODE… MOVLW DATA_INDEX call constants ;… THE CONSTANT IS IN W The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available, so the older table-read method must be used. 11.2 Data Memory Organization The data memory (refer to Figure 11-1) is partitioned into four banks, which contain the General Purpose Registers (GPR) and the Special Function Registers (SFR). The Special Function Registers are located in the first 32 locations of each bank. Register locations 20h-7Fh in Bank 0, A0h-EFh in Bank 1, 120h-16Fh in Bank 2 and 1A0h-1EFh in Bank 3 are General Purpose Registers, implemented as static RAM. All other RAM is unimplemented and returns ‘0’ when read. The RP bits in the STATUS register are the bank select bits. EXAMPLE 11-2: BANK SELECT RP1 RP0 0 0  Bank 0 is selected 0 1 Bank 1 is selected 1 0  Bank 2 is selected 1 1  Bank 3 is selected To move values from one register to another register, the value must pass through the W register. This means that for all register-to-register moves, two instruction cycles are required. The entire data memory can be accessed either directly or indirectly. Direct addressing may require the use of the RP bits. Indirect addressing requires the use of the FSR. Indirect addressing uses the Indirect Register Pointer (IRP) bit in the STATUS register for access to the Bank0/Bank1 or the Bank2/Bank3 areas of data memory. 11.2.1 GENERAL PURPOSE REGISTER FILE The register file is organized as 64 x 8 in the MCP19116/7. Each register is accessed, either directly or indirectly, through the FSR (refer to Section 11.5 “Indirect Addressing, INDF and FSR Registers”). DS20005479D-page 82  2015-2020 Microchip Technology Inc. MCP19116/7 11.2.2 CORE REGISTERS 11.2.2.1 The core registers contain the registers that directly affect the basic operation. The core registers can be addressed from any bank. These registers are listed in Table 11-1. For detailed information, refer to Table 11-2. TABLE 11-1: CORE REGISTERS Addresses BANKx x00h, x80h, x100h, or x180h INDF x02h, x82h, x102h, or x182h PCL x03h, x83h, x103h, or x183h STATUS x04h, x84h, x104h, or x184h FSR x0Ah, x8Ah, x10Ah, or x18Ah PCLATH x0Bh, x8Bh, x10Bh, or x18Bh INTCON The STATUS register contains: • the arithmetic status of the ALU • the Reset status • the bank select bits for data memory (RAM) The STATUS register can be the destination for any instruction, like any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, the Write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘000u u1uu’ (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions be used to alter the STATUS register, because these instructions do not affect any Status bits. Note: REGISTER 11-1: R/W-0 The C and DC bits operate as Borrow and Digit Borrow out bits, respectively, in subtraction. STATUS: STATUS REGISTER R/W-0 IRP STATUS Register RP1 R/W-0 RP0 R-1 TO R-1 PD R/W-x Z R/W-x DC bit 7 (1) R/W-x C (1) bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR x = Bit is unknown ‘0’ = Bit is cleared ‘1’ = Bit is set bit 7 IRP: Register Bank Select bit (used for Indirect addressing) 1 = Bank 2 & 3 (100h - 1FFh) 0 = Bank 0 & 1 (00h - FFh) bit 6-5 RP: Register Bank Select bits (used for Direct addressing) 00 = Bank 0 (00h - 7Fh) 01 = Bank 1 (80h - FFh) 10 = Bank 2 (100h - 17Fh) 11 = Bank 3 (180h - 1FFh) bit 4 TO: Time-Out bit 1 = After power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time out occurred Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit in the source register.  2015-2020 Microchip Technology Inc. DS20005479D-page 83 MCP19116/7 REGISTER 11-1: STATUS: STATUS REGISTER (CONTINUED) bit 3 PD: Power-Down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2 Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1 DC: Digit Carry/Digit Borrow bit (1) (ADDWF, ADDLW, SUBLW, SUBWF instructions) 1 = A carry-out from the 4th low-order bit of the result occurred 0 = No carry-out from the 4th low-order bit of the result bit 0 C: Carry/Borrow bit (1) (ADDWF, ADDLW, SUBLW, SUBWF instructions) (1) 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred Note 1: 11.2.3 For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit in the source register. SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral functions for controlling the desired operation of the device (refer to Figure 11-2). These registers are static RAM. The special registers can be classified into two sets: • core • peripheral The Special Function Registers associated with the microcontroller core are described in this section. Those related to the operation of the peripheral features are described in the associated section for that peripheral feature. DS20005479D-page 84  2015-2020 Microchip Technology Inc. MCP19116/7 11.3 DATA MEMORY FIGURE 11-2: MCP19116/7 DATA MEMORY MAP File Address Indirect addr. (1) TMR0 PCL STATUS FSR PORTGPA PORTGPB PIR1 PIR2 PCON PCLATH INTCON TMR1L TMR1H T1CON TMR2 T2CON PR2 PWMPHL PWMPHH PWMRL PWMRH VREFCON VREF2CON OSCTUNE ADRESL ADRESH ADCON0 ADCON1 General Purpose Register 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 96 Bytes File Address Indirect addr. (1) OPTION_REG PCL STATUS FSR TRISGPA TRISGPB PIE1 PIE2 PCLATH INTCON VINUVLO VINOVLO VINCON CC1RL CC1RH CC2RL CC2RH CCDCON DESATCON OVCON OVREFCON DEADCON SLPCRCON ICOACON ICLEBCON General Purpose Register 80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h File Address Indirect addr. (1) TMR0 PCL STATUS FSR WPUGPA WPUGPB PE1 MODECON ABECON PCLATH INTCON Reserved SSPADD SSPBUF SSPCON1 SSPCON2 SSPCON3 SSPMSK1 SSPSTAT SSPADD2 SSPMSK2 VRSPCAL VR2SPCAL SPBRG RCREG TXREG TXSTA RCSTA General Purpose Register 80 Bytes Accesses Bank 0 7Fh Bank 0 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h 80 bytes EFh F0h Accesses Bank 0 FFh Bank 1 File Address Indirect addr. (1) OPTION_REG PCL STATUS FSR IOCA IOCB ANSELA ANSELB PCLATH INTCON PORTICD (2) TRISICD (2) ICKBUG (2) BIGBUG (2) PMCON1 PMCON2 PMADRL PMADRH PMDATL PMDATH DSTCAL RFBTCAL OSCCAL DCSCAL TTACAL BGRCAL EAOFFCAL AVDDCAL A2GCAL OVRSPCAL General Purpose Register 80 bytes 16F 170h Accesses Bank 0 17Fh Bank2 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h 1EF 1F0h 1FFh Bank3 Unimplemented data memory locations, read as '0'. Note 1: 2: Not a physical register. Only accessible when DBGEN = 0 and ICKBUG = 1.  2015-2020 Microchip Technology Inc. DS20005479D-page 85 Addr. Name MCP19116/7 SPECIAL REGISTERS SUMMARY BANK 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets (1) Bank 0 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 02h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000 03h STATUS 000q quuu 04h FSR 05h IRP RP1 RP0 TO PORTGPA GPA7 GPA6 GPA5 06h PORTGPB GPB7 GPB6 GPB5 GPB4 — — 07h PIR1 TXIF RCIF BCLIF SSPIF CC2IF CC1IF 08h PIR2 CDSIF ADIF — OTIF OVIF DRUVIF VDDFLAG VDDOK PD Z DC C 0001 1xxx xxxx xxxx uuuu uuuu GPA1 GPA0 xxx- xxxx uuu- uuuu GPB1 GPB0 xxxx --xx uuuu --uu TMR2IF TMR1IF 0000 0000 0000 0000 OVLOIF UVLOIF 00-0 0000 00-0 0000 POR BOR 0--- 10qq 0--- 10uu Indirect data memory address pointer ADC_REFR 09h PCON — — 0Ah PCLATH — — — 0Bh INTCON GIE PEIE T0IE — GPA3 — GPA2 Write buffer for upper 5 bits of program counter INTE IOCE T0IF INTF IOCF (2) ---0 0000 ---0 0000 0000 000x 0000 000u uuuu uuuu  2015-2020 Microchip Technology Inc. 0Ch TMR1L Holding register for the Least Significant byte of the 16-bit TMR1 xxxx xxxx 0Dh TMR1H Holding register for the Most Significant byte of the 16-bit TMR1 xxxx xxxx uuuu uuuu 0Eh T1CON --00 --00 --uu --uu 0Fh TMR2 0000 0000 uuuu uuuu 10h T2CON ---- -000 ---- -000 11h PR2 Timer2 Module Period Register 1111 1111 1111 1111 12h — Unimplemented — — 13h PWMPHL SLAVE Phase Shift Register xxxx xxxx uuuu uuuu 14h PWMPHH SLAVE Phase Shift Register xxxx xxxx uuuu uuuu 15h PWMRL PWM Register Low Byte xxxx xxxx uuuu uuuu 16h PWMRH PWM Register High Byte xxxx xxxx uuuu uuuu 17h — Unimplemented — — 18h — Unimplemented — — 19h VREFCON VREF7 VREF6 VREF5 VREF4 VREF3 VREF2 VREF1 VREF0 0000 0000 0000 0000 1Ah VREF2CON VREF27 VREF26 VREF25 VREF24 VREF23 VREF22 VREF21 VREF20 0000 0000 0000 0000 1Bh OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 ---0 0000 ---0 0000 1Ch ADRESL Least significant 8 bits of the A/D result xxxx xxxx uuuu uuuu 1Dh ADRESH Most significant 2 bits of the A/D result 0000 00xx 0000 00uu 1Eh ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON -000 0000 -000 0000 1Fh ADCON1 — ADCS2 ADCS1 ADCS0 — — — VCFG -000 ---0 -000 ---0 Legend: Note 1: 2: — — T1CKPS1 T1CKPS0 — — — — — — TMR1CS TMR1ON TMR2ON T2CKPS1 T2CKPS0 Timer2 Module Register — — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation. MCLR and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will be set again if the mismatch exists. MCP19116/7 DS20005479D-page 86 TABLE 11-2:  2015-2020 Microchip Technology Inc. TABLE 11-3: Addr. MCP19116/7 SPECIAL REGISTERS SUMMARY BANK 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Values on all other resets (1) xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 0000 0000 0000 0001 1xxx 000q quuu Bank 1 80h INDF 81h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) 82h PCL RAPU INTEDG T0CS T0SE PSA PS2 PS1 Program Counter's (PC) Least Significant byte 83h STATUS 84h FSR 85h TRISGPA TRISA7 TRISA6 TRISA5 — 86h TRISGPB TRISB7 TRISB6 TRISB5 TRISB4 — — 87h PIE1 TXIE RCIE BCLIE SSPIE CC2IE CC1IE 88h PIE2 CDSIE ADIE — OTIE OVIE DRUVIE OVLOIE 89h PS0 IRP RP1 RP0 TO PD Z DC C Indirect data memory address pointer — TRISA3 TRISA2 xxxx xxxx uuuu uuuu TRISA0 1110 1111 1110 1111 TRISB1 TRISB0 1111 0011 1111 0011 TMR2IE TMR1IE 0000 0000 0000 0000 UVLOIE 00-0 0000 00-0 0000 TRISA1 Unimplemented 8Ah PCLATH — — — 8Bh INTCON GIE PEIE T0IE Write buffer for upper 5 bits of program counter INTE IOCE T0IF INTF IOCF (2) — — ---0 0000 ---0 0000 0000 000x 0000 000u 8Ch — Unimplemented — — 8Dh — Unimplemented — — 8Eh — Unimplemented — — 8Fh — Unimplemented — — 90h VINUVLO UVLO0 --xx xxxx --uu uuuu 91h VINOVLO — — OVLO5 OVLO4 OVLO3 OVLO2 OVLO1 OVLO0 --xx xxxx --uu uuuu 92h VINCON UVLOEN UVLOOUT UVLOINTP UVLOINTN OVLOEN OVLOOUT OVLOINTP OVLOINTN 0x00 0x00 0u00 0u00 93h CC1RL Capture1/Compare1 Register1 x Low Byte (LSB) xxxx xxxx uuuu uuuu uuuu uuuu — — UVLO5 UVLO4 UVLO3 UVLO2 UVLO1 CC1RH Capture1/Compare1 Register2 x High Byte (MSB) xxxx xxxx CC2RL Capture2/Compare2 Register1 x Low Byte (LSB) xxxx xxxx uuuu uuuu 96h CC2RH Capture2/Compare2 Register2 x High Byte (MSB) xxxx xxxx uuuu uuuu 97h CCDCON 98h DESATCON 99h OVCON 9Ah OVREFCON 9Bh CC2M CC1M DS20005479D-page 87 xxxx xxxx uuuu uuuu CDSMUX CDSWDE Reserved CDSPOL CDSOE CDSOUT CDSINTP CDSINTN 0000 0x00 0000 0u00 — — — — OVEN OVOUT OVINTP OVINTN ---- 0x00 ---- 0u00 OOV7 OOV6 OOV5 OOV4 OOV3 OOV2 OOV1 OOV0 xxxx xxxx uuuu uuuu DEADCON PDRVDT3 PDRVDT2 PDRVDT1 PDRVDT0 SDRVDT3 SDRVDT2 SDRVDT1 SDRVDT0 xxxx xxxx uuuu uuuu 9Ch SLPCRCON — SLPBY SLPS5 SLPS4 SLPS3 SLPS2 SLPS1 SLPS0 -xxx xxxx -uuu uuuu 9Dh ICOACON — — — — ICOAC3 ICOAC2 ICOAC1 ICOAC0 ---- xxxx ---- uuuu 9Eh ICLEBCON — — — — — — ICLEBC1 ICLEBC0 ---- --xx ---- --uu — — 9Fh Legend: Note 1: 2: — Unimplemented — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation. MCLR and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will be set again if the mismatch exists. MCP19116/7 94h 95h Addr. Name MCP19116/7 SPECIAL REGISTERS SUMMARY BANK 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Value on all other resets (1) Bank 2 100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 102h PCL Program Counter's (PC) Least Significant byte 0000 0000 0000 0000 103h STATUS 0001 1xxx 000q quuu IRP RP1 RP0 TO PD Z DC C 104h FSR xxxx xxxx uuuu uuuu 105h WPUGPA — — WPUA5 Indirect data memory address pointer — WPUA3 WPUA2 WPUA1 WPUA0 --1- 1111 --u- uuuu 106h WPUGPB WPUB7 WPUB6 WPUB5 WPUB4 — — WPUB1 — 1111 --1- uuuu --u- 107h PE1 PDRVEN SDRVEN PDRVBY SDRVBY — ISPUEN PWMSTR_PEN PWMSTR_SEN 0000 -100 0000 -100 108h MODECON 109h ABECON 10Ah PCLATH — — — 10Bh INTCON GIE PEIE T0IE 10Ch — 10Dh MSC1 MSC0 RFB — MSC2 — — — 001- 0--- 001- 0--- DIGOEN DSEL2 DSEL1 DSEL0 DRUVSEL — EADIS ANAOEN 0000 0-00 0000 0-00 ---0 0000 ---0 0000 0000 000x 0000 000u Reserved — — — Unimplemented — — 10Eh — Unimplemented — — 10Fh — Unimplemented — — 110h SSPADD ADD 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 0000 0000 0000 0000 Write buffer for upper 5 bits of program counter INTE IOCE T0IF INTF IOCF (2)  2015-2020 Microchip Technology Inc. 111h SSPBUF 112h SSPCON1 WCOL SSPOV SSPEN Synchronous Serial Port Receive Buffer/Transmit Register CKP 113h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 114h SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 0000 0000 0000 115h SSPMSK1 1111 1111 1111 1111 116h SSPSTAT 117h SSPADD2 118h SSPMSK2 119h VRSPCAL — — — VRSPCAL4 VRSPCAL3 VRSPCAL2 VRSPCAL1 VRSPCAL0 11Ah VR2SPCAL — — — VR2SPCAL4 VR2SPCAL3 VR2SPCAL2 VR2SPCAL1 SPBRG7 SPBRG6 SPBRG5 SPBRG4 SPBRG3 SPBRG2 SPBRG1 SSPM MSK SMP CKE D/A P S R/W UA BF — — 0000 0000 0000 0000 1111 1111 1111 1111 ---x xxxx ---u uuuu VR2SPCAL0 ---x xxxx ---u uuuu SPBRG0 ADD2 MSK2 11Bh SPBRG 0000 0000 0000 0000 11Ch RCREG USART Receive Data Register 0000 0000 0000 0000 11Dh TXREG USART Transmit Data Register 0000 0000 0000 0000 11Eh TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 0000 0000 0000 11Fh RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 0000 0000 0000 Legend: Note 1: 2: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation. MCLR and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will be set again if the mismatch exists. MCP19116/7 DS20005479D-page 88 TABLE 11-4:  2015-2020 Microchip Technology Inc. TABLE 11-5: Addr. MCP19116/7 SPECIAL REGISTERS SUMMARY BANK 3 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Reset Values on all other resets (1) xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 0000 0000 0000 0001 1xxx 000q quuu Bank 3 180h INDF 181h OPTION_REG Addressing this location uses contents of FSR to address data memory (not a physical register) 182h PCL RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter's (PC) Least Significant byte 183h STATUS 184h FSR IRP RP1 RP0 TO 185h IOCA IOCA7 IOCA6 IOCA5 — PD Z DC C Indirect data memory address pointer IOCA3 IOCA2 IOCA1 xxxx xxxx uuuu uuuu IOCA0 000- 0000 0000 0000 186h IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — IOCB1 IOCB0 0000 --00 0000 --00 187h ANSELA — — — — ANSA3 ANSA2 ANSA1 ANSA0 ---- 1111 ---- 1111 188h ANSELB — ANSB6 ANSB5 ANSB4 — — ANSB1 — -111 --1- -111 --1- 189h — 18Ah PCLATH 18Bh INTCON Unimplemented — — — GIE PEIE T0IE Write buffer for upper 5 bits of program counter INTE IOCE T0IF INTF IOCF (2) — — ---0 0000 ---0 0000 0000 000x 0000 000u In-Circuit Debug Port Register xxx --xx uuuu --uu TRISICD (3) In-Circuit Debug TRIS Register 1111 0011 1111 0011 18Eh ICKBUG (3) In-Circuit Debug Register 0000 0000 000u uuuu 18Fh BIGBUG (3) In-Circuit Debug Breakpoint Register 0000 0000 uuuu uuuu 190h PMCON1 -0-- -000 -0-- -000 18Ch PORTICD 18Dh (3) — CALSEL — — — WREN WR RD 191h PMCON2 ---- ---- ---- ---- 192h PMADRL PMADRL7 PMADRL6 PMADRL5 Program Memory Control Register 2 (not a physical register) PMADRL4 PMADRL3 PMADRL2 PMADRL1 PMADRL0 0000 0000 0000 0000 193h PMADRH — — — — PMADRH3 PMADRH2 PMADRH1 PMADRH0 ---- -000 ---- -000 194h PMDATL PMDATL7 PMDATL6 PMDATL5 PMDATL4 PMDATL3 PMDATL2 PMDATL1 PMDATL0 0000 0000 0000 0000 195h PMDATH — — PMDATH5 PMDATH4 PMDATH3 PMDATH2 PMDATH1 PMDATH0 --00 0000 --00 0000 DSTCAL — — — DSTCAL4 DSTCAL3 DSTCAL2 DSTCAL1 DSTCAL0 ---x xxxx ---u uuuu RFBTCAL — — RFBCAL5 RFBCAL4 RFBCAL3 RFBCAL2 RFBCAL1 RFBCAL0 --xx xxxx --uu uuuu 198h OSCCAL — FCALT6 FCALT5 FCALT4 FCALT3 FCALT2 FCALT1 FCALT0 -xxx xxxx -uuu uuuu 199h DCSCAL — DCSCAL6 DCSCAL5 DCSCAL4 DCSCAL3 DCSCAL2 DCSCAL1 DCSCAL0 -xxx xxxx -uuu uuuu 19Ah TTACAL — — — — TTA3 TTA2 TTA1 TTA0 ---- xxxx ---- uuuu 19Bh BGRCAL — — — BGRT4 BGRT3 BGRT2 BGRT1 BGRT0 ---x xxxx ---u uuuu 19Ch EAOFFCAL — — — EAOFFCAL4 EAOFFCAL3 EAOFFCAL2 EAOFFCAL1 EAOFFCAL0 ---x xxxx ---u uuuu 19Dh AVDDCAL — — — — AVDDCAL3 AVDDCAL2 AVDDCAL1 AVDDCAL0 ---- xxxx ---- uuuu 19Eh A2GCAL — — — — A2GCAL3 A2GCAL2 A2GCAL1 A2GCAL0 ---- xxxx ---- uuuu 19Fh OVRSPCAL — — — ---x xxxx ---u uuuu Legend: Note 1: 2: 3: OVRSPCAL4 OVRSPCAL3 OVRSPCAL2 OVRSPCAL1 OVRSPCAL0 — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented Other (non power-up) resets include MCLR Reset and Watchdog Timer Reset during normal operation. MCLR and WDT reset does not affect the previous value data latch. The IOCF bit will be cleared upon reset but will be set again if the mismatch exists. Only accessible when DBGEN = 0 and ICKBUG = 1. MCP19116/7 DS20005479D-page 89 196h 197h MCP19116/7 11.3.1 OPTION_REG REGISTER Note: The OPTION_REG register is a readable and writable register, which contains various control bits to configure: • • • • Timer0/WDT prescaler External GPA2/INT interrupt Timer0 Weak pull-ups on PORTGPA and PORTGPB REGISTER 11-2: To achieve a 1:1 prescaler assignment for Timer0, assign the prescaler to the WDT by setting PSA bit to ‘1’ in the OPTION_REG register. Refer to Section 23.1.3 “Software Programmable Prescaler”. OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR x = Bit is unknown ‘0’ = Bit is cleared ‘1’ = Bit is set bit 7 RAPU: Port GPx Pull-Up Enable bit (1) 1 = Port GPx pull-ups are disabled 0 = Port GPx pull-ups are enabled bit 6 INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of INT pin 0 = Interrupt on falling edge of INT pin bit 5 T0CS: TMR0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock bit 4 T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin bit 3 PSA: Prescaler Assignment bit 1 = Prescaler is assigned to WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0 PS: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1: 2 1: 1 001 1: 4 1: 2 010 1: 8 1: 4 011 1: 16 1: 8 100 1: 32 1: 16 101 1: 64 1: 32 110 1: 128 1: 64 111 1: 256 1: 128 Note 1: Individual WPUx bit must also be enabled. DS20005479D-page 90  2015-2020 Microchip Technology Inc. MCP19116/7 11.4 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC) is not directly readable or writable and comes from PCLATH. On any reset, the PC is cleared. Figure 11-3 shows the two situations for loading the PC: • the upper example shows how the PC is loaded on a write to PCL (PCLATH  PCH) • the lower example shows how the PC is loaded during a CALL or GOTO instruction (PCLATH  PCH). FIGURE 11-3: PROGRAM COUNTER (PC) LOADING IN DIFFERENT SITUATIONS PCH PCL 12 8 7 0 Instruction with Destination PC 8 PCLATH 5 ALU Result PCLATH PCH 12 11 10 PCL 8 0 7 PC GOTO, CALL 2 PCLATH 11 OPCODE PCLATH 11.4.1 11.4.3 COMPUTED GOTO A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). Care should be exercised when jumping into a look-up table or program branch table (computed GOTO) by modifying the PCL register. Assuming that PCLATH is set to the table start address, if the table length is greater than 255 instructions or if the lower eight bits of the memory address roll over from 0xFFh to 0X00h in the middle of the table, then PCLATH must be incremented for each address rollover that occurs between the table beginning and the table location within the table.  2015-2020 Microchip Technology Inc. COMPUTED FUNCTION CALLS A computed function CALL allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. When performing a table-read using a computed function CALL, care should be exercised if the table location crosses a PCL memory boundary (each 256-byte block). If using the CALL instruction, the PCH and PCL registers are loaded with the operand of the CALL instruction. PCH is loaded with PCLATH. 11.4.4 STACK The MCP19116/7 devices have an 8-level x 13-bit wide hardware stack (refer to Figure 11-1). The stack space is not part of either program or data space and the Stack Pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation. The stack operates as a circular buffer. This means that after the stack has been PUSHed eight times, the 9th push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). Note 1: There are no Status bits to indicate Stack Overflow or Stack Underflow conditions. 2: There are no instructions/mnemonics called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or the vectoring to an interrupt address. MODIFYING PCL REGISTER Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC bits (PCH) to be replaced by the contents of the PCLATH register. This allows the entire contents of the program counter to be changed by writing the desired upper five bits to the PCLATH register. When the lower eight bits are written to the PCL register, all 13 bits of the program counter will change to the values contained in the PCLATH register and those being written to the PCL register. 11.4.2 For more information, refer to Application Note AN556, “Implementing a Table Read” (DS00000556). 11.5 Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF register (see Table 11-1). Any instruction using the INDF register actually accesses data pointed to by the File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing to the INDF register directly results in a NO OPERATION (NOP) (although Status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR and the IRP bit in the STATUS register, as shown in Figure 11-4. A simple program to clear RAM location 40h-7Fh using indirect addressing is shown in Example 11-3. DS20005479D-page 91 MCP19116/7 EXAMPLE 11-3: MOVLW MOVWF NEXT CLRF INCF BTFSS GOTO CONTINUE INDIRECT ADDRESSING 0x40 FSR INDF FSR FSR,7 NEXT FIGURE 11-4: ;initialize pointer ;to RAM ;clear INDF register ;inc pointer ;all done? ;no clear next ;yes continue DIRECT/INDIRECT ADDRESSING Direct Addressing RP1 RP0 Bank Select From Opcode 6 Indirect Addressing 0 7 IRP Bank Select Location Select 00 01 10 File Select Register 0 Location Select 11 00h 180h Data Memory 7Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 For memory map detail, refer to Figure 11-2. DS20005479D-page 92  2015-2020 Microchip Technology Inc. MCP19116/7 12.0 DEVICE CONFIGURATION Note: Device Configuration consists of Configuration Word, Code Protection and Device ID. 12.1 Configuration Word There are several Configuration Word bits that allow different timers to be enabled and memory protection options. These are implemented as Configuration Word at 2007h. REGISTER 12-1: The DBGEN bit in Configuration Word is managed automatically by device development tools, including debuggers and programmers. For normal device operation, this bit should be maintained as a '1'. Debug is available only on the MCP19117. CONFIG: CONFIGURATION WORD R/P-1 U-1 R/P-1 R/P-1 U-1 R/P-1 DBGEN — WRT1 WRT0 — BOREN (1) bit 13 U-1 R/P-1 — CP bit 8 R/P-1 MCLRE R/P-1 PWRTE (1) R/P-1 U-1 U-1 U-1 WDTE — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘1’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 13 DBGEN: ICD Debug bit 1 = ICD debug mode disabled 0 = ICD debug mode enabled bit 12 Unimplemented: Read as ‘0’ bit 11-10 WRT: Flash Program Memory Self-Write Enable bit 11 = Write protection off 10 = 000h to 7FFh write protected, 800h to 1FFFh may be modified by PMCON1 control 01 = 000h to FFFh write protected, 1000h to 1FFFh may be modified by PMCON1 control 00 = 000h to 1FFFh write protected, entire program memory is write protected. bit 9 Unimplemented: Read as ‘1’ bit 8 BOREN: Brown-out Reset Enable bit (1) 1 = BOR disabled during Sleep and Enabled during operation 0 = BOR disabled bit 7 Unimplemented: Read as ‘1’ bit 6 CP: Code Protection 1 = Program memory is not code protected 0 = Program memory is external read and write protected bit 5 MCLRE: MCLR Pin Function Select 1 = MCLR pin is MCLR function and weak internal pull-up is enabled 0 = MCLR pin is alternate function, MCLR function is internally disabled bit 4 PWRTE: Power-Up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 3 WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 2-0 Unimplemented: Read as ‘1’ Note 1: Enabling Brown-out Reset does not automatically enable the Power-up Timer.  2015-2020 Microchip Technology Inc. DS20005479D-page 93 MCP19116/7 12.2 Code Protection Code protection allows the device to be protected from unauthorized access. Internal access to the program memory is unaffected by any code protection setting. 12.2.1 PROGRAM MEMORY PROTECTION The entire program memory space is protected from external reads and writes by the CP bit in the Configuration Word. When CP = 0, external reads and writes of program memory are inhibited and a read will return all ‘0’s. The CPU can continue to read program memory, regardless of the protection bit settings. Writing the program memory is dependent upon the write protection setting. Refer to Section 12.3 “Write Protection” for more information. 12.3 Write Protection Write protection allows the device to be protected from unintended self-writes. Applications, such as boot loader software, can be protected while allowing other regions of the program memory to be modified. The WRT bits in the Configuration Word define the size of the program memory block that is protected. 12.4 ID Locations Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers. These locations are not accessible during normal execution but are readable and writable during Program/Verify mode. Only the Least Significant 7 bits of the ID locations are reported when using MPLAB Integrated Development Environment (IDE). DS20005479D-page 94  2015-2020 Microchip Technology Inc. MCP19116/7 13.0 OSCILLATOR MODES Note: The MCP19116/7 devices have one oscillator configuration which is an 8 MHz internal oscillator. 13.1 13.3 Internal Oscillator (INTOSC) The Internal Oscillator module provides a system clock source of 8 MHz. The frequency of the internal oscillator can be trimmed with a calibration value in the OSCTUNE register. 13.2 Oscillator Calibration The FCAL bits in the CALWD6 register must be written into the OSCCAL register to calibrate the internal oscillator. Frequency Tuning in User Mode In addition to the factory calibration, the base frequency can be tuned in the user's application. This frequency tuning capability allows the user to deviate from the factory-calibrated frequency. The user can tune the frequency by writing to the OSCTUNE register (refer to Register 13-1). The 8 MHz internal oscillator is factory-calibrated. The factory calibration values reside in the read-only CALWD6 register. These values must be read from the CALWD6 register and stored in the OSCCAL register. Refer to Section 18.0 “Flash Program Memory Control” for the procedure on reading the program memory. REGISTER 13-1: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — TUN4 TUN3 TUN2 TUN1 TUN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 TUN: Frequency Tuning bits 01111 = Maximum frequency 01110 = Maximum frequency • • • 00001 = 00000 = Center frequency. Oscillator Module is running at the calibrated frequency. 11111 = • • • 10000 = Minimum frequency  2015-2020 Microchip Technology Inc. DS20005479D-page 95 MCP19116/7 13.3.1 OSCILLATOR DELAY UPON POWER-UP, WAKE-UP AND BASE FREQUENCY CHANGE In applications where the OSCTUNE register is used to shift the frequency of the internal oscillator, it is recommended that the application does not expect the frequency of the internal oscillator to stabilize immediately. In this case, the frequency may shift gradually toward the new value. The time for this frequency shift is less than eight cycles of the base frequency. On power-up, the device is held in reset by the power-up time if the power-up timer is enabled. Following a wake-up from Sleep mode or POR, an internal delay of ~10 µs is invoked to allow the memory bias to stabilize before program execution can begin. TABLE 13-1: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page OSCTUNE — — — TUN4 TUN3 TUN2 TUN1 TUN0 95 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by clock sources. TABLE 13-2: Name CONFIG6 SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH CLOCK SOURCES Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 13:8 — — — — — — — — 7:0 — FCAL6 FCAL5 FCAL4 FCAL3 FCAL2 FCAL1 FCAL0 Register on page 62 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by clock sources. DS20005479D-page 96  2015-2020 Microchip Technology Inc. MCP19116/7 14.0 RESETS The reset logic is used to place the MCP19116/7 into a known state. The source of the reset can be determined by using the device status bits. There are multiple ways to reset the MCP19116/7 devices: • • • • • Power-on Reset (POR) Overtemperature Reset (OT) MCLR Reset WDT Reset Brown-out Reset (BOR) WDT (Watchdog Timer) wake-up does not cause register resets in the same manner as a WDT Reset, since wake-up is viewed as the resumption of normal operation. TO and PD bits are set or cleared differently in different Reset situations, as indicated in Table 14-1. The software can use these bits to determine the nature of the Reset. Refer to Table 14-2 for a full description of Reset states of all registers. A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 14-1. To allow VDD to stabilize, an optional power-up timer can be enabled to extend the Reset time after a POR event. The MCLR Reset path has a noise filter to detect and ignore small pulses. Refer to Section 5.0 “Digital Electrical Characteristics” for pulse-width specifications. Some registers are not affected in any Reset condition; their status is unknown on POR and unchanged in any other Reset. Most other registers are reset to a “Reset state” on: • • • • • Power-on Reset MCLR Reset MCLR Reset during Sleep WDT Reset Brown-out Reset FIGURE 14-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR/TEST_EN pin Sleep WDT Module Time-Out Reset VDD Rise Power-On Reset Detect Brown-Out Brown-Out Reset VDD S Chip_Reset Reset R Q BOREN PWRT On-Chip RC OSC 11-bit Ripple Counter Enable PWRT TABLE 14-1: TIME-OUT IN VARIOUS SITUATIONS Power-Up PWRTE = 0 PWRTE = 1 Wake-Up from Sleep TPWRT — —  2015-2020 Microchip Technology Inc. DS20005479D-page 97 MCP19116/7 TABLE 14-2: STATUS/PCON BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 x 1 1 Power-on Reset u 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-Up u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep Legend: u = unchanged, x = unknown 14.1 Power-on Reset (POR) The on-chip POR circuit holds the chip in Reset until VDD has reached a high enough level for proper operation. To take advantage of the POR, simply connect the MCLR pin through a resistor to VDD. This will eliminate external RC components usually needed to create Power-on Reset. When the device starts normal operation (exits the Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure proper operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. 14.2 MCLR MCP19116/7 devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. Voltages applied to the MCLR pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event. For this reason, Microchip recommends that the MCLR pin no longer be tied directly to VDD. The use of a Resistor-Capacitor (RC) network, as shown in Figure 14-2, is recommended. An internal MCLR option is enabled by clearing the MCLRE bit in the CONFIG register. When MCLRE = 0, the Reset signal to the chip is generated internally. When MCLRE = 1, the MCLR pin becomes an external Reset input. In this mode, the MCLR pin has a weak pull-up to VDD. FIGURE 14-2: RECOMMENDED MCLR CIRCUIT VDD R2 SW1 (optional) 100 (needed with capacitor) MCLR MCP19116/7 R1 1 k (or greater) C1 0.1 µF (optional, not critical) DS20005479D-page 98  2015-2020 Microchip Technology Inc. MCP19116/7 14.3 Brown-Out Reset (BOR) Note: The Power-Up Timer is enabled by the PWRTE bit in the CONFIG register. If VDD drops below VBOR while the Power-Up Timer is running, the chip will go back into a Brown-out Reset and the Power-Up Timer will be re-initialized. Once the VDD rises above VBOR, the Power-Up Timer will execute a 64 ms reset. The BOREN bit in the CONFIG register enables or disables the BOR mode, as defined in the CONFIG register. A brown-out occurs when VDD falls below VBOR for greater than 100 µs minimum. On any Reset (Power-on, Brown-out, Watchdog Timer, etc.), the chip will remain in Reset until VDD rises above VBOR (refer to Figure 14-3). If enabled, the Power-Up Timer will be invoked by the Reset and will keep the chip in Reset for an additional 64 ms. During power-up, it is recommended that the BOR configuration bit is enabled holding the MCU in Reset (OSC turned off and no code execution) until VDD exceeds the VBOR threshold. Users have the option of adding an additional 64 ms delay by clearing the PWRTE bit. At this time, the VDD voltage level is high enough to operate the MCU functions only; all other device functionality is not operational. This is independent of the value of VIN, which is typically VDD + VDROPOUT. During power-down with BOR enabled, the MCU operation will be held in Reset when VDD falls below the VBOR threshold. With BOR disabled or while operating in Sleep mode, the POR will hold the part in Reset when VDD falls below the VPOR threshold. FIGURE 14-3: BROWN-OUT SITUATIONS VDD Internal Reset VBOR 64 ms (1) VDD Internal Reset VBOR < 64 ms 64 ms (1) VDD VBOR Internal Reset 64 ms (1) Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.  2015-2020 Microchip Technology Inc. DS20005479D-page 99 MCP19116/7 14.4 Power-Up Timer (PWRT) The Power-Up Timer provides a fixed 64 ms (nominal) time-out on power-up only, from POR Reset. The Power-Up Timer operates from an internal RC oscillator. The chip is kept in Reset as long as PWRT is active. The PWRT delay allows the VDD to rise to an acceptable level. A bit (PWRTE) in the CONFIG register can disable (if set) or enable (if cleared or programmed) the Power-Up Timer. The Power-Up Timer delay varies from chip to chip due to: • VDD variation • Temperature variation • Process variation Note: Voltage spikes below AGND at the MCLR pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a “low” level to the MCLR pin, rather than pulling this pin directly to AGND. The Power-Up Timer optionally delays device execution after a POR event. This timer is typically used to allow VDD to stabilize before allowing the device to start running. The Power-Up Timer is controlled by the PWRTE bit in the CONFIG register. FIGURE 14-4: 14.5 Watchdog Timer (WDT) Reset The Watchdog Timer generates a Reset if the firmware does not issue a CLRWDT instruction within the time-out period. The TO and PD bits in the STATUS register are changed to indicate the WDT Reset. Refer to Section 17.0 “Watchdog Timer (WDT)” for more information. 14.6 Start-Up Sequence Upon the release of a POR, the following must occur before the device begins executing: • Power-Up Timer runs to completion (if enabled) • Oscillator start-up timer runs to completion • MCLR must be released (if enabled) The total time out will vary based on PWRTE bit status. For example, with PWRTE bit erased (PWRT disabled), there will be no time out at all. Figures 14-4, 14-5 and 14-6 represent time-out sequences. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Then, bringing MCLR high begins execution immediately (refer to Figure 14-5). This is useful for testing purposes or to synchronize more than one MCP19116/7 device operating in parallel. 14.6.1 POWER CONTROL (PCON) REGISTER The Power Control (PCON) register (address 8Eh) has two Status bits to indicate what type of Reset occurred last. TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-Out TIOSCST OST Time-Out Internal Reset DS20005479D-page 100  2015-2020 Microchip Technology Inc. MCP19116/7 FIGURE 14-5: TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE 2 VDD MCLR Internal POR TPWRT PWRT Time-Out TIOSCST OST Time-Out Internal Reset FIGURE 14-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH VDD) VDD MCLR Internal POR TPWRT PWRT Time-Out TIOSCST OST Time-Out Internal Reset 14.7 Determining the Cause of a Reset Upon any Reset, multiple bits in the STATUS and PCON register are updated to indicate the cause of the Reset. Tables 14-3 and 14-4 show the Reset conditions of these registers.  2015-2020 Microchip Technology Inc. TABLE 14-3: RESET STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD Condition 0 x 1 1 Power-on Reset u 0 1 1 Brown-out Reset u u 0 u WDT Reset u u 0 0 WDT Wake-Up from Sleep u u 1 0 Interrupt Wake-Up from Sleep u u u u MCLR Reset during normal operation u u 1 0 MCLR Reset during Sleep 0 u 0 x Not allowed. TO is set on POR. 0 u x 0 Not allowed. PD is set on POR. DS20005479D-page 101 MCP19116/7 RESET CONDITION FOR SPECIAL REGISTERS (1) TABLE 14-4: Program Counter STATUS Register PCON Register Power-on Reset 0000h 0001 1xxx ---- --0u Brown-out Reset 0000 0001 1xxx ---- --u0 MCLR Reset during normal operation 0000h 000u uuuu ---- --uu MCLR Reset during Sleep 0000h 0001 0uuu ---- --uu WDT Reset 0000h 0000 uuuu ---- --uu PC + 1 uuu0 0uuu ---- --uu PC + 1 (2) uuu1 0uuu ---- --uu Condition WDT Wake-Up from Sleep Interrupt Wake-Up from Sleep Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’. Note 1: If a Status bit is not implemented, that bit will be read as ‘0’. 2: When the wake-up is due to an interrupt and Global Enable bit (GIE) is set, the return address is pushed on the stack and PC is loaded with the interrupt vector (0004h) after execution of PC + 1. 14.8 Power Control (PCON) Register The Power Control (PCON) register contains flag bits to differentiate between a: • Power-on Reset (POR) • Brown-out Reset (BOR) The PCON register bits are shown in Register 14-1. REGISTER 14-1: PCON: POWER CONTROL REGISTER R-0 U-0 U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 ADC_REFR — — — VDDFLAG VDDOK POR BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ADC_REFR: VDD > AVDD Status bit that shows if the ADC Reference is present at the ADC 1 = VDD is greater than AVDD and the ADC Reference is present at the ADC 0 = VDD is not greater than AVDD and the ADC Reference is not present at the ADC bit 6-4 Unimplemented: Read as '0' bit 3 VDDFLAG: VDDOK history status bit 1 = VDD LDO has not dropped out of regulation (VDDOK has not gone low since this bit was last set) 0 = VDD LDO has dropped out of regulation at some time since this bit was last set. Must be set by firmware when VDDOK=1 bit 2 VDDOK: VDD Status bit 1 = VDD is in regulation 0 = VDD is not in regulation bit 1 POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) DS20005479D-page 102  2015-2020 Microchip Technology Inc. MCP19116/7 TABLE 14-5: Name PCON STATUS SUMMARY OF REGISTERS ASSOCIATED WITH RESETS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page — — — — — — POR BOR 102 IPR RP1 RP0 TO PD Z DC C 83 Legend: — = unimplemented bit, read as ‘0’. Shaded cells are not used by Resets. Note: Other (non power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.  2015-2020 Microchip Technology Inc. DS20005479D-page 103 MCP19116/7 NOTES: DS20005479D-page 104  2015-2020 Microchip Technology Inc. MCP19116/7 15.0 INTERRUPTS The MCP19116/7 devices have multiple sources of interrupt: • • • • • • • • • • • • • • • • • External Interrupt (INT pin) Interrupt-on-Change (IOC) Interrupts Timer0 Overflow Interrupt Timer1 Overflow Interrupt Timer2 Match Interrupt ADC Interrupt System Input Undervoltage Error System Input Overvoltage Error SSP BCL USART TX Interrupt USART RC Interrupt Desaturation Detection Gate Drive UVLO Capture/Compare 1 Capture/Compare 2 Overtemperature The Interrupt Control (INTCON) register and the Peripheral Interrupt Request (PIRx) registers record individual interrupt requests in flag bits. The INTCON register also has individual and global interrupt enable bits. The Global Interrupt Enable bit (GIE) in the INTCON register enables (if set) all unmasked interrupts or disables (if cleared) all interrupts. Individual interrupts can be disabled through their corresponding enable bits in the INTCON register and PIEx registers. GIE is cleared on Reset. When an interrupt is serviced, the following actions occur automatically: • The GIE is cleared to disable any further interrupt • The return address is pushed onto the stack • The PC is loaded with 0004h The firmware within the Interrupt Service Routine (ISR) should determine the source of the interrupt by polling the interrupt flag bits. The interrupt flag bits must be cleared before exiting the ISR to avoid repeated interrupts. Because the GIE bit is cleared, any interrupt that occurs while executing the ISR is recorded through its interrupt flag but does not cause the processor to redirect to the interrupt vector.  2015-2020 Microchip Technology Inc. Note 1: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit. 2: When an instruction that clears the GIE bit is executed, any interrupts that were pending for execution in the next cycle are ignored. The interrupts which were ignored are still pending to be serviced when the GIE bit is set again. The RETFIE instruction exits the ISR by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the GIE bit. For additional information on a specific interrupt operation, refer to its peripheral chapter. 15.1 Interrupt Latency For external interrupt events, such as the INT pin or PORTGPx change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends upon when the interrupt event occurs (refer to Figure 15-2). The latency is the same for one- or two-cycle instructions. 15.2 GPA2/INT Interrupt The external interrupt on the GPA2/INT pin is edge-triggered, either on the rising edge if the INTEDG bit in the OPTION_REG register is set, or the falling edge if the INTEDG bit is clear. When a valid edge appears on the GPA2/INT pin, the INTF bit in the INTCON register is set. This interrupt can be disabled by clearing the INTE control bit in the INTCON register. The INTF bit must be cleared by software in the Interrupt Service Routine before re-enabling this interrupt. The GPA2/INT interrupt can wake up the processor from Sleep, if the INTE bit was set prior to going into Sleep. Refer to Section 16.0, Power-Down Mode (Sleep) for details on Sleep and Section 16.1 “Wake-Up from Sleep” for timing of wake-up from Sleep through GPA2/INT interrupt. Note: The ANSEL register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’ and cannot generate an interrupt. DS20005479D-page 105 MCP19116/7 FIGURE 15-1: INTERRUPT LOGIC CDSIF CDSIE OVIF OVIE OVLOIF OVLOIE UVLOIF UVLOIE DRUVIF DRUVIE OTIF OTIE ADIF ADIE TOIF TOIE Wake-up (if in Sleep mode) INTF INTE Interrupt to CPU IOCF IOCE BCLIF BCLIE SSPIF SSPIE CC1IF CC1IE CC2IF CC2IE PEIF PEIE GIE TMR2,F TMR2,E TMR1IF TMR1IE TXIF TXIE RCIF RCIE FIGURE 15-2: INT PIN INTERRUPT TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CLKIN CLKOUT (1) (2) INT pin (3) INTF flag (INTCON reg.) (3) Interrupt Latency (5) (4) GIE bit (INTCON reg.) INSTRUCTION FLOW PC PC Instruction Fetched Instruction Executed Note 1: Inst (PC) Inst (PC – 1) PC + 1 Inst (PC + 1) Inst (PC) PC + 1 — Dummy Cycle 0004h 0005h Inst (0004h) Inst (0005h) Dummy Cycle Inst (0004h) CLKOUT is available only in INTOSC and RC Oscillator modes. 2: For minimum width of INT pulse, refer to AC specifications in Section 5.0, Digital Electrical Characteristics. 3: INTF flag is sampled here (every Q1). 4: INTF is enabled to be set any time during the Q4-Q1 cycles. 5: Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single-cycle or a two-cycle instruction. DS20005479D-page 106  2015-2020 Microchip Technology Inc. MCP19116/7 15.3 Interrupt Control Registers 15.3.1 Note: INTCON REGISTER The INTCON register is a readable and writable register that contains the various enable and flag bits for the TMR0 register overflow, interrupt-on-change and external INT pin interrupts. REGISTER 15-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit (GIE) in the INTCON register. The user’s software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE IOCE T0IF INTF IOCF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GIE: Global Interrupt Enable bit 1 = Enables all unmasked interrupts 0 = Disables all interrupts bit 6 PEIE: Peripheral Interrupt Enable bit 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts bit 5 T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4 INTE: INT External Interrupt Enable bit 1 = Enables the INT external interrupt 0 = Disables the INT external interrupt bit 3 IOCE: Interrupt-on-Change Enable bit (1) 1 = Enables the interrupt-on-change 0 = Disables the interrupt-on-change bit 2 T0IF: TMR0 Overflow Interrupt Flag bit (2) 1 = TMR0 register overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1 INTF: External Interrupt Flag bit 1 = The external interrupt occurred (must be cleared in software) 0 = The external interrupt did not occur bit 0 IOCF: Interrupt-on-Change Interrupt Flag bit 1 = When at least one of the interrupt-on-change pins changed state 0 = None of the interrupt-on-change pins changed state Note 1: 2: x = Bit is unknown IOCx registers must also be enabled. T0IF bit is set when TMR0 rolls over. TMR0 is unchanged on Reset and should be initialized before clearing T0IF bit.  2015-2020 Microchip Technology Inc. DS20005479D-page 107 MCP19116/7 15.3.1.1 PIE1 Register The PIE1 register contains the Peripheral Interrupt Enable bits, as shown in Register 15-2. Note 1: Bit PEIE in the INTCON register must be set to enable any peripheral interrupt. REGISTER 15-2: PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXIE RCIE BCLIE SSPIE CC2IE CC1IE TMR2IE TMR1IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 6 RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 5 BCLIE: MSSP Bus Collision Interrupt Enable bit 1 = Enables the MSSP Bus Collision Interrupt 0 = Disables the MSSP Bus Collision Interrupt bit 4 SSPIE: Synchronous Serial Port (MSSP) Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt bit 3 CC2IE: Capture2/Compare2 Interrupt Enable bit 1 = Enables the Capture2/Compare2 interrupt 0 = Disables the Capture2/Compare2 interrupt bit 2 CC1IE: Capture1/Compare1 Interrupt Enable bit 1 = Enables the Capture1/Compare1 interrupt 0 = Disables the Capture1/Compare1 interrupt bit 1 TMR2IE: Timer2 Interrupt Enable 1 = Enables the Timer2 interrupt 0 = Disables the Timer2 interrupt bit 0 TMR1IE: Timer1 Interrupt Enable 1 = Enables the Timer1 interrupt 0 = Disables the Timer1 interrupt DS20005479D-page 108 x = Bit is unknown  2015-2020 Microchip Technology Inc. MCP19116/7 15.3.1.2 PIE2 Register The PIE2 register contains the Peripheral Interrupt Enable bits, as shown in Register 15-3. Note 1: Bit PEIE in the INTCON register must be set to enable any peripheral interrupt. REGISTER 15-3: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CDSIE ADIE — OTIE OVIE DRUVIE OVLOIE UVLOIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CDSIE: Desaturation Detection Interrupt Enable bit 1 = Enables the DESAT Detect interrupt 0 = Disables the DESAT Detect interrupt bit 6 ADIE: ADC Interrupt Enable bit 1 = Enables the ADC interrupt 0 = Disables the ADC interrupt bit 5 Unimplemented: Read as ‘0’ bit 4 OTIE: Overtemperature Interrupt Enable bit 1 = Enables overtemperature interrupt 0 = Disables overtemperature interrupt bit 3 OVIE: VOUT Overvoltage Interrupt Enable bit 1 = Enables the OV interrupt 0 = Disables the OV interrupt bit 2 DRUVIE: Gate Drive Undervoltage Lockout Interrupt Enable bit 1 = Enables Gate Drive UVLO interrupt 0 = Disables Gate Drive UVLO interrupt bit 1 OVLOIE: VIN Overvoltage Lockout Interrupt Enable bit 1 = Enables OVLO interrupt 0 = Disables OVLO interrupt bit 0 UVLOIE: VIN Undervoltage Lockout Interrupt Enable bit 1 = Enables UVLO interrupt 0 = Disables UVLO interrupt  2015-2020 Microchip Technology Inc. x = Bit is unknown DS20005479D-page 109 MCP19116/7 15.3.1.3 PIR1 Register Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit (GIE) in the INTCON register. The user’s software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR1 register contains the Peripheral Interrupt Flag bits, as shown in Register 15-4. REGISTER 15-4: PIR1: PERIPHERAL INTERRUPT FLAG REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXIF RCIF BCLIF SSPIF CC2IF CC1IF TMR2IF TMR1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART receive buffer is not full bit 6 RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is not full bit 5 BCLIF: MSSP Bus Collision Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 4 SSPIF: Synchronous Serial Port (MSSP) Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending bit 3 CC2IF: Capture2/Compare2 Interrupt Flag bit 1 = Capture or Compare has occurred 0 = Capture or Compare has not occurred bit 2 CC1IF: Capture1/Compare1 Interrupt Flag bit 1 = Capture or Compare has occurred 0 = Capture or Compare has not occurred bit 1 TMR2IF: Timer2 to PR2 Match Interrupt Flag 1 = Timer2 to PR2 match occurred (must be cleared in software) 0 = Timer2 to PR2 match did not occur bit 0 TMR1IF: Timer1 Interrupt Flag 1 = Timer1 rolled over (must be cleared in software) 0 = Timer1 did not roll over DS20005479D-page 110  2015-2020 Microchip Technology Inc. MCP19116/7 15.3.1.4 PIR2 Register Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit (GIE) in the INTCON register. The user’s software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. The PIR2 register contains the Peripheral Interrupt Flag bits, as shown in Register 15-5. REGISTER 15-5: PIR2: PERIPHERAL INTERRUPT FLAG REGISTER 2 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CDSIF ADIF — OTIF OVIF DRUVIF OVLOIF UVLOIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 CDSIF: DESAT Detect comparator module interrupt flag bit 1 = An interrupt is pending 0 = An interrupt is not pending bit 6 ADIF: ADC Interrupt Flag bit 1 = ADC conversion complete 0 = ADC conversion has not completed or has not been started bit 5 Unimplemented: Read as ‘0’ bit 4 OTIF: Overtemperature Interrupt Flag bit 1 = Overtemperature event has occurred 0 = Overtemperature event has not occurred bit 3 OVIF: Overvoltage Interrupt Flag bit With OVINTP bit set: 1 = A VOUT Not Overvoltage-to-Overvoltage edge has been detected 0 = A VOUT Not Overvoltage-to-Overvoltage edge has not been detected With OVINTN bit set: 1 = A VOUT Overvoltage-to-Not Overvoltage edge has been detected 0 = A VOUT Overvoltage-to-Not Overvoltage edge has not been detected bit 2 DRUVIF: Gate Drive Undervoltage Lockout Interrupt Flag bit 1 = Gate Drive Undervoltage Lockout has occurred 0 = Gate Drive Undervoltage Lockout has not occurred bit 1 OVLOIF: VIN Overvoltage Lockout Interrupt Flag bit With OVLOINTP bit set: 1 = A VIN Not Overvoltage-to-VIN Overvoltage edge has been detected 0 = A VIN Not Overvoltage-to-VIN Overvoltage edge has not been detected With OVLOINTN bit set: 1 = A VIN Overvoltage-to-VIN Not Overvoltage edge has been detected 0 = A VIN Overvoltage-to-VIN Not Overvoltage edge has not been detected bit 0 UVLOIF: VIN Undervoltage Lockout Interrupt Flag bit With UVLOINTP bit set: 1 = A VIN Not Undervoltage-to-VIN Undervoltage edge has been detected 0 = A VIN Not Undervoltage-to-VIN Undervoltage edge has not been detected With UVLOINTN bit set: 1 = A VIN Undervoltage-to-VIN Not Undervoltage edge has been detected 0 = A VIN Undervoltage-to-VIN Not Undervoltage edge has not been detected  2015-2020 Microchip Technology Inc. DS20005479D-page 111 MCP19116/7 TABLE 15-1: SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 107 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 90 PIE1 TXIE RCIE BCLIE SSPIE CC2IE CC1IE TMR2IE TMR1IE 108 PIE2 CDSIE ADIE — OTIE OVIE DRUVIE OVLOIE UVLOIE 109 PIR1 TXIF RCIF BCLIF SSPIF — — TMR2IF TMR1IF 110 PIR2 CDSIF ADIF — OTIF OVIF DRUVIF OVLOIF UVLOIF 111 Name INTCON OPTION_REG Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by interrupts. DS20005479D-page 112  2015-2020 Microchip Technology Inc. MCP19116/7 15.4 Context Saving During Interrupts During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W and STATUS registers). This must be implemented in software. Temporary holding registers W_TEMP and STATUS_TEMP should be placed in the last 16 bytes of GPR. These 16 locations are common to all banks and do not require banking. This makes context save and restore operations simpler. The code shown in Example 15-1 can be used to: • • • • • Store the W register Store the STATUS register Execute the ISR code Restore the Status (and Bank Select Bit) register Restore the W register Note: The MCP19116/7 devices do not require saving the PCLATH. However, if computed GOTOs are used in both the ISR and the main code, the PCLATH must be saved and restored in the ISR. EXAMPLE 15-1: MOVWF SWAPF SAVING STATUS AND W REGISTERS IN RAM W_TEMP STATUS,W MOVWF STATUS_TEMP : :(ISR) : SWAPF STATUS_TEMP,W MOVWF SWAPF SWAPF STATUS W_TEMP,F W_TEMP,W  2015-2020 Microchip Technology Inc. ;Copy W to TEMP ;Swap status to ;Swaps are used ;Save status to register be saved into W because they do not affect the status bits bank zero STATUS_TEMP register ;Insert user code here ;Swap STATUS_TEMP register into W ;(sets bank to original state) ;Move W into STATUS register ;Swap W_TEMP ;Swap W_TEMP into W DS20005479D-page 113 MCP19116/7 NOTES: DS20005479D-page 114  2015-2020 Microchip Technology Inc. MCP19116/7 16.0 POWER-DOWN MODE (SLEEP) 16.1 Wake-Up from Sleep The Power-Down mode is entered by executing a SLEEP instruction. The device can wake up from Sleep through one of the following events: Upon entering Sleep mode, the following conditions occur: 1. 2. 3. 4. 5. 1. 2. 3. 4. 5. 6. 7. 8. 9. WDT is cleared but keeps running, if enabled for operation during Sleep. PD bit in the STATUS register is cleared. TO bit in the STATUS register is set. CPU clock is disabled. The ADC is inoperable due to the absence of the 4V LDO power (AVDD) when the ADC reference is set to AVDD. I/O ports maintain the status they had before SLEEP was executed (driving high, low or high-impedance). Resets other than WDT and BOR are not affected by Sleep mode. Analog Circuit power (AVDD) is removed during Sleep mode. To minimize sleep current the ADC Reference must be set to AVDD (default). Refer to individual chapters for more details on peripheral operation during Sleep. To minimize current consumption, the following conditions should be considered: I/O pins should not be floating (1) External circuitry sinking current from I/O pins Internal circuitry sourcing current from I/O pins Current draw from pins with internal weak pull-ups Modules using Timer1 oscillator ADC Reference should be set to the default condition (AVDD). • VDR will draw a small amount of current from VDD if VDD is connected to VDR externally. To achieve minimum Sleep current, disconnect VDR from VDD during Sleep. • • • • • • External Reset input on MCLR pin, if enabled POR Reset Watchdog Timer, if enabled Any external interrupt Interrupts by peripherals capable of running during Sleep (see individual peripheral for more information) The first two events will cause a device reset. The last three events are considered a continuation of program execution. To determine whether a device reset or wake-up event occurred, refer to Section 14.7 “Determining the Cause of a Reset”. The following peripheral interrupts can wake the device from Sleep: 1. 2. Interrupt-on-change External Interrupt from INT pin When the SLEEP instruction is being executed, the next instruction (PC + 1) is prefetched. For the device to wake up through an interrupt event, the corresponding interrupt enable bit must be enabled. Wake-up will occur regardless of the state of the GIE bit. If the GIE bit is disabled, the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is enabled, the device executes the instruction after the SLEEP instruction and will then call the Interrupt Service Routine. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NO OPERATION (NOP) after the SLEEP instruction. The WDT is cleared when the device wakes up from Sleep, regardless of the source of wake-up. Note 1: It is recommended that the I/O pins that are high-impedance inputs be pulled to VDD or GND externally to avoid switching currents caused by floating inputs. The SLEEP instruction removes power from the analog circuitry. AVDD is shut down to minimize current draw in Sleep mode and to maintain a shutdown current of 50 µA typical. The 5V LDO (VDD) voltage drops to 2.9V minimum in Sleep mode. External current draw from the 5V LDO (VDD) should be limited to less than 1 mA. Loads drawing more than 1 mA externally during Sleep mode risk loading down the VDD voltage and tripping POR. A POR event during Sleep mode will wake the device from Sleep. The enable state of the analog circuitry does not change with the execution of the SLEEP instruction.  2015-2020 Microchip Technology Inc. DS20005479D-page 115 MCP19116/7 16.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction: - SLEEP instruction will execute as a NOP - WDT and WDT prescaler are not cleared - TO bit in the STATUS register are not set - PD bit in the STATUS register are not cleared FIGURE 16-1: • If the interrupt occurs during or after the execution of a SLEEP instruction: - SLEEP instruction is completely executed - Device immediately wakes up from Sleep - WDT and WDT prescaler are cleared - TO bit in the STATUS register is set - PD bit in the STATUS register is cleared Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC TOST Interrupt Latency (1) Interrupt flag GIE bit (INTCON reg.) Processor in Sleep Instruction Flow PC Instruction Fetched Instruction Executed Note 1: PC Inst(PC) = Sleep Inst(PC - 1) INTCON PC + 2 PC + 2 Inst(PC + 2) Sleep Inst(PC + 1) PC + 2 Dummy Cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line. TABLE 16-1: Name PC + 1 Inst(PC + 1) SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 107 IOCA IOCA7 IOCA6 IOCA5 — IOCA3 IOCA2 IOCA1 IOCA0 134 IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — IOCB1 IOCB0 134 PIE1 TXIE RCIE BCLIE SSPIE CC2IE CC1IE TMR2IE TMR1IE 108 PIE2 CDSIE ADIE — OTIE OVIE DRUVIE OVLOIE UVLOIE 109 PIR1 TXIF RCIF BCLIF SSPIF CC2IF CC1IF TMR2IF TMR1IF 110 PIR2 CDSIF ADIF — OTIF OVIF DRUVIF OVLOIF UVLOIF 111 IRP RP1 RP0 TO PD Z DC C 83 STATUS Legend: — = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode. DS20005479D-page 116  2015-2020 Microchip Technology Inc. MCP19116/7 17.0 WATCHDOG TIMER (WDT) 17.2 The WDT has a nominal time-out period of 18 ms (with no prescaler). The time-out periods vary with temperature, VDD and process variations from part to part (refer to Table 5-3). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT under software control by writing to the OPTION_REG register. Thus, time-out periods up to 2.3 seconds can be realized. The Watchdog Timer is a free running timer. The WDT is enabled by setting the WDTE bit in the CONFIG register (default setting). During normal operation, a WDT time out generates a device reset. If the device is in Sleep mode, a WDT time out causes the device to wake up and continue with normal operation. The WDT can be permanently disabled by clearing the WDTE bit in the CONFIG register. Refer to Section 12.1 “Configuration Word” for more information. 17.1 WDT Period The CLRWDT and SLEEP instructions clear the WDT and the prescaler, if assigned to the WDT, and prevent it from timing out and generating a device reset. The TO bit in the STATUS register will be cleared upon a Watchdog Timer time out. Watchdog Timer (WDT) Operation During normal operation, a WDT time out generates a device reset. If the device is in Sleep mode, a WDT time out causes the device to wake-up and continue with normal operation; this is known as a WDT wake-up. The WDT can be permanently disabled by clearing the WDTE configuration bit. 17.3 WDT Programming Considerations Under worst-case conditions (i.e., VDD = Minimum, Temperature = Maximum, Maximum WDT prescaler), it may take several seconds before a WDT time out occurs. The postscaler assignment is fully under software control and can be changed during program execution. FIGURE 17-1: WATCHDOG TIMER WITH SHARED PRESCALE BLOCK DIAGRAM FOSC/4 Data Bus 0 8 1 Sync 2 TCY 1 T0CKI pin T0SE T0CS 0 0 Set Flag bit T0IF on Overflow PSA 8-Bit Prescaler TMR0 1 PSA 8 PS Watchdog Timer 1 0 PSA WDT Time-Out WDTE Note 1: T0SE, T0CS, PSA, PS are bits in the OPTION_REG register. 2: WDTE bit is in the CONFIG register.  2015-2020 Microchip Technology Inc. DS20005479D-page 117 MCP19116/7 TABLE 17-1: WDT STATUS Conditions WDT WDTE = 0 CLRWDT Command Cleared Exit Sleep TABLE 17-2: SUMMARY OF REGISTERS ASSOCIATED WITH WATCHDOG TIMER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page OPTION_REG RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 90 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: Refer to Register 12-1 for operation of all the bits in the CONFIG register. TABLE 17-3: Name CONFIG SUMMARY OF CONFIGURATION WORD ASSOCIATED WITH WATCHDOG TIMER Bits Bit -/7 Bit -/6 Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 Bit 9/1 Bit 8/0 Register on page 13:8 — — DBGEN — WRT1 WRT0 — BOREN 93 7:0 — CP MCLRE PWRTE WDTE — — — Legend: — = unimplemented location, read as ‘1’. Shaded cells are not used by Watchdog Timer. DS20005479D-page 118  2015-2020 Microchip Technology Inc. MCP19116/7 18.0 FLASH PROGRAM MEMORY CONTROL The Flash program memory is readable and writable during normal operation (full VIN range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers (refer to Registers 18-1 to 18-5). There are six SFRs used to read and write this memory: • • • • • • PMCON1 PMCON2 PMDATL PMDATH PMADRL PMADRH When interfacing the program memory block, the PMDATL and PMDATH registers form a two-byte word which holds the 14-bit data for read/write, while the PMADRL and PMADRH registers form a two-byte word, which holds the 13-bit address of the FLASH location being accessed. These devices have 8000 words of program Flash with an address range from 0000h to 1FFFh. The program memory allows single-word read and a four-word write. A four-word write automatically erases the row of the location and writes the new data (erase before write). The write time is controlled by an on-chip timer. The write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. 18.1 PMADRH and PMADRL Registers The PMADRH and PMADRL registers can address up to a maximum of 8000 words of program memory. When selecting a program address value, the Most Significant Byte (MSB) of the address is written to the PMADRH register and the Least Significant Byte (LSB) is written to the PMADRL register. 18.2 PMCON1 and PMCON2 Registers The PMCON1 register is the control register for the data program memory accesses. Control bits RD and WR initiate read and write, respectively. In software, these bits can only be set, not cleared. They are cleared in hardware at completion of the read or write operation. The inability to clear the WR bit in software prevents the accidental premature termination of a write operation. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The CALSEL bit allows the user to read locations in test memory in case there are calibration bits stored in the calibration word locations that need to be transferred to SFR trim registers. The CALSEL bit is only for reads. If a write operation is attempted with CALSEL = 1, no write occurs. PMCON2 is not a physical register. Reading PMCON2 will read all '0's. The PMCON2 register is used exclusively in the flash memory write sequence. When the device is code-protected, the CPU may continue to read and write the Flash program memory. Depending on the settings of the Flash Program Memory Enable (WRT) bits, the device may or may not be able to write certain blocks of the program memory; however, reads of the program memory are allowed. When the Flash Program Memory Code Protection (CP) bit is enabled, the program memory is code-protected and the device programmer (ICSP) cannot access data or program memory.  2015-2020 Microchip Technology Inc. DS20005479D-page 119 MCP19116/7 18.3 Flash Program Memory Control Registers REGISTER 18-1: R/W-0 PMDATL: PROGRAM MEMORY DATA LOW BYTE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMDATL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown PMDATL: 8 Least Significant Data bits to write or read from program memory REGISTER 18-2: R/W-0 PMADRL: PROGRAM MEMORY ADDRESS LOW BYTE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMADRL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown PMADRL: 8 Least Significant Address bits for Program Memory Read/Write Operation REGISTER 18-3: PMDATH: PROGRAM MEMORY DATA HIGH BYTE REGISTER U-0 U-0 — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMDATH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 PMDATH: 6 Most Significant Data bits from program memory DS20005479D-page 120  2015-2020 Microchip Technology Inc. MCP19116/7 REGISTER 18-4: PMADRH: PROGRAM MEMORY ADDRESS HIGH BYTE REGISTER U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 PMADRH bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 PMADRH: 4 Most Significant Address bits or High bits for program memory reads REGISTER 18-5: PMCON1: PROGRAM MEMORY CONTROL REGISTER 1 U-1 R/W-0 U-0 U-0 U-0 R/W-0 R/S-0 R/S-0 — CALSEL — — — WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown S = Bit can only be set bit 7 Unimplemented: Read as '1' bit 6 CALSEL: Program Memory calibration space select bit 1 = Select test memory area for reads only (for loading calibration trim registers) 0 = Select user area for reads bit 5-3 Unimplemented: Read as '0' bit 2 WREN: Program Memory Write Enable bit 1 = Allows write cycles 0 = Inhibits write to the EEPROM bit 1 WR: Write Control bit 1 = Initiates a write cycle to program memory. (The bit is cleared by hardware when write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle to the Flash memory is complete bit 0 RD: Read Control bit 1 = Initiates a program memory read. (The read takes one cycle. The RD is cleared in hardware; the RD bit can only be set (not cleared) in software.) 0 = Does not initiate a Flash memory read  2015-2020 Microchip Technology Inc. DS20005479D-page 121 MCP19116/7 18.3.1 READING THE FLASH PROGRAM MEMORY To read a program memory location, the user must write two bytes of the address to the PMADRL and PMADRH registers, and then set control bit RD (bit 0 in the PMCON1register). Once the read control bit is set, the Program Memory Flash controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the BSF PMCON1,RD instruction to be ignored. The data is available, in the very next cycle, in the PMDATL and PMDATH registers; it can be read as two bytes in the following instructions. PMDATL and PMDATH registers will hold this value until another read or until it is written to by the user (during a write operation). EXAMPLE 18-1: FLASH PROGRAM READ BANKSELPM_ADR; Change STATUS bits RP1:0 to select bank with PMADR MOVLWMS_PROG_PM_ADDR; MOVWFPMADRH; MS Byte of Program Address to read MOVLWLS_PROG_PM_ADDR; MOVWFPMADRL; LS Byte of Program Address to read BANKSELPMCON1; Bank to containing PMCON1 BSF PMCON1, RD; EE Read NOP ; First instruction after BSF PMCON1,RD executes normally NOP ; Any instructions here are ignored as program ; memory is read in second cycle after BSF PMCON1,RD ; BANKSELPMDATL; Bank to containing PMADRL MOVFPMDATL, W; W = LS Byte of Program PMDATL MOVFPMDATH, W; W = MS Byte of Program PMDATL FIGURE 18-1: Q1 Flash ADDR FLASH PROGRAM MEMORY READ CYCLE EXECUTION – NORMAL MODE Q2 Q3 Q4 PC Flash DATA Q1 Q2 Q4 PC + 1 INSTR (PC) INSTR (PC - 1) Executed here Q3 Q1 Q2 Q3 Q4 PMADRH,PMADRL INSTR (PC + 1) BSF PMCON1,RD Executed here Q1 Q2 Q3 Q1 Q2 Q3 Q4 PC + 4 PC+3 PC +3 PMDATH,PMDATL INSTR (PC + 1) Executed here Q4 INSTR (PC + 3) NOP Executed here Q1 Q2 Q3 Q4 PC + 5 INSTR (PC + 4) INSTR (PC + 3) Executed here INSTR (PC + 4) Executed here RD bit PMDATH PMDATL Register EERHLT DS20005479D-page 122  2015-2020 Microchip Technology Inc. MCP19116/7 18.3.2 WRITING TO THE FLASH PROGRAM MEMORY A word of the Flash program memory may only be written to if the word is in an unprotected segment of memory, as defined in Section 12.1 “Configuration Word” (bits ). Note: The write-protect bits are used to protect the user’s program from modification by the user’s code. They have no effect when programming is performed by ICSP. The code-protect bits, when programmed for code protection, will prevent the program memory from being written via the ICSP interface. Flash program memory must be written in eight-word blocks. Refer to Figures 18-2 and 18-3 for more details. A block consists of eight words with sequential addresses, with a lower boundary defined by an address, where PMADRL = 00. All block writes to program memory are done as 16-word erase by eight-word write operations. The write operation is edge-aligned and cannot occur across boundaries. To write program data, the WREN bit must first be loaded into the buffer registers (refer to Figure 18-2). This is accomplished by first writing the destination address to PMADRL and PMADRH and then writing the data to PMDATL and PMDATH. After the address and data have been set, the following sequence of events must be executed: 1. 2. Write 55h, then AAh, to PMCON2 (Flash programming sequence) Set the WR control bit in the PMCON1 register All eight buffer register locations should be written to with correct data. If less than eight words are being written to in the block of eight words, a read from the program memory location(s) not being written to must be performed. This takes the data from the program location(s) not being written and loads it into the PMDATL and PMDATH registers. Then the sequence of events to transfer data to the buffer registers must be executed. To transfer data from the buffer registers to the program memory, the PMADRL and PMADRH must point to the last location in the eight-word block (PMADRL = 111). Then the following sequence of events must be executed: 1. 2. Write 55h, then AAh, to PMCON2 (Flash programming sequence). Set control bit WR in the PMCON1 register to begin the write operation.  2015-2020 Microchip Technology Inc. The user must follow the same specific sequence to initiate the write for each word in the program block, writing each program word in sequence (000, 001, 010, 011). When the write is performed on the last word (PMADRL = 111), a block of sixteen words is automatically erased and the content of the eight-word buffer registers are written into the program memory. After the BSF PMCON1,WR instruction, the processor requires two cycles to set up the erase/write operation. The user must place two NOP instructions after the WR bit is set. Since data is being written to buffer registers, the writing of the first three words of the block appears to occur immediately. The processor will halt internal operations for the typical 4 ms only during the cycle in which the erase takes place (i.e., the last word of the sixteen-word block erase). This is not Sleep mode, as the clocks and peripherals will continue to run. After the four-word write cycle, the processor will resume operation with the third instruction after the PMCON1 write instruction. The above sequence must be repeated for the higher 12 words. Note: An erase is only initiated for the write of four words just after a row boundary; or PMCON1 set with PMADRL = xxxx0011. Refer to Figure 18-2 for a block diagram of the buffer registers and the control signals for test mode. 18.3.3 PROTECTION AGAINST SPURIOUS WRITE There are conditions when the device should not write to the program memory. To protect against spurious writes, various mechanisms have been built in. On power-up, WREN is cleared. Also, the Power-Up Timer (72 ms duration) prevents program memory writes. The write initiate sequence and the WREN bit help prevent an accidental write during a power glitch or software malfunction. 18.3.4 OPERATION DURING CODE PROTECT When the device is code-protected, the CPU is able to read and write unscrambled data to the program memory. The test mode access is disabled. 18.3.5 OPERATION DURING WRITE PROTECT When the program memory is write-protected, the CPU can read and execute from the program memory. The portions of program memory that are write-protected cannot be modified by the CPU using the PMCON registers. The write protection has no effect in ICSP mode. DS20005479D-page 123 MCP19116/7 FIGURE 18-2: BLOCK WRITES TO 8000 FLASH PROGRAM MEMORY 7 5 0 0 7 If at new row sixteen words of Flash are erased, then four buffers are transferred to Flash automatically after this word is written. PMDATL PMDATH 6 8 14 14 First word of block to be written 14 PMADRL = 00 PMADRL = 10 PMADRL = 01 Buffer Register Buffer Register 14 PMADRL = 11 Buffer Register Buffer Register Program Memory FIGURE 18-3: FLASH PROGRAM MEMORY LONG WRITE CYCLE EXECUTION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 PMADRH, PMADRL PC + 1 Flash ADDR INSTR (PC) Flash DATA Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 INSTR (PC + 1) ignored read BSF PMCON1,WR INSTR (PC + 1) Executed here Executed here PMDATH, PMDATL Processor halted EE Write Time PC + 2 PC + 3 INSTR (PC+2) NOP Executed here PC + 4 INSTR (PC+3) (INSTR (PC + 2) NOP INSTR (PC + 3) Executed here Executed here Flash Memory Location WR bit PMWHLT DS20005479D-page 124  2015-2020 Microchip Technology Inc. MCP19116/7 19.0 I/O PORTS 19.1 In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has the registers for its operation. These registers are: • TRISGPx registers (data direction register) • PORTGPx registers (read the levels on the pins of the device) Some ports may have one or more of the following additional registers. These registers are: • ANSELx (analog select) • WPUGPx (weak pull-up) Ports with analog functions also have an ANSELx register, which can disable the digital input and save power. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in Figure 19-1. FIGURE 19-1: GENERIC I/O PORTGPX OPERATION Read LATx D TRISGPx Write PORTGPx Q CK PORTGPA is an 8-bit-wide, bidirectional port consisting of five CMOS I/Os, one open-drain I/O and one open-drain input-only pin (GPA4 is not available). The corresponding data direction register is TRISGPA. Setting a TRISGPA bit to 1 makes the corresponding PORTGPA pin an input (i.e., disable the output driver). Clearing a TRISGPA bit set to 0 makes the corresponding PORTGPA pin an output (i.e., enables output driver). The exception is GPA5, which is input only and its TRISGPA bit always reads as ‘1’. Example 19-1 shows how to initialize an I/O port. Reading the PORTGPA register reads the status of the pins, whereas writing to it writes to the PORT latch. All write operations are read-modify-write operations. The TRISGPA register controls the PORTGPA pin output drivers, even when they are being used as analog inputs. The user must ensure the bits in the TRISGPA register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. If the pin is configured for a digital output (either port or alternate function), the TRISGPA bit must be cleared in order for the pin to drive the signal, and a read reflects the state of the pin. 19.1.1 Write LATx VDD Data Register PORTGPA and TRISGPA Registers INTERRUPT-ON-CHANGE Each PORTGPA pin is individually configurable as an interrupt-on-change pin. Control bits IOCB and IOCB enable or disable the interrupt function for each pin. The interrupt-on-change feature is disabled on a Power-on Reset. Reference Section 20.0 “Interrupt-On-Change” for more information. Data Bus I/O pin Read PORTGPx To peripherals ANSELx EXAMPLE 19-1: ; ; ; ; AGND INITIALIZING PORTGPA This code example illustrates initializing the PORTGPA register. The other ports are initialized in the same manner. BANKSEL CLRF BANKSEL CLRF BANKSEL MOVLW MOVWF PORTGPA; PORTGPA;Init PORTA ANSELA; ANSELA;digital I/O TRISGPA; B'00011111';Set GPA as ;inputs TRISGPA;and set GPA as ;outputs  2015-2020 Microchip Technology Inc. 19.1.2 WEAK PULL-UPS PORTGPA and PORTGPA5 have an internal weak pull-up. PORTGPA do not have internal weak pull-ups. Individual control bits can enable or disable the internal weak pull-ups (refer to Register 19-3). The weak pull-up is automatically turned off when the port pin is configured as an output or as an alternate function. It is also automatically disabled on a Power-on Reset where the RAPU bit is set by default. The weak pull-up on GPA5 is automatically enabled when the pin is configured as MCLR and there is no software control in this case. However, when the pin is configured as an I/O there is software control of the weak pull-up just like all of the other pins. DS20005479D-page 125 MCP19116/7 19.1.3 ANSELA REGISTER The ANSELA register is used to configure the input mode of an I/O pin to analog. Setting the appropriate ANSELA bit high causes all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELA bits has no effect on digital output functions. A pin with TRISGPA cleared and ANSELx set still operates as a digital output, but the input mode is analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. Note: 19.1.4 The ANSELA bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by the user’s software. PORTGPA FUNCTIONS ALAND OUTPUT PRIORITIES Each PORTGPA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 19-1. For additional information, refer to the appropriate section in this data sheet. TABLE 19-1: PORTGPA OUTPUT PRIORITY Function Priority (1) Pin Name GPA0 GPA0 TEST_OUT GPA1 GPA1 CLKPIN GPA2 GPA2 T0CKI INT GPA3 GPA3 GPA5 GPA5 (open-drain, input only) MCLR TEST_EN GPA6 GPA6 CCD ICSPDAT GPA7 GPA7 (open-drain output, ST input) SCL Note 1: Output function priority listed from lowest to highest. Pin GPA7 in the PORTGPA register is a true open-drain pin with no connection back to VDD. When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. Analog input functions, such as ADC, are not shown in the priority lists. These inputs are active when the I/O pin is set for Analog mode using the ANSELA register. Digital output functions may control the pin when it is in Analog mode with the priority shown in Table 19-1. DS20005479D-page 126  2015-2020 Microchip Technology Inc. MCP19116/7 REGISTER 19-1: PORTGPA: PORTGPA REGISTER R/W-x R/W-x R-x U-0 R/W-x R/W-x R/W-x R/W-x GPA7 GPA6 GPA5 — GPA3 GPA2 GPA1 GPA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 GPA7: General Purpose Open-Drain I/O pin 1 = Port pin is > VIH 0 = Port pin is < VIL bit 6 GPA6: General Purpose I/O pin 1 = Port pin is > VIH 0 = Port pin is < VIL bit 5 GPA5/MCLR/TEST_EN5: General Purpose Open-Drain input pin bit 4 Unimplemented: Read as ‘0’ bit 3-0 GPA: General Purpose I/O pin 1 = Port pin is > VIH 0 = Port pin is < VIL REGISTER 19-2: R/W-1 TRISGPA: PORTGPA TRI-STATE REGISTER R/W-1 TRISA7 TRISA6 R-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 TRISA: PORTGPA Tri-State Control bits 1 = PORTGPA pin configured as an input (tri-stated) 0 = PORTGPA pin configured as an output bit 5 TRISA5: GPA5 Port Tri-State Control bit This bit is always ‘1’ as GPA5 is an input only bit 4 Unimplemented: Read as ‘0’ bit 3-0 TRISA: PORTGPA Tri-State Control bits 1 = PORTGPA pin configured as an input (tri-stated) 0 = PORTGPA pin configured as an output  2015-2020 Microchip Technology Inc. DS20005479D-page 127 MCP19116/7 WPUGPA: WEAK PULL-UP PORTGPA REGISTER (1) REGISTER 19-3: U-0 U-0 — — R/W-1 WPUA5 (2) U-0 R/W-1 R/W-1 R/W-1 R/W-1 — WPUA3 WPUA2 WPUA1 WPUA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5 WPUA5: Weak Pull-Up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 4 Unimplemented: Read as ‘0’ bit 3-0 WPUA: Weak Pull-Up Register bits 1 = Pull-up enabled 0 = Pull-up disabled Note 1: 2: The weak pull-up device is enabled only when the global RAPU bit is enabled, the pin is in input mode (TRISGPA = 1) and the individual WPUA bit is enabled (WPUA = 1), and the pin is not configured as an analog input. GPA5 weak pull-up is also enabled when the pin is configured as MCLR in the CONFIG register. REGISTER 19-4: ANSELA: ANALOG SELECT GPA REGISTER U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — ANSA3 ANSA2 ANSA1 ANSA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 ANSA: Analog Select GPA Register bits 1 = Analog input. Pin is assigned as analog input (1) 0 = Digital I/O. Pin is assigned to port or special function Note 1: Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and interrupt-on-change if available. The corresponding TRISA bit must be set to Input mode in order to allow external control of the voltage on the pin. DS20005479D-page 128  2015-2020 Microchip Technology Inc. MCP19116/7 TABLE 19-2: Name ANSELA OPTION_REG SUMMARY OF REGISTERS ASSOCIATED WITH PORTGPA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page — — — — ANSA3 ANSA2 ANSA1 ANSA0 128 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 90 PORTGPA GPA7 GPA6 GPA5 — GPA3 GPA2 GPA1 GPA0 127 TRISGPA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 127 WPUGPA — — WPUA5 — WPUA3 WPUA2 WPUA1 WPUA0 128 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used by PORTGPA. 19.2 PORTGPB and TRISGPB Registers Due to special function pin requirements, a limited number of the PORTGPB I/Os are utilized. On the 24-pin QFN MCP19116, GPB0 and GPB1 are implemented. GPB0 is an open-drain general purpose I/O and SDA pin. GPB1 is a general purpose I/O, analog input and VREF2 DAC output. The 28-pin QFN MCP19116 has four additional general purpose PORTGPB I/O pins. The corresponding data direction register is TRISGPB. Setting a TRISGPB bit to 1 will make the corresponding PORTGPB pin an input (i.e., disable the output driver). Clearing a TRISGPB bit to 0 will make the corresponding PORTGPB pin an output (i.e., enable the output driver). Example 19-1 shows how to initialize an I/O port. Some pins for PORTGPB are multiplexed with an alternate function for the peripheral or a clock function. In general, when a peripheral or clock function is enabled, that pin may not be used as a general purpose I/O pin. Reading the PORTGPB register reads the status of the pins, whereas writing to it writes to the PORT latch. All write operations are read-modify-write operations. The TRISGPB register controls the PORTGPB pin output drivers, even when they are being used as analog inputs. It is recommended that the user ensures the bits in the TRISGPB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. If the pin is configured for a digital output (either port or alternate function), the TRISGPB bit must be cleared in order for the pin to drive the signal and a read will reflect the state of the pin. 19.2.1 19.2.2 WEAK PULL-UPS Each of the PORTGPB pins has an individually configurable internal weak pull-up. Control bits WPUB and WPUB enable or disable each pull-up (refer to Register 19-7). Each weak pull-up is automatically turned off when the port pin is configured as an output. All pull-ups are disabled on a Power-on Reset by the RAPU bit in the OPTION_REG register. 19.2.3 ANSELB REGISTER The ANSELB register is used to configure the input mode of an I/O pin to analog. Setting the appropriate ANSELB bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. The state of the ANSELB bits has no effect on the digital output functions. A pin with TRISGPB clear and ANSELB set will still operate as a digital output, but the input mode will be analog. This can cause unexpected behavior when executing read-modify-write instructions on the affected port. The TRISGPB register controls the PORTGPB pin output drivers, even when they are being used as analog inputs. The user should ensure the bits in the TRISGPB register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. Note: The ANSELB bits default to the Analog mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSELB bits must be initialized to ‘0’ by the user’s software. INTERRUPT-ON-CHANGE Each PORTGPB pin is individually configurable as an interrupt-on-change pin. Control bits IOCB and IOCB enable or disable the interrupt function for each pin. The interrupt-on-change feature is disabled on a Power-on Reset. Reference Section 20.0 “Interrupt-On-Change” for more information.  2015-2020 Microchip Technology Inc. DS20005479D-page 129 MCP19116/7 19.2.4 PORTGPB FUNCTIONS AND OUTPUT PRIORITIES TABLE 19-3: Each PORTGPB pin is multiplexed with other functions. The pins, their combined functions and their output priorities are shown in Table 19-3. For additional information, refer to the appropriate section in this data sheet. GPB0 SDA GPB7 GPB1 VREF2 GPB4 GPB4 (MCP19117) ICSPDAT Analog input functions, such as ADC, and some digital input functions are not included in Table 19-3. These inputs are active when the I/O pin is set for Analog mode using the ANSELB register. Digital output functions may control the pin when it is in Analog mode, with the priority shown in Table 19-3. (1) GPB0 (open-drain input/output) GPB1 When multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. R/W-x Function Priority (1) Pin Name GPB0 pin in the PORTGPB register is a true open-drain pin with no connection back to VDD. REGISTER 19-5: PORTGPB OUTPUT PRIORITY GPB5 GPB5 (MCP19117) GPB6 GPB6 (MCP19117) GPB7 GPB7 (MCP19117) CCD2 Note 1: Output function priority listed from lowest to highest. PORTGPB: PORTGPB REGISTER R/W-x R/W-x R/W-x U-0 U-0 R/W-x R/W-x GPB6 (1) GPB5 (1) GPB4 (1) — — GPB1 GPB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 GPB: General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 GPB: General Purpose I/O Pin bits 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: MCP19117 only. DS20005479D-page 130  2015-2020 Microchip Technology Inc. MCP19116/7 REGISTER 19-6: R/W-1 TRISB7 TRISGPB: PORTGPB TRI-STATE REGISTER R/W-1 (1) TRISB6 (1) R/W-1 TRISB5 (1) R/W-1 TRISB4 (1) U-0 U-0 R/W-1 R/W-1 — — TRISB1 TRISB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 TRISB: PORTGPB Tri-State Control bits (1) 1 = PORTGPB pin configured as an input (tri-stated) 0 = PORTGPB pin configured as an output bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 TRISB: PORTGPB Tri-State Control bits 1 = PORTGPB pin configured as an input (tri-stated) 0 = PORTGPB pin configured as an output Note 1: MCP19117 only. WPUGPB: WEAK PULL-UP PORTGPB REGISTER (1) REGISTER 19-7: R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 R/W-1 U-0 WPUB7 (2) WPUB6 (2) WPUB5 (2) WPUB4 (2) — — WPUB1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 WPUB: Weak Pull-up Register bits (2) 1 = Pull-up enabled 0 = Pull-up disabled bit 3-2 Unimplemented: Read as ‘0’ bit 1 WPUB: Weak Pull-up Register bit 1 = Pull-up enabled 0 = Pull-up disabled bit 0 Unimplemented: Read as ‘0’ Note 1: 2: The weak pull-up device is enabled only when the global RAPU bit is enabled, the pin is in input mode (TRISGPA = 1) and the individual WPUB bit is enabled (WPUB = 1), and the pin is not configured as an analog input. MCP19117 only.  2015-2020 Microchip Technology Inc. DS20005479D-page 131 MCP19116/7 REGISTER 19-8: U-0 ANSELB: ANALOG SELECT GPB REGISTER R/W-1 ANSB6 — (1) R/W-1 ANSB5 R/W-1 (1) ANSB4 U-0 U-0 R/W-1 U-0 — — ANSB1 — (1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 ANSB: Analog Select GPA Register bits 1 = Analog input. Pin is assigned as analog input (2) 0 = Digital I/O. Pin is assigned to port or special function bit 3-2 Unimplemented: Read as ‘0’ bit 1 ANSB: Analog Select GPA Register bits 1 = Analog input. Pin is assigned as analog input (2) 0 = Digital I/O. Pin is assigned to port or special function bit 0 Unimplemented: Read as ‘0’ Note 1: 2: MCP19117 only. Setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and interrupt-on-change if available. The corresponding TRIS bit must be set to Input mode in order to allow external control of the voltage on the pin. TABLE 19-4: Name ANSELB OPTION_REG PORTGPB SUMMARY OF REGISTERS ASSOCIATED WITH PORTGPB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page — ANSB6 (1) ANSB5 (1) ANSB4 (1) — — ANSB1 — 132 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 90 GPB7 (1) GPB6 (1) GPB5 (1) GPB4 (1) — — GPB1 GPB0 130 TRISGPB TRISB7 (1) TRISB6 (1) TRISB5 (1) TRISB4 (1) — — TRISB1 TRISB0 131 WPUGPB WPUB7 (1) WPUB6 (1) WPUB5 (1) WPUB4 (1) — — WPUB1 131 — = unimplemented locations, read as ‘0’. Shaded cells are not used by the PORTGPB register. Legend: — Note 1: MCP19117 only. DS20005479D-page 132  2015-2020 Microchip Technology Inc. MCP19116/7 20.0 INTERRUPT-ON-CHANGE Each PORTGPA and PORTGPB pin is individually configurable as an interrupt-on-change pin. Control bits IOCA and IOCB enable or disable the interrupt function for each pin. Refer to Registers 20-1 and 20-2. The interrupt-on-change is disabled on a Power-on Reset. The interrupt-on-change on GPA5 is disabled when configured as MCLR pin in the CONFIG register. For enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of PORTGPA or PORTGPB. The mismatched outputs of the last read of all the PORTGPA and PORTGPB pins are OR’ed together to set the Interrupt-on-Change Interrupt Flag (IOCF) bit in the INTCON register. 20.1 Enabling the Module To allow individual port pins to generate an interrupt, the IOCE bit in the INTCON register must be set. If the IOCE bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 20.2 Individual Pin Configuration To enable a pin to detect an interrupt-on-change, the associated IOCAx or IOCBx bit in the IOCA or IOCB registers is set. 20.3 Clearing Interrupt Flags The user, in the Interrupt Service Routine, clears the interrupt by: a) Any read of PORTGPA or PORTGPB AND Clear flag bit IOCF. This ends the mismatch condition. OR b) Any write of PORTGPA or PORTGPB AND Clear flag bit IOCF. This ends the mismatch condition. A mismatch condition continues to set flag bit IOCF. Reading PORTGPA or PORTGPB ends the mismatch condition and allows flag bit IOCF to be cleared. The latch holding the last read value is not affected by a MCLR Reset. After this Reset, the IOCF flag continues to be set if a mismatch is present. Note: 20.4 If a change on the I/O pin occurs when any PORTGPA or PORTGPB operation is being executed, the IOCF interrupt flag may not get set. Operation in Sleep The interrupt-on-change interrupt sequence wakes the device from Sleep mode, if the IOCE bit is set.  2015-2020 Microchip Technology Inc. DS20005479D-page 133 MCP19116/7 20.5 Interrupt-On-Change Registers REGISTER 20-1: IOCA: INTERRUPT-ON-CHANGE PORTGPA REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 IOCA7 IOCA6 IOCA5 — IOCA3 IOCA2 IOCA1 IOCA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 IOCA: Interrupt-on-Change PORTGPA register bits 1 = Interrupt-on-change enabled on the pin 0 = Interrupt-on-change disabled on the pin bit 5 IOCA: Interrupt-on-Change PORTGPA register bit (1) 1 = Interrupt-on-change enabled on the pin 0 = Interrupt-on-change disabled on the pin bit 4 Unimplemented: Read as ‘0’ bit 3-0 IOCA: Interrupt-on-Change PORTGPA register bits 1 = Interrupt-on-change enabled on the pin 0 = Interrupt-on-change disabled on the pin Note 1: The Interrupt-on-Change on GPA5 is disabled if GPA5 is configured as MCLR. REGISTER 20-2: IOCB: INTERRUPT-ON-CHANGE PORTGPB REGISTER R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 IOCB7 (1) IOCB6 (1) IOCB5 (1) IOCB4 (1) — — IOCB1 IOCB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 IOCB: Interrupt-on-Change PORTGPB register bits 1 = Interrupt-on-change enabled on the pin 0 = Interrupt-on-change disabled on the pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 IOCB: Interrupt-on-Change PORTGPB register bits 1 = Interrupt-on-change enabled on the pin 0 = Interrupt-on-change disabled on the pin Note 1: MCP19117 only. DS20005479D-page 134  2015-2020 Microchip Technology Inc. MCP19116/7 TABLE 20-1: Name ANSELA ANSELB SUMMARY OF REGISTERS ASSOCIATED WITH INTERRUPT-ON-CHANGE Bit 7 Bit 6 — — — ANSB6 Bit 5 Bit 4 — (1) ANSB5 — (1) ANSB4 (1) Bit 3 Bit 2 Bit 1 Bit 0 Register on page ANSA3 ANSA2 ANSA1 ANSA0 128 — — ANSB1 — 132 GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 107 IOCA IOCA7 IOCA6 IOCA5 — IOCA3 IOCA2 IOCA1 IOCA0 134 IOCB IOCB7 (1) IOCB6 (1) IOCB5 (1) IOCB4 (1) — — IOCB1 IOCB0 134 TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 127 — — TRISB1 TRISB0 131 INTCON TRISGPA TRISGPB TRISB7 (1) TRISB6 (1) TRISB5 (1) TRISB4 (1) Legend: — = unimplemented locations, read as ‘0’. Shaded cells are not used by interrupt-on-change. Note 1: MCP19117 only.  2015-2020 Microchip Technology Inc. DS20005479D-page 135 MCP19116/7 NOTES: DS20005479D-page 136  2015-2020 Microchip Technology Inc. MCP19116/7 21.0 INTERNAL TEMPERATURE INDICATOR MODULE The MCP19116/7 devices are equipped with a temperature circuit designed to measure the operating temperature of the silicon die. The circuit's range of operating temperature falls between –40°C and +125°C. The output is a voltage that is proportional to the device temperature. The output of the temperature indicator is internally connected to the device ADC. 21.1 Circuit Operation This internal temperature measurement circuit is always enabled. FIGURE 21-1: TEMPERATURE CIRCUIT DIAGRAM 21.2 Temperature Output The output of the circuit is measured using the internal analog-to-digital converter. Channel 13 is reserved for the temperature circuit output. Refer to Section 22.0, Analog-to-Digital Converter (ADC) Module for detailed information. The temperature of the silicon die can be calculated by the ADC measurement by using Equation 21-1. A factory-stored 10-bit ADC value for 30°C is located at address 2084h. The temperature coefficient for this circuit is 14.0 mV/°C from –40°C to +125°C. Other temperature readings can be calculated from the 30°C mark. Note: ADC temperature numbers represented are with ADC_REF = AVDD VDD VOUT ADC MUX ADC n CHS bits (ADCON0 register) EQUATION 21-1: SILICON DIE TEMPERATURE  ADC_READING (counts) – ADC_30  C_READING (counts  TEMP_DIE(  C  = ----------------------------------------------------------------------------------------------------------------------------------------------------- + 30  C 3.5 (counts/  C   2015-2020 Microchip Technology Inc. DS20005479D-page 137 MCP19116/7 NOTES: DS20005479D-page 138  2015-2020 Microchip Technology Inc. MCP19116/7 22.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE Note: The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs that are multiplexed into a single sample-and-hold circuit. The output of the sample-and-hold is connected to the input of the converter. The converter generates a 10-bit binary result via successive approximation and stores the right-justified conversion result into the ADC result registers (ADRESH:ADRESL register pair). Figure 22-1 shows the block diagram of the ADC. Once VIN is greater than AVDD + VDROPOUT, AVDD is in regulation, allowing A/D readings to be accurate. Once VIN is greater than VDD + VDROPOUT, VDD is in regulation, allowing accurate ratiometric measurements. The internal band gap supplies the voltage reference to the ADC. FIGURE 22-1: ADC BLOCK DIAGRAM VIN/n 00000 VREF OV_REF 00001 Note 1: When ADON = 0, all multiplexer inputs are disconnected. 00010 VBGR* 00011 2: Refer to ADCON0 register for detailed analog channel selection per device. VS 00100 EA_SC 00101 A2 00110 PEDESTAL 00111 Reserved 01000 Reserved 01001 IP_ADJ 01010 IP_OFF_REF 01011 VDR/n 01100 TEMP_SNS 01101 DLL_VCON 01110 SLPCMP_REF 01111 TRI-STATE AVDD CHS4: CHS0 GPA0/AN0 11000 GPA1/AN1 11001 GPA2/AN2 11010 GPA3/AN3 11011 GPB1/AN4 11100 MCP19117 only GPB4/AN5 11101 MCP19117 only GPB5/AN6 11110 MCP19117 only GPB6/AN7 11111 ADC GO/DONE 10 10 ADON ADRESH ADRESL AGND CHS4: CHS0  2015-2020 Microchip Technology Inc. DS20005479D-page 139 MCP19116/7 22.1 ADC Configuration When configuring and using the ADC, the following functions must be considered: • • • • • Port configuration Channel selection ADC conversion clock source Interrupt control Result formatting 22.1.1 PORT CONFIGURATION The ADC is used to convert analog signals into a corresponding digital representation. When converting analog signals, the I/O pin should be configured for analog by setting the associated TRIS and ANSEL bits. Refer to Section 19.0, I/O Ports for more information. Note: 22.1.2 Analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. CHANNEL SELECTION 22.1.3 The source of the conversion clock is software selectable via the ADCS bits in the ADCON1 register. There are five possible clock options: • • • • • FOSC/8 FOSC/16 FOSC/32 FOSC/64 FRC (clock derived from internal oscillator with a divisor of 16) The time to complete one-bit conversion is defined as TAD. One full 10-bit conversion requires 11 TAD periods, as shown in Figure 22-2. For a correct conversion, the appropriate TAD specification must be met. Refer to the A/D conversion requirements in Section 4.0 “Electrical Characteristics” for more information. Table 22-1 gives examples of appropriate ADC clock selections. Note: There are up to 21 channel selections available for the MCP19116 and 24 channels for the MCP19117: • • • • • • • • • • • • • • • • • • AN pins AN pins (MCP19117 only) VIN: 1/15.53 of the input voltage (VIN) VREF: voltage reference for regulation set point OV_REF: reference for OV comparator VBGR: band gap reference VS: voltage proportional to VOUT EA_SC: error amplifier output after slope compensation A2: secondary current sense amplifier output Pedestal Reserved Reserved IP_ADJ: IP after pedestal and offset adjust IP_OFF_REF: IP offset reference VDR: VDR * 0.229V/V TEMP_SNS: analog voltage representing internal temperature (refer to Equation 21-1) DLL_VCON: delay locked loop voltage reference SLPCMP_REF: slope compensation reference The CHS bits in the ADCON0 register determine which channel is connected to the sample and hold circuit. When changing channels, a delay is required before starting the next conversion. Refer to Section 22.2 “ADC Operation” for more information. DS20005479D-page 140 ADC CONVERSION CLOCK Unless using the FRC, any changes in the system clock frequency will change the ADC clock frequency, which may adversely affect the ADC result. TABLE 22-1: ADC CLOCK PERIOD (TAD) VS. DEVICE OPERATING FREQUENCIES ADC Clock Period (TAD) ADC Clock Source Device Frequency (FOSC) ADCS 8 MHz FOSC/8 001 1.0 µs (1) FOSC/16 101 2.0 µs FOSC/32 010 4.0 µs FOSC/64 110 8.0 µs (2) FRC x11 2.0 – 6.0 µs (3, 4) Legend: Shaded cells are outside of recommended range. Note 1: These values violate the minimum required TAD time. 2: For faster conversion times, the selection of another clock source is recommended. 3: The FRC source has a typical TAD time of 4 µs for VDD > 3.0V. 4: The FRC clock source is only recommended if the conversion will be performed during Sleep.  2015-2020 Microchip Technology Inc. MCP19116/7 FIGURE 22-2: ANALOG-TO-DIGITAL CONVERSION TAD CYCLES TCY - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b9 b8 b7 b6 b5 b4 b2 b3 b1 b0 Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO/DONE bit On the following cycle: ADRESH:ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. 22.1.4 INTERRUPTS Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake up from Sleep and resume in-line code execution, the GIE and PEIE bits in the INTCON register must be disabled. If the GIE and PEIE bits in the INTCON register are enabled, execution will switch to the Interrupt Service Routine. The ADC module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. The ADC Interrupt Flag is the ADIF bit in the PIR1 register. The ADC Interrupt Enable is the ADIE bit in the PIE1 register. The ADIF bit must be cleared in software. 22.1.5 Note 1: The ADIF bit is set at the completion of every conversion, regardless of whether or not the ADC interrupt is enabled. The 10-bit A/D conversion result is supplied in right-justified format only. Figure 22-3 shows the output format. This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt wakes the device up. Upon waking from FIGURE 22-3: RESULT FORMATTING 10-BIT A/D RESULT FORMAT (ADFM = 1) MSB bit 7 LSB bit 0 Read as ‘0  2015-2020 Microchip Technology Inc. bit 7 bit 0 10-bit A/D Result DS20005479D-page 141 MCP19116/7 22.2 22.2.1 ADC Operation ADC REFERENCE SWITCH Users have the option of connecting the 5V LDO (VDD) or the 4.096V LDO (AVDD) as the reference to the Analog-to-Digital Converter. This control bit (VCFG) is located in the ADCON1 register bit 0 (see Register 22-2). Default configuration connects the AVDD to the ADC reference. 22.2.2 STARTING A CONVERSION To enable the ADC module, the ADON bit in the ADCON0 register must be set to a ‘1’. Setting the GO/DONE bit in the ADCON0 register to a ‘1’ starts the analog-to-digital conversion. Note: 22.2.3 The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 22.2.6 “A/D Conversion Procedure”. COMPLETION OF A CONVERSION When the conversion is complete, the ADC module: • Clears the GO/DONE bit • Sets the ADIF Interrupt Flag bit • Updates the ADRESH:ADRESL registers with new conversion result 22.2.4 TERMINATING A CONVERSION If a conversion must be terminated before completion, the GO/DONE bit can be cleared in software. The ADRESH:ADRESL registers are not updated with the partially complete analog-to-digital conversion sample. Instead, the ADRESH:ADRESL register pair retains the value of the previous conversion. Additionally, two ADC clock cycles are required before another acquisition can be initiated. Following the delay, an input acquisition is automatically started on the selected channel. Note: 22.2.5 A device reset forces all registers to their Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. ADC OPERATION DURING SLEEP The ADC is not operational during Sleep mode. The AVDD 4V reference has been removed to minimize Sleep current. DS20005479D-page 142 22.2.6 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an analog-to-digital conversion: 1. 2. 3. 4. 5. 6. 7. 8. Configure Port: • Disable pin output driver (refer to the TRISGPx registers) • Configure pin as analog (refer to the ANSELx registers) Configure the ADC module: • Select ADC conversion clock • Select ADC input channel • Turn on ADC module Configure ADC interrupt (optional): • Clear ADC interrupt flag • Enable ADC interrupt • Enable peripheral interrupt • Enable global interrupt (1) Wait the required acquisition time (2). Start conversion by setting the GO/DONE bit. Wait for ADC conversion to complete by one of the following: • Polling the GO/DONE bit • Waiting for the ADC interrupt (interrupts enabled) Read ADC Result. Clear the ADC interrupt flag (required if interrupt is enabled). Note 1: The global interrupt can be disabled if the user is attempting to wake up from Sleep and resume in-line code execution. 2: Refer to Section 22.4 “A/D Acquisition Requirements”. EXAMPLE 22-1: A/D CONVERSION ;This code block configures the ADC ;for polling, Frc clock and AN0 input. ; ;Conversion start & polling for completion ; are included. ; BANKSELADCON1; MOVLWB’01110000’;Frc clock MOVWFADCON1; BANKSELTRISGPA; BSF TRISGPA,0;Set GPA0 to input BANKSELANSELA; BSF ANSELA,0;Set GPA0 to analog BANKSELADCON0; MOVLWB’01100001’;Select channel AN0 MOVWFADCON0;Turn ADC On CALLSampleTime;Acquisiton delay BSF ADCON0,1;Start conversion BTFSCADCON0,1;Is conversion done? GOTO$-1 ;No, test again BANKSELADRESH; MOVFADRESH,W;Read upper 2 bits MOVWFRESULTHI;store in GPR space BANKSELADRESL; MOVFADRESL,W;Read lower 8 bits MOVWFRESULTLO;Store in GPR space  2015-2020 Microchip Technology Inc. MCP19116/7 22.3 ADC Register Definitions The following registers are used to control the operation of the ADC: REGISTER 22-1: ADCON0: A/D CONTROL REGISTER 0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-2 CHS: Analog Channel Select bits 00000 = VIN/n analog voltage measurement (VIN/n = VIN/15.5328) 00001 = VREF (DAC reference voltage setting current regulation level) 00010 = OV_REF (reference for overvoltage comparator) 00011 = VBGR (band gap reference) 00100 = VS (Voltage proportional to VOUT) 00101 = EA_SC (Error Amplifier after Slope Compensation output) 00110 = A2 (Secondary Current Sense Amplifier output) 00111 = Pedestal (Pedestal Voltage) 01000 = Reserved 01001 = Reserved 01010 = IP_ADJ (IP after Pedestal and Offset Adjust (at PWM Comparator)) 01011 = IP_OFF_REF (IP Offset Reference) 01100 = VDR/n (VDR/n analog driver voltage measurement = 0.229V/V * VDR) 01101 = TEMP_SNS (analog voltage representing internal temperature) 01110 = DLL_VCON (Delay Locked-Loop Voltage Reference – Control voltage for dead time) 01111 = SLPCMP_REF (Slope compensation reference) 10000 = Unimplemented 10001 = Unimplemented 10010 = Unimplemented 10011 = Unimplemented 10100 = Unimplemented 10101 = Unimplemented 10110 = Unimplemented 10111 = Unimplemented 11000 = GPA0/AN0 11001 = GPA1/AN1 11010 = GPA2/AN2 11011 = GPA3/AN3 11100 = GPB1/AN4 11101 = GPB4/AN5 (MCP19117 only) 11110 = GPB5/AN6 (MCP19117 only) 11111 = GPB6/AN7 (MCP19117 only) bit 1 GO/DONE: A/D Conversion Status bit 1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle This bit is automatically cleared by hardware when the A/D conversion has completed 0 = A/D conversion completed/not in progress bit 0 ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current  2015-2020 Microchip Technology Inc. DS20005479D-page 143 MCP19116/7 REGISTER 22-2: ADCON1: A/D CONTROL REGISTER 1 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 — ADCS2 ADCS1 ADCS0 — — — VCFG bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-4 ADCS: A/D Conversion Clock Select bits 000 = Reserved 001 = FOSC/8 010 = FOSC/32 x11 = FRC (clock derived from internal oscillator with a divisor of 16) 100 = Reserved 101 = FOSC/16 110 = FOSC/64 bit 3-1 Unimplemented: Read as ‘0’ bit 0 VCFG: ADC Reference Voltage Configuration 0 = AVDD 1 = VDD REGISTER 22-3: ADRESH: ADC RESULT REGISTER HIGH U-0 U-0 U-0 U-0 U-0 U-0 R-x R-x — — — — — — ADRES9 ADRES8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1-0 ADRES: Most Significant A/D Results REGISTER 22-4: ADRESL: ADC RESULT REGISTER LOW R-x R-x R-x R-x R-x R-x R-x R-x ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 ADRES: Least Significant A/D results DS20005479D-page 144  2015-2020 Microchip Technology Inc. MCP19116/7 22.4 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 22-4. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), refer to Figure 22-4. The maximum recommended impedance for analog sources is 10 k. EQUATION 22-1: As the source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started. To calculate the minimum acquisition time, Equation 22-1 may be used. This equation assumes that 1/2 LSb error is used (1,024 steps for the ADC). The 1/2 LSb error is the maximum error allowed for the ADC to meet its specified resolution. ACQUISITION TIME EXAMPLE Assumptions: Temperature = +50°C and external impedance of 10 k  5.0V V DD T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient = T AMP + T C + T COFF = 2 µs + T C +   Temperature - 25°C   0.05 µs/°C   The value for TC can be approximated with the following equations:   1 V APPLIED  1 – ------------------------------ = V CHOLD n+1  2  – 1 – TC  ----------  RC  V 1–e  = V CHOLD APPLIED     – TC  ----------    RC  1 V 1–e  = V APPLIED  1 – ------------------------------ APPLIED  n+1   2  – 1   ;[1] VCHOLD charged to within 1/2 lsb ;[2] VCHOLD charge response to VAPPLIED ;combining [1] and [2] Note: Where n = number of bits of the ADC. Solving for TC: T C = – C HOLD  R IC + R SS + R S  ln(1/2047) = – 10 pF  1 k  + 7 k  + 10 k   ln(0.0004885) = 1.37 µs Therefore: T ACQ = 2 µs + 1.37µs +   50°C- 25°C   0.05µs/°C   = 4.67 µs Note 1: The charge holding capacitor (CHOLD) is not discharged after each conversion. 2: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification.  2015-2020 Microchip Technology Inc. DS20005479D-page 145 MCP19116/7 FIGURE 22-4: ANALOG INPUT MODEL RS VA Sampling Switch SS RSS VDD Analog Input pin VT  0.6V CPIN 5 pF VT  0.6V RIC  1k ILEAKAGE(1) CHOLD = 10 pF AGND/VREF – Legend: CHOLD = Sample/Hold Capacitance CPIN = Input Capacitance ILEAKAGE = Leakage current at the pin due to various junctions 6V 5V VDD 4V 3V 2V RIC = Interconnect Resistance RSS 5 6 7 8 91011 Sampling Switch (kW) RSS = Resistance of Sampling Switch SS = Sampling Switch VT = Threshold Voltage Note 1: Refer to Section 4.0 “Electrical Characteristics”. FIGURE 22-5: ADC TRANSFER FUNCTION ADC Output Code Full-Scale Range 3FFh 3FEh 3FDh 3FCh 3FBh 03h 02h 01h 00h Analog Input Voltage 0.5 LSB VREF- DS20005479D-page 146 Zero-Scale Transition 1.5 LSB Full-Scale Transition VREF+  2015-2020 Microchip Technology Inc. MCP19116/7 TABLE 22-2: SUMMARY OF REGISTERS ASSOCIATED WITH ADC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page ADCON0 — CHS4 CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 143 Name ADCON1 — ADCS2 ADCS1 ADCS0 — — — — 144 ADRESH — — — — — — ADRES9 ADRES8 144 ADRESL ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 ADRES1 ADRES0 144 ANSELA — — — — ANSA3 ANSA2 ANSA1 ANSA0 128 ANSELB — ANSB6 ANSB5 ANSB4 — — ANSB1 — 132 INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 107 PIE2 CDSIE ADIE — OTIE OVIE DRUVIE OVLOIE UVLOIE 109 PIR2 CDSIF ADIF — OTIF OVIF DRUVIF OVLOIF UVLOIF 111 TRISGPA TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 127 TRISGPB TRISB7 TRISB6 TRISB5 TRISB4 — — TRISB1 TRISB0 131 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for ADC module.  2015-2020 Microchip Technology Inc. DS20005479D-page 147 MCP19116/7 NOTES: DS20005479D-page 148  2015-2020 Microchip Technology Inc. MCP19116/7 23.0 TIMER0 MODULE The Timer0 module is an 8-bit timer/counter with the following features: • • • • • 8-bit timer/counter register (TMR0) 8-bit prescaler Programmable internal or external clock source Programmable external clock edge selection Interrupt on overflow Figure 23-1 is a block diagram of the Timer0 module. FIGURE 23-1: TIMER0 BLOCK DIAGRAM FOSC/4 Data Bus 0 T0CKI 1 1 0 TMR0SE TMR0CS 8-bit Prescaler PSA 8 Sync 2 TCY TMR0 Set Flag bit TMR0IF on Overflow Overflow to Timer1 8 PS 23.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 23.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-Bit Timer mode is selected by clearing the T0CS bit in the OPTION_REG register. When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. Note: 23.1.2 The value written to the TMR0 register can be adjusted, in order to account for the two-instruction cycle delay when TMR0 is written. 8-BIT COUNTER MODE 23.1.3 SOFTWARE PROGRAMMABLE PRESCALER A single software programmable prescaler is available for use with either Timer0 or the Watchdog Timer (WDT), but not both simultaneously. The prescaler assignment is controlled by the PSA bit in the OPTION_REG register. To assign the prescaler to Timer0, the PSA bit must be cleared to ‘0’. There are eight prescaler options for the Timer0 module ranging from 1:2 to 1:256. The prescale values are selectable via the PS bits in the OPTION_REG register. In order to have a 1:1 prescaler value for the Timer0 module, the prescaler must be disabled by setting the PSA bit in the OPTION_REG register. The prescaler is not readable or writable. When assigned to the Timer0 module, all instructions writing to the TMR0 register will clear the prescaler. In 8-Bit Counter mode, the Timer0 module increments on every rising or falling edge of the T0CKI pin. The incrementing edge is determined by the T0SE bit in the OPTION_REG register. 8-Bit Counter mode using the T0CKI pin is selected by setting the T0SE bit in the OPTION_REG register to ‘1’.  2015-2020 Microchip Technology Inc. DS20005479D-page 149 MCP19116/7 23.1.4 23.1.5 SWITCHING PRESCALER BETWEEN TIMER0 AND WDT MODULES As a result of having the prescaler assigned to either Timer0 or the WDT, it is possible to generate an unintended device reset when switching prescaler values. When changing the prescaler assignment from Timer0 to the WDT module, the instruction sequence shown in Example 23-1 must be executed. EXAMPLE 23-1: Timer0 will generate an interrupt when the TMR0 register overflows from FFh to 00h. The T0IF interrupt flag bit in the INTCON register is set every time the TMR0 register overflows, regardless of whether or not the Timer0 interrupt is enabled. The T0IF bit can only be cleared in software. The Timer0 interrupt enable is the T0IE bit in the INTCON register. Note: CHANGING PRESCALER (TIMER0  WDT) 23.1.6 BANKSELTMR0; CLRWDT ;Clear WDT CLRFTMR0;Clear TMR0 and ;prescaler BANKSELOPTION_REG; BSF OPTION_REG,PSA;Select WDT CLRWDT ; ; MOVLWb’11111000’;Mask prescaler ANDWFOPTION_REG,W;bits IORLWb’00000101’;Set WDT prescaler MOVWFOPTION_REG;to 1:32 The Timer0 interrupt cannot wake the processor from Sleep since the timer is frozen during Sleep. USING TIMER0 WITH AN EXTERNAL CLOCK When Timer0 is in Counter mode, the synchronization of the T0CKI input and the Timer0 register is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, the high and low periods of the external clock source must meet the timing requirements as shown in Section 4.0 “Electrical Characteristics”. 23.1.7 When changing the prescaler assignment from the WDT to the Timer0 module, the following instruction sequence must be executed (refer to Example 23-2). EXAMPLE 23-2: TIMER0 INTERRUPT OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. CHANGING PRESCALER (WDT  TIMER0) CLRWDT ;Clear WDT and ;prescaler BANKSELOPTION_REG; MOVLWb’11110000’;Mask TMR0 select and ANDWFOPTION_REG,W;prescaler bits IORLWb’00000011’;Set prescale to 1:16 MOVWFOPTION_REG; TABLE 23-1: Name INTCON OPTION_REG SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 3 Bit 2 Bit 1 Bit 0 Register on page GIE PEIE T0IE INTE IOCIE T0IF INTF IOCIF 107 RAPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 90 TMR0 TRISGPA Bit 4 Timer0 Module Register TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 149* TRISA2 TRISA1 TRISA0 127 Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. DS20005479D-page 150  2015-2020 Microchip Technology Inc. MCP19116/7 24.0 TIMER1 MODULE The Timer1 module is a 16-bit timer with the following features: • • • • • 16-bit timer register pair (TMR1H:TMR1L) Readable and writable (both registers) Selectable internal clock source 2-bit prescaler Interrupt on overflow Figure 24-1 is a block diagram of the Timer1 module. FIGURE 24-1: TIMER1 BLOCK DIAGRAM TMR1ON Set flag bit TMR1IF on Overflow TMR1(1) TMR1H TMR1L FOSC 1 Prescaler 1, 2, 4, 8 0 2 T1CKPS TMR1CS Note 1: TMR1 register increments on rising edge. 24.1 Timer1 Operation The Timer1 module is a 16-bit incrementing timer which is accessed through the TMR1H:TMR1L register pair. Writes to TMR1H or TMR1L directly update the counter. The timer is incremented on every instruction cycle. Timer1 is enabled by configuring the TMR1ON bit in the T1CON register. Table 24-1 displays the Timer1 enable selections. 24.2 Clock Source Selection The TMR1CS bit in the T1CON register is used to select the clock source for Timer1. Table 24-1 displays the clock source selections.  2015-2020 Microchip Technology Inc. 24.2.1 INTERNAL CLOCK SOURCE The TMR1H:TMR1L register pair will increment on multiples of FOSC or FOSC/4 as determined by the Timer1 prescaler. As an example, when the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. TABLE 24-1: TMR1CS CLOCK SOURCE SELECTIONS Clock Source 1 8 MHz system clock (FOSC) 0 2 MHz instruction clock (FOSC/4) DS20005479D-page 151 MCP19116/7 24.3 Timer1 Prescaler 24.5 Timer1 in Sleep Timer1 has four prescaler options, allowing 1, 2, 4 or 8 divisions of the clock input. The T1CKPS bits in the T1CON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMR1H or TMR1L. Unlike other standard mid-range Timer1 modules, the MCP19116/7 Timer1 module only clocks from an internal system clock, and thus cannot run during Sleep mode, nor can it be used to wake the device from this mode. 24.4 The Timer1 Control (T1CON) register, shown in Register 24-1, is used to control Timer1 and select the various features of the Timer1 module. 24.6 Timer1 Interrupt The Timer1 register pair (TMR1H:TMR1L) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit in the PIR1 register is set. To enable the interrupt on rollover, these bits must be set: • • • • Timer1 Control Register TMR1ON bit in the T1CON register TMR1IE bit in the PIE1 register PEIE bit in the INTCON register GIE bit in the INTCON register The interrupt is cleared by clearing the TMR1IF bit in the Interrupt Service Routine. Note: The TMR1H:TMR1L register pair and the TMR1IF bit should be cleared before enabling interrupts. REGISTER 24-1: T1CON: TIMER1 CONTROL REGISTER U-0 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0/ R/W-0 — — T1CKPS1 T1CKPS0 — — TMR1CS TMR1ON bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 T1CKPS: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3-2 Unimplemented: Read as ‘0’ bit 1 TMR1CS: Timer1 Clock Source Control bit 1 = 8 MHz system clock (FOSC) 0 = 2 MHz instruction clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1, Clears Timer1 gate flip-flop DS20005479D-page 152  2015-2020 Microchip Technology Inc. MCP19116/7 TABLE 24-2: SUMMARY OF REGISTERS ASSOCIATED WITH TIMER1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 107 PIE1 TXIE RCIE BCLIE SSPIE CC2IE CC1IE TMR2IE TMR1IE 108 PIR1 TXIF RCIF BCLIF SSPIF CC2IF CC1IF TMR2IF TMR1IF 110 TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register T1CON — — T1CKPS1 T1CKPS0 — — TMR1CS TMR1ON 151* 151* 152 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. * Page provides register information.  2015-2020 Microchip Technology Inc. DS20005479D-page 153 MCP19116/7 NOTES: DS20005479D-page 154  2015-2020 Microchip Technology Inc. MCP19116/7 25.0 TIMER2 MODULE The Timer2 module is an 8-bit timer with the following features: • • • • 8-bit timer register (TMR2) 8-bit period register (PR2) Interrupt on TMR2 match with PR2 Software programmable prescaler (1:1, 1:4, 1:16) Timer2 Operation The clock input to the Timer2 module is the system clock (FOSC). The clock is fed into the Timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. The output of the prescaler is then used to increment the TMR2 register. The values of TMR2 and PR2 are constantly compared to determine when they match. TMR2 increments from 00h until it matches the value in PR2. When a match occurs, TMR2 is reset to 00h on the next increment cycle. FIGURE 25-1: The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘1’. Timer2 is turned off by clearing the TMR2ON bit to a ‘0’. Refer to Figure 25-1 for a block diagram of Timer2. 25.1 The match output of the Timer2/PR2 comparator is used to set the TMR2IF interrupt flag bit in the PIR1 register. The Timer2 prescaler is controlled by the T2CKPS bits in the T2CON register. The prescaler counter is cleared when: • A write to TMR2 occurs • A write to T2CON occurs • Any device reset occurs (Power-on Reset, MCLR Reset, Watchdog Timer Reset or Brown-out Reset) Note: TMR2 is not cleared when T2CON is written. TIMER2 BLOCK DIAGRAM TMR2 Output FOSC Prescaler 1:1, 1:4, 1:8, 1:16 2 TMR2 Comparator T2CKPS Sets Flag bit TMR2IF Reset EQ PR2  2015-2020 Microchip Technology Inc. DS20005479D-page 155 MCP19116/7 25.2 Timer2 Control Register REGISTER 25-1: T2CON: TIMER2 CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is ON 0 = Timer2 is OFF bit 1-0 T2CKPS: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 10 = Prescaler is 8 11 = Prescaler is 16 TABLE 25-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on page INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 107 PIE1 TXIE RCIE BCLIE SSPIE CC2IE CC1IE TMR2IE TMR1IE 108 PIR1 TXIF RCIF BCLIF SSPIF CC2IF CC1IF TMR2IF TMR1IF 110 PR2 T2CON Timer2 Module Period Register — TMR2 — — — — 155* TMR2ON T2CKPS1 T2CKPS0 Holding Register for the 8-bit TMR2 Time Base 156 155* Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for Timer2 module. * Page provides register information. DS20005479D-page 156  2015-2020 Microchip Technology Inc. MCP19116/7 26.0 ENHANCED PWM MODULE The PWM module implemented on the MCP19116/7 is a scaled-down version of the Capture/Compare/PWM (CCP) module found in standard mid-range microcontrollers. The module only features the PWM module, which is slightly modified from standard mid-range microcontrollers. In the MCP19116/7, the PWM module is used to generate the system clock or system oscillator. This system clock can control the MCP19116/7 switching frequency, as well as set the maximum allowable duty cycle. The PWM module does not continuously adjust the duty cycle to control the output voltage. This is accomplished by the analog control loop and associated circuitry. 26.1 26.1.1 When the MCP19116/7 is running stand-alone, the PWM signal functions as the system clock. It is operating at the programmed switching frequency with a programmed maximum duty cycle (DCLOCK). The programmed maximum duty cycle is not adjusted on a cycle-by-cycle basis to control the MCP19116/7 system output. The required duty cycle (DPDRVON) to control the output is adjusted by the MCP19116/7 analog control loop and associated circuitry. DCLOCK does however set the maximum allowable DPDRVON. EQUATION 26-1: D PDRVON  1 – D CLOCK Standard Pulse-Width Modulation Mode The CCP will only function in PWM mode. The PWM signal is used to set the operating frequency and maximum allowable duty cycle of the MCP19116/7. Figure 26-1 is a snippet of the MCP19116/7 block diagram showing the PWM signal from the CCP module. FIGURE 26-1: MCP19116/7 SNIPPET SHOWING SYSTEM CLOCK FROM PWM MODULE PWM signal from CCP 116 OV OVE PWM S Q R Q There are two modes of operation that concern the system clock PWM signal. These modes are Stand-Alone (non-frequency synchronization) and Frequency Synchronization. STAND-ALONE (NON-FREQUENCY SYNCHRONIZATION) MODE 26.1.2 SWITCHING FREQUENCY SYNCHRONIZATION MODE The MCP19116/7 can be programmed to be switching frequency MASTER or SLAVE devices. The MASTER device functions as described in Section 26.1.1 “Stand-Alone (Non-Frequency Synchronization) Mode” with the exception of the system clock also being applied to GPA1. A SLAVE device will receive the MASTER system clock on GPA1. This MASTER system clock will be OR’ed with the output of the TIMER2 module. This OR’ed signal will latch PWMRL into PWMRH and PWMPHL into PWMPHH. Figure 26-2 shows a simplified block diagram of the CCP module in PWM mode. The PWMPHL register allows for a phase shift to be added to the SLAVE system clock. It is desired to have the MCP19116/7 SLAVE device’s system clock start point shifted by a programmed amount from the MASTER system clock. This SLAVE phase shift is specified by writing to the PWMPHL register. The SLAVE phase shift can be calculated by using the following equation. EQUATION 26-2: SLAVE PHASE SHIFT = PWMPHL  T OSC   T2 PRESCALE VALUE   2015-2020 Microchip Technology Inc. DS20005479D-page 157 MCP19116/7 FIGURE 26-2: SIMPLIFIED PWM BLOCK DIAGRAM PWMPHL PWMRL 8 8 PWMPHH (SLAVE) PWMRH (SLAVE) LATCH DATA LATCH DATA 8 8 Comparator Comparator 8 R Q S Q OSC SYSTEM CLOCK 8 RESET TIMER TMR2 (1) (Note 1) WDM_ RESET 8 Comparator 8 EN_ SS CLKPIN_IN PR2 Note 1: TIMER 2 should be clocked by FOSC (8 MHz). A PWM output (Figure 26-2) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 26-3: PWM OUTPUT Period 26.1.3 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following equation. EQUATION 26-1: PWM PERIOD =   PR2  + 1   T OSC   T2 PRESCALE VALUE  Duty Cycle TMR2 = PR2 + 1 TMR2 = PWMRH TMR2 = PR2 + 1 DS20005479D-page 158 When TMR2 is equal to PR2, the following two events occur on the next increment cycle: • TMR2 is cleared • The PWM duty cycle is latched from PWMRL into PWMRH  2015-2020 Microchip Technology Inc. MCP19116/7 26.1.4 PWM DUTY CYCLE (DCLOCK) The PWM duty cycle (DCLOCK) is specified by writing to the PWMRL register. Up to 8-bit resolution is available. The following equation is used to calculate the PWM duty cycle (DCLOCK). DUTY CYCLE TABLE 26-1: = PWMRL  T OSC 26.2   T2 PRESCALE VALUE  SUMMARY OF REGISTERS ASSOCIATED WITH PWM MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 MODECON MSC1 MSC0 RFB — MSC2 — — — — — T2CON Operation During Sleep When the device is placed in Sleep, the allocated timer will not increment and the state of the module will not change. If the CLKPIN pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. EQUATION 26-2: PWM The PWMRL bits can be written to at any time, but the duty cycle value is not latched into PWMRH until after a match between PR2 and TMR2 occurs. PR2 PWMRL PWMPHL Bit 2 Bit 1 Bit 0 — — — TMR2ON T2CKPS1 T2CKPS0 Register on page 52 156 Timer2 Module Period Register 157 PWM Register Low Byte 157* Phase Shift Low Byte 157* Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by PWM mode. * Page provides register information.  2015-2020 Microchip Technology Inc. DS20005479D-page 159 MCP19116/7 NOTES: DS20005479D-page 160  2015-2020 Microchip Technology Inc. MCP19116/7 27.0 PWM CONTROL LOGIC The PWM Control Logic implements standard comparator modules to identify events such as input undervoltage, input overvoltage and desaturation detection. The control logic takes action in hardware to appropriately enable/disable the output drive (PDRV/SDRV), as well as to set corresponding interrupt flags to be read by software. This control logic also defines normal PWM operation. For definition of individual bits within the control logic, refer to the Special Function Register (SFR) sections. FIGURE 27-1: PWM CONTROL LOGIC D Q1 EN Q UVLOOUT UVLOINTP OVINTP OVIF OVINTN + - Q1 Q OVLOOUT EN OVLOINTP UVLO Vs OV_REF D UVLOIF UVLOINTN OVLOIF OVLOINTN UVLOEN OV D Q OVOUT OVLO Q1 EN OVLOEN PWM PWMSTR_SEN SDRVEN OVEN PDRVEN DELAY E/AOUT Ip SDRV SDRV_ON + DELAY PDRV PWM S PWMSTR_PEN CDSINTP DESATP BG CDSPOL MUX DESATN CDSIF CDSINTN + - VDRUVBY VDRUVLO + DRUVIF CDSMUX DEFAULT TO DESATP D Q CDSOUT TMPTBY Q1 EN S CDSOE 200 ns SDRV_ON ONE SHOT  2015-2020 Microchip Technology Inc. 33 ns Q PWM ONE SHOT S OT + OTIF R CDSWDE WDM_RESET DS20005479D-page 161 MCP19116/7 NOTES: DS20005479D-page 162  2015-2020 Microchip Technology Inc. MCP19116/7 28.0 DUAL CAPTURE/COMPARE (CCD) MODULE The CCD module is implemented on the MCP19116/7. This module is a new module based on the standard CCP module. It has two capture and compare-only register sets with no PWM function. 28.1 Capture Mode In Capture mode, the CCxRH:CCxRL register set captures the 16-bit value of the TMR1 register when an event occurs on the DIMI pin. An event is defined as one of the following: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge FIGURE 28-1: The type of event is configured by control bits CCxM3:CCxM0 (CCDCON for register set 1 or CCDCON for register set 2). When a capture is made, the interrupt request flag bit, CCxIF (PIR1 for register set 1 or PIR1 for register set 2), is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the register set is read, the old captured value is overwritten by the new value. 28.1.1 CCX PIN CONFIGURATION In Capture mode, the DIMI pin should be configured as an input by setting the TRIS bit for that pin. Note: If the CCD pin is configured as an output, a write to the port can cause a capture condition. CAPTURE MODE OPERATION BLOCK DIAGRAM Prescaler ÷1, 4, 16 Set Flag bit CCxIF (PIR1 register) CCxRH CCD pin and Edge Detect CCxRL Capture Enable TMR1H TMR1L CCDCON (FOSC) 28.1.2 TIMER1 MODE SELECTION Timer1 must be running off of the instruction clock for the CCD module to use the capture feature. If Timer1 is running off of the 8 MHz clock, the capture feature may not function correctly. 28.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the enable for the capture interrupt clear in order to avoid false interrupts and should clear the flag bit, CCxIF, following any such change in the operating mode.  2015-2020 Microchip Technology Inc. 28.1.4 CCD PRESCALER There are four prescaler settings, specified by bits CCxM3:CCxM0. Whenever the CCD register set is disabled or not set to Capture mode, the prescaler counter is cleared. Any reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first capture may be from a non-zero prescaler. It is recommended to disable the register set (CCxM3:0 = 00xx) prior to changing the prescaler value. DS20005479D-page 163 MCP19116/7 28.2 Compare Mode The action on the pin is based on the value of the control bits, CCxM3:CCxM0. At the same time, interrupt flag bit, CCP1IF, is set. In Compare mode, the 16-bit CCDRx register value is constantly compared against the TMR1 register pair value. When a match occurs, the CMPx pin: • • • • Is driven high Is driven low Toggles Remains unchanged FIGURE 28-2: COMPARE MODE OPERATION BLOCK DIAGRAM CCDCON Mode Select Set CCDxIF Interrupt Flag (PIR1) 4 CCDRxH Q S R CCD pin Output Logic CCDRxL Comparator Match TRIS Output Enable TMR1H TMR1L Special Event Trigger Special Event Trigger will: - NOT set interrupt flag bit TMR1IF in the PIR1 register. - Set the GO/DONE bit to start the ADC conversion. 28.2.1 CMPX PIN CONFIGURATION The user must configure the CMPx pin as an output by clearing the TRIS bit for that pin. Clearing the CCxM bits will set the CMPx compare output latch to the default state. This is not the GPIO pin data latch. The default state for set-on-match or toggle-on-match is 0 but the default state for clear-on-match is 1. 28.2.2 TIMER1 MODE SELECTION Timer1 must be running off of the instruction clock for the CCD module to use the compare feature. If Timer1 is running off of the 8 MHz clock, the compare feature may not function correctly. DS20005479D-page 164 28.2.3 SOFTWARE INTERRUPT MODE When Generate Software Interrupt mode is chosen, the CCP1 pin is not affected. The CCP1IF bit is set, causing a CCx interrupt (if enabled). 28.2.4 SPECIAL EVENT TRIGGER In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The Special Event Trigger output of CCD does not reset the TMR1 register pair and starts an A/D conversion (if the A/D module is enabled). Note: The Special Event Trigger from the CCD module does not set the interrupt flag bit TMR1IF (bit 0 in the PIR1 register).  2015-2020 Microchip Technology Inc. MCP19116/7 28.3 Dual Capture/Compare Register The Dual Capture/Compare Module is a new module based on the standard CCP. It has no PWM function. REGISTER 28-1: CCDCON: DUAL CAPTURE/COMPARE CONTROL MODULE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CC2M3 CC2M2 CC2M1 CC2M0 CC1M3 CC1M2 CC1M1 CC1M0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 CC2M: CC Register Set 2 Mode Select bits 00xx = Capture/Compare off (resets the module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CC2IF bit is set) 1001 = Compare mode, clear output on match (CC2IF bit is set) 1010 = Compare mode, toggle output on match (CC2IF bit is set) 1011 = Reserved 11xx = Compare mode, generate software interrupt on match (CC2IF bit is set, CMP2 pin is unaffected and configured as an I/O) 1111 = Compare mode, trigger special event (CC2IF bit is set; CC2 does not reset TMR1(1) and starts an A/D conversion, if the A/D module is enabled. CMP2 pin is unaffected and configured as an I/O port) bit 3-0 CC1M: CC Register Set 1 Mode Select bits 00xx = Capture/Compare off (resets the module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CC1IF bit is set) 1001 = Compare mode, clear output on match (CC1IF bit is set) 1010 = Compare mode, toggle output on match (CC1IF bit is set) 1011 = Reserved 11xx = Compare mode, generate software interrupt on match (CC1IF bit is set, CMP1 pin is unaffected and configured as an I/O) 1111 = Compare mode, trigger special event (CC1IF bit is set; CC1 resets TMR1 and starts an A/D conversion, if the A/D module is enabled. CMP1 pin is unaffected and configured as an I/O port). Note 1: When the Compare interrupt is set, a PIC will typically reset TMR1. This module does NOT reset TMR1.  2015-2020 Microchip Technology Inc. DS20005479D-page 165 MCP19116/7 NOTES: DS20005479D-page 166  2015-2020 Microchip Technology Inc. MCP19116/7 29.0 29.1 The I2C interface supports the following modes and features: MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE • • • • • • • • • • • • • MSSP Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module in the MCP19116/7 only operates in Inter-Integrated Circuit (I2C) mode. Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-Master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Dual Address masking Address Hold and Data Hold modes Selectable SDA hold times Figure 29-1 is a block diagram of the I2C interface module in Master mode. Figure 29-2 is a diagram of the I2C interface module in Slave mode. FIGURE 29-1: MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal Data Bus Read [SSPxM 3:0] Write SSPBUF Baud rate generator (SSPADD) Shift Clock SDA SDA in Start bit, Stop bit, Acknowledge Generate (SSPCON2) SCL in Bus Collision  2015-2020 Microchip Technology Inc. Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Clock arbitrate/BCOL detect (Hold off clock source) Receive Enable (RCEN) SCL LSb Clock Cntl SSPSR MSb Set/Reset: S, P, SSPSTAT, WCOL, SSPxOV Reset SEN, PEN (SSPCON2) Set SSPIF, BCLIF DS20005479D-page 167 MCP19116/7 FIGURE 29-2: MSSP BLOCK DIAGRAM (I2C SLAVE MODE) Internal Data Bus Read Write SSPBUF Reg SCL If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. Shift Clock SSPSR Reg SDA LSb MSb SSPMSK1 Reg Match Detect Addr Match SSPADD Reg Start and Stop bit Detect 29.2 To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. Set, Reset S, P bits (SSPSTAT Reg) A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. I2C MODE OVERVIEW VDD The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment, where the master devices initiate the communication. A Slave device is controlled through addressing. The I 2C I2C MASTER/ SLAVE CONNECTION FIGURE 29-3: bus specifies two signal connections: • Serial Clock (SCL) • Serial Data (SDA) Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero; letting the line float is considered a logical one. Figure 29-3 shows a typical connection between two devices configured as master and slave. The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: • Master Transmit mode (master is transmitting data to a slave) • Master Receive mode (master is receiving data from a slave) • Slave Transmit mode (slave is transmitting data to a master) • Slave Receive mode (slave is receiving data from a master) DS20005479D-page 168 SCL SCL VDD Master SDA Slave SDA The Acknowledge bit (ACK) is an active-low signal which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, it repeatedly receives a byte of data from the slave and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode.  2015-2020 Microchip Technology Inc. MCP19116/7 On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in Receive mode. The I2C bus specifies three message protocols: • Single message where a master writes data to a slave • Single message where a master reads data from a slave • Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves When one device is transmitting a logical one or letting the line float and a second device is transmitting a logical zero or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. 29.2.1 CLOCK STRETCHING When a slave device has not completed processing data, it can delay the transfer of more data through the process of Clock Stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. 29.2.2 ARBITRATION Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an idle state. However, two master devices may try to initiate a transmission at or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels don't match loses arbitration and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it must also stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far the transmission appears exactly as expected, with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data.  2015-2020 Microchip Technology Inc. DS20005479D-page 169 MCP19116/7 29.3 I2C MODE OPERATION All MSSP I2C communication is byte-oriented and shifted out MSb first. Six SFR registers and two interrupt flags interface the module with the PIC microcontroller and with the user’s software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 29.3.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a Master to a Slave or vice versa, followed by an Acknowledge bit sent back. After the 8th falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained in the following sections. TABLE 29-1: 29.3.2 DEFINITION OF I2C TERMINOLOGY There is language and terminology in the description of I2C communication that have definitions specific to I2C. Such word usage is defined in Table 29-1 and may be used in the rest of this document without explanation. The information in this table was adapted from the Philips I2C specification. 29.3.3 SDA AND SCL PINS Selecting any I2C mode with the SSPEN bit set forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note: Data is tied to output zero when an I2C mode is enabled. 29.3.4 SDA HOLD TIME The hold time of the SDA pin is selected by the SDAHT bit in the SSPCON3 register. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. I2C BUS TERMS Term Description Transmitter The device that shifts data out onto the bus Receiver The device that shifts data in from the bus Master The device that initiates a transfer, generates clock signals and terminates a transfer Slave The device addressed by the master Multi-Master A bus with more than one device that can initiate data transfers Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus Idle No master is controlling the bus and both SDA and SCL lines are high Active Any time one or more master devices are controlling the bus Addressed Slave Slave device that has received a matching address and is actively being clocked by a master Matching Address Address byte that is clocked into a slave that matches the value stored in SSPADDx Write Request Slave receives a matching address with R/W bit clear and is ready to clock in data Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. The data that follows is read by the Master. A data transfer is terminated by a Stop condition which is generated by the Master. The Master could also generate a repeated START condition is applicable. Clock Stretching When a device on the bus holds SCL low to stall communication Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state DS20005479D-page 170  2015-2020 Microchip Technology Inc. MCP19116/7 29.3.5 START CONDITION 29.3.7 2 RESTART CONDITION The I C specification defines a Start condition as a transition of SDA from a high state to a low state, while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 29-4 shows the wave forms for Start and Stop conditions. A Restart is valid any time that a Stop is valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. In 10-bit Addressing Slave mode, a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. 29.3.6 STOP CONDITION A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained until a Stop condition, a high address with R/W clear or a high address match fails. Note: At least one SCL low time must appear before a Stop is valid. Therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. 29.3.8 START/STOP CONDITION INTERRUPT MASKING The SCIE and PCIE bits in the SSPCON3 register can enable the generation of an interrupt in Slave modes that do not typically support this function. These bits will have no effect on slave modes where interrupt on Start and Stop detect are already enabled. FIGURE 29-4: I2C START AND STOP CONDITIONS SDA SCL S Start condition FIGURE 29-5: P Change of data allowed Change of data allowed Stop condition I2C RESTART CONDITION Sr Change of data allowed  2015-2020 Microchip Technology Inc. Restart condition Change of data allowed DS20005479D-page 171 MCP19116/7 29.3.9 ACKNOWLEDGE SEQUENCE th 29.4.2 2 The 9 SCL pulse for any transferred byte in I C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low, indicating to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit in the SSPCON2 register. Slave software, when the AHEN and DHEN bits are set, allows the user to set the ACK value sent back to the transmitter. The ACKDT bit in the SSPCON2 register is set/cleared to determine the response. Slave hardware will generate an ACK response if the AHEN and DHEN bits in the SSPCON3 register are clear. There are certain conditions where an ACK will not be sent by the slave. If the BF bit in the SSPSTAT register or the SSPOV bit in the SSPCON1 register are set when a byte is received, the ACK will not be sent. When the module is addressed, after the 8th falling edge of SCL on the bus, the ACKTIM bit in the SSPCON3 register is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM status bit is only active when the AHEN or DHEN bits are enabled. 29.4 I2C SLAVE MODE OPERATION The MSSP Slave mode operates in one of the four modes selected in the SSPM bits in SSPCON1 register. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing mode operates the same as 7-bit, with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operate the same as the other modes, with SSPIF additionally getting set upon detection of a Start, Restart or Stop condition. 29.4.1 SLAVE MODE ADDRESSES The SSPADD register contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSPMSK1 register affects the address matching process. Refer to Section 29.4.10 “SSPMSK1 Register” for more information. DS20005479D-page 172 SECOND SLAVE MODE ADDRESS The SSPADD2 register contains a second 7-bit Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSPMSK2 register affects the address matching process. Refer to Section 29.4.10 “SSPMSK1 Register” for more information. 29.4.2.1 I2C Slave 7-Bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 29.4.2.2 I2C Slave 10-Bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb of the 10-bit address and are stored in bits 2 and 1 in the SSPADD register. After the high byte has been acknowledged, the UA bit is set and SCL is held low until the user updates SSPADD with the low address. The low-address byte is clocked in, and all 8 bits are compared to the low-address value in SSPADD. Even if there is no address match, SSPIF and UA are set and SCL is held low until SSPADD is updated to receive a high byte again. When SSPADD is updated, the UA bit is cleared. This ensures the module is ready to receive the high-address byte on the next communication. A high- and low-address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware then acknowledges the read request and prepares to clock out data. This is only valid for a slave after it has received a complete high and low address-byte match. 29.4.3 SLAVE RECEPTION When the R/W bit of a matching received address byte is clear, the R/W bit in the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and acknowledged. When an overflow condition exists for a received address, then Not Acknowledge is given. An overflow condition is defined as either bit BF in the SSPSTAT register is set, or bit SSPOV in the SSPCON1 register is set. The BOEN bit in the SSPCON3 register modifies this operation. For more information, refer to Register 29-4.  2015-2020 Microchip Technology Inc. MCP19116/7 A MSSP interrupt is generated for each transferred data byte. Flag bit SSPIF must be cleared by software. 29.4.3.2 When the SEN bit in the SSPCON2 register is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit in the SSPCON1 register, except sometimes in 10-bit mode. Slave device reception with AHEN and DHEN set operates the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants the ACK to receive address or data byte, rather than the hardware. 29.4.3.1 7-Bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C Slave in 7-bit Addressing mode, including all decisions made by hardware or software and their effect on reception. Figures 29-5 and 29-6 are used as a visual reference for this description. This is a step-by-step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Start bit detected. S bit in the SSPSTAT register is set; SSPIF is set if interrupt-on-Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low, sending an ACK to the master, and sets SSPIF bit. Software clears the SSPIF bit. Software reads received address from SSPBUF clearing the BF flag. If SEN = 1, Slave software sets CKP bit to release the SCL line. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSPIF bit. Software clears SSPIF. Software reads the received byte from SSPBUF clearing BF. Steps 8-12 are repeated for all received bytes from the Master. Master sends Stop condition, setting P bit in the SSPSTAT register, and the bus goes idle.  2015-2020 Microchip Technology Inc. 7-Bit Reception with AHEN and DHEN This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 29-7 displays a module using both address and data holding. Figure 29-8 includes the operation with the SEN bit in the SSPCON2 register set. 1. S bit in the SSPSTAT register is set; SSPIF is set if interrupt-on-Start detect is enabled. 2. Matching address with R/W bit clear is clocked in. SSPIF is set and CKP cleared after the 8th falling edge of SCL. 3. Slave clears the SSPIF. 4. Slave can look at the ACKTIM bit in the SSPCON3 register to determine if the SSPIF was after or before the ACK. 5. Slave reads the address value from SSPBUF, clearing the BF flag. 6. Slave sets ACK value clocked out to the master by setting ACKDT. 7. Slave releases the clock by setting CKP. 8. SSPxIF is set after an ACK, not after a NACK. 9. If SEN = 1 the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPIF. Note: SSPIF is still set after the 9th falling edge of SCL even if there is no clock stretching and BF has been cleared. The SSPIF is not set only when NACK is sent to Master. 11. SSPIF set and CKP cleared after 8th falling edge of SCL for a received data byte. 12. Slave looks at ACKTIM bit in the SSPCON3 register to determine the source of the interrupt. 13. Slave reads the received data from SSPBUF clearing BF. 14. Steps 7-14 are the same for each received data byte. 15. Communication is ended by either the slave sending an ACK = 1 or the master sending a Stop condition. If a Stop is sent and Interrupt-on-Stop Detect is disabled, the slave will only know by polling the P bit in the SSPSTAT register. DS20005479D-page 173 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 0, DHEN = 0) Bus Master sends Stop condition From Slave to Master Receiving Address SDA A7 A6 A5 A4 SCL S 1 2 3 4 Receiving Data A3 A2 A1 5 6 7 ACK 8 9 Receiving Data ACK = 1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 SSPIF Cleared by software BF SSPBUF is read SSPOV Cleared by software First byte of data is available in SSPBUF SSPOV set because SSPBUF is still full. ACK is not sent. 8 9 P SSPIF set on 9th falling edge of SCL MCP19116/7 DS20005479D-page 174 FIGURE 29-6:  2015-2020 Microchip Technology Inc.  2015-2020 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 29-7: Bus Master sends Stop condition Receive Address SDA SCL A7 A6 A5 A4 A3 A2 A1 S 1 2 3 4 5 6 7 R/W=0 8 9 Receive Data ACK Receive Data D7 D6 D5 D4 D3 D2 D1 D0 ACK SEN 1 2 3 4 5 6 7 8 Clock is held low until CKP is set to ‘1’ 9 ACK D7 D6 D5 D4 D3 D2 D1 D0 SEN 1 2 3 4 5 6 7 8 SSPIF Cleared by software BF SSPBUF is read SSPOV Cleared by software 9 P SSPIF set on 9th falling edge of SCL First byte of data is available in SSPBUF SSPOV set because SSPBUF is still full. ACK is not sent. CKP CKP is written to ‘1’ in software, releasing SCL CKP is written to ‘1’ in software, releasing SCL DS20005479D-page 175 MCP19116/7 SCL is not held low because ACK = 1 I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 1) Master Releases SDAx to Slave for ACK sequence Receiving Address SDA A7 A6 A5 A4 A3 A2 A1 Master sends Stop condition Receiving Data ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Received Data ACK = 1 D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF If AHEN = 1, SSPIF is set BF ACKDT CKP Address is read from SSBUF ACKTIM  2015-2020 Microchip Technology Inc. ACKTIM set by hardware on 8th falling edge of SCL P Cleared by software Data is read from SSPBUF Slave software clears ACKDT to ACK the received byte When AHEN = 1: CKP is cleared by hardware and SCL is stretched S SSPIF is set on 9th falling edge of SCL, after ACK Slave software sets ACKDT to not ACK When DHEN = 1: CKP is cleared by hardware on 8th falling edge of SCL ACKTIM cleared by hardware on 9th rising edge of SCL CKP set by software, SCL is released ACKTIM set by hardware on 8th falling edge of SCL No interrupt after not ACK from Slave MCP19116/7 DS20005479D-page 176 FIGURE 29-8:  2015-2020 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 1, DHEN = 1) FIGURE 29-9: R/W = 0 Receiving Address SDA A7 A6 A5 A4 A3 A2 A1 SCL S 1 2 3 4 5 6 7 Master sends Stop condition Master releases SDA to Slave for ACK sequence Receive Data ACK D7 D6 D5 D4 D3 D2 D1 D0 8 9 1 2 3 4 5 6 7 8 ACK Receive Data D7 D6 D5 D4 D3 D2 D1 D0 9 1 2 3 4 5 6 7 8 SSPIF Received address is loaded into SSPBUF ACKDT Slave software clears ACKDT to ACK the received byte CKP When AHEN = 1: on the 8th falling edge of SCL of an address byte, CKP is cleared ACKTIM ACKTIM is set by hardware on 8th falling edge of SCL P SSPBUF can be read any time before next byte is loaded Slave sends not ACK When DHEN = 1: on the 8th falling edge of SCL of a received data byte, CKP is cleared Set by software, release SCL CKP is not cleared if not ACK ACKTIM is cleared by hardware on 9th rising edge of SCL DS20005479D-page 177 MCP19116/7 S Received data is available on SSPBUF P No interrupt after if not ACK from Slave Cleared by software BF 9 MCP19116/7 29.4.4 SLAVE TRANSMISSION 29.4.4.2 7-Bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit in the SSPSTAT register is set. The received address is loaded into the SSPBUF register and an ACK pulse is sent by the slave on the 9th bit. A master device can transmit a read request to a slave, and then it clocks data out of the slave. The list below outlines what slave software does in order to accomplish a standard transmission. Figure 29-10 can be used as a reference to this list. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low. Refer to Section 29.4.7, Clock Stretching for more details. By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. 1. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Then the SCL pin should be released by setting the CKP bit in the SSPCON1 register. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the 9th SCL input pulse. This ACK value is copied to the ACKSTAT bit in the SSPCON2 register. If ACKSTAT is set (not ACK), the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared by software, and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the 9th clock pulse. 29.4.4.1 Slave Mode Bus Collision A slave receives a read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit in the SSPCON3 register is set, the BCLIF bit in the PIR register is set. Once a bus collision is detected, the slave goes idle and waits to be addressed again. The user’s software can use the BCLIF bit to handle a slave bus collision. DS20005479D-page 178 Master sends a Start condition on SDA and SCL. 2. S bit in the SSPSTAT register is set; SSPIF is set if interrupt-on-Start detect is enabled. 3. Matching address with R/W bit set is received by the Slave setting SSPIF bit. 4. Slave hardware generates an ACK and sets SSPIF. 5. SSPIF bit is cleared by user. 6. Software reads the received address from SSPBUF, clearing BF. 7. R/W is set so CKP was automatically cleared after the ACK. 8. The slave software loads the transmit data into SSPBUF. 9. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. 10. SSPIF is set after the ACK response from the master is loaded into the ACKSTAT register. 11. SSPIF bit is cleared. 12. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. Note 1: If the master ACKs, the clock will be stretched. 2: ACKSTAT is the only bit updated on the rising edge of SCL (9th) rather than on the falling edge. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK, the clock is not held but SSPIF is still set. 15. The master sends a Restart condition or a Stop 16. The slave is no longer addressed.  2015-2020 Microchip Technology Inc.  2015-2020 Microchip Technology Inc. FIGURE 29-10: I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 0) Master sends Stop condition Receiving Address R/W = 1 Automatic Transmitting Data Automatic Transmitting Data ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 SDA SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SSPIF Cleared by software BF Received address is read from SSPBUF Data to transmit is loaded into SSPBUF BF is automatically cleared after 8th falling edge of SCL CKP ACKSTAT When R/W is set, SCL is always held low after 9th SCL falling edge Master’s not ACK is copied to ACKSTAT R/W D/A R/W is copied from the matching address byte DS20005479D-page 179 P MCP19116/7 Indicates an address has been received S Set by software CKP is not held for not ACK MCP19116/7 29.4.4.3 7-Bit Transmission with Address Hold Enabled Setting the AHEN bit in the SSPCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPIF interrupt is set. Figure 29-11 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts idle. Master sends Start condition; the S bit in the SSPSTAT register is set; SSPIF is set if interrupt-on-Start detect is enabled. 3. Master sends matching address with R/W bit set. After the 8th falling edge of the SCL line, the CKP bit is cleared and SSPIF interrupt is generated. 4. Slave software clears SSPIF. 5. Slave software reads ACKTIM bit in the SSPCON3 register and R/W and D/A bits in the SSPSTAT register to determine the source of the interrupt. 6. Slave reads the address value from the SSPBUF register, clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK, and sets ACKDT bit in the SSPCON2 register accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPIF after the ACK if the R/W bit is set. 11. Slave software clears SSPIF. 12. Slave loads value to transmit to the master into SSPBUF setting the BF bit. Note: SSPBUF cannot be loaded until after the ACK. 13. Slave sets CKP bit releasing the clock. 14. Master clocks out the data from the slave and sends an ACK value on the 9th SCL pulse. 15. Slave hardware copies the ACK value into the ACKSTAT bit in the SSPCON2 register. 16. Steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. If the master sends a not ACK, the slave releases the bus, allowing the master to send a Stop and end the communication. Note: Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. DS20005479D-page 180  2015-2020 Microchip Technology Inc.  2015-2020 Microchip Technology Inc. I2C SLAVE, 7-BIT ADDRESS, TRANSMISSION (AHEN = 1) FIGURE 29-11: Master sends Stop condition Receiving Address R/W = 1 SDA SCL A7 A6 A5 A4 A3 A2 A1 S 1 2 3 4 5 6 7 8 9 SSPIF BF Automatic Transmitting Data Automatic Transmitting Data ACK ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P Cleared by software Received address is read from SSPBUF Data to transmit is loaded into SSPBUF BF is automatically cleared after 8th falling edge of SCL ACKDT Slave clears ACKDT to ACK address ACKSTAT Master’s ACK response is copied to SSPSTAT CKP ACKTIM DS20005479D-page 181 D/A ACKTIM is set on 8th falling edge of SCL When R/W = 1: CKP is always cleared after ACK Set by software, releases SCL ACKTIM is set on 9th rising edge of SCL CKP not cleared after not ACK MCP19116/7 R/W When AHEN = 1: CKP is cleared by hardware after receiving matching address. MCP19116/7 29.4.5 SLAVE MODE 10-BIT ADDRESS RECEPTION This section describes a standard sequence of events for the MSSP module configured as an I2C Slave in 10-bit Addressing mode. Figure 29-12 is used as a visual reference for this description. This is a step-by-step process of what must be done by slave software to accomplish I2C communication: 1. 2. 3. 4. 5. 6. 7. 8. Bus starts idle. Master sends Start condition; S bit in the SSPSTAT register is set; SSPIF is set if interrupt-on-Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit in the SSPSTAT register is set. Slave sends ACK and SSPIF is set. Software clears the SSPIF bit. Software reads received address from SSPBUF, clearing the BF flag. Slave loads low address into SSPADD, releasing SCL. Master sends matching low-address byte to the Slave; UA bit is set. 29.4.6 10-BIT ADDRESSING WITH ADDRESS OR DATA HOLD Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and the SCL line is held low, is the same. Figure 29-13 can be used as a reference of a slave in 10-bit addressing with AHEN set. Figure 29-14 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. Note: Updates to the SSPADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPIF is set. Note: If the low address does not match, SSPIF and UA are still set so that the slave software can set SSPADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. Slave clears SSPIF. 11. Slave reads the received matching address from SSPBUF, clearing BF. 12. Slave loads high address into SSPADD. 13. Master clocks a data byte to the slave and clocks out the slave’s ACK on the 9th SCL pulse; SSPIF is set. 14. If SEN bit in the SSPCON2 register is set, CKP is cleared by hardware and the clock is stretched. 15. Slave clears SSPIF. 16. Slave reads the received byte from SSPBUF, clearing BF. 17. If SEN is set, the slave sets CKP to release the SCL. 18. Steps 13-17 are repeated for each received byte. 19. Master sends Stop to end the transmission. DS20005479D-page 182  2015-2020 Microchip Technology Inc.  2015-2020 Microchip Technology Inc. I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 1, AHEN = 0, DHEN = 0) FIGURE 29-12: Master sends Stop condition Receive First Address Byte SDA S SSPIF BF UA ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK 1 1 1 1 0 A9 A8 SCL 1 2 3 4 5 6 7 Receive Data Receive Data Receive Second Address Byte 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 P SCL is held low while CKP = 0 Set by hardware on 9th falling edge Cleared by software Receive address is read from SSPBUF If address matches SSPADD, it is loaded into SSPBUF When UA = 1: SCL is held low Data is read from SSPBUF Software updates SSPADD and releases SCL CKP Set by software, releasing SCL DS20005479D-page 183 MCP19116/7 When SEN = 1: CKP is cleared after 9th falling edge of received byte Receive First Address Byte SDA SCL S 1 1 1 1 0 A9 A8 1 2 3 4 5 6 7 R/W = 0 Receive Second Address Byte ACK A7 A6 A5 A4 A3 A2 A1 A0 8 9 UA 1 2 3 4 5 6 7 8 Receive Data Receive Data ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK D7 D6 D5 9 UA 1 2 3 4 5 6 7 8 9 1 2 SSPIF Set by hardware on 9th falling edge Cleared by software Cleared by software BF ACKDT Slave software clears ACKDT to ACK the received byte SSPBUF can be read anytime before the next received cycle Received data is read from SSPBUF UA Update to SSPADD is not allowed until 9th falling edge of SCL  2015-2020 Microchip Technology Inc. If when AHEN = 1: on the 8th falling edge of SCL of an address byte, CKP is ACKTIM cleared ACKTIM is set by hardware on 8th falling edge of SCL CKP Update of SSPADD, clears UA and releases SCL Set CKP with software releases SCL MCP19116/7 DS20005479D-page 184 I2C SLAVE, 10-BIT ADDRESS, RECEPTION (SEN = 0, AHEN = 1, DHEN = 0) FIGURE 29-13:  2015-2020 Microchip Technology Inc. FIGURE 29-14: I2C SLAVE, 10-BIT ADDRESS, TRANSMISSION (SEN = 0, AHEN = 0, DHEN = 0) Master sends Master sends Stop condition not ACK Master sends Restart event Receiving Address R/W = 0 Receiving Second Address Byte 1 1 1 1 0 A9 A8 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK SDA SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Receive First Address Byte 1 1 1 1 0 A9 A8 ACK 1 2 3 4 5 6 7 8 9 Transmitting Data Byte ACK = 1 D7 D6 D5 D4D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 Sr P SSPIF Set by hardware BF UA CKP Cleared by software Received address is read from SSPBUF SSPBUF loaded with received address UA indicates SSPADD must be updated ACKSTAT Set by hardware After SSPADD is updated. UA is cleared and SCL is released Data to transmit is loaded into SSPBUF High address is loaded back into SSPADD When R/W = 1: CKP is cleared on 9th falling edge of SCLx Set by software releases SCL Master’s not ACK is copied R/W R/W is copied from the matching address byte Indicates an address has been received DS20005479D-page 185 MCP19116/7 D/A MCP19116/7 29.4.7 CLOCK STRETCHING 29.4.7.2 Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching, as it is stretching anytime it is active on the bus and not transferring data. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit in the SSPCON1 register is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 29.4.7.1 Normal Clock Stretching Following an ACK, if the R/W bit in the SSPSTAT register is set, causing a read request, the slave hardware will clear CKP. This allows the slave time to update SSPBUF with data to transfer to the master. If the SEN bit in the SSPCON2 register is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready, CKP is set by software and communication resumes. Note 1: The BF bit has no effect on whether the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock or clear CKP if SSPBUF was read before the 9th falling edge of SCL. 2: Previous versions of the module did not stretch the clock for a transmission if SSPBUF was loaded before the 9th falling edge of SCL. It is now always cleared for read requests. FIGURE 29-15: 10-Bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSPADD. Note: 29.4.7.3 Previous versions of the module did not stretch the clock if the second address byte did not match. Byte NACKing When AHEN bit in the SSPCON3 register is set, CKP is cleared by hardware after the 8th falling edge of SCL for a received matching address byte. When DHEN bit in the SSPCON3 register is set, CKP is cleared after the 8th falling edge of SCL for received data. Stretching after the 8th falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 29.4.8 CLOCK SYNCHRONIZATION AND THE CKP BIT Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high-time requirement for SCL (refer to Figure 29-16). CLOCK SYNCHRONIZATION TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX DX ‚ – 1 SCL CKP Master device asserts clock Master device releases clock WR SSPCON1 DS20005479D-page 186  2015-2020 Microchip Technology Inc. MCP19116/7 29.4.9 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device is the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. If the AHEN bit in the SSPCON3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of SCL. The slave must then set its ACKDT value and release the clock with communication progressing as it would normally. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit in the SSPCON2 register is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPBUF and respond. Figure 29-7 shows a general call reception sequence. FIGURE 29-16: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE Address is compared to General Call Address after ACK, set interrupt Receiving Data ACK R/W = 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SSPIF BF (SSPSTAT) GCEN (SSPCON2) Cleared by software SSPBUF is read ‘1’ 29.4.10 SSPMSK1 REGISTER An SSP Mask (SSPMSK1) register is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK1 register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSPMSK1 register is active during: • 7-bit Address mode: address compare of A • 10-bit Address mode: address compare of A only. The SSP mask has no effect during the reception of the first (high) byte of the address  2015-2020 Microchip Technology Inc. DS20005479D-page 187 MCP19116/7 29.5 I2C MASTER MODE Master mode is enabled by setting and clearing the appropriate SSPM bits in the SSPCON1 register and by setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary, to drive the pins low. The Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set or the bus is idle. In Firmware-Controlled Master mode, user code conducts all I 2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user’s software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit (SSPIF) to be set (SSP interrupt, if enabled): • • • • • Start condition detected Stop condition detected Data-transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Note 1: The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPBUF register to initiate transmission before the Start condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. 2: When in Master mode, Start/Stop detection is masked and an interrupt is generated when the SEN/PEN bit is cleared and the generation is complete. DS20005479D-page 188 29.5.1 I2C MASTER MODE OPERATION The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus is not released. In Master Transmit mode, serial data is output through SDA while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit is logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit is logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. Refer to Section 29.6 “Baud Rate Generator” for more details. 29.5.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any Receive, Transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device (Figure 29-17).  2015-2020 Microchip Technology Inc. MCP19116/7 FIGURE 29-17: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX ‚ – 1 SCL deasserted but Slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BGR decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 29.5.3 WCOL STATUS FLAG If the user writes the SSPBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set, it indicates that an action on SSPBUF was attempted while the module was not idle. Note: 29.5.4 Because queuing of events is not allowed, writing to the lower five bits in the SSPCON2 register is disabled until the Start condition is complete. I2C MASTER MODE START CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN, in the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action FIGURE 29-18: of the SDA being driven low while SCL is high is the Start condition, and causes the S bit in the SSPSTAT1 register to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPADD and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit in the SSPCON2 register will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Note 1: If, at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if, during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag (BCLIF) is set, the Start condition is aborted and the I2C module is reset into its idle state. 2: The Philips I2C Specification states that a bus collision cannot occur on a Start. FIRST START BIT TIMING Write to SEN bit occurs here Set S bit (SSPSTAT) At completion of Start bit, SDA = 1, hardware clears SEN bit SCL = 1 and sets SSPIF bit TBRG TBRG SDA Write to SSPBUF occurs here 1st bit 2nd bit TBRG SCL S  2015-2020 Microchip Technology Inc. TBRG DS20005479D-page 189 MCP19116/7 29.5.5 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it does not take effect. A Repeated Start condition occurs when the RSEN bit in the SSPCON2 register is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit in the SSPCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on the SDA and SCL pins, the S bit in the SSPSTAT register is set. The SSPIF bit will not be set until the Baud Rate Generator has timed out. FIGURE 29-19: 2: A bus collision during the Repeated Start condition occurs if: • SDA is sampled low when SCL goes from low to high • SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’ REPEAT START CONDITION WAVEFORM Write to SSPCON2 occurs here SDA = 1, SCL (no change) S bit set by hardware At completion of Start bit, hardware clears RSEN bit and sets SSPIF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSPBUF occurs here TBRG SCL Sr Repeated Start DS20005479D-page 190 TBRG  2015-2020 Microchip Technology Inc. MCP19116/7 29.5.6 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action sets the Buffer Full (BF) flag bit and allows the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data is shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the 8th bit is shifted out (the falling edge of the 8th clock), the BF flag is cleared and the master releases the SDA. This allows the slave device being addressed to respond with an ACK bit during the 9th bit time if an address match occurred or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the 9th clock. If the master receives an Acknowledge, the Acknowledge Status bit (ACKSTAT) is cleared. If not, the bit is set. After the 9th clock, the SSPIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 29-20). After the write to the SSPBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the 8th clock, the master releases the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the 9th clock, the master samples the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit in the SSPCON2 register. Following the falling edge of the 9th clock transmission of the address, the SSPIF is set, the BF flag is cleared and the Baud Rate Generator is turned off until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 29.5.6.1 BF Status Flag In Transmit mode, the BF bit in the SSPSTAT register is set when the CPU writes to SSPBUF and is cleared when all eight bits are shifted out.  2015-2020 Microchip Technology Inc. 29.5.6.2 WCOL Status Flag If the user writes the SSPBUF when a Transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write does not occur). WCOL must be cleared by software before the next transmission. 29.5.6.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit in the SSPCON2 register is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call) or when the slave has properly received its data. 29.5.6.4 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Typical Transmit Sequence The user generates a Start condition by setting the SEN bit in the SSPCON2 register. SSPIF is set by hardware on completion of the Start. SSPIF is cleared by software. The MSSP module waits the required start time before any other operation takes place. The user loads the SSPBUF with the slave address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit in the SSPCON2 register. The MSSP module generates an interrupt at the end of the 9th clock cycle by setting the SSPIF bit. The user loads the SSPBUF with eight bits of data Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit in the SSPCON2 register. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits in the SSPCON2 register. Interrupt is generated once the Stop/Restart condition is complete. DS20005479D-page 191 ACKSTAT in SSPCON2 = 1 Write SSPCON2 SEN = 1 From slave, clear ACKSTAT bit SSPCON2 Transmitting Data or Second Half of 10-bit Address Start condition begins SEN = 0 Transmit Address to Slave SDA A7 A6 A5 A4 A3 R/W = 0 A2 ACK = 0 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 SSPBUF written with 7-bit address and R/W start transmit SCL S 1 2 3 4 5 6 7 8 9 SCL held low while CPU responds to SSPIF 9 P SSPIF Cleared by software Cleared by software service routine from SSP interrupt BF (SSPSTAT) SSPBUF written SEN After Start condition, SEN cleared by hardware  2015-2020 Microchip Technology Inc. PEN R/W SSPBUF is written by software Cleared by software MCP19116/7 DS20005479D-page 192 I2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) FIGURE 29-20: MCP19116/7 29.5.7 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable (RCEN) bit in the SSPCON2 register. 29.5.7.4 1. 2. Note: The MSSP module must be in an idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and, upon each rollover, the state of the SCL pin changes (high-to-low/low-to-high) and data is shifted into the SSPSR. After the falling edge of the 8th clock, the receive enable flag is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF flag bit is set, the SSPIF flag bit is set and the Baud Rate Generator is suspended from counting, holding SCL low. The MSSP is now in idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable (ACKEN) bit in the SSPCON2 register. 29.5.7.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read. 29.5.7.2 SSPOV Status Flag 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. In receive operation, the SSPOV bit is set when 8 bits are received into the SSPSR and the BF flag bit is already set from a previous reception. 13. 14. 29.5.7.3 15. WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur).  2015-2020 Microchip Technology Inc. Typical Receive Sequence The user generates a Start condition by setting the SEN bit in the SSPCON2 register. SSPIF is set by hardware on completion of the Start. SSPIF is cleared by software User writes SSPBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit in the SSPCON2 register. The MSSP module generates an interrupt at the end of the 9th clock cycle by setting the SSPIF bit. User sets the RCEN bit in the SSPCON2 register and the Master clocks in a byte from the slave. After the 8th falling edge of SCL, SSPIF and BF are set. Master clears SSPIF and reads the received byte from SSPUF, then clears BF. Master sets ACK value sent to slave in ACKDT bit in the SSPCON2 register and initiates the ACK by setting the ACKEN bit. Masters ACK is clocked out to the slave and SSPIF is set. The user clears SSPIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. DS20005479D-page 193 I2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Write to SSPCON2 to start Acknowledge sequence SDA = ACKDT (SSPCON2) = 0 Write to SSPCON2 (SEN = 1), ACK from Master begin Start condition Master configured as a receiver SDA = ACKDT = 0 SEN = 0 by programming SSPCON2 (RCEN = 1) Write to SSPBUF RCEN = 1, start RCEN cleared ACK from Slave occurs here, start XMIT next receive automatically A7 A6 A5 A4 A3 A2 A1 R/W ACK D7 D6 D5 D4 D3 D2 D1 RCEN cleared automatically PEN bit = 1 written here Receiving Data from Slave Receiving Data from Slave SDA Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 ACK D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK ACK is not sent SCL S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 9 8 SSPIF Cleared by software Cleared by software Cleared by software BF (SSPSTAT) 2 3 4 5 6 7 8 9 Data shifted in on falling edge of CLK Set SSPIF Set SSPIF interrupt at end of receive at end of Acknowledge sequence Set SSPIF interrupt at end of receive SDA = 0, SCLx = 1 while CPU responds to SSPxIR 1 Cleared by software Cleared by software P Bus master terminates transfer Set SSPIF interrupt at end of Acknowledge sequence Set P bit (SSPSTAT) and SSPIF Last bit is shifted into SSPSR and contents are unloaded into SSPBUF SSPOV SSPOV is set because SSPBUF is still full  2015-2020 Microchip Technology Inc. ACKEN RCEN Master configured as a receiver by programming SSPCON2 (RCEN = 1) RCEN cleared automatically ACK from Master SDA = ACKDT = 0 RCEN cleared automatically MCP19116/7 DS20005479D-page 194 FIGURE 29-21: MCP19116/7 29.5.8 ACKNOWLEDGE SEQUENCE TIMING 29.5.9 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit (PEN) in the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the 9th clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be brought high and then, one TBRG (Baud Rate Generator rollover count) later, the SDA pin is deasserted. When the SDA pin is sampled high while SCL is high, the P bit in the SSPSTAT register, is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 29-23). An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable (ACKEN) bit in the SSPCON2 register. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode (Figure 29-22). 29.5.8.1 STOP CONDITION TIMING 29.5.9.1 WCOL Status Flag If the user writes the SSPBUF when a Stop sequence is in progress, the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). WCOL Status Flag If the user writes the SSPBUF when an Acknowledge sequence is in progress, WCOL is set and the contents of the buffer are unchanged (the write does not occur). FIGURE 29-22: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, write to SSPCON2 ACKEN = 1, ACKDT = 0 SDA ACKEN automatically cleared SCL TBRG TBRG D0 ACK 8 9 SSPIF SSPIF set at the end of receive Note: TBRG = one Baud Rate Generator period. FIGURE 29-23: Cleared in software STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT) is set. PEN bit (SSPCON2) is cleared by hardware and the SSPIF bit is set Write to SSPCON2, set PEN Falling edge of 9th clock TBRG SCL SDA ACK TBRG Note: Cleared in software SSPIF set at the end of Acknowledge sequence P TBRG TBRG SCL brought high after TBRG TBRG = one Baud Rate Generator period.  2015-2020 Microchip Technology Inc. DS20005479D-page 195 MCP19116/7 29.5.10 SLEEP OPERATION 29.5.13 2 While in Sleep mode, the I C slave module can receive addresses or data and, when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 29.5.11 EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. 29.5.12 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSPx module is disabled. Control of the I 2C bus may be taken when the P bit in the SSPSTAT register is set or the bus is idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt generates the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLIF bit. The states where arbitration can be lost are: • • • • • Address Transfer Data Transfer a Start Condition a Repeated Start Condition an Acknowledge Condition MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA by letting SDA float high, and another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, a bus collision has taken place. The master sets the Bus Collision Interrupt Flag (BCLIF) and resets the I2C port to its Idle state (Figure 29-24). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master continues to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPIF bit is set. A write to the SSPBUF starts the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is idle and the S and P bits are cleared. FIGURE 29-24: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low Sample SDA. While SCL is high, by another source data does not match what is driven by the master. Bus collision has occurred. SDA released by master SDA SCL Set Bus Collision Interrupt (BCLIF) BCLIF DS20005479D-page 196  2015-2020 Microchip Technology Inc. MCP19116/7 29.5.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 29-25) SCL is sampled low before SDA is asserted low (Figure 29-26) During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 29-27). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: If the SDA pin is already low or the SCL pin is already low, all of the following occur: • the Start condition is aborted • the BCLIF flag is set • the MSSP module is reset to its Idle state (Figure 29-25) The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. FIGURE 29-25: The reason for which bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. BUS COLLISION DURING A START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN BCLIF SEN cleared automatically because of bus collision. SSP module reset into Idle state. SDA sampled low before Start condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared by software S SSPIF SSPIF and BCLIF are cleared by software  2015-2020 Microchip Technology Inc. DS20005479D-page 197 MCP19116/7 FIGURE 29-26: BUS COLLISION DURING A START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA SCL Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time out, bus collision occurs. Set BCLIF. BCLIF S ‘0’ SSPIF ‘0’ FIGURE 29-27: Interrupt cleared by software ‘0’ ‘0’ BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPIF TBRG SDA pulled low by other master. Reset BRG and assert SDAx. SCL s SCLx pulled low after BRG time out SEN BCLIF Set SEN, enable Start sequence if SDA = 1, SCL = 1 ‘0’ S SSPIF DS20005479D-page 198 SDAx = 0, SCL = 1, set SSPIF Interrupts cleared by software  2015-2020 Microchip Technology Inc. MCP19116/7 29.5.13.2 Bus Collision during a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 29-28). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) a low level is sampled on SDA when SCL goes from low level to high level SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’ If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition (refer to Figure 29-29). When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPADD and counts down to zero. The SCL pin is then deasserted and, when sampled high, the SDA pin is sampled. FIGURE 29-28: If, at the end of the BRG time out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared by software ‘0’ S ‘0’ SSPIF FIGURE 29-29: BUS COLLISION DURING A REPEATED START CONDITION (CASE 2) TBRG TBRG SDA SCL BCLIF SCL goes low before SDA, set BCLIF. Release SDA and SCL. RSEN Interrupt cleared by software S ‘0’ SSPIF ‘0’  2015-2020 Microchip Technology Inc. DS20005479D-page 199 MCP19116/7 29.5.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 29-30). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure 29-31). Bus collision occurs during a Stop condition if: a) b) after the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out after the SCL pin is deasserted, SCL is sampled low before SDA goes high FIGURE 29-30: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG TBRG SDA sampled low after TBRG, set BCLIF TBRG SDA SCL SDA asserted low PEN BCLIF P ‘0’ SSPIF ‘0’ FIGURE 29-31: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG SDA Assert SDA TBRG TBRG SCL goes low before SDA goes high, set BCLIF SCL PEN BCLIF P ‘0’ SSPIF ‘0’ DS20005479D-page 200  2015-2020 Microchip Technology Inc. MCP19116/7 TABLE 29-2: SUMMARY OF REGISTERS ASSOCIATED WITH I2C OPERATION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INTCON GIE PEIE T0IE INTE IOCE T0IF INTF IOCF 107 PIE1 TXIE RCIE BCLIE SSPIE CC2IE CC1IE TMR2IE TMR1IE 108 TXIF RCIF BCLIF SSPIF CC2IF CC1IF TMR2IF TMR1IF 110 TRISGPA PIR1 TRISA7 TRISA6 TRISA5 — TRISA3 TRISA2 TRISA1 TRISA0 127 TRISGPB TRISB7 TRISB6 TRISB5 TRISB4 — — TRISB1 TRISB0 131 SSPADD ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 208 WCOL SSPOV SSPEN CKP SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN SSPCON3 ACKTIM PCIE SCIE BOEN SDAHT SBCDE SSPMSK1 MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 208 SSPSTAT SMP CKE D/A P S R/W UA BF 203 SSPMSK2 MSK27 MSK26 MSK25 MSK24 MSK23 MSK22 MSK21 MSK20 209 SSPADD2 ADD27 ADD26 ADD25 ADD24 ADD23 ADD22 ADD21 ADD20 209 SSPBUF SSPCON1 Synchronous Serial Port Receive Buffer/Transmit Register SSPM3 SSPM2 167* SSPM1 SSPM0 204 RSEN SEN 206 AHEN DHEN 207 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP module in I * Page provides register information.  2015-2020 Microchip Technology Inc. 2C mode. DS20005479D-page 201 MCP19116/7 29.6 Baud Rate Generator The MSSP module has a Baud Rate Generator available for clock generation in the I2C Master mode. The Baud Rate Generator (BRG) reload value is placed in the SSPADD register. When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock automatically stops counting and the clock pin remains in its last state. An internal signal “Reload” in Figure 29-32 triggers the value from SSPADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode the MSSP is being operated in. Table 29-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD. EQUATION 29-1: FOSC F CLOCK = --------------------------------------------- SSPADD + 1   4  FIGURE 29-32: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM SSPM SCL Reload Control SSPCLK Note: Reload BRG Down Counter FOSC/2 Values of 0x00, 0x01 and 0x02 are not valid for SSPADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. TABLE 29-3: Note 1: SSPADD MSSP CLOCK RATE W/BRG FCLOCK (2 rollovers of BRG) FOSC FCY BRG Value 8 MHz 2 MHz 04h 400 kHz (1) 8 MHz 2 MHz 0Bh 166 kHz 8 MHz 2 MHz 13h 100 kHz The I2C interface does not conform to the 400 kHz I2C specification (which applies to rates greater than 100 kHz) in all details, but may be used with care where higher rates are required by the application. DS20005479D-page 202  2015-2020 Microchip Technology Inc. MCP19116/7 REGISTER 29-1: SSPSTAT: SSP STATUS REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: Data Input Sample bit 1 = Slew rate control disabled for standard-speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high-speed mode (400 kHz) bit 6 CKE: Clock Edge Select bit 1 = Enable input logic so that thresholds are compliant with SM bus specification 0 = Disable SM bus specific inputs bit 5 D/A: Data/Address bit 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4 P: Stop bit (This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Stop bit has been detected last (this bit is ‘0’ on Reset) 0 = Stop bit was not detected last bit 3 S: Start bit (This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a Start bit has been detected last (this bit is ‘0’ on Reset) 0 = Start bit was not detected last bit 2 R/W: Read/Write bit information This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit, or not ACK bit In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Idle mode bit 1 UA: Update Address bit (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0 BF: Buffer Full status bit Receive: 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit: 1 = Data transmit in progress (does not include the ACK and Stop bits), SSPBUF is full 0 = Data transmit complete (does not include the ACK and Stop bits), SSPBUF is empty  2015-2020 Microchip Technology Inc. DS20005479D-page 203 MCP19116/7 REGISTER 29-2: SSPCON1:SSP CONTROL REGISTER 1 R/C/HS-0 R/C/HS-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP R/W-0 R/W-0 R/W-0 R/W-0 SSPM bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit (1) 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode (must be cleared in software) 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins (2) 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In I2 C Slave mode: SCL release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time) In I2 C Master mode: Unused in this mode Note 1: 2: 3: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. When enabled, the SDA and SCL pins must be configured as inputs. SSPADD values of 0, 1 or 2 are not supported for I2C mode. DS20005479D-page 204  2015-2020 Microchip Technology Inc. MCP19116/7 REGISTER 29-2: bit 3-0 SSPCON1:SSP CONTROL REGISTER 1 (CONTINUED) SSPM: Synchronous Serial Port Mode Select bits 0000 = Reserved 0001 = Reserved 0010 = Reserved 0011 = Reserved 0100 = Reserved 0101 = Reserved 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC/(4 * (SSPADD+1)) (3) 1001 = Reserved 1010 = Reserved 1011 = I2C Firmware-Controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with Start and Stop bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with Start and Stop bit interrupts enabled Note 1: 2: 3: In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. When enabled, the SDA and SCL pins must be configured as inputs. SSPADD values of 0, 1 or 2 are not supported for I2C mode.  2015-2020 Microchip Technology Inc. DS20005479D-page 205 MCP19116/7 REGISTER 29-3: R/W-0/0 SSPCON2: SSP CONTROL REGISTER 2 R-0/0 GCEN ACKSTAT R/W-0/0 R/S/HS-0/0 ACKDT (1) ACKEN R/S/HS-0/0 RCEN (1) R/S/HS-0/0 PEN (1) R/S/HS-0/0 RSEN (1) R/W/HS-0/0 SEN (1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware S = User set bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0x00 or 00h) is received in the SSPSR register 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C mode only) 1 = Acknowledge was not received 0 = Acknowledge was received bit 5 ACKDT: Acknowledge Data bit (in I2C mode only) In Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (in I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins and transmit ACKDT data bit. Automatically cleared by hardware 0 = Acknowledge sequence idle bit 3 RCEN: Receive Enable bit (in I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle bit 2 PEN: Stop Condition Enable bit (in I2C Master mode only) SCK Release Control: 1 = Initiate Stop condition on SDA and SCL pins. Automatically cleared by hardware 0 = Stop condition idle bit 1 RSEN: Repeated Start Condition Enabled bit (in I2C Master mode only) 1 = Initiate Repeated Start condition on SDA and SCL pins. Automatically cleared by hardware 0 = Repeated Start condition idle bit 0 SEN: Start Condition Enabled bit (in I2C Master mode only) In Master mode: 1 = Initiate Start condition on SDA and SCL pins. Automatically cleared by hardware 0 = Start condition idle In Slave mode: 1 = Clock stretching is enabled for both Slave Transmit and Slave Receive (stretch enabled) 0 = Clock stretching is disabled Note 1: If the I2C module is not in Idle mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). DS20005479D-page 206  2015-2020 Microchip Technology Inc. MCP19116/7 REGISTER 29-4: SSPCON3: SSP CONTROL REGISTER 3 R-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 R/W-0/0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time status bit (I2C mode only) (1) 1 = Indicates the I2C bus is in an Acknowledge sequence, set on 8th falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock bit 6 PCIE: Stop Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled (2) bit 5 SCIE: Start Condition Interrupt Enable bit (I2C mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled (2) bit 4 BOEN: Buffer Overwrite Enable bit In I2C Master mode: This bit is ignored. In I2C Slave mode: 1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state of the SSPOV bit only if the BF bit = 0. 0 = SSPBUF is only updated when SSPOV is clear. bit 3 SDAHT: SDA Hold Time Selection bit 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL bit 2 SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only) If, on the rising edge of SCL, SDA is sampled low when the module outputs a high state, the BCLIF bit in the PIR1 register is set and bus goes idle. 1 = Enable slave bus collision interrupts 0 = Slave bus collision interrupts are disabled bit 1 AHEN: Address Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit in the SSPCON1 register is cleared and the SCL is held low 0 = Address holding is disabled bit 0 DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit in the SSPCON1 register and SCL is held low 0 = Data holding is disabled Note 1: 2: The ACKTIM status bit is only active when the AHEN bit or DHEN bit is set. This bit has no effect in Slave modes where Start and Stop condition detection is explicitly listed as enabled.  2015-2020 Microchip Technology Inc. DS20005479D-page 207 MCP19116/7 REGISTER 29-5: R/W-1 SSPMSK1: SSP MASK REGISTER 1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK R/W-1 MSK bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK: Mask bits 1 = The received address bit n is compared to SSPADD to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM = 0111 or 1111): 1 = The received address bit 0 is compared to SSPADD to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 29-6: R/W-0 SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD: Baud Rate Clock Divider bits SCL pin clock period = ((ADD + 1) * 4)/FOSC 10-Bit Slave mode — Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register bit 2-1 ADD: Two Most Significant bits of 10-bit address. bit 0 Not used: Unused in this mode. Bit state is a “don’t care” 10-Bit Slave mode — Least Significant Address byte: bit 7-0 ADD: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care” DS20005479D-page 208  2015-2020 Microchip Technology Inc. MCP19116/7 REGISTER 29-7: R/W-1 SSPMSK2: SSP MASK REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 MSK2 R/W-1 MSK2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-1 MSK2: Mask bits 1 = The received address bit n is compared to SSPADD2 to detect I2C address match 0 = The received address bit n is not used to detect I2C address match bit 0 MSK2: Mask bit for I2C Slave mode, 10-bit Address I2C Slave mode, 10-bit address (SSPM = 0111 or 1111): 1 = The received address bit 0 is compared to SSPADD2 to detect I2C address match 0 = The received address bit 0 is not used to detect I2C address match I2C Slave mode, 7-bit address, the bit is ignored REGISTER 29-8: R/W-0 SSPADD2: MSSP ADDRESS 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD2: Baud Rate Clock Divider bits SCL pin clock period = ((ADD + 1) * 4)/FOSC 10-Bit Slave mode — Most Significant Address byte: bit 7-3 Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pattern sent by master is fixed by I2C specification and must be equal to ‘11110’. However, those bits are compared by hardware and are not affected by the value in this register bit 2-1 ADD2: Two Most Significant bits of 10-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care” 10-Bit Slave mode — Least Significant Address byte: bit 7-0 ADD2: Eight Least Significant bits of 10-bit address 7-Bit Slave mode: bit 7-1 ADD2: 7-bit address bit 0 Not used: Unused in this mode. Bit state is a “don’t care”  2015-2020 Microchip Technology Inc. DS20005479D-page 209 MCP19116/7 NOTES: DS20005479D-page 210  2015-2020 Microchip Technology Inc. MCP19116/7 30.0 INSTRUCTION SET SUMMARY The MCP19116/7 instruction set is highly orthogonal and is comprised of three basic categories: TABLE 30-1: OPCODE FIELD DESCRIPTIONS Field Description • Byte-oriented operations • Bit-oriented operations • Literal and control operations W Working register (accumulator) Each instruction is a 14-bit word divided into: b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip Technology Inc. software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1. • an opcode, which specifies the instruction type • one or more operands, which further specify the operation of the instruction. The formats for each of the categories is presented in Figure 30-1, while the various opcode fields are summarized in Table 30-1. Table 30-2 lists the instructions recognized by the MPASMTM assembler. For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If ‘d’ is 0, the result is placed in the W register. If ‘d’ is 1, the result is placed in the file register specified in the instruction. For bit-oriented instructions, ‘b’ represents a bit field designator, which selects the bit affected by the operation, while ‘f’ represents the address of the file in which the bit is located. For literal and control operations, ‘k’ represents an 8-bit or 11-bit constant, or literal value. f Register file address (0x00 to 0x7F) PC TO C DC Z Program Counter Time-Out bit Carry bit Digit carry bit Zero bit PD Power-down bit FIGURE 30-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 OPCODE d f (FILE #) d = 0 for destination W d = 1 for destination f f = 7-bit file register address One instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 MHz, this gives a normal instruction execution time of 1 µs. All instructions are executed within a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second cycle executed as a NOP. Bit-oriented file register operations 13 10 9 7 6 OPCODE b (BIT #) f (FILE #) All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. Literal and control operations 30.1 Read-Modify-Write Operations Any instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (RMW) operation. The register is read, the data is modified, and the result is stored according to either the instruction or the destination designator ‘d’. A read operation is performed on a register even if the instruction writes to that register. 0 0 b = 3-bit address f = 7-bit file register address General 13 8 7 OPCODE 0 k (literal) k = 8-bit immediate value CALL and GOTO instructions only 13 11 OPCODE 10 0 k (literal) k = 11-bit immediate value For example, a CLRF PORTA instruction will read PORTGPA, clear all the data bits, then write the result back to PORTGPA. This example would have the unintended consequence of clearing the condition that sets the IOCIF flag.  2015-2020 Microchip Technology Inc. DS20005479D-page 211 MCP19116/7 TABLE 30-2: MCP19116/7 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff C, DC, Z ffff Z ffff Z xxxx Z ffff Z ffff Z ffff ffff Z ffff ffff Z ffff Z ffff 0000 ffff C ffff C ffff C, DC, Z ffff ffff Z 1, 2 1, 2 2 bfff bfff bfff bfff ffff ffff ffff ffff 1, 2 1, 2 3 3 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk C, DC, Z kkkk Z kkkk 0100 TO, PD kkkk Z kkkk kkkk 1001 kkkk 1000 0011 TO, PD kkkk C, DC, Z Z kkkk 1, 2 1, 2 1, 2, 3 1, 2 1, 2, 3 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 1, 2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW Note 1: 2: 3: k k k – k k k – k – – k k Add literal and W AND literal with W Call Subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into Standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 When an I/O register is modified as a function of itself (e.g., MOVF PORTA, 1), the value used will be that value present on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external device, the data will be written back with a ‘0’. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 module. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS20005479D-page 212  2015-2020 Microchip Technology Inc. MCP19116/7 30.2 Instruction Descriptions ADDLW Add literal and W Syntax: [ label ] ADDLW Operands: 0  k  255 Operation: (W) + k  (W) Status Affected: Description: BCF Bit Clear f Syntax: [ label ] BCF Operands: 0  f  127 0b7 C, DC, Z Operation: 0  (f) The contents of the W register are added to the 8-bit literal ‘k’ and the result is placed in the W register. Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. ADDWF Add W and f BSF Bit Set f Syntax: [ label ] ADDWF Syntax: [ label ] BSF Operands: 0  f  127 d 0,1 Operands: 0  f  127 0b7 Operation: (W) + (f)  (destination) Operation: 1  (f) Status Affected: C, DC, Z Status Affected: None Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: Bit ‘b’ in register ‘f’ is set. ANDLW AND literal with W BTFSC Bit Test f, Skip if Clear Syntax: [ label ] ANDLW Syntax: [ label ] BTFSC f,b Operands: 0  k  255 Operands: Operation: (W) .AND. (k)  (W) 0  f  127 0b7 Status Affected: Z Operation: skip if (f) = 0 Description: The contents of W register are AND’ed with the 8-bit literal ‘k’. The result is placed in the W register. Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a two-cycle instruction. ANDWF AND W with f Syntax: [ label ] ANDWF Operands: 0  f  127 d 0,1 Operation: (W) .AND. (f)  (destination) Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.  2015-2020 Microchip Technology Inc. k f,d k f,b f,b f,d DS20005479D-page 213 MCP19116/7 BTFSS Bit Test f, Skip if Set CLRWDT Clear Watchdog Timer Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRWDT Operands: 0  f  127 0b