MCP621/1S/2/3/4/5/9
20 MHz, 200 µV Op Amps with mCal
Features:
Description:
•
•
•
•
•
•
The Microchip Technology Inc. MCP621/1S/2/3/4/5/9
family of high bandwidth and high slew rate operational
amplifiers features low offset. At power-up, these op
amps are self-calibrated using mCal. Some package
options also provide a Calibration/Chip Select pin
(CAL/CS) that supports a Low-Power mode of
operation, with offset calibration at the time normal
operation is re-started. These amplifiers are optimized
for high speed, low noise and distortion, single-supply
operation with rail-to-rail output and an input that
includes the negative rail.
•
•
•
•
•
•
Gain-Bandwidth Product: 20 MHz (typical)
Slew Rate: 30 V/µs
Low Input Offset: ±200 µV (maximum)
Low Input Bias Current: 5 pA (typical)
Noise: 13 nV/Hz, at 1 MHz
Ease-of-Use:
- Unity-Gain Stable
- Rail-to-Rail Output
- Input Range incl. Negative Rail
- No Phase Reversal
Supply Voltage Range: +2.5V to +5.5V
High Output Current: ±70 mA
Supply Current: 2.5 mA/Ch (typical)
Low-Power Mode: 5 µA/Ch
Small Packages: SOT23-5, DFN
Extended Temperature Range: -40°C to +125°C
Typical Application Circuit
Detector Amplifier with 350kHz
2nd-order MFB Low pass Filter
Typical Applications:
•
•
•
•
•
•
•
This family is offered in single (MCP621 and
MCP621S), single with CAL/CS pin (MCP623), dual
(MCP622), dual with CAL/CS pins (MCP625), quad
(MCP624) and quad with CAL/CS pins (MCP629). All
devices are fully specified from -40°C to +125°C.
CF 3 pF
Optical Detector Amplifier
Barcode Scanners
Multi-Pole Active Filter
Driving A/D Converters
Fast Low-Side Current Sensing
Power Amplifier Control Loops
Consumer Audio
RF
Photo Detector
100 k
CD
ID
100 nA
30 pF
A
VREF
Design Aids:
•
•
•
•
•
SPICE Macro Models
FilterLab® Software
Microchip Advanced Part Selector (MAPS)
Analog Demonstration and Evaluation Boards
Application Notes
2.61 k
270 pF
26.1 k
294
MCP622
100 pF
VOUT
B
VREF
High Gain-Bandwidth Op Amp Portfolio
Model Family
Channels/Package
Gain Bandwidth
VOS (max.)
IQ/Ch (typ.)
MCP621/1S/2/3/4/5/9
1, 2, 4
20 MHz
0.2 mV
2.5 mA
MCP631/2/3/4/5/9
1, 2, 4
24 MHz
8.0 mV
2.5 mA
MCP651/1S/2/3/4/5/9
1, 2, 4
50 MHz
0.2 mV
6.0 mA
1, 2, 3, 4
60 MHz
8.0 mV
6.0 mA
MCP660/1/2/3/4/5/9
2009-2014 Microchip Technology Inc.
DS20002188D-page 1
MCP621/1S/2/3/4/5/9
Package Types
NC 1
8 CAL/CS
VIN– 2
MCP621S
SOT-23-5
MCP621
2x3 TDFN *
MCP621
SOIC
NC 1
VIN+ 3
7 VDD
6 VOUT
VIN+ 3
VSS 4
5 VCAL
VSS 4
8 CAL/CS VOUT 1
VIN– 2
EP
9
7 VDD
VSS
6 VOUT
5 VCAL
MCP624
SOIC, TSSOP
5 VDD
2
4 VIN-
VIN+ 3
VOUTA 1
14 VOUTD
VINA- 2
VINA+ 3
13 VIND12 VIND+
11 VSS
VDD 4
VINB+ 5
10 VINC+
VINB- 6
VOUTB 7
6 VINB–
5 VINB+
VINA+ 3
VSS 4
6 VINB–
5 VINB+
VSS
6 VDD
5 CAL/CS
2
4 VIN-
VIN+ 3
VIND-
VSS 4
7 VOUTB
VINA– 2
8 VDD
VOUT 1
7 VOUTB
VOUTD
EP
9
VOUTA 1
CALAD/CSAD
VINA– 2
VINA+ 3
8 VDD
MCP629
4x4 QFN*
VOUTA
VOUTA 1
MCP623
SOT-23-6
MCP622
SOIC
MCP622
3x3 DFN *
9 VINC8 VOUTC
16 15 14 13
VINA- 1
EP
11
VSS 4
CALA/CSA 5
8 VINB–
7 VINB+
6 CALB/CSB
VINA– 2
VINA+ 3
VSS 4
CALA/CSA 5
10 VDD
9 VOUTB
8 VINB–
7 VINB+
6 CALB/CSB
9 VINC5
6
7
8
VOUTC
VINA+ 3
VOUTA 1
VDD 3
VINB+ 4
VOUTB
VINA– 2
10 VDD
9 VOUTB
11 VSS
10 VINC+
EP
17
CALBC/CSBC
VOUTA 1
MCP625
MSOP
VINB-
MCP625
3x3 DFN *
12 VIND+
VINA+ 2
* Includes Exposed Thermal Pad (EP); see Table 3-1.
DS20002188D-page 2
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
1.0
ELECTRICAL CHARACTERISTICS
1.1
Absolute Maximum Ratings †
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at those or any other
conditions above those indicated in the operational
listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may
affect device reliability.
VDD – VSS .......................................................................6.5V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+ and VIN–) †† . VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
Output Short Circuit Current ................................ Continuous
Current at Output and Supply Pins ..........................±150 mA
Storage Temperature ...................................-65°C to +150°C
Max. Junction Temperature ........................................ +150°C
ESD protection on all pins (HBM, MM) 1 kV, 200V
1.2
†† See Section 4.2.2, Input Voltage and Current
Limits.
Specifications
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
VOS
-200
—
+200
µV
After calibration (Note 1)
VOSTRM
—
37
200
µV
(Note 2)
VOS/TA
—
±2.0
—
PSRR
61
76
—
dB
IB
—
5
—
pA
Across Temperature
IB
—
100
—
pA
TA = +85°C
Across Temperature
IB
—
1700
5,000
pA
TA = +125°C
Input Offset Current
IOS
—
±10
—
pA
Common Mode Input
Impedance
ZCM
—
1013||9
—
||pF
Differential Input Impedance
ZDIFF
—
1013||2
—
||pF
Common Mode Input Voltage
Range
VCMR
VSS 0.3
—
VDD 1.3
V
(Note 3)
Common Mode Rejection Ratio
CMRR
65
81
—
dB
VDD = 2.5V, VCM = -0.3 to
1.2V
CMRR
68
84
—
dB
VDD = 5.5V, VCM = -0.3 to
4.2V
AOL
88
117
—
dB
VDD = 2.5V,
VOUT = 0.3V to 2.2V
AOL
94
126
—
dB
VDD = 5.5V,
VOUT = 0.3V to 5.2V
Input Offset
Input Offset Voltage
Input Offset Voltage Trim Step
Size
Input Offset Voltage Drift
Power Supply Rejection Ratio
µV/°C TA = -40°C to +125°C
Input Current and Impedance
Input Bias Current
Common Mode
Open-Loop Gain
DC Open-Loop Gain
(large signal)
Note 1:
2:
3:
4:
Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is
toggled. Thus, 1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.
Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability.
See Figure 2-6 and Figure 2-7 for temperature effects.
The ISC specifications are for design guidance only; they are not tested.
2009-2014 Microchip Technology Inc.
DS20002188D-page 3
MCP621/1S/2/3/4/5/9
TABLE 1-1:
DC ELECTRICAL SPECIFICATIONS (CONTINUED)
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/3, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Maximum Output Voltage Swing VOL, VOH
VSS + 20
—
VDD 20
mV
VDD = 2.5V, G = +2,
0.5V Input Overdrive
VOL, VOH
VSS + 40
—
VDD 40
mV
VDD = 5.5V, G = +2,
0.5V Input Overdrive
ISC
±40
±85
±130
mA
VDD = 2.5V (Note 4)
ISC
±35
±70
±110
mA
VDD = 5.5V (Note 4)
mV
VCAL pin externally driven
Output
Output Short Circuit Current
Calibration Input
Calibration Input Voltage Range VCALRNG VSS + 0.1
—
VDD – 1.4
0.323V
0.333V
Internal Calibration Voltage
VCAL
DD
DD 0.343VDD
Input Impedance
VCAL pin open
ZCAL
—
100 || 5
—
k||pF
VDD
2.5
—
5.5
V
Power Supply
Supply Voltage
IQ
1.2
2.5
3.6
mA
POR Input Threshold, Low
Quiescent Current per Amplifier
VPRL
1.15
1.40
—
V
POR Input Threshold, High
VPRH
—
1.40
1.65
V
Note 1:
2:
3:
4:
IO = 0
Describes the offset (under the specified conditions) right after power-up, or just after the CAL/CS pin is
toggled. Thus, 1/f noise effects (an apparent wander in VOS; see Figure 2-35) are not included.
Increment between adjacent VOS trim points; Figure 2-3 shows how this affects the VOS repeatability.
See Figure 2-6 and Figure 2-7 for temperature effects.
The ISC specifications are for design guidance only; they are not tested.
TABLE 1-2:
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND,
VCM = VDD/2, VOUT VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CAL/CS = VSS (refer to Figure 1-2).
Parameters
Sym.
Min.
Typ.
Max.
Units
GBWP
—
20
—
MHz
PM
—
60
—
°
ROUT
—
15
—
THD+N
—
0.0018
—
%
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
Open-Loop Output Impedance
G = +1
AC Distortion
Total Harmonic Distortion plus
Noise
G = +1, VOUT = 2VP-P, f = 1 kHz,
VDD = 5.5V, BW = 80 kHz
Step Response
Rise Time, 10% to 90%
tr
—
13
—
ns
SR
—
10
—
V/µs
G = +1
Eni
—
20
—
µVP-P
f = 0.1 Hz to 10 Hz
Input Noise Voltage Density
eni
—
13
—
nV/Hz f = 1 MHz
Input Noise Current Density
ini
4
—
fA/Hz
Slew Rate
G = +1, VOUT = 100 mVP-P
Noise
Input Noise Voltage
DS20002188D-page 4
f = 1 kHz
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
TABLE 1-3:
DIGITAL ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to +5.5V, VSS = GND, VCM = VDD/2,
VOUT VDD/2, VL = VDD/2, RL = 2 k to VL, CL = 50 pF and CAL/CS = VSS (refer to Figure 1-1 and Figure 1-2).
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
CAL/CS Logic Threshold, Low
VIL
VSS
—
0.2VDD
V
CAL/CS Input Current, Low
ICSL
—
0
—
nA
CAL/CS Logic Threshold, High
VIH
0.8VDD
VDD
V
CAL/CS Input Current, High
ICSH
—
0.7
—
µA
CAL/CS = VDD
ISS
-3.5
-1.8
—
µA
Single, CAL/CS = VDD = 2.5V
ISS
-8
-4
—
µA
Single, CAL/CS = VDD = 5.5V
ISS
-5
-2.5
—
µA
Dual, CAL/CS = VDD = 2.5V
ISS
-10
-5
—
µA
Dual, CAL/CS = VDD = 5.5V
RPD
—
5
—
M
IO(LEAK)
—
50
—
nA
CAL/CS = VDD, TA = 125°C
VDD Low to Amplifier Off Time
(output goes High Z)
tPOFF
—
200
—
ns
G = +1 V/V, VL = VSS,
VDD = 2.5V to 0V step to VOUT = 0.1
(2.5V)
VDD High to Amplifier On Time
(including calibration)
tPON
100
200
300
ms
G = +1 V/V, VL = VSS,
VDD = 0V to 2.5V step to VOUT = 0.9
(2.5V)
CAL/CS Input Hysteresis
VHYST
—
0.25
—
V
CAL/CS Setup Time
(between CAL/CS edges)
tCSU
1
—
—
µs
G = +1 V/V, VL = VSS (Notes 2, 3, 4)
CAL/CS = 0.8VDD to VOUT = 0.1
(VDD/2)
CAL/CS High to Amplifier Off Time
(output goes High Z)
tCOFF
—
200
—
ns
G = +1 V/V, VL = VSS,
CAL/CS = 0.8VDD to VOUT = 0.1
(VDD/2)
CAL/CS Low to Amplifier On Time
(including calibration)
tCON
—
3
4
ms
G = +1 V/V, VL = VSS, MCP621 and
MCP625, CAL/CS = 0.2VDD to
VOUT = 0.9 (VDD/2)
tCON
—
6
8
ms
G = +1 V/V, VL = VSS, MCP629,
CAL/CS = 0.2VDD to
VOUT = 0.9 (VDD/2)
CAL/CS Low Specifications
CAL/CS = 0V
CAL/CS High Specifications
GND Current
CAL/CS Internal Pull-Down
Resistor
Amplifier Output Leakage
POR Dynamic Specifications
CAL/CS Dynamic Specifications
Note 1:
2:
3:
4:
The MCP622 single, MCP625 dual and MCP629 quad have their CAL/CS inputs internally pulled down to VSS (0V).
This time ensures that the internal logic recognizes the edge. However, for the rising edge case, if CAL/CS is raised
before the calibration is complete, the calibration will be aborted and the part will return to Low-Power mode.
For the MCP625 dual, there is an additional constraint. CALA/CSA and CALB/CSB can be toggled simultaneously
(within a time much smaller than tCSU) to make both op amps perform the same function simultaneously. If they are
toggled independently, then CALA/CSA (CALB/CSB) cannot be allowed to toggle while op amp B (op amp A) is in
Calibration mode; allow more than the maximum tCON time (4 ms) before the other side is toggled.
For the MCP629 quad, there is an additional constraint. CALAD/CSAD and CALBC/CSBC can be toggled simultaneously
(within a time much smaller than tCSU) to make all four op amps perform the same function simultaneously, and the
maximum tCON time is approximately doubled (8 ms). If they are toggled independently, then CALAD/CSAD
(CALBC/CSBC) cannot be allowed to toggle while op amps B and C (op amps A and D) are in Calibration mode; allow
more than the maximum tCON time (8 ms) before the other side is toggled.
2009-2014 Microchip Technology Inc.
DS20002188D-page 5
MCP621/1S/2/3/4/5/9
TABLE 1-4:
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, all limits are specified for: VDD = +2.5V to +5.5V,VSS = GND.
Parameters
Sym.
Min.
Typ.
Max.
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Conditions
Temperature Ranges
(Note 1)
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23
θJA
—
220.7
—
°C/W
Thermal Resistance, 6L-SOT-23
θJA
—
190.5
—
°C/W
Thermal Resistance, 8L-2x3 TDFN
θJA
—
52.5
—
°C/W
Thermal Resistance, 8L-3x3 DFN
θJA
—
56.7
—
°C/W
Thermal Resistance, 8L-SOIC
θJA
—
149.5
—
°C/W
Thermal Resistance, 10L-3x3 DFN
θJA
—
53.3
—
°C/W
Thermal Resistance, 10L-MSOP
θJA
—
202
—
°C/W
Thermal Resistance, 14L-SOIC
θJA
—
95.3
—
°C/W
Thermal Resistance, 14L-TSSOP
θJA
—
100
—
°C/W
Thermal Resistance, 16L-4x4-QFN
θJA
—
45.7
—
°C/W
Note 1:
2:
1.3
(Note 2)
(Note 2)
(Note 2)
Operation must not cause TJ to exceed the Maximum Junction Temperature specification (150°C).
Measured on a standard JC51-7, four-layer printed circuit board with ground plane and vias.
Timing Diagram
VIH
CAL/CS
VDD
VPRH
tPON
tCSU
tCOFF
VOUT High Z
On
ISS -3 µA (typical)
-2.5 mA (typical)
ICS 0 nA (typical)
Note:
VIL
High Z
-3 µA (typical)
0.7 µA (typical)
VPRL
tCON
tPOFF
On
-2.5 mA (typical)
High Z
-3 µA (typical)
0 nA (typical)
For the MCP625 dual and the MCP629 quad, there is an additional constraint on toggling the two
CAL/CS pins close together; see the TCON specification in Table 1-3.
FIGURE 1-1:
DS20002188D-page 6
Timing Diagram.
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
1.4
Test Circuits
The circuit used for most DC and AC tests is shown in
Figure 1-2. This circuit can independently set VCM and
VOUT; see Equation 1-1. Note that VCM is not the
circuit’s Common mode voltage ((VP + VM)/2), and that
VOST includes VOS plus the effects (on the input offset
error, VOST) of temperature, CMRR, PSRR and AOL.
CF
6.8 pF
RG
10 k
VP
EQUATION 1-1:
CB1
100 nF
MCP62X
VCM = VP + V DD 2 2
Where:
GDM = Differential Mode Gain
(V/V)
VCM = Op Amp’s Common Mode
Input Voltage
(V)
(mV)
VDD/2
CB2
2.2 µF
VIN–
VOST = V IN– – V IN+
V OUT = VDD 2 + VP – V M + V OST 1 + GDM
2009-2014 Microchip Technology Inc.
VDD
VIN+
G DM = R F R G
VOST = Op Amp’s Total Input Offset
Voltage
RF
10 k
VM
RG
10 k
RL
2 k
RF
10 k
CF
6.8 pF
VOUT
CL
50 pF
VL
FIGURE 1-2:
AC and DC Test Circuit for
Most Specifications.
DS20002188D-page 7
MCP621/1S/2/3/4/5/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
DC Signal Inputs
80 Samples
TA = +25°C
VDD = 2.5V and 5.5V
Calibrated at +25°C
-80
-60
-40 -20
0
20
40
Input Offset Voltage (µV)
Percentage of Occurrences
FIGURE 2-1:
24%
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
Input Offset Voltage (µV)
22%
20%
18%
16%
14%
12%
10%
8%
6%
4%
2%
0%
60
Input Offset Voltage.
-8
-6
-4
-2
0
2
4
6
8
10
50
40
30
20
10
0
-10
-20
-30
-40
-50
Input Offset Voltage Drift.
No Change
(includes noise)
Calibration
Changed
(+1 step)
-60 -50 -40 -30 -20 -10 0 10 20 30 40 50 60
Input Offset Voltage Calibration Repeatability
(µV)
FIGURE 2-3:
Input Offset Voltage
Repeatability (repeated calibration).
DS20002188D-page 8
VDD = 5.5V
VDD = 2.5V
FIGURE 2-5:
Output Voltage.
0.0
200 Samples
TA = +25°C
VDD = 2.5V and 5.5V
Calibration
Changed
(-1 step)
Representative Part
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Low Input Common
Mode Headroom (V)
Percentage of Occurrences
50%
45%
40%
35%
30%
25%
20%
15%
10%
5%
0%
+125°C
+85°C
+25°C
-40°C
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Power Supply Voltage (V)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-2:
Representative Part
Calibrated at VDD = 6.5V
FIGURE 2-4:
Input Offset Voltage vs.
Power Supply Voltage.
80 Samples
VDD = 2.5V and 5.5V
TA = -40°C to +125°C
Calibrated at +25°C
-10
300
200
100
0
-100
-200
-300
-400
-500
-600
-700
80
Input Offset Voltage (µV)
Percentage of Occurrences
2.1
Input Offset Voltage vs.
1 Lot
Low (VCMR_L – VSS)
-0.1
-0.2
VDD = 2.5V
-0.3
VDD = 5.5V
-0.4
-0.5
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
125
FIGURE 2-6:
Low Input Common Mode
Voltage Headroom vs. Ambient Temperature.
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
1 Lot
High (VDD – VCMR_H)
1.3
CMRR, PSRR (dB)
High Input Common
Mode Headroom (V)
1.4
V DD = 2.5V
1.2
1.1
V DD = 5.5V
1.0
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
CMRR, VDD = 2.5V
-25
125
FIGURE 2-8:
Input Offset Voltage vs.
Common Mode Voltage with VDD = 2.5V.
VDD = 5.5V
115
VDD = 2.5V
110
105
100
-50
10,000
Input Bias, Offset Currents
(pA)
Input Common Mode Voltage (V)
FIGURE 2-9:
Input Offset Voltage vs.
Common Mode Voltage with VDD = 5.5V.
2009-2014 Microchip Technology Inc.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
+125°C
+85°C
+25°C
-40°C
0.0
125
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-11:
DC Open-Loop Gain vs.
Ambient Temperature.
VDD = 5.5V
Representative Part
-0.5
Input Offset Voltage (µV)
100
120
Input Common Mode Voltage (V)
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
0
25
50
75
Ambient Temperature (°C)
FIGURE 2-10:
CMRR and PSRR vs.
Ambient Temperature.
DC Open-Loop Gain (dB)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
+125°C
+85°C
+25°C
-40°C
-0.4
CMRR, VDD = 5.5V
130
VDD = 2.5V
Representative Part
-0.6
Input Offset Voltage (µV)
PSRR
-50
125
FIGURE 2-7:
High Input Common Mode
Voltage Headroom vs. Ambient Temperature.
1000
800
600
400
200
0
-200
-400
-600
-800
-1000
110
105
100
95
90
85
80
75
70
65
60
VDD = 5.5V
VCM = VCMR_H
1,000
IB
100
10
| IOS |
1
25
45
65
85
105
Ambient Temperature (°C)
125
FIGURE 2-12:
Input Bias and Offset
Currents vs. Ambient Temperature with
VDD = +5.5V.
DS20002188D-page 9
MCP621/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
1.E-03
1m
Input Current Magnitude (A)
IOS
100
100µ
1.E-04
80
10µ
1.E-05
60
1µ
1.E-06
Representative Part
TA = +85°C
VDD = 5.5V
40
20
100n
1.E-07
10n
1.E-08
0
-20
1n
1.E-09
100p
1.E-10
IB
-40
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-60
-0.5
Input Bias, Offset Currents
(pA)
120
Common Mode Input Voltage (V)
FIGURE 2-13:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +85°C.
Input Bias, Offset Currents
(pA)
1500
10p
1.E-11
1p
1.E-12
+125°C
+85°C
+25°C
-40°C
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-15:
Input Bias Current vs. Input
Voltage (below VSS).
IOS
1000
Representative Part
TA = +125°C
VDD = 5.5V
500
0
IB
-500
-1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-14:
Input Bias and Offset
Currents vs. Common Mode Input Voltage with
TA = +125°C.
DS20002188D-page 10
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
Other DC Voltages and Currents
3.5
VDD = 5.5V
12
VOL – VSS
-IOUT
3.0
Supply Current
(mA/amplifier)
10
8
6
4
VDD – VOH
IOUT
VDD = 2.5V
+125°C
+85°C
+25°C
-40°C
1.0
RL = 2 kΩ
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
100
1.0
0.0
10
Output Current Magnitude (mA)
Power Supply Voltage (V)
FIGURE 2-16:
Ratio of Output Voltage
Headroom to Output Current.
FIGURE 2-19:
Supply Voltage.
Supply Current vs. Power
3.0
VOL – VSS
VDD = 5.5V
2.5
VDD = 5.5V
Supply Current
(mA/amplifier)
2.0
VDD = 2.5V
1.5
1.0
0.5
VDD – VOH
VDD = 2.5V
5.5
5.0
4.5
4.0
3.5
Common Mode Input Voltage (V)
FIGURE 2-17:
Output Voltage Headroom
vs. Ambient Temperature.
100
80
60
40
20
0
-20
-40
-60
-80
-100
3.0
125
2.5
100
2.0
0.0
0
25
50
75
Ambient Temperature (°C)
1.5
-25
1.0
-50
0.0
Output Headroom (mV)
1.5
0.0
0
1
FIGURE 2-20:
Supply Current vs. Common
Mode Input Voltage.
POR Trip Voltages (V)
1.8
+125°C
+85°C
+25°C
-40°C
1.6
VPRH
1.4
1.2
1.0
VPRL
0.8
0.6
0.4
0.2
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
Output Short Circuit Current
(mA)
2.0
0.5
2
20
18
16
14
12
10
8
6
4
2
0
2.5
0.5
Ratio of Output Headroom to
Output Current (mV/mA)
14
0.5
2.2
Power Supply Voltage (V)
FIGURE 2-18:
Output Short-Circuit Current
vs. Power Supply Voltage.
2009-2014 Microchip Technology Inc.
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-21:
Power-On Reset Voltages
vs. Ambient Temperature.
DS20002188D-page 11
MCP621/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
25%
144 Samples
VDD = 2.5V and 5.5V
20%
15%
10%
5%
Normalized Internal Calibration Voltage;
VCAL/VDD
FIGURE 2-22:
Normalized Internal
Calibration Voltage.
DS20002188D-page 12
33.52%
33.48%
33.44%
33.40%
33.36%
33.32%
33.28%
33.24%
0%
Internal V CAL Resistance (kΩ)
30%
33.20%
Percentage of Occurrences
VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
140
120
100
80
60
40
20
0
-50
-25
FIGURE 2-23:
Temperature.
0
25
50
75
Ambient Temperature (°C)
100
125
VCAL Input Resistance vs.
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
0
120
-30
100
-60
AOL
-150
| AOL |
-180
0
-210
-20
-240
35
25
25
GBWP
20
50
45
15
-50
-25
0
25
50
75 100
Ambient Temperature (°C)
40
125
FIGURE 2-26:
Gain Bandwidth Product
and Phase Margin vs. Ambient Temperature.
2009-2014 Microchip Technology Inc.
Open-Loop Output Impedance (Ω)
55
Phase Margin (°)
Gain Bandwidth Product
(MHz)
60
VDD = 5.5V
VDD = 2.5V
50
GBWP
20
45
40
FIGURE 2-28:
Gain Bandwidth Product
and Phase Margin vs. Output Voltage.
65
30
55
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
70
PM
60
VDD = 5.5V
VDD = 2.5V
15
Open-Loop Gain vs.
40
65
PM
30
Frequency (Hz)
45
70
40
1.E+0
1.E+5 1.E+6
1.E+7 100M
1.E+8
1 1.E+1
10 1.E+2
100 1.E+3
1k 1.E+4
10k 100k
1M 10M
35
6.0
45
-120
FIGURE 2-25:
Frequency.
5.5
FIGURE 2-27:
Gain Bandwidth Product
and Phase Margin vs. Common Mode Input
Voltage.
-90
60
20
40
Common Mode Input Voltage (V)
140
40
15
1.E+7
10M
CMRR and PSRR vs.
80
45
5.0
1.E+6
1M
20
Phase Margin (°)
Open-Loop Gain (dB)
FIGURE 2-24:
Frequency.
1.E+4
1.E+5
10k
100k
Frequency (Hz)
50
GBWP
4.5
1.E+3
1k
Open-Loop Phase (°)
10
1.E+2
100
25
55
4.0
20
VDD = 5.5V
VDD = 2.5V
30
3.5
30
60
PM
3.0
PSRR+
PSRR-
40
35
2.5
50
65
2.0
60
40
1.5
70
70
1.0
CMRR
45
-0.5
Gain Bandwidth Product
(MHz)
80
Gain Bandwidth Product
(MHz)
CMRR, PSRR (dB)
90
0.5
100
Phase Margin (°)
Frequency Response
0.0
2.3
100
10
G = 101 V/V
G = 11 V/V
G = 1 V/V
1
0.1
1k
10k
100k 1.0E+06
1M
10M
100M
1.0E+03
1.0E+04
1.0E+05
1.0E+07
1.0E+08
Frequency (Hz)
FIGURE 2-29:
Closed-Loop Output
Impedance vs. Frequency.
DS20002188D-page 13
MCP621/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
10
9
8
7
6
5
4
3
2
1
0
10p
1.0E-11
150
RS = 0Ω
RS = 1 kΩ
140
GN = 1 V/V
GN = 2 V/V
GN 4 V/V
Channel-to-Channel
Separation (dB)
Gain Peaking (dB)
VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
130
120
110
100
90
80
70
60
100p
1n
1.0E-10
1.0E-09
Normalized Capacitive Load; CL/GN (F)
FIGURE 2-30:
Gain Peaking vs.
Normalized Capacitive Load.
DS20002188D-page 14
RTI
VCM = VDD/2
G = +1 V/V
RS = 10 kΩ
RS = 100 kΩ
50
1k
1.E+03
10k
1.E+04
1M
100k
1.E+05
1.E+06
Frequency (Hz)
10M
1.E+07
FIGURE 2-31:
Channel-to-Channel
Separation vs. Frequency.
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
Input Noise and Distortion
1.E+4
10µ
Input Offset + Noise;
V OS + eni(t) (µV)
20
1.E+3
1µ
1.E+2
100n
15
Representative Part
Analog NPBW = 0.1 Hz
Sample Rate = 2 SPS
10
5
0
-5
-10
-15
-20
1.E+1
10n
0.1
1.E-1
1
1.E+0
10
1.E+1
FIGURE 2-32:
vs. Frequency.
Input Noise Voltage Density
5
15
20 25 30
Time (min)
35
40
45
1
200
THD + Noise (%)
250
VDD = 2.5V
150
VDD = 5.5V
100
50
0.1
G = 1 V/V
G = 11 V/V
BW = 22 Hz to > 500 kHz
0.01
0.001
BW = 22 Hz to 80 kHz
VDD = 5.0V
VOUT = 2 VP-P
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
1.5
1.0
-0.5
0.5
f = 100 Hz
0
0.0001
100
1.E+2
Common Mode Input Voltage (V)
FIGURE 2-33:
Input Noise Voltage Density
vs. Input Common Mode Voltage with f = 100 Hz.
FIGURE 2-36:
1k
1.E+3
10k
1.E+4
Frequency (Hz)
100k
1.E+5
THD+N vs. Frequency.
30
25
20
VDD = 2.5V
VDD = 5.5V
15
10
5
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
-0.5
0.5
f = 1 MHz
0
0.0
Input Noise Voltage Density
(nV/Hz)
10
FIGURE 2-35:
Input Noise plus Offset vs.
Time with 0.1 Hz Filter.
300
0.0
Input Noise Voltage Density
(nV/Hz)
0
1k 1.E+4
10M
10k 100k
1M 1.E+7
1.E+3
1.E+5 1.E+6
Frequency (Hz)
100
1.E+2
2.0
Input Noise Voltage Density (nV/Hz)
2.4
Common Mode Input Voltage (V)
FIGURE 2-34:
Input Noise Voltage Density
vs. Input Common Mode Voltage with f = 1 MHz.
2009-2014 Microchip Technology Inc.
DS20002188D-page 15
MCP621/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
2.5
Time Response
0
20
Output Voltage (V)
VIN
VOUT
40
60
Output Voltage (V)
FIGURE 2-37:
Step Response.
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
Non-Inverting Small Signal
VIN
VOUT
FIGURE 2-40:
Response.
7
VDD = 5.5V
G=1
VIN
VOUT
Inverting Large Signal Step
VDD = 5.5V
G=2
6
VIN
5
VOUT
4
3
2
1
0
-1
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time (µs)
Output Voltage (10 mV/div)
FIGURE 2-38:
Step Response.
Non-Inverting Large Signal
0
Slew Rate (V/µs)
VDD = 5.5V
G = -1
RF = 1 kΩ
VOUT
100
200
FIGURE 2-39:
Response.
DS20002188D-page 16
300
400 500
Time (ns)
600
700
800
Inverting Small Signal Step
1
2
3
4
5
6
Time (ms)
7
8
9
10
FIGURE 2-41:
The MCP621/1S/2/3/4/5/9
Family Shows No Input Phase Reversal with
Overdrive.
VIN
0
VDD = 5.5V
G = -1
RF = 1 kΩ
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Time (µs)
80 100 120 140 160 180 200
Time (ns)
Input, Output Voltages (V)
Output Voltage (10 mV/div)
VDD = 5.5V
G=1
24
22
20
18
16
14
12
10
8
6
4
2
0
Falling Edge
VDD = 2.5V
VDD = 5.5V
Rising
-50
-25
FIGURE 2-42:
Temperature.
0
25
50
75
Ambient Temperature (°C)
100
125
Slew Rate vs. Ambient
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
Maximum Output Voltage
Swing (VP-P)
10
VDD = 5.5V
VDD = 2.5V
1
0.1
100k
1.E+05
1M
10M
1.E+06
1.E+07
Frequency (Hz)
100M
1.E+08
FIGURE 2-43:
Maximum Output Voltage
Swing vs. Frequency.
2009-2014 Microchip Technology Inc.
DS20002188D-page 17
MCP621/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
Calibration and Chip Select Response
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
0.40
CAL/CS = VDD
CAL/CS Hysteresis (V)
CAL/CS Current (µA)
2.6
0.35
0.30
0.20
0.10
0.05
0.00
-50
VDD = 2.5V
G=1
VL = 0V
7
6
IDD
5
6
4
2
0
4
Calibration
starts
3
2
-2
Op Amp Op Amp
turns on turns off
-4
-6
CAL/CS
VOUT
1
0
-8
-10
-1
-12
0
2
4
6
8
10
Time (ms)
12
14
16
VDD = 5.5V
G=1
VL = 0V
14
12
IDD
10
6
4
2
0
8
Calibration
starts
6
4
-2
Op Amp Op Amp
turns on turns off
-4
-6
CAL/CS
2
-8
VOUT
0
-10
-2
-12
0
2
4
6
8
10
Time (ms)
12
14
Power Supply Current;
IDD (mA)
FIGURE 2-45:
CAL/CS Voltage, Output
Voltage and Supply Current (for Side A) vs. Time
with VDD = 2.5V.
16
FIGURE 2-46:
CAL/CS Voltage, Output
Voltage and Supply Current (for Side A) vs. Time
with VDD = 5.5V.
DS20002188D-page 18
100
125
7
6
5
4
3
2
1
0
-50
16
0
25
50
75
Ambient Temperature (°C)
8
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-48:
CAL/CS Turn-On Time vs.
Ambient Temperature.
8
CAL/CS Pull-down Resistor
(MΩ)
8
-25
FIGURE 2-47:
CAL/CS Hysteresis vs.
Ambient Temperature.
CAL/CS Turn On Time (ms)
CAL/CS Current vs. Power
Power Supply Current;
IDD (mA)
FIGURE 2-44:
Supply Voltage.
CAL/CS, V OUT (V)
VDD = 2.5V
0.15
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
CAL/CS, V OUT (V)
VDD = 5.5V
0.25
Representative Part
7
6
5
4
3
2
1
0
-50
-25
0
25
50
75
Ambient Temperature (°C)
100
125
FIGURE 2-49:
CAL/CS’s Pull-Down
Resistor (RPD) vs. Ambient Temperature.
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.5V to 5.5V, VSS = GND, VCM = VDD/3, VOUT = VDD/2,
VL = VDD/2, RL = 2 kto VL, CL = 50 pF, and CAL/CS = VSS.
1.E-06
CAL/CS = VDD
-1
Output Leakage Current (A)
Negative Power Supply
Current; I SS (µA)
0
-2
-3
-4
+125°C
+85°C
+25°C
-40°C
-5
-6
Power Supply Voltage (V)
FIGURE 2-50:
Quiescent Current in
Shutdown vs. Power Supply Voltage.
2009-2014 Microchip Technology Inc.
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-7
CAL/CS = VDD = 5.5V
1.E-07
+125°C
1.E-08
+85°C
1.E-09
1.E-10
+25°C
1.E-11
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Output Voltage (V)
FIGURE 2-51:
Output Voltage.
Output Leakage Current vs.
DS20002188D-page 19
2009-2014 Microchip Technology Inc.
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
MCP621
PIN FUNCTION TABLE
MCP621S
MCP622
MCP623
SOIC DFN
SOT-23
SOIC
4
3
6
—
—
2
3
4
5
2
3
4
5
6
TDFN
SOT-23
2
3
7
—
—
2
3
7
—
—
4
3
5
—
—
2
3
8
5
2
3
8
5
6
6
—
—
—
—
—
7
—
—
—
7
—
—
—
—
—
—
—
—
—
—
—
4
4
—
MCP625
Symbol
Description
DFN
QFN
2
3
10
7
2
3
10
7
1
2
3
4
6
8
8
5
VIN–, VINA–
VIN+, VINA+
VDD
VINB+
VINB–
7
—
9
—
9
—
6
VOUTB
—
7
—
—
—
8
8
—
—
8
—
—
—
9
9
—
—
9
VINC–
Inverting Input (op amp C)
—
—
—
10
10
—
—
10
VINC+
Non-inverting input (op amp C)
2
4
4
11
11
4
4
11
VSS
—
—
—
—
2
—
12
12
—
—
12
VIND+
Non-inverting input (op amp D)
—
—
—
—
—
—
13
13
—
—
13
VINDD–
Inverting Input (op amp D)
—
—
—
—
—
—
—
14
VOUTD
Output (op amp D)
—
—
—
—
—
—
14
—
—
—
—
15
1
14
—
TSSOP MSOP
MCP629
DS20002188D-page 20
6
6
1
1
1
—
9
—
—
9
8
8
—
—
—
—
—
—
—
—
—
—
—
6
5
1
5
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
5
7
Inverting Input (op amp A)
Non-inverting Input (op amp A)
Positive Power Supply
Non-inverting Input (op amp B)
Inverting Input (op amp B)
Output (op amp B)
CALBC/CSBC Calibrate/Chip Select Digital Input
(op amps B and C)
Output (op amp C)
VOUTC
Negative Power Supply
CALAD/CSAD Calibrate/Chip Select Digital Input
(op amps A and D)
VOUT, VOUTA Output (op amp A)
1
1
1
1
—
—
—
11
16
17
—
—
5
5
—
CAL/CS,
CALA/CSA
Calibrate/Chip Select Digital Input (op amp A)
6
—
CALB/CSB
—
—
—
—
VCAL
NC
Calibrate/Chip Select Digital Input (op amp B)
Calibration Common Mode Voltage Input
No Internal Connection
EP
Exposed Thermal Pad (EP);
must be connected to VSS
MCP621/1S/2/3/4/5/9
SOIC
MCP624
MCP621/1S/2/3/4/5/9
3.1
Analog Outputs
The analog output pins (VOUT) are low-impedance
voltage sources.
3.2
Analog Inputs
The non-inverting and inverting inputs (VIN+, VIN–, …)
are high-impedance CMOS inputs with low bias
currents.
3.3
Power Supply Pins
The positive power supply (VDD) is 2.5V to 5.5V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
3.4
Calibration Common Mode
Voltage Input
A low-impedance voltage placed at this input (VCAL)
will set the op amps’ Common mode input voltage
during calibration. If this pin is left open, the Common
mode input voltage during calibration is approximately
VDD/3. The internal resistor divider is disconnected
from the supplies whenever the part is not in
calibration.
2009-2014 Microchip Technology Inc.
3.5
Calibrate/Chip Select Digital Input
This input (CAL/CS, …) is a CMOS, Schmitt-triggered
input that affects the Calibration and Low-Power
modes of operation. When this pin goes high, the part
is placed into a Low-Power mode and the output is
High Z. When this pin goes low, a calibration sequence
is started (which corrects VOS). At the end of the calibration sequence, the output becomes low-impedance
and the part resumes normal operation.
An internal POR triggers a calibration event when the
part is powered-on, or when the supply voltage drops
too low. Thus, the MCP622 parts are calibrated, even
though they do not have a CAL/CS pin.
3.6
Exposed Thermal Pad (EP)
There is an internal connection between the Exposed
Thermal Pad (EP) and the VSS pin; they must be
connected to the same potential on the Printed Circuit
Board (PCB).
This pad can be connected to a PCB ground plane to
provide a larger heat sink. This improves the package
thermal resistance (JA).
DS20002188D-page 21
MCP621/1S/2/3/4/5/9
4.0
APPLICATIONS
The MCP621/1S/2/3/4/5/9 family of self-zeroed op
amps is manufactured using Microchip’s state-of-theart CMOS process. It is designed for low-cost, lowpower and high-precision applications. Its low supply
voltage, low quiescent current and wide bandwidth
makes the MCP621/1S/2/3/4/5/9 ideal for batterypowered applications.
4.1
Calibration and Chip Select
These op amps include circuitry for dynamic calibration
of the offset voltage (VOS).
4.1.1
mCal CALIBRATION CIRCUITRY
The internal mCal circuitry, when activated, starts a
delay timer (to wait for the op amp to settle to its new
bias point), then calibrates the input offset voltage
(VOS). The mCal circuitry is triggered at power-up (and
after some power brown-out events) by the internal
POR, and by the memory’s parity detector. The
power-up time, when the mCal circuitry triggers the
calibration sequence, is 200 ms (typical).
4.1.2
CAL/CS PIN
The CAL/CS pin gives the user a means to externally
demand a Low-Power mode of operation, then to
calibrate VOS. Using the CAL/CS pin makes it possible
to correct VOS as it drifts over time (1/f noise and aging;
see Figure 2-35) and across temperature.
The CAL/CS pin performs two functions: it places the
op amp(s) in a Low-Power mode when it is held high,
and starts a calibration event (correction of VOS) after a
rising edge.
While in the Low-Power mode, the quiescent current is
quite small (ISS = -3 µA, typical). The output is also in a
High Z state.
During the calibration event, the quiescent current is
near, but smaller than, the specified quiescent current
(2.5 mA, typical). The output continues in the High Z
state, and the inputs are disconnected from the
external circuit, to prevent internal signals from
affecting circuit operation. The op amp inputs are
internally connected to a Common mode voltage buffer
and feedback resistors. The offset is corrected (using a
digital state machine, logic and memory), and the
calibration constants are stored in memory.
Once the calibration event is completed, the amplifier is
reconnected to the external circuitry. The turn-on time,
when calibration is started with the CAL/CS pin, is 5 ms
(typical).
There is an internal 5 M pull-down resistor tied to the
CAL/CS pin. If the CAL/CS pin is left floating, the
amplifier operates normally.
For the MCP625 dual and the MCP629 quad, there is
an additional constraint on toggling the two CAL/CS
pins close together; see the tCON specification in
Table 1-3. If the two pins are toggled simultaneously, or
if they are toggled separately with an adequate delay
between them (greater than tCON), then the CAL/CS
inputs are accepted as valid. If one of the two pins
toggles, while the other pin’s calibration routine is in
progress, then an invalid input occurs and the result is
unpredictable.
4.1.3
INTERNAL POR
This part includes an internal Power-on Reset (POR) to
protect the internal calibration memory cells. The POR
monitors the power supply voltage (VDD). When the
POR detects a low VDD event, it places the part into the
Low-Power mode of operation. When the POR detects
a normal VDD event, it starts a delay counter, then
triggers a calibration event. The additional delay gives
a total POR turn-on time of 200 ms (typical); this is also
the power-up time (since the POR is triggered at power
up).
4.1.4
PARITY DETECTOR
A parity error detector monitors the memory contents
for any corruption. In the rare event that a parity error is
detected (e.g., corruption from an alpha particle), a
POR event is automatically triggered. This will cause
the input offset voltage to be recorrected, and the op
amp will not return to normal operation for a period of
time (the POR turn-on time, tPON).
4.1.5
CALIBRATION INPUT PIN
A VCAL pin is available in some options (e.g., the single
MCP621) for those applications that need the
calibration to occur at an internally driven Common
mode voltage other than VDD/3.
Figure 4-1 shows the reference circuit that internally
sets the op amp’s Common mode reference voltage
(VCM_INT) during calibration (the resistors are
disconnected from the supplies at other times). The
5 k resistor provides overcurrent protection for the
buffer.
300 k
VCM_INT
5 k
VCAL
BUFFER
150 k
VSS
FIGURE 4-1:
Input Circuitry.
DS20002188D-page 22
To op amp during
calibration
VDD
Common-Mode Reference’s
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
When the VCAL pin is left open, the internal resistor
divider generates a VCM_INT of approximately VDD/3,
which is near the center of the input Common mode
voltage range. It is recommended that an external
capacitor from VCAL to ground be added to improve
noise immunity.
When the VCAL pin is driven by an external voltage
source, which is within its specified range, the op amp
will have its input offset voltage calibrated at that
Common mode input voltage. Make sure that VCAL is
within its specified range.
It is possible to use an external resistor voltage divider
to modify VCM_INT; see Figure 4-2. The internal circuitry
at the VCAL pin looks like 100 k tied to VDD/3. The
parallel equivalent of R1 and R2 should be much
smaller than 100 k to minimize differences in matching and temperature drift between the internal and
external resistors. Again, make sure that VCAL is within
its specified range.
VDD
MCP62X
R1
VCAL
C1
R2
VSS
FIGURE 4-2:
Resistors.
4.2.1
Input
PHASE REVERSAL
The input devices are designed to not exhibit phase
inversion when the input pins exceed the supply
voltages. Figure 2-41 shows an input voltage
exceeding both supplies with no phase inversion.
4.2.2
VDD Bond
Pad
VIN+
Bond
Pad
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-3. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
2009-2014 Microchip Technology Inc.
Bond
VIN–
Pad
Input
Stage
VSS Bond
Pad
FIGURE 4-3:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuit must limit the currents
(and voltages) at the input pins (see Section 1.1
“Absolute Maximum Ratings †”). Figure 4-4 shows
the recommended approach to protecting these inputs.
The internal ESD diodes prevent the input pins (VIN+
and VIN–) from going too far below ground, and the
resistors R1 and R2 limit the possible current drawn out
of the input pins. Diodes D1 and D2 prevent the input
pins (VIN+ and VIN–) from going too far above VDD, and
dump any currents onto VDD. When implemented as
shown, resistors R1 and R2 also limit the current
through D1 and D2.
Setting VCM with External
For instance, a design goal to set VCM_INT = 0.1V when
VDD = 2.5V could be met with: R1 = 24.3 k,
R2 = 1.00 k and C1 = 100 nF. This will keep VCAL
within its range for any VDD, and should be close
enough to 0V for ground-based applications.
4.2
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
VDD
V1
V2
D1
R1
D2
MCP62X
VOUT
R2
VSS – (minimum expected V1)
2 mA
VSS – (minimum expected V2)
R2 >
2 mA
R1 >
FIGURE 4-4:
Inputs.
Protecting the Analog
It is also possible to connect the diodes to the left of the
resistor R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
DS20002188D-page 23
MCP621/1S/2/3/4/5/9
A significant amount of current can flow out of the
inputs (through the ESD diodes) when the Common
mode voltage (VCM) is below ground (VSS); see
Figure 2-15. Applications that are high-impedance may
need to limit the usable voltage range.
4.2.3
NORMAL OPERATION
The input stage of the MCP621/1S/2/3/4/5/9 op amps
use a differential PMOS input stage. It operates at low
Common mode input voltage (VCM), with VCM up to
VDD – 1.3V and down to VSS – 0.3V. The input offset
voltage (VOS) is measured at VCM = VSS – 0.3V and
VDD – 1.3V to ensure proper operation. See Figure 2-6
and Figure 2-7 for temperature effects.
When operating at very low non-inverting gains, the
output voltage is limited at the top by the VCM range
(< VDD – 1.3V); see Figure 4-5.
4.3.2.1
Power Dissipation
Since the output short-circuit current (ISC) is specified
at ±70 mA (typical), these op amps are capable of both
delivering and dissipating significant power.
Two common loads, and their impact on the op amp’s
power dissipation, will be discussed.
Figure 4-7 shows a resistive load (RL) with a DC output
voltage (VOUT). VL is RL’s ground point, VSS is usually
ground (0V) and IOUT is the output current. The input
currents are assumed to be negligible.
VDD
IDD
VOUT
MCP62X
RL
ISS
VDD
MCP62X
VIN
IOUT
VSS
VL
VOUT
FIGURE 4-7:
Diagram for Resistive Load
Power Calculations.
V SS V IN V OUT VDD – 1.3V
The DC currents are:
FIGURE 4-5:
Unity Gain Voltage
Limitations for Linear Operation.
4.3
EQUATION 4-1:
V OUT – V L
I OUT = -------------------------RL
I DD I Q + max 0, I OUT
Rail-to-Rail Output
4.3.1
MAXIMUM OUTPUT VOLTAGE
The Maximum Output Voltage (see Figure 2-16 and
Figure 2-17) describes the output range for a given
load. For instance, the output voltage swings to within
40 mV of the negative rail with a 2 k load tied to
VDD/2.
4.3.2
OUTPUT CURRENT
VOH Limited
RL = 100Ω
RL = 10Ω
+ISC Limited
RL = 2 kΩ
Where:
IQ = Quiescent supply current for one op
amp (mA/amplifier)
VOUT = A DC value (V)
The DC op amp power is:
EQUATION 4-2:
P OA = I DD V DD – V OUT + ISS VSS – V OUT
The maximum op amp power, for resistive loads at DC,
occurs when VOUT is halfway between VDD and VL, or
halfway between VSS and VL:
(VDD = 5.5V)
-ISC Limited
EQUATION 4-3:
max P OA = I DD V DD – V SS
2
FIGURE 4-6:
DS20002188D-page 24
80
60
40
20
0
-20
-40
VOL Limited
-60
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
-80
VOUT (V)
Figure 4-6 shows the possible combinations of output
voltage (VOUT) and output current (IOUT). IOUT is
positive when it flows out of the op amp into the
external circuit.
ISS – I Q + min 0, I OUT
max V DD – V L VL – VSS
+ -----------------------------------------------------------------4RL
IOUT (mA)
Output Current.
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
Figure 4-7 shows a capacitive load (CL), which is
driven by a sine wave with DC offset. The capacitive
load causes the op amp to output higher currents at
higher frequencies. Because the output rectifies IOUT,
the op amp’s dissipated power increases (even though
the capacitor does not dissipate power).
The power dissipated in a package depends on the
powers dissipated by each op amp in that package:
EQUATION 4-7:
n
P PKG =
POA
k=1
VDD
Where:
IDD
n = Number of op amps in package (1 or 2)
IOUT
MCP62X
VOUT
ISS
CL
VSS
FIGURE 4-8:
Diagram for Capacitive Load
Power Calculations.
The maximum ambient-to-junction temperature rise
(TJA) and junction temperature (TJ) can be calculated
using the maximum expected package power (PPKG),
ambient temperature (TA) and the package thermal
resistance (JA) found in Table 1-4:
EQUATION 4-8:
TJA = PPKG JA
The output voltage is assumed to be:
T J = T A + T JA
EQUATION 4-4:
VOUT = V DC + V AC sin t
Where:
VDC = DC offset (V)
VAC = Peak output swing (VPK)
The worst-case power derating for the op amps in a
particular package can be easily calculated:
EQUATION 4-9:
T Jmax – T A
P PKG --------------------------
= Radian frequency (2 f) (rad/s)
The op amp’s currents are:
EQUATION 4-5:
dV OUT
I OUT = CL ----------------- = V AC C L cos t
dt
IDD I Q + max 0, IOUT
I SS – I Q + min 0, IOUT
Where:
IQ = Quiescent supply current for one op
amp (mA/amplifier)
The op amp’s instantaneous power, average power
and peak power are:
EQUATION 4-6:
POA = I DD V DD – V OUT + I SS VSS – V OUT
JA
Where:
TJmax = Absolute maximum junction
temperature (°C)
TA = Ambient temperature (°C)
Several techniques are available to reduce TJA for a
given package:
• Reduce JA
- Use another package
- Improve the PCB layout (ground plane, etc.)
- Add heat sinks and air flow
• Reduce max (PPKG)
- Increase RL
- Decrease CL
- Limit IOUT using RISO (see Figure 4-9)
- Decrease VDD
4V AC fC L
ave POA = VDD – VSS IQ + ------------------------
max POA = VDD – VSS I Q + 2VAC fCL
2009-2014 Microchip Technology Inc.
DS20002188D-page 25
MCP621/1S/2/3/4/5/9
4.4
Improving Stability
4.4.1
4.4.2
CAPACITIVE LOADS
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. See Figure 2-30. A unity gain buffer (G = +1)
is the most sensitive to capacitive loads, though all
gains show the same general behavior.
Figure 4-11 shows an op amp circuit that represents
non-inverting amplifiers (VM is a DC voltage and VP is
the input) or inverting amplifiers (VP is a DC voltage
and VM is the input). The capacitances CN and CG
represent the total capacitance at the input pins; they
include the op amp’s Common mode input capacitance
(CCM), board parasitic capacitance and any capacitor
placed in parallel.
When driving large capacitive loads with these op
amps (e.g., > 10 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-9) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
RG
RF
GAIN PEAKING
RN
VP
MCP62X
VOUT
VM
RG
FIGURE 4-11:
Capacitance.
RISO
CN
CG
RF
Amplifier with Parasitic
VOUT
CG acts in parallel with RG (except for a gain of +1 V/V),
which causes an increase in gain at high frequencies.
CG also reduces the phase margin of the feedback
loop, which becomes less stable. This effect can be
reduced by either reducing CG or RF.
FIGURE 4-9:
Output Resistor, RISO
Stabilizes Large Capacitive Loads.
CN and RN form a low-pass filter that affects the signal
at VP. This filter has a single real pole at 1/(2RNCN).
Figure 4-10 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
The largest value of RF that should be used depends
on noise gain (see GN in Section 4.4.1 “Capacitive
Loads”) and CG. Figure 4-12 shows the maximum
recommended RF for several CG values.
CL
MCP62X
1,000
Recommended RISO (Ω)
1.E+05
100k
CG = 10 pF
CG = 32 pF
CG = 100 pF
CG = 320 pF
CG = 1 nF
Maximum Recommended RF
(Ω)
RN
10k
1.E+04
100
1k
1.E+03
10
G N = +1
G N +2
1
1p
1.E-12
10p
100p
1n
1.E-11
1.E-10
1.E-09
Normalized Capacitance; CL/GN (F)
1
10n
1.E-08
FIGURE 4-10:
Recommended RISO Values
for Capacitive Loads.
After selecting RISO, double check the resulting frequency response peaking and step response overshoot. Modify RISO’s value until the response is
reasonable. Bench evaluation and simulations with the
MCP621/1S/2/3/4/5/9 SPICE macro model are helpful.
DS20002188D-page 26
G N > +1 V/V
100
1.E+02
FIGURE 4-12:
RF vs. Gain.
10
Noise Gain; G N (V/V)
100
Maximum Recommended
Figures 2-37 and 2-38 show the small signal and large
signal step responses at G = +1 V/V. The unity gain
buffer usually has RF = 0 and RG open.
Figures 2-39 and 2-40 show the small signal and large
signal step responses at G = -1 V/V. Since the noise
gain is 2 V/V and CG 10 pF, the resistors were
chosen to be RF = RG = 1k and RN = 500.
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
It is also possible to add a capacitor (CF) in parallel with
RF to compensate for the destabilizing effect of CG.
This makes it possible to use larger values of RF.
The conditions for stability are summarized in
Equation 4-10.
EQUATION 4-10:
Given:
G N1 = 1 + R F R G
G N2 = 1 + C G C F
fF = 1 2 RF CF
f Z = f F G N1 G N2
We need:
f F f GBWP 2G N2 , G N1 < G N2
Use coax cables, or low-inductance wiring, to route the
signal and power to and from the PCB. Mutual and selfinductance of power wires is often a cause of crosstalk
and unusual behavior.
4.7
Typical Applications
4.7.1
POWER DRIVER WITH HIGH GAIN
Figure 4-13 shows a power driver with high gain
(1 + R2/R1). The MCP621/1S/2/3/4/5/9 op amp’s shortcircuit current makes it possible to drive significant
loads. The calibrated input offset voltage supports
accurate response at high gains. R3 should be small,
and equal to R1||R2, in order to minimize the bias
current induced offset.
f F f GBWP 4G N1 , G N1 > G N2
R1
VDD/2
4.5
Power Supply
With this family of operational amplifiers, the power
supply pin (VDD for single supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. Surface mount,
multilayer ceramic capacitors, or their equivalent,
should be used.
These op amps require a bulk capacitor (i.e., 2.2 µF or
larger) within 50 mm to provide large, slow currents.
Tantalum capacitors, or their equivalent, may be a good
choice. This bulk capacitor can be shared with other
nearby analog parts as long as crosstalk through the
supplies does not prove to be a problem.
4.6
High Speed PCB Layout
These op amps are fast enough that a little extra care
in the PCB (Printed Circuit Board) layout can make a
significant difference in performance. Good PC board
layout techniques will help you achieve the
performance shown in the specifications and Typical
Performance Curves; it will also help you minimize
EMC (Electro-Magnetic Compatibility) issues.
Use a solid ground plane. Connect the bypass local
capacitor(s) to this plane with minimal length traces.
This cuts down inductive and capacitive crosstalk.
Separate digital from analog, low-speed from highspeed, and low-power from high-power. This will
reduce interference.
Keep sensitive traces short and straight. Separate
them from interfering components and traces. This is
especially important for high-frequency (low rise time)
signals.
R2
VOUT
RL
R3
VIN
MCP62X
FIGURE 4-13:
4.7.2
Power Driver.
OPTICAL DETECTOR AMPLIFIER
Figure 4-14 shows a transimpedance amplifier, using
the MCP621 op amp, in a photo detector circuit. The
photo detector is a capacitive current source. The op
amp’s input Common mode capacitance (9 pF, typical)
and Differential capacitance (2 pF, typical) act in parallel with CD. RF provides enough gain to produce 10 mV
at VOUT. CF stabilizes the gain and limits
the transimpedance bandwidth to about 0.51 MHz.
RF’s parasitic capacitance (e.g., 0.15 pF for a
0603 SMD) acts in parallel with CF.
CF
3 pF
Photo
Detector
ID
100 nA
RF
100 k
CD
30pF
VOUT
MCP621
VDD/2
FIGURE 4-14:
Transimpedance Amplifier
for an Optical Detector.
Sometimes, it helps to place guard traces next to victim
traces. They should be on both sides of the victim
trace, and as close as possible. Connect guard traces
to ground plane at both ends, and in the middle for long
traces.
2009-2014 Microchip Technology Inc.
DS20002188D-page 27
MCP621/1S/2/3/4/5/9
4.7.3
H-BRIDGE DRIVER
Figure 4-15 shows the MCP622 dual op amp used as
a H-bridge driver. The load could be a speaker or a DC
motor.
½ MCP622
VIN
RF
RL
RGT
RGB
VOT
RF
RF
VDD/2
VOB
½ MCP622
FIGURE 4-15:
H-Bridge Driver.
This circuit automatically makes the noise gains (GN)
equal, when the gains are set properly, so that the
frequency responses match well (in magnitude and in
phase). Equation 4-11 shows how to calculate RGT and
RGB so that both op amps have the same DC gains;
GDM needs to be selected first.
EQUATION 4-11:
V OT – VOB
GDM -------------------------------- 2 V/V
VIN – VDD 2
RF
RGT = -------------------------------- G DM 2 – 1
RF
RGB = ------------------G DM 2
Equation 4-12 gives the resulting Common mode and
Differential mode output voltages.
EQUATION 4-12:
VOT + V OB
V DD
--------------------------- = ----------2
2
V DD
V OT – VOB = G DM V IN – -----------
2
DS20002188D-page 28
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
5.0
DESIGN AIDS
Microchip provides the basic design aids needed for
the MCP621/1S/2/3/4/5/9 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the
MCP621/1S/2/3/4/5/9 op amps is available on the
Microchip web site at www.microchip.com. This model
is intended to be an initial design tool that works well in
the op amp’s linear region of operation over the
temperature range. See the model file for information
on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
Filter-Lab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
5.3
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps efficiently identify
Microchip devices that fit a particular design
requirement. Available at no cost from the Microchip
web site at www.microchip.com/maps, the MAPS is an
overall selection tool for Microchip’s product portfolio
that includes Analog, Memory, MCUs and DSCs. Using
this tool, a customer can define a filter to sort features
for a parametric search of devices and export
side-by-side technical comparison reports. Helpful links
are also provided for data sheets, purchase and
sampling of Microchip parts.
5.4
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help customers achieve faster time to
market. For a complete listing of these boards and their
corresponding user’s guides and technical information,
visit
the
Microchip
web
site
at
www.microchip.com/analog tools.
Some boards that are especially useful are:
•
•
•
•
•
•
MCP6XXX Amplifier Evaluation Board 1
MCP6XXX Amplifier Evaluation Board 2
MCP6XXX Amplifier Evaluation Board 3
MCP6XXX Amplifier Evaluation Board 4
Active Filter Demo Board Kit
8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
5.5
Application Notes
The following Microchip Application Notes are
available on the Microchip web site at www.microchip.
com/appnotes and are recommended as supplemental
reference resources.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits” (DS21821)
• AN722: “Operational Amplifier Topologies and DC
Specifications” (DS00722)
• AN723: “Operational Amplifier AC Specifications
and Applications” (DS00723)
• AN884: “Driving Capacitive Loads With Op Amps”
(DS00884)
• AN990: “Analog Sensor Conditioning Circuits –
An Overview” (DS00990)
• AN1177: “Op Amp Precision Design: DC Errors”
(DS01177)
• AN1228: “Op Amp Precision Design: Random
Noise” (DS01228)
• AN1332: “Current Sensing Circuit Concepts and
Fundamentals” (DS01332)
Some of these application notes, and others, are listed
in the design guide:
• “Signal Chain Design Guide” (DS21825)
2009-2014 Microchip Technology Inc.
DS20002188D-page 29
MCP621/1S/2/3/4/5/9
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
Example:
5-Lead SOT-23 (MCP621S)
XXNN
YU25
Example
6-Lead SOT-23 ( MCP623)
XXNN
JB25
Example:
8-Lead TDFN (2 x 3) (MCP621)
AAY
129
25
8-Lead DFN (3x3) (MCP622)
Example
Device
MCP622T-E/MF
Code
DABL
DABL
1129
256
Note: Applies to 8-Lead 3x3 DFN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
DS20002188D-page 30
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2009-2014 Microchip Technology Inc.
MCP621/1S/2/3/4/5/9
Package Marking Information (Continued)
8-Lead SOIC (150 mil) (MCP621, MCP622)
Example:
MCP621E
SN e^^1129
3
256
NNN
Example
10-Lead DFN (3x3) (MCP625)
Device
MCP625T-E/MF
BAFA
1129
256
Code
BAFA
Note: Applies to 10-Lead 3x3 DFN
Example:
10-Lead MSOP (MCP625)
625EUN
129256
Example
14-Lead SOIC (.150”) (MCP624)
MCP624
3
E/SL e^^
1129256
Example
14-Lead TSSOP (MCP624)
XXXXXXXX
YYWW
NNN
624E/ST
1129
256
16-Lead QFN (4x4) (MCP629)
PIN 1
2009-2014 Microchip Technology Inc.
Example
PIN 1
629
E/ML e^^3
129256
DS20002188D-page 31
MCP621/1S/2/3/4/5/9
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