MCP6561/1R/1U/2/4
1.8V Low-Power Push-Pull Output Comparator
Features
Description
• Propagation Delay at 1.8 VDD:
- 56 ns (typical) high-to-low
- 49 ns (typical) low-to-high
• Low Quiescent Current: 100 µA (typical)
• Input Offset Voltage: ±3 mV (typical)
• Rail-to-Rail Input: VSS – 0.3V to VDD + 0.3V
• CMOS/TTL-Compatible Output
• Wide Supply Voltage Range: 1.8V to 5.5V
• Available in Single, Dual and Quad
• Packages: SC70, SOT-23, SOIC, MSOP, TSSOP
The Microchip Technology Inc. MCP6561/1R/1U/2/4
families of CMOS/TTL-compatible comparators are
offered in single, dual and quad configurations.
Typical Applications
This family operates with a single-supply voltage of 1.8V
to 5.5V, while drawing less than 100 µA/comparator of
quiescent current (typical).
Laptop Computers
Mobile Phones
Handheld Electronics
RC Timers
Alarm and Monitoring Circuits
Window Comparators
Multivibrators
Package Types
MCP6561
5-Lead SOT-23, SC70
VDD
VOUT
MCP656X
R2
R3
+
–
MCP6561R
MCP6564
14-Lead SOIC, TSSOP
OUT 1
VDD 2
5 VSS
VIN+ 1
4 -IN
VIN- 3
+
–
OUTA 1
14 OUTD
-INA 2
MCP6561U
5-Lead SOT-23
VSS 2
+
6 -INB
5 +INB
13 -IND
+INA 3
VDD 4
12 +IND
+INB 5
10 +INC
-INB 6
9 -INC
OUTB 7
11 VSS
+
–
–
7 OUTB
5-Lead SOT-23
VDD
VIN
+INA 3
VSS 4
+IN 3
Typical Application
–
+
4 -IN
+
–
• Open-Drain Output: MCP6566/6R/6U/7/9
+IN 3
+
–
Related Devices
8 VDD
-INA 2
+
–
• Microchip Advanced Part Selector (MAPS)
• Analog Demonstration and Evaluation Boards
• Application Notes
5 VDD OUTA 1
–
Design Aids
MCP6562
8-Lead SOIC, MSOP
+
–
OUT 1
VSS 2
+
•
•
•
•
•
•
•
These comparators are optimized for low-power 1.8V,
single-supply applications with greater than rail-to-rail
input operation. The internal input hysteresis eliminates
output switching due to internal input noise voltage,
reducing current draw. The push-pull output of the
MCP6561/1R/1U/2/4 family supports rail-to-rail output
swing and interfaces with CMOS/TTL logic. The output
toggle frequency can reach a typical of 4 MHz while
limiting supply current surges and dynamic power
consumption during switching.
8 OUTC
5 VDD
4 OUT
RF
2009-2020 Microchip Technology Inc.
DS20002139E-page 1
MCP6561/1R/1U/2/4
NOTES:
DS20002139E-page 2
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
1.0
ELECTRICAL
CHARACTERISTICS
1.1
Absolute Maximum Ratings†
†
Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at those or any other conditions above those
indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
VDD – VSS ...................................................................... 6.5V
Analog Input (VIN)†† .....................VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs.........VSS – 0.3V to VDD + 0.3V
Difference Input voltage ..................................... |VDD – VSS|
Output Short-Circuit Current .................................... ±25 mA
Current at Input Pins .................................................. ±2 mA
Current at Output and Supply Pins .......................... ±50 mA
Storage Temperature .................................. -65°C to +150°C
Ambient Temp. with Power Applied ............ -40°C to +125°C
Junction Temp. .......................................................... +150°C
ESD Protection on All Pins (HBM/MM) 4 kV/300V
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN- = VSS,
RL = 10 k to VDD/2 (see Figure 1-1).
Parameters
Symbol
Min
Typ
Max
Units
Conditions
VDD
1.8
—
5.5
V
IQ
60
100
130
µA
IOUT = 0
PSRR
63
70
—
dB
VCM = VSS
VCM = VSS (Note 1)
Power Supply
Supply Voltage
Quiescent Current per Comparator
Power Supply Rejection Ratio
Input
VOS
-10
3
+10
mV
VOS/T
—
2
—
µV/°C
IOS
—
1
—
pA
IB
—
1
—
pA
Input Offset Voltage
Input Offset Drift
Input Offset Current
Input Bias Current
VCM = VSS
VCM = VSS
TA = +25°C, VIN- = VDD/2
—
60
—
pA
TA = +85°C, VIN- = VDD/2
—
1500
5000
pA
TA = +125°C, VIN- = VDD/2
VCM = VSS (Notes 1, 2)
VHYST
1.0
—
5.0
mV
Input Hysteresis Linear Temp. Co.
TC1
—
10
—
µV/°C
Input Hysteresis Quadratic
Temp. Co.
TC2
—
0.3
—
µV/°C2
Common-Mode Input Voltage
Range
VCMR
VSS – 0.2
—
VDD + 0.2
V
VSS – 0.3
—
VDD + 0.3
V
VDD = 5.5V
Common-Mode Rejection Ratio
CMRR
54
66
—
dB
VCM = -0.3V to VDD + 0.3V, VDD = 5.5V
Input Hysteresis Voltage
VDD = 1.8V
50
63
—
dB
VCM = VDD/2 to VDD + 0.3V, VDD = 5.5V
54
65
—
dB
VCM = -0.3V to VDD/2, VDD = 5.5V
Common-Mode Input Impedance
ZCM
—
1013||4
—
||pF
Differential Input Impedance
ZDIFF
—
1013||2
—
||pF
High-Level Output Voltage
VOH
VDD – 0.7
—
—
V
IOUT = -3 mA/-8 mA with VDD = 1.8V/5.5V
(Note 3)
Low-Level Output Voltage
VOL
—
—
0.6
V
IOUT = 3 mA/8 mA with VDD = 1.8V/5.5V
(Note 3)
ISC
—
±30
—
mA
COUT
—
8
—
pF
Push-Pull Output
Short-Circuit Current
Output Pin Capacitance
Note 1:
2:
3:
Note 3
The input offset voltage is the center of the input referred trip points. The input hysteresis is the difference between the
input referred trip points.
VHYST at different temperatures is estimated using VHYST (TA) = VHYST @ +25°C + (TA – 25°C) TC1 + (TA – 25°C)2 TC2.
Limit the output current to the absolute maximum rating of 50 mA.
2009-2020 Microchip Technology Inc.
DS20002139E-page 3
MCP6561/1R/1U/2/4
AC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2,
VIN- = VSS, RL = 10 k to VDD/2 and CL = 25 pF (see Figure 1-1).
Parameters
Symbol
Min
Typ
Max
Units
Conditions
tPHL
—
56
80
ns
VCM = VDD/2, VDD = 1.8V
—
34
80
ns
VCM = VDD/2, VDD = 5.5V
—
49
80
ns
VCM = VDD/2, VDD = 1.8V
—
47
80
ns
VCM = VDD/2, VDD = 5.5V
tPDS
—
±10
—
ns
Rise Time
tR
—
20
—
ns
Fall Time
tF
—
20
—
ns
fTG
—
4
—
MHz
VDD = 5.5V
—
2
—
MHz
VDD = 1.8V
—
350
—
µVP-P
10 Hz to 10 MHz
Propagation Delay
High-to-Low,100 mV Overdrive
Low-to-High, 100 mV Overdrive
(1)
Skew
tPLH
Output
Maximum Toggle Frequency
(2)
Input Voltage Noise
Note 1:
2:
ENI
Propagation delay skew is defined as: tPDS = tPLH – tPHL.
ENI is based on SPICE simulation.
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated: VDD = +1.8V to +5.5V and VSS = GND.
Parameters
Symbol
Min
Typ
Max
Units
Specified Temperature Range
TA
-40
—
+125
°C
Operating Temperature Range
TA
-40
—
+125
°C
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 5-Lead SC70
JA
—
331
—
°C/W
Thermal Resistance, 5-Lead SOT-23
JA
—
220.7
—
°C/W
Thermal Resistance, 8-Lead SOIC
JA
—
149.5
—
°C/W
Thermal Resistance, 8-Lead MSOP
JA
—
211
—
°C/W
Thermal Resistance, 14-Lead SOIC
JA
—
95.3
—
°C/W
Thermal Resistance, 14-Lead TSSOP
JA
—
100
—
°C/W
Conditions
Temperature Ranges
Thermal Package Resistances
DS20002139E-page 4
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
1.2
Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC specifications.
MCP656X
VDD
200 k
+
IOUT
–
200 k
200 k
VIN = VSS
200 k
VOUT
25 pF
VSS = 0V
FIGURE 1-1:
AC and DC Test Circuit for
the Push-Pull Output Comparators.
2009-2020 Microchip Technology Inc.
DS20002139E-page 5
MCP6561/1R/1U/2/4
NOTES:
DS20002139E-page 6
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 10 k to VDD/2 and CL = 25 pF.
40%
30%
30%
VDD = 5.5V
VCM = VSS
Avg. = -0.9 mV
StDev = 2.1 mV
3588 units
VDD = 1.8V
VCM = VSS
Avg. = -0.1 mV
StDev = 2.1 mV
3588 units
Occurrences (%)
Occurrences (%)
50%
20%
10%
0%
-6
FIGURE 2-1:
40%
-4
-2 0
2
VOS (mV)
4
6
8
Input Offset Voltage.
10%
1.0
0%
36
48
Input Offset Voltage Drift.
VDD = 5.5V
VIN -
VOUT
3.0
2.0
1.0
0.0
2.5 3.0 3.5
VHYST (mV)
4.0
4.5
5.0
Input Hysteresis Voltage.
Time (3 µs/div)
Input vs. Output Signal, No
2009-2020 Microchip Technology Inc.
VDD = 1.8V
Avg. = 12 µV/°C
StDev = 0.6 µV/°C
20%
1380 Units
TA = -40°C to 125°C
VCM = VSS
10%
2
4
6
8 10 12 14 16
VHYST Drift, TC1 (µV/°C)
18
20
FIGURE 2-5:
Input Hysteresis Voltage
Drift – Linear Temp. Co. (TC1).
30%
VDD = 5.5V
VDD = 1.8V
2
20%
10%
Avg. = 0.25 µV/°C
StDev = 0.1 µV/°C2
2
Avg. = 0.3 µV/°C
StDev = 0.2 µV/°C2
1380 Units
TA = -40°C to +125°C
VCM = VSS
0%
-0.50
-1.0
FIGURE 2-3:
Phase Reversal.
2.0
30%
0
VIN+ = VDD /2
5.0
VOUT (V)
40%
60
Occurrences (%)
FIGURE 2-2:
1.5
VDD = 5.5V
Avg. = 10.4 µV/°C
StDev = 0.6 µV/°C
50%
0%
-60 -48 -36 -24 -12 0 12 24
VOS Drift (µV/°C)
4.0
5%
60%
VCM = VSS
Avg. = 0.9 µV/°C
StDev = 6.6 µV/°C
1380 Units
TA = -40°C to +125°C
20%
6.0
10%
FIGURE 2-4:
30%
7.0
15%
10
Occurrences (%)
Occurrences (%)
50%
20%
VDD = 5.5V
Avg. = 3.6 mV
StDev = 0.1 mV
3588 units
0%
-10 -8
60%
VDD = 1.8V
Avg. = 3.4 mV
StDev = 0.2 mV
3588 units
25%
-0.25
0.00
0.25
0.50
0.75
VHYST Drift, TC2 (µV/°C2)
1.00
FIGURE 2-6:
Input Hysteresis Voltage
Drift – Quadratic Temp. Co. (TC2).
DS20002139E-page 7
MCP6561/1R/1U/2/4
Note: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 10 k to VDD/2 and CL = 25 pF.
3.0
5.0
VCM = VSS
2.0
VCM = VSS
VDD= 1.8V
VHYST (mV)
V OS (mV)
4.0
1.0
0.0
-1.0
3.0
VDD= 1.8V
2.0
VDD= 5.5V
-2.0
VDD= 5.0V
-3.0
1.0
-50
-25
0
FIGURE 2-7:
Temperature.
4.0
25
50
75
Temperature (°C)
100
125
Input Offset Voltage vs.
-50
-25
0
FIGURE 2-10:
Temperature.
25
50
75
Temperature (°C)
5.0
VDD = 1.8V
2.0
TA= +125°C
4.0
VHYST (mV)
TA= +85°C
0.0
TA= +25°C
TA= -40°C
-2.0
3.0
TA= +25°C
2.0
TA= +85°C
VDD = 1.8V
-4.0
-0.3
0.0
0.3
0.6
0.9 1.2
VCM (V)
1.5
1.8
1.0
-0.3
2.1
FIGURE 2-8:
Input Offset Voltage vs.
Common-Mode Input Voltage.
3.0
TA= +25°C
0.0
-1.0
0.9
1.2
VCM (V)
1.5
1.8
2.1
-2.0
3.0
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
2.0
TA= +85°C
TA= +125°C
1.0
2.0
3.0
VCM (V)
4.0
5.0
FIGURE 2-9:
Input Offset Voltage vs.
Common-Mode Input Voltage.
DS20002139E-page 8
0.6
4.0
TA= -40°C
1.0
0.0
0.3
5.0
VDD = 5.5V
VHYST (mV)
VOS (mV)
0.0
TA= -40°C
FIGURE 2-11:
Input Hysteresis Voltage vs.
Common-Mode Input Voltage.
2.0
-3.0
-1.0
125
Input Hysteresis Voltage vs.
TA= +125°C
VOS (mV)
100
6.0
1.0
-0.5
0.5
1.5
VDD = 5.5V
2.5
3.5
VCM (V)
4.5
5.5
FIGURE 2-12:
Input Hysteresis Voltage vs.
Common-Mode Input Voltage.
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 10 k to VDD/2 and CL = 25 pF.
3.0
5.0
0.0
TA= +125°C
TA= +85°C
4.0
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
1.0
VHYST (mV)
VOS (mV)
2.0
-1.0
TA= +25°C
3.0
TA= -40°C
2.0
-2.0
-3.0
1.0
1.5
2.5
3.5
VDD (V)
4.5
5.5
1.5
FIGURE 2-13:
Input Offset Voltage vs.
Supply Voltage vs. Temperature.
4.5
5.5
140.0
VDD = 5.5V
Avg. = 97 µA
StDev= 4 µA
1794 units
VDD = 1.8V
Avg. = 88 µA
StDev= 4 µA
1794 units
40%
30%
20%
120.0
100.0
IQ (µA)
Occurrences (%)
3.5
VDD (V)
FIGURE 2-16:
Input Hysteresis Voltage vs.
Supply Voltage vs. Temperature.
50%
80.0
60.0
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
40.0
10%
20.0
0%
0.0
60
70
FIGURE 2-14:
130
120
80
90
100
IQ (µA)
110
120
130
Quiescent Current.
0.0
130
VDD = 1.8V
120
2.0
IQ (µA)
Sweep VIN+ ,VIN- = VDD /2
90
80
Sweep VIN - ,VIN+ = VDD/2
/
70
0.0
0.5
1.0
VCM (V)
1.5
2.0
FIGURE 2-15:
Quiescent Current vs.
Common-Mode Input Voltage.
2009-2020 Microchip Technology Inc.
3.0
V DD (V)
4.0
5.0
6.0
VDD = 5.5V
110
100
60
-0.5
1.0
FIGURE 2-17:
Quiescent Current vs.
Supply Voltage vs. Temperature.
110
IQ (µA)
2.5
Sweep VIN+ ,VIN- = VDD/2
100
90
Sweep VIN- ,VIN+ = VDD/2
80
70
2.5
60
-1.0
0.0
1.0
2.0
3.0
VCM (V)
4.0
5.0
6.0
FIGURE 2-18:
Quiescent Current vs.
Common-Mode Input Voltage.
DS20002139E-page 9
MCP6561/1R/1U/2/4
Note: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 10 k to VDD/2 and CL = 25 pF.
400
350
VDD = 5.5V
250
200
VDD = 1.8V
150
0
-40
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
-120
50
10
10
100
100
1000
0.0
1k
10k 100000
100k 100000
1M
10M
1000
10000
1E+07
Toggle Frequency (Hz)
0
FIGURE 2-19:
Quiescent Current vs.
Toggle Frequency.
1400
VDD= 1.8V
VDD - VOH
800
VOL
600
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
400
200
0
3.0
6.0
9.0
IOUT (mA)
12.0
3.0
VDD (V)
4.0
5.0
6.0
VDD= 5.5V
1200
VDD - VOH
TA = 125°C
TA = 85°C
TA = 25°C
TA = -40°C
1000
800
600
400
200
15.0
VOL
Output Headroom vs.
50%
VDD= 1.8V
100 mV Over-Drive
VCM = VDD /2
tPLH
Avg. = 47 ns
StDev= 2 ns
198 units
0
5
FIGURE 2-23:
Current.
50%
Occurrences (%)
FIGURE 2-20:
Output Current.
30%
2.0
0
0.0
40%
1.0
FIGURE 2-22:
Short-Circuit Current vs.
Supply Voltage vs. Temperature.
VOL, VDD - VOH (mV)
VOL, VDD - VOH (mV)
40
-80
100
Occurrences (%)
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
80
ISC (mA)
IQ (µA)
300
120
0dB Output Attenuation
100 mV Over-Drive
VCM = VDD /2
RL = Open
tPHL
Avg. = 54.4 ns
StDev= 2 ns
198 units
20%
10%
0%
10
15
IOUT (mA)
25
Output Headroom vs.Output
tPHL
Avg. = 33 ns
StDev= 1 ns
198 units
40%
20
VDD= 5.5V
100mV Over-Drive
VCM = VDD /2
30%
tPLH
Avg. = 44.6 ns
StDev= 2.7 ns
198 units
20%
10%
0%
30
35
40
45
50
55
60
65
70
Prop. Delay (ns)
FIGURE 2-21:
Low-to-High and
High-to-Low Propagation Delays.
DS20002139E-page 10
75
80
30
35
40
45
50
55
60
65
70
75
80
Prop. Delay (ns)
FIGURE 2-24:
Low-to-High and
High-to-Low Propagation Delays.
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 10 k to VDD/2 and CL = 25 pF.
80
100 mV Over-Drive
VCM = VDD /2
40%
VDD = 1.8V
Avg. = -7.3 ns
StDev= 0.8 ns
198 units
30%
VDD = 5.5V
Avg. = 11.6 ns
StDev= 2 ns
198 units
20%
100 mV Over-Drive
VCM = VDD /2
70
Prop. Delay (ns)
Occurrences (%)
50%
10%
50
40
tPLH , VDD = 5.5V
tPHL , VDD = 5.5V
30
0%
20
-20
-15
-10
-5
0
5
10
15
20
-50
-25
Prop. Delay Skew (ns)
FIGURE 2-25:
Propagation Delay Skew.
100
125
Propagation Delay vs.
VCM = VDD/2
tPHL , 10 mV Over-Drive
tPLH , 10 mV Over-Drive
Prop. Delay (ns)
Prop. Delay (ns)
FIGURE 2-28:
Temperature.
100
80
tPHL , 100 mV Over-Drive
tPLH , 100 mV Over-Drive
60
40
20
210
tPLH , VDD = 1.8V
tPHL , VDD = 1.8V
160
110
tPLH , VDD = 5.5V
tPHL , VDD = 5.5V
60
10
1.5
2.5
FIGURE 2-26:
Supply Voltage.
3.5
V DD (V)
4.5
5.5
1
Propagation Delay vs.
FIGURE 2-29:
Overdrive.
100
1000
Propagation Delay vs. Input
80
VDD = 1.8V
100 mV Over-Drive
tPHL
70
tPLH
60
50
40
30
20
0.00
10
Over-Drive (mV)
Prop. Delay (ns)
Prop. Delay (ns)
25
50
75
Temperature (°C)
VCM = VDD/2
120
70
0
260
140
80
tPLH , VDD = 1.8V
tPHL
tPHL , VDD = 1.8V
60
VDD= 5.5V
100 mV Over-Drive
60
tPHL
tPLH
50
40
30
20
0.50
1.00
VCM (V)
1.50
FIGURE 2-27:
Propagation Delay vs.
Common-Mode Input Voltage.
2009-2020 Microchip Technology Inc.
2.00
0.0
1.0
2.0
3.0
VCM (V)
4.0
5.0
6.0
FIGURE 2-30:
Propagation Delay vs.
Common-Mode Input Voltage.
DS20002139E-page 11
MCP6561/1R/1U/2/4
Note: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 10 k to VDD/2 and CL = 25 pF.
1000
10
30%
VDD = 1.8V, tPLH
VDD = 1.8V, tPHL
Occurrences (%)
Prop. Delay (µs)
100
100mV Over-Drive
VCM = VDD/2
VDD = 5.5V, tPLH
VDD = 5.5V, tPHL
1
0.1
0.01
0.001
1
0.01
10
Propagation Delay vs.
15%
10%
5%
-600
FIGURE 2-34:
Ratio (PSRR).
30%
Occurrences (%)
1E+09
1m
10µ
1E+07
100n
1E+05
TA= -40°C
TA= +25°C
TA= +85°C
TA= +125°C
1n
1E+03
10p
1E+01
0.1p
1E-01
-0.8
-400
-200
-0.4
-0.2
10%
VCM = -0.2V to VDD + 0.2V
Avg. = 0.6 mV
StDev= 0.1 mV
VCM = VDD/2 to VDD+ 0.2V
Avg. = 0.7 mV
StDev= 1 mV
VCM = -0.2V to VDD/2
Avg. = 0.5 mV
StDev= 0.1 mV
-5
VDD = 1.8V
3588 units
-4
-3
-2
-1
FIGURE 2-35:
Ratio (CMRR).
30%
78
Occurrences (%)
VCM = VSS
VDD = 1.8V to 5.5V
PSRR
CMRR
72
VCM = -0.3V to VDD + 0.3V
VDD = 5.5V
70
-25
0
25
50
75
Temperature (°C)
100
125
FIGURE 2-33:
Common-Mode Rejection
Ratio and Power Supply Rejection Ratio vs.
Temperature.
DS20002139E-page 12
0
1
2
3
4
5
CMRR (mV/V)
Input Referred
CMRR/PSRR (dB)
600
20%
0
80
-50
400
0%
-0.6
FIGURE 2-32:
Input Bias Current vs. Input
Voltage vs. Temperature.
74
200
Power Supply Rejection
Input Voltage (V)
76
0
PSRR (µV/V)
10m
1E+11
Input Current (A)
20%
0%
0.1
1
10
10
1000
100
1000
10000
100000
1E+06
Capacitive Load (nf)
FIGURE 2-31:
Capacitive Load.
VCM = VSS
Avg. = 200 µV/V
StDev= 94 µV/V
3588 units
25%
Common-Mode Rejection
V CM = V DD /2 to VDD+ 0.3V
Avg. = 0.03 mV
StDev= 0.7 mV
VCM = -0.3V to VDD + 0.3V
Avg. = 0.1 mV
StDev= 0.4 mV
20%
10%
VCM = -0.3V to VDD/2
Avg. = 0.2 mV
StDev= 0.4 mV
VDD = 5.5V
3588 units
0%
-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
CMRR (mV/V)
FIGURE 2-36:
Ratio (CMRR).
Common-Mode Rejection
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note: Unless otherwise indicated: VDD = +1.8V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD /2, VIN - = GND,
RL = 10 k to VDD/2 and CL = 25 pF.
10000
VDD = 5.5V
1000
VIN+ = 2Vpp (sine)
100
10
1
VDD = 5.5V
IB @ TA=
1000
IOS and IB (pA)
Output Jitter pk-pk (ns)
10000
IB @ TA=
100
10
1
|IOS| @ TA= 125°C
0.1
|IOS|@ TA= 85°C
0.01
0.001
0.1
100
100
1k
1000
10M
10k
100k
1M
10000 100000 1000000 1E+07
Input Frequency (Hz)
FIGURE 2-37:
Frequency.
Output Jitter vs. Input
0
1
2
3
V CM (V)
4
5
6
FIGURE 2-39:
Input Offset Current and
Input Bias Current vs. Common-Mode Input
Voltage vs. Temperature.
IOS and IB (pA)
1000
100
IB
10
1
|I OS|
0.1
25
50
75
100
Temperature (°C)
125
FIGURE 2-38:
Input Offset Current and
Input Bias Current vs. Temperature.
2009-2020 Microchip Technology Inc.
DS20002139E-page 13
MCP6561/1R/1U/2/4
NOTES:
DS20002139E-page 14
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP6561 MCP6561R MCP6561U
MCP6562
MCP6564
SOT-23
MSOP,
SOIC
SOIC,
TSSOP
1
4
1
1
4
4
3
2
2
VIN-, VINA-
3
3
1
3
3
VIN+, VINA+ Noninverting Input (Comparator A)
5
2
5
8
4
VDD
—
—
—
5
5
VINB+
—
—
—
6
6
VINB-
Inverting Input (Comparator B)
—
—
—
7
7
OUTB
Digital Output (Comparator B)
—
—
—
—
8
OUTC
Digital Output (Comparator C)
—
—
—
—
9
VINC-
Inverting Input (Comparator C)
Noninverting Input (Comparator C)
SC70,
SOT-23
SOT-23
1
3.1
Description
OUT, OUTA Digital Output (Comparator A)
Inverting Input (Comparator A)
Positive Power Supply
Noninverting Input (Comparator B)
—
—
—
—
10
VINC+
2
5
2
4
11
VSS
—
—
—
—
12
VIND+
Noninverting Input (Comparator D)
—
—
—
—
13
VIND-
Inverting Input (Comparator D)
—
—
—
—
14
OUTD
Digital Output (Comparator D)
Analog Inputs
The comparator noninverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.2
Symbol
Digital Outputs
The comparator outputs are CMOS push-pull, digital
outputs. They are designed to be compatible with
CMOS and TTL logic, and are capable of driving heavy
DC or capacitive loads.
2009-2020 Microchip Technology Inc.
3.3
Negative Power Supply
Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 1.8V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1 µF) within 2 mm of the VDD pin. These pins can
share a bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
DS20002139E-page 15
MCP6561/1R/1U/2/4
NOTES:
DS20002139E-page 16
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
4.0
APPLICATION INFORMATION
The MCP6561/1R/1U/2/4 families of push-pull output
comparators are fabricated on Microchip’s state-of-theart CMOS process. They are suitable for a wide range
of high-speed applications requiring low-power
consumption.
4.1
Comparator Inputs
4.1.1
The MCP6561/1R/1U/2/4 families have internally set
hysteresis VHYST that is small enough to maintain input
offset accuracy and large enough to eliminate output
chattering caused by the comparator’s own input noise
voltage, ENI. Figure 4-1 depicts this behavior. Input
offset voltage (VOS) is the center (average) of the (input
referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points.
VDD = 5.0V
VIN–
VOUT
Hysteresis
25
20
15
10
5
0
-5
-10
-15
-20
-25
-30
Input Voltage (10 mV/div)
Output Voltage (V)
VIN+ Bond
Pad
NORMAL OPERATION
The input stage of these families of devices uses three
differential input stages in parallel: one operates at low
input voltages, one at high input voltages and one at
middle input voltages. With this topology, the input voltage
range is 0.3V above VDD and 0.3V below VSS, while providing low offset voltage throughout the Common-mode
range. The input offset voltage is measured at both
VSS – 0.3V and VDD + 0.3V to ensure proper operation.
8
7
6
5
4
3
2
1
0
-1
-2
-3
VDD Bond
Pad
Time (100 ms/div)
VSS
Bond V IN
Pad
Input
Stage
Bond
Pad
FIGURE 4-2:
Structures.
Simplified Analog Input ESD
In order to prevent damage and/or improper operation
of these amplifiers, the circuits they are in must limit the
currents (and voltages) at the VIN+ and VIN- pins (see
Section 1.1 “Absolute Maximum Ratings†” at the
beginning of Section 1.0 “Electrical Characteristics”). Figure 4-3 shows the recommended approach
to protecting these inputs. The internal ESD diodes
prevent the input pins (VIN+ and VIN-) from going too far
below ground, and the resistors, R1 and R2, limit the
possible current drawn out of the input pin. Diodes, D1
and D2, prevent the input pin (VIN+ and VIN-) from
going too far above VDD. When implemented as
shown, resistors, R1 and R2, also limit the current
through D1 and D2.
VDD
D1
V1
+
MCP656X
–
R1
D2
V2
R2
R3
FIGURE 4-1:
The MCP6561/1R/1U/2/4
Comparators’ Internal Hysteresis Eliminates
Output Chatter Caused by Input Noise Voltage.
R1
VSS – (minimum expected V1)
2 mA
4.1.2
R2
VSS – (minimum expected V2)
2 mA
INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-2. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD. Their breakdown voltage is high enough to
allow normal operation and low enough to bypass ESD
events within the specified limits.
2009-2020 Microchip Technology Inc.
VOUT
FIGURE 4-3:
Protecting the Analog Inputs.
It is also possible to connect the diodes to the left of the
resistors, R1 and R2. In this case, the currents through
the diodes, D1 and D2, need to be limited by some other
mechanism. The resistor then serves as an inrush
current limiter; the DC current into the input pins (VIN+
and VIN-) should be very small.
DS20002139E-page 17
MCP6561/1R/1U/2/4
A significant amount of current can flow out of the
inputs when the Common-mode voltage (VCM) is below
ground (VSS); see Figure 2-32. Applications that are
high-impedance may need to limit the usable voltage
range.
4.1.3
4.3.1
Figure 4-4 shows a noninverting circuit for singlesupply applications using just two resistors. The
resulting hysteresis diagram is shown in Figure 4-5.
PHASE REVERSAL
VDD
The MCP6561/1R/1U/2/4 comparator families use
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supply voltages. Figure 2-3 shows an input voltage
exceeding both supplies with no resulting phase
inversion.
4.2
Push-Pull Output
The push-pull output is designed to be compatible with
CMOS and TTL logic, while the output transistors are
configured to give rail-to-rail output performance. They
are driven with circuitry that minimizes any switching
current (shoot-through current from supply-to-supply)
when the output is transitioned from high-to-low or from
low-to-high (see Figure 2-15 and Figure 2-18 for more
information).
4.3
NONINVERTING CIRCUIT
Externally Set Hysteresis
Greater flexibility in selecting hysteresis (or input trip
points) is achieved by using external resistors.
Hysteresis reduces output chattering when one input is
slowly moving past the other. It also helps in systems
where it is best not to cycle between high and low
states too frequently (e.g., air conditioner thermostatic
control). Output chatter also increases the dynamic
supply current.
–
VREF
VOUT
MCP656X
+
VIN
R1
RF
FIGURE 4-4:
Noninverting Circuit with
Hysteresis for Single Supply.
VOUT
VDD
VOH
High-to-Low
VOL
VSS
VSS
Low-to-High
VIN
VTHL VTLH
VDD
FIGURE 4-5:
Hysteresis Diagram for the
Noninverting Circuit.
The trip points for Figure 4-4 and Figure 4-5 are:
EQUATION 4-1:
R1
R1
VTLH = V REF 1 + ------- – V OL -------
RF
RF
R1
R 1
VTHL = V REF 1 + ------- – V OH -------
RF
RF
Where:
VTLH = Trip Voltage from Low-to-High
VTHL = Trip Voltage from High-to-Low
DS20002139E-page 18
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
4.3.2
INVERTING CIRCUIT
Where:
Figure 4-6 shows an inverting circuit for single supply
using three resistors. The resulting hysteresis diagram
is shown in Figure 4-7.
R2R3
R 23 = ------------------R2 + R3
R3
V23 = ------------------- V DD
R2 + R3
VDD
VIN
–
VDD
Using this simplified circuit, the trip voltage can be
calculated using the following equation:
VOUT
MCP656X
+
EQUATION 4-2:
R2
RF
R 23
V THL = V OH ----------------------- + V 23 ----------------------
R
+
R
R
23
23 + R F
F
RF
R3
RF
R23
V TLH = V OL ----------------------- + V 23 ----------------------
R
+
R
R
23
23 + R F
F
FIGURE 4-6:
Hysteresis.
Inverting Circuit with
Where:
VTLH = Trip Voltage from Low-to-High
VTHL = Trip Voltage from High-to-Low
VOUT
VDD
VOH
Figure 2-20, and Figure 2-23 can be used to determine
typical values for VOH and VOL.
Low-to-High
VOL
VSS
VSS
High-to-Low
4.4
VIN
VTLH VTHL
FIGURE 4-7:
Inverting Circuit.
VDD
Hysteresis Diagram for the
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge rate performance.
4.5
In order to determine the trip voltages (VTHL and VTLH)
for the circuit shown in Figure 4-6, R2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to VDD, as shown in Figure 4-8.
VDD
Bypass Capacitors
Capacitive Loads
Reasonable capacitive loads (e.g., logic gates) have
little impact on propagation delay (see Figure 2-31).
The supply current increases with increasing toggle
frequency (Figure 2-19), especially with higher capacitive loads. The output slew rate and propagation delay
performance will be reduced with higher capacitive
loads.
–
MCP656X
+
VOUT
VSS
V23
R23
FIGURE 4-8:
RF
Thevenin Equivalent Circuit.
2009-2020 Microchip Technology Inc.
DS20002139E-page 19
MCP6561/1R/1U/2/4
4.6
PCB Surface Leakage
4.7
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012. A 5V difference would
cause 5 pA of current to flow. This is greater than the
MCP6561/1R/1U/2/4 families’ bias current at +25°C
(1 pA, typical).
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-9.
IN-
IN+
VSS
PCB Layout Technique
When designing the PCB layout, it is critical to note that
analog and digital signal traces are adequately
separated to prevent signal coupling. If the comparator
output trace is at close proximity to the input traces,
then large output voltage changes from VSS to VDD, or
visa versa, may couple to the inputs and cause the
device output to oscillate. To prevent such oscillation,
the output traces must be routed away from the input
pins. The SC70 and SOT-23 are relatively immune
because the output pin OUT (Pin 1) is separated by the
power pin VDD/VSS (Pin 2) from the input pin +IN (as
long as the analog and digital traces remain separated
throughout the PCB). However, the pinouts for the dual
and quad packages (SOIC, MSOP, TSSOP) have OUT
and -IN pins (Pins 1 and 2) close to each other. The
recommended layout for these packages is shown in
Figure 4-10.
VDD
OUTA
Guard Ring
FIGURE 4-9:
Example Guard Ring Layout
for Inverting Circuit.
1.
2.
Inverting Configuration (Figures 4-6 and 4-9):
a) Connect the guard ring to the noninverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).
b) Connect the inverting pin (VIN-) to the input
pad without touching the guard ring.
Noninverting Configuration (Figure 4-4):
a) Connect the noninverting pin (VIN+) to the
input pad without touching the guard ring.
b) Connect the guard ring to the inverting input
pin (VIN-).
-INA
OUTB
+INA
-INB
VSS
+INB
FIGURE 4-10:
4.8
Recommended Layout.
Unused Comparators
An unused amplifier in a quad package (MCP6564)
should be configured as shown in Figure 4-11. This
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see Figure 2-15 and
Figure 2-18).
¼ MCP6564
VDD
–
+
FIGURE 4-11:
DS20002139E-page 20
Unused Comparators.
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
4.9
Typical Applications
4.9.1
4.9.3
PRECISE COMPARATOR
Some applications require higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6291) to gain-up the input signal
before it reaches the comparator. Figure 4-12 shows
an example of this approach.
BISTABLE MULTIVIBRATOR
A simple bistable multivibrator design is shown in
Figure 4-14. VREF needs to be between the power
supplies (VSS = GND and VDD) to achieve oscillation.
The output duty cycle changes with VREF.
R1
R2
VREF
VDD
VDD
VREF
+
+
MCP6291
–
MCP6561
–
VOUT
VDD
VIN
R1
R2
VREF
FIGURE 4-12:
Comparator.
4.9.2
+
MCP656X
–
C1
VOUT
FIGURE 4-14:
R3
Bistable Multivibrator.
Precise Inverting
WINDOWED COMPARATOR
Figure 4-13 shows one approach to designing a
windowed comparator. The AND gate produces a logic
‘1’ when the input voltage is between VRB and VRT
(where VRT > VRB).
VDD
VRT
+
–
VIN
1/2
MCP6562
+
VRB
FIGURE 4-13:
–
1/2
MCP6562
Windowed Comparator.
2009-2020 Microchip Technology Inc.
DS20002139E-page 21
MCP6561/1R/1U/2/4
NOTES:
DS20002139E-page 22
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
5.0
DESIGN AIDS
5.3
5.1
Microchip Advanced Part Selector
(MAPS)
The following Microchip Application Note is available
on the Microchip website at www.microchip.com and is
recommended as a supplemental reference resource:
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for data sheets,
purchase and sampling of Microchip parts.
5.2
Application Notes
• AN895, “Oscillator Circuits For RTD Temperature
Sensors”, DS00895
Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
a complete listing of these boards and their
corresponding user’s guides and technical information,
visit the Microchip website at www.microchip.com/
analogtools. Three of our boards that are especially
useful are:
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
• 14-Pin SOIC/TSSOP/DIP Evaluation Board,
P/N SOIC14EV
• 5/6-Pin SOT23 Evaluation Board, P/N VSUPEV2
2009-2020 Microchip Technology Inc.
DS20002139E-page 23
MCP6561/1R/1U/2/4
NOTES:
DS20002139E-page 24
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
6.0
PACKAGING INFORMATION
6.1
Package Marking Information
5-Lead SC-70 (MCP6561)
Example:
BC25
XXNN
5-Lead SOT-23 (MCP6561, MCP6561R, MCP6561U)
Device
XXNN
Example:
Code
MCP6561T
WBNN
MCP6561RT
WANN
MCP6561UT
WKNN
WA25
Note: Applies to 5-Lead SOT-23.
8-Lead MSOP (MCP6562)
XXXXXX
YWWNNN
Example:
6562E
932256
8-Lead SOIC (150 mil) (MCP6562)
Example:
XXXXXXXX
MCP6562E
NNN
256
XXXXYYWW
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
SN e3 1932
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2009-2020 Microchip Technology Inc.
DS20002139E-page 25
MCP6561/1R/1U/2/4
Package Marking Information (Continued)
14-Lead SOIC (150 mil) (MCP6564)
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
Example:
MCP6564
E/SL e3
1932256
14-Lead TSSOP (MCP6564)
Example:
XXXXXXXX
YYWW
NNN
MCP6564E
1932
256
DS20002139E-page 26
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (LT) [SC70]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
e
e
3
B
1
E1
E
2X
0.15 C
4
N
5X TIPS
0.30 C
NOTE 1
2X
0.15 C
5X b
0.10
C A B
TOP VIEW
C
c
A2
A
SEATING
PLANE
A1
L
SIDE VIEW
END VIEW
Microchip Technology Drawing C04-061-LT Rev E Sheet 1 of 2
2009-2020 Microchip Technology Inc.
DS20002139E-page 27
MCP6561/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (LT) [SC70]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Standoff
A1
A2
Molded Package Thickness
Overall Length
D
Overall Width
E
Molded Package Width
E1
b
Terminal Width
Terminal Length
L
c
Lead Thickness
MIN
0.80
0.00
0.80
0.15
0.10
0.08
MILLIMETERS
NOM
5
0.65 BSC
2.00 BSC
2.10 BSC
1.25 BSC
0.20
-
MAX
1.10
0.10
1.00
0.40
0.46
0.26
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-061-LT Rev E Sheet 2 of 2
DS20002139E-page 28
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (LT) [SC70]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
Gx
SILK SCREEN
3
2
1
C
G
4
5
Y
X
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width
X
Contact Pad Length
Y
Distance Between Pads
G
Distance Between Pads
Gx
MIN
MILLIMETERS
NOM
0.65 BSC
2.20
MAX
0.45
0.95
1.25
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2061-LT Rev E
2009-2020 Microchip Technology Inc.
DS20002139E-page 29
MCP6561/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 C 2X
D
e1
A
D
N
E/2
E1/2
E1
E
(DATUM D)
(DATUM A-B)
0.15 C D
2X
NOTE 1
1
2
e
B
NX b
0.20
C A-B D
TOP VIEW
A
A A2
0.20 C
SEATING PLANE
A
SEE SHEET 2
A1
C
SIDE VIEW
Microchip Technology Drawing C04-091-OT Rev F Sheet 1 of 2
DS20002139E-page 30
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
c
T
L
L1
VIEW A-A
SHEET 1
Units
Dimension Limits
N
Number of Pins
e
Pitch
e1
Outside lead pitch
A
Overall Height
A2
Molded Package Thickness
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Foot Length
L
Footprint
L1
I
Foot Angle
c
Lead Thickness
b
Lead Width
MIN
0.90
0.89
-
0.30
0°
0.08
0.20
MILLIMETERS
NOM
5
0.95 BSC
1.90 BSC
2.80 BSC
1.60 BSC
2.90 BSC
0.60 REF
-
MAX
1.45
1.30
0.15
0.60
10°
0.26
0.51
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-091-OT Rev F Sheet 2 of 2
2009-2020 Microchip Technology Inc.
DS20002139E-page 31
MCP6561/1R/1U/2/4
5-Lead Plastic Small Outline Transistor (OT) [SOT23]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
X
SILK SCREEN
5
Y
Z
C
G
1
2
E
GX
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
C
Contact Pad Spacing
X
Contact Pad Width (X5)
Contact Pad Length (X5)
Y
Distance Between Pads
G
Distance Between Pads
GX
Overall Width
Z
MIN
MILLIMETERS
NOM
0.95 BSC
2.80
MAX
0.60
1.10
1.70
0.35
3.90
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2091-OT Rev F
DS20002139E-page 32
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2020 Microchip Technology Inc.
DS20002139E-page 33
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002139E-page 34
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2020 Microchip Technology Inc.
DS20002139E-page 35
MCP6561/1R/1U/2/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
NOTE 1
2
1
e
B
NX b
0.25
C A–B D
NOTE 5
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
8X
A1
SIDE VIEW
0.10 C
h
R0.13
h
R0.13
H
SEE VIEW C
VIEW A–A
0.23
L
(L1)
VIEW C
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 1 of 2
DS20002139E-page 36
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
L1
Footprint
Foot Angle
c
Lead Thickness
b
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0.17
0.31
5°
5°
MILLIMETERS
NOM
8
1.27 BSC
6.00 BSC
3.90 BSC
4.90 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-SN Rev E Sheet 2 of 2
2009-2020 Microchip Technology Inc.
DS20002139E-page 37
MCP6561/1R/1U/2/4
8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-SN Rev E
DS20002139E-page 38
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
NOTE 5
D
N
E
2
E2
2
E1
E
2X
0.10 C D
NOTE 1
1
2
2X N/2 TIPS
0.20 C
3
e
NX b
B
0.25
NOTE 5
C A–B D
TOP VIEW
0.10 C
C
A A2
SEATING
PLANE
14X
A1
h
0.10 C
SIDE VIEW
h
R0.13
H
R0.13
c
SEE VIEW C
L
VIEW A–A
(L1)
VIEW C
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 1 of 2
2009-2020 Microchip Technology Inc.
DS20002139E-page 39
MCP6561/1R/1U/2/4
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Pins
N
e
Pitch
Overall Height
A
Molded Package Thickness
A2
§
Standoff
A1
Overall Width
E
Molded Package Width
E1
Overall Length
D
Chamfer (Optional)
h
Foot Length
L
Footprint
L1
Lead Angle
Foot Angle
c
Lead Thickness
Lead Width
b
Mold Draft Angle Top
Mold Draft Angle Bottom
MIN
1.25
0.10
0.25
0.40
0°
0°
0.10
0.31
5°
5°
MILLIMETERS
NOM
14
1.27 BSC
6.00 BSC
3.90 BSC
8.65 BSC
1.04 REF
-
MAX
1.75
0.25
0.50
1.27
8°
0.25
0.51
15°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimension D does not include mold flash, protrusions or gate burrs, which shall
not exceed 0.15 mm per end. Dimension E1 does not include interlead flash
or protrusion, which shall not exceed 0.25 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-065-SL Rev D Sheet 2 of 2
DS20002139E-page 40
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
14-Lead Plastic Small Outline (SL) - Narrow, 3.90 mm Body [SOIC]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
14
SILK SCREEN
C
Y
1
2
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Contact Pad Width (X14)
X
Contact Pad Length (X14)
Y
MIN
MILLIMETERS
NOM
1.27 BSC
5.40
MAX
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2065-SL Rev D
2009-2020 Microchip Technology Inc.
DS20002139E-page 41
MCP6561/1R/1U/2/4
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
N
E
2
E1
2
E1
E
1
2X 7 TIPS
0.20 C B A
2
e
TOP VIEW
A
C
A2 A
SEATING
PLANE
14X
0.10 C
14X b
0.10
A1
A
C B A
SIDE VIEW
SEE DETAIL B
VIEW A–A
Microchip Technology Drawing C04-087 Rev D Sheet 1 of 2
DS20002139E-page 42
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(ș2)
R1
H
R2
c
L
ș1
(L1)
(ș3)
DETAIL B
Number of Terminals
Pitch
Overall Height
Standoff
Molded Package Thickness
Overall Length
Overall Width
Molded Package Width
Terminal Width
Terminal Thickness
Terminal Length
Footprint
Lead Bend Radius
Lead Bend Radius
Foot Angle
Mold Draft Angle
Mold Draft Angle
Notes:
Units
Dimension Limits
N
e
A
A1
A2
D
E
E1
b
c
L
L1
R1
R2
ș1
ș2
ș3
MIN
–
0.05
0.80
4.90
4.30
0.19
0.09
0.45
0.09
0.09
0°
–
–
MILLIMETERS
NOM
14
0.65 BSC
–
–
1.00
5.00
6.40 BSC
4.40
–
–
0.60
1.00 REF
–
–
–
12° REF
12° REF
MAX
1.20
0.15
1.05
5.10
4.50
0.30
0.20
0.75
–
–
8°
–
–
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-087 Rev D Sheet 2 of 2
2009-2020 Microchip Technology Inc.
DS20002139E-page 43
MCP6561/1R/1U/2/4
14Lead Thin Shrink Small Outline Package [ST] 4.4 mm Body [TSSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
G
SILK SCREEN
C
Y
X
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C
Contact Pad Width (Xnn)
X
Contact Pad Length (Xnn)
Y
Contact Pad to Contact Pad (Xnn)
G
MIN
MILLIMETERS
NOM
0.65 BSC
5.90
MAX
0.45
1.45
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2087 Rev D
DS20002139E-page 44
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
APPENDIX A:
REVISION HISTORY
Revision E (March 2020)
The following is the list of modifications:
1.
Updated package drawings for the 5-lead SC-70
and 14-lead TSSOP packages in Section 6.0
“Packaging Information”.
Revision D (October 2019)
The following is the list of modifications:
1.
Updated Section 6.0 “Packaging
Information”.
Revision C (February 2013)
The following is the list of modifications:
1.
2.
Added the Analog Input (VIN) parameter in
Section 1.0 “Electrical Characteristics”.
Updated the package drawing section.
Revision B (August 2009)
The following is the list of modifications:
1.
2.
Added MCP6561U throughout the document.
Updated package drawing section.
Revision A (March 2009)
• Original Release of this Document.
2009-2020 Microchip Technology Inc.
DS20002139E-page 45
MCP6561/1R/1U/2/4
NOTES:
DS20002139E-page 46
2009-2020 Microchip Technology Inc.
MCP6561/1R/1U/2/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device:
–
X
/XX
Temperature
Range
Package
MCP6561T:
Single Comparator (Tape and Reel)
(SC70, SOT-23)
MCP6561RT: Single Comparator (Tape and Reel)
(SOT-23 only)
MCP6561UT: Single Comparator (Tape and Reel)
(SOT-23 only)
MCP6562:
Dual Comparator
MCP6562T:
Dual Comparator (Tape and Reel)
MCP6564:
Quad Comparator
MCP6564T:
Quad Comparator (Tape and Reel)
Temperature Range: E
= -40C to +125C
Package:
=
=
=
=
=
Examples:
a) MCP6561T-E/LT:
Tape and Reel,
Extended Temperature,
5-Lead SC70 Package.
b) MCP6561T-E/OT: Tape and Reel,
Extended Temperature,
5-Lead SOT-23 Package.
a) MCP6561RT-E/OT: Tape and Reel,
Extended Temperature,
5-Lead SOT-23 Package.
a) MCP6561UT-E/OT: Tape and Reel,
Extended Temperature,
5-Lead SOT-23 Package.
a) MCP6562-E/MS:
b) MCP6562-E/SN:
LT
OT
MS
SN
ST
SL =
Plastic Small Outline Transistor (SC70), 5-Lead
Plastic Small Outline Transistor (SOT-23), 5-Lead
Plastic Micro Small Outline Transistor (MSOP), 8-Lead
Plastic Small Outline Transistor (SOIC), 8-Lead
Plastic Thin Shrink Small Outline Transistor (TSSOP),
14-Lead
Plastic Small Outline Transistor (SOIC), 14-Lead
2009-2020 Microchip Technology Inc.
Extended Temperature,
8-Lead MSOP Package.
Extended Temperature,
8-Lead SOIC Package.
a) MCP6564T-E/SL: Tape and Reel,
Extended Temperature,
14-Lead SOIC Package.
b) MCP6564T-E/ST: Tape and Reel,
Extended Temperature,
14-Lead TSSOP Package.
DS20002139E-page 47
MCP6561/1R/1U/2/4
NOTES:
DS20002139E-page 48
2009-2020 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2020, Microchip Technology Incorporated, All Rights
Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2009-2020 Microchip Technology Inc.
ISBN: 978-1-5224-5713-8
DS20002139E-page 49
Worldwide Sales and Service
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Corporate Office
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Tel: 480-792-7200
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