MTCH650/2
Programmable Voltage Boost with Built-in Level Shifters
and Serial Interface with Output Enable
MTCH652 Features:
MTCH650 Features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
FIGURE 1:
21 High Voltage I/O lines
1.8V to 5.5V Input Operating Range
Low Quiescent Current: 1.5 x ILIM or 1.5 x IPK (L) (whichever is
greater), where ILIM = selected current limit value and
IPK (L) = Peak inductor current. Examples of recommended inductors are shown in Table 5-1.
DS40001749A-page 14
Preliminay
2014 Microchip Technology Inc.
MTCH650/2
FIGURE 5-1:
MTCH652 SOIC AND
SSOP RECOMMENDED
LAYOUT
FIGURE 5-2:
MTCH652 UQFN
RECOMMENDED LAYOUT
2014 Microchip Technology Inc.
Preliminay
DS40001749A-page 15
MTCH650/2
6.0
APPLICATION EXAMPLE
MTCH650/2 are very simple to set up and use, only
requiring configuration of a Configuration Word and a
Data Word. The difference between MTCH650 and
MTCH652 is the addition of the PWM input and the
selectable options for VOUT and ILIM. Figure 6-1
shows a typical application using a PIC®
microcontroller and MTCH652.
FIGURE 6-1:
TYPICAL APPLICATION
PIC® MCU
6.1
MTCH650/2 Connections
6.2
The following pins are required to drive MTCH650/2
from the host side:
•
•
•
•
•
PWM – Output (MTCH652 only)
OE – Output
LE – Output
SDO(1) – serial data output
SCLK(1) – serial data clock output
The following shows the basic operations for
initialization addressed in additional individual notes
within this section:
1.
2.
Note 1: These pins can be from a standard
MSSP module or bit-banged.
3.
-
DS40001749A-page 16
MTCH650/2 Initialization
Preliminary
On the host, I/O ports to be used for OE and LE
functionality should be configured as outputs.
Set OE low and set LE high.
Configure the host SPI port for 1 MHz or
equivalent bit-bang function. It is recommended
that a function that takes the bit mask and sends
it to MTCH650/2 be created. Example 6-1
shows such an example.
Host sends command to configure the
MTCH650/2 CONFIG Word to default settings:
ILIMDIS = 0 – ILO Enabled
VCMPSEN = 0 – Synchronization Disabled
SSDID = 0 – Soft Start Enabled
ILIM = 00 – ILIM = 200 mA
VOUT = 000 – Boost Disabled
2014 Microchip Technology Inc.
MTCH650/2
4.
(MTCH652 only) Configure the host PWM to
output on the correct I/O pin. It is recommended
that PWM starts at a frequency of 500 kHz with
a 70% duty cycle. It may be necessary to later
adjust the parameters to optimize the efficiency
and ripple.
EXAMPLE 6-1:
6.5
For Low-Power or Shutdown modes, set VOUT =
000. Turn off the PWM for the absolute minimum
operating power mode.
6.6
BIT-BANG CODE
void send MTCH65x (unsigned long data)
{
unsigned int x;
MTCH65x_LE_LAT_CLR;
// clear LE to start
for (x=0; x VDD) ................................................................................................... 20 mA
Maximum output current sunk by any I/O pin................................................................................................... 25 mA
Maximum output current sourced by any I/O pin ............................................................................................. 25 mA
Maximum current sourced by analog outputs, -40°C < TA < +85°C for industrial ............................................ 25 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD – IOH} + {(VDD – VOH) x IOH} + (VOL x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
7.2
Standard Operating Conditions
The standard operating conditions for any device are defined as:
Operating Voltage:
Operating Temperature:
VDDMIN VDD VDDMAX
TA_MIN TA TA_MAX
VDD — Operating Supply Voltage
MTCH650/2
VDDMIN ..................................................................................................................................... +1.8V
VDDMAX .................................................................................................................................... +5.5V
TA — Operating Ambient Temperature Range
Industrial Temperature
TA_MIN ...................................................................................................................................... -40°C
TA_MAX .................................................................................................................................... +85°C
Note 1:
Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 7-6: “Thermal
Characteristics” to calculate device specifications.
DS40001749A-page 18
Preliminary
2014 Microchip Technology Inc.
MTCH650/2
7.3
DC Characteristics
TABLE 7-1:
BASIC OPERATING CHARACTERISTICS
DC Characteristics
Sym.
Standard Operating Conditions (unless otherwise stated)
Characteristic
Min.
Typ†
Max.
Units
Conditions
VDD
Supply Voltage
1.8
—
5.5
V
IPD
Standby Current
—
2
TBD
µA
VDD = 3.6V
IDD
Supply Current(1)
—
1.4
TBD
mA
ILIM = 00, VDD = 3.6, Boost to
18V, unloaded
IDD
Supply Current(1)
—
0.85
TBD
mA
ILIM = 01, VDD = 3.6, Boost to
18V, unloaded
IDD
Supply Current(1)
—
0.8
TBD
mA
ILIM = 10, VDD = 3.6, Boost to
18V, unloaded
VPOR
Power-on Reset Release Voltage
0.7
1.1
1.75
V
Note 1:
ILIM = 11, current strongly dependent on OSCIN frequency and duty cycle.
TABLE 7-2:
I/O CHARACTERISTICS
DC Characteristics
Sym.
Standard Operating Conditions (unless otherwise stated)
Min.
Typ†
Max.
Units
VIL
Digital Input Low Voltage
VSS
—
0.2 VDD
V
VIH
Digital Input High Voltage
0.8 VDD
—
VDD
V
IIL
Digital Input Leakage Current
—
±5
±125
nA
VOL
Output Low Voltage
—
—
0.6
V
IOL = 5 mA
VOH
Output High Voltage
VPP – 0.7
—
—
V
IOH = 5 mA
7.4
Characteristic
Conditions
85°C; VSS VPIN VDD
Analog and AC Characteristics
TABLE 7-3:
SERIAL INTERFACE TIMING REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Max.
Units
SI1
tch
External CLK High Time
0.5
µs
SI2
tcl
External CLK Low Time
0.5
µs
SI3
tcper
External CLK Period
1
µs
SI4
fc
External CLK Frequency
DC
1
MHz
SI5
tds
DIN Setup Time
10
ns
SI6
tdh
DIN Hold Time
10
ns
SI7
tls
LE Setup Time
10
ns
SI8
tlh
LE High Time
10
ns
Note 1:
See Figure 3-1 for the corresponding timing diagram.
2014 Microchip Technology Inc.
Preliminary
Conditions
DS40001749A-page 19
MTCH650/2
TABLE 7-4:
MTCH652 VOLTAGE BOOST AND TIMING AND ANALOG CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
VB1
—
VB2
VB3
VB4
VB5
Sym.
FOSC
—
VPP
VRIPP
ILIMIT
IAVG
Characteristic
Min.
Typ.
Max.
Units
External OSCIN Frequency
—
—
2
MHz
—
—
90%
—
VDD
V
VOUT = 000 (boost disabled)
Duty Cycle
High Voltage Output
Ripple Voltage
Switch Current Limit(1)
Average Output Current
DS40001749A-page 20
VDD – 0.8 VDD – 0.3
Conditions
5.4
6
6.6
V
VOUT = 001
7.2
8
8.8
V
VOUT = 010
9.0
10
11.0
V
VOUT = 011
10.8
12
13.2
V
VOUT = 100
12.6
14
15.4
V
VOUT = 101
14.4
16
17.6
V
VOUT = 110
16.2
18
19.8
V
VOUT = 111
—
40
—
mVPP VDD = 3.6V, Boost to VPP =
18V, 1 µH inductor, 150 pF
load, 1 µF VPP capacitor, ILIM
= 00
—
75
—
mVPP VDD = 3.6V, Boost to VPP =
18V, 1 µH inductor, 150 pF
load, 1 µF VPP capacitor, ILIM
= 01
—
85
—
mVPP VDD = 3.6V, Boost to VPP =
18V, 1 µH inductor, 150 pF
load, 1 µF VPP capacitor, ILIM
= 10
—
0.15
0.3
A
ILIM = 00
—
0.6
1
A
ILIM = 01
—
1
1.5
A
ILIM = 10
—
—
1.6
A
ILIM = 11, OSCIN/duty cycle
Limited
—
0.5
—
mA
Preliminary
2014 Microchip Technology Inc.
MTCH650/2
TABLE 7-4:
MTCH652 VOLTAGE BOOST AND TIMING AND ANALOG CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
VB9
Sym.
Characteristic
tresp
Response Time
Fall Time
Note 1:
2:
Min.
Typ.
Max.
Units
Conditions
—
2.3
—
ms
Total for all channels;
VPP = 18V,
Cload = 15pF per channel,
OE frequency = 1 MHZ,
ILIM = 00, VDD = 3.6V Boost
with 1 µH inductor to VPP =
18V, CVPP = 1uF, unloaded,
FOSC = 1 MHz, (Note 2)
—
400
—
µs
Total for all channels;
VPP = 18V,
Cload = 15pF per channel,
OE frequency = 1 MHZ,
ILIM = 01, VDD = 3.6V Boost
with 1 µH inductor to VPP =
18V, CVPP = 1uF, unloaded,
FOSC = 1 MHz, (Note 2)
—
175
—
µs
Total for all channels;
VPP = 18V,
Cload = 15pF per channel,
OE frequency = 1 MHZ,
ILIM = 10, VDD = 3.6V Boost
with 1 µH inductor to VPP =
18V, CVPP = 1uF, unloaded,
FOSC = 1 MHz, (Note 2)
—
—
100
µs
All ILIM, VDD = 3.6V, program
fall from VPP = 18V to VPP =
6V Boost with 1 µH inductor,
unloaded, CVPP = 1uF, FOSC
= 1 MHz
These specs are tested at DC. Actual thresholds under dynamic operation may be higher.
CVPP = Capacitance between VPP and VSS = C2 in application diagram.
TABLE 7-5:
MTCH650 VPP ANALOG CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
VP1
Sym.
VPP
Characteristic
High Voltage Input
2014 Microchip Technology Inc.
Min.
Max.
Units
3.6
18
V
VDD < 3.6V
VDD
18
V
VDD 3.6V
Preliminary
Conditions
DS40001749A-page 21
MTCH650/2
TABLE 7-6:
THERMAL CHARACTERISTICS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Typ.
Units
TH01
JA
Thermal Resistance Junction to Ambient
TH02
JC
Thermal Resistance Junction to Case
69.7
48
18.9
C/W
C/W
C/W
TH03
TJMAX
Maximum Junction Temperature
12
150
C/W
C
DS40001749A-page 22
Preliminary
Conditions
28-pin SOIC package
28-pin UQFN package
28-pin SOIC package
28-pin UQFN package
2014 Microchip Technology Inc.
MTCH650/2
NOTES:
2014 Microchip Technology Inc.
Preliminary
DS40001749A-page 23
MTCH650/2
8.0
TYPICAL PERFORMANCE
CURVES
The graphs and tables provided in this section are for design guidance and are not tested.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
“Typical” represents the mean of the distribution at 25C. “MAXIMUM”, “Max.”, “MINIMUM” or “Min.”
represents (mean + 3) or (mean - 3) respectively, where is a standard deviation, over each
temperature range.
FIGURE 8-1:
TYPICAL PWM; fPWM = 500
kHz, 70% DUTY CYCLE,
VDD = 3.3V
FIGURE 8-3:
OE vs. OUT00; VDD = 3.3V,
VPP = 18V,
CVPP(C2) = 1µF
FIGURE 8-2:
OE vs. OUT00; VDD = 3.3V,
VPP = 18V,
CVPP(C2) = 10µF
FIGURE 8-4:
BOOST VPP 6V TO 18V
AND DISCHARGE 18V TO
6V; DISCHARGE ON,
VDD = 3.3V,
CVPP (C2) = 10µF
DS40001749A-page 24
Preliminary
2014 Microchip Technology Inc.
MTCH650/2
FIGURE 8-5:
BOOST VPP 6V TO 18V
AND DISCHARGE 18V TO
6V; DISCHARGE ON,
VDD = 3.3V,
CVPP (C2) = 1µF
FIGURE 8-6:
RIPPLE ON VPP AND
OUT00; VDD = 3.3V,
VPP = 18V,
CVPP (C2) = 10µF
FIGURE 8-7:
RIPPLE ON VPP AND
OUT00; VDD = 3.3V,
VPP = 18V,
CVPP (C2) = 1µF
2014 Microchip Technology Inc.
Preliminary
DS40001749A-page 25
MTCH650/2
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
28-Lead SOIC (7.50 mm)
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
MTCH650
I/SO
YYWWNNN
1322017
28-Lead SSOP (5.30 mm)
Example
MTCH652
I/SS
1322017
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
*
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability
code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
DS40001749A-page 26
Preliminary
2014 Microchip Technology Inc.
MTCH650/2
9.1
Package Marking Information (Continued)
28-Lead UQFN (4x4x0.5 mm)
Example
PIN 1
PIN 1
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
*
MTCH
652
I/MV
1322017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Standard PIC® device marking consists of Microchip part number, year code, week code, and traceability
code. For PIC device marking beyond this, certain price adders apply. Please check with your Microchip
Sales Office. For QTP devices, any special marking adders are included in QTP price.
2014 Microchip Technology Inc.
Preliminary
DS40001749A-page 27
MTCH650/2
9.2
Package Details
The following sections give the technical details of the packages.
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001749A-page 28
Preliminary
2014 Microchip Technology Inc.
MTCH650/2
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2014 Microchip Technology Inc.
Preliminary
DS40001749A-page 29
MTCH650/2
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001749A-page 30
Preliminary
2014 Microchip Technology Inc.
MTCH650/2
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