PIC16C55X
EPROM-Based 8-Bit CMOS Microcontrollers
Devices Included in this Data Sheet:
Pin Diagram
Referred to collectively as PIC16C55X.
PDIP, SOIC, Windowed CERDIP
High Performance RISC CPU:
• Only 35 instructions to learn
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
- DC - 20 MHz clock input
- DC - 20 ns instruction cycle
18
17
16
15
14
13
12
11
10
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4
20
19
18
17
16
15
14
13
12
11
RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
VDD
RB7
RB6
RB5
RB4
SSOP
Device
Program
Memory
Data Memory
PIC16C554
512
80
PIC16C557
2K
128
PIC16C558
2K
128
Interrupt capability
16-18 special function hardware registers
8-level deep hardware stack
Direct, Indirect and Relative Addressing modes
•1
2
3
4
5
6
7
8
9
10
RA2
RA3
RA4/T0CKI
MCLR/Vpp
VSS
VSS
RB0/INT
RB1
RB2
RB3
PIC16C554/558
PDIP, SOIC, Windowed CERDIP
VSS
RA5
RA0
RA1
RA2
RA3
RB0/INT
RB1
RB2
RB3
RB4
Peripheral Features:
• 13-22 I/O pins with individual direction control
- Pull-up resistors on PORTB
• High current sink/source for direct LED drive
• Timer0: 8-bit timer/counter with 8-bit programmable prescaler
N/C
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR/VPP
OSC1/CLKIN
OSC2/CLKOUT
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
PIC16C557
RA4/T0CKI
VDD
PIC16C557
•
•
•
•
•1
2
3
4
5
6
7
8
9
RA2
RA3
RA4/T0CKI
MCLR/Vpp
VSS
RB0/INT
RB1
RB2
RB3
PIC16C554/558
• PIC16C554
• PIC16C557
• PIC16C558
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MCLR/VPP
OSC1/CLKIN
OSC2/CLKOUT
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
RB7
RB6
RB5
SSOP
VSS
RA4/T0CKI
VDD
RA5
RA0
RA1
RA2
RA3
RB0/INT
RB1
RB2
RB3
RB4
VSS
1996-2013 Microchip Technology Inc.
Preliminary
•1
2
3
4
5
6
7
8
9
10
11
12
13
14
DS40143E-page 1
PIC16C55X
Special Microcontroller Features:
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Serial in-circuit programming (via two pins)
• Four user programmable ID locations
Note:
For additional information on enhancements, see Appendix A
CMOS Technology:
• Low power, high speed CMOS EPROM technology
• Fully static design
• Wide operating voltage range
- 2.5V to 5.5V
• Commercial, Industrial and Extended temperature
range
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15 A typical 3.0V, 32 kHz
- < 1.0 A typical standby current @ 3.0V
Device Differences
Device
Voltage Range
Oscillator
PIC16C554
2.5 - 5.5
(Note 1)
PIC16C557
2.5 - 5.5
(Note 1)
PIC16C558
2.5 - 5.5
(Note 1)
Note 1: If you change from this device to another device, please verify oscillator characteristics in your application.
DS40143E-page 2
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
Table of Contents
1.0 General Description...................................................................................................................................................................... 5
2.0 PIC16C55X Device Varieties ....................................................................................................................................................... 7
3.0 Architectural Overview ................................................................................................................................................................. 9
4.0 Memory Organization ................................................................................................................................................................. 13
5.0 I/O Ports ..................................................................................................................................................................................... 23
6.0 Special Features of the CPU...................................................................................................................................................... 31
7.0 Timer0 Module ........................................................................................................................................................................... 47
8.0 Instruction Set Summary ............................................................................................................................................................ 53
9.0 Development Support................................................................................................................................................................. 67
10.0 Electrical Specifications.............................................................................................................................................................. 73
11.0 Packaging Information................................................................................................................................................................ 87
Appendix A: Enhancements............................................................................................................................................................. 97
Appendix B:
Compatibility ............................................................................................................................................................... 97
Index .................................................................................................................................................................................................... 99
On-Line Support................................................................................................................................................................................. 101
Systems Information and Upgrade Hot Line ...................................................................................................................................... 101
Reader Response .............................................................................................................................................................................. 102
Product Identification System ............................................................................................................................................................ 103
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 3
PIC16C55X
NOTES:
DS40143E-page 4
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
1.0
GENERAL DESCRIPTION
The PIC16C55X are 18, 20 and 28-Pin EPROM-based
members of the versatile PIC16CXX family of low cost,
high
performance,
CMOS,
fully-static,
8-bit
microcontrollers.
All PIC® microcontrollers employ an advanced RISC
architecture. The PIC16C55X have enhanced core features, eight-level deep stack, and multiple internal and
external interrupt sources. The separate instruction
and data buses of the Harvard architecture allow a 14bit wide instruction word with the separate 8-bit wide
data. The two-stage instruction pipeline allows all
instructions to execute in a single-cycle, except for program branches (which require two cycles). A total of 35
instructions (reduced instruction set) are available.
Additionally, a large register set gives some of the
architectural innovations used to achieve a very high
performance.
PIC16C55X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16C554 has 80 bytes of RAM. The PIC16C557
and PIC16C558 have 128 bytes of RAM. The
PIC16C554 and PIC16C558 have 13 I/O pins and an 8bit timer/counter with an 8-bit programmable prescaler.
The PIC16C557 has 22 I/O pins and an 8-bit timer/
counter with an 8-bit programmable prescaler.
PIC16C55X devices have special features to reduce
external components, thus reducing cost, enhancing
system reliability and reducing power consumption.
There are four oscillator options, of which the single pin
RC oscillator provides a low cost solution, the LP
oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for high speed crystals.
The SLEEP (power-down) mode offers power saving.
The user can wake-up the chip from SLEEP through
several external and internal interrupts and RESET.
A UV-erasable CERDIP packaged version is ideal for
code development while the cost effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
Table 1-1 shows the features of the PIC16C55X midrange microcontroller families.
A simplified block diagram of the PIC16C55X is shown
in Figure 3-1.
The PIC16C55X series fit perfectly in applications
ranging from motor control to low power remote sensors. The EPROM technology makes customization of
application programs (detection levels, pulse generation, timers, etc.) extremely fast and convenient. The
small footprint packages make this microcontroller
series perfect for all applications with space limitations.
Low cost, low power, high performance, ease of use
and I/O flexibility make the PIC16C55X very versatile.
1.1
Family and Upward Compatibility
Users familiar with the family of microcontrollers will
realize that this is an enhanced version of the architecture. Please refer to Appendix A for a detailed list of
enhancements. Code written for can be easily ported
to PIC16C55X family of devices (Appendix B).
The PIC16C55X family fills the niche for users wanting
to migrate up from the family and not needing various
peripheral features of other members of the PIC16XX
mid-range microcontroller family.
1.2
Development Support
The PIC16C55X family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low cost development programmer and a
full-featured programmer.
A highly reliable Watchdog Timer, with its own on-chip
RC oscillator, provides protection against software
lock-up.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 5
PIC16C55X
TABLE 1-1:
Clock
Memory
Peripherals
PIC16C55X FAMILY OF DEVICES
PIC16C554
PIC16C557
PIC16C558
Maximum Frequency of Operation
(MHz)
20
20
20
EPROM Program Memory
(x14 words)
512
2K
2K
Data Memory (bytes)
80
128
128
Timer Module(s)
TMR0
TMR0
TMR0
Interrupt Sources
3
3
3
I/O Pins
Features
Voltage Range (Volts)
Brown-out Reset
Packages
13
22
13
2.5-5.5
2.5-5.5
2.5-5.5
—
—
—
18-pin DIP, SOIC;
20-pin SSOP
28-pin DIP, SOIC;
28-pin SSOP
18-pin DIP, SOIC,
SSOP
All PIC® Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high
I/O current capability. All PIC16C55X Family devices use serial programming with clock pin RB6 and data pin RB7.
DS40143E-page 6
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
2.0
PIC16C55X
DEVICE VARIETIES
2.3
A variety of frequency ranges and packaging options
are available. Depending on application and production
requirements, the proper device option can be selected
using the information in the PIC16C55X Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of
the data sheet to specify the correct part number.
2.1
UV Erasable Devices
The UV erasable version, offered in CERDIP package,
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
PROMATE
Microchip's
PICSTART and
programmers both support programming of the
PIC16C55X.
2.2
One-Time Programmable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
1996-2013 Microchip Technology Inc.
Quick-Turnaround Production
(QTP) Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available for users who choose not to program a
medium-to-high quantity of units and whose code patterns have stabilized. The devices are identical to the
OTP devices, but with all EPROM locations and configuration options already programmed by the factory.
Certain code and prototype verification procedures
apply before production shipments are available.
Please contact your Microchip Technology sales office
for more details.
2.4
Serialized Quick-Turnaround
Production (SQTPSM) Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.
Preliminary
DS40143E-page 7
PIC16C55X
NOTES:
DS40143E-page 8
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
3.0
ARCHITECTURAL OVERVIEW
The high performance of the PIC16C55X family can be
attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16C55X uses a Harvard architecture in
which program and data are accessed from separate
memories using separate busses. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently from 8-bit
wide data words. Instruction opcodes are 14-bit wide
making it possible to have all single word instructions.
A 14-bit wide program memory access bus fetches a
14-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (35) execute in a singlecycle (200 ns @ 20 MHz) except for program branches.
The table below lists the memory (EPROM and RAM).
Device
Program
Memory
(EPROM)
Data
Memor
(RAM)
PIC16C554
512
80
PIC16C557
2K
128
PIC16C558
2K
128
The ALU is 8-bits wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Borrow and Digit Borrow out bit,
respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.
The PIC16C554 addresses 512 x 14 on-chip program
memory. The PIC16C557 and PIC16C558 addresses
2 K x 14 program memory. All program memory is internal.
The PIC16C55X can directly or indirectly address its
register files or data memory. All special function
registers, including the program counter, are mapped
into the data memory. The PIC16C55X has an orthogonal (symmetrical) instruction set that makes it possible
to carry out any operation on any register using any
Addressing mode. This symmetrical nature and lack of
‘special optimal situations’ make programming with the
PIC16C55X simple yet efficient. In addition, the
learning curve is reduced significantly.
The PIC16C55X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 9
PIC16C55X
FIGURE 3-1:
BLOCK DIAGRAM
Device
Program
Memory
PIC16C554
512 x 14
80 x 8
PIC16C557
2 K x 14
128 x 8
PIC16C558
2 K x 14
128 x 8
EPROM
Data
Memory
13
Program
Memory
512 x 14
to
2K x 14
Program
Bus
PORTA
RA0
RA1
RA2
RA3
RAM
File
Registers
80 x 8 to
128 x 8
8-Level Stack
(13-bit)
14
8
Data Bus
Program Counter
RAM Addr(1)
RA4/T0CKI
PORTB
8
Addr MUX
Instruction reg
7
Direct Addr
8
RB0/INT
Indirect
Addr
RB7:RB1
FSR
STATUS reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Timing
Generation
PORTC(2)
MUX
RC7:RC0
Oscillator
Start-up Timer
Power-on
Reset
ALU
8
Watchdog
Timer
W reg
OSC1/CLKIN
OSC2/CLKOUT
Timer0
VPP
Note
1:
2:
VDD, VSS
Higher order bits are from STATUS Register.
PIC16C557 only.
DS40143E-page 10
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
TABLE 3-1:
PIC16C55X PINOUT DESCRIPTION
Pin Number
Name
PDIP
SOIC
SSOP
Pin
Type
Buffer
Type
Description
OSC1/CLKIN
16
16
18
I
OSC2/CLKOUT
15
15
17
O
ST/CMOS Oscillator crystal input/external clock source output.
—
Oscillator crystal output. Connects to crystal or resonator
in Crystal Oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR/VPP
4
4
4
I/P
ST
Master clear (Reset) input/programming voltage input.
This pin is an active low RESET to the device.
RA0
17
17
19
I/O
ST
Bi-directional I/O port
RA1
18
18
20
I/O
ST
Bi-directional I/O port
RA2
1
1
1
I/O
ST
Bi-directional I/O port
RA3
2
2
2
I/O
ST
Bi-directional I/O port
RA4/T0CKI
3
3
3
I/O
ST
Bi-directional I/O port or external clock input for TMR0.
Output is open drain type.
RB0/INT
6
6
7
I/O
TTL/ST(1)
RB1
7
7
8
I/O
TTL
Bi-directional I/O port can be software programmed for
internal weak pull-up.
RB2
8
8
9
I/O
TTL
Bi-directional I/O port can be software programmed for
internal weak pull-up.
RB3
9
9
10
I/O
TTL
Bi-directional I/O port can be software programmed for
internal weak pull-up.
RB4
10
10
11
I/O
TTL
Bi-directional I/O port can be software programmed for
internal weak pull-up. Interrupt-on-change pin.
RB5
11
11
12
I/O
TTL
Bi-directional I/O port can be software programmed for
internal weak pull-up. Interrupt-on-change pin.
RB6
12
12
13
I/O
TTL/ST(2)
Bi-directional I/O port can be software programmed for
internal weak pull-up. Interrupt-on-change pin. Serial programming clock.
RB7
13
13
14
I/O
TTL/ST(2)
Bi-directional I/O port can be software programmed for
internal weak pull-up. Interrupt-on-change pin. Serial programming data.
RC0(3)
18
18
18
I/O
TTL
Bi-directional I/O port input buffer.
RC1(3)
19
19
19
I/O
TTL
Bi-directional I/O port input buffer.
(3)
20
20
20
I/O
TTL
Bi-directional I/O port input buffer.
(3)
21
21
21
I/O
TTL
Bi-directional I/O port input buffer.
(3)
RC4
22
22
22
I/O
TTL
Bi-directional I/O port input buffer.
RC5(3)
23
23
23
I/O
TTL
Bi-directional I/O port input buffer.
(3)
24
24
24
I/O
TTL
Bi-directional I/O port input buffer.
(3)
RC7
25
25
25
I/O
TTL
Bi-directional I/O port input buffer.
VSS
5
5
5,6
P
—
Ground reference for logic and I/O pins.
VDD
14
14
15,16
P
—
Positive supply for logic and I/O pins.
RC2
RC3
RC6
Bi-directional I/O port can be software programmed for
internal weak pull-up. RB0/INT can also be selected as an
external interrupt pin.
Legend:
O = Output
I/O = Input/output
P = Power
— = Not used
I = Input
ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: PIC16C557 only.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 11
PIC16C55X
3.1
Clocking Scheme/Instruction
Cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g., GOTO),
then two cycles are required to complete the instruction
(Example 3-1).
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow are shown in Figure 3-2.
3.2
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Instruction Flow/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
FIGURE 3-2:
CLOCK/INSTRUCTION CYCLE
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
Q1
Q2
Internal
phase
clocks
Q3
Q4
PC
PC
OSC2/CLKOUT
(RC mode)
PC+1
Fetch INST (PC)
Execute INST (PC-1)
EXAMPLE 3-1:
PC+2
Fetch INST (PC+1)
Execute INST (PC)
Fetch INST (PC+2)
Execute INST (PC+1)
INSTRUCTION PIPELINE FLOW
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
SUB_1
4. BSF
PORTA, BIT3
Fetch 1
Execute 1
Fetch 2
Execute 2
Fetch 3
Execute 3
Fetch 4
Flush
Fetch SUB_1 Execute SUB_1
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction
is “flushed” from the pipeline while the new instruction is being fetched and then executed.
DS40143E-page 12
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
4.0
MEMORY ORGANIZATION
4.1
Program Memory Organization
FIGURE 4-2:
The PIC16C55X has a 13-bit program counter capable
of addressing an 8 K x 14 program memory space.
Only the first 512 x 14 (0000h - 01FFh) for the
PIC16C554 and 2K x 14 (0000h - 07FFh) for the
PIC16C557 and PIC16C558 are physically implemented. Accessing a location above these boundaries
will cause a wrap-around within the first 512 x 14
spaces in the PIC16C554, or 2K x 14 space of the
PIC16C558 and PIC16C557. The RESET vector is at
0000h and the interrupt vector is at 0004h (Figure 4-1,
Figure 4-2).
FIGURE 4-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C557 AND
PIC16C558
PC
CALL, RETURN
RETFIE, RETLW
13
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
000h
Interrupt Vector
0004
0005
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16C554
PC
CALL, RETURN
RETFIE, RETLW
13
On-chip Program
Memory
Stack Level 1
07FFh
Stack Level 2
0800h
Stack Level 8
1FFFh
RESET Vector
Interrupt Vector
000h
0004
0005
On-chip Program
Memory
01FFh
0200h
4.2
Data Memory Organization
The data memory (Figure 4-3 through Figure 4-5) is
partitioned into two banks which contain the General
Purpose Registers (GPR) and the Special Function
Registers (SFR). Bank 0 is selected when the RP0 bit
(STATUS ) is cleared. Bank 1 is selected when the
RP0 bit is set. The Special Function Registers are
located in the first 32 locations of each Bank. Register
locations 20-6Fh (Bank 0) on the PIC16C554 and 207Fh (Bank 0) and A0-BFh (Bank 1) on the PIC16C558
and PIC16C557 are General Purpose Registers implemented as static RAM. Some special purpose registers
are mapped in Bank 1.
4.2.1
1FFFh
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 80 x 8 in the
PIC16C554 and 128 x 8 in the PIC16C557 and
PIC16C558. Each can be accessed either directly or
indirectly through the File Select Register, FSR
(Section 4.4).
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 13
PIC16C55X
FIGURE 4-3:
DATA MEMORY MAP FOR
THE PIC16C554
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
6Fh
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PCLATH
INTCON
PCON
FIGURE 4-4:
File
Address
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
A0h
General
Purpose
Register
DATA MEMORY MAP FOR
THE PIC16C557
File
Address
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PCLATH
INTCON
PCON
General
Purpose
Register
General
Purpose
Register
70h
7Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
FFh
Bank 0
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
DS40143E-page 14
7Fh
Bank 1
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
FIGURE 4-5:
DATA MEMORY MAP FOR
THE PIC16C558
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
File
Address
INDF(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
INDF(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PCLATH
INTCON
PCON
General
Purpose
Register
General
Purpose
Register
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
The Special Function Registers can be classified into
two sets (core and peripheral). The special function
registers associated with the “core” functions are
described in this section. Those related to the operation
of the peripheral features are described in the section
of that peripheral feature.
A0h
BFh
C0h
7Fh
FFh
Bank 0
Bank 1
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 15
PIC16C55X
TABLE 4-1:
Address
SPECIAL REGISTERS FOR THE PIC16C55X
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Detail on
POR Reset
Page:
Bank 0
00h
INDF
Addressing this location uses contents of FSR to address data memory (not a
physical register)
xxxx xxxx
21
01h
TMR0
Timer0 Module’s Register
xxxx xxxx
47
02h
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
21
03h
STATUS
04h
FSR
05h
PORTA
IRP(2)
RP1(2)
RP0
TO
PD
Z
DC
C
Indirect data memory address pointer
—
—
—
RA4
RA3
RA2
RA1
RA0
0001 1xxx
17
xxxx xxxx
21
---x xxxx
23
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
25
07h
PORTC(4)
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
27
—
08h
—
Unimplemented
—
09h
—
Unimplemented
—
0Ah
PCLATH
—
—
—
0Bh
INTCON
GIE
(3)
T0IE
0Ch
—
0Dh-1Eh
—
1Fh
—
Write buffer for upper 5 bits of program counter ---0 0000
INTE
RBIE
T0IF
INTF
RBIF
—
21
0000 000x
19
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
xxxx xxxx
21
Bank 1
80h
INDF
Addressing this location uses contents of FSR to address data memory (not a
physical register)
81h
OPTION
82h
PCL
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
Program Counter's (PC) Least Significant Byte
83h
STATUS
84h
FSR
85h
TRISA
—
—
RP0
TO
PD
Z
DC
C
—
—
18
21
0001 1xxx
17
xxxx xxxx
21
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111
23
Indirect data memory address pointer
—
1111 1111
0000 0000
86h
TRISB
TRISB7
TRISB6
TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111
25
87h
TRISC(4)
TRISC7 TRISC6
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111
27
88h
—
Unimplemented
—
89h
—
Unimplemented
—
8Ah
PCLATH
—
—
—
8Bh
INTCON
GIE
(3)
T0IE
8Ch
—
8Dh
—
8Eh
PCON
Write buffer for upper 5 bits of program counter ---0 0000
19
Unimplemented
—
—
Unimplemented
—
—
—
—
—
RBIE
—
T0IF
—
INTF
POR
RBIF
—
21
0000 000x
—
INTE
—
---- --0-
20
8Fh-9Eh
—
Unimplemented
—
—
—
9Fh
—
Unimplemented
—
—
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
2: IRP & RP1 bits are reserved, always maintain these bits clear.
3: Bit 6 of INTCON register is reserved for future use. Always maintain this bit as clear.
4: PIC16C557 only.
DS40143E-page 16
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
4.2.2.1
STATUS Register
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions be used to alter the
STATUS register because these instructions do not
affect any status bits. For other instructions, not affecting any status bits, see the “Instruction Set Summary”.
The STATUS register, shown in Figure 4-2, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as the destination may be different
than intended.
Note 1: The IRP and RP1 bits (STATUS)
are not used by the PIC16C55X and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits is
NOT recommended, since this may affect
upward compatibility with future products.
2: The C and DC bits operate as a Borrow
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the STATUS register
as 000uu1uu (where u = unchanged).
REGISTER 4-1:
STATUS REGISTER (ADDRESS 03h OR 83h)
Reserved
Reserved
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit7
bit0
bit 7
IRP: Register Bank Select bit (used for Indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
The IRP bit is reserved on the PIC16C55X, always maintain this bit clear
bit 6-5
RP1:RP0: Register Bank Select bits (used for Direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved on the PIC16C55X, always maintain this bit clear.
bit 4
TO: Timeout bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT timeout occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions) (for borrow the polarity is
reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second
operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the
source register.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
1996-2013 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS40143E-page 17
PIC16C55X
4.2.2.2
OPTION Register
Note 1: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1).
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0 and the weak pull-ups on PORTB.
REGISTER 4-2:
OPTION REGISTER (ADDRESS 81H)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit7
bit0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
TMR0 Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
WDT Rate
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
DS40143E-page 18
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
1996-2013 Microchip Technology Inc.
PIC16C55X
4.2.2.3
INTCON Register
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all interrupt sources.
REGISTER 4-3:
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON).
INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0
Reserved
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
—
T0IE
INTE
RBIE
T0IF
INTF
RBIF
bit7
bit0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6
Reserved: For future use. Always maintain this bit clear.
bit 5
T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
1996-2013 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS40143E-page 19
PIC16C55X
4.2.2.4
PCON Register
The PCON register contains a flag bit to differentiate
between a Power-on Reset, an external MCLR Reset
or WDT Reset. See Section 6.3 and Section 6.4 for
detailed RESET operation.
REGISTER 4-4:
PCON REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
U-0
—
—
—
—
—
—
POR
—
bit7
bit0
bit 7-2
Unimplemented: Read as '0'
bit 1
POR: Power-on Reset status bit
1 = No Power-on Reset occurred
0 = Power-on Reset occurred
bit 0
Unimplemented: Read as '0'
Legend:
DS40143E-page 20
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
Preliminary
x = Bit is unknown
1996-2013 Microchip Technology Inc.
PIC16C55X
4.3
PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high bits (PC) are not
directly readable or writable and come from PCLATH.
On any RESET, the PC is cleared. Figure 4-6 shows
the two situations for the loading of the PC. The upper
example in the figure shows how the PC is loaded on a
write to PCL (PCLATH PCH). The lower example in Figure 4-6 shows how the PC is loaded during a
CALL or GOTO instruction (PCLATH PCH).
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or vectoring to an interrupt
address.
LOADING OF PC IN
DIFFERENT SITUATIONS
FIGURE 4-6:
4.4
PCH
PCL
12
8
7
0
PC
8
PCLATH
5
Instruction with
PCL as
Destination
ALU result
PCLATH
PCH
12
11 10
PCL
8
0
7
GOTO, CALL
PC
2
PCLATH
11
Opcode
The INDF register is not a physical register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a nooperation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS), as
shown in Figure 4-7. However, IRP is not used in the
PIC16C55X.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 4-1.
PCLATH
4.3.1
Indirect Addressing, INDF and
FSR Registers
EXAMPLE 4-1:
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note “Implementing a Table Read" (AN556).
NEXT
movlw
movwf
clrf
incf
btfss
goto
INDIRECT ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;no clear next
;yes continue
CONTINUE:
4.3.2
STACK
The PIC16C55X family has an 8-level deep x 13-bit
wide hardware stack (Figure 4-1 and Figure 4-2). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a
PUSH or POP operation.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 21
PIC16C55X
FIGURE 4-7:
DIRECT/INDIRECT ADDRESSING PIC16C55X
Direct Addressing
(1)
from opcode
RP1 RP0
6
bank select
location select
Indirect Addressing
IRP(1)
0
7
bank select
00
01
10
FSR register
0
location select
11
00h
00h
not used
Data
Memory
7Fh
7Fh
Bank 0
Bank 1
Bank 2
Bank 3
For memory map detail see Figure 4-3 and Figure 4-5.
Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
DS40143E-page 22
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
5.0
I/O PORTS
FIGURE 5-2:
The PIC16C554 and PIC16C558 have two ports,
PORTA and PORTB. The PIC16C557 has three ports,
PORTA, PORTB and PORTC.
5.1
PORTA and TRISA Registers
Data
bus
WR
PORTA
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open-drain output. Port RA4 is multiplexed
with the T0CKI clock input. All other RA port pins have
Schmitt Trigger input levels and full CMOS output drivers. All pins have data direction bits (TRIS registers)
which can configure these pins as input or output.
A '1' in the TRISA register puts the corresponding output driver in a Hi-impedance mode. A '0' in the TRISA
register puts the contents of the output latch on the
selected pin(s).
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch.
BLOCK DIAGRAM OF RA4
PIN
D
Q
CK
Q
N
I/O pin(1)
Data Latch
WR
TRISA
D
Q
CK
Q
VSS
Schmitt
Trigger
input
buffer
TRISA Latch
VSS
RD TRISA
Q
D
EN
EN
RD PORTA
TMR0 clock input
Note 1: On RESET, the TRISA register is set to all
inputs.
FIGURE 5-1:
BLOCK DIAGRAM OF
PORT PINS RA
Data
Bus
WR
PORTA
D
Q
CK
Q
VDD
VDD
P
Data Latch
WR
TRISA
D
Q
CK
Q
N
VSS
Schmitt
Trigger
input
buffer
TRIS Latch
I/O pin
VSS
RD TRISA
Q
D
EN
RD PORTA
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 23
PIC16C55X
TABLE 5-1:
PORTA FUNCTIONS
Name
Bit #
Buffer
Type
RA0
RA1
RA2
RA3
RA4/T0CKI
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
ST
ST
ST
ST
ST
Function
Bi-directional I/O port.
Bi-directional I/O port.
Bi-directional I/O port.
Bi-directional I/O port.
Bi-directional I/O port or external clock input for TMR0. Output is open
drain type.
Legend: ST = Schmitt Trigger input
TABLE 5-2:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
RESETS
05h
PORTA
—
—
—
RA4
RA3
RA2
RA1
RA0
---x xxxx
---u uuuu
85h
TRISA
—
—
—
---1 1111
---1 1111
Address
TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
Legend: — = Unimplemented locations, read as ‘0’, x = unknown, u = unchanged
Note 1: Shaded bits are not used by PORTA.
DS40143E-page 24
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
5.2
PORTB and TRISB Registers
latched in INTCON). This interrupt can wake the
device from SLEEP. The user, in the interrupt service
routine, can clear the interrupt in the following manner:
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a Hi-impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
• Any read or write of PORTB (this will end the mismatch condition)
• Clear flag bit RBIF
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
Reading PORTB register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then
this value is modified and written to the port data latch.
The interrupt on mismatch feature, together with
software configurable pull-ups on these four pins,
allows easy interface to a key pad and make it possible
for wake-up on key-depression. (See AN552 in the
Microchip Embedded Control Handbook.)
Each of the PORTB pins has a weak internal pull-up
(200 A typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Note 1: If a change on the I/O pin should occur
when the read operation is being executed (start of the Q2 cycle), then the
RBIF interrupt flag may not get set.
Four of PORTB’s pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RBIF interrupt (flag
FIGURE 5-3:
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
BLOCK DIAGRAM OF RB7:RB4 PINS
RBPU(1)
VDD
VDD
Data Latch
Data Bus
D
WR PORTB
Q
weak
P pull-up
VDD
P
CK
WR TRISB
D
Q
CK
Q
RD TRISB
I/O
pin
N
TRIS Latch
VSS
VSS
TTL ST
Input Buffer
Buffer
Latch
Q
D
EN
RD PORTB
Set RBIF
From other
RB7:RB4 pins
Q
D
EN
RB7:RB6 in Serial Programming mode
Note
1:
RD PORTB
TRISB = 1 enables weak pull-up if RBPU = ‘0’ (OPTION).
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 25
PIC16C55X
FIGURE 5-4:
BLOCK DIAGRAM OF RB3:RB0 PINS
RBPU(1)
VDD
VDD
Data Latch
Data Bus
D
WR PORTB
Q
weak
P pull-up
VDD
P
CK
D
WR TRISB
I/O
pin
N
TRIS Latch
Q
CK
VSS
VSS
Q
TTL ST
Input Buffer
Buffer
RD TRISB
Latch
Q
D
EN
RD PORTB
RB0/INT
ST
Buffer
RD PORTB
Note
1:
TRISB = 1 enables weak pull-up if RBPU = ‘0’ (OPTION).
TABLE 5-3:
Name
PORTB FUNCTIONS
Bit #
Buffer Type
RB0/INT
Bit 0
TTL/ST(1)
Bi-directional I/O port. Internal software programmable weak pull-up.
Function
RB1
Bit 1
TTL
Bi-directional I/O port. Internal software programmable weak pull-up.
RB2
Bit 2
TTL
Bi-directional I/O port. Internal software programmable weak pull-up.
RB3
Bit 3
TTL
Bi-directional I/O port. Internal software programmable weak pull-up.
RB4
Bit 4
TTL
Bi-directional I/O port (with interrupt-on-change). Internal software programmable
weak pull-up.
RB5
Bit 5
TTL
Bi-directional I/O port (with interrupt-on-change). Internal software programmable
weak pull-up.
RB6
Bit 6
TTL/ST(2)
Bi-directional I/O port (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming clock pin.
RB7
Bit 7
TTL/ST(2)
Bi-directional I/O port (with interrupt-on-change). Internal software programmable
weak pull-up. Serial programming data pin.
Legend: ST = Schmitt Trigger, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB AND TRISB
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
RESETS
06h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
86h
TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
1111 1111
1111 1111
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
0BH, 8BH
INTCON
GIE
Reserved
T0IE
INTE
BRIE
T0IF
INTF
RBIF
0000 000x
0000 000x
Address
Legend:
x = unknown, u = unchanged
Note 1: Shaded bits are not used by PORTB.
DS40143E-page 26
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
5.3
PORTC and TRISC Registers(1)
FIGURE 5-5:
PORTC is a 8-bit wide latch. All pins have data direction bits (TRIS registers) which can configure these
pins as input or output.
BLOCK DIAGRAM OF
PORT PINS RC
Data
Bus
D
A '1' in the TRISC register puts the corresponding output driver in a Hi-impedance mode. A '0' in the TRISC
register puts the contents of the output latch on the
selected pin(s).
WR
PORTC
Q
VDD
CK
Q
VDD
P
Data Latch
Reading the PORTC register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations. So a
write to a port implies that the port pins are first read,
then this value is modified and written to the port data
latch
WR
TRISC
D
Q
N
CK
Q
VSS
TRIS Latch
I/O pin
VSS
TTL
Input
Buffer
RD TRISC
Q
D
EN
RD PORTC
TABLE 5-5:
Name
PORTC FUNCTIONS
Bit #
Buffer Type
RC0
Bit 0
TTL
Bi-directional I/O port.
RC1
Bit 1
TTL
Bi-directional I/O port.
RC2
Bit 2
TTL
Bi-directional I/O port.
RC3
Bit 3
TTL
Bi-directional I/O port.
RC4
Bit 4
TTL
Bi-directional I/O port.
RC5
Bit 5
TTL
Bi-directional I/O port.
RC6
Bit 6
TTL
Bi-directional I/O port.
RC7
Bit 7
TTL
Bi-directional I/O port.
Legend:
ST = Schmitt Trigger, TTL = TTL input
TABLE 5-6:
Address
Function
Name
SUMMARY OF REGISTERS ASSOCIATED WITH PORTC AND TRISC
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
Value on
All Other
RESETS
07h
PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0
xxxx xxxx
uuuu uuuu
87h
TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
TRISC0
1111 1111
1111 1111
Legend:
x = unknown, u = unchanged
Note 1: PIC16C557 ONLY.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 27
PIC16C55X
5.4
5.4.1
I/O Programming Considerations
BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, execute the bit operation and write the result
back to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bi-directional I/O pin
(e.g., bit 0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the Input mode, no problem occurs.
However, if bit 0 is switched into Output mode later on,
the content of the data latch may now be unknown.
DS40143E-page 28
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read-modify-write instructions
(ex. BCF, BSF, etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
Example 5-1 shows the effect of two sequential readmodify-write instructions (ex., BCF,BSF, etc.) on an
I/O port.
A pin actively outputting a low or high should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
EXAMPLE 5-1:
READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
5.4.2
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle, as shown
in Figure 5-6. Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load
dependent) before the next instruction which causes
that file to be read into the CPU is executed. Otherwise,
the previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with an NOP or another
instruction not accessing this I/O port.
; Initial PORT settings: PORTB Inputs
;
;
PORTB Outputs
; PORTB have external pull-up and are
; not connected to other circuitry
;
;
PORT latch PORT pins
;
---------- --------;
BCF
BCF
BSF
BCF
BCF
PORTB, 7
PORTB, 6
STATUS, RP0
TRISB, 7
TRISB, 6
FIGURE 5-6:
;
;
;
;
;
11pp pppp
11pp pppp
10pp pppp
10pp pppp
11pp pppp
10pp pppp
SUCCESSIVE I/O OPERATION
Q1
PC
Instruction
fetched
01pp pppp
10pp pppp
SUCCESSIVE OPERATIONS ON I/O
PORTS
Q2
Q3
Q4
PC
MOVWF PORTB
Write to
PORTB
Q1
Q2
Q3
Q4
Q1
PC + 1
MOVF PORTB, W
Read PORTB
Q2
Q3
Q4
Q1
Q2
Q3
PC + 2
PC + 3
NOP
NOP
Q4
RB
Port pin
sampled here
T PD
Execute
MOVWF
PORTB
Execute
MOVF
PORTB, W
Execute
NOP
Note 1: This example shows write to PORTB followed by a read from PORTB.
2: Data setup time = (0.25 TCY - TPD) where TCY = instruction cycle and TPD = propagation delay of Q1 cycle to
output valid. Therefore, at higher clock frequencies, a write followed by a read may be problematic.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 29
PIC16C55X
NOTES:
DS40143E-page 30
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
6.0
SPECIAL FEATURES OF THE
CPU
What sets a microcontroller apart from other
processors are special circuits to deal with the needs of
real-time applications. The PIC16C55X family has a
host of such features intended to maximize system
reliability, minimize cost through elimination of external
components, provide power saving operating modes
and offer code protection.
These are:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
6.1
Configuration Bits
The configuration bits can be programmed (read as '0')
or left unprogrammed (read as '1') to select various
device configurations. These bits are mapped in
program memory location 2007h.
The user will note that address 2007h is beyond
the user program memory space. In fact, it belongs
to the special test/configuration memory space
(2000h – 3FFFh), which can be accessed only during
programming.
OSC selection
RESET
Power-on Reset (POR)
Power-up Timer (PWRT)
Oscillator Start-Up Timer (OST)
Interrupts
Watchdog Timer (WDT)
SLEEP
Code protection
ID Locations
In-circuit serial programming™
The PIC16C55X has a Watchdog Timer which is
controlled by configuration bits. It runs off its own RC
oscillator for added reliability. There are two timers that
offer necessary delays on power-up. One is the
Oscillator Start-up Timer (OST), which is intended to
keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which
provides a fixed delay of 72 ms (nominal) on power-up
only, designed to keep the part in RESET while the
power supply stabilizes. With these two functions onchip, most applications need no external RESET circuitry.
The SLEEP mode is designed to offer a very low
current Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost while the LP crystal option saves power. A set of
configuration bits are used to select various options.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 31
PIC16C55X
REGISTER 6-1:
CP1
CONFIGURATION WORD
CP0
CP1
CP0
CP1
CP0
—
Reserved
CP1
CP0
PWRTE
WDTE
F0SC1
bit 13
bit 13-8
bit 5-4
bit 7
F0SC0
bit 0
CP: Code protection bits(1)
11 = Program Memory code protection off
10 = 0400h - 07FFh code protected
01 = 0200h - 07FFh code protected
11 = 0000h - 07FFh code protected
Unimplemented: Read as '1'
bit 6
Reserved: Do not use
bit 3
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 1-0
FOSC1:FOSC0: Oscillator Selection bits
11 = RC oscillator
10 = HS oscillator
01 = XT oscillator
00 = LP oscillator
Note
1:
All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR reset
’1’ = Bit is set
’0’ = Bit is cleared
DS40143E-page 32
Preliminary
x = Bit is unknown
1996-2013 Microchip Technology Inc.
PIC16C55X
6.2
TABLE 6-1:
Oscillator Configurations
6.2.1
OSCILLATOR TYPES
The PIC16C55X can be operated in four different
oscillator options. The user can program two
configuration bits (FOSC1 and FOSC0) to select one of
these four modes:
•
•
•
•
LP
XT
HS
RC
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
Resistor/Capacitor
6.2.2
CRYSTAL OSCILLATOR / CERAMIC
RESONATORS
In XT, LP or HS modes a crystal or ceramic resonator
is connected to the OSC1 and OSC2 pins to establish
oscillation (Figure 6-1). The PIC16C55X oscillator
design requires the use of a parallel cut crystal. Use of
a series cut crystal may give a frequency out of the
crystal manufacturers specifications. When in XT, LP or
HS modes, the device can have an external clock
source to drive the OSC1 pin (Figure 6-2).
CRYSTAL OPERATION
(OR CERAMIC
RESONATOR) (HS, XT OR
LP OSC
CONFIGURATION)
FIGURE 6-1:
Ranges Characterized:
Mode
Freq
OSC1(C1)
OSC2(C2)
XT
455 kHz
2.0 MHz
4.0 MHz
22 - 100 pF
15 - 68 pF
15 - 68 pF
22 - 100 pF
15 - 68 pF
15 - 68 pF
HS
8.0 MHz
16.0 MHz
10 - 68 pF
10 - 22 pF
10 - 68 pF
10 - 22 pF
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Since each resonator has
its own characteristics, the user should
consult with the resonator manufacturer for
appropriate values of external components.
TABLE 6-2:
To internal logic
XTAL
Freq
OSC1(C1)
OSC2(C2)
LP
32 kHz
200 kHz
68 - 100 pF
15 - 30 pF
68 - 100 pF
15 - 30 pF
XT
100 kHz
2 MHz
4 MHz
68 - 150 pF
15 - 30 pF
15 - 30 pF
150 - 200 pF
15 - 30 pF
15 - 30 pF
HS
8 MHz
10 MHz
20 MHz
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
15 - 30 pF
SLEEP
RF
OSC2
C2
Note
1:
2:
RS
Note 1
A series resistor may be required for AT strip cut
crystals.
See Table 6-1 and Table 6-2 for recommended values of C1 and C2.
FIGURE 6-2:
Clock from
ext. system
PIC16C55X
EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR
LP OSC
CONFIGURATION)
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
(PRELIMINARY)
Mode
OSC1
C1
CAPACITOR SELECTION FOR
CERAMIC RESONATORS
(PRELIMINARY)
Note 1: Higher capacitance increases the stability
of the oscillator but also increases the
start-up time. These values are for design
guidance only. Rs may be required in HS
mode as well as XT mode to avoid overdriving crystals with low-drive level specification. Since each crystal has its own
characteristics, the user should consult
with the crystal manufacturer for appropriate values of external components.
OSC1
PIC16C55X
Open
OSC2
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 33
PIC16C55X
6.2.3
EXTERNAL CRYSTAL OSCILLATOR
CIRCUIT
Either a pre-packaged oscillator can be used or a simple oscillator circuit with TTL gates can be built.
Prepackaged oscillators provide a wide operating
range and better stability. A well-designed crystal
oscillator will provide good performance with TTL
gates. Two types of crystal oscillator circuits can be
used: one with series resonance, or one with parallel
resonance.
Figure 6-3 shows implementation of a parallel resonant
oscillator circuit. The circuit is designed to use the
fundamental frequency of the crystal. The 74AS04
inverter performs the 180 phase shift that a parallel
oscillator requires. The 4.7 k resistor provides the
negative feedback for stability. The 10 k
potentiometers bias the 74AS04 in the linear region.
This could be used for external oscillator designs.
FIGURE 6-3:
EXTERNAL PARALLEL
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
+5V
To other
Devices
10k
PIC16C55X
74AS04
4.7k
RC OSCILLATOR
For timing insensitive applications the “RC” device
option offers additional cost savings. The RC oscillator
frequency is a function of the supply voltage, the
resistor (REXT) and capacitor (CEXT) values, and the
operating temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the
difference in lead frame capacitance between package
types will also affect the oscillation frequency,
especially for low CEXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 6-5 shows how the
R/C combination is connected to the PIC16C55X. For
REXT values below 2.2 k, the oscillator operation may
become unstable, or stop completely. For very high
REXT values (e.g., 1 M), the oscillator becomes
sensitive to noise, humidity and leakage. Thus, we
recommend to keep REXT between 3 k and 100 k.
Although the oscillator will operate with no external
capacitor (CEXT = 0 pF), we recommend using values
above 20 pF for noise and stability reasons. With no or
small external capacitance, the oscillation frequency
can vary dramatically due to changes in external
capacitances, such as PCB trace capacitance or
package lead frame capacitance.
The oscillator frequency, divided by 4, is available on
the OSC2/CLKOUT pin, and can be used for test
purposes or to synchronize other logic (Figure 3-2 for
waveform).
CLKIN
74AS04
6.2.4
10k
XTAL
FIGURE 6-5:
RC OSCILLATOR MODE
10k
VDD
20 pF
20 pF
PIC16C55X
REXT
Figure 6-4 shows a series resonant oscillator circuit.
This circuit is also designed to use the fundamental
frequency of the crystal. The inverter performs a 180
phase shift in a series resonant oscillator circuit. The
330 resistors provide the negative feedback to bias
the inverters in their linear region.
FIGURE 6-4:
OSC1
Internal Clock
CEXT
VSS
Fosc/4
OSC2/CLKOUT
EXTERNAL SERIES
RESONANT CRYSTAL
OSCILLATOR CIRCUIT
330
330
74AS04
74AS04
To other
Devices
PIC16C55X
74AS04
CLKIN
0.1 F
XTAL
DS40143E-page 34
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
6.3
RESET
The PIC16C55X differentiates between various kinds
of RESET:
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset (normal operation)
WDT wake-up (SLEEP)
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 6-6.
The MCLR Reset path has a noise filter to detect and
ignore small pulses. See Table 10-3 for pulse width
specification.
Some registers are not affected in any RESET condition; their status is unknown on POR and unchanged in
any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset, on MCLR or WDT
Reset and on MCLR Reset during SLEEP. They are not
affected by a WDT wake-up, since this is viewed as the
resumption of normal operation. TO and PD bits are set
or cleared differently in different RESET situations as
indicated in Table 6-4. These bits are used in software
to determine the nature of the RESET. See Table 6-6
for a full description of RESET states of all registers.
FIGURE 6-6:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
Reset
MCLR/
VPP Pin
WDT
Module
SLEEP
WDT
Timeout
Reset
VDD rise
detect
Power-on Reset
VDD
S
OST/PWRT
OST
Chip_Reset
10-bit Ripple-counter
OSC1/
CLKIN
Pin
On-chip(1)
RC OSC
R
Q
PWRT
10-bit Ripple-counter
Enable PWRT
See Table 6-3 for timeout situations.
Enable OST
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 35
PIC16C55X
6.4
6.4.1
Power-on Reset (POR), Power-up
Timer (PWRT), Oscillator Start-up
Timer (OST)
POWER-ON RESET (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.6V – 1.8V). To
take advantage of the POR, just tie the MCLR pin
through a resistor to VDD. This will eliminate external
RC components usually needed to create Power-on
Reset. A maximum rise time for VDD is required. See
Electrical Specifications for details.
The POR circuit does not produce internal RESET
when VDD declines.
When the device starts normal operation (exits the
RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating conditions are met.
For additional information, refer to Application Note
AN607 “Power-up Trouble Shooting”.
6.4.2
POWER-UP TIMER (PWRT)
The Power-up Timer provides a fixed 72 ms (nominal)
timeout on power-up only, from POR. The Power-up
Timer operates on an internal RC oscillator. The chip is
kept in RESET as long as PWRT is active. The PWRT
delay allows the VDD to rise to an acceptable level. A
configuration bit, PWRTE can disable (if set) or enable
(if cleared or programmed) the Power-up Timer. The
Power-Up Time delay will vary from chip to chip and
due to VDD, temperature and process variation. See
DC parameters for details.
DS40143E-page 36
6.4.3
OSCILLATOR START-UP TIMER
(OST)
The Oscillator Start-Up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over. This ensures that the crystal
oscillator or resonator has started and stabilized.
The OST timeout is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
6.4.4
TIMEOUT SEQUENCE
On power-up, the timeout sequence is as follows: First
PWRT timeout is invoked after POR has expired, then
OST is activated. The total timeout will vary based on
oscillator configuration and PWRTE bit status. For
example, in RC mode with PWRTE bit erased (PWRT
disabled), there will be no timeout at all. Figure 6-7,
Figure 6-8 and Figure 6-9 depict timeout sequences.
Since the timeouts occur from the POR pulse, if MCLR
is kept low long enough, the timeouts will expire. Then
bringing MCLR high will begin execution immediately
(see Figure 6-8). This is useful for testing purposes or
to synchronize more than one PIC16C55X device operating in parallel.
Table 6-5 shows the RESET conditions for some special registers, while Table 6-6 shows the RESET conditions for all the registers.
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
6.4.5
POWER CONTROL/STATUS
REGISTER (PCON)
Bit1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a subsequent RESET if POR is ‘0’, it will indicate that a Poweron Reset must have occurred (VDD may have gone too
low).
TABLE 6-3:
TIMEOUT IN VARIOUS SITUATIONS
Power-up
Oscillator
Configuration
XT, HS, LP
PWRTE = 0
PWRTE = 1
Wake-up from
SLEEP
72 ms + 1024 TOSC
1024 TOSC
1024 TOSC
72 ms
—
—
RC
TABLE 6-4:
STATUS BITS AND THEIR SIGNIFICANCE
POR
TO
PD
0
1
1
Power-on Reset
0
0
X
Illegal, TO is set on POR
0
X
0
Illegal, PD is set on POR
1
0
u
WDT Reset
1
0
0
WDT Wake-up
1
u
u
MCLR Reset during normal operation
1
1
0
MCLR Reset during SLEEP
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 37
PIC16C55X
TABLE 6-5:
INITIALIZATION CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0-
MCLR Reset during normal operation
000h
000u uuuu
---- --u-
MCLR Reset during SLEEP
000h
0001 0uuu
---- --u-
WDT Reset
000h
0000 uuuu
---- --u-
PC + 1
uuu0 0uuu
---- --u-
uuu1 0uuu
---- --u-
Condition
WDT Wake-up
Interrupt Wake-up from SLEEP
PC +
1(1)
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: When the wake-up is due to an interrupt and global enable bit, GIE is set, the PC is loaded with the interrupt vector (0004h) after execution of PC+1.
TABLE 6-6:
Register
W
INITIALIZATION CONDITION FOR REGISTERS
Address
Power-on Reset
MCLR Reset during normal
operation
MCLR Reset during SLEEP
WDT Reset
—
xxxx xxxx
uuuu uuuu
Wake-up from SLEEP
through interrupt
Wake-up from SLEEP
through WDT timeout
uuuu uuuu
INDF
00h
—
—
—
TMR0
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h
0000 0000
0000 0000
PC + 1(2)
quuu(3)
uuuq quuu(3)
STATUS
03h
0001 1xxx
FSR
04h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTA
05h
---x xxxx
---u uuuu
---u uuuu
PORTB
000q
06h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORTC(4)
06h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCLATH
0Ah
---0 0000
---0 0000
---u uuuu
INTCON
0Bh
0000 000x
0000 000u
uuuu uuuu(1)
OPTION
81h
1111 1111
1111 1111
uuuu uuuu
TRISA
85h
---1 1111
---1 1111
---u uuuu
TRISB
86h
1111 1111
1111 1111
uuuu uuuu
86h
1111 1111
1111 1111
uuuu uuuu
8Eh
---- --0-
---- --u-
---- --u-
TRISC
(4)
PCON
Legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ‘0’, q = value depends on condition.
Note 1: One or more bits in INTCON will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt
vector (0004h).
3: See Table 6-5 for RESET value for specific condition.
4: PIC16C557 only.
DS40143E-page 38
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
FIGURE 6-7:
TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIMEOUT
TOST
OST TIMEOUT
INTERNAL RESET
TIMEOUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2
FIGURE 6-8:
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIMEOUT
TOST
OST TIMEOUT
INTERNAL RESET
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 39
PIC16C55X
FIGURE 6-9:
TIMEOUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD): CASE 3
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIMEOUT
TOST
OST TIMEOUT
INTERNAL RESET
FIGURE 6-10:
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW VDD POWER-UP)
VDD
VDD
D
R
R1
MCLR
C
Note
1:
2:
3:
PIC16C55X
External Power-on Reset circuit is required only if
VDD power-up slope is too slow. The diode D helps
discharge the capacitor quickly when VDD powers
down.
< 40 k is recommended to make sure that voltage
drop across R does not violate the device’s electrical
specification.
R1 = 100 to 1 k will limit any current flowing into
MCLR from external capacitor C in the event of
MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).
DS40143E-page 40
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
6.5
Interrupts
The PIC16C55X has 3 sources of interrupt:
• External interrupt RB0/INT
• TMR0 overflow interrupt
• PORTB change interrupts (pins RB7:RB4)
The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in
INTCON register. GIE is cleared on RESET.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs (Figure 6-12).
The latency is the same for one or two cycle
instructions. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid multiple interrupt requests. Individual interrupt
flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
Note 1: Individual interrupt flag bits are set
regardless of the status of their
corresponding mask bit or the GIE bit.
The “Return from Interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables RB0/INT interrupts.
The INT pin interrupt, the RB port change interrupt and
the TMR0 overflow interrupt flags are contained in the
INTCON register.
When an interrupt is responded to, the GIE is cleared
to disable any further interrupt, the return address is
pushed into the stack and the PC is loaded with 0004h.
Once in the interrupt service routine the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid RB0/INT
recursive interrupts.
FIGURE 6-11:
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The CPU will execute a NOP
in the cycle immediately following the
instruction which clears the GIE bit. The
interrupts which were ignored are still
pending to be serviced when the GIE bit
is set again.
INTERRUPT LOGIC
Wake-up
(If in SLEEP mode)
T0IF
T0IE
INTF
INTE
Interrupt
to CPU
RBIF
RBIE
GIE
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 41
PIC16C55X
6.5.1
RB0/INT INTERRUPT
6.5.2
An overflow (FFh 00h) in the TMR0 register will
set the T0IF (INTCON) bit. The interrupt can
be enabled/disabled by setting/clearing T0IE
(INTCON) bit. For operation of the Timer0 module,
see Section 7.0.
An external interrupt on RB0/INT pin is edge triggered:
either rising if INTEDG bit (OPTION) is set, or falling if INTEDG bit is clear. When a valid edge appears
on the RB0/INT pin, the INTF bit (INTCON) is set.
This interrupt can be disabled by clearing the INTE
control bit (INTCON). The INTF bit must be cleared
in software in the interrupt service routine before reenabling this interrupt. The RB0/INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was
set prior to going into SLEEP. The status of the GIE bit
decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 6.8 for
details on SLEEP and Figure 6-14 for timing of wakeup from SLEEP through RB0/INT interrupt.
FIGURE 6-12:
TMR0 INTERRUPT
6.5.3
PORTB INTERRUPT
An input change on PORTB sets the RBIF
(INTCON) bit. The interrupt can be enabled/disabled by setting/clearing the RBIE (INTCON) bit.
For operation of PORTB (Section 5.2).
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF interrupt flag may get set.
INT PIN INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT 3
4
INT pin
1
1
INTF flag
(INTCON)
Interrupt Latency 2
5
GIE bit
(INTCON)
INSTRUCTION FLOW
PC
PC
PC+1
Instruction
fetched
Inst (PC)
Inst (PC+1)
Instruction
executed
Inst (PC-1)
Inst (PC)
PC+1
—
Dummy Cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy Cycle
Inst (0004h)
Note 1: INTF flag is sampled here (every Q1).
2: Interrupt latency = 3-4 TCY where TCY = instruction cycle time. Latency is the same whether Inst (PC) is a single
cycle or a 2-cycle instruction.
3: CLKOUT is available only in RC Oscillator mode.
4: For minimum width of INT pulse, refer to AC specs.
5: INTF is enabled to be set anytime during the Q4-Q1 cycles.
DS40143E-page 42
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
6.6
Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt (e.g., W register and STATUS
register). This will have to be implemented in software.
Example 6-1 stores and restores the STATUS and W
registers. The user register, W_TEMP, must be defined
in both banks and must be defined at the same offset
from the bank base address (i.e., W_TEMP is defined at
0x20 in Bank 0 and it must also be defined at 0xA0 in
Bank 1). The user register, STATUS_TEMP, must be
defined in Bank 0. The Example 6-1:
•
•
•
•
Stores the W register
Stores the STATUS register in Bank 0
Executes the ISR code
Restores the STATUS (and bank select bit
register)
• Restores the W register
EXAMPLE 6-1:
W_TEMP
SWAPF
STATUS,W
BCF
STATUS,RP0
MOVWF
STATUS_TEMP
:
:
:
SWAPF
MOVWF
SWAPF
SWAPF
WDT PERIOD
The WDT has a nominal timeout period of 18 ms, (with
no prescaler). The timeout periods vary with temperature, VDD and process variations from part-to-part (see
DC specs). If longer timeout periods are desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT under software control by writing
to the OPTION register. Thus, timeout periods up to 2.3
seconds can be realized.
;copy W to TEMP
;register, could be in
;either bank
;swap STATUS to be
;saved into W
;change to bank0
;regardless of
;current bank
;save STATUS to bank0
;register
STATUS_TEMP,W;swap STATUS_TEMP
;register into W, sets
;bank to original state
STATUS
;move W into STATUS
;register
W_TEMP,F
;swap W_TEMP
W_TEMP,W
;swap W_TEMP into W
1996-2013 Microchip Technology Inc.
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC oscillator which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the CLKIN pin. That means that the WDT will run, even
if the clock on the OSC1 and OSC2 pins of the device
has been stopped, for example, by execution of a
SLEEP instruction. During normal operation, a WDT
timeout generates a device RESET. If the device is in
SLEEP mode, a WDT timeout causes the device to
wake-up and continue with normal operation. The WDT
can be permanently disabled by programming the configuration bit WDTE as clear (Section 6.1).
6.7.1
SAVING THE STATUS
AND W REGISTERS IN
RAM
MOVWF
6.7
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler, if assigned to the WDT, and prevent
it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer timeout.
6.7.2
WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT timeout occurs.
Preliminary
DS40143E-page 43
PIC16C55X
FIGURE 6-13:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 7-6)
0
Watchdog
Timer
M
U
X
1
Postscaler
8
PS
8 - to - 1 MUX
PSA
WDT
Enable Bit
To TMR0
(Figure 7-6)
0
1
MUX
PSA
WDT
Timeout
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
TABLE 6-7:
Address
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
Bit 7
Bit 6
Bit 5
Bit 4
2007h
Config. bits
—
Reserved
CP1
CP0
81h
OPTION
RBPU
INTEDG
T0CS T0SE
Bit 3
Bit 2
PWRTE WDTE
PSA
PS2
Bit 1
Bit 0
FOSC1
FOSC0
PS1
PS0
Value on POR
Value on all
other RESETS
1111 1111
1111 1111
Legend: x = unknown, u = unchanged, q = value depends on condition, — = unimplemented, read as ‘0’.
Shaded cells are not used by the Watchdog Timer.
DS40143E-page 44
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
6.8
Power-Down Mode (SLEEP)
The first event will cause a device RESET. The two latter events are considered a continuation of program
execution. The TO and PD bits in the STATUS register
can be used to determine the cause of device RESET.
PD bit, which is set on power-up is cleared when
SLEEP is invoked. TO bit is cleared if WDT Wake-up
occurred.
The Power-down mode is entered by executing a
SLEEP instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the STATUS register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had,
before SLEEP was executed (driving high, low, or hiimpedance).
When the SLEEP instruction is being executed, the
next instruction (PC + 1) is pre-fetched. For the device
to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up
is regardless of the state of the GIE bit. If the GIE bit is
clear (disabled), the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
set (enabled), the device executes the instruction after
the SLEEP instruction and then branches to the interrupt address (0004h). In cases where the execution of
the instruction following SLEEP is not desirable, the
user should have an NOP after the SLEEP instruction.
For lowest current consumption in this mode, all I/O
pins should be either at VDD, or VSS, with no external
circuitry drawing current from the I/O pin. I/O pins that
are hi-impedance inputs should be pulled high or low
externally to avoid switching currents caused by floating inputs. The T0CKI input should also be at VDD or
VSS for lowest current consumption. The contribution
from on-chip pull-ups on PORTB should be considered.
The MCLR pin must be at a logic high level (VIHMC).
Note:
Note:
It should be noted that a RESET generated
by a WDT timeout does not drive MCLR
pin low.
6.8.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
If the global interrupts are disabled (GIE is
cleared), but any interrupt source has both
its interrupt enable bit and the corresponding interrupt flag bits set, the device will
immediately wake-up from SLEEP. The
SLEEP instruction is completely executed.
The WDT is cleared when the device wakes-up from
SLEEP, regardless of the source of wake-up.
External RESET input on MCLR pin
Watchdog Timer Wake-up (if WDT was enabled)
Interrupt from RB0/INT pin or RB Port change
FIGURE 6-14:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKOUT(4)
INT pin
INTF flag
(INTCON)
Interrupt Latency(2)
GIE bit
(INTCON)
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
fetched
Instruction
executed
Note
1:
2:
3:
4:
PC
Inst(PC) = SLEEP
Inst(PC - 1)
PC+1
PC+2
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
PC + 2
Dummy cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy cycle
Inst(0004h)
XT, HS or LP Oscillator mode assumed.
TOST = 1024TOSC (drawing not to scale). This delay will not be there for RC osc mode.
GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 45
PIC16C55X
6.9
FIGURE 6-15:
Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out for verification purposes.
Note:
6.10
Microchip does not recommend code
protecting windowed devices.
ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code-identification numbers. These locations are
not accessible during normal execution but are
readable and writable during program/verify.
6.11
External
Connector
Signals
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
To Normal
Connections
PIC16C55X
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB6
Data I/O
RB7
In-Circuit Serial Programming™
The PIC16C55X microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data, and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices, and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware or a custom
firmware to be programmed.
VDD
To Normal
Connections
The device is placed into a Program/Verify mode by
holding the RB6 and RB7 pins low while raising the
MCLR (VPP) pin from VIL to VIHH (see programming
specification). RB6 becomes the programming clock
and RB7 becomes the programming data. Both RB6
and RB7 are Schmitt Trigger inputs in this mode.
After RESET, to place the device into Programming/
Verify mode, the program counter (PC) is at location
00h. A 6-bit command is then supplied to the device.
Depending on the command, 14 bits of program data
are then supplied to or from the device, depending if
the command was a load or a read. For complete
details of serial programming, please refer to the
PIC16C6X/7X Programming Specifications (Literature
#DS30228).
A typical in-circuit serial programming connection is
shown in Figure 6-15.
DS40143E-page 46
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
7.0
TIMER0 MODULE
bit (OPTION). Clearing the T0SE bit selects the
rising edge. Restrictions on the external clock input are
discussed in detail in Section 7.2.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
The prescaler is shared between the Timer0 module
and the Watchdog Timer. The prescaler assignment is
controlled in software by the control bit PSA
(OPTION). Clearing the PSA bit will assign the
prescaler to Timer0. The prescaler is not readable or
writable. When the prescaler is assigned to the Timer0
module, prescale value of 1:2, 1:4, ..., 1:256 are
selectable. Section 7.3 details the operation of the
prescaler.
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Figure 7-1 is a simplified block diagram of the Timer0
module.
7.1
Timer mode is selected by clearing the T0CS bit
(OPTION). In Timer mode, the TMR0 will increment
every instruction cycle (without prescaler). If Timer0 is
written, the increment is inhibited for the following two
cycles (Figure 7-2 and Figure 7-3). The user can work
around this by writing an adjusted value to TMR0.
Timer0 interrupt is generated when the TMR0 register
timer/counter overflows from FFh to 00h. This overflow
sets the T0IF bit. The interrupt can be masked by
clearing the T0IE bit (INTCON). The T0IF bit
(INTCON) must be cleared in software by the
Timer0 module interrupt service routine before reenabling this interrupt. The Timer0 interrupt cannot
wake the processor from SLEEP since the timer is shut
off during SLEEP. See Figure 7-4 for Timer0 interrupt
timing.
Counter mode is selected by setting the T0CS bit. In
this mode Timer0 will increment either on every rising
or falling edge of pin RA4/T0CKI. The incrementing
edge is determined by the source edge (T0SE) control
FIGURE 7-1:
TIMER0 Interrupt
TIMER0 BLOCK DIAGRAM
Data bus
RA4/T0CKI
pin
FOSC/4
0
PSout
1
1
Programmable
Prescaler
0
PS2:PS0
PSA
8
Sync with
Internal
clocks
TMR0
PSout
(2 Tcy delay)
T0SE
Set Flag bit T0IF
on Overflow
T0CS
Note 1: Bits, T0SE, T0CS, PS2, PS1, PS0 and PSA are located in the OPTION register.
2: The prescaler is shared with Watchdog Timer (Figure 7-6)
FIGURE 7-2:
PC
(Program
Counter)
TIMER0 (TMR0) TIMING: INTERNAL CLOCK/NO PRESCALER
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC-1
Instruction
Fetch
TMR0
PC
MOVWF TMR0
T0
T0+1
Instruction
Executed
1996-2013 Microchip Technology Inc.
PC+1
PC+2
PC+3
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
T0+2
NT0
NT0
Write TMR0
executed
Read TMR0
reads NT0
Read TMR0
reads NT0
Preliminary
PC+4
MOVF TMR0,W
NT0
Read TMR0
reads NT0
PC+5
PC+6
MOVF TMR0,W
NT0+1
NT0+2
T0
Read TMR0
Read TMR0
reads NT0 + 1 reads NT0 + 2
DS40143E-page 47
PIC16C55X
FIGURE 7-3:
TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
(Program
Counter)
PC-1
PC
PC+1
MOVWF TMR0
Instruction
Fetch
T0
TMR0
PC+2
PC+3
T0+1
Instruction
Execute
MOVF TMR0,W
PC+5
PC+6
MOVF TMR0,W
NT0+1
NT0
Write TMR0
executed
FIGURE 7-4:
PC+4
MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0
Read TMR0
reads NT0 + 1
TIMER0 INTERRUPT TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKOUT(3)
TMR0 timer
FFh
FEh
1
T0IF bit
(INTCON)
00h
01h
02h
1
GIE bit
(INTCON)
Interrupt Latency Time
INSTRUCTION FLOW
PC
PC
Instruction
fetched
Inst (PC)
Instruction
executed
Inst (PC-1)
Note
1:
2:
3:
PC +1
PC +1
Inst (PC+1)
Inst (PC)
Dummy cycle
0004h
0005h
Inst (0004h)
Inst (0005h)
Dummy cycle
Inst (0004h)
T0IF interrupt flag is sampled here (every Q1).
Interrupt latency = 4 TCY, where TCY = instruction cycle time.
CLKOUT is available only in RC Oscillator mode.
DS40143E-page 48
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
7.2
Using Timer0 with External Clock
When an external clock input is used for Timer0, it must
meet certain requirements. The external clock
requirement is due to internal phase clock (TOSC)
synchronization. Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
7.2.1
EXTERNAL CLOCK
SYNCHRONIZATION
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI with the internal phase clocks is
accomplished by sampling the prescaler output on the
Q2 and Q4 cycles of the internal phase clocks
(Figure 7-5). Therefore, it is necessary for T0CKI to be
high for at least 2TOSC (and a small RC delay of 20 ns)
and low for at least 2TOSC (and a small RC delay of
20 ns). Refer to the electrical specification of the
desired device.
FIGURE 7-5:
When a prescaler is used, the external clock input is
divided by the asynchronous ripple-counter type
prescaler so that the prescaler output is symmetrical.
For the external clock to meet the sampling
requirement, the ripple-counter must be taken into
account. Therefore, it is necessary for T0CKI to have a
period of at least 4TOSC (and a small RC delay of 40 ns)
divided by the prescaler value. The only requirement
on T0CKI high and low time is that they do not violate
the minimum pulse width requirement of 10 ns. Refer to
parameters 40, 41 and 42 in the electrical specification
of the desired device.
7.2.2
TIMER0 INCREMENT DELAY
Since the prescaler output is synchronized with the
internal clocks, there is a small delay from the time the
external clock edge occurs to the time the TMR0 is
actually incremented. Figure 7-5 shows the delay from
the external clock edge to the timer incrementing.
TIMER0 TIMING WITH EXTERNAL CLOCK
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
Q1 Q2 Q3 Q4
External Clock Input or
Prescaler output (2)
Q1 Q2 Q3 Q4
Small pulse
misses sampling
(1)
(3)
External Clock/Prescaler
Output after sampling
Increment Timer0 (Q4)
Timer0
T0
T0 + 1
T0 + 2
Note 1: Delay from clock input change to Timer0 increment is 3 TOSC to 7 TOSC. (Duration of Q = TOSC).
Therefore, the error in measuring the interval between two edges on Timer0 input = ±4 TOSC max.
2: External clock if no prescaler selected, prescaler output otherwise.
3: The arrows indicate the points in time where sampling occurs.
7.3
Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 7-6). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet.
Note:
There is only one prescaler available
which is mutually exclusive between the
Timer0 module and the Watchdog Timer.
Thus, a prescaler assignment for the
Timer0 module means that there is no
prescaler for the Watchdog Timer, and
vice-versa.
1996-2013 Microchip Technology Inc.
The PSA and PS2:PS0 bits (OPTION) determine
the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1,
MOVWF 1, BSF 1,x....etc.) will clear the prescaler.
When assigned to WDT, a CLRWDT instruction will clear
the prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
Preliminary
DS40143E-page 49
PIC16C55X
FIGURE 7-6:
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
Data Bus
CLKOUT (=Fosc/4)
0
T0CKI
pin
8
M
U
X
1
M
U
X
0
1
SYNC
2
Tcy
TMR0 reg
T0SE
T0CS
0
Watchdog
Timer
1
M
U
X
Set flag bit T0IF
on Overflow
PSA
8-bit Prescaler
8
8-to-1MUX
PS0 - PS2
PSA
WDT Enable bit
0
1
MUX
PSA
WDT
Timeout
Note 1: T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
DS40143E-page 50
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
7.3.1
SWITCHING PRESCALER
ASSIGNMENT
To change prescaler from the WDT to the TMR0
module use the sequence shown in Example 7-2. This
precaution must be taken even if the WDT is disabled.
The prescaler assignment is fully under software
control (i.e., it can be changed “on the fly” during
program execution). To avoid an unintended device
RESET,
the
following
instruction
sequence
(Example 7-1) must be executed when changing the
prescaler assignment from Timer0 to WDT. Lines 5-7
are required only if the desired postscaler rate is 1:1
(PS = 000) or 1:2 (PS = 001).
EXAMPLE 7-1:
BCF
CLRF
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
CHANGING PRESCALER
(WDTTIMER0)
;Clear WDT and
;prescaler
CLRWDT
CHANGING PRESCALER
(TIMER0WDT)
BSF
MOVLW
STATUS, RP0
b'xxxx0xxx'
MOVWF
BCF
OPTION
STATUS, RP0
;Select TMR0, new
;prescale value and
;clock source
STATUS, RP0 ;Skip if already in
;Bank 0 CLRWDT Clear WDT
TMR0
;Clear TMR0 & Prescaler
STATUS, RP0 ;Bank 1
'00101111’b ;These 3 lines (5, 6, 7)
OPTION
;Are required only if
;Desired PS are
;CLRWDT 000 or 001
'00101xxx’b ;Set Postscaler to
OPTION
;Desired WDT rate
STATUS, RP0 ;Return to Bank 0
TABLE 7-1:
Address
EXAMPLE 7-2:
Name
REGISTERS ASSOCIATED WITH TIMER0
Bit 7
Bit 6
Value on
All Other
RESETS
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR
xxxx xxxx
uuuu uuuu
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000x
01h
TMR0
0Bh/8Bh
INTCON
Timer0 module’s register
GIE
Reserved
T0IE
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
1111 1111
85h
TRISA
—
—
—
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
---1 1111
---1 1111
Legend:
— = Unimplemented locations, read as ‘0’,
Note 1: Shaded bits are not used by TMR0 module.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 51
PIC16C55X
NOTES:
DS40143E-page 52
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
8.0
INSTRUCTION SET SUMMARY
Each PIC16C55X instruction is a 14-bit word divided
into an OPCODE which specifies the instruction type
and one or more operands which further specify the
operation of the instruction. The PIC16C55X instruction set summary in Table 8-2 lists byte-oriented, bitoriented, and literal and control operations. Table 81 shows the opcode field descriptions.
For byte-oriented instructions, 'f' represents a file
register designator and 'd' represents a destination
designator. The file register designator specifies which
file register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If 'd' is zero, the result is
placed in the W register. If 'd' is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.
For literal and control operations, 'k' represents an
eight or eleven bit constant or literal value.
TABLE 8-1:
OPCODE FIELD
DESCRIPTIONS
Field
• Byte-oriented operations
• Bit-oriented operations
• Literal and control operations
All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles with the second cycle executed as a
NOP. One instruction cycle consists of four oscillator
periods. Thus, for an oscillator frequency of 4 MHz, the
normal instruction execution time is 1 s. If a
conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 s.
Table 8-1 lists the instructions recognized by the
MPASM™ assembler.
Figure 8-1 shows the three general formats that the
instructions can have.
Note:
0xhh
Description
where h signifies a hexadecimal digit.
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It
is the recommended form of use for compatibility with all Microchip software tools.
FIGURE 8-1:
label
Label name
TOS
Top of Stack
Program Counter High Latch
GIE
Global Interrupt Enable bit
WDT
Watchdog Timer/Counter
TO
Timeout bit
PD
Power-down bit
dest
]
Options
(
)
Contents
< >
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
Destination either the W register or the specified
register file location
[
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
Program Counter
PC
PCLATH
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1
d
To maintain upward compatibility with
future PIC® MCU products, do not use the
OPTION and TRIS instructions.
All examples use the following format to represent a
hexadecimal number:
f
The instruction set is highly orthogonal and is grouped
into three basic categories:
13
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
Assigned to
CALL and GOTO instructions only
Register bit field
13
In the set of
11
OPCODE
italics User defined term (font is courier)
10
0
k (literal)
k = 11-bit immediate value
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 53
PIC16C55X
TABLE 8-2:
Mnemonic,
Operands
PIC16C55X INSTRUCTION SET
14-Bit Opcode
Description
Cycles
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
0011
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
1
1
1(2)
1(2)
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
01
01
01
01
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external
device, the data will be written back with a '0'.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if
assigned to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
DS40143E-page 54
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
8.1
Instruction Descriptions
ADDLW
Add Literal and W
Syntax:
[ label ] ADDLW
Operands:
ANDLW
AND Literal with W
Syntax:
[ label ] ANDLW
0 k 255
Operands:
0 k 255
Operation:
(W) + k (W)
Operation:
(W) .AND. (k) (W)
Status Affected:
C, DC, Z
Status Affected:
Z
Encoding:
11
Encoding:
11
Description:
111x
k
kkkk
kkkk
The contents of the W register are
added to the eight bit literal 'k' and the
result is placed in the W register.
Description:
1
Words:
1
Cycles:
1
Cycles:
1
ADDLW
Example
ANDLW
0x15
kkkk
0x5F
Before Instruction
W
=
0xA3
After Instruction
W
=
0x03
Before Instruction
W
=
0x10
After Instruction
W
=
0x25
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
0 f 127
d
Operands:
0 f 127
d
Operation:
(W) + (f) (dest)
Operation:
(W) .AND. (f) (dest)
Status Affected:
C, DC, Z
Status Affected:
Z
00
Encoding:
00
ADDWF
Add W and f
Syntax:
[ label ] ADDWF
Operands:
Encoding:
Description:
0111
f,d
dfff
ffff
Add the contents of the W register
with register 'f'. If 'd' is 0 the result is
stored in the W register. If 'd' is 1 the
result is stored back in register 'f'.
Description:
1
Words:
1
Cycles:
1
Cycles:
1
Example
ADDWF
Example
ANDWF
0
dfff
ffff
FSR,
1
Before Instruction
W
=
0x17
FSR =
0xC2
After Instruction
W
=
0x17
FSR =
0x02
Before Instruction
W
=
0x17
FSR =
0xC2
After Instruction
W
=
0xD9
FSR =
0xC2
1996-2013 Microchip Technology Inc.
0101
f,d
AND the W register with register 'f'. If
'd' is 0 the result is stored in the W
register. If 'd' is 1 the result is stored
back in register 'f'.
Words:
FSR,
kkkk
The contents of W register are
AND’ed with the eight bit literal 'k'. The
result is placed in the W register.
Words:
Example
1001
k
Preliminary
DS40143E-page 55
PIC16C55X
BCF
Bit Clear f
Syntax:
[ label ] BCF
Operands:
BTFSC
Syntax:
[ label ] BTFSC f,b
0 f 127
0b7
Operands:
0 f 127
0b7
Operation:
0 (f)
Operation:
skip if (f) = 0
Status Affected:
None
Status Affected:
None
Encoding:
Description:
01
f,b
Bit Test, Skip if Clear
00bb
bfff
Words:
1
Cycles:
1
Example
BCF
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 127
0b7
Operation:
1 (f)
Status Affected:
None
Encoding:
01
01bb
Words:
1
Cycles:
1
FLAG_REG,
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
10bb
bfff
ffff
Description:
Words:
1
Cycles:
1(2)
Example
0x47
bfff
Bit 'b' in register 'f' is set.
DS40143E-page 56
0xC7
01
If bit 'b' in register 'f' is '0' then the next
instruction is skipped. If bit 'b' is '0' then
the next instruction fetched during the
current instruction execution is discarded, and a NOP is executed instead,
making this a two-cycle instruction.
f,b
Description:
BSF
Encoding:
FLAG_REG, 7
Before Instruction
FLAG_REG =
After Instruction
FLAG_REG =
Example
ffff
Bit 'b' in register 'f' is cleared.
ffff
HERE
FALSE
TRUE
BTFSC
GOTO
•
•
•
FLAG,1
PROCESS_CODE
Before Instruction
PC
= address HERE
After Instruction
if FLAG = 0,
PC
= address TRUE
if FLAG = 1,
PC
= address FALSE
7
0x0A
0x8A
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
BTFSS
Bit Test f, Skip if Set
CALL
Call Subroutine
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CALL k
Operands:
0 f 127
0b VDD) ........................................................................................................±20 mA
Output Clamp Current, IOK (V0 < 0 or V0 > VDD).................................................................................................. ±20 mA
Maximum Output Current sunk by any I/O pin ........................................................................................................25 mA
Maximum Output Current sourced by any I/O pin...................................................................................................25 mA
Maximum Current sunk by PORTA, PORTB and PORTC ....................................................................................200 mA
Maximum Current sourced by PORTA, PORTB and PORTC ...............................................................................200 mA
Note 1: Power dissipation is calculated as follows: PDIS = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL)
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 73
PIC16C55X
VOLTAGE-FREQUENCY GRAPH, 0C TA +70C (COMMERCIAL TEMPS)
FIGURE 10-1:
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
VOLTAGE-FREQUENCY GRAPH,
-40C TA 0C, +70C TA +125C (OUTSIDE OF COMMERCIAL TEMPS)
FIGURE 10-2:
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
4
10
Frequency (MHz)
20
25
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
DS40143E-page 74
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
VOLTAGE-FREQUENCY GRAPH, 0C TA +85C
FIGURE 10-3:
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
PIC16LC554/557/558 VOLTAGE-FREQUENCY GRAPH, -40C TA 0C
FIGURE 10-4:
6.0
5.5
5.0
VDD
(Volts)
4.5
4.0
3.5
3.0
2.7
2.5
2.0
0
4
10
20
25
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: The maximum rated speed of the part limits the permissible combinations of voltage and frequency.
Please reference the Product Identification System section for the maximum rated speed of the parts.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 75
PIC16C55X
10.1
DC Characteristics: PIC16C55X-04 (Commercial, Industrial, Extended)
PIC16C55X-20 (Commercial, Industrial, Extended)
HCS1365-04 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40C TA +85C for industrial and
0C TA +70C for commercial and
-40C TA +125C for extended
DC Characteristics
Param
No.
Sym
VDD
Characteristic
Min
Typ† Max Units
Conditions
Supply Voltage
D001
16LC55X
3.0
2.5
—
5.5
5.5
V
XT and RC osc configuration
LP osc configuration
16C55X
3.0
4.5
—
—
5.5
5.5
V
V
XT, RC and LP osc configuration
HS osc configuration
D001
D001A
D002
VDR
RAM Data Retention
Voltage(1)
—
1.5*
—
V
Device in SLEEP mode
D003
VPOR
VDD Start Voltage to
ensure Power-on Reset
—
VSS
—
V
See Section 6.4, Power-on Reset for
details
D004
SVDD
VDD Rise Rate to ensure
Power-on Reset
0.05*
—
—
—
1.4
2.5
mA
—
26
53
A
—
1.8
3.3
mA
D010A
—
35
70
A
D013
—
9.0
20
mA
IDD
Supply Current(2)
16LC55X
D010
D010A
16C55X
D010
*
V/ms See Section 6.4, Power-on Reset for
details
XT and RC osc configuration
Fosc = 2.0 MHz, VDD = 3.0V, WDT
disabled(4)
LP osc configuration
Fosc = 32 kHz, VDD = 3.0V, WDT
disabled
XT and RC osc configuration
FOSC = 4 MHz, VDD = 5.5V,
WDT disabled(4)
LP osc configuration,
PIC16C55X-04 only
FOSC = 32 kHz, VDD = 4.0V,
WDT disabled
HS osc configuration
FOSC = 20 MHz, VDD = 5.5V,
WDT disabled
These parameters are characterized but not tested.
† Data is “Typ” column is at 5V, 25C,unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins configured as input, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins configured as input and tied to VDD or VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k
5: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
DS40143E-page 76
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
10.1
DC Characteristics: PIC16C55X-04 (Commercial, Industrial, Extended)
PIC16C55X-20 (Commercial, Industrial, Extended)
HCS1365-04 (Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40C TA +85C for industrial and
0C TA +70C for commercial and
-40C TA +125C for extended
DC Characteristics
Param
No.
D020
Sym
IPD
IWDT
*
Characteristic
Min
Typ† Max Units
Conditions
Power-Down Current(3)
16LC55X
—
0.7
2
A
VDD = 3.0V, WDT disabled
16C55X
—
1.0
2.5
15
A
A
VDD = 4.0V, WDT disabled
(+85C to +125C)
16LC55X
—
6.0
15
A
VDD = 3.0V
16C55X
—
6.0
20
A
VDD = 4.0V
(+85C to +125C)
WDT Current(5)
These parameters are characterized but not tested.
† Data is “Typ” column is at 5V, 25C,unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode without losing RAM data.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin
loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an
impact on the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail to rail; all I/O pins configured as input, pulled to VDD,
MCLR = VDD; WDT enabled/disabled as specified.
3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is
measured with the part in SLEEP mode, with all I/O pins configured as input and tied to VDD or VSS.
4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in k
5: The current is the additional current consumed when this peripheral is enabled. This current should be
added to the base IDD or IPD measurement.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 77
PIC16C55X
10.2
DC Characteristics: PIC16C55X (Commercial, Industrial, Extended)
PIC16LC55X(Commercial, Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial and
0°C TA +70°C for commercial and
-40°C TA +125°C for automotive
Operating voltage VDD range as described in DC spec Table 10-1
DC Characteristics
Param.
No.
Sym
VIL
Characteristic
Min
Typ†
Max
Unit
with TTL buffer
VSS
—
0.8V
0.15 VDD
V
with Schmitt Trigger input
VSS
0.2 VDD
V
0.2 VDD
V
Conditions
Input Low Voltage
I/O ports
D030
D031
D032
MCLR, RA4/T0CKI,OSC1 (in
RC mode)
D033
VIH
VSS
—
OSC1 (in XT* and HS)
VSS
—
0.3 VDD
V
OSC1 (in LP*)
VSS
—
0.6 VDD-1.0
V
2.0V
0.8 + 0.25 VDD
—
—
VDD
VDD
V
V
VDD = 4.5V to 5.5V
otherwise
(Note1)
Input High Voltage
I/O ports
D040
—
with TTL buffer
D041
with Schmitt Trigger input
0.8V
VDD = 4.5V to 5.5V
otherwise
VDD
D042
MCLR RA4/T0CKI
0.8 VDD
—
VDD
V
D043
D043A
OSC1 (XT*, HS and LP*)
OSC1 (in RC mode)
0.7 VDD
0.9 VDD
—
VDD
V
50
200
400
A
VDD = 5.0V, VPIN = VSS
1.0
A
VSS VPIN VDD, pin at hiimpedance
0.5
A
Vss VPIN VDD, pin at hiimpedance
D070
IPURB
PORTB weak pull-up current
IIL
Input Leakage Current(2)(3)
(Note1)
I/O ports (Except PORTA)
D060
PORTA
D061
RA4/T0CKI
—
—
1.0
A
Vss VPIN VDD
D063
OSC1, MCLR
—
—
5.0
A
Vss VPIN VDD, XT, HS and
LP osc configuration
—
0.6
V
IOL=8.5 mA, VDD=4.5V, -40 to
+85C
VOL
—
—
Output Low Voltage
D080
I/O ports
—
—
—
0.6
V
IOL=7.0 mA, VDD=4.5V, +125C
D083
OSC2/CLKOUT
—
—
0.6
V
IOL=1.6 mA, VDD=4.5V, -40 to
+85C
—
—
0.6
V
IOL=1.2 mA, VDD=4.5V, +125C
VDD-0.7
—
—
V
IOH=-3.0 mA, VDD=4.5V, -40 to
+85C
(RC only)
VOH
D090
Output High Voltage
(3)
I/O ports (Except RA4)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C55X be
driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
DS40143E-page 78
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
10.2
DC Characteristics: PIC16C55X (Commercial, Industrial, Extended)
PIC16LC55X(Commercial, Industrial, Extended) (Continued)
Standard Operating Conditions (unless otherwise stated)
Operating temperature -40°C TA +85°C for industrial and
0°C TA +70°C for commercial and
-40°C TA +125°C for automotive
Operating voltage VDD range as described in DC spec Table 10-1
DC Characteristics
Param.
No.
Sym
D092
*
VOD
Characteristic
Min
Typ†
Max
Unit
VDD-0.7
—
—
V
IOH=-2.5 mA,
VDD=4.5V, +125C
OSC2/CLKOUT
VDD-0.7
—
—
V
IOH=-1.3 mA, VDD=4.5V, -40 to
+85C
(RC only)
VDD-0.7
—
—
V
IOH=-1.0 mA,
VDD=4.5V, +125C
10*
V
RA4 pin
15
pF
In XT, HS and LP modes when
external clock used to drive
OSC1.
50
pF
Open-Drain High Voltage
Conditions
Capacitive Loading Specs on Output Pins
D100
COSC OSC2 pin
2
D101
CIO
All I/O pins/OSC2 (in RC
mode)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: In RC oscillator configuration, the OSC1 pin is a Schmitt Trigger input. It is not recommended that the PIC16C55X be
driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as coming out of the pin.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 79
PIC16C55X
10.3
Timing Parameter Symbology
The timing parameter symbols have been created with
one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase subscripts (pp) and their meanings:
pp
ck
CLKOUT
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
FIGURE 10-5:
T
Time
os
t0
OSC1
T0CKI
P
R
V
Z
Period
Rise
Valid
Hi-impedance
LOAD CONDITIONS
Load condition 1
Load condition 2
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL = 464
CL = 50 pF
15 pF
DS40143E-page 80
for all pins except OSC2
for OSC2 output
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
10.4
Timing Diagrams and Specifications
FIGURE 10-6:
EXTERNAL CLOCK TIMING
Q4
Q1
Q3
Q2
Q4
Q1
OSC1
1
3
3
4
4
2
CLKOUT
TABLE 10-1:
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
Characteristic
Min
Fos
External CLKIN Frequency(1)
DC
—
4
MHz
XT and RC osc mode, VDD=5.0V
DC
—
20
MHz
HS osc mode
LP osc mode
Oscillator Frequency(1)
1
Tosc
External CLKIN Period(1)
Oscillator Period(1)
2
Tcy
3*
TosL,
TosH
4*
TosR,
TosF
Instruction Cycle
External Clock in (OSC1) Rise or
Fall Time
Max
Units
Conditions
DC
—
200
kHz
DC
—
4
MHz
RC osc mode, VDD=5.0V
0.1
—
4
MHz
XT osc mode
1
—
20
MHz
HS osc mode
DC
–
200
kHz
LP osc mode
250
—
—
ns
XT and RC osc mode
50
—
—
ns
HS osc mode
5
—
—
s
LP osc mode
250
—
—
ns
RC osc mode
250
—
10,000
ns
XT osc mode
50
—
1,000
ns
HS osc mode
5
—
—
s
LP osc mode
1.0
Fos/4
DC
s
TCY=FOS/4
100*
—
—
ns
XT osc mode
Time(1)
External Clock in (OSC1) High or
Low Time
Typ†
2*
—
—
s
LP osc mode
20*
—
—
ns
HS osc mode
25*
—
—
ns
XT osc mode
50*
—
—
ns
LP osc mode
15*
—
—
ns
HS osc mode
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0 V, 25C unless otherwise stated. These parameters are for design guidance only and are not
tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device executing
code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current
consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1 pin.
When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 81
PIC16C55X
FIGURE 10-7:
CLKOUT AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
10
11
22
23
CLKOUT
13
19
14
12
18
16
I/O Pin
(input)
15
17
I/O Pin
(output)
new value
old value
20, 21
Note 1: All tests must be done with specified capacitance loads (Figure 10-5) 50 pF on I/O pins and CLKOUT.
DS40143E-page 82
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
TABLE 10-2:
Parameter #
CLKOUT AND I/O TIMING REQUIREMENTS
Sym
Characteristic
Min
Typ†
Max
Units
10*
TosH2ckL
OSC1 to CLKOUT
(1)
—
—
75
—
200
400
ns
ns
11*
TosH2ckH
OSC1 to CLKOUT (1)
—
—
75
—
200
400
ns
ns
12*
TckR
CLKOUT rise time(1)
—
—
35
—
100
200
ns
ns
13*
TckF
CLKOUT fall time(1)
—
—
35
—
100
200
ns
ns
14*
TckL2ioV
CLKOUT to Port out valid(1)
—
—
20
ns
15*
TioV2ckH
Port in valid before CLKOUT
Tosc +200 ns
Tosc +400 ns
—
—
—
—
ns
ns
16*
TckH2ioI
Port in hold after CLKOUT (1)
0
—
—
ns
17*
TosH2ioV
OSC1 (Q1 cycle) to Port out valid
—
—
50
150
300
ns
ns
18*
TosH2ioI
OSC1 (Q2 cycle) to Port input invalid (I/O in
hold time)
100
200
—
—
—
—
ns
ns
19*
TioV2osH
Port input valid to OSC1(I/O in setup time)
0
—
—
ns
20*
TioR
Port output rise time
—
—
10
—
40
80
ns
ns
21*
TioF
Port output fall time
—
—
10
—
40
80
ns
ns
22*
Tinp
RB0/INT pin high or low time
25
40
—
—
—
—
ns
ns
Trbp
RB change interrupt high or low time
Tcy
—
—
ns
23*
*
(1)
These parameters are characterized but not tested.
† Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 83
PIC16C55X
FIGURE 10-8:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Timeout
32
OSC
Timeout
Internal
RESET
Watchdog
Timer
RESET
31
34
34
I/O Pins
TABLE 10-3:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER REQUIREMENTS
Param
No.
Sym
Characteristic
Min
Typ†
Max
Units
30
TmcL
MCLR Pulse Width (low)
2000
—
—
ns
-40 to +85C
31
Twdt
Watchdog Timer Timeout Period
(No Prescaler)
7*
18
33*
ms
VDD = 5.0V, -40 to +85C
32
Tost
Oscillation Start-up Timer Period
—
1024
TOSC
—
—
TOSC = OSC1 period
33
Tpwrt
Power-up Timer Period
28*
72
132*
ms
VDD = 5.0V, -40 to +85C
TIOZ
I/O hi-impedance from MCLR low
—
2.0*
s
34
Conditions
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance
only and are not tested.
DS40143E-page 84
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
FIGURE 10-9:
TIMER0 CLOCK TIMING
RA4/T0CKI
41
40
42
TMR0
TABLE 10-4:
TIMER0 CLOCK REQUIREMENTS
Param
No.
Sym
40
Tt0H
T0CKI High Pulse Width
41
Tt0L
T0CKI Low Pulse Width
Characteristic
No Prescaler
Min
Typ†
Max
Units
0.5 TCY + 20*
—
—
ns
With Prescaler
No Prescaler
10*
—
—
ns
0.5 TCY + 20*
—
—
ns
10*
—
—
ns
TCY + 40*
N
—
—
ns
With Prescaler
42
Tt0P
T0CKI Period
Conditions
N = prescale value
(1, 2, 4, ..., 256)
*
These parameters are characterized but not tested.
†
Data in “Typ” column is at 5.0V, 25C unless otherwise stated. These parameters are for design guidance only and are
not tested.
FIGURE 10-10:
LOAD CONDITIONS
Load condition 2
Load condition 1
VDD/2
RL
CL
Pin
CL
Pin
VSS
VSS
RL = 464
CL = 50 pF
15 pF
1996-2013 Microchip Technology Inc.
for all pins except OSC2
for OSC2 output
Preliminary
DS40143E-page 85
PIC16C55X
NOTES:
DS40143E-page 86
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
11.0
PACKAGING INFORMATION
11.1
Package Marking Information
18-Lead PDIP
Example
PIC16C558
-04I / P456
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
28-Lead PDIP
9823 CBA
Example
PIC16C557
-04I / P456
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
20-Lead SSOP
9823 CBA
Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC16C558
-04/SS218
0020 CBP
28-Lead SSOP
Example
PIC16C557
-04I / SS123
XXXXXXXXXXXX
XXXXXXXXXXXX
0025 CBA
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 87
PIC16C55X
Package Marking Information (Cont’d)
18-Lead SOIC (.300”)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC16C558
-04I / S0218
9818 CDK
28-Lead SOIC (.300”)
Example
PIC16C557
-04I / P456
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
YYWWNNN
9823 CBA
18-Lead CERDIP Windowed
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
16C558
/JW
9801 CBA
28-Lead CERDIP Windowed
Example
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
DS40143E-page 88
Preliminary
16C557
/JW
9801 CBA
1996-2013 Microchip Technology Inc.
PIC16C55X
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
2
n
1
E
A2
A
L
c
A1
B1
p
B
eB
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
18
.100
.155
.130
MAX
MILLIMETERS
NOM
18
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
22.61
22.80
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
Molded Package Thickness
A2
.115
.145
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
E1
.240
.250
.260
Overall Length
D
.890
.898
.905
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.045
.058
.070
Lower Lead Width
B
.014
.018
.022
Overall Row Spacing
§
eB
.310
.370
.430
Mold Draft Angle Top
5
10
15
Mold Draft Angle Bottom
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
1996-2013 Microchip Technology Inc.
Preliminary
MAX
4.32
3.68
8.26
6.60
22.99
3.43
0.38
1.78
0.56
10.92
15
15
DS40143E-page 89
PIC16C55X
28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
2
n
1
E
A2
A
L
c
B1
A1
eB
Units
Number of Pins
Pitch
p
B
Dimension Limits
n
p
INCHES*
MIN
NOM
MILLIMETERS
MAX
MIN
NOM
28
MAX
28
2.54
.100
Top to Seating Plane
A
.140
.150
.160
3.56
3.81
4.06
Molded Package Thickness
A2
.125
.130
.135
3.18
3.30
3.43
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.310
.325
7.62
7.87
8.26
Molded Package Width
E1
.275
.285
.295
6.99
7.24
7.49
Overall Length
D
1.345
1.365
1.385
34.16
34.67
35.18
Tip to Seating Plane
L
c
.125
.130
.135
3.18
3.30
3.43
.008
.012
.015
0.20
0.29
0.38
Upper Lead Width
B1
.040
.053
.065
1.02
1.33
1.65
Lower Lead Width
B
.016
.019
.022
0.41
0.48
0.56
eB
.320
.350
.430
8.13
8.89
10.92
5
10
15
5
10
15
5
10
15
5
10
15
Lead Thickness
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
0.38
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-095
Drawing No. C04-070
DS40143E-page 90
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
p
E1
D
2
B
n
1
h
45
c
A2
A
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A2
A1
E
E1
D
h
L
c
B
MIN
.093
.088
.004
.394
.291
.446
.010
.016
0
.009
.014
0
0
A1
INCHES*
NOM
18
.050
.099
.091
.008
.407
.295
.454
.020
.033
4
.011
.017
12
12
MAX
.104
.094
.012
.420
.299
.462
.029
.050
8
.012
.020
15
15
MILLIMETERS
NOM
18
1.27
2.36
2.50
2.24
2.31
0.10
0.20
10.01
10.34
7.39
7.49
11.33
11.53
0.25
0.50
0.41
0.84
0
4
0.23
0.27
0.36
0.42
0
12
0
12
MIN
MAX
2.64
2.39
0.30
10.67
7.59
11.73
0.74
1.27
8
0.30
0.51
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 91
PIC16C55X
28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
D
B
2
1
n
h
45
c
A2
A
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle Top
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A2
A1
E
E1
D
h
L
c
B
A1
MIN
.093
.088
.004
.394
.288
.695
.010
.016
0
.009
.014
0
0
INCHES*
NOM
28
.050
.099
.091
.008
.407
.295
.704
.020
.033
4
.011
.017
12
12
MAX
.104
.094
.012
.420
.299
.712
.029
.050
8
.013
.020
15
15
MILLIMETERS
NOM
28
1.27
2.36
2.50
2.24
2.31
0.10
0.20
10.01
10.34
7.32
7.49
17.65
17.87
0.25
0.50
0.41
0.84
0
4
0.23
0.28
0.36
0.42
0
12
0
12
MIN
MAX
2.64
2.39
0.30
10.67
7.59
18.08
0.74
1.27
8
0.33
0.51
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-052
DS40143E-page 92
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
18-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
W2
2
n
1
W1
E
A2
A
c
L
A1
eB
B1
p
B
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Ceramic Package Height
Standoff
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
§
Window Width
Window Length
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-036
Drawing No. C04-010
1996-2013 Microchip Technology Inc.
A
A2
A1
E
E1
D
L
c
B1
B
eB
W1
W2
MIN
.170
.155
.015
.300
.285
.880
.125
.008
.050
.016
.345
.130
.190
INCHES*
NOM
18
.100
.183
.160
.023
.313
.290
.900
.138
.010
.055
.019
.385
.140
.200
Preliminary
MAX
.195
.165
.030
.325
.295
.920
.150
.012
.060
.021
.425
.150
.210
MILLIMETERS
NOM
18
2.54
4.32
4.64
3.94
4.06
0.38
0.57
7.62
7.94
7.24
7.37
22.35
22.86
3.18
3.49
0.20
0.25
1.27
1.40
0.41
0.47
8.76
9.78
3.30
3.56
4.83
5.08
MIN
MAX
4.95
4.19
0.76
8.26
7.49
23.37
3.81
0.30
1.52
0.53
10.80
3.81
5.33
DS40143E-page 93
PIC16C55X
28-Lead Ceramic Dual In-line with Window (JW) – 300 mil (CERDIP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E1
D
W2
2
n
1
W1
E
A2
A
c
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Top to Seating Plane
Ceramic Package Height
Standoff
Shoulder to Shoulder Width
Ceramic Pkg. Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
Lower Lead Width
Overall Row Spacing
§
Window Width
Window Length
* Controlling Parameter
§ Significant Characteristic
JEDEC Equivalent: MO-058
Drawing No. C04-080
DS40143E-page 94
B1
B
A1
eB
A
A2
A1
E
E1
D
L
c
B1
B
eB
W1
W2
MIN
.170
.155
.015
.300
.285
1.430
.135
.008
.050
.016
.345
.130
.290
INCHES*
NOM
28
.100
.183
.160
.023
.313
.290
1.458
.140
.010
.058
.019
.385
.140
.300
Preliminary
MAX
.195
.165
.030
.325
.295
1.485
.145
.012
.065
.021
.425
.150
.310
p
MILLIMETERS
NOM
28
2.54
4.32
4.64
3.94
4.06
0.38
0.57
7.62
7.94
7.24
7.37
36.32
37.02
3.43
3.56
0.20
0.25
1.27
1.46
0.41
0.47
8.76
9.78
3.30
3.56
7.37
7.62
MIN
MAX
4.95
4.19
0.76
8.26
7.49
37.72
3.68
0.30
1.65
0.53
10.80
3.81
7.87
1996-2013 Microchip Technology Inc.
PIC16C55X
20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
D
B
2
1
n
c
A2
A
L
A1
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Foot Length
Lead Thickness
Foot Angle
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A2
A1
E
E1
D
L
c
B
MIN
.068
.064
.002
.299
.201
.278
.022
.004
0
.010
0
0
INCHES*
NOM
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
.013
5
5
MAX
.078
.072
.010
.322
.212
.289
.037
.010
8
.015
10
10
MILLIMETERS
NOM
20
0.65
1.73
1.85
1.63
1.73
0.05
0.15
7.59
7.85
5.11
5.25
7.06
7.20
0.56
0.75
0.10
0.18
0.00
101.60
0.25
0.32
0
5
0
5
MIN
MAX
1.98
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 95
PIC16C55X
28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
Note:
For the most current package drawings, please see the Microchip Packaging Specification located
at http://www.microchip.com/packaging
E
E1
p
D
B
2
1
n
A
c
A2
A1
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Foot Length
Lead Thickness
Foot Angle
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
* Controlling Parameter
§ Significant Characteristic
A
A2
A1
E
E1
D
L
c
B
MIN
.068
.064
.002
.299
.201
.396
.022
.004
0
.010
0
0
INCHES
NOM
28
.026
.073
.068
.006
.309
.207
.402
.030
.007
4
.013
5
5
MAX
.078
.072
.010
.319
.212
.407
.037
.010
8
.015
10
10
MILLIMETERS*
NOM
MAX
28
0.65
1.73
1.85
1.98
1.63
1.73
1.83
0.05
0.15
0.25
7.59
7.85
8.10
5.11
5.25
5.38
10.06
10.20
10.34
0.56
0.75
0.94
0.10
0.18
0.25
0.00
101.60
203.20
0.25
0.32
0.38
0
5
10
0
5
10
MIN
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-150
Drawing No. C04-073
DS40143E-page 96
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
APPENDIX A:
ENHANCEMENTS
APPENDIX B:
COMPATIBILITY
The following are the list of enhancements over the
PIC16C5X microcontroller family:
To convert code written for PIC16C5X to PIC16C55X,
the user should take the following steps:
1.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
Instruction word length is increased to 14 bits.
This allows larger page sizes both in program
memory (4K now as opposed to 512 before) and
register file (up to 128 bytes now versus 32
bytes before).
A PC high latch register (PCLATH) is added to
handle program memory paging. PA2, PA1, PA0
bits are removed from STATUS register.
Data memory paging is slightly redefined.
STATUS register is modified.
Four new instructions have been added:
RETURN, RETFIE, ADDLW, and SUBLW.
Two instructions TRIS and OPTION are being
phased out although they are kept for
compatibility with PIC16C5X.
OPTION and TRIS registers are made
addressable.
Interrupt capability is added. Interrupt vector is
at 0004h.
Stack size is increased to 8 deep.
RESET vector is changed to 0000h.
RESET of all registers is revised. Three different
RESET (and wake-up) types are recognized.
Registers are reset differently.
Wake-up from SLEEP through interrupt is
added.
Two separate timers, Oscillator Start-up Timer
(OST) and Power-up Timer (PWRT) are
included for more reliable power-up. These
timers are invoked selectively to avoid
unnecessary delays on power-up and wake-up.
PORTB has weak pull-ups and interrupt-onchange feature.
Timer0 clock input, T0CKI pin is also a port pin
(RA4/T0CKI) and has a TRIS bit.
FSR is made a full 8-bit register.
“In-circuit programming” is made possible. The
user can program PIC16C55X devices using
only five pins: VDD, VSS, VPP, RB6 (clock) and
RB7 (data in/out).
PCON status register is added with a Power-on
Reset (POR) status bit.
Code protection scheme is enhanced such that
portions of the program memory can be
protected, while the remainder is unprotected.
PORTA inputs are now Schmitt Trigger inputs.
1996-2013 Microchip Technology Inc.
2.
3.
4.
5.
Remove any program memory page select
operations (PA2, PA1, PA0 bits) for CALL, GOTO.
Revisit any computed jump operations (write to
PC or add to PC, etc.) to make sure page bits
are set properly under the new scheme.
Eliminate any data memory page switching.
Redefine data variables to reallocate them.
Verify all writes to STATUS, OPTION, and FSR
registers since these have changed.
Change RESET vector to 0000h.
APPENDIX C:
REVISION HISTORY
Revision E (January 2013)
Added a note to each package outline drawing.
Preliminary
DS40143E-page 97
PIC16C55X
NOTES:
DS40143E-page 98
Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
INDEX
A
ADDLW Instruction ............................................................. 55
ADDWF Instruction ............................................................. 55
ANDLW Instruction ............................................................. 55
ANDWF Instruction ............................................................. 55
Architectural Overview .......................................................... 9
Assembler
MPASM Assembler ..................................................... 67
B
BCF Instruction ................................................................... 56
Block Diagram
TIMER0....................................................................... 47
TMR0/WDT PRESCALER .......................................... 50
BSF Instruction ................................................................... 56
BTFSC Instruction............................................................... 56
BTFSS Instruction ............................................................... 57
C
CALL Instruction ................................................................. 57
Clocking Scheme/Instruction Cycle .................................... 12
CLRF Instruction ................................................................. 57
CLRW Instruction ................................................................ 58
CLRWDT Instruction ........................................................... 58
Code Protection .................................................................. 46
COMF Instruction ................................................................ 58
Configuration Bits................................................................ 31
D
Data Memory Organization ................................................. 13
DECF Instruction................................................................. 58
DECFSZ Instruction ............................................................ 59
Development Support ......................................................... 67
E
Errata .................................................................................... 3
External Crystal Oscillator Circuit ....................................... 34
G
General purpose Register File ............................................ 13
GOTO Instruction ................................................................ 59
I
I/O Ports .............................................................................. 23
I/O Programming Considerations........................................ 28
ICEPIC In-Circuit Emulator ................................................. 68
ID Locations ........................................................................ 46
INCF Instruction .................................................................. 59
INCFSZ Instruction ............................................................. 60
In-Circuit Serial Programming ............................................. 46
Indirect Addressing, INDF and FSR Registers ................... 21
Instruction Flow/Pipelining .................................................. 12
Instruction Set
ADDLW ....................................................................... 55
ADDWF....................................................................... 55
ANDLW ....................................................................... 55
ANDWF....................................................................... 55
BCF............................................................................. 56
BSF ............................................................................. 56
BTFSC ........................................................................ 56
BTFSS ........................................................................ 57
CALL ........................................................................... 57
CLRF........................................................................... 57
1996-2013 Microchip Technology Inc.
CLRW ......................................................................... 58
CLRWDT .................................................................... 58
COMF ......................................................................... 58
DECF.......................................................................... 58
DECFSZ ..................................................................... 59
GOTO ......................................................................... 59
INCF ........................................................................... 59
INCFSZ....................................................................... 60
IORLW ........................................................................ 60
IORWF........................................................................ 60
MOVF ......................................................................... 61
MOVLW ...................................................................... 60
MOVWF...................................................................... 61
NOP............................................................................ 61
OPTION...................................................................... 61
RETFIE....................................................................... 62
RETLW ....................................................................... 62
RETURN..................................................................... 62
RLF............................................................................. 62
RRF ............................................................................ 63
SLEEP ........................................................................ 63
SUBLW ....................................................................... 63
SUBWF....................................................................... 64
SWAPF ....................................................................... 64
TRIS ........................................................................... 64
XORLW....................................................................... 65
XORWF ...................................................................... 65
Instruction Set Summary .................................................... 53
INT Interrupt ....................................................................... 42
INTCON Register................................................................ 19
Interrupts ............................................................................ 41
IORLW Instruction .............................................................. 60
IORWF Instruction .............................................................. 60
K
KEELOQ Evaluation and Programming Tools...................... 70
M
MOVF Instruction................................................................ 61
MOVLW Instruction............................................................. 60
MOVWF Instruction ............................................................ 61
MPLAB C17 and MPLAB C18 C Compilers ....................... 67
MPLAB ICD In-Circuit Debugger ........................................ 69
MPLAB ICE High Performance Universal In-Circuit Emulator
with MPLAB IDE ................................................................. 68
MPLAB Integrated Development Environment Software.... 67
MPLINK Object Linker/MPLIB Object Librarian .................. 68
N
NOP Instruction .................................................................. 61
O
One-Time-Programmable (OTP) Devices ............................ 7
OPTION Instruction ............................................................ 61
OPTION Register................................................................ 18
Oscillator Configurations..................................................... 33
Oscillator Start-up Timer (OST) .......................................... 36
P
PCL and PCLATH............................................................... 21
PCON Register ................................................................... 20
PICDEM 1 Low Cost PIC MCU Demonstration Board........ 69
PICDEM 17 Demonstration Board...................................... 70
PICDEM 2 Low Cost PIC16CXX Demonstration Board ..... 69
PICDEM 3 Low Cost PIC16CXXX Demonstration Board ... 70
Preliminary
DS40143E-page 99
PIC16C55X
PICSTART Plus Entry Level Development Programmer .... 69
Port RB Interrupt ................................................................. 42
PORTA................................................................................ 23
PORTB.......................................................................... 25, 27
Power Control/Status Register (PCON) .............................. 37
Power-Down Mode (SLEEP)............................................... 45
Power-On Reset (POR) ...................................................... 36
Power-up Timer (PWRT)..................................................... 36
Prescaler ............................................................................. 49
PRO MATE II Universal Device Programmer ..................... 69
Program Memory Organization ........................................... 13
Q
Quick-Turnaround-Production (QTP) Devices ...................... 7
R
RC Oscillator ....................................................................... 34
Reset................................................................................... 35
RETFIE Instruction.............................................................. 62
RETLW Instruction .............................................................. 62
RETURN Instruction............................................................ 62
RLF Instruction.................................................................... 62
RRF Instruction ................................................................... 63
S
Serialized Quick-Turnaround-Production (SQTP) Devices ... 7
SLEEP Instruction ............................................................... 63
Software Simulator (MPLAB SIM)....................................... 68
Special Features of the CPU............................................... 31
Special Function Registers ................................................. 15
Stack ................................................................................... 21
Status Register.................................................................... 17
SUBLW Instruction.............................................................. 63
SUBWF Instruction.............................................................. 64
SWAPF Instruction.............................................................. 64
T
Timer0
TIMER0 ....................................................................... 47
TIMER0 (TMR0) Interrupt ........................................... 47
TIMER0 (TMR0) Module ............................................. 47
TMR0 with External Clock........................................... 49
Timer1
Switching Prescaler Assignment................................. 51
Timing Diagrams and Specifications................................... 81
TMR0 Interrupt .................................................................... 42
TRIS Instruction .................................................................. 64
TRISA.................................................................................. 23
TRISB............................................................................ 25, 27
W
Watchdog Timer (WDT) ...................................................... 43
WWW, On-Line Support........................................................ 3
X
XORLW Instruction ............................................................. 65
XORWF Instruction ............................................................. 65
DS40143E-page 100
Preliminary
1996-2013 Microchip Technology Inc.
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
1996-2013 Microchip Technology Inc.
DS40143E-page 101
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
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RE:
Reader Response
Total Pages Sent ________
From: Name
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City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
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Device:
Literature Number: DS40143E
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS40143E-page 102
1996-2013 Microchip Technology Inc.
PIC16C55X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device
X
Temperature
Range
/XX
XXX
Package
Pattern
Examples:
a)
PIC17C756–16L Commercial Temp.,
PLCC package, 16 MHz,
normal VDD limits
b)
PIC17LC756–08/PT Commercial Temp.,
TQFP package, 8MHz,
extended VDD limits
c)
PIC17C756–33I/PT Industrial Temp.,
TQFP package, 33 MHz,
normal VDD limits
PIC17C756: Standard VDD range
PIC17C756T: (Tape and Reel)
PIC17LC756: Extended VDD range
Temperature Range
I
=
=
0C to +70C
-40C to +85C
Package
CL
PT
L
Pattern
QTP, SQTP, ROM Code (factory specified) or
Special Requirements. Blank for OTP and
Windowed devices.
=
=
=
Windowed LCC
TQFP
PLCC
* JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of
each oscillator type.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
Your local Microchip sales office
The Microchip Worldwide Site (www.microchip.com)
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 103
PIC16C55X
NOTES:
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Preliminary
1996-2013 Microchip Technology Inc.
PIC16C55X
NOTES:
1996-2013 Microchip Technology Inc.
Preliminary
DS40143E-page 105
PIC16C55X
DS40143E-page 106
Preliminary
1996-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 1996-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 9781620769737
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
1996-2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Preliminary
DS40143E-page 107
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-213-7828
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS40143E-page 108
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
11/29/12
Preliminary
1996-2013 Microchip Technology Inc.
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