PIC16LF18455T-I/STX

PIC16(L)F18455/56 28-Pin Full-Featured, Low Pin Count Microcontrollers with XLP Description PIC16(L)F184XX microcontrollers feature Intelligent Analog, Core Independent Peripherals (CIPs) and communication peripherals combined with eXtreme Low-Power (XLP) for a wide range of general purpose and low-power applications. Features such as a 12-bit Analog-to-Digital Converter with Computation (ADC2), Memory Access Partitioning (MAP), the Device Information Area (DIA), Powersaving operating modes, and Peripheral Pin Select (PPS), offer flexible solutions for a wide variety of custom applications. Core Features • • • • • • • • • • • • C Compiler Optimized RISC Architecture Only 50 Instructions Operating Speed: – DC – 32 MHz clock input – 125 ns minimum instruction cycle Interrupt Capability 16-Level Deep Hardware Stack Timers: – Up to two 24-bit timers – Up to four 8-bit timers – Up to four 16-bit timers Low-Current Power-on Reset (POR) Configurable Power-up Timer (PWRT) Brown-out Reset (BOR) Low-Power BOR (LPBOR) Option Windowed Watchdog Timer (WWDT): – Variable prescaler selection – Variable window size selection – Configurable in hardware (Configuration Words) and/or software Programmable Code Protection Memory • • Up to 28 KB Program Flash Memory Up to 2 KB Data SRAM Memory © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 1 PIC16(L)F18455/56 • • • • • 256B Data EEPROM Direct, Indirect and Relative Addressing modes Memory Access Partition (MAP): – Write-protect – Customizable partition Device Information Area (DIA) Device Configuration Information (DCI) Operating Characteristics • • Operating Voltage Range: – 1.8V to 3.6V (PIC16LF184XX) – 2.3V to 5.5V (PIC16F184XX) Temperature Range: – Industrial: -40°C to 85°C – Extended: -40°C to 125°C Power-Saving Operation Modes • • • • • Doze: CPU and Peripherals Running at Different Cycle Rates (typically CPU is lower) Idle: CPU Halted While Peripherals Operate Sleep: Lowest Power Consumption Peripheral Module Disable (PMD): – Ability to selectively disable hardware module to minimize active power consumption of unused peripherals Extreme Low-Power mode (XLP) – Sleep: 500 nA typical @ 1.8V – Sleep and Watchdog Timer: 900 nA typical @ 1.8V eXtreme Low-Power (XLP) Features • • • Sleep mode: 50 nA @ 1.8, typical Watchdog Timer: 500 nA @ 1.8V, typical Secondary Oscillator: 500 nA @ 32 kHz • Operating Current: – 8 uA @ 32 kHz, 1.8V, typical – 32 uA/MHz @ 1.8V, typical Digital Peripherals • • Configurable Logic Cell (CLC): – 4 CLCs – Integrated combinational and sequential logic Complementary Waveform Generator (CWG): – 3 CWGs © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 2 PIC16(L)F18455/56 • • • • • • • • – Rising and falling edge dead-band control – Full-bridge, half-bridge, 1-channel drive – Multiple signal sources Capture/Compare/PWM (CCP) modules: – 5 CCPs – 16-bit resolution for Capture/Compare modes – 10-bit resolution for PWM mode Pulse-Width Modulators (PWM): – 2 10-bit PWMs Numerically Controlled Oscillator (NCO): – Precision linear frequency generator (@50% duty cycle) with 0.0001% step size of source input clock – Input Clock: 0 Hz < fNCO < 32 MHz – Resolution: fNCO/220 Peripheral Pin Select (PPS): – I/O pin remapping of digital peripherals Serial Communications: – EUSART • 2 EUSART(s) • RS-232, RS-485, LIN compatible • Auto-Baud Detect, Auto-wake-up on Start. – Master Synchronous Serial Port (MSSP) • 2 MSSP(s) • SPI ™ • I2C, SMBus and PMBus compatible Data Signal Modulator (DSM): – Modulates a carrier signal with digital data to create custom carrier synchronized output waveforms Up to 26 I/O Pins: – Individually programmable pull-ups – Slew rate control – Interrupt-on-change with edge-select – Input level selection control (ST or TTL) – Digital open-drain enable Timer modules: – Timer0: • 8/16-bit timer/counter • Synchronous or asynchronous operation • Programmable prescaler/postscaler • Time base for capture/compare function – Timer1/3/5 with gate control: • 16-bit timer/counter • Programmable internal or external clock sources • Multiple gate sources © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 3 PIC16(L)F18455/56 – – • Multiple gate modes • Time base for capture/compare function Timer2/4/6 with Hardware Limit Timer: • 8-bit timers • Programmable prescaler/postscaler • Time base for PWM function • Hardware Limit (HLT) and one-shot extensions • Selectable clock sources Signal Measurement Timer (SMT) • 2 SMT(s) • 24-bit timer/counter with programmable prescaler Analog Peripherals • • • • • • Analog-to-Digital Converter with Computation (ADC2): – 12-bit with up to 24 external channels – Conversion available during Sleep – Automated post-processing – Automated math functions on input signals: • Averaging, filter calculations, oversampling and threshold comparison – Integrated charge pump for low-voltage operation – CVD support Zero-Cross Detect (ZCD): – AC high voltage zero-crossing detection for simplifying TRIAC control – Synchronized switching control and timing Temperature Sensor Circuit Comparator: – 2 Comparators – Fixed Voltage Reference at (non)inverting input(s) – Comparator outputs externally accessible Digital-to-Analog Converter (DAC): – 5-bit resolution, rail-to-rail – Positive Reference Selection – Unbuffered I/O pin output – Internal connections to ADCs and comparators Fixed Voltage Reference (FVR) module: – 1.024V, 2.048V and 4.096V output levels Flexible Oscillator Structure • • High-Precision Internal Oscillator: – Software-selectable frequency range up to 32 MHz – ±2% at calibration (nominal) 4x PLL for use with External Sources: – up to 32 MHz (4-8 MHz input) © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 4 PIC16(L)F18455/56 • • • • 2x PLL for use with the HFINTOSC: – up to 32 MHz Low-Power Internal 31 kHz Oscillator (LFINTOSC) External 32.768 kHz Crystal Oscillator (SOCS) External Oscillator Block with: – Three crystal/resonator modes up to 20 MHz – Three external clock modes up to 32 MHz – Fail-Safe Clock Monitor • Detects clock source failure Oscillator Start-up Timer (OST) • Ensures stability of crystal oscillator sources – PIC16(L)F184XX Family Types 2 2 4 1 Y Y Y Y Y Y I PIC16(L)F18456 16384 28 256 2048 26 24 1 2 3 1 4/4 5 2 1 2 2 4 1 Y Y Y Y Y Y I Note:  1. I - Debugging integrated on-chip. 2. One pin is input-only. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 5 Debug(1) DSM Device Information Area CLC Memory Access Partition MSSP (I2C/SPI) Windowed Watchdog Timer EUSART 1 PMD NCO 2 XLP PWM 1 4/4 5 PPS CCP Timers (8/16-bit) CWG 3 Clock Ref Comparators 2 I/O’s(2) PIC16(L)F18455 8192 14 256 1024 26 24 1 Device 5-bit DAC 12-bit ADC2 (ch) Data SRAM (bytes) Data Memory (EEPROM) (bytes) Program Flash Memory (Kbytes) Program Flash Memory (Words) Table 1. Devices Included In This Data Sheet PIC16(L)F18455/56 1 1 4 1 Y Y Y Y Y Y I PIC16(L)F18425 8192 14 256 1024 12 11 1 2 2 1 4/4 4 2 1 1 2 4 1 Y Y Y Y Y Y I PIC16(L)F18426 16384 28 256 2048 12 11 1 2 2 1 4/4 4 2 1 1 2 4 1 Y Y Y Y Y Y I PIC16(L)F18444 4096 7 256 512 18 17 1 2 2 1 4/4 4 2 1 1 1 4 1 Y Y Y Y Y Y I PIC16(L)F18445 8192 14 256 1024 18 17 1 2 2 1 4/4 4 2 1 1 2 4 1 Y Y Y Y Y Y I PIC16(L)F18446 16384 28 256 2048 18 17 1 2 2 1 4/4 4 2 1 1 2 4 1 Y Y Y Y Y Y I Data Sheet Index: 1. 2. 3. DS40002000A, PIC16(L)F18424/44 Data Sheet, 14/20-Pin Full-Featured, Low Pin Count Microcontrollers with XLP DS40002002A, PIC16(L)F18425/45 Data Sheet, 14/20-Pin Full-Featured, Low Pin Count Microcontrollers with XLP DS40001985A, PIC16(L)F18426/46 Data Sheet, 14/20-Pin Full-Featured, Low Pin Count Microcontrollers with XLP Packages SPDIP SOIC SSOP VQFN (4x4) PIC16(L)F18455 ● ● ● ● PIC16(L)F18456 ● ● ● ● Packages Note:  Pin details are subject to change. Important:  For other small form-factor package availability and marking information, visit www.microchip.com/ packaging or contact your local sales office. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 6 Debug(1) DSM Device Information Area CLC Memory Access Partition MSSP (I2C/SPI) Windowed Watchdog Timer EUSART 1 PMD NCO 2 XLP PWM 1 4/4 4 PPS CCP Timers (8/16-bit) CWG 2 Clock Ref Comparators 2 PIC16(L)F18424 4096 I/O’s(2) 7 256 512 12 11 1 Device 5-bit DAC 12-bit ADC2 (ch) Data SRAM (bytes) Data Memory (EEPROM) (bytes) Program Flash Memory (Words) Program Flash Memory (Kbytes) Table 2. Devices Not Included In This Data Sheet PIC16(L)F18455/56 Pin Diagrams Figure 1. 28-pin SPDIP, SSOP, SOIC Rev. 00-000 028A 3/6/201 7 MCLR/VPP /RE3 RA0 RA1 RA2 RA3 RA4 RA5 VSS RA7 RA6 RC0 RC1 RC2 RC3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7/ICSPDAT RB6/ICSPCLK RB6 RB4 RB3 RB2 RB1 RB0 VDD VSS RC7 RC6 RC5 RC4 RA1 RA0 RE3/MCLR/VPP RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 Figure 2. 28-pin VQFN Rev. 00-000028B 6/23/2017 28 27 26 25 24 23 22 RA2 RA3 RA4 RA5 VSS RA7 RA6 1 21 RB3 20 RB2 2 3 19 RB1 18 RB0 4 5 17 VDD 16 VSS 6 7 15 RC7 8 9 10 11 12 13 14 RC0 RC1 RC2 RC3 RC4 RC5 RC6 1 Filename: 00-000028A.vsd Title: 28-pin DIP Last Edit: 3/6/2017 First Used: N/A Notes: Generic 28-pin dual in-line diagram 28-Pin Diagrams Note:  It is recommended that the exposed bottom pad be connected to VSS. Related Links 1 28-Pin Allocation Table © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 7 PIC16(L)F18455/56 Pin Allocation Tables Basic Pull-up Interrupts CLKR CLC EUSART ZCD MSSP CWG PWM CCP Timers DSM DAC NCO Comparator 27 Reference 2 ADC 28-pin VQFN 28-Pin Allocation Table 28-pin SPDIP/SOIC/SSOP I/O 1 C1IN0RA0 ANA0 — — — — — — — — — — — CLCIN0(1) — IOCA0 Y — — — — — — — — — — — CLCIN1(1) — IOCA1 Y — — — — — — — — — — — IOCA2 Y — — C2IN0- C1IN1RA1 3 28 ANA1 — C2IN1- C1IN0+ RA2 4 1 ANA2 ADCVREF- DAC1VREF— DAC1OUT1 C2IN0+ RA3 5 2 ANA3 — DAC1VREF+ MDCARL(1) — — — — — — — — — IOCA3 Y RA4 6 3 ANA4 — — — — T0CKI(1) CCP5IN(1) — — — — — IOCA4 Y — 7 4 ANA5 — — — — — — — — — SS1(1) — RA5 MDCARH(1) MDSRC(1) — — — — IOCA5 Y — RA6 10 7 ANA6 — — — — — — — — — — — — — — IOCA6 Y ADCVREF+ C1IN1+ OSC2 CLKOUT RA7 9 6 ANA7 — — — — — — — — — — — — — — IOCA7 Y OSC1 CLKIN RB0 21 18 ANB0 — RB1 22 19 ANB1 — C2IN1+ — — — — CCP4IN(1) — — — — — — — CWG1IN(1) CWG2IN(1) C1IN3- 23 20 ANB2 — — SCK2(1) ZCD1 — — — IOCB0 Y INT(1) — — — — IOCB1 Y — — — — — IOCB2 Y — SCL2(1,3) C2IN3RB2 — — — — — — — CWG3IN(1) SDI2(1) SDA2(1,3)SS2(1) RB3 24 21 ANB3 — — — — — — — — — — — — — IOCB3 Y — — — — — — — — — IOCB4 Y — CCP3IN(1) — — — — — — — IOCB5 Y — — — — — — — IOCB6 Y C1IN2C2IN2- T5G(1) ANB4 RB4 25 22 RB5 26 23 RB6 27 24 — — — — — ANB5 — — — — — ANB6 — — — — — ADACT(1) SMT2WIN(1) T1G(1) SMT2SIG(1) — CK2(1,3) CLCIN2(1) ICSPCLK ICDCLK RB7 28 25 ANB7 — — — DAC1OUT2 — T6IN(1) RX2(1) — — — — — DT2(1,3) ICSPDAT — — IOCB7 Y ICDDAT T1CKI(1) RC0 11 8 ANC0 — — — — — T3CKI(1) — — — — — — — — IOCC0 Y T3G(1) © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 8 SOSCO Basic Pull-up Interrupts CLKR CLC EUSART ZCD MSSP CWG PWM CCP Timers DSM DAC NCO Comparator Reference ADC 28-pin VQFN 28-pin SPDIP/SOIC/SSOP I/O PIC16(L)F18455/56 SMT1WIN(1) RC1 12 9 ANC1 — — — — — RC2 13 10 ANC2 — — — — — SMT1SIG(1) T5CKI(1) CCP2IN(1) CCP1IN(1) — — — — — — — IOCC1 Y SOSCI — — — — — — — IOCC2 Y — — — — — IOCC3 Y — — — — — IOCC4 Y — SCK1(1) RC3 14 11 ANC3 — — — — — T2IN(1) — — — RC4 15 12 ANC4 — — — — — — — — — RC5 16 13 ANC5 — — — — — T4IN(1) — — — — — — — — IOCC5 Y — RC6 17 14 ANC6 — — — — — — — — — — — — CK1(1,3) — IOCC6 Y — RC7 18 15 ANC7 — — — — — — — — — — — — — IOCC7 Y — RE3 1 — — — — — — — — — — — — — — IOCE3 Y SCL1(1,3) SDI1(1) SDA1(1,3) RX1(1) 26 DT1(1,3) — MCLR VPP VDD 20 17 — — — — — — — — — — — — — — — — — VDD VSS 8 5 — — — — — — — — — — — — — — — — — VSS VSS 19 16 — — — — — — — — — — — — — — — — — VSS CLC1OUT CLKR — — — CLC2OUT — — — — CLC3OUT — — — — — — — — — CWG1A SDO1 — — ADCGRDA — C1OUT NCO1OUT — DSM1OUT TMR0OUT CCP1OUT PWM6OUT CWG2A DT1(3) — SDO2 DT2(3) CWG3A CWG1B SCK1 — — ADCGRDB — C2OUT — — — — CCP2OUT PWM7OUT CWG2B CK1(3) — SCK2 CK2(3) CWG3B OUT(2) CWG1C SCL1(3) — — — — — — — — — CCP3OUT — CWG2C TX1 — TX2 SCL2(3) CWG3C CWG1D SDA1(3) — — — — — — — — — CCP4OUT — CWG2D — — CLC4OUT — — — — — SDA2(3) CWG3D — — — — — — — — — CCP5OUT — — — Note:  1. This is a PPS re-mappable input signal. The input function may be moved from the default location shown to one of several other PORTx pins. 2. All digital output signals shown in these rows are PPS re-mappable. These signals may be mapped to output onto one of several PORTx pin options. 3. This is a bidirectional signal. For normal module operation, the firmware should map this signal to the same pin in both the PPS input and PPS output registers. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 9 PIC16(L)F18455/56 Table of Contents Description.......................................................................................................................1 Core Features..................................................................................................................1 Memory............................................................................................................................1 Operating Characteristics................................................................................................ 2 Power-Saving Operation Modes......................................................................................2 eXtreme Low-Power (XLP) Features...............................................................................2 Digital Peripherals........................................................................................................... 2 Analog Peripherals.......................................................................................................... 4 Flexible Oscillator Structure.............................................................................................4 PIC16(L)F184XX Family Types....................................................................................... 5 Packages.........................................................................................................................6 Pin Diagrams................................................................................................................... 7 1. 28-Pin Diagrams...........................................................................................................................7 Pin Allocation Tables....................................................................................................... 8 1. 28-Pin Allocation Table.................................................................................................................8 1. Device Overview......................................................................................................20 1.1. 1.2. 1.3. 1.4. New Core Features.................................................................................................................... 20 Other Special Features.............................................................................................................. 21 Details on Individual Family Members........................................................................................21 Register and Bit Naming Conventions....................................................................................... 23 2. Guidelines for Getting Started with PIC16(L)F18455/56 Microcontrollers...............26 2.1. 2.2. Basic Connection Requirements................................................................................................ 26 Power Supply Pins..................................................................................................................... 26 2.3. 2.4. 2.5. 2.6. Master Clear (MCLR) Pin........................................................................................................... 27 In-Circuit Serial Programming™ ICSP™ Pins.............................................................................28 External Oscillator Pins.............................................................................................................. 28 Unused I/Os............................................................................................................................... 30 3. Enhanced Mid-Range CPU..................................................................................... 31 3.1. 3.2. 3.3. Automatic Interrupt Context Saving............................................................................................31 16-Level Stack with Overflow and Underflow.............................................................................32 File Select Registers.................................................................................................................. 32 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 10 PIC16(L)F18455/56 3.4. Instruction Set............................................................................................................................ 32 4. Device Configuration............................................................................................... 33 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. 4.9. Configuration Words...................................................................................................................33 Code Protection..........................................................................................................................33 Write Protection..........................................................................................................................33 User ID....................................................................................................................................... 33 Device ID and Revision ID......................................................................................................... 34 Register Summary - Configuration Words..................................................................................34 Register Definitions: Configuration Words................................................................................. 34 Register Summary - Device and Revision..................................................................................43 Register Definitions: Device and Revision................................................................................. 43 5. Device Information Area.......................................................................................... 46 5.1. 5.2. 5.3. 5.4. Microchip Unique Identifier (MUI)...............................................................................................47 External Unique Identifier (EUI)..................................................................................................47 Analog-to-Digital Conversion Data of the Temperature Sensor................................................. 48 Fixed Voltage Reference Data................................................................................................... 48 6. Device Configuration Information............................................................................ 49 6.1. DIA and DCI Access...................................................................................................................49 7. Memory Organization.............................................................................................. 50 7.1. 7.2. 7.3. 7.4. 7.5. 7.6. 7.7. 7.8. 7.9. 7.10. Program Memory Organization.................................................................................................. 50 Memory Access Partition (MAP)................................................................................................ 52 Data Memory Organization........................................................................................................ 54 PCL and PCLATH...................................................................................................................... 57 Stack.......................................................................................................................................... 59 Indirect Addressing.....................................................................................................................62 Register Summary - Memory and Status................................................................................... 65 Register Definitions: Memory and Status................................................................................... 66 Register Summary: Shadow Registers...................................................................................... 80 Register Definitions: Shadow Registers..................................................................................... 80 8. Resets..................................................................................................................... 87 8.1. 8.2. 8.3. 8.4. 8.5. 8.6. Power-on Reset (POR).............................................................................................................. 88 Brown-out Reset (BOR)............................................................................................................. 88 Low-Power Brown-out Reset (LPBOR)...................................................................................... 89 MCLR Reset...............................................................................................................................90 Windowed Watchdog Timer (WWDT) Reset.............................................................................. 91 8.7. 8.8. 8.9. 8.10. 8.11. 8.12. 8.13. Stack Overflow/Underflow Reset................................................................................................91 Programming Mode Exit.............................................................................................................91 Power-up Timer (PWRT)............................................................................................................ 92 Start-up Sequence..................................................................................................................... 92 Memory Execution Violation.......................................................................................................93 Determining the Cause of a Reset............................................................................................. 94 Power Control (PCONx) Register...............................................................................................95 RESET Instruction......................................................................................................................91 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 11 PIC16(L)F18455/56 8.14. Register Summary - BOR Control and Power Control............................................................... 96 8.15. Register Definitions: Power Control........................................................................................... 96 9. Oscillator Module (with Fail-Safe Clock Monitor)...................................................101 9.1. 9.2. 9.3. 9.4. 9.5. 9.6. Overview.................................................................................................................................. 101 Clock Source Types................................................................................................................. 102 Clock Switching........................................................................................................................ 108 Fail-Safe Clock Monitor.............................................................................................................111 Register Summary - OSC.........................................................................................................113 Register Definitions: Oscillator Control.....................................................................................113 10. Interrupts............................................................................................................... 124 10.1. 10.2. 10.3. 10.4. 10.5. 10.6. 10.7. Operation..................................................................................................................................124 Interrupt Latency...................................................................................................................... 125 Interrupts During Sleep............................................................................................................ 126 INT Pin..................................................................................................................................... 126 Automatic Context Saving........................................................................................................ 127 Register Summary - Interrupt Control...................................................................................... 128 Register Definitions: Interrupt Control...................................................................................... 128 11. Power-Saving Operation Modes............................................................................152 11.1. 11.2. 11.3. 11.4. 11.5. Doze Mode............................................................................................................................... 152 Sleep Mode.............................................................................................................................. 153 Idle Mode..................................................................................................................................156 Register Summary - Power Savings Control............................................................................158 Register Definitions: Power Savings Control............................................................................158 12. (WWDT) Windowed Watchdog Timer....................................................................162 12.1. 12.2. 12.3. 12.4. 12.5. 12.6. 12.7. 12.8. Independent Clock Source....................................................................................................... 163 WWDT Operating Modes......................................................................................................... 164 Time-out Period........................................................................................................................164 Watchdog Window....................................................................................................................164 Clearing the WWDT................................................................................................................. 165 Operation During Sleep............................................................................................................165 Register Summary - WDT Control............................................................................................167 Register Definitions: Windowed Watchdog Timer Control........................................................167 13. (NVM) Nonvolatile Memory Control.......................................................................174 13.1. 13.2. 13.3. 13.4. 13.5. 13.6. Program Flash Memory............................................................................................................174 Data EEPROM......................................................................................................................... 175 FSR and INDF Access............................................................................................................. 175 NVMREG Access..................................................................................................................... 176 Register Summary: NVM Control............................................................................................. 190 Register Definitions: Nonvolatile Memory................................................................................ 190 14. I/O Ports................................................................................................................ 196 14.1. PORT Availability......................................................................................................................196 14.2. I/O Ports Description................................................................................................................ 196 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 12 PIC16(L)F18455/56 14.3. 14.4. 14.5. 14.6. 14.7. I/O Priorities..............................................................................................................................197 PORTx Registers..................................................................................................................... 198 PORTE Registers.....................................................................................................................200 Register Summary - Input/Output.............................................................................................201 Register Definitions: Port Control............................................................................................. 202 15. (PPS) Peripheral Pin Select Module......................................................................230 15.1. 15.2. 15.3. 15.4. 15.5. 15.6. 15.7. 15.8. 15.9. PPS Inputs............................................................................................................................... 230 PPS Outputs.............................................................................................................................232 Bidirectional Pins......................................................................................................................234 PPS Lock..................................................................................................................................234 PPS Permanent Lock............................................................................................................... 235 Operation During Sleep............................................................................................................235 Effects of a Reset..................................................................................................................... 235 Register Summary - PPS......................................................................................................... 236 Register Definitions: PPS Input and Output Selection............................................................. 238 16. (PMD) Peripheral Module Disable......................................................................... 242 16.1. 16.2. 16.3. 16.4. 16.5. Disabling a Module...................................................................................................................242 Enabling a Module....................................................................................................................242 System Clock Disable.............................................................................................................. 242 Register Summary - PMD........................................................................................................ 243 Register Definitions: Peripheral Module Disable...................................................................... 243 17. Interrupt-on-Change.............................................................................................. 253 17.1. 17.2. 17.3. 17.4. 17.5. 17.6. Enabling the Module.................................................................................................................253 Individual Pin Configuration......................................................................................................254 Interrupt Flags.......................................................................................................................... 254 Operation in Sleep....................................................................................................................254 Register Summary - Interrupt-on-Change................................................................................ 255 Register Definitions: Interrupt-on-Change Control................................................................... 255 18. (FVR) Fixed Voltage Reference.............................................................................268 18.1. 18.2. 18.3. 18.4. Independent Gain Amplifiers.................................................................................................... 268 FVR Stabilization Period.......................................................................................................... 268 Register Summary - FVR ........................................................................................................ 270 Register Definitions: FVR Control............................................................................................ 270 19. Temperature Indicator Module...............................................................................273 19.1. 19.2. 19.3. 19.4. 19.5. Module Operation.....................................................................................................................273 Minimum Operating VDD...........................................................................................................274 Temperature Indicator Range...................................................................................................274 Estimation of Temperature....................................................................................................... 274 ADC Acquisition Time...............................................................................................................275 20. (ADC2) Analog-to-Digital Converter with Computation Module............................. 276 20.1. ADC Configuration................................................................................................................... 277 20.2. ADC Operation......................................................................................................................... 282 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 13 PIC16(L)F18455/56 20.3. 20.4. 20.5. 20.6. 20.7. 20.8. ADC Acquisition Requirements................................................................................................ 286 ADC Charge Pump...................................................................................................................289 Capacitive Voltage Divider (CVD) Features............................................................................. 289 Computation Operation............................................................................................................ 293 Register Summary - ADC Control............................................................................................ 299 Register Definitions: ADC Control............................................................................................ 300 21. (DAC) 5-Bit Digital-to-Analog Converter Module................................................... 324 21.1. 21.2. 21.3. 21.4. 21.5. 21.6. 21.7. Output Voltage Selection..........................................................................................................325 Ratiometric Output Level..........................................................................................................326 DAC Voltage Reference Output............................................................................................... 326 Operation During Sleep............................................................................................................326 Effects of a Reset..................................................................................................................... 326 Register Summary - DAC Control............................................................................................ 327 Register Definitions: DAC Control............................................................................................ 327 22. Numerically Controlled Oscillator (NCO) Module.................................................. 330 22.1. 22.2. 22.3. 22.4. 22.5. 22.6. 22.7. 22.8. 22.9. NCO Operation.........................................................................................................................331 Fixed Duty Cycle Mode............................................................................................................ 332 Pulse Frequency Mode............................................................................................................ 333 Output Polarity Control............................................................................................................. 334 Interrupts.................................................................................................................................. 334 Effects of a Reset..................................................................................................................... 334 Operation in Sleep....................................................................................................................334 Register Summary - NCO........................................................................................................ 335 Register Definitions: NCO........................................................................................................ 335 23. (CMP) Comparator Module................................................................................... 340 23.1. Comparator Overview.............................................................................................................. 340 23.2. Comparator Control..................................................................................................................341 23.3. Comparator Hysteresis.............................................................................................................342 23.4. Operation With Timer1 Gate.....................................................................................................342 23.5. Comparator Interrupt................................................................................................................ 343 23.6. Comparator Positive Input Selection........................................................................................ 343 23.7. Comparator Negative Input Selection...................................................................................... 344 23.8. Comparator Response Time.................................................................................................... 345 23.9. Analog Input Connection Considerations................................................................................. 345 23.10. CWG1 Auto-Shutdown Source................................................................................................ 346 23.11. ADC Auto-Trigger Source.........................................................................................................346 23.12. Even Numbered Timers Reset.................................................................................................346 23.13. Operation in Sleep Mode......................................................................................................... 346 23.14. Register Summary - Comparator............................................................................................. 347 23.15. Register Definitions: Comparator Control................................................................................ 347 24. (ZCD) Zero-Cross Detection Module.....................................................................353 24.1. External Resistor Selection...................................................................................................... 354 24.2. ZCD Logic Output.....................................................................................................................354 24.3. ZCD Logic Polarity................................................................................................................... 354 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 14 PIC16(L)F18455/56 24.4. ZCD Interrupts..........................................................................................................................355 24.5. Correction for ZCPINV Offset......................................................................................................355 24.6. Handling VPEAK Variations........................................................................................................357 24.7. Operation During Sleep............................................................................................................358 24.8. Effects of a Reset..................................................................................................................... 358 24.9. Disabling the ZCD Module....................................................................................................... 358 24.10. Register Summary: ZCD Control............................................................................................. 359 24.11. Register Definitions: ZCD Control............................................................................................ 359 25. Timer0 Module.......................................................................................................361 25.1. 25.2. 25.3. 25.4. 25.5. 25.6. Timer0 Operation......................................................................................................................362 Clock Selection.........................................................................................................................362 Timer0 Output and Interrupt..................................................................................................... 363 Operation During Sleep............................................................................................................364 Register Summary - Timer0..................................................................................................... 365 Register Definitions: Timer0 Control.........................................................................................365 26. Timer1 Module with Gate Control.......................................................................... 370 26.1. Timer1 Operation......................................................................................................................371 26.2. Clock Source Selection............................................................................................................ 372 26.3. Timer1 Prescaler...................................................................................................................... 373 26.4. Secondary Oscillator................................................................................................................ 373 26.5. Timer1 Operation in Asynchronous Counter Mode.................................................................. 374 26.6. Timer1 16-Bit Read/Write Mode............................................................................................... 374 26.7. Timer1 Gate..............................................................................................................................375 26.8. Timer1 Interrupt........................................................................................................................380 26.9. Timer1 Operation During Sleep................................................................................................381 26.10. CCP Capture/Compare Time Base..........................................................................................381 26.11. CCP Special Event Trigger.......................................................................................................382 26.12. Peripheral Module Disable....................................................................................................... 382 26.13. Register Summary - Timer1 .................................................................................................... 383 26.14. Register Definitions: Timer1.....................................................................................................383 27. Timer2 Module.......................................................................................................390 27.1. 27.2. 27.3. 27.4. 27.5. 27.6. 27.7. 27.8. 27.9. Timer2 Operation......................................................................................................................392 Timer2 Output...........................................................................................................................393 External Reset Sources............................................................................................................393 Timer2 Interrupt........................................................................................................................ 394 Operating Modes......................................................................................................................395 Operation Examples.................................................................................................................397 Timer2 Operation During Sleep................................................................................................407 Register Summary - Timer2..................................................................................................... 408 Register Definitions: Timer2 Control.........................................................................................408 28. CCP/PWM Timer Resource Selection................................................................... 417 28.1. Register Summary - Timer Selection Registers for CCP/PWM................................................418 28.2. Register Definitions: CCP/PWM Timer Selection..................................................................... 418 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 15 PIC16(L)F18455/56 29. Capture/Compare/PWM Module........................................................................... 421 29.1. 29.2. 29.3. 29.4. 29.5. 29.6. CCP Module Configuration.......................................................................................................421 Capture Mode...........................................................................................................................422 Compare Mode.........................................................................................................................424 PWM Overview.........................................................................................................................426 Register Summary - CCP Control............................................................................................ 431 Register Definitions: CCP Control............................................................................................ 431 30. (PWM) Pulse-Width Modulation............................................................................ 436 30.1. Fundamental Operation............................................................................................................437 30.2. PWM Output Polarity................................................................................................................437 30.3. PWM Period............................................................................................................................. 437 30.4. PWM Duty Cycle...................................................................................................................... 438 30.5. PWM Resolution.......................................................................................................................438 30.6. Operation in Sleep Mode..........................................................................................................439 30.7. Changes in System Clock Frequency...................................................................................... 439 30.8. Effects of Reset........................................................................................................................ 439 30.9. Setup for PWM Operation using PWMx Output Pins............................................................... 439 30.10. Setup for PWM Operation to Other Device Peripherals...........................................................440 30.11. Register Summary - Registers Associated with PWM............................................................. 441 30.12. Register Definitions: PWM Control...........................................................................................441 31. (CWG) Complementary Waveform Generator Module..........................................444 31.1. Fundamental Operation............................................................................................................444 31.2. Operating Modes......................................................................................................................444 31.3. Start-up Considerations............................................................................................................456 31.4. Clock Source............................................................................................................................ 456 31.5. Selectable Input Sources......................................................................................................... 456 31.6. Output Control.......................................................................................................................... 457 31.7. Dead-Band Control...................................................................................................................457 31.8. Rising Edge and Reverse Dead Band......................................................................................457 31.9. Falling Edge and Forward Dead Band..................................................................................... 458 31.10. Dead-Band Jitter...................................................................................................................... 459 31.11. Auto-Shutdown.........................................................................................................................459 31.12. Operation During Sleep............................................................................................................462 31.13. Configuring the CWG............................................................................................................... 462 31.14. Register Summary - CWG Control...........................................................................................464 31.15. Register Definitions: CWG Control...........................................................................................464 32. (DSM) Data Signal Modulator Module...................................................................475 32.1. 32.2. 32.3. 32.4. 32.5. 32.6. 32.7. DSM Operation.........................................................................................................................476 Modulator Signal Sources........................................................................................................ 476 Carrier Signal Sources............................................................................................................. 477 Carrier Synchronization............................................................................................................479 Carrier Source Polarity Select.................................................................................................. 481 Programmable Modulator Data................................................................................................ 481 Modulated Output Polarity........................................................................................................481 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 16 PIC16(L)F18455/56 32.8. Operation in Sleep Mode..........................................................................................................481 32.9. Effects of a Reset..................................................................................................................... 481 32.10. Peripheral Module Disable....................................................................................................... 481 32.11. Register Summary - DSM........................................................................................................ 482 32.12. Register Definitions: Modulation Control..................................................................................482 33. (CLC) Configurable Logic Cell...............................................................................488 33.1. 33.2. 33.3. 33.4. 33.5. 33.6. 33.7. 33.8. CLC Setup................................................................................................................................489 CLC Interrupts.......................................................................................................................... 494 Output Mirror Copies................................................................................................................ 495 Effects of a Reset..................................................................................................................... 495 Operation During Sleep............................................................................................................495 CLC Setup Steps......................................................................................................................496 Register Summary - CLC Control.............................................................................................497 Register Definitions: Configurable Logic Cell........................................................................... 498 34. Reference Clock Output Module........................................................................... 510 34.1. 34.2. 34.3. 34.4. 34.5. 34.6. Clock Source............................................................................................................................ 511 Programmable Clock Divider....................................................................................................511 Selectable Duty Cycle.............................................................................................................. 512 Operation in Sleep Mode..........................................................................................................512 Register Summary: Reference CLK......................................................................................... 513 Register Definitions: Reference Clock......................................................................................513 35. (MSSP) Master Synchronous Serial Port Module................................................. 516 35.1. 35.2. 35.3. 35.4. 35.5. 35.6. 35.7. 35.8. 35.9. SPI Mode Overview..................................................................................................................516 SPI Mode Operation.................................................................................................................518 I2C Mode Overview.................................................................................................................. 526 I2C Mode Operation................................................................................................................. 530 I2C Slave Mode Operation....................................................................................................... 534 I2C Master Mode...................................................................................................................... 553 Baud Rate Generator............................................................................................................... 567 Register Summary: MSSP Control...........................................................................................569 Register Definitions: MSSP Control......................................................................................... 569 36. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver Transmitter ...............................................................................................................................581 36.1. 36.2. 36.3. 36.4. 36.5. 36.6. EUSART Asynchronous Mode................................................................................................. 583 EUSART Baud Rate Generator (BRG).................................................................................... 590 EUSART Synchronous Mode...................................................................................................598 EUSART Operation During Sleep............................................................................................ 604 Register Summary - EUSART .................................................................................................606 Register Definitions: EUSART Control..................................................................................... 606 37. (SMT) Signal Measurement Timer.........................................................................616 37.1. SMT Operation......................................................................................................................... 616 37.2. Register Summary - SMT Control............................................................................................ 630 37.3. Register Definitions: SMT Control............................................................................................ 630 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 17 PIC16(L)F18455/56 38. Register Summary.................................................................................................643 39. In-Circuit Serial Programming™ (ICSP™) .............................................................675 39.1. High-Voltage Programming Entry Mode...................................................................................675 39.2. Low-Voltage Programming Entry Mode....................................................................................675 39.3. Common Programming Interfaces........................................................................................... 675 40. Instruction Set Summary....................................................................................... 678 40.1. Read-Modify-Write Operations.................................................................................................678 40.2. Standard Instruction Set...........................................................................................................679 41. Development Support............................................................................................701 41.1. MPLAB X Integrated Development Environment Software...................................................... 701 41.2. MPLAB XC Compilers.............................................................................................................. 702 41.3. MPASM Assembler.................................................................................................................. 702 41.4. MPLINK Object Linker/MPLIB Object Librarian........................................................................703 41.5. MPLAB Assembler, Linker and Librarian for Various Device Families..................................... 703 41.6. MPLAB X SIM Software Simulator........................................................................................... 703 41.7. MPLAB REAL ICE In-Circuit Emulator System........................................................................ 704 41.8. MPLAB ICD 3 In-Circuit Debugger System..............................................................................704 41.9. PICkit 3 In-Circuit Debugger/Programmer................................................................................704 41.10. MPLAB PM3 Device Programmer............................................................................................704 41.11. Demonstration/Development Boards, Evaluation Kits, and Starter Kits...................................704 41.12. Third-Party Development Tools................................................................................................705 42. Electrical Specifications.........................................................................................706 42.1. 42.2. 42.3. 42.4. Absolute Maximum Ratings(†).................................................................................................. 706 Standard Operating Conditions................................................................................................ 706 DC Characteristics................................................................................................................... 708 AC Characteristics....................................................................................................................719 43. DC and AC Characteristics Graphs and Tables.................................................... 742 43.1. Graphs......................................................................................................................................743 44. Packaging Information...........................................................................................744 44.1. Package Details....................................................................................................................... 745 45. Revision History.....................................................................................................755 The Microchip Web Site.............................................................................................. 756 Customer Change Notification Service........................................................................756 Customer Support....................................................................................................... 756 Product Identification System...................................................................................... 757 Microchip Devices Code Protection Feature............................................................... 757 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 18 PIC16(L)F18455/56 Legal Notice.................................................................................................................758 Trademarks................................................................................................................. 758 Quality Management System Certified by DNV...........................................................759 Worldwide Sales and Service......................................................................................760 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 19 PIC16(L)F18455/56 Device Overview 1. Device Overview This document contains device-specific information for the following devices: • PIC16F18455 • PIC16LF18455 • PIC16F18456 • PIC16LF18456 1.1 New Core Features 1.1.1 XLP Technology All of the devices in the PIC16(L)F184XX family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • • • • 1.1.2 Alternate Run Modes: By clocking the controller from the secondary oscillator or the internal oscillator block, power consumption during code execution can be reduced by as much as 90%. Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operation requirements. On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the user to incorporate power-saving ideas into their application’s software design. Peripheral Module Disable: Modules that are not being used in the code can be selectively disabled using the PMD module. This further reduces the power consumption. Multiple Oscillator Options and Features All of the devices in the PIC16(L)F184XX family offer several different oscillator options. The PIC16(L)F184XX family can be clocked from several different sources: • • • • • • HFINTOSC – 1-32 MHz precision digitally controlled internal oscillator LFINTOSC – 31 kHz internal oscillator EXTOSC – External clock (EC) – Low-power oscillator (LP) – Medium-power oscillator (XT) – High-power oscillator (HS) SOSC – Secondary oscillator circuit optimized for 32 kHz clock crystals A Phase Lock Loop (PLL) frequency multiplier (2x/4x) is available to the External Oscillator modes enabling clock speeds of up to 32 MHz Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the LFINTOSC. If a clock failure occurs, the controller is switched to the internal oscillator block, allowing for continued operation or a safe application shutdown. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 20 PIC16(L)F18455/56 Device Overview 1.2 Other Special Features • • • • • 1.3 12-bit A/D Converter with Computation: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period and thus, reduce code overhead. It has a new module called ADC2 with computation features, which provides a digital filter and threshold interrupt functions. Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 10K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. Self-programmability: These devices can write to their own program memory spaces under internal software control. By using a boot loader routine located in the protected Boot Block at the top of program memory, it becomes possible to create an application that can update itself in the field. Enhanced Peripheral Pin Select: The Peripheral Pin Select (PPS) module connects peripheral inputs and outputs to the device I/O pins. Only digital signals are included in the selections. All analog inputs and outputs remain fixed to their assigned pins. Windowed Watchdog Timer (WWDT): – Timer monitoring of overflow and underflow events – Variable prescaler selection – Variable window size selection – All sources configurable in hardware or software Details on Individual Family Members The devices of the PIC16(L)F184XX family described in the current datasheet are available in 28-pin packages. The block diagram for this device is shown in Figure 1-1. The devices have the following differences: 1. 2. 3. 4. 5. 6. 7. Program Flash Memory Data Memory SRAM Data Memory EEPROM A/D channels I/O ports Enhanced USART Input Voltage Range/Power Consumption All other features for devices in this family are identical. These are summarized in the following Device Features table. The pinouts for all devices are listed in the pin summary tables. Table 1-1. Device Features Features PIC16(L)F18455 PIC16(L)F18456 14 28 Program Memory (Instructions) 8192 16384 Data Memory (Bytes) 1024 2048 Data EEPROM Memory (Bytes) 256 256 Program Memory (KBytes) © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 21 PIC16(L)F18455/56 Device Overview Features PIC16(L)F18455 PIC16(L)F18456 28 - SPDIP 28 - SPDIP 28 - SSOP 28 - SSOP 28 - SOIC (7.5 mm) 28 - SOIC (7.5 mm) 28 - vQFN (4x4) 28 - vQFN (4x4) A, B, C A, B, C Capture/Compare/PWM Modules (CCP) 5 5 Configurable Logic Cell (CLC) 4 4 10-Bit Pulse-Width Modulator (PWM) 2 2 12-Bit Analog-to-Digital Module (ADC2) with Computation Accelerator 24 channels 24 channels 5-Bit Digital-to-Analog Module (DAC) 1 1 Comparators 2 2 Numerical Contolled Oscillator (NCO) 1 1 Interrupt Sources 47 47 Timers (16-/8-bit) 4 4 2 MSSP 2 MSSP 2 EUSART 2 EUSART Complementary Waveform Generator (CWG) 3 3 Zero-Cross Detect (ZCD) 1 1 Data Signal Modulator (DSM) 1 1 Reference Clock Output Module 1 1 Peripheral Pin Select (PPS) YES YES Peripheral Module Disable (PMD) YES YES Programmable Brown-out Reset (BOR) YES YES POR, BOR, RESET Instruction, Stack Overflow, Stack Underflow (PWRT, OST), MCLR, WDT POR, BOR, RESET Instruction, Stack Overflow, Stack Underflow (PWRT, OST), MCLR, WDT 50 instructions 50 instructions Packages I/O Ports Serial Communications Resets (and Delays) Instruction Set © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 22 PIC16(L)F18455/56 Device Overview Features Filename: Title: Last Edit: First Used: Notes: 10-000039AA.vsd 7/7/2017 PIC16(L)F18455 PIC16(L)F18456 16-levels hardware stack 16-levels hardware stack DC – 32 MHz DC – 32 MHz Operating Frequency Figure 1-1. PIC16(L)F18455/56 Device Block Diagram Program Flash Memory Rev. 10-000039A 7/7/2017 RAM PORTA Timing Generation CLKOUT/OSC2 PORTB EXTOSC Oscillator CLKIN/OSC1 PORTC CPU PORTE Secondary Oscillator (SOSC) SOSCI SOSCO MCLR WDT Temp Indicator CWG3 NCO1 CWG2 PWM7 CWG1 PWM6 SMT2 Timer6 SMT1 Timer5 Timer4 EUSART2 EUSART1 MSSP2 Timer3 MSSP1 Timer2 Timer1 CLC4 CLC3 Timer0 CLC2 C2 C1 CLC1 CCP5 ADC2 12-bit CCP4 DAC1 CCP3 FVR CCP2 CCP1 Note:  1. See applicable chapters for more information on peripherals. 1.4 Register and Bit Naming Conventions 1.4.1 Register Names When there are multiple instances of the same peripheral in a device, the Peripheral Control registers will be depicted as the concatenation of a peripheral identifier, peripheral instance, and control identifier. The control registers section will show just one instance of all the register names with an ‘x’ in the place of the peripheral instance number. This naming convention may also be applied to peripherals when there is only one instance of that peripheral in the device to maintain compatibility with other devices in the family that contain more than one. 1.4.2 Bit Names There are two variants for bit names: • • 1.4.2.1 Short name: Bit function abbreviation Long name: Peripheral abbreviation and short name Short Bit Names Short bit names are an abbreviation for the bit function. For example, some peripherals are enabled with the EN bit. The bit names shown in the registers are the short name variant. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 23 PIC16(L)F18455/56 Device Overview Short bit names are useful when accessing bits in C programs. The general format for accessing bits by the short name is RegisterNamebits.ShortName. For example, the enable bit, EN, in the CM1CON0 register can be set in C programs with the instruction CM1CON0bits.EN = 1. Short names are generally not useful in assembly programs because the same name may be used by different peripherals in different bit positions. When this occurs, during the include file generation, all instances of that short bit name are appended with an underscore plus the name of the register in which the bit resides to avoid naming contentions. 1.4.2.2 Long Bit Names Long bit names are constructed by adding a peripheral abbreviation prefix to the short name. The prefix is unique to the peripheral, thereby making every long bit name unique. The long bit name for the COG1 enable bit is the COG1 prefix, G1, appended with the enable bit short name, EN, resulting in the unique bit name G1EN. Long bit names are useful in both C and assembly programs. For example, in C the COG1CON0 enable bit can be set with the G1EN = 1 instruction. In assembly, this bit can be set with the BSF COG1CON0,G1EN instruction. 1.4.2.3 Bit Fields Bit fields are two or more adjacent bits in the same register. Bit fields adhere only to the short bit naming convention. For example, the three Least Significant bits of the COG1CON0 register contain the mode control bits. The short name for this field is MD. There is no long bit name variant. Bit field access is only possible in C programs. The following example demonstrates a C program instruction for setting the COG1 to the Push-Pull mode: COG1CON0bits.MD = 0x5; Individual bits in a bit field can also be accessed with long and short bit names. Each bit is the field name appended with the number of the bit position within the field. For example, the Most Significant mode bit has the short bit name MD2 and the long bit name is G1MD2. The following two examples demonstrate assembly program sequences for setting the COG1 to Push-Pull mode: Example 1: MOVLW ANDWF MOVLW IORWF ~(1UTH Interrupt if ERR≤UTH Interrupt if ERRUTH Interrupt if ERR>LTH and ERR CxVN CxVP < CxVN CxVP < CxVN CxVP > CxVN Bit 4 – POL Comparator Output Polarity Select bit Value 1 0 Description Comparator output is inverted Comparator output is not inverted Bit 1 – HYS Comparator Hysteresis Enable bit Value 1 0 Description Comparator hysteresis enabled Comparator hysteresis disabled Bit 0 – SYNC Comparator Output Synchronous Mode bit Output updated on the falling edge of prescaled Timer1 clock. Value 1 0 Description Comparator output to Timer1 and I/O pin is synchronous to changes on the prescaled Timer1 clock. Comparator output to Timer1 and I/O pin is asynchronous © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 348 PIC16(L)F18455/56 (CMP) Comparator Module 23.15.2 CMxCON1 Name:  CMxCON1 Address:  0x991,0x995 Comparator x Control Register 1 Bit 7 6 5 4 3 Access Reset 2 1 0 INTP INTN R/W R/W 0 0 Bit 1 – INTP Comparator Interrupt on Positive-Going Edge Enable bit Value 1 0 Description The CxIF interrupt flag will be set upon a positive-going edge of the CxOUT bit No interrupt flag will be set on a positive-going edge of the CxOUT bit Bit 0 – INTN Comparator Interrupt on Negative-Going Edge Enable bit Value 1 0 Description The CxIF interrupt flag will be set upon a negative-going edge of the CxOUT bit No interrupt flag will be set on a negative-going edge of the CxOUT bit © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 349 PIC16(L)F18455/56 (CMP) Comparator Module 23.15.3 CMxNCH Name:  CMxNCH Address:  0x992,0x996 Comparator x Inverting Channel Select Register Bit 7 6 5 4 3 2 1 0 NCH[2:0] Access Reset R/W R/W R/W 0 0 0 Bits 2:0 – NCH[2:0] Comparator Inverting Input Channel Select bits NCH Negative Input Sources 111 CxVN connects to AVSS 110 CxVN connects to FVR Buffer 2 101 CxVN not connected 100 CxVN not connected 011 CxVN connects to CxIN3- pin 010 CxVN connects to CxIN2- pin 001 CxVN connects to CxIN1- pin 000 CxVN connects to CxIN0- pin © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 350 PIC16(L)F18455/56 (CMP) Comparator Module 23.15.4 CMxPCH Name:  CMxPCH Address:  0x993,0x997 Comparator x Non-Inverting Channel Select Register PCH Bit Positive Input Source 111 CxVP connects to VSS 110 CxVP connects to FVR Buffer 2 101 CxVP connects to DAC1 output 100 CxVP not connected 011 CxVP not connected 010 CxVP not connected 001 CxVP connects to CxIN1+ pin 000 CxVP connects to CxIN0+ pin 7 6 5 4 3 2 1 0 PCH[2:0] Access Reset R/W R/W R/W 0 0 0 Bits 2:0 – PCH[2:0] Comparator Non-Inverting Input Channel Select bits © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 351 PIC16(L)F18455/56 (CMP) Comparator Module 23.15.5 CMOUT Name:  CMOUT Address:  0x98F Comparator Output Register Bit 7 6 5 4 3 Access Reset 2 1 0 MC2OUT MC1OUT RO RO 0 0 Bits 0, 1 – MCxOUT Mirror copy of CxOUT bit © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 352 PIC16(L)F18455/56 (ZCD) Zero-Cross Detection Module 24. (ZCD) Zero-Cross Detection Module The ZCD module detects when an A/C signal crosses through the ground potential. The actual zero crossing threshold is the zero crossing reference voltage, ZCPINV, which is typically 0.75V above ground. The connection to the signal to be detected is through a series current-limiting resistor. The module applies a current source or sink to the ZCD pin to maintain a constant voltage on the pin, thereby preventing the pin voltage from forward biasing the ESD protection diodes. When the applied voltage is greater than the reference voltage, the module sinks current. When the applied voltage is less than the Filename: 10-000194D.vsd Title: ZERO CROSS DETECT BLOCK DIAGRAM (DEDICATED OUTPUT reference voltage, the module sources current. The current source and sinkPIN) action keeps the pin voltage Last Edit: 6/10/2016 constantFirst over the full range of the applied voltage. The ZCD module is shown in the following simplified Used: PIC16(L)F153xx Notes: block diagram. Figure 24-1. Simplified ZCD Block Diagram VPULLUP Rev. 10-000194D 6/10/2016 optional VDD - Zcpinv RPULLUP ZCDxIN RSERIES RPULLDOWN + External voltage source optional ZCD Output for other modules ZCDxPOL ZCDxOUT pin Interrupt det ZCDxINTP ZCDxINTN Set ZCDxIF flag Interrupt det The ZCD module is useful when monitoring an A/C waveform for, but not limited to, the following purposes: • A/C period measurement © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 353 PIC16(L)F18455/56 (ZCD) Zero-Cross Detection Module • • • 24.1 Accurate long term time measurement Dimmer phase delayed drive Low EMI cycle switching External Resistor Selection The ZCD module requires a current-limiting resistor in series with the external voltage source. The impedance and rating of this resistor depends on the external source peak voltage. Select a resistor value that will drop all of the peak voltage when the current through the resistor is nominally 300 μA. Make sure that the ZCD I/O pin internal weak pull-up is disabled so it does not interfere with the current source and sink. Equation 24-1. External Resistor ����� ������� = 3 × 10−4 Figure 24-2. External Voltage Source Rev. 30-000001A 7/18/2017 VPEAK VMAXPEAK VMINPEAK Z CPINV 24.2 ZCD Logic Output The ZCD module includes a Status bit, which can be read to determine whether the current source or sink is active. The OUT bit is set when the current sink is active, and cleared when the current source is active. The OUT bit is affected by the polarity bit. The OUT signal can also be used as input to other modules. This is controlled by the registers of the corresponding module. OUT can be used as follows: • • • 24.3 Gate source for TMR1/3/5 Clock source for TMR2/4/6 Reset source for TMR2/4/6 ZCD Logic Polarity The POL bit inverts the OUT bit relative to the current source and sink output. When the POL bit is set, a OUT high indicates that the current source is active, and a low output indicates that the current sink is active. The POL bit affects the ZCD interrupts. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 354 PIC16(L)F18455/56 (ZCD) Zero-Cross Detection Module 24.4 ZCD Interrupts An interrupt will be generated upon a change in the ZCD logic output when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in the ZCD for this purpose. The ZCDIF bit of the PIRx register will be set when either edge detector is triggered and its associated enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts. Priority of the interrupt can be changed if the IPEN bit of the INTCON register is set. The ZCD interrupt can be made high or low priority by setting or clearing the ZCDIP bit of the IPRx register. To fully enable the interrupt, the following bits must be set: • • • • ZCDIE bit of the PIEx register INTP bit for rising edge detection INTN bit for falling edge detection PEIE and GIE bits of the INTCON register Changing the POL bit will cause an interrupt, regardless of the level of the SEN bit. The ZCDIF bit of the PIRx register must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Related Links 7.8.10 INTCON 10.7.13 PIR2 24.5 Correction for ZCPINV Offset The actual voltage at which the ZCD switches is the reference voltage at the non-inverting input of the ZCD op amp. For external voltage source waveforms other than square waves, this voltage offset from zero causes the zero-cross event to occur either too early or too late. 24.5.1 Correction by AC Coupling When the external voltage source is sinusoidal, the effects of the ZCPINV offset can be eliminated by isolating the external voltage source from the ZCD pin with a capacitor, in addition to the voltage reducing resistor. The capacitor will cause a phase shift resulting in the ZCD output switch in advance of the actual zero crossing event. The phase shift will be the same for both rising and falling zero crossings, which can be compensated for by either delaying the CPU response to the ZCD switch by a timer or other means, or selecting a capacitor value large enough that the phase shift is negligible. To determine the series resistor and capacitor values for this configuration, start by computing the impedance, Z, to obtain a peak current of 300 μA. Next, arbitrarily select a suitably large non-polar capacitor and compute its reactance, Xc, at the external voltage source frequency. Finally, compute the series resistor, capacitor peak voltage, and phase shift by the formulas shown below. When this technique is used and the input signal is not present, the ZCD will tend to oscillate. To avoid this oscillation, connect the ZCD pin to VDD or GND with a high-impedance resistor such as 200K. Equation 24-2. R-C Equations VPEAK = external voltage source peak voltage f = external voltage source frequency © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 355 PIC16(L)F18455/56 (ZCD) Zero-Cross Detection Module C = series capacitor R = series resistor VC = Peak capacitor voltage Φ = Capacitor induced zero crossing phase advance in radians TΦ = Time ZC event occurs before actual zero crossing �= ����� 3 × 10−4 �� = �= 1 2��� �2 − ��2 �� = �� 3 × 10−4 Φ = tan −1� �Φ = Φ 2�� �� � Equation 24-3. R-C Calcuation Example ���� = 120 ����� = ���� × 2 = 169.7 � = 60 �� � = 0.1 �� �= ����� 3 × 10−4 �� = �= = 169.7 = 565.7 �Ω 3 × 10−4 1 1 = = 26.53 �Ω 2��� 2� × 60 × 10−7 �2 − ��2 = 565.1 �Ω �������� �� = 560 �Ω ���� �� = ��2 + ��2 = 560.6 �Ω ����� = ����� = 302.7 × 10−6� �� �� = �� × ����� = 8.0 � Φ = tan −1� �� = 0.047������� � © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 356 PIC16(L)F18455/56 (ZCD) Zero-Cross Detection Module �Φ = 24.5.2 Φ = 125.6�� 2�� Correction By Offset Current When the waveform is varying relative to VSS, then the zero cross is detected too early as the waveform falls and too late as the waveform rises. When the waveform is varying relative to VDD, then the zero cross is detected too late as the waveform rises and too early as the waveform falls. The actual offset time can be determined for sinusoidal waveforms with the corresponding equations shown below. Equation 24-4. ZCD Event Offset When External Voltage source is relative to VSS ������� = sin−1 ������ ����� 2�� When External Voltage source is relative to VDD ������� = sin−1 ��� − ������ ����� 2�� This offset time can be compensated for by adding a pull-up or pull-down biasing resistor to the ZCD pin. A pull-up resistor is used when the external voltage source is varying relative to VSS. A pull-down resistor is used when the voltage is varying relative to VDD. The resistor adds a bias to the ZCD pin so that the target external voltage source must go to zero to pull the pin voltage to the ZCPINV switching voltage. The pull-up or pull-down value can be determined with the equations shown below. Equation 24-5. ZCD Pull-up/Pull-down Resistor When External Voltage source is relative to VSS ������� = ������� ������� − ������ ������ When External Voltage source is relative to VDD ��������� = 24.6 ������� ������ ��� − ������ Handling VPEAK Variations If the peak amplitude of the external voltage is expected to vary, the series resistor must be selected to keep the ZCD current source and sink below the design maximum range of ± 600 μA and above a reasonable minimum range. A general rule of thumb is that the maximum peak voltage can be no more than six times the minimum peak voltage. To ensure that the maximum current does not exceed ± 600 μA and the minimum is at least ± 100 μA, compute the series resistance as shown in Equation 24-6. The compensating pull-up for this series resistance can be determined with the equations shown in Equation 24-5 because the pull-up value is independent from the peak voltage. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 357 PIC16(L)F18455/56 (ZCD) Zero-Cross Detection Module Equation 24-6. Series R for V range ����_���� + ����_���� ������� = 7 × 10−4 24.7 Operation During Sleep The ZCD current sources and interrupts are unaffected by Sleep. 24.8 Effects of a Reset The ZCD circuit can be configured to default to the active or inactive state on Power-on Reset (POR). When the ZCD Configuration bit is cleared, the ZCD circuit will be active at POR. When the ZCD Configuration bit is set, the SEN bit must be set to enable the ZCD module. 24.9 Disabling the ZCD Module The ZCD module can be disabled in two ways: 1. 2. The ZCD Configuration bit disables the ZCD module when set. When this is the case then the ZCD module will be enabled by setting the SEN bit. When the ZCD bit is clear, the ZCD is always enabled and the SEN bit has no effect. The ZCD can also be disabled using the ZCDMD bit of the PMDx register. This is subject to the status of the ZCD bit. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 358 PIC16(L)F18455/56 (ZCD) Zero-Cross Detection Module 24.10 Register Summary: ZCD Control Address Name Bit Pos. 0x091F ZCDCON 7:0 24.11 SEN OUT POL INTP INTN Register Definitions: ZCD Control Long bit name prefixes for the ZCD peripherals are shown in the table below. Refer to the "Long Bit Names Section" for more information. Table 24-1. ZCD Long Bit Name Prefixes Peripheral Bit Name Prefix ZCD ZCD Related Links 1.4.2.2 Long Bit Names 1.4.2.2 Long Bit Names © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 359 PIC16(L)F18455/56 (ZCD) Zero-Cross Detection Module 24.11.1 ZCDCON Name:  ZCDCON Address:  0x91F Zero-Cross Detect Control Register Bit 7 Access Reset 5 4 1 0 SEN 6 OUT POL 3 2 INTP INTN R/W RO R/W R/W R/W 0 x 0 0 0 Bit 7 – SEN Zero-Cross Detect Software Enable bit This bit is ignored when ZCD fuse is cleared. Value X 1 0 Condition Description ZCD Config fuse = 0 Zero-cross detect is always enabled. ZCD. This bit is ignored. source and sink current. ZCD Config fuse = 1 Zero-cross detect is enabled. ZCD pin is forced to output to source and sink current. ZCD Config fuse = 1 Zero-cross detect is disabled. ZCD pin operates according to PPS and TRIS controls. Bit 5 – OUT Zero-Cross Detect Data Output bit Value 1 0 1 0 Condition POL = 0 POL = 0 POL = 1 POL = 1 Description ZCD pin is sinking current ZCD pin is sourcing current ZCD pin is sourcing current ZCD pin is sinking current Bit 4 – POL Zero-Cross Detect Polarity bit Value 1 0 Description ZCD logic output is inverted ZCD logic output is not inverted Bit 1 – INTP Zero-Cross Detect Positive-Going Edge Interrupt Enable bit Value 1 0 Description ZCDIF bit is set on low-to-high ZCD_output transition ZCDIF bit is unaffected by low-to-high ZCD_output transition Bit 0 – INTN Zero-Cross Detect Negative-Going Edge Interrupt Enable bit Value 1 0 Description ZCDIF bit is set on high-to-low ZCD_output transition ZCDIF bit is unaffected by high-to-low ZCD_output transition © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 360 PIC16(L)F18455/56 Timer0 Module 25. Timer0 Module Timer0 module has the following features: • • • • • • • • 8-Bit B\Timer with Programmable Period 16-Bit Timer Selectable Clock Sources Synchronous and Asynchronous Operation Programmable Prescaler and Postscaler Interrupt on Match or Overflow Output on I/O Pin (via PPS) or to Other Peripherals Operation During Sleep Figure 25-1. Timer0 Block Diagram Rev. 10-000017I 2/8/2018 See T0CON1 Register T0CKPS Peripherals TMR0 body T0OUTPS T0IF 1 Prescaler IN SYNC OUT TMR0 FOSC/4 T016BIT T0ASYNC PPS T0_out Postscaler 0 Q D T0CKIPPS PPS RxyPPS CK Q T0CS 16-bit TMR0 Body Diagram (T016BIT = 1) 8-bit TMR0 Body Diagram (T016BIT = 0) IN TMR0L R Clear IN TMR0L TMR0 High Byte OUT 8 Read TMR0L COMPARATOR OUT Write TMR0L T0_match 8 8 TMR0H TMR0 High Byte Latch Enable 8 TMR0H 8 Internal Data Bus © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 361 PIC16(L)F18455/56 Timer0 Module 25.1 Timer0 Operation Timer0 can operate as either an 8-bit or 16-bit timer. The mode is selected with the T016BIT bit. 25.1.1 8-bit Mode In this mode Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock input gives several prescale options (see prescaler control bits, T0CKPS). In this mode as shown in Figure 25-1, a buffered version of TMR0H is maintained. This is compared with the value of TMR0L on each cycle of the selected clock source. When the two values match, the following events occur: • • 25.1.2 TMR0L is reset The contents of TMR0H are copied to the TMR0H buffer for next comparison 16-Bit Mode In this mode Timer0 increments on the rising edge of the selected clock source. A prescaler on the clock input gives several prescale options (see prescaler control bits, T0CKPS). In this mode TMR0H:TMR0L form the 16-bit timer value. As shown in Figure 25-1, read and write of the TMR0H register are buffered. TMR0H register is updated with the contents of the high byte of Timer0 during a read of TMR0L register. Similarly, a write to the high byte of Timer0 takes place through the TMR0H buffer register. The high byte is updated with the contents of TMR0H register when a write occurs to TMR0L register. This allows all 16 bits of Timer0 to be read and written at the same time. Timer0 rolls over to 0x0000 on incrementing past 0xFFFF. This makes the timer free running. TMR0L/H registers cannot be reloaded in this mode once started. 25.2 Clock Selection Timer0 has several options for clock source selections, option to operate synchronously/asynchronously and a programmable prescaler. 25.2.1 Clock Source Selection The T0CS bits are used to select the clock source for Timer0. The possible clock sources are listed in the table below. Table 25-1. Timer0 Clock Source Selections T0CS Clock Source 111 CLC1_out 110 SOSC 101 MFINTOSC(500 kHz) 100 LFINTOSC 011 HFINTOSC 010 FOSC/4 001 Pin selected by T0CKIPPS (Inverted) 000 Pin selected by T0CKIPPS (Noninverted) © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 362 PIC16(L)F18455/56 Timer0 Module 25.2.2 Synchronous Mode When the T0ASYNC bit is clear, Timer0 clock is synchronized to the system clock (FOSC/4). When operating in Synchronous mode, Timer0 clock frequency cannot exceed FOSC/4. During Sleep mode system clock is not available and Timer0 cannot operate. 25.2.3 Asynchronous Mode When the T0ASYNC bit is set, Timer0 increments with each rising edge of the input source (or output of the prescaler, if used). Asynchronous mode allows Timer0 to continue operation during Sleep mode provided the selected clock source is available. 25.2.4 Programmable Prescaler Timer0 has 16 programmable input prescaler options ranging from 1:1 to 1:32768. The prescaler values are selected using the T0CKPS bits. The prescaler counter is not directly readable or writable. The prescaler counter is cleared on the following events: • • • A write to the TMR0L register A write to either the T0CON0 or T0CON1 registers Any device Reset Related Links 8. Resets 25.3 Timer0 Output and Interrupt 25.3.1 Programmable Postscaler Timer0 has 16 programmable output postscaler options ranging from 1:1 to 1:16. The postscaler values are selected using the T0OUTPS bits. The postscaler divides the output of Timer0 by the selected ratio. The postscaler counter is not directly readable or writable. The postscaler counter is cleared on the following events: • • • 25.3.2 A write to the TMR0L register A write to either the T0CON0 or T0CON1 registers Any device Reset Timer0 Output TMR0_out is the output of the postscaler. TMR0_out toggles on every match between TMR0L and TMR0H in 8-bit mode, or when TMR0H:TMR0L rolls over in 16-bit mode. If the output postscaler is used, the output is scaled by the ratio selected. The Timer0 output can be routed to an I/O pin via the RxyPPS output selection register. The Timer0 output can be monitored through software via the T0OUT output bit. Related Links 15.2 PPS Outputs 25.3.3 Timer0 Interrupt The Timer0 Interrupt Flag bit (TMR0IF) is set when the TMR0_out toggles. If the Timer0 interrupt is enabled (TMR0IE), the CPU will be interrupted when the TMR0IF bit is set. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 363 PIC16(L)F18455/56 Timer0 Module When the postscaler bits (T0OUTPS) are set to 1:1 operation (no division), the T0IF flag bit will be set with every TMR0 match or rollover. In general, the TMR0IF flag bit will be set every T0OUTPS +1 matches or rollovers. 25.3.4 Timer0 Example Timer0 Configuration: • Timer0 mode = 16-bit • Clock Source = FOSC/4 (250 kHz) • Synchronous operation • Prescaler = 1:1 • Postscaler = 1:2 (T0OUTPS = 1) In this case the TMR0_out toggles every two rollovers of TMR0H:TMR0L. i.e., (0xFFFF)*2*(1/250kHz) = 524.28 ms 25.4 Operation During Sleep When operating synchronously, Timer0 will halt when the device enters Sleep mode. When operating asynchronously and selected clock source is active, Timer0 will continue to increment and wake the device from Sleep mode if Timer0 interrupt is enabled. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 364 PIC16(L)F18455/56 Timer0 Module 25.5 Register Summary - Timer0 Address Name Bit Pos. 0x059C TMR0L 7:0 0x059D TMR0H 7:0 0x059E T0CON0 7:0 0x059F T0CON1 7:0 25.6 TMR0L[7:0] TMR0H[7:0] T0EN T0OUT T0CS[2:0] T016BIT T0OUTPS[3:0] T0ASYNC T0CKPS[3:0] Register Definitions: Timer0 Control © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 365 PIC16(L)F18455/56 Timer0 Module 25.6.1 T0CON0 Name:  T0CON0 Address:  0x59E Timer0 Control Register 0 Bit Access Reset 5 4 T0EN 7 6 T0OUT T016BIT 3 R/W R R/W R/W 0 0 0 0 2 1 0 R/W R/W R/W 0 0 0 T0OUTPS[3:0] Bit 7 – T0EN TMR0 Enable bit Value 1 0 Description The module is enabled and operating The module is disabled Bit 5 – T0OUT TMR0 Output bit Bit 4 – T016BIT TMR0 Operating as 16-Bit Timer Select bit Value 1 0 Description TMR0 is a 16-bit timer TMR0 is an 8-bit timer Bits 3:0 – T0OUTPS[3:0] TMR0 Output Postscaler (Divider) Select bits Value 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Description 1:16 Postscaler 1:15 Postscaler 1:14 Postscaler 1:13 Postscaler 1:12 Postscaler 1:11 Postscaler 1:10 Postscaler 1:9 Postscaler 1:8 Postscaler 1:7 Postscaler 1:6 Postscaler 1:5 Postscaler 1:4 Postscaler 1:3 Postscaler 1:2 Postscaler 1:1 Postscaler © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 366 PIC16(L)F18455/56 Timer0 Module 25.6.2 T0CON1 Name:  T0CON1 Address:  0x59F Timer0 Control Register 1 Bit 7 6 5 T0CS[2:0] Access Reset 4 3 2 T0ASYNC 1 0 T0CKPS[3:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:5 – T0CS[2:0] Timer0 Clock Source Select bits Refer the clock source selection table Bit 4 – T0ASYNC TMR0 Input Asynchronization Enable bit Value 1 0 Description The input to the TMR0 counter is not synchronized to system clocks The input to the TMR0 counter is synchronized to Fosc/4 Bits 3:0 – T0CKPS[3:0] Prescaler Rate Select bit Value 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Description 1:32768 1:16384 1:8192 1:4096 1:2048 1:1024 1:512 1:256 1:128 1:64 1:32 1:16 1:8 1:4 1:2 1:1 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 367 PIC16(L)F18455/56 Timer0 Module 25.6.3 TMR0H Name:  TMR0H Address:  0x59D Timer0 Period/Count High Register Bit 7 6 5 4 3 2 1 0 TMR0H[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TMR0H[7:0] TMR0 Most Significant Counter bits Value 0 to 255 0 to 255 Condition Description T016BIT = 0 8-bit Timer0 Period Value. TMR0L continues counting from 0 when this value is reached. T016BIT = 1 16-bit Timer0 Most Significant Byte © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 368 PIC16(L)F18455/56 Timer0 Module 25.6.4 TMR0L Name:  TMR0L Address:  0x59C Timer0 Period/Count Low Register Bit 7 6 5 4 3 2 1 0 TMR0L[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TMR0L[7:0] TMR0 Least Significant Counter bits Value 0 to 255 0 to 255 Condition T016BIT = 0 Description 8-bit Timer0 Counter bits T016BIT = 1 16-bit Timer0 Least Significant Byte © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 369 PIC16(L)F18455/56 Timer1 Module with Gate Control 26. Timer1 Module with Gate Control Timer1 module is a 16-bit timer/counter with the following features: • • • • • • • • • • • • • • • 16-Bit Timer/Counter Register Pair (TMRxH:TMRxL) Programmable Internal or External Clock Source 2-Bit Prescaler Optionally Synchronized Comparator Out Multiple Timer1 Gate (count enable) Sources Interrupt-on-Overflow Wake-Up on Overflow (external clock, Asynchronous mode only) 16-Bit Read/Write Operation Time Base for the Capture/Compare Function with the CCP modules Special Event Trigger (with CCP) Selectable Gate Source Polarity Gate Toggle mode Gate Single-Pulse mode Gate Value Status Gate Event Interrupt Important:  References to module Timer1 apply to all the odd numbered timers on this device. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 370 Filename: Title: Last Edit: First Used: Note: 10-000018J.vsd TMR1 Block Diagram 8/15/2016 PIC16(L)F18455/56 16(L)F153xx 1: 2: 3: 4: 5: 6: Timer1 Module with Gate Control ST Buffer is high speed type when using TxCKIPPS. TMRx register increments on rising edge. Synchronize does not operate while in Sleep. See Register 25-3 for Clock source selections. See Register 25-4 for GATE source selections. Synchronized comparator output should not be used in conjunction with synchronized input clock. Figure 26-1. Timer1 Block Diagram TMRxGATE Rev. 10-000018J 8/15/2016 4 TxGPPS TxGSPM PPS 00000 0 NOTE (5) 11111 1 D D Q 0 TxGVAL Q1 Q TxGGO/DONE TxGPOL CK TMRxON Q Interrupt R TxGTM set bit TMRxGIF det TMRxGE set flag bit TMRxIF Tx_overflow 1 Single Pulse Acq. Control TMRxH TMRxL TMRxON EN TMRx(2) Q To Comparators (6) Synchronized Clock Input 0 D 1 TxCLK TxSYNC TMRxCLK 4 TxCKIPPS (1) PPS 0000 Note Prescaler 1,2,4,8 (4) 1111 2 TxCKPS Synchronize(3) det Fosc/2 Internal Clock Sleep Input Note:  1. This signal comes from the pin seleted by TxCKIPPS. 2. TMRx register increments on rising edge. 3. Synchronize does not operate while in Sleep. 4. See TMRxCLK for clock source selections. 5. See TMRxGATE for gate source selection. 6. Synchronized comparator output should not be used in conjunction with synchronized input clock. 26.1 Timer1 Operation The Timer1 module is a 16-bit incrementing counter that is accessed through the TMRxH:TMRxL register pair. Writes to TMRxH or TMRxL directly update the counter. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the ON and GE bits in the TxCON and TxGCON registers, respectively. The table below displays the Timer1 enable selections. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 371 PIC16(L)F18455/56 Timer1 Module with Gate Control Table 26-1. Timer1 Enable Selections 26.2 ON GE Timer1 Operation 1 1 Count Enabled 1 0 Always On 0 1 Off 0 0 Off Clock Source Selection The CS bits select the clock source for Timer1. These bits allow the selection of several possible synchronous and asynchronous clock sources. The table below lists the clock source selections. Table 26-2. Timer Clock Sources Clock Source CS 26.2.1 Timer1 Timer3 Timer5 11111-10001 Reserved Reserved Reserved 10000 CLC4_out CLC4_out CLC4_out 01111 CLC3_out CLC3_out CLC3_out 01110 CLC2_out CLC2_out CLC2_out 01101 CLC1_out CLC1_out CLC1_out 01100 Timer5 overflow output Timer5 overflow output Reserved 01011 Timer3 overflow output Reserved Timer3 overflow output 01010 Reserved Timer1 overflow output Timer1 overflow output 01001 Timer0 overflow output Timer0 overflow output Timer0 overflow output 01000 CLKR output CLKR output CLKR output 00111 SOSC SOSC SOSC 00110 MFINTOSC (32 kHz) MFINTOSC (32 kHz) MFINTOSC (32 kHz) 00101 MFINTOSC (500 kHz) MFINTOSC (500 kHz) MFINTOSC (500 kHz) 00100 LFINTOSC LFINTOSC LFINTOSC 00011 HFINTOSC HFINTOSC HFINTOSC 00010 FOSC FOSC FOSC 00001 FOSC/4 FOSC/4 FOSC/4 00000 T1CKIPPS T3CKIPPS T5CKIPPS Internal Clock Source When the internal clock source is selected the TMRxH:TMRxL register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 372 PIC16(L)F18455/56 Timer1 Module with Gate Control When the FOSC internal clock source is selected, the Timer1 register value will increment by four counts every instruction clock cycle. Due to this condition, a 2 LSB error in resolution will occur when reading the Timer1 value. To utilize the full resolution of Timer1, an asynchronous input signal must be used to gate the Timer1 clock input. Important:  In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • Timer1 enabled after POR • Write to TMRxH or TMRxL • Timer1 is disabled • Timer1 is disabled (TMRxON = 0) when TxCKI is high then Timer1 is enabled (TMRxON = 1) when TxCKI is low. Refer to the figure below. Figure 26-2. Timer1 Incrementing Edge Rev. 30-000136A 5/24/2017 TxCKI = 1 when TMRx Enabled TxCKI = 0 when TMRx Enabled Note:  1. Arrows indicate counter increments. 2. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 26.2.2 External Clock Source When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input of the TxCKIPPS pin. This external clock source can be synchronized to the system clock or it can run asynchronously. 26.3 Timer1 Prescaler Timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The CKPS bits control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMRxH or TMRxL. 26.4 Secondary Oscillator A secondary low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output). This internal circuit is to be used in conjunction with an external 32.768 kHz crystal. The secondary oscillator is not dedicated only to Timer1; it can also be used by other modules. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 373 PIC16(L)F18455/56 Timer1 Module with Gate Control The oscillator circuit is enabled by setting the SOSCEN bit of the OSCEN register. This can be used as one of the Timer1 clock sources selected with the CS bits. The oscillator will continue to run during Sleep. Important:  The oscillator requires a start-up and stabilization time before use. Thus, the SOSCEN bit of the OSCEN register should be set and a suitable delay observed prior to enabling Timer1. A software check can be performed to confirm if the secondary oscillator is enabled and ready to use. This is done by polling the SOR bit of the OSCSTAT. Related Links 9.2.1.5 Secondary Oscillator 26.5 Timer1 Operation in Asynchronous Counter Mode When the SYNC control bit is set, the external clock input is not synchronized. The timer increments asynchronously to the internal phase clocks. If external clock source is selected then the timer will continue to run during Sleep and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the timer (see 26.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode). Important:  When switching from synchronous to asynchronous operation, it is possible to skip an increment. When switching from asynchronous to synchronous operation, it is possible to produce an additional increment. 26.5.1 Reading and Writing Timer1 in Asynchronous Counter Mode Reading TMRxH or TMRxL while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). However, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. For writes, it is recommended that the user simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the TMRxH:TMRxL register pair. 26.6 Timer1 16-Bit Read/Write Mode Timer1 can be configured to read and write all 16 bits of data, to and from, the 8-bit TMRxL and TMRxH registers, simultaneously. The 16-bit read and write operations are enabled by setting the RD16 bit. To accomplish this function, the TMRxH register value is mapped to a buffer register called the TMRxH buffer register. While in 16-Bit mode, the TMRxH register is not directly readable or writable and all read and write operations take place through the use of this TMRxH buffer register. When a read from the TMRxL register is requested, the value of the TMRxH register is simultaneously loaded into the TMRxH buffer register. When a read from the TMRxH register is requested, the value is provided from the TMRxH buffer register instead. This provides the user with the ability to accurately read all 16 bits of the Timer1 value from a single instance in time. Refer the figure below for more details. In contrast, when not in 16-Bit mode, the user must read each register separately and determine if the values have become invalid due to a rollover that may have occurred between the read operations. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 374 PIC16(L)F18455/56 Timer1 Module with Gate Control When a write request of the TMRxL register is requested, the TMRxH buffer register is simultaneously updated with the contents of the TMRxH register. The value of TMRxH must be preloaded into the TMRxH buffer register prior to the write request for the TMRxL register. This provides the user with the ability to write all 16 bits to the TMRxL:TMRxH register pair at the same time. Any requests to write to the TMRxH directly does not clear the Timer1 prescaler value. The prescaler value is only cleared through write requests to the TMRxL register. Figure 26-3. Timer1 16-Bit Read/Write Mode Block Diagram From Timer1 Circuitry TMR1 High Byte TMR1L 8 Rev. 30-000135A 5/24/2017 Set TMR1IF on Overflow Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus 26.7 Timer1 Gate Timer1 can be configured to count freely or the count can be enabled and disabled using Timer1 gate circuitry. This is also referred to as Timer1 gate enable. Timer1 gate can also be driven by multiple selectable sources. 26.7.1 Timer1 Gate Enable The Timer1 Gate Enable mode is enabled by setting the GE bit. The polarity of the Timer1 Gate Enable mode is configured using the GPOL bit. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate signal is inactive, the timer will not increment and hold the current count. Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See figure below for timing details. Table 26-3. Timer1 Gate Enable Selections TMRxCLK GPOL TxG Timer1 Operation ↑ 1 1 Counts ↑ 1 0 Holds Count ↑ 0 1 Holds Count ↑ 0 0 Counts © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 375 PIC16(L)F18455/56 Timer1 Module with Gate Control Figure 26-4. Timer1 Gate Enable Mode Rev. 30-000137A 5/24/2017 TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3/5/7 26.7.2 N N+1 N+2 N+3 N+4 Timer1 Gate Source Selection The gate source for Timer1 is selected using the GSS bits. The polarity selection for the gate source is controlled by the GPOL bit. The table below lists the gate source selections. Table 26-4. Timer Gate Sources Gate Source GSS Timer1 Timer3 Timer5 11111-11001 Reserved Reserved Reserved 11000 SMT2_overflow SMT2_overflow SMT2_overflow 10111 CCP5_out CCP5_out CCP5_out 10110 CLC4_out CLC4_out CLC4_out 10101 CLC3_out CLC3_out CLC3_out 10100 CLC2_out CLC2_out CLC2_out 10011 CLC1_out CLC1_out CLC1_out 10010 ZCD1_output ZCD1_output ZCD1_output 10001 C2OUT_sync C2OUT_sync C2OUT_sync 10000 C1OUT_sync C1OUT_sync C1OUT_sync 01111 NCO1_out NCO1_out NCO1_out 01110 PWM7_out PWM7_out PWM7_out 01101 PWM6_out PWM6_out PWM6_out © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 376 PIC16(L)F18455/56 Timer1 Module with Gate Control Gate Source GSS Timer1 Timer3 Timer5 01100 CCP4_out CCP4_out CCP4_out 01011 CCP3_out CCP3_out CCP3_out 01010 CCP2_out CCP2_out CCP2_out 01001 CCP1_out CCP1_out CCP1_out 01000 SMT1_overflow SMT1_overflow SMT1_overflow 00111 TMR6_postscaled output TMR6_postscaled output TMR6_postscaled output 00110 Timer5 overflow output Timer5 overflow output Reserved 00101 TMR4_postscaled output TMR4_postscaled output TMR4_postscaled output 00100 Timer3 overflow output Reserved Timer3 overflow output 00011 TMR2_postscaled output TMR2_postscaled output TMR2_postscaled output 00010 Reserved Timer1 overflow output Timer1 overflow output 00001 Timer0 overflow output Timer0 overflow output Timer0 overflow output 00000 T1GPPS T3GPPS T5GPPS Any of the above mentioned signals can be used to trigger the gate. The output of the CMPx can be synchronized to the Timer1 clock or left asynchronous. For more information refer to the Comparator Output Synchronization section. Related Links 23.4.1 Comparator Output Synchronization 26.7.3 Timer1 Gate Toggle Mode When Timer1 Gate Toggle mode is enabled, it is possible to measure the full-cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See figure below for timing details. Timer1 Gate Toggle mode is enabled by setting the GTM bit. When the GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. Important:  Enabling Toggle mode at the same time as changing the gate polarity may result in indeterminate operation. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 377 PIC16(L)F18455/56 Timer1 Module with Gate Control Figure 26-5. TIMER1 GATE TOGGLE MODE Rev. 30-000138A 5/25/2017 TMRxGE TxGPOL TxGTM TxTxG_IN TxCKI TxGVAL TIMER1/3/5/7 26.7.4 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 Timer1 Gate Single-Pulse Mode When Timer1 Gate Single-Pulse mode is enabled, it is possible to capture a single-pulse gate event. Timer1 Gate Single-Pulse mode is first enabled by setting the GSPM bit. Next, the GGO/DONE must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the GGO/DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the GGO/DONE bit is once again set in software. Clearing the GSPM bit will also clear the GGO/DONE bit. See figure below for timing details. Enabling the Toggle mode and the Single-Pulse mode simultaneously will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See figure below for timing details. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 378 PIC16(L)F18455/56 Timer1 Module with Gate Control Figure 26-6. TIMER1 GATE SINGLE-PULSE MODE Rev. 30-000139A 5/25/2017 TMRxGE TxGPOL TxGSPM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5/7 TMRxGIF N Cleared by software © 2018 Microchip Technology Inc. N+1 N+2 Set by hardware on falling edge of TxGVAL Datasheet Preliminary Cleared by software DS40002038B-page 379 PIC16(L)F18455/56 Timer1 Module with Gate Control Figure 26-7. TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE Rev. 30-000140A 5/25/2017 TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5/7 TMRxGIF 26.7.5 N Cleared by software N+1 N+2 N+3 Set by hardware on falling edge of TxGVAL N+4 Cleared by software Timer1 Gate Value Status When Timer1 Gate Value Status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the GVAL bit in the TxGCON register. The GVAL bit is valid even when the Timer1 gate is not enabled (GE bit is cleared). 26.7.6 Timer1 Gate Event Interrupt When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of GVAL occurs, the TMRxGIF flag bit in the PIR5 register will be set. If the TMRxGIE bit in the PIE5 register is set, then an interrupt will be recognized. The TMRxGIF flag bit operates even when the Timer1 gate is not enabled (GE bit is cleared). For more information on selecting high or low priority status for the Timer1 gate event interrupt see the Interrupts chapter. 26.8 Timer1 Interrupt The Timer1 register pair (TMRxH:TMRxL) increments to FFFFh and rolls over to 0000h. When Timer1 rolls over, the Timer1 interrupt flag bit of the PIRx register is set. To enable the interrupt-on-rollover, the following bits must be set: © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 380 PIC16(L)F18455/56 Timer1 Module with Gate Control • • • • TMRxON bit of the TxCON register TMRxIE bits of the PIEx register PEIE/GIEL bit of the INTCON register GIE/GIEH bit of the INTCON register The interrupt is cleared by clearing the TMRxIF bit in the Interrupt Service Routine. For more information on selecting high or low priority status for the Timer1 overflow interrupt, see the Interrupts chapter. Important:  The TMRxH:TMRxL register pair and the TMRxIF bit should be cleared before enabling interrupts. 26.9 Timer1 Operation During Sleep Timer1 can only operate during Sleep when set up in Asynchronous Counter mode. In this mode, an external crystal or clock source can be used to increment the counter. To set up the timer to wake the device: • • • • • • TMRxON bit of the TxCON register must be set TMRxIE bit of the PIEx register must be set PEIE/GIEL bit of the INTCON register must be set TxSYNC bit of the TxCON register must be set Configure the TMRxCLK register for using secondary oscillator as the clock source Enable the SOSCEN bit of the OSCEN register The device will wake-up on an overflow and execute the next instruction. If the GIE/GIEH bit of the INTCON register is set, the device will call the Interrupt Service Routine. The secondary oscillator will continue to operate in Sleep regardless of the TxSYNC bit setting. 26.10 CCP Capture/Compare Time Base The CCP modules use the TMRxH:TMRxL register pair as the time base when operating in Capture or Compare mode. In Capture mode, the value in the TMRxH:TMRxL register pair is copied into the CCPRxH:CCPRxL register pair on a configured event. In Compare mode, an event is triggered when the value in the CCPRxH:CCPRxL register pair matches the value in the TMRxH:TMRxL register pair. This event can be a Special Event Trigger. For more information, see Capture/Compare/PWM Module(CCP) chapter. Related Links 29. Capture/Compare/PWM Module © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 381 PIC16(L)F18455/56 Timer1 Module with Gate Control 26.11 CCP Special Event Trigger When any of the CCPs are configured to trigger a special event, the trigger will clear the TMRxH:TMRxL register pair. This special event does not cause a Timer1 interrupt. The CCP module may still be configured to generate a CCP interrupt. In this mode of operation, the CCPRxH:CCPRxL register pair becomes the period register for Timer1. Timer1 should be synchronized and FOSC/4 should be selected as the clock source in order to utilize the special event trigger. Asynchronous operation of Timer1 can cause a special event trigger to be missed. In the event that a write to TMRxH or TMRxL coincides with a special event trigger from the CCP, the write will take precedence. 26.12 Peripheral Module Disable When a peripheral is not used or inactive, the module can be disabled by setting the Module Disable bit in the PMD registers. This will reduce power consumption to an absolute minimum. Setting the PMD bits holds the module in Reset and disconnects the module’s clock source. The Module Disable bits for Timer1 (TMR1MD) are in the PMD1 register. See Peripheral Module Disable (PMD) chapter for more information. Related Links 16.4 Register Summary - PMD © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 382 PIC16(L)F18455/56 Timer1 Module with Gate Control 26.13 Register Summary - Timer1 Address Name 0x020C TMR1 0x020E T1CON Bit Pos. 7:0 TMRxL[7:0] 15:8 TMRxH[7:0] 7:0 CKPS[1:0] 0x020F T1GCON 7:0 0x0210 TMR1GATE 7:0 GSS[4:0] 0x0211 TMR1CLK 7:0 CS[4:0] 0x0212 TMR3 0x0214 T3CON GTM GSPM GGO/DONE 7:0 TMRxL[7:0] TMRxH[7:0] 7:0 0x0215 T3GCON 7:0 TMR3GATE 7:0 0x0217 TMR3CLK 7:0 TMR5 GPOL 15:8 0x0216 0x0218 GE SYNC CKPS[1:0] GE GPOL GTM GGO/DONE RD16 ON RD16 ON GVAL GSS[4:0] CS[4:0] 7:0 TMRxL[7:0] 15:8 TMRxH[7:0] 0x021A T5CON 7:0 0x021B T5GCON 7:0 0x021C TMR5GATE 7:0 GSS[4:0] 0x021D TMR5CLK 7:0 CS[4:0] 26.14 ON GVAL SYNC GSPM RD16 CKPS[1:0] GE GPOL GTM GSPM SYNC GGO/DONE GVAL Register Definitions: Timer1 Long bit name prefixes for the odd numbered timers is shown in the following table. Refer to the "Long Bit Names" section for more information. Table 26-5. Timer1 prefixes Peripheral Bit Name Prefix Timer1 T1 Timer3 T3 Timer5 T5 Related Links 1.4.2.2 Long Bit Names © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 383 PIC16(L)F18455/56 Timer1 Module with Gate Control 26.14.1 TxCON Name:  TxCON Address:  0x20E,0x214,0x21A Timer Control Register Bit 7 6 5 4 3 CKPS[1:0] Access Reset 2 1 0 SYNC RD16 ON R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 5:4 – CKPS[1:0] Timer Input Clock Prescale Select bits Reset States: POR/BOR = 00 All Other Resets = uu Value 11 10 01 00 Description 1:8 Prescale value 1:4 Prescale value 1:2 Prescale value 1:1 Prescale value Bit 2 – SYNC Timer External Clock Input Synchronization Control bit Reset States: POR/BOR = 0 All Other Resets = u Value X 1 0 Condition CS = FOSC/4 or FOSC Else Else Description This bit is ignored. Timer uses the incoming clock as is. Do not synchronize external clock input Synchronize external clock input with system clock Bit 1 – RD16 16-Bit Read/Write Mode Enable bit Reset States: POR/BOR = 0 All Other Resets = u Value 1 0 Description Enables register read/write of Timer in one 16-bit operation Enables register read/write of Timer in two 8-bit operations Bit 0 – ON Timer On bit Reset States: POR/BOR = 0 All Other Resets = u Value 1 0 Description Enables Timer Disables Timer © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 384 PIC16(L)F18455/56 Timer1 Module with Gate Control 26.14.2 TxGCON Name:  TxGCON Address:  0x20F,0x215,0x21B Timer Gate Control Register Bit Access Reset 7 6 5 4 3 2 GE GPOL GTM GSPM GGO/DONE GVAL R/W R/W R/W R/W R/W RO 0 0 0 0 0 x 1 0 Bit 7 – GE Timer Gate Enable bit Reset States: POR/BOR = 0 All Other Resets = u Value 1 0 X Condition ON = 1 ON = 1 ON = 0 Description Timer counting is controlled by the Timer gate function Timer is always counting This bit is ignored Bit 6 – GPOL Timer Gate Polarity bit Reset States: POR/BOR = 0 All Other Resets = u Value 1 0 Description Timer gate is active-high (Timer counts when gate is high) Timer gate is active-low (Timer counts when gate is low) Bit 5 – GTM Timer Gate Toggle Mode bit Timer Gate Flip-Flop Toggles on every rising edge Reset States: POR/BOR = 0 All Other Resets = u Value 1 0 Description Timer Gate Toggle mode is enabled Timer Gate Toggle mode is disabled and Toggle flip-flop is cleared Bit 4 – GSPM Timer Gate Single Pulse Mode bit Reset States: POR/BOR = 0 All Other Resets = u Value 1 0 Description Timer Gate Single Pulse mode is enabled and is controlling Timer gate) Timer Gate Single Pulse mode is disabled Bit 3 – GGO/DONE Timer Gate Single Pulse Acquisition Status bit This bit is automatically cleared when TxGSPM is cleared. Reset States: POR/BOR = 0 All Other Resets = u © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 385 PIC16(L)F18455/56 Timer1 Module with Gate Control Value 1 0 Description Timer Gate Single Pulse Acquisition is ready, waiting for an edge Timer Gate Single Pulse Acquisition has completed or has not been started. Bit 2 – GVAL Timer Gate Current State bit Indicates the current state of the Timer gate that could be provided to TMRxH:TMRxL Unaffected by Timer Gate Enable (TMRxGE) © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 386 PIC16(L)F18455/56 Timer1 Module with Gate Control 26.14.3 TMRxCLK Name:  TMRxCLK Address:  0x211,0x217,0x21D Timer Clock Source Selection Register Bit 7 6 5 4 3 2 1 0 CS[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4:0 – CS[4:0] Timer Clock Source Selection bits Refer to the clock source selection table. Reset States: POR/BOR = 00000 All Other Resets = uuuuu © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 387 PIC16(L)F18455/56 Timer1 Module with Gate Control 26.14.4 TMRxGATE Name:  TMRxGATE Address:  0x210,0x216,0x21C Timer Gate Source Selection Register Bit 7 6 5 4 3 2 1 0 GSS[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4:0 – GSS[4:0] Timer Gate Source Selection bits Refer to the gate source selection table. Reset States: POR/BOR = 00000 All Other Resets = uuuuu © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 388 PIC16(L)F18455/56 Timer1 Module with Gate Control 26.14.5 TMRx Name:  TMRx Address:  0x20C,0x212,0x218 Timer Low Byte Register Bit 15 14 13 12 11 10 9 8 TMRxH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TMRxL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:8 – TMRxH[7:0] Timer Most Significant Byte Reset States: POR/BOR = 00000000 All Other Resets = uuuuuuuu Bits 7:0 – TMRxL[7:0] Timer Least Significant Byte Reset States: POR/BOR = 00000000 All Other Resets = uuuuuuuu © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 389 PIC16(L)F18455/56 Timer2 Module 27. Timer2 Module The Timer2 module is a 8-bit timer that incorporates the following features: • • • • • • • • • • • 8-Bit Timer and Period Registers Readable and Writable Software Programmable Prescaler (1:1 to 1:128) Software Programmable Postscaler (1:1 to 1:16) Interrupt on T2TMR Match with T2PR One-Shot Operation Full Asynchronous Operation Includes Hardware Limit Timer (HLT) Alternate Clock Sources External Timer Reset Signal Sources Configurable Timer Reset Operation See Figure 27-1 for a block diagram of Timer2. See table below for the clock source selections. Important:  References to module Timer2 apply to all the even numbered timers on this device. (Timer2, Timer4, etc.) © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 390 PIC16(L)F18455/56 Timer2 Module Figure 27-1. Timer2 with Hardware Limit Timer (HLT) Block Diagram RSEL INPPS TxIN PPS External Reset (2) Sources Rev. 10-000168C 9/10/2015 MODE TMRx_ers Edge Detector Level Detector Mode Control (2 clock Sync) MODE reset CCP_pset(1) MODE=01 enable D MODE=1011 Q Clear ON CPOL Prescaler TMRx_clk 3 CKPS ON Sync (2 Clocks) 0 Sync 1 Fosc/4 PSYNC TxTMR R Comparator Set flag bit TMRxIF Postscaler TMRx_postscaled 4 1 TxPR OUTPS 0 CSYNC Note:  1. Signal to the CCP to trigger the PWM pulse. 2. See TxRST for external Reset sources. Table 27-1. Clock Source Selection CS Clock Source Timer2 Timer4 Timer6 1111 Reserved Reserved Reserved 1110 CLC4_out CLC4_out CLC4_out 1101 CLC3_out CLC3_out CLC3_out 1100 CLC2_out CLC2_out CLC2_out 1011 CLC1_out CLC1_out CLC1_out 1010 ZCD1_output ZCD1_output ZCD1_output 1001 NCO1_out NCO1_out NCO1_out 1000 CLKR CLKR CLKR 0111 SOSC SOSC SOSC © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 391 PIC16(L)F18455/56 Timer2 Module Clock Source CS 27.1 Timer2 Timer4 Timer6 0110 MFINTOSC(31.25 kHz) MFINTOSC(31.25 kHz) MFINTOSC(31.25 kHz) 0101 MFINTOSC(500 kHz) MFINTOSC(500 kHz) MFINTOSC(500 kHz) 0100 LFINTOSC LFINTOSC LFINTOSC 0011 HFINTOSC(32 MHz) HFINTOSC(32 MHz) HFINTOSC(32 MHz) 0010 FOSC FOSC FOSC 0001 FOSC/4 FOSC/4 FOSC/4 0000 T2CKIPPS T4CKIPPS T6CKIPPS Timer2 Operation Timer2 operates in three major modes: • • • Free Running Period One-shot Monostable Within each mode there are several options for starting, stopping, and reset. Table 27-3 lists the options. In all modes, the T2TMR count register is incremented on the rising edge of the clock signal from the programmable prescaler. When T2TMR equals T2PR, a high level is output to the postscaler counter. T2TMR is cleared on the next clock input. An external signal from hardware can also be configured to gate the timer operation or force a T2TMR count Reset. In Gate modes the counter stops when the gate is disabled and resumes when the gate is enabled. In Reset modes the T2TMR count is reset on either the level or edge from the external source. The T2TMR and T2PR registers are both directly readable and writable. The T2TMR register is cleared and the T2PR register initializes to FFh on any device Reset. Both the prescaler and postscaler counters are cleared on the following events: • • • • A write to the T2TMR register A write to the T2CON register Any device Reset External Reset Source event that resets the timer. Important:  T2TMR is not cleared when T2CON is written. 27.1.1 Free Running Period Mode The value of T2TMR is compared to that of the Period register, T2PR, on each clock cycle. When the two values match, the comparator resets the value of T2TMR to 00h on the next cycle and increments the output postscaler counter. When the postscaler count equals the value in the OUTPS bits of the T2CON © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 392 PIC16(L)F18455/56 Timer2 Module register then a one clock period wide pulse occurs on the TMR2_postscaled output, and the postscaler count is cleared. 27.1.2 One-Shot Mode The One-Shot mode is identical to the Free Running Period mode except that the ON bit is cleared and the timer is stopped when T2TMR matches T2PR and will not restart until the ON bit is cycled off and on. Postscaler (OUTPS) values other than zero are ignored in this mode because the timer is stopped at the first period event and the postscaler is reset when the timer is restarted. 27.1.3 Monostable Mode Monostable modes are similar to One-Shot modes except that the ON bit is not cleared and the timer can be restarted by an external Reset event. 27.2 Timer2 Output The Timer2 module’s primary output is TMR2_postscaled, which pulses for a single TMR2_clk period upon each match of the postscaler counter and the OUTPS bits of the T2CON register. The postscaler is incremented each time the T2TMR value matches the T2PR value. This signal can be selected as an input to several other input modules: • • • • • • The ADC module, as an auto-conversion trigger CWG, as an auto-shutdown source The CRC memory scanner, as a trigger for triggered mode Gate source for odd numbered timers (Timer1, Timer3, etc.) Alternate SPI clock Reset signals for other instances of even numbered timers (Timer2, Timer4, etc.) In addition, the Timer2 is also used by the CCP module for pulse generation in PWM mode. See “PWM Overview” and “Pulse-width Modulation” sections for more details on setting up Timer2 for use with the CCP and PWM modules. Related Links 29.4 PWM Overview 30. (PWM) Pulse-Width Modulation 27.3 External Reset Sources In addition to the clock source, the Timer2 also takes in an external Reset source. This external Reset source is selected for each timer with the corresponding TxRST register. This source can control starting and stopping of the timer, as well as resetting the timer, depending on which mode the timer is in. Reset source selections are shown in the following table. Table 27-2. External Reset Sources RSEL Reset Source TMR2 TMR4 TMR6 1111 CCP5_out CCP5_out CCP5_out 1101 CLC4_out CLC4_out CLC4_out © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 393 PIC16(L)F18455/56 Timer2 Module Reset Source RSEL 27.4 TMR2 TMR4 TMR6 1100 CLC3_out CLC3_out CLC3_out 1011 CLC2_out CLC2_out CLC2_out 1010 CLC1_out CLC1_out CLC1_out 1001 ZCD1_output ZCD1_output ZCD1_output 1000 C2OUT_sync C2OUT_sync C2OUT_sync 0111 C1OUT_sync C1OUT_sync C1OUT_sync 0110 PWM7_out PWM7_out PWM7_out 0101 PWM6_out PWM6_out PWM6_out 0100 CCP4_out CCP4_out CCP4_out 0011 CCP3_out CCP3_out CCP3_out 0010 CCP2_out CCP2_out CCP2_out 0001 CCP1_out CCP1_out CCP1_out 0000 T2INPPS T4INPPS T6INPPS Timer2 Interrupt Timer2 can also generate a device interrupt. The interrupt is generated when the postscaler counter matches with the selected postscaler value (OUTPS bits of T2CON register). The interrupt is enabled by setting the TMR2IE interrupt enable bit. Interrupt timing is illustrated in the figure below. Figure 27-2. Timer2 Prescaler, Postscaler, and Interrupt Timing Diagram Rev. 10-000205A 4/7/2016 0b010 CKPS PRx 1 OUTPS 0b0001 TMRx_clk TMRx 0 1 0 1 0 1 0 TMRx_postscaled TMRxIF (1) (2) (1) Note:  1. Setting the interrupt flag is synchronized with the instruction clock. 2. Cleared by software. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 394 PIC16(L)F18455/56 Timer2 Module 27.5 Operating Modes The mode of the timer is controlled by the MODE bits of the T2HLT register. Edge-Triggered modes require six Timer clock periods between external triggers. Level-Triggered modes require the triggering level to be at least three Timer clock periods long. External triggers are ignored while in Debug mode. Table 27-3. Operating Modes Table Mode Free Running Period MODE 00 Output Operation Timer Control Start Reset Stop 000 Software gate (Figure 27-3) ON = 1 — ON = 0 ON = 1 and TMRx_ers = 1 — 001 Hardware gate, activehigh (Figure 27-4) ON = 0 or TMRx_ers = 0 Hardware gate, activelow ON = 1 and TMRx_ers = 0 — 010 ON = 0 or TMRx_ers = 1 011 Rising or falling edge Reset TMRx_ers ↕ Rising edge Reset (Figure 27-5) TMRx_ers ↑ 100 101 110 Period Pulse Period Pulse with Hardware Reset 111 000 One-shot 001 One-shot Operation 01 010 Edge Triggered Start (Note 1) 011 © 2018 Microchip Technology Inc. Falling edge Reset ON = 1 ON = 0 TMRx_ers ↓ Low level Reset TMRx_ers =0 High level Reset (Figure 27-6) TMRx_ers =1 Software start (Figure 27-7) ON = 1 Rising edge start (Figure 27-8) ON = 1 and TMRx_ers ↑ Falling edge start ON = 1 and TMRx_ers ↓ — Any edge start ON = 1 and TMRx_ers ↕ — ON = 0 or TMRx_ers = 0 ON = 0 or TMRx_ers = 1 — — ON = 0 or Next clock after Datasheet Preliminary TMRx = PRx (Note 2) DS40002038B-page 395 PIC16(L)F18455/56 Timer2 Module Mode MODE Output Operation 100 101 Edge Triggered Start and 110 Hardware Reset (Note 1) 111 Operation Start Reset Rising edge start and Rising edge Reset (Figure 27-9) ON = 1 and TMRx_ers ↑ TMRx_ers ↑ Falling edge start and Falling edge Reset ON = 1 and TMRx_ers ↓ TMRx_ers ↓ Rising edge start and Low level Reset (Figure 27-10) ON = 1 and TMRx_ers ↑ TMRx_ers =0 Falling edge start and High level Reset ON = 1 and TMRx_ers ↓ TMRx_ers =1 000 001 Monostable 010 Edge Triggered Start 011 Reserved 10 Rising edge start (Figure 27-11) ON = 1 and TMRx_ers ↑ Falling edge start ON = 1 and TMRx_ers ↓ — Any edge start ON = 1 and TMRx_ers ↕ — 100 Reserved 101 Reserved 110 Level Triggered Start One-shot and 111 © 2018 Microchip Technology Inc. Stop Reserved (Note 1) Reserved Timer Control Hardware Reset High level start and Low level Reset (Figure 27-12) ON = 1 and TMRx_ers = 1 Low level start & High level Reset ON = 1 and TMRx_ers = 0 Datasheet Preliminary ON = 0 or — Next clock after TMRx = PRx (Note 3) TMRx_ers =0 ON = 0 or Held in Reset (Note 2) TMRx_ers =1 DS40002038B-page 396 PIC16(L)F18455/56 Timer2 Module Mode Reserved MODE 11 Output Operation xxx Operation Timer Control Start Reset Stop Reserved Note:  1. If ON = 0 then an edge is required to restart the timer after ON = 1. 2. 3. 27.6 When T2TMR = T2PR then the next clock clears ON and stops T2TMR at 00h. When T2TMR = T2PR then the next clock stops T2TMR at 00h but does not clear ON. Operation Examples Unless otherwise specified, the following notes apply to the following timing diagrams: • • • • Both the prescaler and postscaler are set to 1:1 (both the CKPS and OUTPS bits in the T2CON register are cleared). The diagrams illustrate any clock except FOSC/4 and show clock-sync delays of at least two full cycles for both ON and Timer2_ers. When using FOSC/4, the clock-sync delay is at least one instruction period for Timer2_ers; ON applies in the next instruction period. ON and Timer2_ers are somewhat generalized, and clock-sync delays may produce results that are slightly different than illustrated. The PWM Duty Cycle and PWM output are illustrated assuming that the timer is used for the PWM function of the CCP module as described in the “PWM Overview” section. The signals are not a part of the Timer2 module. Related Links 29.4 PWM Overview 30. (PWM) Pulse-Width Modulation 27.6.1 Software Gate Mode This mode corresponds to legacy Timer2 operation. The timer increments with each clock input when ON = 1 and does not increment when ON = 0. When the TMRx count equals the PRx period count the timer resets on the next clock and continues counting from 0. Operation with the ON bit software controlled is illustrated in Figure 27-3. With PRx = 5, the counter advances until TMRx = 5, and goes to zero with the next clock. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 397 PIC16(L)F18455/56 Timer2 Module Figure 27-3. Software Gate Mode Timing Diagram (MODE = 00000) Rev. 10-000195B 5/30/2014 0b00000 MODE TMRx_clk Instruction(1) BSF BCF BSF ON PRx TMRx 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note:  1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 29.4 PWM Overview 30. (PWM) Pulse-Width Modulation 27.6.2 Hardware Gate Mode The Hardware Gate modes operate the same as the Software Gate mode except the TMRx_ers external signal can also gate the timer. When used with the CCP, the gating extends the PWM period. If the timer is stopped when the PWM output is high, then the duty cycle is also extended. When MODE = 00001 then the timer is stopped when the external signal is high. When MODE = 00010, then the timer is stopped when the external signal is low. Figure 27-4 illustrates the Hardware Gating mode for MODE = 00001 in which a high input level starts the counter. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 398 PIC16(L)F18455/56 Timer2 Module Figure 27-4. Hardware Gate Mode Timing Diagram (MODE = 00001) Rev. 10-000 196B 5/30/201 4 MODE 0b00001 TMRx_clk TMRx_ers 5 PRx TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Related Links 29.4 PWM Overview 30. (PWM) Pulse-Width Modulation 27.6.3 Edge-Triggered Hardware Limit Mode In Hardware Limit mode, the timer can be reset by the TMRx_ers external signal before the timer reaches the period count. Three types of Resets are possible: • Reset on rising or falling edge (MODE= 00011) • Reset on rising edge (MODE = 00100) • Reset on falling edge (MODE = 00101) When the timer is used in conjunction with the CCP in PWM mode then an early Reset shortens the period and restarts the PWM pulse after a two clock delay. Refer to Figure 27-5. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 399 PIC16(L)F18455/56 Timer2 Module Figure 27-5. Edge-Triggered Hardware Limit Mode Timing Diagram (MODE = 00100) Rev. 10-000 197B 5/30/201 4 0b00100 MODE TMRx_clk PRx 5 Instruction(1) BSF BCF BSF ON TMRx_ers TMRx 0 1 2 0 1 2 3 4 5 0 1 2 3 4 5 0 1 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note:  1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 29.4 PWM Overview 30. (PWM) Pulse-Width Modulation 27.6.4 Level-Triggered Hardware Limit Mode In the Level-Triggered Hardware Limit Timer modes the counter is reset by high or low levels of the external signal TMRx_ers, as shown in Figure 27-6. Selecting MODE = 00110 will cause the timer to reset on a low level external signal. Selecting MODE = 00111 will cause the timer to reset on a high level external signal. In the example, the counter is reset while TMRx_ers = 1. ON is controlled by BSF and BCF instructions. When ON = 0 the external signal is ignored. When the CCP uses the timer as the PWM time base then the PWM output will be set high when the timer starts counting and then set low only when the timer count matches the CCPRx value. The timer is reset when either the timer count matches the PRx value or two clock periods after the external Reset signal goes true and stays true. The timer starts counting, and the PWM output is set high, on either the clock following the PRx match or two clocks after the external Reset signal relinquishes the Reset. The PWM output will remain high until the timer counts up to match the CCPRx pulse width value. If the external Reset signal goes true while the PWM output is high then the PWM output will remain high until the Reset signal is released allowing the timer to count up to match the CCPRx value. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 400 PIC16(L)F18455/56 Timer2 Module Figure 27-6. Level-Triggered Hardware Limit Mode Timing Diagram (MODE = 00111) Rev. 10-000198B 5/30/2014 MODE 0b00111 TMRx_clk 5 PRx Instruction(1) BSF BCF BSF ON TMRx_ers TMRx 0 1 2 0 1 2 3 4 5 0 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note:  1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 29.4 PWM Overview 30. (PWM) Pulse-Width Modulation 27.6.5 Software Start One-Shot Mode In One-Shot mode the timer resets and the ON bit is cleared when the timer value matches the PRx period value. The ON bit must be set by software to start another timer cycle. Setting MODE = 01000 selects One-Shot mode which is illustrated in Figure 27-7. In the example, ON is controlled by BSF and BCF instructions. In the first case, a BSF instruction sets ON and the counter runs to completion and clears ON. In the second case, a BSF instruction starts the cycle, BCF/BSF instructions turn the counter off and on during the cycle, and then it runs to completion. When One-Shot mode is used in conjunction with the CCP PWM operation the PWM pulse drive starts concurrent with setting the ON bit. Clearing the ON bit while the PWM drive is active will extend the PWM drive. The PWM drive will terminate when the timer value matches the CCPRx pulse width value. The PWM drive will remain off until software sets the ON bit to start another cycle. If software clears the ON bit after the CCPRx match but before the PRx match then the PWM drive will be extended by the length of time the ON bit remains cleared. Another timing cycle can only be initiated by setting the ON bit after it has been cleared by a PRx period count match. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 401 PIC16(L)F18455/56 Timer2 Module Figure 27-7. Software Start One-shot Mode Timing Diagram (MODE = 01000) Rev. 10-000199B 4/7/2016 MODE 0b01000 TMRx_clk 5 PRx Instruction(1) BSF BSF BCF BSF ON TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note:  1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 29.4 PWM Overview 30. (PWM) Pulse-Width Modulation 27.6.6 Edge-Triggered One-Shot Mode The Edge-Triggered One-Shot modes start the timer on an edge from the external signal input, after the ON bit is set, and clear the ON bit when the timer matches the PRx period value. The following edges will start the timer: • Rising edge (MODE = 01001) • Falling edge (MODE = 01010) • Rising or Falling edge (MODE = 01011) If the timer is halted by clearing the ON bit then another TMRx_ers edge is required after the ON bit is set to resume counting. Figure 27-8 illustrates operation in the rising edge One-Shot mode. When Edge-Triggered One-Shot mode is used in conjunction with the CCP then the edge-trigger will activate the PWM drive and the PWM drive will deactivate when the timer matches the CCPRx pulse width value and stay deactivated when the timer halts at the PRx period count match. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 402 PIC16(L)F18455/56 Timer2 Module Figure 27-8. Edge-Triggered One-Shot Mode Timing Diagram (MODE = 01001) Rev. 10-000200B 5/19/2016 MODE 0b01001 TMRx_clk 5 PRx Instruction(1) BSF BSF BCF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 CCP_pset TMRx_postscaled PWM Duty Cycle 3 PWM Output Note:  1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 29.4 PWM Overview 30. (PWM) Pulse-Width Modulation 27.6.7 Edge-Triggered Hardware Limit One-Shot Mode In Edge-Triggered Hardware Limit One-Shot modes the timer starts on the first external signal edge after the ON bit is set and resets on all subsequent edges. Only the first edge after the ON bit is set is needed to start the timer. The counter will resume counting automatically two clocks after all subsequent external Reset edges. Edge triggers are as follows: • Rising edge start and Reset (MODE = 01100) • Falling edge start and Reset (MODE = 01101) The timer resets and clears the ON bit when the timer value matches the PRx period value. External signal edges will have no effect until after software sets the ON bit. Figure 27-9 illustrates the rising edge hardware limit one-shot operation. When this mode is used in conjunction with the CCP then the first starting edge trigger, and all subsequent Reset edges, will activate the PWM drive. The PWM drive will deactivate when the timer matches the CCPRx pulse-width value and stay deactivated until the timer halts at the PRx period match unless an external signal edge resets the timer before the match occurs. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 403 PIC16(L)F18455/56 Timer2 Module Figure 27-9. Edge-Triggered Hardware Limit One-Shot Mode Timing Diagram (MODE = 01100) Rev. 10-000201B 4/7/2016 0b01100 MODE TMRx_clk 5 PRx Instruction(1) BSF BSF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note:  1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 29.4 PWM Overview 30. (PWM) Pulse-Width Modulation 27.6.8 Level Reset, Edge-Triggered Hardware Limit One-Shot Modes In Level -Triggered One-Shot mode the timer count is reset on the external signal level and starts counting on the rising/falling edge of the transition from Reset level to the active level while the ON bit is set. Reset levels are selected as follows: • Low Reset level (MODE = 01110) • High Reset level (MODE = 01111) When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a PRx match or by software control, a new external signal edge is required after the ON bit is set to start the counter. When Level-Triggered Reset One-Shot mode is used in conjunction with the CCP PWM operation, the PWM drive goes active with the external signal edge that starts the timer. The PWM drive goes inactive when the timer count equals the CCPRx pulse width count. The PWM drive does not go active when the timer count clears at the PRx period count match. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 404 PIC16(L)F18455/56 Timer2 Module Figure 27-10. Low Level Reset, Edge-Triggered hardware Limit one-Shot Mode Timing Diagram (MODE = 01110) Rev. 10-000202B 4/7/2016 0b01110 MODE TMRx_clk PRx Instruction(1) 5 BSF BSF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note:  1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 29.4 PWM Overview 30. (PWM) Pulse-Width Modulation 27.6.9 Edge-Triggered Monostable Modes The Edge-Triggered Monostable modes start the timer on an edge from the external Reset signal input, after the ON bit is set, and stop incrementing the timer when the timer matches the PRx period value. The following edges will start the timer: • Rising edge (MODE = 10001) • Falling edge (MODE = 10010) • Rising or Falling edge (MODE = 10011) When an Edge-Triggered Monostable mode is used in conjunction with the CCP PWM operation, the PWM drive goes active with the external Reset signal edge that starts the timer, but will not go active when the timer matches the PRx value. While the timer is incrementing, additional edges on the external Reset signal will not affect the CCP PWM. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 405 PIC16(L)F18455/56 Timer2 Module Figure 27-11. Rising Edge-Triggered Monostable Mode Timing Diagram (MODE = 10001) Rev. 10-000203A 4/7/2016 0b10001 MODE TMRx_clk PRx Instruction(1) 5 BSF BCF BSF BCF BSF ON TMRx_ers TMRx 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 TMRx_postscaled PWM Duty Cycle 3 PWM Output Note:  1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 29.4 PWM Overview 30. (PWM) Pulse-Width Modulation 27.6.10 Level-Triggered Hardware Limit One-Shot Modes The Level-Triggered Hardware Limit One-Shot modes hold the timer in Reset on an external Reset level and start counting when both the ON bit is set and the external signal is not at the Reset level. If one of either the external signal is not in Reset or the ON bit is set, then the other signal being set/made active will start the timer. Reset levels are selected as follows: • Low Reset level (MODE = 10110) • High Reset level (MODE = 10111) When the timer count matches the PRx period count, the timer is reset and the ON bit is cleared. When the ON bit is cleared by either a PRx match or by software control, the timer will stay in Reset until both the ON bit is set and the external signal is not at the Reset level. When Level-Triggered Hardware Limit One-Shot modes are used in conjunction with the CCP PWM operation, the PWM drive goes active with either the external signal edge or the setting of the ON bit, whichever of the two starts the timer. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 406 PIC16(L)F18455/56 Timer2 Module Figure 27-12. Level-Triggered hardware Limit one-Shot Mode Timing Diagram (MODE = 10110) Rev. 10-000204A 4/7/2016 0b10110 MODE TMR2_clk 5 PRx Instruction(1) BSF BSF BCF BSF ON TMR2_ers TMRx 0 1 2 3 4 5 0 1 2 3 0 1 2 3 4 5 0 TMR2_postscaled PWM Duty Cycle ‘D3 PWM Output Note:  1. BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input. Related Links 29.4 PWM Overview 30. (PWM) Pulse-Width Modulation 27.7 Timer2 Operation During Sleep When PSYNC = 1, Timer2 cannot be operated while the processor is in Sleep mode. The contents of the T2TMR and T2PR registers will remain unchanged while processor is in Sleep mode. When PSYNC = 0, Timer2 will operate in Sleep as long as the clock source selected is also still running. If any internal oscillator is selected as the clock source, it will stay active during Sleep mode. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 407 PIC16(L)F18455/56 Timer2 Module 27.8 Register Summary - Timer2 Address Name Bit Pos. 0x028C T2TMR 7:0 0x028D T2PR 7:0 0x028E T2CON 7:0 ON 0x028F T2HLT 7:0 PSYNC 0x0290 T2CLKCON 7:0 CS[3:0] 0x0291 T2RST 7:0 RSEL[3:0] 0x0292 T4TMR 7:0 0x0293 T4PR 7:0 0x0294 T4CON 7:0 ON 0x0295 T4HLT 7:0 PSYNC 0x0296 T4CLKCON 7:0 0x0297 T4RST 7:0 0x0298 T6TMR 7:0 TxTMR[7:0] 0x0299 T6PR 7:0 TxPR[7:0] 0x029A T6CON 7:0 ON 0x029B T6HLT 7:0 PSYNC 0x029C T6CLKCON 7:0 CS[3:0] 0x029D T6RST 7:0 RSEL[3:0] 27.9 TxTMR[7:0] TxPR[7:0] CKPS[2:0] CPOL OUTPS[3:0] CSYNC MODE[4:0] TxTMR[7:0] TxPR[7:0] CKPS[2:0] CPOL OUTPS[3:0] CSYNC MODE[4:0] CS[3:0] RSEL[3:0] CKPS[2:0] CPOL OUTPS[3:0] CSYNC MODE[4:0] Register Definitions: Timer2 Control Long bit name prefixes for the Timer2 peripherals are shown in table below. Refer to Section "Long Bit Names" for more information. Table 27-4. Timer2 long bit name prefixes Peripheral Bit Name Prefix Timer2 T2 Timer4 T4 Timer6 T6 Notice:  References to module Timer2 apply to all the even numbered timers on this device. (Timer2, Timer4, etc.) Related Links 1.4.2.2 Long Bit Names © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 408 PIC16(L)F18455/56 Timer2 Module 27.9.1 TxTMR Name:  TxTMR Address:  0x28C,0x292,0x298 Timer Counter Register Bit 7 6 5 4 3 2 1 0 TxTMR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TxTMR[7:0] Timerx Counter bits © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 409 PIC16(L)F18455/56 Timer2 Module 27.9.2 TxPR Name:  TxPR Address:  0x28D,0x293,0x299 Timer Period Register Bit 7 6 5 4 3 2 1 0 TxPR[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 7:0 – TxPR[7:0] Timer Period Register bits Value Description 0 - 255 The timer restarts at ‘0’ when TxTMR reaches TxPR value © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 410 PIC16(L)F18455/56 Timer2 Module 27.9.3 TxCON Name:  TxCON Address:  0x28E,0x294,0x29A Timerx Control Register Bit 7 6 ON Access Reset 5 4 3 2 CKPS[2:0] 1 0 OUTPS[3:0] R/W/HC R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – ON Timer On bit(1) Value 1 0 Description Timer is on Timer is off: all counters and state machines are reset Bits 6:4 – CKPS[2:0] Timer Clock Prescale Select bits Value 111 110 101 100 011 010 001 000 Description 1:128 Prescaler 1:64 Prescaler 1:32 Prescaler 1:16 Prescaler 1:8 Prescaler 1:4 Prescaler 1:2 Prescaler 1:1 Prescaler Bits 3:0 – OUTPS[3:0] Timer Output Postscaler Select bits Value 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 Description 1:16 Postscaler 1:15 Postscaler 1:14 Postscaler 1:13 Postscaler 1:12 Postscaler 1:11 Postscaler 1:10 Postscaler 1:9 Postscaler 1:8 Postscaler 1:7 Postscaler 1:6 Postscaler 1:5 Postscaler 1:4 Postscaler 1:3 Postscaler © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 411 PIC16(L)F18455/56 Timer2 Module Value 0001 0000 Description 1:2 Postscaler 1:1 Postscaler Note:  1. In certain modes, the ON bit will be auto-cleared by hardware. See Table 27-3. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 412 PIC16(L)F18455/56 Timer2 Module 27.9.4 TxHLT Name:  TxHLT Address:  0x28F,0x295,0x29B Timer Hardware Limit Control Register Bit Access Reset 7 6 5 PSYNC CPOL CSYNC 4 3 R/W R/W R/W R/W R/W 0 0 0 0 0 2 1 0 R/W R/W R/W 0 0 0 MODE[4:0] Bit 7 – PSYNC Timer Prescaler Synchronization Enable bit(1, 2) Value 1 0 Description Timer Prescaler Output is synchronized to FOSC/4 Timer Prescaler Output is not synchronized to FOSC/4 Bit 6 – CPOL Timer Clock Polarity Selection bit(3) Value 1 0 Description Falling edge of input clock clocks timer/prescaler Rising edge of input clock clocks timer/prescaler Bit 5 – CSYNC Timer Clock Synchronization Enable bit(4, 5) Value 1 0 Description ON bit is synchronized to timer clock input ON bit is not synchronized to timer clock input Bits 4:0 – MODE[4:0] Timer Control Mode Selection bits(6, 7) Value 00000 to 11111 Description See Table 27-3 Note:  1. Setting this bit ensures that reading TxTMR will return a valid data value. 2. When this bit is ‘1’, Timer cannot operate in Sleep mode. 3. CKPOL should not be changed while ON = 1. 4. 5. Setting this bit ensures glitch-free operation when the ON is enabled or disabled. When this bit is set then the timer operation will be delayed by two input clocks after the ON bit is set. Unless otherwise indicated, all modes start upon ON = 1 and stop upon ON = 0 (stops occur without affecting the value of TxTMR). 6. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 413 PIC16(L)F18455/56 Timer2 Module 7. When TxTMR = TxPR, the next clock clears TxTMR, regardless of the operating mode. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 414 PIC16(L)F18455/56 Timer2 Module 27.9.5 TxCLKCON Name:  TxCLKCON Address:  0x290,0x296,0x29C Timer Clock Source Selection Register Bit 7 6 5 4 3 2 1 0 CS[3:0] Access Reset R/W R/W R/W R/W 0 0 0 0 Bits 3:0 – CS[3:0] Timer Clock Source Selection bits Value n Description See Clock Source Selection table © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 415 PIC16(L)F18455/56 Timer2 Module 27.9.6 TxRST Name:  TxRST Address:  0x291,0x297,0x29D Timer External Reset Signal Selection Register Bit 7 6 5 4 3 2 1 0 RSEL[3:0] Access Reset R/W R/W R/W R/W 0 0 0 0 Bits 3:0 – RSEL[3:0] External Reset Source Selection Bits Value n Description See External Reset Sources table © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 416 PIC16(L)F18455/56 CCP/PWM Timer Resource Selection 28. CCP/PWM Timer Resource Selection Each CCP/PWM module has an independent timer selection which can be accessed using the CxTSEL or PxTSEL bits in the CCPTMRS0 and/or CCPTMRS1 registers. The default timer selection is TMR1 when using Capture/Compare mode and T2TMR when using PWM mode in the CCPx module. The default timer selection for the PWM module is always T2TMR. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 417 PIC16(L)F18455/56 CCP/PWM Timer Resource Selection 28.1 Register Summary - Timer Selection Registers for CCP/PWM Address Name Bit Pos. 0x021E CCPTMRS0 7:0 0x021F CCPTMRS1 7:0 28.2 C4TSEL[1:0] C3TSEL[1:0] C2TSEL[1:0] P7TSEL[1:0] P6TSEL[1:0] C1TSEL[1:0] Register Definitions: CCP/PWM Timer Selection © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 418 PIC16(L)F18455/56 CCP/PWM Timer Resource Selection 28.2.1 CCPTMRS0 Name:  CCPTMRS0 Address:  0x21E CCP Timers Selection Register0 Bit 7 6 5 C4TSEL[1:0] Access Reset 4 3 C3TSEL[1:0] 2 1 C2TSEL[1:0] 0 C1TSEL[1:0] R/W R/W R/W R/W R/W R/W R/W R/W 0 1 0 1 0 1 0 1 Bits 0:1, 2:3, 4:5, 6:7 – CxTSEL CCPx Timer Selection bits Value 11 10 01 00 Description CCPx is based off Timer5 in Capture/Compare mode and Timer6 in PWM mode CCPx is based off Timer3 in Capture/Compare mode and Timer4 in PWM mode CCPx is based off Timer1 in Capture/Compare mode and Timer2 in PWM mode Reserved © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 419 PIC16(L)F18455/56 CCP/PWM Timer Resource Selection 28.2.2 CCPTMRS1 Name:  CCPTMRS1 Address:  0x21F CCP Timers Control Register Bit 7 6 5 4 3 P7TSEL[1:0] Access Reset 2 1 0 P6TSEL[1:0] R/W R/W R/W R/W 0 1 0 1 Bits 2:3, 4:5 – PxTSEL PWMx Timer Selection bits Value 11 10 01 00 Description PWMx based on TMR6 PWMx based on TMR4 PWMx based on TMR2 Reserved © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 420 PIC16(L)F18455/56 Capture/Compare/PWM Module 29. Capture/Compare/PWM Module The Capture/Compare/PWM module is a peripheral that allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle. This family of devices contains five standard Capture/Compare/PWM modules (CCP1, CCP2, CCP3, CCP4 and CCP5). It should be noted that the Capture/Compare mode operation is described with respect to TMR1 and the PWM mode operation is described with respect to T2TMR in the following sections. The Capture and Compare functions are identical for all CCP modules. Important:  1. In devices with more than one CCP module, it is very important to pay close attention to the register names used. A number placed after the module acronym is used to distinguish between separate modules. For example, the CCP1CON and CCP2CON control the same operational aspects of two completely different CCP modules. 2. Throughout this section, generic references to a CCP module in any of its operating modes may be interpreted as being equally applicable to CCPx module. Register names, module signals, I/O pins, and bit names may use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module, when required. 29.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (CCPxCON), a capture input selection register (CCPxCAP) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). 29.1.1 CCP Modules and Timer Resources The CCP modules utilize Timers 1 through 6 that vary with the selected mode. Various timers are available to the CCP modules in Capture, Compare or PWM modes, as shown in the table below. Table 29-1. CCP Mode - Timer Resources CCP Mode Capture Compare PWM Timer Resource Timer1, Timer3 or Timer5 Timer2, Timer4 or Timer6 The assignment of a particular timer to a module is determined by the timer to CCP enable bits in the CCPTMRS0 and/or CCPTMRS1 registers. All of the modules may be active at once and may share the same timer resource if they are configured to operate in the same mode (Capture/Compare or PWM) at the same time. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 421 PIC16(L)F18455/56 Capture/Compare/PWM Module 29.1.2 Open-Drain Output Option When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters. 29.2 Capture Mode Capture mode makes use of the 16-bit odd numbered timer resources (Timer1, Timer3, etc.). When an event occurs on the capture source, the 16-bit CCPRx register captures and stores the 16-bit value of the TMRx register. An event is defined as one of the following and is configured by the MODE bits: • • • • • Every falling edge of CCPx input Every rising edge of CCPx input Every 4th rising edge of CCPx input Every 16th rising edge of CCPx input Every edge of CCPx input (rising or falling) When a capture is made, the Interrupt Request Flag bit CCPxIF of the PIRx register is set. The interrupt flag must be cleared in software. If another capture occurs before the value in the CCPRx register is read, the old captured value is overwritten by the new captured value. Important:  If an event occurs during a 2-byte read, the high and low-byte data will be from different events. It is recommended while reading the CCPRxH:CCPRxL register pair to either disable the module or read the register pair twice for data integrity. The following figure shows a simplified diagram of the capture operation. Figure 29-1. Capture Mode Operation Block Diagram Rev. 10-000158E 6/26/2017 RxyPPS CCPx PPS CTS TRIS Control CCPRxH Capture Trigger Sources See CCPxCAP register Prescaler 1,4,16 and Edge Detect CCPRxL 16 set CCPxIF 16 CCPx PPS MODE TMR1H TMR1L CCPxPPS 29.2.1 Capture Sources In Capture mode, the CCPx pin should be configured as an input by setting the associated TRIS control bit. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 422 PIC16(L)F18455/56 Capture/Compare/PWM Module Important:  If the CCPx pin is configured as an output, a write to the port can cause a capture condition. The capture source is selected by configuring the CTS bits as shown in the following table: Table 29-2. Capture Trigger Sources CTS 29.2.2 Source 111 CLC4_out 110 CLC3_out 101 CLC2_out 100 CLC1_out 011 IOC_interrupt 010 C2_out 001 C1_out 000 Pin selected by CCPxPPS Timer1 Mode Resource Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. See section "Timer1 Module with Gate Control" for more information on configuring Timer1. Related Links 26. Timer1 Module with Gate Control 29.2.3 Software Interrupt Mode When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE Interrupt Priority bit of the PIEx register clear to avoid false interrupts. Additionally, the user should clear the CCPxIF interrupt flag bit of the PIRx register following any change in Operating mode. Important:  Clocking Timer1 from the system clock (FOSC) should not be used in Capture mode. In order for Capture mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. 29.2.4 CCP Prescaler There are four prescaler settings specified by the MODE bits. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. To avoid this unexpected operation, turn the module off by clearing the CCPxCON register before changing the prescaler. The example below demonstrates the code to perform this function. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 423 PIC16(L)F18455/56 Capture/Compare/PWM Module Example 29-1. Changing Between Capture Prescalers BANKSEL CLRF MOVLW MOVWF 29.2.5 CCP1CON CCP1CON NEW_CAPT_PS CCP1CON ;(only needed when CCP1CON is not in ACCESS space) ;Turn CCP module off ;CCP ON and Prescaler select → W ;Load CCP1CON with this value Capture During Sleep Capture mode depends upon the Timer1 module for proper operation. There are two options for driving the Timer1 module in Capture mode. It can be driven by the instruction clock (FOSC/4), or by an external clock source. When Timer1 is clocked by FOSC/4, Timer1 will not increment during Sleep. When the device wakes from Sleep, Timer1 will continue from its previous state. Capture mode will operate during Sleep when Timer1 is clocked by an external clock source. 29.3 Compare Mode The Compare mode function described in this section is available and identical for all CCP modules. Compare mode makes use of the 16-bit odd numbered Timer resources (Timer1, Timer3, etc.). The 16-bit value of the CCPRx register is constantly compared against the 16-bit value of the TMRx register. When a match occurs, one of the following events can occur: • • • • • • Toggle the CCPx output and clear TMRx Toggle the CCPx output without clearing TMRx Set the CCPx output Clear the CCPx output Pulse output Pulse output and clear TMRx The action on the pin is based on the value of the MODE control bits. At the same time, the interrupt flag CCPxIF bit is set, and an ADC conversion can be triggered, if selected. All Compare modes can generate an interrupt and trigger an ADC conversion. When MODE = '0001' or '1011', the CCP resets the TMRx register. The following figure shows a simplified diagram of the compare operation. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 424 PIC16(L)F18455/56 Capture/Compare/PWM Module Figure 29-2. Compare Mode Operation Block Diagram Rev. 30-000133A 6/27/2017 MODE Auto-conversion Trigger 4 CCPx Q PPS RxyPPS S R CCPRxH CCPRxL Output Logic Comparator TMR1H TRIS TMR1L Set CCPxIF Interrupt Flag 29.3.1 CCPx Pin Configuration The software must configure the CCPx pin as an output by clearing the associated TRIS bit and defining the appropriate output pin through the RxyPPS registers. See section "Peripheral Pin Select (PPS) Module" for more details. The CCP output can also be used as an input for other peripherals. Important:  Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. Related Links 15. (PPS) Peripheral Pin Select Module 29.3.2 Timer1 Mode Resource In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode. See Section "Timer1 Module with Gate Control" for more information on configuring Timer1. Important:  Clocking Timer1 from the system clock (FOSC) should not be used in Compare mode. In order for Compare mode to recognize the trigger event on the CCPx pin, Timer1 must be clocked from the instruction clock (FOSC/4) or from an external clock source. 29.3.3 Auto-Conversion Trigger All CCPx modes set the CCP Interrupt Flag (CCPxIF). When this flag is set and a match occurs, an autoconversion trigger can take place if the CCP module is selected as the conversion trigger source. Refer to Section "Auto-Conversion Trigger" for more information. Important:  Removing the match condition by changing the contents of the CCPRxH and CCPRxL register pair, between the clock edge that generates the Auto-conversion Trigger and the clock edge that generates the Timer1 Reset, will preclude the Reset from occurring. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 425 PIC16(L)F18455/56 Capture/Compare/PWM Module Related Links 20.2.6 Auto-Conversion Trigger 29.3.4 Compare During Sleep Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep, unless the timer is running. The device will wake on interrupt (if enabled). 29.4 PWM Overview Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully ON and fully OFF states. The PWM signal resembles a square wave where the high portion of the signal is considered the ON state and the low portion of the signal is considered the OFF state. The high portion, also known as the pulse width, can vary in time and is defined in steps. A larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. Lowering the number of steps applied, which shortens the pulse width, supplies less power. The PWM period is defined as the duration of one complete cycle or the total amount of ON and OFF time combined. PWM resolution defines the maximum number of steps that can be present in a single PWM period. A higher resolution allows for more precise control of the pulse-width time and in turn the power that is applied to the load. The term duty cycle describes the proportion of the ON time to the OFF time and is expressed in percentages, where 0% is fully OFF and 100% is fully ON. A lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. The shows a typical waveform of the PWM signal. Figure 29-3. CCP PWM Output Signal Rev. 30-000134A 5/9/2017 Period Pulse Width TMR2 = PR2 TMR2 = CCPRxH:CCPRxL TMR2 = 0 29.4.1 Standard PWM Operation The standard PWM function described in this section is available and identical for all CCP modules. The standard PWM mode generates a Pulse-Width Modulation (PWM) signal on the CCPx pin with up to ten bits of resolution. The period, duty cycle, and resolution are controlled by the following registers: • • • • Even numbered TxPR registers (T2PR, T4PR, etc) Even numbered TxCON registers (T2CON, T4CON, etc) 16-bit CCPRx registers CCPxCON registers It is required to have FOSC/4 as the clock input to TxTMR for correct PWM operation. The following figure shows a simplified block diagram of PWM operation. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 426 PIC16(L)F18455/56 Capture/Compare/PWM Module Figure 29-4. Simplified PWM Block Diagram Rev. 10-000 157C 9/5/201 4 Duty cycle registers CCPRxH CCPRxL CCPx_out 10-bit Latch(2) (Not accessible by user) Comparator R S Q PPS RxyPPS TMR2 Module R TMR2 To Peripherals set CCPIF CCPx TRIS Control (1) ERS logic Comparator CCPx_pset PR2 Note:  1. 8-bit timer is concatenated with two bits generated by FOSC or two bits of the internal prescaler to create 10-bit time base. 2. The alignment of the 10 bits from the CCPRx register is determined by the CCPxFMT bit. Important:  The corresponding TRIS bit must be cleared to enable the PWM output on the CCPx pin. 29.4.2 Setup for PWM Operation The following steps should be taken when configuring the CCP module for standard PWM operation: 1. 2. 3. 4. 5. Use the desired output pin RxyPPS control to select CCPx as the source and disable the CCPx pin output driver by setting the associated TRIS bit. Load the T2PR register with the PWM period value. Configure the CCP module for the PWM mode by loading the CCPxCON register with the appropriate values. Load the CCPRx register with the PWM duty cycle value and configure the FMT bit to set the proper register alignment. Configure and start Timer2: – Clear the TMR2IF interrupt flag bit of the PIRx register. See Note below. – Select the timer clock source to be as FOSC/4 using the TxCLKCON register. This is required for correct operation of the PWM module. – Configure the T2CKPS bits of the T2CON register with the timer prescale value. – Enable the timer by setting the T2ON bit. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 427 PIC16(L)F18455/56 Capture/Compare/PWM Module 6. Enable PWM output pin: – Wait until the timer overflows and the TMR2IF bit of the PIRx register is set. See Note below. – Enable the CCPx pin output driver by clearing the associated TRIS bit. Important:  In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. Related Links 27.9.3 TxCON 29.4.3 Timer2 Timer Resource The PWM standard mode makes use of the 8-bit Timer2 timer resources to specify the PWM period. 29.4.4 PWM Period The PWM period is specified by the T2PR register of Timer2. The PWM period can be calculated using the formula in the equation below. Equation 29-1. PWM Period ��������� = �2�� + 1 • 4 • ���� • ���2Pr����������� where TOSC = 1/FOSC When T2TMR is equal to T2PR, the following three events occur on the next increment cycle: • • • T2TMR is cleared The CCPx pin is set. (Exception: If the PWM duty cycle = 0%, the pin will not be set.) The PWM duty cycle is transferred from the CCPRx register into a 10-bit buffer. Important:  The Timer postscaler (see "Timer2 Interrupt") is not used in the determination of the PWM frequency. Related Links 27.4 Timer2 Interrupt 29.4.5 PWM Duty Cycle The PWM duty cycle is specified by writing a 10-bit value to the CCPRx register. The alignment of the 10bit value is determined by the FMT bit (see Figure 29-5). The CCPRx register can be written to at any time. However, the duty cycle value is not latched into the 10-bit buffer until after a match between T2PR and T2TMR. The equations below are used to calculate the PWM pulse width and the PWM duty cycle ratio. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 428 PIC16(L)F18455/56 Capture/Compare/PWM Module Figure 29-5. PWM 10-Bit Alignment Rev. 10-000 160A 12/9/201 3 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 FMT = 1 FMT = 0 CCPRxH CCPRxL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 10-bit Duty Cycle 9 8 7 6 5 4 3 2 1 0 Equation 29-2. Pulse Width ����� ����ℎ = ������: ������ �������� ����� • ���� • ���2 Pr������ ����� Equation 29-3. Duty Cycle ������: ������ �������� ����� �������������� = 4 �2�� + 1 The CCPRx register is used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. The 8-bit timer T2TMR register is concatenated with either the 2-bit internal system clock (FOSC), or two bits of the prescaler, to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. When the 10-bit time base matches the CCPRx register, then the CCPx pin is cleared (see Figure 29-4). 29.4.6 PWM Resolution The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when T2PR is 255. The resolution is a function of the T2PR register value as shown below. Equation 29-4. PWM Resolution log 4 �2�� + 1 Re�������� = ���� log 2 Important:  If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain unchanged. Table 29-3. Example PWM Frequencies and Resolutions (FOSC = 20 MHz) PWM Frequency Timer Prescale T2PR Value Maximum Resolution (bits) © 2018 Microchip Technology Inc. 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 16 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Datasheet Preliminary DS40002038B-page 429 PIC16(L)F18455/56 Capture/Compare/PWM Module Table 29-4. Example PWM Frequencies and Resolutions (FOSC = 8 MHz) PWM Frequency Timer Prescale T2PR Value Maximum Resolution (bits) 1.22 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 16 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 29.4.7 Operation in Sleep Mode In Sleep mode, the T2TMR register will not increment and the state of the module will not change. If the CCPx pin is driving a value, it will continue to drive that value. When the device wakes up, T2TMR will continue from the previous state. 29.4.8 Changes in System Clock Frequency The PWM frequency is derived from the system clock frequency. Any changes in the system clock frequency will result in changes to the PWM frequency. See the "Oscillator Module (with Fail-Safe Clock Monitor)" section for additional details. Related Links 9. Oscillator Module (with Fail-Safe Clock Monitor) 29.4.9 Effects of Reset Any Reset will force all ports to Input mode and the CCP registers to their Reset states. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 430 PIC16(L)F18455/56 Capture/Compare/PWM Module 29.5 Register Summary - CCP Control Address Name Bit Pos. 0x030C CCPR1 0x030E CCP1CON 7:0 0x030F CCP1CAP 7:0 7:0 15:8 CCPRH[7:0] EN OUT FMT MODE[3:0] CTS[2:0] 7:0 CCPRL[7:0] 15:8 CCPRH[7:0] 0x0310 CCPR2 0x0312 CCP2CON 7:0 0x0313 CCP2CAP 7:0 EN OUT CCPR3 0x0316 CCP3CON 7:0 0x0317 CCP3CAP 7:0 FMT MODE[3:0] CTS[2:0] 7:0 0x0314 CCPRL[7:0] 15:8 CCPRH[7:0] EN OUT FMT MODE[3:0] CTS[2:0] 7:0 CCPRL[7:0] 15:8 CCPRH[7:0] 0x0318 CCPR4 0x031A CCP4CON 7:0 0x031B CCP4CAP 7:0 EN OUT CCPR5 0x031E CCP5CON 7:0 0x031F CCP5CAP 7:0 FMT MODE[3:0] CTS[2:0] 7:0 0x031C 29.6 CCPRL[7:0] CCPRL[7:0] 15:8 CCPRH[7:0] EN OUT FMT MODE[3:0] CTS[2:0] Register Definitions: CCP Control Long bit name prefixes for the CCP peripherals are shown in the following table. Refer to the “Long Bit Names” section for more information. Table 29-5. CCP Long bit name prefixes Peripheral Bit Name Prefix CCP1 CCP1 CCP2 CCP2 CCP3 CCP3 CCP4 CCP4 CCP5 CCP5 Related Links 1.4.2.2 Long Bit Names © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 431 PIC16(L)F18455/56 Capture/Compare/PWM Module 29.6.1 CCPxCON Name:  CCPxCON Address:  0x30E,0x312,0x316,0x31A,0x31E CCP Control Register Bit Access Reset 5 4 EN 7 6 OUT FMT 3 R/W RO R/W R/W 0 x 0 0 2 1 0 R/W R/W R/W 0 0 0 MODE[3:0] Bit 7 – EN CCP Module Enable bit Value 1 0 Description CCP is enabled CCP is disabled Bit 5 – OUT CCP Output Data bit (read-only) Bit 4 – FMT CCPW (pulse-width) Value Alignment bit Value x x 1 0 Condition Capture mode Compare mode PWM mode PWM mode Description Not used Not used Left-aligned format Right-aligned format Bits 3:0 – MODE[3:0] CCP Mode Select bits Table 29-6. CCPx Mode Select Bits MODE Operating Mode Operation Set CCPxIF 11xx PWM PWM Operation Yes 1011 Compare Pulse output; clear TMR1(2) Yes 1010 Pulse output Yes 1001 Clear output(1) Yes 1000 Set output(1) Yes Every 16th rising edge of CCPx input Yes 0110 Every 4th rising edge of CCPx input Yes 0101 Every rising edge of CCPx input Yes 0100 Every falling edge of CCPx input Yes 0011 Every edge of CCPx input Yes Toggle output Yes 0111 0010 Capture Compare © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 432 PIC16(L)F18455/56 Capture/Compare/PWM Module MODE Operating Mode 0001 0000 Operation Set CCPxIF Toggle output; clear TMR1(2) Yes Disabled — Note:  1. The set and clear operations of the Compare mode are reset by setting MODE = '0000' or EN = 0. 2. When MODE = '0001' or '1011', then the timer associated with the CCP module is cleared. TMR1 is the default selection for the CCP module, so it is used for indication purpose only. Note:  1. The set and clear operations of the Compare mode are reset by setting MODE = '0000' or EN = 0. 2. When MODE = '0001' or '1011', then the timer associated with the CCP module is cleared. TMR1 is the default selection for the CCP module, so it is used for indication purpose only. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 433 PIC16(L)F18455/56 Capture/Compare/PWM Module 29.6.2 CCPxCAP Name:  CCPxCAP Address:  0x30F,0x313,0x317,0x31B,0x31F Capture Trigger Input Selection Register Bit 7 6 5 4 3 2 1 0 CTS[2:0] Access Reset R/W R/W R/W 0 0 0 Bits 2:0 – CTS[2:0] Capture Trigger Input Selection bits Table 29-7. Capture Trigger Sources CTS Source 111 CLC4_out 110 CLC3_out 101 CLC2_out 100 CLC1_out 011 IOC_interrupt 010 C2_out 001 C1_out 000 Pin selected by CCPxPPS © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 434 PIC16(L)F18455/56 Capture/Compare/PWM Module 29.6.3 CCPRx Name:  CCPRx Address:  0x30C,0x310,0x314,0x318,0x31C Capture/Compare/Pulse Width Register Bit 15 14 13 12 11 10 9 8 CCPRH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 CCPRL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 15:8 – CCPRH[7:0] Capture/Compare/Pulse Width High byte Value 0 to 255 0 to 255 0,1,2,3 Name MODE = Capture Description High byte of 16-bit captured value MODE = Compare High byte of 16-bit compare value MODE = PWM & FMT=0 CCPRH=Bits of 10-bit Pulse width value 0 to 255 MODE = PWM & FMT=1 CCPRH not used Bits of 10-bit Pulse width value Bits 7:0 – CCPRL[7:0] Capture/Compare/Pulse Width Low byte Value 0 to 255 0 to 255 0 to 255 0,64,12 8,192 Name MODE = Capture Description Low byte of 16-bit captured value MODE = Compare Low byte of 16-bit compare value MODE = PWM & FMT=0 Bits of 10-bit Pulse width value MODE = PWM & FMT=1 CCPRL=Bits of 10-bit Pulse width value © 2018 Microchip Technology Inc. CCPRL not used Datasheet Preliminary DS40002038B-page 435 PIC16(L)F18455/56 (PWM) Pulse-Width Modulation 30. (PWM) Pulse-Width Modulation The PWM module generates a Pulse-Width Modulated signal determined by the duty cycle, period, and resolution that are configured by the following registers: • • • • TxPR TxCON PWMxDC PWMxCON Important:  The corresponding TRIS bit must be cleared to enable the PWM output on the PWMx pin. Each PWM module can select the timer source that controls the module. Note that the PWM mode Filename: 10-000022B.vsd operation is described with respect to TMR2 in the following sections. Title: PWM Block Diagram Last Edit: Figure 30-1 shows 9/24/2014 a simplified block diagram of PWM operation. First Used: 16(L)F1614/5/8/9 (LECW/X) Notes: Figure 30-2 shows a typical waveform of the PWM signal. Figure 30-1. Simplified PWM Block Diagram Rev. 10-000022B 9/24/2014 PWMxDCL Duty cycle registers PWMxDCH PWMx_out 10-bit Latch (Not visible to user) Comparator R Q 0 S To Peripherals Q 1 PPS PWMx TMR2 Module TMR2 Comparator R PWMxPOL (1) RxyPPS TRIS Control T2_match PR2 Note 1: 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to Note:  create 10-bit time-base. 1. 8-bit timer is concatenated with two bits generated by Fosc or two bits of the internal prescaler to create 10-bit time base. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 436 PIC16(L)F18455/56 (PWM) Pulse-Width Modulation Figure 30-2. PWM Output Period Rev. 30-000129A 5/17/2017 Pulse Width TMR2 = PR2 TMR2 = PWMxDCH:PWMxDCL TMR2 = 0 For a step-by-step procedure on how to set up this module for PWM operation, refer to 30.9 Setup for PWM Operation using PWMx Output Pins. 30.1 Fundamental Operation The PWM module produces a 10-bit resolution output. The PWM timer can be selected using the PxTSEL bits in the CCPTMRS register. The default selection for PWMx is TMR2. Note that the PWM module operation in the following sections is described with respect to TMR2. Timer2 and T2PR set the period of the PWM. The PWMxDCL and PWMxDCH registers configure the duty cycle. The period is common to all PWM modules, whereas the duty cycle is independently controlled. Important:  The Timer2 postscaler is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. All PWM outputs associated with Timer2 are set when T2TMR is cleared. Each PWMx is cleared when TxTMR is equal to the value specified in the corresponding PWMxDCH (8 MSb) and PWMxDCL (2 LSb) registers. When the value is greater than or equal to T2PR, the PWM output is never cleared (100% duty cycle). Important:  The PWMxDCH and PWMxDCL registers are double buffered. The buffers are updated when T2TMR matches T2PR. Care should be taken to update both registers before the timer match occurs. 30.2 PWM Output Polarity The output polarity is inverted by setting the POL bit. 30.3 PWM Period The PWM period is specified by the TxPR register The PWM period can be calculated using the formula of 30.3 PWM Period. It is required to have FOSC/4 as the selected clock input to the timer for correct PWM operation. Equation 30-1. PWM Period ��������� = �2�� + 1 • 4 • ���� • ���2 Pr����������� Note:  TOSC = 1/FOSC When T2TMR is equal to T2PR, the following three events occur on the next increment cycle: © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 437 PIC16(L)F18455/56 (PWM) Pulse-Width Modulation • • • T2TMR is cleared The PWM output is active. (Exception: When the PWM duty cycle = 0%, the PWM output will remain inactive.) The PWMxDCH and PWMxDCL register values are latched into the buffers. Important:  The Timer2 postscaler has no effect on the PWM operation. 30.4 PWM Duty Cycle The PWM duty cycle is specified by writing a 10-bit value to the PWMxDCH and PWMxDCL register pair. The PWMxDCH register contains the eight MSbs and the PWMxDCL, the two LSbs. The PWMxDCH and PWMxDCL registers can be written to at any time. The formulas below are used to calculate the PWM pulse width and the PWM duty cycle ratio. Equation 30-2. Pulse Width ���������ℎ = �������: ������� < 7: 6 > • ���� • ���2Pr����������� Note:  TOSC = 1/FOSC Equation 30-3. Duty Cycle Ratio �������: ������� < 7: 6 > �������������� = 4 �2�� + 1 The 8-bit timer T2TMR register is concatenated with the two Least Significant bits of 1/FOSC, adjusted by the Timer2 prescaler to create the 10-bit time base. The system clock is used if the Timer2 prescaler is set to 1:1. 30.5 PWM Resolution The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is ten bits when T2PR is 255. The resolution is a function of the T2PR register value as shown below. Equation 30-4. PWM Resolution log 4 �2�� + 1 Re�������� = ���� log 2 Important:  If the pulse-width value is greater than the period, the assigned PWM pin(s) will remain unchanged. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 438 PIC16(L)F18455/56 (PWM) Pulse-Width Modulation Table 30-1. Example PWM Frequencies and Resolutions (Fosc = 20 MHz) PWM Frequency Timer Prescale T2PR Value Maximum Resolution (bits) 0.31 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz 64 4 1 1 1 1 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 10 10 10 8 7 6.6 Table 30-2. Example PWM Frequencies and Resolutions (Fosc = 8 MHz) PWM Frequency 0.31 kHz 4.90 kHz 19.61 kHz 76.92 kHz 153.85 kHz 200.0 kHz 64 4 1 1 1 1 0x65 0x65 0x65 0x19 0x0C 0x09 8 8 8 6 5 5 Timer Prescale T2PR Value Maximum Resolution (bits) 30.6 Operation in Sleep Mode In Sleep mode, the T2TMR register will not increment and the state of the module will not change. If the PWMx pin is driving a value, it will continue to drive that value. When the device wakes up, T2TMR will continue from its previous state. 30.7 Changes in System Clock Frequency The PWM frequency is derived from the system clock frequency (FOSC). Any changes in the system clock frequency will result in changes to the PWM frequency. Related Links 9. Oscillator Module (with Fail-Safe Clock Monitor) 30.8 Effects of Reset Any Reset will force all ports to Input mode and the PWM registers to their Reset states. 30.9 Setup for PWM Operation using PWMx Output Pins The following steps should be taken when configuring the module for PWM operation using the PWMx pins: 1. 2. 3. 4. 5. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the T2PR register with the PWM period value. Load the PWMxDCH register and bits of the PWMxDCL register with the PWM duty cycle value. Configure and start Timer2: – Clear the TMR2IF interrupt flag bit of the PIRx register.(1) – Select the timer clock source to be as FOSC/4 using the TxCLKCON register. This is required for correct operation of the PWM module. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 439 PIC16(L)F18455/56 (PWM) Pulse-Width Modulation 6. 7. 8. – Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value. – Enable Timer2 by setting the T2ON bit of the T2CON register. Enable PWM output pin and wait until Timer2 overflows, TMR2IF bit of the PIRx register is set.(2) Enable the PWMx pin output driver(s) by clearing the associated TRIS bit(s) and setting the desired pin PPS control bits. Configure the PWM module by loading the PWMxCON register with the appropriate values. Note:  1. In order to send a complete duty cycle and period on the first PWM output, the above steps must be followed in the order given. If it is not critical to start with a complete PWM signal, then move Step 8 to replace Step 4. 2. For operation with other peripherals only, disable PWMx pin outputs. 30.9.1 PWMx Pin Configuration All PWM outputs are multiplexed with the PORT data latch. The user must configure the pins as outputs by clearing the associated TRIS bits. 30.10 Setup for PWM Operation to Other Device Peripherals The following steps should be taken when configuring the module for PWM operation to be used by other device peripherals: 1. 2. 3. 4. 5. 6. 7. Disable the PWMx pin output driver(s) by setting the associated TRIS bit(s). Clear the PWMxCON register. Load the T2PR register with the PWM period value. Load the PWMxDCH register and bits of the PWMxDCL register with the PWM duty cycle value. Configure and start Timer2: – Clear the TMR2IF interrupt flag bit of the PIRx register.(1) – Select the timer clock source to be as FOSC/4 using the TxCLKCON register. This is required for correct operation of the PWM module. – Configure the T2CKPS bits of the T2CON register with the Timer2 prescale value. – Enable Timer2 by setting the T2ON bit of the T2CON register. Wait until Timer2 overflows, TMR2IF bit of the PIRx register is set.(1) Configure the PWM module by loading the PWMxCON register with the appropriate values. Note:  1. In order to send a complete duty cycle and period on the first PWM output, the above steps must be included in the setup sequence. If it is not critical to start with a complete PWM signal on the first output, then step 6 may be ignored. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 440 PIC16(L)F18455/56 (PWM) Pulse-Width Modulation 30.11 Register Summary - Registers Associated with PWM Address Name 0x038C PWM6DC 0x038E PWM6CON 0x038F Reserved 0x0390 PWM7DC 0x0392 PWM7CON 30.12 Bit Pos. 7:0 DCL[1:0] 15:8 7:0 DCH[7:0] EN 7:0 OUT POL DCL[1:0] 15:8 7:0 DCH[7:0] EN OUT POL Register Definitions: PWM Control Long bit name prefixes for the PWM peripherals are shown in the table below. Refer to the "Long Bit Names Section" for more information. Table 30-3. PWM Bit Name Prefixes Peripheral Bit Name Prefix PWM6 PWM6 PWM7 PWM7 Related Links 1.4.2.2 Long Bit Names © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 441 PIC16(L)F18455/56 (PWM) Pulse-Width Modulation 30.12.1 PWMxCON Name:  PWMxCON Address:  0x38E,0x392 PWM Control Register Bit Access Reset 5 4 EN 7 6 OUT POL R/W RO R/W 0 0 0 3 2 1 0 Bit 7 – EN PWM Module Enable bit Value 1 0 Description PWM module is enabled PWM module is disabled Bit 5 – OUT PWM Module Output Level When Bit is Read Bit 4 – POL PWM Output Polarity Select bit Value 1 0 Description PWM output is inverted PWM output is normal © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 442 PIC16(L)F18455/56 (PWM) Pulse-Width Modulation 30.12.2 PWMxDC Name:  PWMxDC Address:  0x38C,0x390 PWM Duty Cycle Register Bit 15 14 13 12 11 10 9 8 DCH[7:0] Access Reset x Bit 7 x x x x x x x 6 5 4 3 2 1 0 DCL[1:0] Access Reset x x Bits 15:8 – DCH[7:0] PWM Duty Cycle Most Significant bits These bits are the MSbs of the PWM duty cycle. Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Bits 7:6 – DCL[1:0] PWM Duty Cycle Least Significant bits These bits are the LSbs of the PWM duty cycle. Reset States: POR/BOR = xx All Other Resets = uu © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 443 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31. (CWG) Complementary Waveform Generator Module The Complementary Waveform Generator (CWG) produces half-bridge, full-bridge, and steering of PWM waveforms. It is backwards compatible with previous CCP functions. The PIC16(L)F18455/56 family has 3 instance(s) of the CWG module. The CWG has the following features: • • • • • 31.1 Six Operating modes: – Synchronous Steering mode – Asynchronous Steering mode – Full-Bridge mode, Forward – Full-Bridge mode, Reverse – Half-Bridge mode – Push-Pull mode Output Polarity Control Output Steering Independent 6-Bit Rising and Falling Event Dead-Band Timers: – Clocked dead band – Independent rising and falling dead-band enables Auto-Shutdown Control With: – Selectable shutdown sources – Auto-restart option – Auto-shutdown pin override control Fundamental Operation The CWG generates two output waveforms from the selected input source. The off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time delay immediately where neither output is driven. This is referred to as dead time and is covered in 31.7 Dead-Band Control. It may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all. In this case, the active drive must be terminated before the Fault condition causes damage. This is referred to as auto-shutdown and is covered in 31.11 Auto-Shutdown. 31.2 Operating Modes The CWG module can operate in six different modes, as specified by the MODE bits: • • • • • • Half-Bridge mode Push-Pull mode Asynchronous Steering mode Synchronous Steering mode Full-Bridge mode, Forward Full-Bridge mode, Reverse © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 444 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... All modes accept a single pulse data input, and provide up to four outputs as described in the following sections. All modes include auto-shutdown control as described in 31.11 Auto-Shutdown Important:  Except as noted for Full-Bridge mode (31.2.3 Full-Bridge Modes), mode changes should only be performed while EN = 0. 31.2.1 Half-Bridge Mode In Half-Bridge mode, two output signals are generated as true and inverted versions of the input as illustrated in Figure 31-1. A non-overlap (dead-band) time is inserted between the two outputs to prevent shoot-through current in various power supply applications. Dead-band control is described in 31.7 Dead-Band Control. The output steering feature cannot be used in this mode. A basic block diagram of this mode is shown in Figure 31-2. The unused outputs CWGxC and CWGxD drive similar signals, with polarity independently controlled by the POLC and POLD bits, respectively. Figure 31-1. CWG Half-Bridge Mode Operation Rev. 30-000097A 4/14/2017 CWGx_clock CWGxA CWGxC Falling Event Dead Band Rising Event Dead Band Rising Event D Falling Event Dead Band CWGxB CWGxD CWGx_data Note:  CWGx_rising_src = CCP1_out, CWGx_falling_src = ~CCP1_out © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 445 Filename: Title: Last Edit: First Used: Notes: 10-000209D.vsd SIMPLIFIED CWG BLOCK DIAGRAM (HALF-BRIDGE MODE) 2/2/2016 PIC18(L)F6xK40 (CWG) Complementary PIC16(L)F18455/56 Waveform Generator Modul... Figure 31-2. Simplified CWG Block Diagram (Half-Bridge Mode, MODE = 100) LSAC Rev. 10-000209D 2/2/2016 ‘1’ 00 ‘0’ 01 High-Z 10 11 Rising Dead-Band Block CWG Clock clock data out CWG Data 1 CWG Data A data in 0 POLA CWGxA LSBD ‘1’ 00 ‘0’ 01 High-Z 10 Falling Dead-Band Block clock data out CWG Data B data in 11 1 CWG Data CWG Data Input 0 POLB D CWGxB Q E LSAC EN ‘1’ 00 ‘0’ 01 High-Z 10 11 1 0 POLC Auto-shutdown source (CWGxAS1 register) S CWGxC Q LSBD R REN SHUTDOWN = 0 ‘1’ 00 ‘0’ 01 High-Z 10 11 1 0 POLD CWGxD SHUTDOWN FREEZE D Q CWG Data © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 446 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.2.2 Push-Pull Mode In Push-Pull mode, two output signals are generated, alternating copies of the input as illustrated in Figure 31-3. This alternation creates the push-pull effect required for driving some transformer-based power supply designs. Steering modes are not used in Push-Pull mode. A basic block diagram for the Push-Pull mode is shown in Figure 31-4. The push-pull sequencer is reset whenever EN = 0 or if an auto-shutdown event occurs. The sequencer is clocked by the first input pulse, and the first output appears on CWG1A. The unused outputs CWGxC and CWGxD drive copies of CWGxA and CWGxB, respectively, but with polarity controlled by the POLC and POLD bits of the CWGxCON1 register, respectively. Figure 31-3. CWG Push-Pull Mode Operation Rev. 30-000098A 4/14/2017 CWGx clock Input source CWGxA CWGxB © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 447 Filename: Title: Last Edit: First Used: Notes: 10-000210D.vsd SIMPLIFIED CWG BLOCK DIAGRAM (PUSH-PULL MODE) 2/2/2016 PIC18(L)F6xK40 (CWG) Complementary PIC16(L)F18455/56 Waveform Generator Modul... Figure 31-4. Simplified CWG Block Diagram (Push-Pull Mode, MODE = 101) LSAC Rev. 10-000210D 2/2/2016 ‘1’ 00 ‘0’ 01 High-Z 10 11 CWG Data 1 CWG Data A 0 CWGxA POLA D LSBD Q Q ‘1’ 00 ‘0’ 01 High-Z 10 11 CWG Data B 1 CWG Data Input CWG Data D 0 CWGxB POLB Q LSAC E ‘1’ 00 ‘0’ 01 High-Z 10 EN 11 1 0 CWGxC POLC Auto-shutdown source (CWGxAS1 register) S Q LSBD R REN ‘1’ 00 ‘0’ 01 High-Z 10 SHUTDOWN = 0 11 1 0 CWGxD POLD SHUTDOWN FREEZE D Q CWG Data © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 448 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.2.3 Full-Bridge Modes In Forward and Reverse Full-Bridge modes, three outputs drive static values while the fourth is modulated by the input data signal. The mode selection may be toggled between forward and reverse by toggling the MODE bit of the CWGxCON0 while keeping MODE static, without disabling the Filename: CWG module.10-000263A.vsd When connected, as shown in Figure 31-5, the outputs are appropriate for a full-bridge Title: Example of Full-Bridge Application motor driver. Each CWG output signal has independent polarity control, so the circuit can be adapted to Last Edit: 12/8/2015 and low-active drivers. A simplified block diagram for the Full-Bridge modes is shown in Firsthigh-active Used: PIC18(L)F2x/4xK40 Note: Figure 31-6. Figure 31-5. Example of Full-Bridge Application Rev. 10-000263A 12/8/2015 VDD FET Driver QA QC FET Driver CWGxA CWGxB CWGxC CWGxD © 2018 Microchip Technology Inc. LOAD FET Driver FET Driver QB Datasheet Preliminary QD DS40002038B-page 449 Filename: Title: Last Edit: First Used: Notes: 10-000212D.vsd SIMPLIFIED CWG BLOCK DIAGRAM (FULL-BRIDGE MODES) 2/2/2016 PIC18(L)F6xK40 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... Figure 31-6. Simplified CWG Block Diagram (Forward and Reverse Full-Bridge Modes) Rev. 10-000212D 2/2/2016 MODE = 010: Forward LSAC MODE = 011: Reverse Rising Dead-Band Block CWG Clock clock signal out signal in D CWG Data 00 ‘0’ 01 High-Z 10 11 CWG Data MODE ‘1’ 1 CWG Data A 0 CWGxA POLA Q Q LSBD cwg data signal in signal out clock CWG Clock ‘1’ 00 ‘0’ 01 High-Z 10 11 Falling Dead-Band Block CWG Data Input CWG Data 1 CWG Data B 0 CWGxB POLB D Q LSAC E EN ‘1’ 00 ‘0’ 01 High-Z 10 11 1 CWG Data C Auto-shutdown source (CWGxAS1 register) 0 CWGxC POLC S Q LSBD R REN SHUTDOWN = 0 ‘1’ 00 ‘0’ 01 High-Z 10 11 1 CWG Data D 0 POLD CWGxD SHUTDOWN FREEZE D Q CWG Data © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 450 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... In Forward Full-Bridge mode (MODE = 010), CWGxA is driven to its active state, CWGxB and CWGxC are driven to their inactive state, and CWGxD is modulated by the input signal, as shown in Figure 31-7. In Reverse Full-Bridge mode (MODE = 011), CWGxC is driven to its active state, CWGxA and CWGxD are driven to their inactive states, and CWGxB is modulated by the input signal, as shown in Figure 31-7. In Full-Bridge mode, the dead-band period is used when there is a switch from forward to reverse or viceversa. This dead-band control is described in 31.7 Dead-Band Control, with additional details in 31.8 Rising Edge and Reverse Dead Band and 31.9 Falling Edge and Forward Dead Band. Steering modes are not used with either of the Full-Bridge modes. The mode selection may be toggled between forward and reverse toggling the MODE bit of the CWGxCON0 while keeping MODE static, without disabling the CWG module. Figure 31-7. Example of Full-Bridge Output Rev. 30-000099A 4/14/2017 Forward Mode Period CWGxA (2) CWGxB (2) CWGxC (2) Pulse Width CWGxD (2) (1) Reverse Mode (1) Period CWGxA (2) Pulse Width CWGxB (2) CWGxC (2) CWGxD (2) (1) (1) Note:  1. A rising CWG data input creates a rising event on the modulated output. 2. Output signals shown as active-high; all POLy bits are clear. 31.2.3.1 Direction Change in Full-Bridge Mode In Full-Bridge mode, changing MODE controls the forward/reverse direction. Direction changes occur on the next rising edge of the modulated input. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 451 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... A direction change is initiated in software by changing the MODE bits. The sequence is illustrated in Figure 31-8. • • • The associated active output CWGxA and the inactive output CWGxC are switched to drive in the opposite direction. The previously modulated output CWGxD is switched to the inactive state, and the previously inactive output CWGxB begins to modulate. CWG modulation resumes after the direction-switch dead band has elapsed. 31.2.3.2 Dead-Band Delay in Full-Bridge Mode Dead-band delay is important when either of the following conditions is true: 1. 2. The direction of the CWG output changes when the duty cycle of the data input is at or near 100%, or The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. The dead-band delay is inserted only when changing directions, and only the modulated output is affected. The statically-configured outputs (CWGxA and CWGxC) are not afforded dead band, and switch essentially simultaneously. The following figure shows an example of the CWG outputs changing directions from forward to reverse, at near 100% duty cycle. In this example, at time t1, the output of CWGxA and CWGxD become inactive, while output CWGxC becomes active. Since the turn-off time of the power devices is longer than the turnon time, a shoot-through current will flow through power devices QC and QD for the duration of ‘t’. The same phenomenon will occur to power devices QA and QB for the CWG direction change from reverse to forward. When changing the CWG direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: 1. 2. Reduce the CWG duty cycle for one period before changing directions. Use switch drivers that can drive the switches off faster than they can drive them on. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 452 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... Figure 31-8. Example of PWM Direction Change at Near 100% Duty Cycle Rev. 30-000100A 4/14/2017 Forward Period t1 Reverse Period CWGxA Pulse Width CWGxB CWGxC CWGxD Pulse Width T ON External Switch C TOFF External Switch D Potential ShootThrough Current 31.2.4 T = TOFF - TON Steering Modes In both Synchronous and Asynchronous Steering modes, the modulated input signal can be steered to any combination of four CWG outputs. A fixed-value will be presented on all the outputs not used for the PWM output. Each output has independent polarity, steering, and shutdown options. Dead-band control is not used in either steering mode. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 453 Filename: Title: Last Edit: First Used: Notes: 10-000211D.vsd SIMPLIFIED CWG BLOCK DIAGRAM (OUTPUT STEERING MODES) 5/30/2017 PIC18(L)F6xK40 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... Figure 31-9. Simplified CWG Block Diagram (Output Steering Modes) Rev. 10-000211D 5/30/2017 MODE = 000: Asynchronous LSAC MODE = 001: Synchronous ‘1’ 00 ‘0’ 01 High-Z 10 11 CWG Data A 1 1 POLA 0 CWGxA 0 OVRA STRA CWG Data CWG Data Input LSBD ‘1’ 00 ‘0’ 01 High-Z 10 11 D CWG Data B Q E 1 1 POLB 0 CWGxB 0 OVRB EN STRB LSAC ‘1’ 00 ‘0’ 01 High-Z 10 11 CWG Data C Auto-shutdown source (CWGxAS1 register) S Q 1 1 POLC 0 CWGxC 0 R OVRC STRC REN LSBD SHUTDOWN = 0 ‘1’ 00 ‘0’ 01 High-Z 10 11 CWG Data D 1 1 POLD 0 CWGxD 0 OVRD SHUTDOWN STRD FREEZE D Q CWG Data © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 454 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... For example, when STRA = 0 then the corresponding pin is held at the level defined by OVRA. When STRA = 1, then the pin is driven by the modulated input signal. The POLy bits control the signal polarity only when STRy = 1. The CWG auto-shutdown operation also applies in Steering modes as described in 31.11 AutoShutdown”. An auto-shutdown event will only affect pins that have STRy = 1. 31.2.4.1 Synchronous Steering Mode In Synchronous Steering mode (MODE=001), changes to steering selection registers take effect on the next rising edge of the modulated data input (see figure below). In Synchronous Steering mode, the output will always produce a complete waveform. Important:  Only the STRx bits are synchronized; the OVRx bits are not synchronized. Figure 31-10. Example of Synchronous Steering (MODE = 001) Rev. 30-000101A 4/14/2017 CWGx clock Input source CWGxA CWGxB 31.2.4.2 Asynchronous Steering Mode In Asynchronous mode (MODE = 000), steering takes effect at the end of the instruction cycle that writes to STRx. In Asynchronous Steering mode, the output signal may be an incomplete waveform (see figure below). This operation may be useful when the user firmware needs to immediately remove a signal from the output pin. Figure 31-11. Example of Asynchronous Steering (MODE = 000) Rev. 30-000102A 4/14/2017 CWGx INPUT End of Instruction Cycle End of Instruction Cycle STRA CWGxA CWGxA Follows CWGx data input © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 455 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.3 Start-up Considerations The application hardware must use the proper external pull-up and/or pull-down resistors on the CWG output pins. This is required because all I/O pins are forced to high-impedance at Reset. The polarity control bits (POLy) allow the user to choose whether the output signals are active-high or active-low. 31.4 Clock Source The clock source is used to drive the dead-band timing circuits. The CWG module allows the following clock sources to be selected: • • FOSC (system clock) HFINTOSC When the HFINTOSC is selected, the HFINTOSC will be kept running during Sleep. Therefore, CWG modes requiring dead band can operate in Sleep, provided that the CWG data input is also active during Sleep. The clock sources are selected using the CS bit. The system clock FOSC, is disabled in Sleep and thus dead-band control cannot be used. 31.5 Selectable Input Sources The CWG generates the output waveforms from the input sources which are selected with the ISM bits as shown below. Table 31-1. CWG Data Input Sources ISM Data Source 1111 CCP5_out 1110 CLC4_out 1101 CLC3_out 1100 CLC2_out 1011 CLC1_out 1010 DSM1_out 1001 C2_out 1000 C1_out 0111 NCO1_out 0110 PWM7_out 0101 PWM6_out 0100 CCP4_out 0011 CCP3_out 0010 CCP2_out © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 456 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... ISM Data Source 0001 CCP1_out 0000 Pin selected by CWGxINPPS 31.6 Output Control 31.6.1 CWG Outputs Each CWG output can be routed to a Peripheral Pin Select (PPS) output via the RxyPPS register. Related Links 15. (PPS) Peripheral Pin Select Module 31.6.2 Polarity Control The polarity of each CWG output can be selected independently. When the output polarity bit is set, the corresponding output is active-high. Clearing the output polarity bit configures the corresponding output as active-low. However, polarity does not affect the override levels. Output polarity is selected with the POLy bits. Auto-shutdown and steering options are unaffected by polarity. 31.7 Dead-Band Control The dead-band control provides non-overlapping PWM signals to prevent shoot-through current in PWM switches. Dead-band operation is employed for Half-Bridge and Full-Bridge modes. The CWG contains two 6-bit dead-band counters. One is used for the rising edge of the input source control in Half-Bridge mode or for reverse dead-band Full-Bridge mode. The other is used for the falling edge of the input source control in Half-Bridge mode or for forward dead band in Full-Bridge mode. Dead band is timed by counting CWG clock periods from zero up to the value in the rising or falling deadband counter registers. 31.7.1 Dead-Band Functionality in Half-Bridge mode In Half-Bridge mode, the dead-band counters dictate the delay between the falling edge of the normal output and the rising edge of the inverted output. This can be seen in Figure 31-1. 31.7.2 Dead-Band Functionality in Full-Bridge mode In Full-Bridge mode, the dead-band counters are used when undergoing a direction change. The MODE bit can be set or cleared while the CWG is running, allowing for changes from Forward to Reverse mode. The CWGxA and CWGxC signals will change immediately upon the first rising input edge following a direction change, but the modulated signals (CWGxB or CWGxD, depending on the direction of the change) will experience a delay dictated by the dead-band counters. 31.8 Rising Edge and Reverse Dead Band In Half-Bridge mode, the rising edge dead band delays the turn-on of the CWGxA output after the rising edge of the CWG data input. In Full-Bridge mode, the reverse dead-band delay is only inserted when changing directions from Forward mode to Reverse mode, and only the modulated output CWGxB is affected. The 31.15.8 CWGxDBR register determines the duration of the dead-band interval on the rising edge of the input source signal. This duration is from 0 to 64 periods of the CWG clock. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 457 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... Dead band is always initiated on the edge of the input source signal. A count of zero indicates that no dead band is present. If the input source signal reverses polarity before the dead-band count is completed, then no signal will be seen on the respective output. The CWGxDBR register value is double-buffered. When EN = 0, the buffer is loaded when CWGxDBR is written. When EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the data input, after the LD bit is set. Refer to the following figure for an example. Figure 31-12. Dead-Band Operation, CWGxDBR = 0x01, CWGxDBF = 0x02 Rev. 30-000103A 4/14/2017 cwg_clock Input Source CWGxA CWGxB 31.9 Falling Edge and Forward Dead Band In Half-Bridge mode, the falling edge dead band delays the turn-on of the CWGxB output at the falling edge of the CWG data input. In Full-Bridge mode, the forward dead-band delay is only inserted when changing directions from Reverse mode to Forward mode, and only the modulated output CWGxD is affected. The 31.15.9 CWGxDBF register determines the duration of the dead-band interval on the falling edge of the input source signal. This duration is from zero to 64 periods of CWG clock. Dead-band delay is always initiated on the edge of the input source signal. A count of zero indicates that no dead band is present. If the input source signal reverses polarity before the dead-band count is completed, then no signal will be seen on the respective output. The CWGxDBF register value is double-buffered. When EN = 0, the buffer is loaded when CWGxDBF is written. When EN = 1, then the buffer will be loaded at the rising edge following the first falling edge of the data input after the LD is set. Refer to the following figure for an example. Figure 31-13. Dead-Band Operation, CWGxDBR = 0x03, CWGxDBF = 0x06, Source Shorter Than Dead Band Rev. 30-000104A 4/14/2017 cwg_clock Input Source CWGxA CWGxB source shorter than dead band © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 458 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.10 Dead-Band Jitter When the rising and falling edges of the input source are asynchronous to the CWG clock, it creates jitter in the dead-band time delay. The maximum jitter is equal to one CWG clock period. Refer to the equations below for more details. Equation 31-1. Dead-Band Delay Time Calculation 1 ����� − ����_��� = • ��� < 5: 0 > ����_����� ����� − ����_��� = 1 • ��� < 5: 0 > + 1 ����_����� � ������ = ����� − ����_��� − ����� − ����_��� � ������ = 1 ����_����� ����� − ����_��� = ����� − ����_��� + � ������ Equation 31-2. Dead-Band Delay Example Calculation ��� < 5: 0 > = 0�0� = 10 ����_����� = 8 ��� � ������ = 1 = 125�� 8 ��� ����� − ����_��� = 125�� • 10 = 125�� ����� − ����_��� = 1.25�� + 0.125 �� = 1.37�� 31.11 Filename: Title: Last Edit: First Used: Notes: 10-000172C.vsd CWG SHUTDOWN BLOCK DIAGRAM 8/7/2015 PIC16(L)F1614/5/8/9 LECW Auto-Shutdown Auto-shutdown is a method to immediately override the CWG output levels with specific overrides that allow for safe shutdown of the circuit. The shutdown state can be either cleared automatically or held until cleared by software. The auto-shutdown circuit is illustrated in the following figure. Figure 31-14. CWG Shutdown Block Diagram Write ‘1’ to SHUTDOWN bit Rev. 10-000172C 8/7/2015 PPS AS0E CWGxINPPS C1OUT_sync AS4E C2OUT_sync AS5E TMR2_postscaled AS1E TMR4_postscaled AS2E S Q SHUTDOWN S D FREEZE REN Write ‘0’ to SHUTDOWN bit Q CWG_shutdown R CWG_data TMR6_postscaled AS3E CK 31.11.1 Shutdown The shutdown state can be entered by either of the following two methods: • Software Generated © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 459 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... • External Input 31.11.1.1 Software Generated Shutdown Setting the SHUTDOWN bit will force the CWG into the shutdown state. When the auto-restart is disabled, the shutdown state will persist as long as the SHUTDOWN bit is set. When auto-restart is enabled, the SHUTDOWN bit will clear automatically and resume operation on the next rising edge event. The SHUTDOWN bit indicates when a shutdown condition exists. The bit may be set or cleared in software or by hardware. 31.11.1.2 External Input Source External shutdown inputs provide the fastest way to safely suspend CWG operation in the event of a Fault condition. When any of the selected shutdown inputs goes active, the CWG outputs will immediately go to the selected override levels without software delay. The override levels are selected by the LSBD and LSAC bits. Several input sources can be selected to cause a shutdown condition. All input sources are active-low. The shutdown input sources are individually enabled by the ASyE bits as shown in the following table: Table 31-2. Shutdown Sources ASyE Source AS6E CLC2_out/CLC3_out (low causes shutdown) AS5E CMP2_out (low causes shutdown) AS4E CMP1_out (low causes shutdown) AS3E TMR6_postscaled (high causes shutdown) AS2E TMR4_postscaled (high causes shutdown) AS1E TMR2_postscaled (high causes shutdown) AS0E Pin selected by CWGxPPS (low causes shutdown) Important:  Shutdown inputs are level sensitive, not edge sensitive. The shutdown state cannot be cleared, except by disabling auto-shutdown, as long as the shutdown input level persists. 31.11.1.3 Pin Override Levels The levels driven to the CWG outputs during an auto-shutdown event are controlled by the LSBD and LSAC bits. The LSBD bits control CWGxB/D output levels, while the LSAC bits control the CWGxA/C output levels. 31.11.1.4 Auto-Shutdown Interrupts When an auto-shutdown event occurs, either by software or hardware setting SHUTDOWN, the CWGxIF flag bit of the PIRx register is set. 31.11.2 Auto-Shutdown Restart After an auto-shutdown event has occurred, there are two ways to resume operation: • • Software controlled Auto-restart © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 460 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... In either case, the shutdown source must be cleared before the restart can take place. That is, either the shutdown condition must be removed, or the corresponding ASyE bit must be cleared. 31.11.2.1 Software-Controlled Restart When the REN bit is clear (REN = 0), the CWG module must be restarted after an auto-shutdown event through software. Once all auto-shutdown sources are removed, the software must clear SHUTDOWN. Once SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input. Important:  The SHUTDOWN bit cannot be cleared in software if the auto-shutdown condition is still present. Figure 31-15. SHUTDOWN FUNCTIONALITY, AUTO-RESTART DISABLED (REN = 0, LSAC = 01, LSBD = 01) Rev. 30-000105A 4/14/2017 Shutdown Event Ceases REN Cleared by Software CWG Input Source Shutdown Source SHUTDOWN Tri-State (No Pulse) CWGxA CWGxC CWGxB CWGxD Tri-State (No Pulse) No Shutdown Shutdown Output Resumes 31.11.2.2 Auto-Restart When the REN bit is set (REN = 1), the CWG module will restart from the shutdown state automatically. Once all auto-shutdown conditions are removed, the hardware will automatically clear SHUTDOWN. Once SHUTDOWN is cleared, the CWG module will resume operation upon the first rising edge of the CWG data input. Important:  The SHUTDOWN bit cannot be cleared in software if the auto-shutdown condition is still present. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 461 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... Figure 31-16. SHUTDOWN FUNCTIONALITY, AUTO-RESTART ENABLED (REN = 1, LSAC = 01, LSBD = 01) Rev. 30-000106A 4/14/2017 Shutdown Event Ceases REN auto-cleared by hardware CWG Input Source Shutdown Source SHUTDOWN Tri-State (No Pulse) CWGxA CWGxB CWGxC CWGxD Tri-State (No Pulse) No Shutdown Shutdown 31.12 Output Resumes Operation During Sleep The CWG module operates independently from the system clock and will continue to run during Sleep, provided that the clock and input sources selected remain active. The HFINTOSC remains active during Sleep when all the following conditions are met: • • • CWG module is enabled Input source is active HFINTOSC is selected as the clock source, regardless of the system clock source selected. In other words, if the HFINTOSC is simultaneously selected as the system clock and the CWG clock source, when the CWG is enabled and the input source is active, then the CPU will go idle during Sleep, but the HFINTOSC will remain active and the CWG will continue to operate. This will have a direct effect on the Sleep mode current. 31.13 Configuring the CWG 1. Ensure that the TRIS control bits corresponding to CWG outputs are set so that all are configured as inputs, ensuring that the outputs are inactive during setup. External hardware should ensure that pin levels are held to safe levels. 2. Clear the EN bit, if not already cleared. 3. Configure the MODE bits to set the output operating mode. 4. Configure the POLy bits to set the output polarities. 5. Configure the ISM bits to select the data input source. 6. If a steering mode is selected, configure the STRy bits to select the desired output on the CWG outputs. 7. Configure the LSBD and LSAC bits to select the auto-shutdown output override states (this is necessary even if not using auto-shutdown because start-up will be from a shutdown state). 8. If auto-restart is desired, set the REN bit. 9. If auto-shutdown is desired, configure the ASyE bits to select the shutdown source. 10. Set the desired rising and falling dead-band times with the CWGxDBR and CWGxDBF registers. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 462 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 11. Select the clock source with the CS bits. 12. Set the EN bit to enable the module. 13. Clear the TRIS bits that correspond to the CWG outputs to set them as outputs. If auto-restart is to be used, set the REN bit and the SHUTDOWN bit will be cleared automatically. Otherwise, clear the SHUTDOWN bit in software to start the CWG. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 463 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.14 Register Summary - CWG Control Address Name Bit Pos. 0x060C CWG1CLK 7:0 0x060D CWG1ISM 7:0 0x060E CWG1DBR 7:0 0x060F CWG1DBF 7:0 0x0610 CWG1CON0 7:0 0x0611 CWG1CON1 7:0 0x0612 CWG1AS0 7:0 0x0613 CWG1AS1 7:0 0x0614 CWG1STR 7:0 CS ISM[3:0] DBR[5:0] DBF[5:0] EN LD MODE[2:0] IN SHUTDOWN OVRD REN OVRC POLD LSBD[1:0] POLC LSAC[1:0] AS4E AS3E AS2E AS1E AS0E OVRB OVRA STRD STRC STRB STRA Reserved 0x0616 CWG2CLK 7:0 0x0617 CWG2ISM 7:0 0x0618 CWG2DBR 7:0 DBR[5:0] 0x0619 CWG2DBF 7:0 DBF[5:0] CWG2CON0 7:0 0x061B CWG2CON1 7:0 0x061C CWG2AS0 7:0 0x061D CWG2AS1 7:0 0x061E CWG2STR 7:0 POLA AS5E 0x0615 0x061A POLB CS ISM[3:0] EN LD MODE[2:0] IN SHUTDOWN REN OVRD OVRC POLD LSBD[1:0] POLC POLB POLA LSAC[1:0] AS5E AS4E AS3E AS2E AS1E AS0E OVRB OVRA STRD STRC STRB STRA 0x061F ... Reserved 0x068B 0x068C CWG3CLK 7:0 0x068D CWG3ISM 7:0 0x068E CWG3DBR 7:0 0x068F CWG3DBF 7:0 0x0690 CWG3CON0 7:0 0x0691 CWG3CON1 7:0 0x0692 CWG3AS0 7:0 0x0693 CWG3AS1 7:0 0x0694 CWG3STR 7:0 31.15 CS ISM[3:0] DBR[5:0] DBF[5:0] EN LD MODE[2:0] IN SHUTDOWN OVRD REN OVRC POLD LSBD[1:0] POLC POLB POLA LSAC[1:0] AS5E AS4E AS3E AS2E AS1E AS0E OVRB OVRA STRD STRC STRB STRA Register Definitions: CWG Control Long bit name prefixes for the CWG peripherals are shown in the table below. Refer to the "Long Bit Names Section" for more information. Table 31-3. CWG Bit Name Prefixes Peripheral Bit Name Prefix CWG1 CWG1 CWG2 CWG2 CWG3 CWG3 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 464 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... Related Links 1.4.2.2 Long Bit Names © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 465 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.15.1 CWGxCON0 Name:  CWGxCON0 Address:  0x610,0x61A,0x690 CWG Control Register 0 Bit Access Reset 7 6 EN LD 5 4 3 2 1 0 R/W R/W/HC R/W R/W R/W 0 0 0 0 0 MODE[2:0] Bit 7 – EN CWG1 Enable bit Value 1 0 Description Module is enabled Module is disabled Bit 6 – LD  CWG1 Load Buffers bit(1) Value 1 0 Description Dead-band count buffers to be loaded on CWG data rising edge, following first falling edge after this bit is set Buffers remain unchanged Bits 2:0 – MODE[2:0] CWG1 Mode bits Value 111 110 101 100 011 010 001 000 Description Reserved Reserved CWG outputs operate in Push-Pull mode CWG outputs operate in Half-Bridge mode CWG outputs operate in Reverse Full-Bridge mode CWG outputs operate in Forward Full-Bridge mode CWG outputs operate in Synchronous Steering mode CWG outputs operate in Asynchronous Steering mode Note:  1. This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 466 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.15.2 CWGxCON1 Name:  CWGxCON1 Address:  0x611,0x61B,0x691 CWG Control Register 1 Bit 7 6 Access Reset 3 2 1 0 IN 5 4 POLD POLC POLB POLA RO R/W R/W R/W R/W x 0 0 0 0 Bit 5 – IN CWG Input Value bit (read-only) Value 1 0 Description CWG input is a logic 1 CWG input is a logic 0 Bits 0, 1, 2, 3 – POLy CWG Output 'y' Polarity bit Value 1 0 Description Signal output is inverted polarity Signal output is normal polarity © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 467 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.15.3 CWGxCLK Name:  CWGxCLK Address:  0x60C,0x616,0x68C CWGx Clock Input Selection Register Bit 7 6 5 4 3 2 1 0 CS Access R/W Reset 0 Bit 0 – CS Clock Source CWG Clock Source Selection Select bits Value 1 0 Description HFINTOSC (remains operating during Sleep) FOSC © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 468 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.15.4 CWGxISM Name:  CWGxISM Address:  0x60D,0x617,0x68D CWGx Input Selection Register Bit 7 6 5 4 3 2 1 0 ISM[3:0] Access Reset R/W R/W R/W R/W 0 0 0 0 Bits 3:0 – ISM[3:0] CWG Data Input Source Select bits Table 31-4. CWG Data Input Sources ISM Data Source 1111 CCP5_out 1110 CLC4_out 1101 CLC3_out 1100 CLC2_out 1011 CLC1_out 1010 DSM1_out 1001 C2_out 1000 C1_out 0111 NCO1_out 0110 PWM7_out 0101 PWM6_out 0100 CCP4_out 0011 CCP3_out 0010 CCP2_out 0001 CCP1_out 0000 Pin selected by CWGxINPPS © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 469 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.15.5 CWGxSTR Name:  CWGxSTR Address:  0x614,0x61E,0x694 CWG Steering Control Register (1) Bit Access Reset 7 6 5 4 3 2 1 0 OVRD OVRC OVRB OVRA STRD STRC STRB STRA R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 4, 5, 6, 7 – OVRy Steering Data OVR'y' bit Value x 1 0 Condition STRy = 1 Description CWGx'y' output has the CWG data input waveform with polarity control from POLy bit STRy = 0 and POLy = x CWGx'y' output is high STRy = 0 and POLy = x CWGx'y' output is low Bits 0, 1, 2, 3 – STRy  STR'y' Steering Enable bit(2) Value 1 0 Description CWGx'y' output has the CWG data input waveform with polarity control from POLy bit CWGx'y' output is assigned to value of OVRy bit Note:  1. The bits in this register apply only when MODE = '00x' (31.15.1 CWGxCON0, Steering modes). 2. This bit is double-buffered when MODE = '001'. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 470 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.15.6 CWGxAS0 Name:  CWGxAS0 Address:  0x612,0x61C,0x692 CWG Auto-Shutdown Control Register 0 Bit Access Reset 7 6 SHUTDOWN REN 5 4 3 R/W/HS/HC R/W R/W R/W R/W R/W 0 0 0 1 0 1 LSBD[1:0] 2 1 0 LSAC[1:0] Bit 7 – SHUTDOWN  Auto-Shutdown Event Status bit(1,2) Value 1 0 Description An auto-shutdown state is in effect No auto-shutdown event has occurred Bit 6 – REN Auto-Restart Enable bit Value 1 0 Description Auto-restart is enabled Auto-restart is disabled Bits 5:4 – LSBD[1:0] CWGxB and CWGxD Auto-Shutdown State Control bits Value 11 10 01 00 Description A logic ‘1’ is placed on CWGxB/D when an auto-shutdown event occurs. A logic ‘0’ is placed on CWGxB/D when an auto-shutdown event occurs. Pin is tri-stated on CWGxB/D when an auto-shutdown event occurs. The inactive state of the pin, including polarity, is placed on CWGxB/D after the required dead-band interval when an auto-shutdown event occurs. Bits 3:2 – LSAC[1:0] CWGxA and CWGxC Auto-Shutdown State Control bits Value 11 10 01 00 Description A logic ‘1’ is placed on CWGxA/C when an auto-shutdown event occurs. A logic ‘0’ is placed on CWGxA/C when an auto-shutdown event occurs. Pin is tri-stated on CWGxA/C when an auto-shutdown event occurs. The inactive state of the pin, including polarity, is placed on CWGxA/C after the required dead-band interval when an auto-shutdown event occurs. Note:  1. This bit may be written while EN = 0 (31.15.1 CWGxCON0), to place the outputs into the shutdown configuration. 2. The outputs will remain in auto-shutdown state until the next rising edge of the CWG data input after this bit is cleared. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 471 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.15.7 CWGxAS1 Name:  CWGxAS1 Address:  0x613,0x61D,0x693 CWG Auto-Shutdown Control Register 1 Bit 7 6 Access Reset 5 4 3 2 1 0 AS5E AS4E AS3E AS2E AS1E AS0E R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 Bits 0, 1, 2, 3, 4, 5 – ASyE CWG Auto-shutdown Source ASyE Enable bit(1) Table 31-5. Shutdown Sources ASyE Source AS6E CLC2_out/CLC3_out (low causes shutdown) AS5E CMP2_out (low causes shutdown) AS4E CMP1_out (low causes shutdown) AS3E TMR6_postscaled (high causes shutdown) AS2E TMR4_postscaled (high causes shutdown) AS1E TMR2_postscaled (high causes shutdown) AS0E Pin selected by CWGxPPS (low causes shutdown) Value 1 0 Description Auto-shutdown for source ASyE is enabled Auto-shutdown for source ASyE is disabled Note:  This bit may be written while EN = 0 (31.15.1 CWGxCON0), to place the outputs into the shutdown configuration. The outputs will remain in auto-shutdown state until the next rising edge of the CWG data input after this bit is cleared. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 472 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.15.8 CWGxDBR Name:  CWGxDBR Address:  0x60E,0x618,0x68E CWG Rising Dead-Band Count Register Bit 7 6 5 4 3 2 1 0 DBR[5:0] Access Reset R/W R/W R/W R/W R/W R/W x x x x x x Bits 5:0 – DBR[5:0] CWG Rising Edge Triggered Dead-Band Count bits Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value n 0 Description Dead band is active no less than n, and no more than n+1, CWG clock periods after the rising edge 0 CWG clock periods. Dead-band generation is bypassed © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 473 PIC16(L)F18455/56 (CWG) Complementary Waveform Generator Modul... 31.15.9 CWGxDBF Name:  CWGxDBF Address:  0x60F,0x619,0x68F CWG Falling Dead-Band Count Register Bit 7 6 5 4 3 2 1 0 DBF[5:0] Access Reset R/W R/W R/W R/W R/W R/W x x x x x x Bits 5:0 – DBF[5:0] CWG Falling Edge Triggered Dead-Band Count bits Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value n 0 Description Dead band is active no less than n, and no more than n+1, CWG clock periods after the falling edge 0 CWG clock periods. Dead-band generation is bypassed © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 474 PIC16(L)F18455/56 (DSM) Data Signal Modulator Module 32. (DSM) Data Signal Modulator Module The Data Signal Modulator (DSM) is a peripheral which allows the user to mix a data stream, also known as a modulator signal, with a carrier signal to produce a modulated output. Both the carrier and the modulator signals are supplied to the DSM module either internally, from the output of a peripheral, or externally through an input pin. The modulated output signal is generated by performing a logical “AND” operation of both the carrier and modulator signals and then provided to the MDOUT pin. The carrier signal is comprised of two distinct and separate signals. A carrier high (CARH) signal and a carrier low (CARL) signal. During the time in which the modulator (MOD) signal is in a logic high state, the DSM mixes the carrier high signal with the modulator signal. When the modulator signal is in a logic low state, the DSM mixes the carrier low signal with the modulator signal. Using this method, the DSM can generate the following types of Key Modulation schemes: • • • Frequency-Shift Keying (FSK) Phase-Shift Keying (PSK) On-Off Keying (OOK) Additionally, the following features are provided within the DSM module: • • • • • Carrier Synchronization Carrier Source Polarity Select Programmable Modulator Data Modulated Output Polarity Select Peripheral Module Disable, which provides the ability to place the DSM module in the lowest power consumption mode The figure below shows a Simplified Block Diagram of the Data Signal Modulator peripheral. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 475 Filename: Title: Last Edit: First Used: Notes: 10-000248F.vsd DSM BLOCK DIAGRAM for PIC18(L)F6xK40 1/19/2016 PIC18(L)F6xK40 (MVAC/MVAK) PIC16(L)F18455/56 (DSM) Data Signal Modulator Module Figure 32-1. Simplified Block Diagram of the Data Signal Modulator MDCHS Rev. 10-000248F 1/19/2016 Data Signal Modulator 0000 See MDCARH Register CARH MDCHPOL D SYNC 1111 Q 1 MDSRCS 0 00000 MDCHSYNC RxyPPS See MDSRC Register MOD PPS MDOPOL 11111 MDCLS D SYNC 0000 Q 1 0 See MDCARL Register CARL MDCLSYNC MDCLPOL 1111 32.1 DSM Operation The DSM module can be enabled by setting the EN bit in the MDCON0 register. Clearing the EN bit, disables the output of the module but retain the carrier and source signal selections. The module will resume operation when the EN bit is set again. The output of the DSM module can be rerouted to several pins using the RxyPPS register. When the EN bit is cleared the output pin is held low. 32.2 Modulator Signal Sources The modulator signal can be supplied from the following sources selected with the SRCS bits: © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 476 PIC16(L)F18455/56 (DSM) Data Signal Modulator Module Table 32-1. MDSRC Selection MUX Connections 32.3 SRCS Connection 11111-10100 Reserved 10011 EUSART2 TX (TX/CK output) 10010 CCP5 OUT 10001 MSSP2 - SDO 10000 MSSP1 - SDO 01111 EUSART1 TX (TX/CK output) 01110 CLC4 OUT 01101 CLC3 OUT 01100 CLC2 OUT 01011 CLC1 OUT 01010 C2 OUT 01001 C1 OUT 01000 NCO1 OUT 00111 PWM7 OUT 00110 PWM6 OUT 00101 CCP4 OUT 00100 CCP3 OUT 00011 CCP2 OUT 00010 CCP1 OUT 00001 MDBIT 00000 Pin selected by MDSRCPPS Carrier Signal Sources The carrier high signal and carrier low signal can be supplied from the following sources. The carrier high signal is selected by configuring the CHS bits. Table 32-2. MDCARH Source Selections MDCARH CHS Connection 1111 CCP5 OUT 1110 CLC4 OUT 1101 CLC3 OUT © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 477 PIC16(L)F18455/56 (DSM) Data Signal Modulator Module MDCARH CHS Connection 1100 CLC2 OUT 1011 CLC1 OUT 1010 NCO1 OUT 1001 PWM7 OUT 1000 PWM6 OUT 0111 CCP4 OUT 0110 CCP3 OUT 0101 CCP2 OUT 0100 CCP1 OUT 0011 CLKREF output 0010 HFINTOSC 0001 FOSC (system clock) 0000 Pin selected by MDCARHPPS The carrier low signal is selected by configuring the CLS bits. Table 32-3. MDCARL Source Selections MDCARL CLS Connection 1111 CCP5 OUT 1110 CLC4 OUT 1101 CLC3 OUT 1100 CLC2 OUT 1011 CLC1 OUT 1010 NCO1 OUT 1001 PWM7 OUT 1000 PWM6 OUT 0111 CCP4 OUT 0110 CCP3 OUT 0101 CCP2 OUT 0100 CCP1 OUT 0011 CLKREF output © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 478 PIC16(L)F18455/56 (DSM) Data Signal Modulator Module MDCARL 32.4 CLS Connection 0010 HFINTOSC 0001 FOSC (system clock) 0000 Pin selected by MDCARLPPS Carrier Synchronization During the time when the DSM switches between carrier high and carrier low signal sources, the carrier data in the modulated output signal can become truncated. To prevent this, the carrier signal can be synchronized to the modulator signal. When synchronization is enabled, the carrier pulse that is being mixed at the time of the transition is allowed to transition low before the DSM switches over to the next carrier source. Synchronization is enabled separately for the carrier high and carrier low signal sources. Synchronization for the carrier high signal is enabled by setting the CHSYNC bit. Synchronization for the carrier low signal is enabled by setting the CLSYNC bit. The figures below show the timing diagrams of using various synchronization methods. Figure 32-2. On Off Keying (OOK) Synchronization Rev. 30-000144A 5/26/2017 carrier_low carrier_high modulator MDCHSYNC = 1 MDCLSYNC = 0 MDCHSYNC = 1 MDCLSYNC = 1 MDCHSYNC = 0 MDCLSYNC = 0 MDCHSYNC = 0 MDCLSYNC = 1 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 479 PIC16(L)F18455/56 (DSM) Data Signal Modulator Module Figure 32-3. No Synchronization (MDCHSYNC = 0, MDCLSYNC = 0) Rev. 30-000145A 5/26/2017 carrier_high carrier_low modulator MDCHSYNC = 0 MDCLSYNC = 0 Active Carrier State carrier_high carrier_low carrier_high carrier_low Figure 32-4. Carrier High Synchronization (MDCHSYNC = 1, MDCLSYNC = 0) Rev. 30-000146A 5/26/2017 carrier_high carrier_low modulator MDCHSYNC = 1 MDCLSYNC = 0 Active Carrier State carrier_high both carrier_low carrier_high both carrier_low Figure 32-5. Carrier Low Synchronization (MDCHSYNC = 0, MDCLSYNC = 1) Rev. 30-000147A 5/26/2017 carrier_high carrier_low modulator MDCHSYNC = 0 MDCLSYNC = 1 Active Carrier State carrier_high © 2018 Microchip Technology Inc. carrier_low carrier_high Datasheet Preliminary carrier_low DS40002038B-page 480 PIC16(L)F18455/56 (DSM) Data Signal Modulator Module Figure 32-6. Full Synchronization (MDCHSYNC = 1, MDCLSYNC = 1) Rev. 30-000148A 5/26/2017 carrier_high carrier_low modulator Falling edges used to sync MDCHSYNC = 1 MDCLSYNC = 1 Active Carrier State 32.5 carrier_high carrier_low carrier_high CL Carrier Source Polarity Select The signal provided from any selected input source for the carrier high and carrier low signals can be inverted. Inverting the signal for the carrier high and low source is enabled by setting the CHPOL bit and the CLPOL bit, respectively. 32.6 Programmable Modulator Data The BIT bit can be selected as the modulation source. This gives the user the ability to provide software driven modulation. 32.7 Modulated Output Polarity The modulated output signal provided on the DSM pin can also be inverted. Inverting the modulated output signal is enabled by setting the OPOL bit. 32.8 Operation in Sleep Mode The DSM can still operate during Sleep, if the Carrier and Modulator input sources are also still operable during Sleep. Refer to “Power-Saving Operation Modes” for more details. 32.9 Effects of a Reset Upon any device Reset, the DSM module is disabled. The user’s firmware is responsible for initializing the module before enabling the output. All the registers are reset to their default values. 32.10 Peripheral Module Disable The DSM module can be completely disabled using the PMD module to achieve maximum power saving. When the DSMMD bit of PMDx register is set, the DSM module is completely disabled. This puts the module in its lowest power consumption state. When enabled again all the registers of the DSM module default to POR status. Related Links 16.5 Register Definitions: Peripheral Module Disable © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 481 PIC16(L)F18455/56 (DSM) Data Signal Modulator Module 32.11 Register Summary - DSM Address Name Bit Pos. 0x0897 MD1CON0 7:0 0x0898 MD1CON1 7:0 0x0899 MD1SRC 7:0 0x089A MD1CARL 7:0 CLS[3:0] 0x089B MD1CARH 7:0 CHS[3:0] 32.12 EN OUT OPOL CHPOL CHSYNC BIT CLPOL CLSYNC SRCS[4:0] Register Definitions: Modulation Control Long bit name prefixes for the Modulation Control peripherals are shown in the table below. Refer to the "Long Bit Names Section" for more information. Table 32-4. Modulation Control Long Bit Name Prefixes Peripheral Bit Name Prefix MD MD Related Links 1.4.2.2 Long Bit Names © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 482 PIC16(L)F18455/56 (DSM) Data Signal Modulator Module 32.12.1 MDxCON0 Name:  MDxCON0 Address:  0x0897 Modulation Control Register 0 Bit Access Reset 5 4 EN 7 6 OUT OPOL 3 2 1 BIT 0 R/W R/W R/W R/W 0 0 0 0 Bit 7 – EN Modulator Module Enable bit Value 1 0 Description Modulator module is enabled and mixing input signals Modulator module is disabled and has no output Bit 5 – OUT Modulator Output bit Displays the current output value of the modulator module. Bit 4 – OPOL Modulator Output Polarity Select bit Value 1 0 Description Modulator output signal is inverted; idle high output Modulator output signal is not inverted; idle low output Bit 0 – BIT Modulation Source Select Input bit Allows software to manually set modulation source input to module Note:  1. The modulated output frequency can be greater and asynchronous from the clock that updates this register bit, the bit value may not be valid for higher speed modulator or carrier signals. 2. MDBIT must be selected as the modulation source in the MDxSRC register for this operation. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 483 PIC16(L)F18455/56 (DSM) Data Signal Modulator Module 32.12.2 MDxCON1 Name:  MDxCON1 Address:  0x0898 Modulation Control Register 1 Bit 7 6 Access Reset 5 4 1 0 CHPOL CHSYNC 3 2 CLPOL CLSYNC R/W R/W R/W R/W 0 0 0 0 Bit 5 – CHPOL Modulator High Carrier Polarity Select bit Value 1 0 Description Selected high carrier signal is inverted Selected high carrier signal is not inverted Bit 4 – CHSYNC Modulator High Carrier Synchronization Enable bit Value 1 0 Description Modulator waits for a falling edge on the high time carrier signal before allowing a switch to the low time carrier Modulator output is not synchronized to the high time carrier signal Bit 1 – CLPOL Modulator Low Carrier Polarity Select bit Value 1 0 Description Selected low carrier signal is inverted Selected low carrier signal is not inverted Bit 0 – CLSYNC Modulator Low Carrier Synchronization Enable bit Value 1 0 Description Modulator waits for a falling edge on the low time carrier signal before allowing a switch to the high time carrier Modulator output is not synchronized to the low time carrier signal Note:  1. Narrowed carrier pulse widths or spurs may occur in the signal stream if the carrier is not synchronized. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 484 PIC16(L)F18455/56 (DSM) Data Signal Modulator Module 32.12.3 MDxCARH Name:  MDxCARH Address:  0x089B Modulation High Carrier Control Register Bit 7 6 5 4 3 2 1 0 CHS[3:0] Access R/W R/W R/W R/W 0 0 0 0 Reset Bits 3:0 – CHS[3:0] Modulator Carrier High Selection bits Table 32-5. MDCARH Source Selections MDCARH CHS Connection 1111 CCP5 OUT 1110 CLC4 OUT 1101 CLC3 OUT 1100 CLC2 OUT 1011 CLC1 OUT 1010 NCO1 OUT 1001 PWM7 OUT 1000 PWM6 OUT 0111 CCP4 OUT 0110 CCP3 OUT 0101 CCP2 OUT 0100 CCP1 OUT 0011 CLKREF output 0010 HFINTOSC 0001 FOSC (system clock) 0000 Pin selected by MDCARHPPS © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 485 PIC16(L)F18455/56 (DSM) Data Signal Modulator Module 32.12.4 MDxCARL Name:  MDxCARL Address:  0x089A Modulation Low Carrier Control Register Bit 7 6 5 4 3 2 1 0 CLS[3:0] Access R/W R/W R/W R/W 0 0 0 0 Reset Bits 3:0 – CLS[3:0] Modulator Carrier Low Input Selection bits Table 32-6. MDCARL Source Selections MDCARL CLS Connection 1111 CCP5 OUT 1110 CLC4 OUT 1101 CLC3 OUT 1100 CLC2 OUT 1011 CLC1 OUT 1010 NCO1 OUT 1001 PWM7 OUT 1000 PWM6 OUT 0111 CCP4 OUT 0110 CCP3 OUT 0101 CCP2 OUT 0100 CCP1 OUT 0011 CLKREF output 0010 HFINTOSC 0001 FOSC (system clock) 0000 Pin selected by MDCARLPPS © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 486 PIC16(L)F18455/56 (DSM) Data Signal Modulator Module 32.12.5 MDxSRC Name:  MDxSRC Address:  0x0899 Modulation Source Control Register Bit 7 6 5 4 3 2 1 0 SRCS[4:0] Access Reset R/W R/W R/W R/W R/W 0 0 0 0 0 Bits 4:0 – SRCS[4:0] Modulator Source Selection bits Table 32-7. MDSRC Selection MUX Connections SRCS Connection 11111-10100 Reserved 10011 EUSART2 TX (TX/CK output) 10010 CCP5 OUT 10001 MSSP2 - SDO 10000 MSSP1 - SDO 01111 EUSART1 TX (TX/CK output) 01110 CLC4 OUT 01101 CLC3 OUT 01100 CLC2 OUT 01011 CLC1 OUT 01010 C2 OUT 01001 C1 OUT 01000 NCO1 OUT 00111 PWM7 OUT 00110 PWM6 OUT 00101 CCP4 OUT 00100 CCP3 OUT 00011 CCP2 OUT 00010 CCP1 OUT 00001 MDBIT 00000 Pin selected by MDSRCPPS © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 487 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33. (CLC) Configurable Logic Cell The Configurable Logic Cell (CLCx) module provides programmable logic that operates outside the speed limitations of software execution. The logic cell takes up to 64 input signals and, through the use of configurable gates, reduces the 64 inputs to four logic lines that drive one of eight selectable singleoutput logic functions. Input sources are a combination of the following: • I/O pins • Internal clocks • Peripherals • Register bits The output can be directed internally to peripherals and to an output pin. Important:  There are several CLC instances on this device. Throughout this section, the lower case ‘x’ in register names is a generic reference to the CLC instance number. For example, the first instance of the control register is CLC1CON and is generically described in this chapter as CLCxCON. The following figure is a simplified diagram showing signal flow through the CLC. Possible configurations include: • Combinatorial Logic – AND – NAND – AND-OR – AND-OR-INVERT – OR-XOR – OR-XNOR • Latches – S-R – Clocked D with Set and Reset – Transparent D with Set and Reset © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 488 PIC16(L)F18455/56 (CLC) Configurable Logic Cell Figure 33-1. CLC Simplified Block Diagram Rev. 10-000025H 11/9/2016 D Q OUT CLCxOUT Q1 . . . LCx_in[n-2] LCx_in[n-1] LCx_in[n] CLCx_out Input Data Selection Gates(1) LCx_in[0] LCx_in[1] LCx_in[2] EN lcxg1 lcxg2 lcxg3 to Peripherals CLCxPPS Logic lcxq Function PPS (2) CLCx lcxg4 POL MODE TRIS Interrupt det INTP INTN set bit CLCxIF Interrupt det Note:  1. See Figure 33-2 for input data selection and gating. 2. See Figure 33-3 for programmable logic functions. 33.1 CLC Setup Programming the CLC module is performed by configuring the four stages in the logic signal flow. The four stages are: • Data selection • Data gating • Logic function selection • Output polarity Each stage is setup at run time by writing to the corresponding CLC Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution. 33.1.1 Data Selection There are 64 signals available as inputs to the configurable logic. Four 64-input multiplexers are used to select the inputs to pass on to the next stage. Data selection is through four multiplexers as indicated on the left side of the following diagram. Data inputs in the figure are identified by a generic numbered input name. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 489 PIC16(L)F18455/56 (CLC) Configurable Logic Cell Figure 33-2. Input Data Selection and Gating Rev. 30-000149A 6/12/2017 LCx_in[0] Data Selection 000000 Data GATE 1 LCx_in[n] d1T G 1 D1 T d1N G 1 D1 N G 1 D2 T 111111 D1S G 1 D2 N LCx_in[0] lcxg1 000000 d2T G 1 D3 T G 1 D3 N G 1 D4 T G 1 D4 N G1POL d2N LCx_in[n] 111111 D2S LCx_in[0] 000000 Data GATE 2 lcxg2 d3T (Same as Data GATE 1) d3N LCx_in[n] Data GATE 3 111111 lcxg3 D3S LCx_in[0] (Same as Data GATE 1) Data GATE 4 000000 lcxg4 (Same as Data GATE 1) d4T d4N LCx_in[n] 111111 D4S Note: All controls are undefined at power-up. The following table correlates the generic input name to the actual signal for each CLC module. The column labeled ‘DyS Value’ indicates the MUX selection code for the selected data input. DyS is an abbreviation for the MUX select input codes: D1S through D4S where 'y' is the gate number. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 490 PIC16(L)F18455/56 (CLC) Configurable Logic Cell CLC Data Input Sources DyS Value CLC Input Source DyS Value CLC Input Source 111111 [63] Reserved 011111 [31] DSM1_out 111110 [62] Reserved 011110 [30] IOC_flag 111101 [61] Reserved 011101 [29] ZCD_out 111100 [60] Reserved 011100 [28] C2_out 111011 [59] Reserved 011011 [27] C1_out 111010 58] Reserved 011010 [26] NCO1_out 111001 [57] Reserved 011001 [25] PWM7_out 111000 [56] Reserved 011000 [24] PWM6 _out 110111 [55] Reserved 010111 [23] CCP4_out 110110 [54] Reserved 010110 [22] CCP3_out 110101 [53] Reserved 010101 [21] CCP2_out 110100 [52] Reserved 010100 [20] CCP1_out 110011 [51] EUSART2_CK_out 010011 [19] SMT1_overflow 110010 [50] EUSART2_DT_out 010010 [18] TMR6 _out 110001 [49] CCP5_out 010001 [17] TMR5 _overflow 110000 [48] SMT2_overflow 010000 [16] TMR4_out 101111 [47] CWG3B_out 001111 [15] TMR3 _overflow 101110 [46] CWG3A_out 001110 [14] TMR2_out 101101 [45] CWG2B_out 001101 [13] TMR1_overflow 101100 [44] CWG2A_out 001100 [12] TMR0_overflow 101011 [43] CWG1B_out 001011 [11] CLKR_out 101010 [42] CWG1A_out 001010 [10] FRC 101001 [41] MSSP2_clk_out 001001 [9] SOSC 101000 [40] MSSP2_data_out 001000 [8] MFINTOSC (32 kHz) 100111 [39] MSSP1_clk_out 000111 [7] MFINTOSC (500 kHz) 100110 [38] MSSP1_data_out 000110 [6] LFINTOSC 100101 [37] EUSART1_CK_out 000101 [5] HFINTOSC (32 MHz) 100100 [36] EUSART1_DT_out 000100 [4] FOSC 100011 [35] CLC4_out 000011 [3] CLCIN3PPS 100010 [34] CLC3_out 000010 [2] CLCIN2PPS © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 491 PIC16(L)F18455/56 (CLC) Configurable Logic Cell DyS Value CLC Input Source DyS Value CLC Input Source 100001 [33] CLC2_out 000001 [1] CLCIN1PPS 100000 [32] CLC1_out 000000 [0] CLCIN0PPS Data inputs are selected with CLCxSEL0 through CLCxSEL3 registers. Important:  Data selections are undefined at power-up. 33.1.2 Data Gating Outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. Each data gate can direct any combination of the four selected inputs. The gate stage is more than just signal direction. The gate can be configured to direct each input signal as inverted or non-inverted data. Directed signals are ANDed together in each gate. The output of each gate can be inverted before going on to the logic function stage. The gating is in essence a 1-to-4 input AND/NAND/OR/NOR gate. When every input is inverted and the output is inverted, the gate is an AND of all enabled data inputs. When the inputs and output are not inverted, the gate is an OR or all enabled inputs. The following table summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. The table shows the logic of four input variables, but each gate can be configured to use less than four. If no inputs are selected, the output will be zero or one, depending on the gate output polarity bit. Table 33-1. Data Gating Logic CLCxGLSy GyPOL Gate Logic 0x55 1 AND 0x55 0 NAND 0xAA 1 NOR 0xAA 0 OR 0x00 0 Logic 0 0x00 1 Logic 1 It is possible (but not recommended) to select both the true and negated values of an input. When this is done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transientinduced pulses). If the output of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the gate polarity bit to set the desired level. Data gating is configured with the logic gate select registers as follows: • Gate 1: CLCxSEL0 • Gate 2: CLCxSEL1 • Gate 3: CLCxSEL2 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 492 PIC16(L)F18455/56 (CLC) Configurable Logic Cell • Gate 4: CLCxSEL3 Register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register. Data gating is indicated in the right side of Figure 33-2. Only one gate is shown in detail. The remaining three gates are configured identically with the exception that the data enables correspond to the enables for that gate. 33.1.3 Logic Function There are eight available logic functions including: • • • • • • • • AND-OR OR-XOR AND S-R Latch D Flip-Flop with Set and Reset D Flip-Flop with Reset J-K Flip-Flop with Reset Transparent Latch with Set and Reset Logic functions are shown in the following diagram. Each logic function has four inputs and one output. The four inputs are the four data gate outputs of the previous stage. The output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the CLC itself. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 493 PIC16(L)F18455/56 (CLC) Configurable Logic Cell Figure 33-3. Programmable Logic Functions Rev. 10-000122B 9/13/2016 AND-OR OR-XOR lcxg1 lcxg1 lcxg2 lcxg2 lcxq lcxq lcxg3 lcxg3 lcxg4 lcxg4 MODE = 000 MODE = 001 4-input AND S-R Latch lcxg1 lcxg1 S lcxg2 lcxg2 Q lcxq Q lcxq lcxq lcxg3 lcxg3 lcxg4 R lcxg4 MODE = 010 MODE = 011 1-Input D Flip-Flop with S and R 2-Input D Flip-Flop with R lcxg4 lcxg2 D lcxg1 S Q lcxq lcxg4 D lcxg2 lcxg1 R lcxg3 R lcxg3 MODE = 100 MODE = 101 J-K Flip-Flop with R 1-Input Transparent Latch with S and R lcxg2 J Q lcxq lcxg4 lcxg2 D lcxg3 LE S Q lcxq lcxg1 lcxg4 K R lcxg3 R lcxg1 MODE = 110 MODE = 111 33.1.4 Output Polarity The last stage in the Configurable Logic Cell is the output polarity. Setting the POL bit inverts the output signal from the logic stage. Changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. 33.2 CLC Interrupts An interrupt will be generated upon a change in the output value of the CLCx when the appropriate interrupt enables are set. A rising edge detector and a falling edge detector are present in each CLC for this purpose. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 494 PIC16(L)F18455/56 (CLC) Configurable Logic Cell The CLCxIF bit of the associated PIR register will be set when either edge detector is triggered and its associated enable bit is set. The INTP enables rising edge interrupts and the INTN bit enables falling edge interrupts. To fully enable the interrupt, set the following bits: • CLCxIE bit of the respective PIE register • INTP bit (for a rising edge detection) • INTN bit (for a falling edge detection) • If priority interrupts are not used – Clear the IPEN bit of the INTCON register – Set the GIE bit of the INTCON register – Set the PEIE bit of the INTCON register • If the CLC is a high priority interrupt – Set the IPEN bit of the INTCON register – Set the CLCxIP bit of the respective IPR register – Set the GIEH bit of the INTCON register • If the CLC is a low priority interrupt – Set the IPEN bit of the INTCON register – Clear the CLCxIP bit of the respective IPR register – Set the GIEL bit of the INTCON register The CLCxIF bit of the respective PIR register, must be cleared in software as part of the interrupt service. If another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. Related Links 7.8.10 INTCON 10.7.7 PIE5 10.7.16 PIR5 33.3 Output Mirror Copies Mirror copies of all CLCxOUT bits are contained in the 33.8.11 CLCDATA register. Reading this register reads the outputs of all CLCs simultaneously. This prevents any reading skew introduced by testing or reading the OUT bits in the individual CLCxCON registers. 33.4 Effects of a Reset The CLCxCON register is cleared to zero as the result of a Reset. All other selection and gating values remain unchanged. 33.5 Operation During Sleep The CLC module operates independently from the system clock and will continue to run during Sleep, provided that the input sources selected remain active. The HFINTOSC remains active during Sleep when the CLC module is enabled and the HFINTOSC is selected as an input source, regardless of the system clock source selected. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 495 PIC16(L)F18455/56 (CLC) Configurable Logic Cell In other words, if the HFINTOSC is simultaneously selected as the system clock and as a CLC input source, when the CLC is enabled, the CPU will go idle during Sleep, but the CLC will continue to operate and the HFINTOSC will remain active. This will have a direct effect on the Sleep mode current. 33.6 CLC Setup Steps The following steps should be followed when setting up the CLC: • • • • • • • • • • • Disable CLC by clearing the EN bit. Select desired inputs using the CLCxSEL0 through CLCxSEL3 registers (See CLC Data Input Table). Clear any associated ANSEL bits. Set all TRIS bits associated with inputs. Enable the chosen inputs through the four gates using the CLCxGLS0 through CLCxGLS3 registers. Select the gate output polarities with the GyPOL bits Select the desired logic function with the MODE bits Select the desired polarity of the logic output with the POL bit. (This step may be combined with the previous gate output polarity step). If driving a device pin, set the desired pin PPS control register and also clear the TRIS bit corresponding to that output. Configure the interrupts (optional). See 33.2 CLC Interrupts Enable the CLC by setting the EN bit. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 496 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.7 Register Summary - CLC Control Address Name Bit Pos. 0x1E0F CLCDATA 7:0 0x1E10 CLC1CON 7:0 EN 0x1E11 CLC1POL 7:0 POL MLC4OUT OUT INTP MLC3OUT INTN MLC2OUT MLC1OUT MODE[2:0] G4POL G3POL G2POL G1POL 0x1E12 CLC1SEL0 7:0 D1S[5:0] 0x1E13 CLC1SEL1 7:0 D2S[5:0] 0x1E14 CLC1SEL2 7:0 D3S[5:0] 0x1E15 CLC1SEL3 7:0 0x1E16 CLC1GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x1E17 CLC1GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x1E18 CLC1GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x1E19 CLC1GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 0x1E1A CLC2CON 7:0 EN OUT INTP 0x1E1B CLC2POL 7:0 POL 0x1E1C CLC2SEL0 7:0 D1S[5:0] 0x1E1D CLC2SEL1 7:0 D2S[5:0] 0x1E1E CLC2SEL2 7:0 D3S[5:0] 0x1E1F CLC2SEL3 7:0 D4S[5:0] D4S[5:0] INTN MODE[2:0] G4POL G3POL G2POL G1POL 0x1E20 CLC2GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x1E21 CLC2GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x1E22 CLC2GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x1E23 CLC2GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 0x1E24 CLC3CON 7:0 EN OUT INTP INTN 0x1E25 CLC3POL 7:0 POL 0x1E26 CLC3SEL0 7:0 D1S[5:0] 0x1E27 CLC3SEL1 7:0 D2S[5:0] 0x1E28 CLC3SEL2 7:0 D3S[5:0] 0x1E29 CLC3SEL3 7:0 D4S[5:0] MODE[2:0] G4POL G3POL G2POL G1POL 0x1E2A CLC3GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x1E2B CLC3GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x1E2C CLC3GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x1E2D CLC3GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 0x1E2E CLC4CON 7:0 EN OUT INTP INTN 0x1E2F CLC4POL 7:0 POL MODE[2:0] G4POL G3POL G2POL G1POL 0x1E30 CLC4SEL0 7:0 D1S[5:0] 0x1E31 CLC4SEL1 7:0 D2S[5:0] 0x1E32 CLC4SEL2 7:0 D3S[5:0] 0x1E33 CLC4SEL3 7:0 0x1E34 CLC4GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x1E35 CLC4GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x1E36 CLC4GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x1E37 CLC4GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N D4S[5:0] © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 497 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.8 Register Definitions: Configurable Logic Cell Long bit name prefixes for the CLC peripherals are shown in the table below. Refer to the "Long Bit Names Section" for more information. Table 33-2. CLC Bit Name Prefixes Peripheral Bit Name Prefix CLC1 LC1 CLC2 LC2 CLC3 LC3 CLC4 LC4 Related Links 1.4.2.2 Long Bit Names © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 498 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.8.1 CLCxCON Name:  CLCxCON Address:  0x1E10,0x1E1A,0x1E24,0x1E2E Configurable Logic Cell Control Register Bit Access Reset 5 4 3 EN 7 6 OUT INTP INTN 2 1 0 R/W RO R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 MODE[2:0] Bit 7 – EN CLC Enable bit Value 1 0 Description Configurable logic cell is enabled and mixing signals Configurable logic cell is disabled and has logic zero output Bit 5 – OUT Logic cell output data, after LCPOL. Sampled from CLCxOUT Bit 4 – INTP Configurable Logic Cell Positive Edge Going Interrupt Enable bit Value 1 0 Description CLCxIF will be set when a rising edge occurs on CLCxOUT Rising edges on CLCxOUT have no effect on CLCxIF Bit 3 – INTN Configurable Logic Cell Negative Edge Going Interrupt Enable bit Value 1 0 Description CLCxIF will be set when a falling edge occurs on CLCxOUT Falling edges on CLCxOUT have no effect on CLCxIF Bits 2:0 – MODE[2:0] Configurable Logic Cell Functional Mode Selection bits Value 111 110 101 100 011 010 001 000 Description Cell is 1-input transparent latch with Set and Reset Cell is J-K flip-flop with Reset Cell is 2-input D flip-flop with Reset Cell is 1-input D flip-flop with Set and Reset Cell is S-R latch Cell is 4-input AND Cell is OR-XOR Cell is AND-OR © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 499 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.8.2 CLCxPOL Name:  CLCxPOL Address:  0x1E11,0x1E1B,0x1E25,0x1E2F Signal Polarity Control Register Bit Access Reset 3 2 1 0 POL 7 6 5 4 G4POL G3POL G2POL G1POL R/W R/W R/W R/W R/W 0 x x x x Bit 7 – POL CLCxOUT Output Polarity Control bit Value 1 0 Description The output of the logic cell is inverted The output of the logic cell is not inverted Bits 0, 1, 2, 3 – GyPOL Gate Output Polarity Control bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value 1 0 Description The gate output is inverted when applied to the logic cell The output of the gate is not inverted © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 500 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.8.3 CLCxSEL0 Name:  CLCxSEL0 Address:  0x1E12,0x1E1C,0x1E26,0x1E30 Generic CLCx Data 1 Select Register Bit 7 6 5 4 3 2 1 0 D1S[5:0] Access Reset R/W R/W R/W R/W R/W R/W x x x x x x Bits 5:0 – D1S[5:0] CLCx Data1 Input Selection bits Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value n Description Refer to CLC Input Sources for input selections © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 501 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.8.4 CLCxSEL1 Name:  CLCxSEL1 Address:  0x1E13,0x1E1D,0x1E27,0x1E31 Generic CLCx Data 1 Select Register Bit 7 6 5 4 3 2 1 0 D2S[5:0] Access Reset R/W R/W R/W R/W R/W R/W x x x x x x Bits 5:0 – D2S[5:0] CLCx Data2 Input Selection bits Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value n Description Refer to CLC Input Sources for input selections © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 502 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.8.5 CLCxSEL2 Name:  CLCxSEL2 Address:  0x1E14,0x1E1E,0x1E28,0x1E32 Generic CLCx Data 1 Select Register Bit 7 6 5 4 3 2 1 0 D3S[5:0] Access Reset R/W R/W R/W R/W R/W R/W x x x x x x Bits 5:0 – D3S[5:0] CLCx Data3 Input Selection bits Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value n Description Refer to CLC Input Sources for input selections © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 503 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.8.6 CLCxSEL3 Name:  CLCxSEL3 Address:  0x1E15,0x1E1F,0x1E29,0x1E33 Generic CLCx Data 4 Select Register Bit 7 6 5 4 3 2 1 0 D4S[5:0] Access Reset R/W R/W R/W R/W R/W R/W x x x x x x Bits 5:0 – D4S[5:0] CLCx Data4 Input Selection bits Reset States: POR/BOR = xxxxxx All Other Resets = uuuuuu Value n Description Refer to CLC Input Sources for input selections © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 504 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.8.7 CLCxGLS0 Name:  CLCxGLS0 Address:  0x1E16,0x1E20,0x1E2A,0x1E34 CLCx Gate1 Logic Select Register Bit Access Reset 7 6 5 4 3 2 1 0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 1, 3, 5, 7 – G1DyT dyT: Gate1 Data 'y' True (non-inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value 1 0 Description dyT is gated into g1 dyT is not gated into g1 Bits 0, 2, 4, 6 – G1DyN dyN: Gate1 Data 'y' Negated (inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value 1 0 Description dyN is gated into g1 dyN is not gated into g1 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 505 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.8.8 CLCxGLS1 Name:  CLCxGLS1 Address:  0x1E17,0x1E21,0x1E2B,0x1E35 CLCx Gate2 Logic Select Register Bit Access Reset 7 6 5 4 3 2 1 0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 1, 3, 5, 7 – G2DyT dyT: Gate2 Data 'y' True (non-inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value 1 0 Description dyT is gated into g2 dyT is not gated into g2 Bits 0, 2, 4, 6 – G2DyN dyN: Gate2 Data 'y' Negated (inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value 1 0 Description dyN is gated into g2 dyN is not gated into g2 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 506 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.8.9 CLCxGLS2 Name:  CLCxGLS2 Address:  0x1E18,0x1E22,0x1E2C,0x1E36 CLCx Gate3 Logic Select Register Bit Access Reset 7 6 5 4 3 2 1 0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 1, 3, 5, 7 – G3DyT dyT: Gate3 Data 'y' True (non-inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value 1 0 Description dyT is gated into g3 dyT is not gated into g3 Bits 0, 2, 4, 6 – G3DyN dyN: Gate3 Data 'y' Negated (inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value 1 0 Description dyN is gated into g3 dyN is not gated into g3 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 507 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.8.10 CLCxGLS3 Name:  CLCxGLS3 Address:  0x1E19,0x1E23,0x1E2D,0x1E37 CLCx Gate4 Logic Select Register Bit Access Reset 7 6 5 4 3 2 1 0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 1, 3, 5, 7 – G4DyT dyT: Gate4 Data 'y' True (non-inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value 1 0 Description dyT is gated into g4 dyT is not gated into g4 Bits 0, 2, 4, 6 – G4DyN dyN: Gate4 Data 'y' Negated (inverted) bit Reset States: Default = xxxx POR/BOR = x All Other Resets = u Value 1 0 Description dyN is gated into g4 dyN is not gated into g4 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 508 PIC16(L)F18455/56 (CLC) Configurable Logic Cell 33.8.11 CLCDATA Name:  CLCDATA Address:  0x1E0F CLC Data Ouput Register Mirror copy of Bit 7 6 Access Reset 5 4 3 2 1 0 MLC4OUT MLC3OUT MLC2OUT MLC1OUT R/W R/W R/W R/W 0 0 0 0 Bits 0, 1, 2, 3 – MLCxOUT Mirror copy of CLCx_out bit Value 1 0 Description CLCx_out is 1 CLCx_out is 0 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 509 PIC16(L)F18455/56 Reference Clock Output Module Reference Clock Output Module The reference clock output module provides the ability to send a clock signal to the clock reference output pin (CLKR). The reference clock output can also be routed internally as a signal for other peripherals, such as the Data Signal Modulator (DSM), Memory Scanner, and Timer module. The reference clock output module has the following features: Filename: 10-000261B.vsd Selectable Clock Source Using theWith CLKRCLK Title:• Clock Reference Block Diagram SelectableRegister Clock Source Last Edit: 5/11/2016 • Programmable Clock Divider First Used: PIC18(L)F2x/4x/6xK40 (MVAF,MVAE,MVAB,MVAC,MVAK) • Selectable Duty Cycle Notes: Figure 34-1. Clock Reference Block Diagram Rev. 10-000261B 5/11/2016 DIV EN See CLKRCLK Register Filename: Title: Last Edit: First Used: Notes: Counter Reset Reference Clock Divider 34. 128 111 64 110 32 101 16 100 8 011 10-000264B.vsd 4 010 Clock Reference Timing 5/25/2016 2 001 PIC18(L)F2x/4x/6xK40 (MVAF,MVAE,MVAB,MVAC,MVAK) CLK RxyPPS DC CLKR Duty Cycle PPS To Peripherals 000 EN Figure 34-2. Clock Reference Timing P1 Rev. 10-000264B 5/25/2016 P2 CLKRCLK CLKREN CLKR Output CLKRDIV = 001 CLKRDC = 10 CLKR Output CLKRDIV = 001 CLKRDC = 01 © 2018 Microchip Technology Inc. Duty Cycle (50%) CLKRCLK/2 Duty Cycle (25%) Datasheet Preliminary DS40002038B-page 510 PIC16(L)F18455/56 Reference Clock Output Module 34.1 Clock Source The clock source of the reference clock peripheral is selected with the CLK bits. The available clock sources are listed in the following table: Table 34-1. CLKR Clock Sources 34.1.1 CLK Clock Source 1111-1011 Reserved 1010 CLC4 OUT 1001 CLC3 OUT 1000 CLC2 OUT 0111 CLC1 OUT 0110 NCO1 OUT 0101 SOSC 0100 MFINTOSC (32 kHz) 0011 MFINTOSC (500 kHz) 0010 LFINTOSC 0001 HFINTOSC (32 MHz) 0000 FOSC Clock Synchronization The CLKR output signal is ensured to be glitch-free when the EN bit is set to start the module and enable the CLKR output. When the reference clock output is disabled, the output signal will be disabled immediately. Clock dividers and clock duty cycles can be changed while the module is enabled but doing so may cause glitches to occur on the output. To avoid possible glitches, clock dividers and clock duty cycles should be changed only when the EN bit is clear. 34.2 Programmable Clock Divider The module takes the clock input and divides it based on the value of the DIV bits. The following configurations are available: • • • • • • • • Base Fosc value FOSC divided by 2 FOSC divided by 4 FOSC divided by 8 FOSC divided by 16 FOSC divided by 32 FOSC divided by 64 FOSC divided by 128 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 511 PIC16(L)F18455/56 Reference Clock Output Module The clock divider values can be changed while the module is enabled. However, in order to prevent glitches on the output, the DIV bits should only be changed when the module is disabled (EN = 0). 34.3 Selectable Duty Cycle The DC bits are used to modify the duty cycle of the output clock. A duty cycle of 0%, 25%, 50%, or 75% can be selected for all clock rates when the DIV value is not 0b000. When DIV=0b000 then the duty cycle defaults to 50% for all values of DC except 0b00 in which case the duty cycle is 0% (constant low output). The duty cycle can be changed while the module is enabled. However, in order to prevent glitches on the output, the DC bits should only be changed when the module is disabled (EN = 0). Important:  The DC value at reset is 10. This makes the default duty cycle 50% and not 0%. 34.4 Operation in Sleep Mode The reference clock module continues to operate and provide a signal output in Sleep for all clock source selections except FOSC (CLK=0). © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 512 PIC16(L)F18455/56 Reference Clock Output Module 34.5 Register Summary: Reference CLK Address Name Bit Pos. 0x0895 CLKRCON 7:0 0x0896 CLKRCLK 7:0 34.6 EN DC[1:0] DIV[2:0] CLK[3:0] Register Definitions: Reference Clock Long bit name prefixes for the Reference Clock peripherals are shown in the following table. Refer to the "Long Bit Names" section for more information. Table 34-2. TABLE 5-1: Peripheral Bit Name Prefix CLKR CLKR Related Links 1.4.2.2 Long Bit Names © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 513 PIC16(L)F18455/56 Reference Clock Output Module 34.6.1 CLKRCON Name:  CLKRCON Address:  0x895 Reference Clock Control Register Bit 7 6 5 4 EN Access Reset 3 2 DC[1:0] 1 0 DIV[2:0] R/W R/W R/W R/W R/W R/W 0 1 0 0 0 0 Bit 7 – EN Reference Clock Module Enable bit Value 1 0 Description Reference clock module enabled Reference clock module is disabled Bits 4:3 – DC[1:0] Reference Clock Duty Cycle bits(1) Value 11 10 01 00 Description Clock outputs duty cycle of 75% Clock outputs duty cycle of 50% Clock outputs duty cycle of 25% Clock outputs duty cycle of 0% Bits 2:0 – DIV[2:0] Reference Clock Divider bits Value 111 110 101 100 011 010 001 000 Description Base clock value divided by 128 Base clock value divided by 64 Base clock value divided by 32 Base clock value divided by 16 Base clock value divided by 8 Base clock value divided by 4 Base clock value divided by 2 Base clock value Note:  1. Bits are valid for reference clock divider values of two or larger, the base clock cannot be further divided. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 514 PIC16(L)F18455/56 Reference Clock Output Module 34.6.2 CLKRCLK Name:  CLKRCLK Address:  0x896 Clock Reference Clock Selection MUX Bit 7 6 5 4 3 2 1 0 CLK[3:0] Access Reset R/W R/W R/W R/W 0 0 0 0 Bits 3:0 – CLK[3:0] CLKR Clock Selection bits See the Clock Sources table. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 515 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35. (MSSP) Master Synchronous Serial Port Module The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: • • Serial Peripheral Interface (SPI) Inter-Integrated Circuit (I2C) The SPI interface supports the following modes and features: • • • • • Master mode Slave mode Clock Parity Slave Select Synchronization (Slave mode only) Daisy-chain connection of slave devices The I2C interface supports the following modes and features: • • • • • • • • • • • • • 35.1 Master mode Slave mode Byte NACKing (Slave mode) Limited multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDA hold times SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a Chip Select known as Slave Select. The SPI bus specifies four signal connections: • • • • Serial Clock (SCK) Serial Data Out (SDO) Serial Data In (SDI) Slave Select (SS) The following figure shows the block diagram of the MSSP module when operating in SPI mode. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 516 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Figure 35-1. MSSP Block Diagram (SPI mode) Rev. 30-000011A 3/31/2017 Data Bus Write Read SSPxBUF Reg SSPxDATPPS SDI PPS SSPSR Reg Shift Clock bit 0 SDO PPS RxyPPS SS SS Control Enable PPS SSPxSSPPS Edge Select SSPxCLKPPS(2) SCK SSPM 4 PPS PPS TRIS bit 2 (CKP, CKE) Clock Select Edge Select RxyPPS(1) ( T2_match 2 ) Prescaler TOSC 4, 16, 64 Baud Rate Generator (SSPxADD) Note 1: Output selection for master mode 2: Input selection for slave and master mode The SPI bus operates with a single master device and one or more slave devices. When multiple slave devices are used, an independent Slave Select connection is required from the master device to each slave device. The figure below shows a typical connection between a master device and multiple slave devices. The master selects only one slave at a time. Most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. ©2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 517 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Figure 35-2. SPI Master and Multiple Slave Connection Rev. 30-000012A 3/31/2017 SPI Master SCK SCK SDO SDI SDI SDO General I/O General I/O SS General I/O SCK SDI SDO SPI Slave #1 SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS 35.1.1 SPI Mode Registers The MSSP module has five registers for SPI mode operation. These are: • • • • • • MSSP STATUS register (SSPxSTAT) MSSP Control register 1 (SSPxCON1) MSSP Control register 3 (SSPxCON3) MSSP Data Buffer register (SSPxBUF) MSSP Address register (SSPxADD) MSSP Shift register (SSPSR) (Not directly accessible) SSPxCON1 and SSPxSTAT are the control and STATUS registers for SPI mode operation. The SSPxCON1 register is readable and writable. The lower six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. One of the five SPI master modes uses the SSPxADD value to determine the Baud Rate Generator clock frequency. More information on the Baud Rate Generator is available in 35.7 Baud Rate Generator. SSPSR is the shift register used for shifting data in and out. SSPxBUF provides indirect access to the SSPSR register. SSPxBUF is the buffer register to which data bytes are written, and from which data bytes are read. In receive operations, SSPSR and SSPxBUF together create a buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR. 35.2 SPI Mode Operation Transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. With either the master or the slave device, data is always shifted out one bit at a time, with the Most Significant ©2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 518 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module bit (MSb) shifted out first. At the same time, a new Least Significant bit (LSb) is shifted into the same register. The following figure shows a typical connection between two processors configured as master and slave devices. Figure 35-3. SPI Master/Slave Connection Rev/ 30-000013A 3/31/2017 SPI Master SSPM = 00xx = 1010 SPI Slave SSPM = 010x SDO SDI Serial Input Buffer (BUF) LSb SCK General I/O Processor 1 SDO SDI Shift Register (SSPSR) MSb Serial Input Buffer (SSPxBUF) Serial Clock Shift Register (SSPSR) MSb LSb SCK Slave Select (optional) SS Processor 2 Data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. The master device transmits information out on its SDO output pin which is connected to, and received by, the slave’s SDI input pin. The slave device transmits information out on its SDO output pin, which is connected to, and received by, the master’s SDI input pin. To begin communication, the master device first sends out the clock signal. Both the master and the slave devices should be configured for the same clock polarity. The master device starts a transmission by sending out the MSb from its shift register. The slave device reads this bit from that same line and saves it into the LSb position of its shift register. During each SPI clock cycle, a full-duplex data transmission occurs. This means that while the master device is sending out the MSb from its shift register (on its SDO pin) and the slave device is reading this bit and saving it as the LSb of its shift register, that the slave device is also sending out the MSb from its shift register (on its SDO pin) and the master device is reading this bit and saving it as the LSb of its shift register. After eight bits have been shifted out, the master and slave have exchanged register values.  If there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. Whether the data is meaningful or not (dummy data), depends on the application software. This leads to three scenarios for data transmission: • • Master sends useful data and slave sends dummy data. Master sends useful data and slave sends useful data. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 519 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module • Master sends dummy data and slave sends useful data. Transmissions may involve any number of clock cycles. When there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. Every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own. When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1 and SSPxSTAT). These control bits allow the following to be specified: • • • • • • • Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock Polarity (Idle state of SCK) Data Input Sample Phase (middle or end of data output time) Clock Edge (output data on rising/falling edge of SCK) Clock Rate (Master mode only) Slave Select mode (Slave mode only) To enable the serial port, SSP Enable bit, SSPEN, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPxCONx registers and then set the SSPEN bit. The SDI, SDO, SCK and SS serial port pins are selected with the PPS controls. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed as follows: • • • • • • SDI must have corresponding TRIS bit set SDO must have corresponding TRIS bit cleared SCK (Master mode) must have corresponding TRIS bit cleared SCK (Slave mode) must have corresponding TRIS bit set The RxyPPS and SSPxCLKPPS controls must select the same pin SS must have corresponding TRIS bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. The MSSP consists of a transmit/receive shift register (SSPSR) and a buffer register (SSPxBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPSR until the received data is ready. Once the eight bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full Detect bit, BF, and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission/ reception of data will be ignored and the write collision detect bit, WCOL, will be set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of data to transfer is written to the SSPxBUF. The Buffer Full bit, BF, indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 520 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module The SSPSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various Status conditions. 35.2.1 SPI Master Mode The master can initiate the data transfer at any time because it controls the SCK line. The master determines when the slave (Processor 2, Figure 35-3) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if a normal received byte (interrupts and Status bits appropriately set). The clock polarity is selected by appropriately programming the CKP bit and the CKE bit. This then, would give waveforms for SPI communication as shown in Figure 35-4, Figure 35-6, Figure 35-7 and Figure 35-8, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: • • • • • FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 FOSC/(4 * (SSPxADD + 1)) Figure 35-4 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. Important:  In Master mode the clock signal output to the SCK pin is also the clock signal input to the peripheral. The pin selected for output with the RxyPPS register must also be selected as the peripheral input with the SSPxCLKPPS register. The pin that is selected using the SSPxCLKPPS register should also be made a digital I/O. This is done by clearing the corresponding ANSEL bit. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 521 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Figure 35-4. SPI Mode Waveform (Master Mode) Rev. 30-000014A 3/13/2017 Write to SSPxBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) 4 Clock Modes SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDO (CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI (SMP = 0) bit 0 bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 0 bit 7 Input Sample (SMP = 1) SSPxIF SSPSR to SSPxBUF 35.2.2 SPI Slave Mode In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. The shift register is clocked from the SCK pin input and when a byte is received, the device will generate an interrupt. If enabled, the device will wakeup from Sleep. 35.2.3 Daisy-Chain Configuration The SPI bus can sometimes be connected in a daisy-chain configuration. The first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. The final slave output is connected to the master input. Each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. The whole ©2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 522 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module chain acts as one large communication shift register. The daisy-chain feature only requires a single Slave Select line from the master device. The following figure shows the block diagram of a typical daisy-chain connection when operating in SPI mode. Figure 35-5. SPI Daisy-Chain Connection Rev. 30-000015A 3/31/2017 SPI Master SCK SCK SDO SDI SDI General I/O SDO SPI Slave #1 SS SCK SDI SDO SPI Slave #2 SS SCK SDI SDO SPI Slave #3 SS In a daisy-chain configuration, only the most recent byte on the bus is required by the slave. Setting the BOEN bit will enable writes to the SSPxBUF register, even if the previous byte has not been read. This allows the software to ignore data that may not apply to it. 35.2.4 Slave Select Synchronization The Slave Select can also be used to synchronize communication. The Slave Select line is held high until the master device is ready to communicate. When the Slave Select line is pulled low, the slave knows that a new transmission is starting. If the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the Slave Select line returns to a high state. The slave is then ready to receive a new transmission when the Slave Select line is pulled low again. If the Slave Select line is not used, there is a risk that the slave will eventually become out of sync with the master. If the slave misses a bit, it will always be one bit off in future transmissions. Use of the Slave Select line allows the slave and master to align themselves at  the beginning of each transmission. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPM = 0100). When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, the SDO pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note:  1. When the SPI is in Slave mode with SS pin control enabled (SSPM = 0100), the SPI module will reset if the SS pin is set to VDD. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 523 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 2. 3. When the SPI is used in Slave mode with CKE set; the user must enable SS pin control. While operated in SPI Slave mode the SMP bit must remain clear. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. Figure 35-6. Slave Select Synchronous Waveform Rev. 30-000016A 4/10/2017 SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPSR and bit count are reset SSPxBUF to SSPSR SDO bit 7 bit 6 bit 7 SDI bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 524 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Figure 35-7. SPI Mode Waveform (Slave Mode with CKE = 0) Rev. 30-000017A 4/3/2017 SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active ©2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 525 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Figure 35-8. SPI Mode Waveform (Slave Mode with CKE = 1) Rev. 30-000018A 4/1/2017 SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDO bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDI bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPSR to SSPxBUF Write Collision detection active 35.2.5 SPI Operation in Sleep Mode In  SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted. Special care must be taken by the user when the MSSP clock is much faster than the system clock. In Slave mode, when MSSP interrupts are enabled, after the master completes sending data, an MSSP interrupt will wake the controller from Sleep. If an exit from Sleep mode is not desired, MSSP interrupts should be disabled. In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in Sleep mode and data to be shifted into the SPI Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. 35.3 I2C Mode Overview The Inter-Integrated Circuit (I2C) bus is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 526 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module slave device is controlled through addressing. The following two diagrams show block diagrams of the I2C Master and Slave modes, respectively. Figure 35-9. MSSP Block Diagram (I2C Master mode) Rev. 30-000019A 4/3/2017 Internal data bus SSPxDATPPS(1) Read [SSPM] Write SDA SDA in SSPxBUF Baud Rate Generator (SSPxADD) Shift Clock RxyPPS(1) PPS Receive Enable (RCEN) SSPxCLKPPS(2) SCL MSb LSb Start bit, Stop bit, Acknowledge Generate (SSPxCON2) Clock Cntl SSPSR PPS Clock arbitrate/BCOL detect (Hold off clock source) PPS PPS RxyPPS(2) SCL in Bus Collision Start bit detect, Stop bit detect Write collision detect Clock arbitration State counter for end of XMIT/RCV Address Match detect Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV Reset SEN, PEN (SSPxCON2) Set SSP1IF, BCL1IF Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output  © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 527 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Figure 35-10. MSSP Block Diagram (I2C Slave mode) Rev. 30-000020A 4/3/2017 Internal Data Bus Read Write SSPxCLKPPS(2) SCL SSPxBUF Reg PPS PPS Shift Clock Clock Stretching SSPSR Reg LSb MSb RxyPPS(2) SSPxMSK Reg (1) SSPxDATPPS SDA Addr Match Match Detect PPS SSPxADD Reg PPS Start and Stop bit Detect RxyPPS(1) Set, Reset S, P bits (SSPxSTAT Reg) Note 1: SDA pin selections must be the same for input and output 2: SCL pin selections must be the same for input and output The I2C bus specifies two signal connections: • • Serial Clock (SCL) Serial Data (SDA) Both the SCL and SDA connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. Pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. The following diagram shows a typical connection between two processors configured as master and slave devices. Figure 35-11. I2C Master/ Slave Connection Rev. 30-000021A 4/3/2017 VDD SCL SCL VDD Master Slave SDA SDA The I2C bus can operate with one or more master devices and one or more slave devices. There are four potential modes of operation for a given device: ©2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 528 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module • • • • Master Transmit mode (master is transmitting data to a slave) Master Receive mode (master is receiving data from a slave) Slave Transmit mode (slave is transmitting data to a master) Slave Receive mode (slave is receiving data from the master) To begin communication, a master device starts out in Master Transmit mode. The master device sends out a Start bit followed by the address byte of the slave it intends to communicate with. This is followed by a single Read/Write bit, which determines whether the master intends to transmit to or receive data from the slave device. If the requested slave exists on the bus, it will respond with an Acknowledge bit, otherwise known as an ACK. The master then continues in either Transmit mode or Receive mode and the slave continues in the complement, either in Receive mode or Transmit mode, respectively. A Start bit is indicated by a high-to-low transition of the SDA line while the SCL line is held high. Address and data bytes are sent out, Most Significant bit (MSb) first. The Read/Write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. The Acknowledge bit (ACK) is an active-low signal, which holds the SDA line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. The transition of a data bit is always performed while the SCL line is held low. Transitions that occur while the SCL line is held high are used to indicate Start and Stop bits. If the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ACK bit. In this example, the master device is in Master Transmit mode and the slave is in Slave Receive mode. If the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ACK bit. In this example, the master device is in Master Receive mode and the slave is Slave Transmit mode. On the last byte of data communicated, the master device may end the transmission by sending a Stop bit. If the master device is in Receive mode, it sends the Stop bit in place of the last ACK bit. A Stop bit is indicated by a low-to-high transition of the SDA line while the SCL line is held high. In some cases, the master may want to maintain control of the bus and re-initiate another transmission. If so, the master device may send another Start bit in place of the Stop bit or last ACK bit when it is in receive mode. The I2C bus specifies three message protocols; • • • Single message where a master writes data to a slave. Single message where a master reads data from a slave. Combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCL line, is called clock stretching. Clock stretching gives slave devices a © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 529 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module mechanism to control the flow of data. When this detection is used on the SDA line, it is called arbitration. Arbitration ensures that there is only one master device communicating at any single time. 35.3.1 Register Definitions: I2C Mode The MSSPx module has seven registers for I2C operation. These are: • • • • • • • • MSSP Status register (SSPxSTAT) MSSP Control register 1 (SSPxCON1) MSSP Control register 2 (SSPxCON2) MSSP Control register 3 (SSPxCON3) Serial Receive/Transmit Buffer register (SSPxBUF) MSSP Address register (SSPxADD) I2C Slave Address Mask register (SSPxMSK) MSSP Shift register (SSPSR) – not directly accessible SSPxCON1, SSPxCON2, SSPxCON3 and SSPxSTAT are the Control and STATUS registers in I2C mode operation. The SSPxCON1, SSPxCON2, and SSPxCON3 registers are readable and writable. The lower six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. SSPSR is the Shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. SSPxADD contains the slave device address when the MSSP is configured in I2C Slave mode. When the MSSP is configured in Master mode, the lower seven bits of SSPxADD act as the Baud Rate Generator reload value. SSPxMSK holds the slave address mask value when the module is configured for 7-Bit Address Masking mode. While it is a separate register, it shares the same SFR address as SSPxADD; it is only accessible when the SSPM bits are specifically set to permit access. In receive operations, SSPSR and SSPxBUF together, create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPSR. 35.4 I2C Mode Operation All MSSP I2C communication is byte oriented and shifted out MSb first. Six SFR registers and two ® interrupt flags interface the module with the PIC microcontroller and user software. Two pins, SDA and SCL, are exercised by the module to communicate with other external I2C devices. 35.4.1 Clock Stretching When a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. An addressed slave device may hold the SCL clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. The master that is communicating with the slave will attempt to raise the SCL line in order to transfer the next bit, but will detect that the clock line has not yet been released. Because the SCL connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. Clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 530 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.4.2 Arbitration Each master device must monitor the bus for Start and Stop bits. If the device detects that the bus is busy, it cannot begin a new message until the bus returns to an Idle state. However, two master devices may try to initiate a transmission on or about the same time. When this occurs, the process of arbitration begins. Each transmitter checks the level of the SDA data line and compares it to the level that it expects to find. The first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the SDA line. For example, if one transmitter holds the SDA line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the SDA line will be low. The first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. The first transmitter to notice this difference is the one that loses arbitration and must stop driving the SDA line. If this transmitter is also a master device, it also must stop driving the SCL line. It then can monitor the lines for a Stop condition before trying to reissue its transmission. In the meantime, the other device that has not noticed any difference between the expected and actual levels on the SDA line continues with its original transmission. It can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. Slave Transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. If two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. When two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. Arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support. 35.4.3 Byte Format All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back. After the eighth falling edge of the SCL line, the device outputting data on the SDA changes that pin to an input and reads in an acknowledge value on the next clock pulse. The clock signal, SCL, is provided by the master. Data is valid to change while the SCL signal is low, and sampled on the rising edge of the clock. Changes on the SDA line while the SCL line is high define special conditions on the bus, explained below. 35.4.4 Definition of I2C Terminology There is language and terminology in the description of I2C communication that have definitions specific to I2C. That word usage is defined below and may be used in the rest of this document without explanation. This table was adapted from the Philips I2C specification. TERM Description Transmitter The device which shifts data out onto the bus. Receiver The device which shifts data in from the bus. Master The device that initiates a transfer, generates clock signals and terminates a transfer. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 531 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module TERM Description Slave The device addressed by the master. Multi-master A bus with more than one device that can initiate data transfers. Arbitration Procedure to ensure that only one master at a time controls the bus. Winning arbitration ensures that the message is not corrupted. Synchronization Procedure to synchronize the clocks of two or more devices on the bus. Idle No master is controlling the bus, and both SDA and SCL lines are high. Active Any time one or more master devices are controlling the bus. Addressed Slave Slave device that has received a matching address and is actively being clocked by a master. Matching Address Address byte that is clocked into a slave that matches the value stored in SSPxADD. 35.4.5 Write Request Slave receives a matching address with R/W bit clear, and is ready to clock in data. Read Request Master sends an address byte with the R/W bit set, indicating that it wishes to clock data out of the Slave. This data is the next and all following bytes until a Restart or Stop. Clock Stretching When a device on the bus hold SCL low to stall communication. Bus Collision Any time the SDA line is sampled low by the module while it is outputting and expected high state. SDA and SCL Pins Selection of any I2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open-drain. These pins should be set by the user to inputs by setting the appropriate TRIS bits. Note:  1. Data is tied to output zero when an I2C mode is enabled. 2. Any device pin can be selected for SDA and SCL functions with the PPS peripheral. These functions are bidirectional. The SDA input is selected with the SSPxDATPPS registers. The SCL input is selected with the SSPxCLKPPS registers. Outputs are selected with the RxyPPS registers. It is the user’s responsibility to make the selections so that both the input and the output for each function is on the same pin. 35.4.6 SDA Hold Time The hold time of the SDA pin is selected by the SDAHT bit. Hold time is the time SDA is held valid after the falling edge of SCL. Setting the SDAHT bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. I2C Bus Terms 35.4.7 Start Condition The I2C specification defines a Start condition as a transition of SDA from a high to a low state while SCL line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an Active state. Figure 35-12 shows wave forms for Start and Stop conditions. A bus collision can occur on a Start condition if the module samples the SDA line low before asserting it low. This does not conform to the I2C Specification that states no bus collision can occur on a Start. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 532 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.4.8 Stop Condition A Stop condition is a transition of the SDA line from low-to-high state while the SCL line is high. Important:  At least one SCL low time must appear before a Stop is valid, therefore, if the SDA line goes low then high again while the SCL line stays high, only the Start condition is detected. Figure 35-12. I2C Start and Stop Conditions Rev. 30-000022A 4/3/2017 SDA SCL S Start Condition 35.4.9 P Change of Change of Data Allowed Data Allowed Stop Condition Restart Condition A Restart is valid any time that a Stop would be valid. A master can issue a Restart if it wishes to hold the bus after terminating the current transfer. A Restart has the same effect on the slave that a Start would, resetting all slave logic and preparing it to clock in an address. The master may want to address the same or another slave. Figure 35-13 shows the wave form for a Restart condition. In 10-bit Addressing Slave mode a Restart is required for the master to clock data out of the addressed slave. Once a slave has been fully addressed, matching both high and low address bytes, the master can issue a Restart and the high address byte with the R/W bit set. The slave logic will then hold the clock and prepare to clock out data. After a full match with R/W clear in 10-bit mode, a prior match flag is set and maintained until a Stop condition, a high address with R/W clear, or high address match fails. Figure 35-13. I2C Restart Condition Rev. 30-000023A 4/3/2017  Sr Change of Change of Data Allowed Restart Condition Data Allowed  © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 533 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.4.10 Start/Stop Condition Interrupt Masking The SCIE and PCIE bits can enable the generation of an interrupt in Slave modes that do not typically support this function. These bits will have no effect in Slave modes where interrupt on Start and Stop detect are already enabled. 35.4.11 Acknowledge Sequence The ninth SCL pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDA line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDA line low indicates to the transmitter that the device has received the transmitted data and is ready to receive more. The result of an ACK is placed in the ACKSTAT bit. Slave software, when the AHEN and DHEN bits are set, allow the user to set the ACK value sent back to the transmitter. The ACKDT bit is set/cleared to determine the response. Slave hardware will generate an ACK response if both the AHEN and DHEN bits are clear. However, tf the BF bit or the SSPOV bit are set when a byte is received then the ACK will not be sent by the slave. When the module is addressed, after the eighth falling edge of SCL on the bus, the ACKTIM bit is set. The ACKTIM bit indicates the acknowledge time of the active bus. The ACKTIM Status bit is only active when either the AHEN bit or DHEN bit is enabled. 35.5 I2C Slave Mode Operation The MSSP Slave mode operates in one of four modes selected by the SSPM bits. The modes can be divided into 7-bit and 10-bit Addressing mode. 10-bit Addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. Modes with Start and Stop bit interrupts operate the same as the other modes with SSPxIF additionally getting set upon detection of a Start, Restart, or Stop condition. 35.5.1 Slave Mode Addresses The SSPxADD register contains the Slave mode address. The first byte received after a Start or Restart condition is compared against the value stored in this register. If the byte matches, the value is loaded into the SSPxBUF register and an interrupt is generated. If the value does not match, the module goes idle and no indication is given to the software that anything happened. The SSPxMSK register affects the address matching process. See 35.5.9 SSP Mask Register for more information. 35.5.1.1 I2C Slave 7-bit Addressing Mode In 7-bit Addressing mode, the LSb of the received data byte is ignored when determining if there is an address match. 35.5.1.2 I2C Slave 10-bit Addressing Mode In 10-bit Addressing mode, the first received byte is compared to the binary value of ‘1 1 1 1 0 A9 A8 0’. A9 and A8 are the two MSb’s of the 10-bit address and stored in bits 2 and 1 of the SSPxADD register. After the acknowledge of the high byte the UA bit is set and SCL is held low until the user updates SSPxADD with the low address. The low address byte is clocked in and all eight bits are compared to the low address value in SSPxADD. Even if there is not an address match; SSPxIF and UA are set, and SCL © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 534 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module is held low until SSPxADD is updated to receive a high byte again. When SSPxADD is updated the UA bit is cleared. This ensures the module is ready to receive the high address byte on the next communication. A high and low address match as a write request is required at the start of all 10-bit addressing communication. A transmission can be initiated by issuing a Restart once the slave is addressed, and clocking in the high address with the R/W bit set. The slave hardware will then acknowledge the read request and prepare to clock out data. This is only valid for a slave after it has received a complete high and low address byte match. 35.5.2 Slave Reception When the R/W bit of a matching received address byte is clear, the R/W bit is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF is set, or bit SSPOV is set. The BOEN bit modifies this operation. For more information see SSPxCON3. An MSSP interrupt is generated for each transferred data byte. Flag bit, SSPxIF, must be cleared by software. When the SEN bit is set, SCL will be held low (clock stretch) following each received byte. The clock must be released by setting the CKP bit, except sometimes in 10-bit mode. See 35.5.6.2 10-bit Addressing Mode for more detail. 35.5.2.1 7-bit Addressing Reception This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 7-bit Addressing mode. Figure 35-14 and Figure 35-15 is used as a visual reference for this description. This is a step by step process of what typically must be done to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. Start bit detected. S bit is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is received. The slave pulls SDA low sending an ACK to the master, and sets SSPxIF bit. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. If SEN = 1; Slave software sets CKP bit to release the SCL line. 8. 9. 10. 11. 12. 13. The master clocks out a data byte. Slave drives SDA low sending an ACK to the master, and sets SSPxIF bit. Software clears SSPxIF. Software reads the received byte from SSPxBUF clearing BF. Steps 8-12 are repeated for all received bytes from the master. Master sends Stop condition, setting P bit, and the bus goes idle. 35.5.2.2 7-bit Reception with AHEN and DHEN Slave device reception with AHEN and DHEN set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of SCL. These additional interrupts allow the slave software to decide whether it wants to ACK the receive address or data byte, rather than the hardware. This functionality adds support for PMBus™ that was not present on previous versions of this module. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 535 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module This list describes the steps that need to be taken by slave software to use these options for I2C communication. Figure 35-16 displays a module using both address and data holding. Figure 35-17 includes the operation with the SEN bit of the SSPxCON2 register set. 1. 2. 3. 4. 5. 6. 7. 8. 9. S bit is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit clear is clocked in. SSPxIF is set and CKP cleared after the eighth falling edge of SCL. Slave clears the SSPxIF. Slave can look at the ACKTIM bit to determine if the SSPxIF was after or before the ACK. Slave reads the address value from SSPxBUF, clearing the BF flag. Slave sets ACK value clocked out to the master by setting ACKDT. Slave releases the clock by setting CKP. SSPxIF is set after an ACK, not after a NACK. If SEN = 1, the slave hardware will stretch the clock after the ACK. 10. Slave clears SSPxIF. Important:  SSPxIF is still set after the ninth falling edge of SCL even if there is no clock stretching and BF has been cleared. Only if NACK is sent to master is SSPxIF not set 11. 12. 13. 14. 15. SSPxIF set and CKP cleared after eighth falling edge of SCL for a received data byte. Slave looks at ACKTIM bit to determine the source of the interrupt. Slave reads the received data from SSPxBUF clearing BF. Steps 7-14 are the same for each received data byte. Communication is ended by either the slave sending an ACK = 1, or the master sending a Stop condition. If a Stop is sent and Interrupt on Stop Detect is disabled, the slave will only know by polling the P bit. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 536 © 2018 Microchip Technology Inc.  SSPOV BF SSPxIF SCL SDA S 1 A7 2 A6 3 A5 4 A4 5 A3 Receiving Address 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 First byte of dat a is avai labl e in SSPx BUF 1 D6 4 D4 5 D3 6 D2 7 D1 SSPOV set because SSPxBUF is still full. ACK is not sent. Cleared by software 3 D5 Receiving Data From Slave to Master D0 ACK D7 Figure 35-14. I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 0, DHEN = 0) 8 D0 9 P SSPxIF set on 9th falling edge of SCL ACK = 1 Bus Master sends Stop condition Rev. 30-000024A 4/10/2017 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Datasheet Preliminary DS40002038B-page 537 © 2018 Microchip Technology Inc.  Datasheet Preliminary CKP SSPOV BF SSPxIF 1 SCL S A7 SDA 2 A6 3 A5 4 A4 5 A3 Receive Address 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCL SSPxBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data Figure 35-15. I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) 9 ACK SEN 3 D5 4 D4 5 D3 6 D2 7 D1 CKP is written to ‘1’ in software, releasing SCL SSPOV set because SSPxBUF is still full. ACK is not sent. Cleared by software 2 D6 First byte of dat a is avai labl e in SSPx BUF 1 D7 Receive Data 8 D0 9 ACK Rev. 30-000025A 4/3/2017 SCL is not held low because ACK= 1 SSPxIF set on 9th falling edge of SCL P Bus Master sends Stop condition PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module DS40002038B-page 538 © 2018 Microchip Technology Inc.  S Datasheet Preliminary P S ACKTIM CKP ACKDT BF SSPxIF SCL SDA Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPxIF is set 4 ACKTIM set by hardware on 8th falling edge of SCL When AHEN=1: CKP is cleared by hardware and SCL is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCL When DHEN=1: CKP is cleared by hardware on 8th falling edge of SCL SSPxIF is set on 9th falling edge of SCL, after ACK 1 8 ACK D7 D6 D5 D4 D3 D2 D1 D0 Master Releases SDA to slave for ACK sequence Figure 35-16. I2C Slave, 7-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 1) Received Data 1 2 4 5 6 ACKTIM set by hardware on 8th falling edge of SCL CKP set by software, SCL is released 8 Slave software sets ACKDT to not ACK 7 Cleared by software 3 D7 D6 D5 D4 D3 D2 D1 D0 Data is read from SSPxBUF 9 ACK 9 P No interrupt after not ACK from Slave ACK=1 Master sends Stop condition Rev. 30-000026A 4/3/2017 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module DS40002038B-page 539 © 2018 Microchip Technology Inc.  Datasheet Preliminary S P S ACKTIM CKP ACKDT BF SSPxIF SCL SDA R/W = 0 4 5 6 7 8 When AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte Received address is loaded into SSPxBUF 2 3 ACKTIM is set by hardware on 8th falling edge of SCL 1 A7 A6 A5 A4 A3 A2 A1 Receiving Address 9 ACK Receive Data 2 3 4 5 6 7 8 ACKTIM is cleared by hardware on 9th rising edge of SCL When DHEN = 1; on the 8th falling edge of SCL of a received data byte, CKP is cleared Received data is available on SSPxBUF Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 D0 Master releases SDA to slave for ACK sequence 9 ACK Figure 35-17. I2C Slave, 7-bit Address, Reception (SEN = 1, AHEN = 1, DHEN = 1) Receive Data 1 3 4 5 6 7 8 Set by software, release SCL Slave sends not ACK SSPxBUF can be read any time before next byte is loaded 2 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK CKP is not cleared if not ACK No interrupt after if not ACK from Slave P Master sends Stop condition Rev. 30-000027A 4/3/2017 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module DS40002038B-page 540 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.5.3 Slave Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. Following the ACK, slave hardware clears the CKP bit and the SCL pin is held low (see 35.5.6 Clock Stretching for more detail). By stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. The transmit data must be loaded into the SSPxBUF register which also loads the SSPSR register. Then the SCL pin should be released by setting the CKP bit. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time. The ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. This ACK value is copied to the ACKSTAT bit. If ACKSTAT is set (not ACK), then the data transfer is complete. In this case, when the not ACK is latched by the slave, the slave goes idle and waits for another occurrence of the Start bit. If the SDA line was low (ACK), the next transmit data must be loaded into the SSPxBUF register. Again, the SCL pin must be released by setting bit CKP. An MSSP interrupt is generated for each data transfer byte. The SSPxIF bit must be cleared by software and the SSPxSTAT register is used to determine the status of the byte. The SSPxIF bit is set on the falling edge of the ninth clock pulse. 35.5.3.1 Slave Mode Bus Collision A slave receives a Read request and begins shifting data out on the SDA line. If a bus collision is detected and the SBCDE bit is set, the BCLxIF bit of the PIRx register is set. Once a bus collision is detected, the slave goes idle and waits to be addressed again. User software can use the BCLxIF bit to handle a slave bus collision. 35.5.3.2 7-bit Transmission A master device can transmit a read request to a slave, and then clock data out of the slave. The list below outlines what software for a slave will need to do to accomplish a standard transmission. Figure 35-18 can be used as a reference to this list. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Master sends a Start condition on SDA and SCL. S bit is set; SSPxIF is set if interrupt on Start detect is enabled. Matching address with R/W bit set is received by the Slave setting SSPxIF bit. Slave hardware generates an ACK and sets SSPxIF. SSPxIF bit is cleared by user. Software reads the received address from SSPxBUF, clearing BF. R/W is set so CKP was automatically cleared after the ACK. The slave software loads the transmit data into SSPxBUF. CKP bit is set releasing SCL, allowing the master to clock the data out of the slave. SSPxIF is set after the ACK response from the master is loaded into the ACKSTAT register. SSPxIF bit is cleared. The slave software checks the ACKSTAT bit to see if the master wants to clock out more data. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 541 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Important:  1. If the master ACKs then the clock will be stretched. 2. ACKSTAT is the only bit updated on the rising edge of the ninth SCL clock instead of the falling edge. 13. Steps 9-13 are repeated for each transmitted byte. 14. If the master sends a not ACK; the clock is not held, but SSPxIF is still set. 15. The master sends a Restart condition or a Stop. 16. The slave is no longer addressed. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 542 © 2018 Microchip Technology Inc.  S Datasheet Preliminary P S D/A R/W ACKSTAT CKP BF SSPxIF SCL SDA 1 2 5 6 7 8 Indicates an address has been received R/W is copied from the matching address byte 9 R/W = 1 Automatic ACK Received address is read from SSPxBUF 4 When R/W is set SCL is always held low after 9th SCL falling edge 3 A7 A6 A5 A4 A3 A2 A1 Receiving Address Transmitting Data Automatic 2 3 4 5 Set by software Data to transmit is loaded into SSPxBUF Cleared by software 1 6 7 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Figure 35-18. I2C Slave, 7-bit Address, Transmission (AHEN = 0) Transmitting Data 2 3 4 5 7 8 CKP is not held for not ACK 6 Masters not ACK is copied to ACKSTAT BF is automatically cleared after 8th falling edge of SCL 1 D7 D6 D5 D4 D3 D2 D1 D0 9 ACK P Master sends Stop condition Rev. 30-000028A 4/3/2017 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module DS40002038B-page 543 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 35-19 displays a standard waveform of a 7-bit address slave transmission with AHEN enabled. 1. 2. 3. Bus starts Idle. Master sends Start condition; the S bit is set; SSPxIF is set if interrupt on Start detect is enabled. Master sends matching address with R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSPxIF interrupt is generated. 4. Slave software clears SSPxIF. 5. Slave software reads the ACKTIM, R/W and D/A bits to determine the source of the interrupt. 6. Slave reads the address value from the SSPxBUF register clearing the BF bit. 7. Slave software decides from this information if it wishes to ACK or not ACK and sets the ACKDT bit accordingly. 8. Slave sets the CKP bit releasing SCL. 9. Master clocks in the ACK value from the slave. 10. Slave hardware automatically clears the CKP bit and sets SSPxIF after the ACK if the R/W bit is set. 11. Slave software clears SSPxIF. 12. Slave loads value to transmit to the master into SSPxBUF setting the BF bit. Important:  SSPxBUF cannot be loaded until after the ACK. 13. 14. 15. 16. 17. Slave sets the CKP bit releasing the clock. Master clocks out the data from the slave and sends an ACK value on the ninth SCL pulse. Slave hardware copies the ACK value into the ACKSTAT bit. Steps 10-15 are repeated for each byte transmitted to the master from the slave. If the master sends a not ACK the slave releases the bus allowing the master to send a Stop and end the communication. Important:  Master must send a not ACK on the last byte to ensure that the slave releases the SCL line to receive a Stop. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 544 © 2018 Microchip Technology Inc.  Datasheet Preliminary D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPxIF SCL SDA S 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCL 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address. 1 A7 A6 A5 A4 A3 A2 A1 Receiving Address 3 4 5 6 Cleared by software 2 Set by software, releases SCL Data to transmit is loaded into SSPxBUF 1 7 8 9 Automatic ACK D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data ACKTIM is cleared on 9th rising edge of SCL Automatic Master releases SDA to slave for ACK sequence Figure 35-19. I2C Slave, 7-bit Address, Transmission (AHEN = 1) 1 3 4 5 6 7 after not ACK CKP not cleared Master’s ACK response is copied to SSPxSTAT BF is automatically cleared after 8th falling edge of SCL 2 8 D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data 9 ACK P Master sends Stop condition Rev. 30-00029A 4/10/2017 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module DS40002038B-page 545 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.5.4 Slave Mode 10-bit Address Reception This section describes a standard sequence of events for the MSSP module configured as an I2C slave in 10-bit Addressing mode. Figure 35-20 is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle. Master sends Start condition; S bit is set; SSPxIF is set if interrupt on Start detect is enabled. Master sends matching high address with R/W bit clear; UA bit is set. Slave sends ACK and SSPxIF is set. Software clears the SSPxIF bit. Software reads received address from SSPxBUF clearing the BF flag. Slave loads low address into SSPxADD, releasing SCL. Master sends matching low address byte to the slave; UA bit is set. Important:  Updates to the SSPxADD register are not allowed until after the ACK sequence. 9. Slave sends ACK and SSPxIF is set. Important:  If the low address does not match, SSPxIF and UA are still set so that the slave software can set SSPxADD back to the high address. BF is not set because there is no match. CKP is unaffected. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 35.5.5 Slave clears SSPxIF. Slave reads the received matching address from SSPxBUF clearing BF. Slave loads high address into SSPxADD. Master clocks a data byte to the slave and clocks out the slaves ACK on the ninth SCL pulse; SSPxIF is set. If SEN bit is set, CKP is cleared by hardware and the clock is stretched. Slave clears SSPxIF. Slave reads the received byte from SSPxBUF clearing BF. If SEN is set the slave sets CKP to release the SCL. Steps 13-17 repeat for each received byte. Master sends Stop to end the transmission. 10-bit Addressing with Address or Data Hold Reception using 10-bit addressing with AHEN or DHEN set is the same as with 7-bit modes. The only difference is the need to update the SSPxADD register using the UA bit. All functionality, specifically when the CKP bit is cleared and SCL line is held low are the same. Figure 35-21 can be used as a reference of a slave in 10-bit addressing with AHEN set. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 546 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Figure 35-22 shows a standard waveform for a slave transmitter in 10-bit Addressing mode. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 547 © 2018 Microchip Technology Inc. Datasheet Preliminary CKP UA BF SSPxIF SCL SDA S 1 1 2 1 5 6 7 0 A9 A8 8 Set by hardware on 9th falling edge 4 1 When UA = 1; SCL is held low 9 ACK If address matches SSPxADD it is loaded into SSPxBUF 3 1 Receive First Address Byte 1 3 4 5 6 7 8 Software updates SSPxADD and releases SCL 2 9 A7 A6 A5 A4 A3 A2 A1 A0 ACK Receive Second Address Byte Receive Data 1 3 4 5 6 7 8 9 1 3 4 5 6 7 Data is read from SSPxBUF SCL is held low while CKP = 0 2 8 9 D7 D6 D5 D4 D3 D2 D1 D0 ACK Receive Data Set by software, When SEN = 1; releasing SCL CKP is cleared after 9th falling edge of received byte Receive address is read from SSPxBUF Cleared by software 2 D7 D6 D5 D4 D3 D2 D1 D0 ACK Figure 35-20. I2C Slave, 10-bit Address, Reception (SEN = 1, AHEN = 0, DHEN = 0) P Master sends Stop condition Rev. 30-000030A 4/3/2017 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module DS40002038B-page 548 © 2018 Microchip Technology Inc.  Datasheet Preliminary ACKTIM CKP UA ACKDT BF SSPxIF 1 SCL S 1 SDA 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 8 R/W = 0 ACKTIM is set by hardware on 8th falling edge of SCL If when AHEN = 1; on the 8th falling edge of SCL of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 Receive First Address Byte 9 ACK UA 2 3 A5 4 A4 6 A2 7 A1 Update to SSPxADD is not allowed until 9th falling edge of SCL SSPxBUF can be read anytime before the next received byte 5 A3 Receive Second Address Byte A6 Cleared by software 1 A7 8 A0 Figure 35-21. I2C Slave, 10-bit Address, Reception (SEN = 0, AHEN = 1, DHEN = 0) 9 ACK UA 2 D6 3 D5 4 D4 6 D2 Set CKP with software releases SCL 7 D1 Update of SSPxADD, clears UA and releases SCL 5 D3 Receive Data Cleared by software 1 D7 8 9 2 D6 D5 Received data is read from SSPxBUF 1 D0 ACK D7 Receive Data Rev. 30-000031A 4/3/2017 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module DS40002038B-page 549 © 2018 Microchip Technology Inc.  Datasheet Preliminary D/A R/W ACKSTAT CKP UA BF SSPxIF 4 5 6 7 Set by hardware 3 Indicates an address has been received UA indicates SSPxADD must be updated SSPxBUF loaded with received address 2 8 9 1 SCL S Receiving Address R/W = 0 1 1 1 1 0 A9 A8 ACK SDA 3 4 5 6 7 8 After SSPxADD is updated, UA is cleared and SCL is released Cleared by software 2 9 1 4 5 6 7 8 Set by hardware 2 3 R/W is copied from the matching address byte When R/W = 1; CKP is cleared on 9th falling edge of SCL High address is loaded back into SSPxADD Received address is read from SSPxBUF Sr 1 1 1 1 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ACK 1 Receive First Address Byte Receiving Second Address Byte Master sends Restart event Figure 35-22. I2C Slave, 10-bit Address, Transmission (SEN = 0, AHEN = 0, DHEN = 0) 9 ACK 2 3 4 5 6 7 8 Masters not ACK is copied Set by software releases SCL Data to transmit is loaded into SSPxBUF 1 D7 D6 D5 D4 D3 D2 D1 D0 Transmitting Data Byte 9 P Master sends Stop condition ACK = 1 Master sends not ACK Rev. 30-000032A 4/3/2017 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module DS40002038B-page 550 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.5.6 Clock Stretching Clock stretching occurs when a device on the bus holds the SCL line low, effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. Any stretching done by a slave is invisible to the master software and handled by the hardware that generates SCL. The CKP bit is used to control stretching in software. Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. Setting CKP will release SCL and allow more communication. 35.5.6.1 Normal Clock Stretching Following an ACK if the R/W bit is set, a read request, the slave hardware will clear CKP. This allows the slave time to update SSPxBUF with data to transfer to the master. If the SEN bit is set, the slave hardware will always stretch the clock after the ACK sequence. Once the slave is ready; CKP is set by software and communication resumes. Important:  1. The BF bit has no effect on if the clock will be stretched or not. This is different than previous versions of the module that would not stretch the clock, clear CKP, if SSPxBUF was read before the ninth falling edge of SCL. 2. Previous versions of the module did not stretch the clock for a transmission if SSPxBUF was loaded before the ninth falling edge of SCL. It is now always cleared for read requests. 35.5.6.2 10-bit Addressing Mode In 10-bit Addressing mode, when the UA bit is set, the clock is always stretched. This is the only time the SCL is stretched without CKP being cleared. SCL is released immediately after a write to SSPxADD. Important:  Previous versions of the module did not stretch the clock if the second address byte did not match. 35.5.6.3 Byte NACKing When the AHEN bit is set; CKP is cleared by hardware after the eighth falling edge of SCL for a received matching address byte. When the DHEN bit is set; CKP is cleared after the eighth falling edge of SCL for received data. Stretching after the eighth falling edge of SCL allows the slave to look at the received address or data and decide if it wants to ACK the received data. 35.5.7 Clock Synchronization and the CKP bit Any time the CKP bit is cleared, the module will wait for the SCL line to go low and then hold it. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have released SCL. This ensures that a write to the CKP bit will not violate the minimum high time requirement for SCL (see the following figure). © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 551 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Figure 35-23. Clock Synchronization Timing Rev. 30-000033A 4/3/2017 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 SDA DX ‚ – 1 DX SCL Master device asserts clock CKP Master device releases clock WR SSPxCON1 35.5.8 General Call Address Support The addressing procedure for the I2C bus is such that the first byte after the Start condition usually  determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. The general call address is a reserved address in the I2C protocol, defined as address 0x00. When the GCEN bit is set, the slave module will automatically ACK the reception of this address regardless of the value stored in SSPxADD. After the slave clocks in an address of all zeros with the R/W bit clear, an interrupt is generated and slave software can read SSPxBUF and respond. The following figure shows a general call reception sequence. Figure 35-24. Slave Mode General Call Address Sequence Rev. 30-000034A 4/3/2017 Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 General Call Address SDA SCL S 1 2 3 4 5 6 7 8 9 1 Receiving Data ACK D6 D5 D4 D3 D2 D1 D0 2 3 4 5 6 7 8 9 SSPxIF BF (SSPxSTAT) Cleared by software GCEN (SSPxCON2) SSPxBUF is read ’1’ In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 552 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module If the AHEN bit is set, just as with any other address reception, the slave hardware will stretch the clock after the eighth falling edge of SCL. The slave must then set its ACKEN value and release the clock with communication progressing as it would normally. 35.5.9 SSP Mask Register An SSP Mask register (SSPxMSK) is available in I2C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPxMSK register has the effect of making the corresponding bit of the received address a “don’t care”. This register is reset to all ‘1’s upon any Reset condition and, therefore, has no effect on standard SSP operation until written with a mask value. The SSP Mask register is active during: • • 35.6 7-bit Address mode: address compare of A. 10-bit Address mode: address compare of A only. The SSP mask has no effect during the reception of the first (high) byte of the address. I2C Master Mode Master mode is enabled by setting and clearing the appropriate SSPM bits and setting the SSPEN bit. In Master mode, the SDA and SCK pins must be configured as inputs. The MSSP peripheral hardware will override the output driver TRIS controls when necessary to drive the pins low. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the bus is Idle. In Firmware Controlled Master mode, user code conducts all I2C bus operations based on Start and Stop bit condition detection. Start and Stop condition detection is the only active circuitry in this mode. All other communication is done by the user software directly manipulating the SDA and SCL lines. The following events will cause the SSP Interrupt Flag bit, SSPxIF, to be set (SSP interrupt, if enabled): • • • • • Start condition detected Stop condition detected Data transfer byte transmitted/received Acknowledge transmitted/received Repeated Start generated Important:  1. The MSSP module, when configured in I2C Master mode, does not allow queuing of events. For instance, the user is not allowed to initiate a Start condition and immediately write the SSPxBUF register to initiate transmission before the Start condition is complete. In this case, the SSPxBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPxBUF did not occur. 2. Master mode suspends Start/Stop detection when sending the Start/Stop condition by means of the SEN/PEN control bits. The SSPxIF bit is set at the end of the Start/Stop generation when hardware clears the control bit. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 553 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘0’. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic ‘1’. Thus, the first byte transmitted is a 7-bit slave address followed by a ‘1’ to indicate the receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. Start and Stop conditions indicate the beginning and end of transmission. A Baud Rate Generator is used to set the clock frequency output on SCL. See 35.7 Baud Rate Generator for more detail. 35.6.2 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of 35.9.6 SSPxADD and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count in the event that the clock is held low by an external device as shown in the following figure. Figure 35-25. Baud Rate Generator Timing with Clock Arbitration Rev. 30-000035A 4/3/2017 SDA DX ‚ – 1 DX SCL deasserted but slave holds SCL low (clock arbitration) SCL allowed to transition high SCL BRG decrements on Q2 and Q4 cycles BRG Value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count BRG Reload 35.6.3 WCOL Status Flag If the user writes the SSPxBUF when a Start, Restart, Stop, Receive or Transmit sequence is in progress, the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). Any time the WCOL bit is set it indicates that an action on SSPxBUF was attempted while the module was not idle. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 554 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Important:  Because queuing of events is not allowed, writing to the lower five bits of SSPxCON2 is disabled until the Start condition is complete. 35.6.4 I2C Master Mode Start Condition Timing To initiate a Start condition (Figure 35-26), the user sets the SEN Start Enable bit. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low while SCL is high is the Start condition and causes the S bit to be set. Following this, the Baud Rate Generator is reloaded with the contents of SSPxADD and resumes its count. When the Baud Rate Generator times out (TBRG), the SEN bit will be automatically cleared by hardware; the Baud Rate Generator is suspended, leaving the SDA line held low and the Start condition is complete. Important:  1. If at the beginning of the Start condition, the SDA and SCL pins are already sampled low, or if during the Start condition, the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag, BCLxIF, is set, the Start condition is aborted and the I2C module is reset into its Idle state. 2. The Philips I2C specification states that a bus collision cannot occur on a Start. Figure 35-26. First Start Bit Timing Rev. 30-000036A 4/3/2017 Set S bit (SSPxSTAT) Write to SEN bit occurs here At completion of Start bit, hardware clears SEN bit a nd set s SSPx I F bi t SDA = 1, SCL = 1 TBRG TBRG Write to SSPxBUF occurs here SDA 1st bit 2nd bit TBRG SCL S 35.6.5 TBRG I2C Master Mode Repeated Start Condition Timing A  Repeated Start condition (Figure 35-27) occurs when the RSEN bit is programmed high and the master state machine is no longer active. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting. The SDA pin is released (brought high) for one Baud Rate Generator count (TBRG). When the Baud Rate Generator times out, if SDA is sampled high, the SCL pin will be deasserted (brought high). When SCL is sampled high, the Baud Rate Generator is reloaded and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG while SCL is high. SCL is asserted low. Following this, the RSEN bit will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDA pin held low. As soon as a Start condition is detected on © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 555 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module the SDA and SCL pins, the S bit will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out. Important:  1. If RSEN is programmed while any other event is in progress, it will not take effect. 2. A bus collision during the Repeated Start condition occurs if: – SDA is sampled low when SCL goes from low-to-high. – SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data ‘1’. Figure 35-27. Repeated Start Condition Waveform Rev. 30-000037A 4/10/2017 S bit set by hardware Write to SSPxCON2 occurs here SDA = 1, SCL (no change) At completion of Start bit, hardware clears the RSEN bit and sets SSPxIF SDA = 1, SCL = 1 TBRG TBRG TBRG 1st bit SDA Write to SSPxBUF occurs here TBRG SCL Sr TBRG Repeated Start 35.6.6 I2C Master Mode Transmission Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be  shifted out onto the SDA pin after the falling edge of SCL is asserted. SCL is held low for one Baud Rate Generator rollover count (TBRG). Data should be valid before SCL is released high. When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF flag is cleared and the master releases SDA. This allows the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurred, or if data was received properly. The status of ACK is written into the ACKSTAT bit on the rising edge of the ninth clock. If the master receives an Acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPxIF bit is set and the master clock (Baud Rate Generator) is suspended until the next data byte is loaded into the SSPxBUF, leaving SCL low and SDA unchanged (Figure 35-28). After the write to the SSPxBUF, each bit of the address will be shifted out on the falling edge of SCL until all seven address bits and the R/W bit are completed. On the falling edge of the eighth clock, the master will release the SDA pin, allowing the slave to respond with an Acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT Status bit of the SSPxCON2 register. Following the falling edge of the ninth clock transmission of the address, the SSPxIF is set, the BF flag is cleared and © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 556 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module the Baud Rate Generator is turned off until another write to the SSPxBUF takes place, holding SCL low and allowing SDA to float. 35.6.6.1 BF Status Flag In Transmit mode, the BF bit is set when the CPU writes to SSPxBUF and is cleared when all eight bits are shifted out. 35.6.6.2 WCOL Status Flag If the user writes the SSPxBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). The WCOL bit must be cleared by software before the next transmission. 35.6.6.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit is cleared when the slave has sent an Acknowledge (ACK = 0) and is set when the slave does not Acknowledge (ACK = 1). A slave sends an Acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 35.6.6.4 Typical transmit sequence: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. The user generates a Start condition by setting the SEN bit. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPxBUF with the slave address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. The user loads the SSPxBUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit. Steps 8-11 are repeated for all transmitted data bytes. The user generates a Stop or Restart condition by setting the PEN or RSEN bits. Interrupt is generated once the Stop/Restart condition is complete. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 557 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Figure 35-28. I2C Master Mode Waveform (Transmission, 7 or 10-bit Address) Rev. 30-000038A 4/3/2017 Write SSPxCON2 SEN = 1 Start condition begins From slave, clear ACKSTAT bit SSPxCON2 SEN = 0 A7 A6 A5 A4 A3 A2 Transmitting Data or Second Half of 10-bit Address R/W = 0 Transmit Address to Slave SDA ACKSTAT in SSPxCON2 = 1 ACK = 0 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 1 SCL held low while CPU responds to SSPxIF 2 3 4 5 6 7 8 SSPxBUF written with 7-bit address and R/W start transmit SCL 1 S 2 3 4 5 6 7 8 9 9 P SSPxIF Cleared by software service routine from SSP interrupt Cleared by software Cleared by software BF (SSPxSTAT) SSPxBUF is written by software SSPxBUF written SEN After Start condition, SEN cleared by hardware PEN R/W 35.6.7 I2C Master Mode Reception Master mode reception (Figure 35-29) is enabled by programming the RCEN Receive Enable bit. Important:  The MSSP module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin changes (highto-low/low-to-high) and data is shifted into the SSPSR. After the falling edge of the eighth clock all the following events occur: • The receive enable flag is automatically cleared • The contents of the SSPSR are loaded into the SSPxBUF • The BF flag bit is set • • • The SSPxIF flag bit is set The Baud Rate Generator is suspended from counting The SCL pin is held low The MSSP is now in Idle state awaiting the next command. When the buffer is read by the CPU, the BF flag bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception by setting the Acknowledge Sequence Enable, ACKEN bit. 35.6.7.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPxBUF from SSPSR. It is cleared when the SSPxBUF register is read. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 558 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.6.7.2 SSPOV Status Flag In receive operation, the SSPOV bit is set when eight bits are received into the SSPSR while the BF flag bit is already set from a previous reception. 35.6.7.3 WCOL Status Flag If the user writes the SSPxBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). 35.6.7.4 Typical Receive Sequence: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. The user generates a Start condition by setting the SEN bit. SSPxIF is set by hardware on completion of the Start. SSPxIF is cleared by software. User writes SSPxBUF with the slave address to transmit and the R/W bit set. Address is shifted out the SDA pin until all eight bits are transmitted. Transmission begins as soon as SSPxBUF is written to. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit. The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPxIF bit. User sets the RCEN bit and the master clocks in a byte from the slave. After the eighth falling edge of SCL, SSPxIF and BF are set. Master clears SSPxIF and reads the received byte from SSPUF which clears BF. Master sets the ACK value to be sent to slave in the ACKDT bit and initiates the ACK by setting the ACKEN bit. Master’s ACK is clocked out to the slave and SSPxIF is set. User clears SSPxIF. Steps 8-13 are repeated for each received byte from the slave. Master sends a not ACK or Stop to end communication. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 559 © 2018 Microchip Technology Inc.  S Datasheet Preliminary RCEN ACKEN SSPOV BF (SSPxSTAT) SDA = 0, SCL = 1 while CPU responds to SSPxIF SSPxIF SCL SDA 1 A7 2 4 5 6 Cleared by software 3 A6 A5 A4 A3 A2 Transmit Address to Slave 7 8 9 ACK Receiving Data from Slave 2 3 5 6 7 8 D0 9 ACK Receiving Data from Slave 2 3 4 RCEN cleared automatically 5 6 7 Cleared by software Set SSPxIF interrupt at end of Acknowledge sequence Data shifted in on falling edge of CLK 1 ACK from Master SDA = ACKDT = 0 Cleared in software Set SSPxIF at end of receive 9 ACK is not sent ACK RCEN cleared automatically P Rev. 30-000039A 4/3/2017 Set SSPxIF interrupt at end of Acknowledge sequence Bus master terminates transfer Set P bit (SSPxSTAT) and SSPxIF PEN bit = 1 written here SSPOV is set because SSPxBUF is still full 8 D0 RCEN cleared automatically Set ACKEN, start Acknowledge sequence SDA = ACKDT = 1 D7 D6 D5 D4 D3 D2 D1 Last bit is shifted into SSPSR and contents are unloaded into SSPxBUF Cleared by software Set SSPxIF interrupt at end of receive 4 Cleared by software 1 D7 D6 D5 D4 D3 D2 D1 Master configured as a receiver by programming SSPxCON2 (RCEN = 1) A1 R/W RCEN = 1, start next receive ACK from Master SDA = ACKDT = 0 Write to SSPxCON2 to start Acknowledge sequence SDA = ACKDT (SSPxCON2) = 0 Master configured as a receiver by programming SSPxCON2 (RCEN = 1) SEN = 0 Write to SSPxBUF occurs here, RCEN cleared ACK from Slave automatically start XMIT Write to SSPxCON2(SEN = 1), begin Start condition Figure 35-29. I2C Master Mode Waveform (Reception, 7-bit Address) PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module DS40002038B-page 560 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.6.8 Acknowledge Sequence Timing An Acknowledge sequence is enabled by setting the Acknowledge Sequence Enable ACKEN bit. When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge data bit are presented on the SDA pin. If the user wishes to generate an Acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an Acknowledge sequence. The Baud Rate Generator then counts for one rollover period (TBRG) and the SCL pin is deasserted (pulled high). When the SCL pin is sampled high (clock arbitration), the Baud Rate Generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the Baud Rate Generator is turned off and the MSSP module then goes into Idle mode. Figure 35-30. Acknowledge Sequence Waveform Acknowledge sequence starts here, write to SSPxCON2 ACKEN = 1, ACKDT = 0 ACKEN automatically cleared TBRG TBRG SDA ACK D0 SCL Rev. 30-000040A 4/3/2017 8 9 SSPxIF SSPxIF set at the end of receive Cleared in software Cleared in software SSPxIF set at the end of Acknowledge sequence Note: TBRG = one Baud Rate Generator period. 35.6.8.1 Acknowledge Write Collision If the user writes the SSPxBUF when an Acknowledge sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write does not occur). 35.6.9 Stop Condition Timing A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable PEN bit. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’. When the Baud Rate Generator times out, the SCL pin will be brought high and one TBRG (Baud Rate Generator rollover count) later, the SDA pin will be deasserted. When the SDA pin is sampled high while SCL is high, the P bit is set. One TBRG later, the PEN bit is cleared and the SSPxIF bit is set.  © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 561 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Figure 35-31. Stop Condition in Receive or Transmit Mode SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPxSTAT) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCL SDA Rev. 30-000041A 4/3/2017 ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 35.6.9.1 Write Collision on Stop  the user writes the SSPxBUF when a Stop sequence is in progress, then the WCOL bit is set and the If contents of the buffer are unchanged (the write does not occur). 35.6.10 Sleep Operation While in Sleep mode, the I2C slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 35.6.11 Effects of a Reset A Reset disables the MSSP module and terminates the current transfer. 35.6.12 Multi-Master Mode In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled. Control of the I2C bus may be taken when the P bit is set, or the bus is Idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the Stop condition occurs. In multi-master operation, the SDA line must be monitored for arbitration to see if the signal level is the expected output level. This check is performed by hardware with the result placed in the BCLxIF bit. The states where arbitration can be lost are: • • • • • Address Transfer Data Transfer A Start Condition A Repeated Start Condition An Acknowledge Condition 35.6.13 Multi -Master Communication, Bus Collision and Bus Arbitration Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a ‘1’ on SDA, by letting SDA float high and another master asserts a ‘0’. When the SCL pin floats high, data should be stable. If the expected data on SDA is a ‘1’ and the data sampled on the SDA pin is ‘0’, then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag, BCLxIF and reset the I2C port to its Idle state (Figure 35-32). © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 562 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF flag is cleared, the SDA and SCL lines are deasserted and the SSPxBUF can be written to. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. If a Start, Repeated Start, Stop or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are deasserted and the respective control bits in the SSPxCON2 register are cleared. When the user services the bus collision Interrupt Service Routine and if the I2C bus is free, the user can resume communication by asserting a Start condition. The master will continue to monitor the SDA and SCL pins. If a Stop condition occurs, the SSPxIF bit will be set. A write to the SSPxBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-Master mode, the interrupt generation on the detection of Start and Stop conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set, or the bus is Idle and the S and P bits are cleared. Figure 35-32. Bus Collision Timing for Transmit and Acknowledge Rev. 30-000042A 4/3/2017 Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data does not match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLxIF) BCLxIF 35.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if:  1. 2. SDA or SCL are sampled low at the beginning of the Start condition (Figure 35-33). SCL is sampled low before SDA is asserted low (Figure 35-34). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is already low, or the SCL pin is already low, then all of the following occur: • • • the Start condition is aborted, the BCLxIF flag is set and the MSSP module is reset to its Idle state (Figure 35-33). © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 563 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Figure 35-33. Bus Collision During Start Condition (SDA Only) Rev. 30-000043A 4/3/2017 SDA goes low before the SEN bit is set. Set BCLxIF, S bit and SSPxIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable Start condition if SDA = 1, SCL = 1 SEN cleared automatically because of bus collision. SSPx module reset into Idle state. SEN SDA sampled low before Start condition. Set BCLxIF. S bit and SSPxIF set because SDA = 0, SCL = 1. BCLxIF SSPxIF and BCLxIF are cleared by software S SSPxIF SSPxIF and BCLxIF are cleared by software The Start condition begins with the SDA and SCL pins deasserted. When the SDA pin is sampled high, the Baud Rate Generator is loaded and counts down. If the SCL pin is sampled low while SDA is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ‘1’ during the Start condition. Figure 35-34. Bus Collision During Start Condition (SCL = 0)  Rev. 30-000044A 4/3/2017 SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLxIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLxIF. BCLxIF Interrupt cleared by software ’0’ ’0’ SSPxIF ’0’ ’0’ S © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 564 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 35-35). If, however, a ‘1’ is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The Baud Rate Generator is then reloaded and counts down to zero; if the SCL pin is sampled as ‘0’ during this time, a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Figure 35-35. BRG Reset Due to SDA Arbitration During Start Condition Rev. 30-000045A 4/10/2017 SDA = 0, SCL = 1 Set S Less than TBRG SDA Set SSPxIF TBRG SDA pulled low by other master. Reset BRG and assert SDA. SCL S SCL pulled low after BRG time out SEN BCLxIF Set SEN, enable Start sequence if SDA = 1, SCL = 1 ’0’ S SSPxIF SDA = 0, SCL = 1, set SSPxIF Interrupts cleared by software Important:  The reason that bus collision is not a factor during a Start condition is that no two bus masters can assert a Start condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the Start condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated Start or Stop conditions. 35.6.13.2 Bus Collision During a Repeated Start Condition During a Repeated Start condition, a bus collision occurs if:  1. 2. A low level is sampled on SDA when SCL goes from low level to high level (Case 1). SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data ‘1’ (Case 2). When the user releases SDA and the pin is allowed to float high, the BRG is loaded with SSPxADD and counts down to zero. The SCL pin is then deasserted and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 35-36). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 565 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Figure 35-36. Bus Collision During a Repeated Start Condition (Case 1) Rev. 30-000046A 4/3/2017 SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLxIF and release SDA and SCL. RSEN BCLxIF Cleared by software S ’0’ SSPxIF ’0’ If SCL goes from high-to-low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition, see Figure 35-37. If, at the end of the BRG time out, both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated Start condition is complete. Figure 35-37. Bus Collision During Repeated Start Condition (Case 2) Rev. 30-000047A 4/3/2017 TBRG TBRG SDA SCL BCLxIF SCL goes low before SDA, set BCLxIF. Release SDA and SCL. Interrupt cleared by software RSEN  ’0’ S SSPxIF 35.6.13.3 Bus Collision During a Stop Condition  Bus collision occurs during a Stop condition if: 1. 2. After the SDA pin has been deasserted and allowed to float high, SDA is sampled low after the BRG has timed out (Case 1). After the SCL pin is deasserted, SCL is sampled low before SDA goes high (Case 2). The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 566 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module and counts down to zero. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 35-38). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data ‘0’ (Figure 35-39). Figure 35-38. Bus Collision During a Stop Condition (Case 1) Rev. 30-000048A 4/3/2017 TBRG TBRG TBRG SDA SDA sampled low after TBRG, set BCLxIF SDA asserted low SCL PEN BCLxIF P ’0’ SSPxIF ’0’ Figure 35-39. Bus Collision During a Stop Condition (Case 2) Rev. 30-000049A 4/3/2017 TBRG TBRG TBRG SDA Assert SDA SCL SCL goes low before SDA goes high, set BCLxIF PEN BCLxIF 35.7 P ’0’ SSPxIF ’0’ Baud Rate Generator The MSSP module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register. When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. An internal signal “Reload” shown in Figure 35-40 triggers the value from SSPxADD to be loaded into the BRG counter. This occurs twice for each oscillation of the module clock line. The logic dictating when the reload signal is asserted depends on the mode in which the MSSP is being operated.   © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 567 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Table 35-1 illustrates clock rates based on instruction cycles and the BRG value loaded into SSPxADD. Example 35-1. MSSP Baud Rate Generator Frequency Equation ������ = ���� 4 × ������� + 1` Figure 35-40. Baud Rate Generator Block Diagram Rev. 30-000050A 4/3/2017 SSPM SSPM Reload SCL Control SSPCLK SSPxADD Reload BRG Down Counter F OSC/2 Important:  Values of 0x00, 0x01 and 0x02 are not valid for SSPxADD when used as a Baud Rate Generator for I2C. This is an implementation limitation. Table 35-1. MSSP Clock Rate w/BRG FOSC FCY BRG Value Fclock (2 Rollovers of BRG) 32 MHz 8 MHz 13h 400 kHz 32 MHz 8 MHz 19h 308 kHz 32 MHz 8 MHz 4Fh 100 kHz 16 MHz 4 MHz 09h 400 kHz 16 MHz 4 MHz 0Ch 308 kHz 16 MHz 4 MHz 27h 100 kHz 4 MHz 1 MHz 09h 100 kHz Note:  Refer to the I/O port electrical specifications in the "Electrical Specifications" section, Internal Oscillator Parameters, to ensure the system is designed to support Iol requirements.  © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 568 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.8 Register Summary: MSSP Control Address Name Bit Pos. 0x018C SSP1BUF 7:0 0x018D SSP1ADD 7:0 0x018E SSP1MSK 7:0 0x018F SSP1STAT 7:0 SMP CKE D/A P 0x0190 SSP1CON1 7:0 WCOL SSPOV SSPEN CKP 0x0191 SSP1CON2 7:0 GCEN ACKSTAT ACKDT ACKEN RCEN 0x0192 SSP1CON3 7:0 ACKTIM PCIE SCIE BOEN SDAHT BUF[7:0] ADD[7:0] MSK[6:0] MSK0 S R/W UA BF PEN RSEN SEN SBCDE AHEN DHEN R/W UA SSPM[3:0] 0x0193 ... Reserved 0x0195 0x0196 SSP2BUF 7:0 BUF[7:0] 0x0197 SSP2ADD 7:0 ADD[7:0] 0x0198 SSP2MSK 7:0 0x0199 SSP2STAT 7:0 SMP CKE D/A P 0x019A SSP2CON1 7:0 WCOL SSPOV SSPEN CKP 0x019B SSP2CON2 7:0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0x019C SSP2CON3 7:0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 35.9 MSK[6:0] MSK0 S BF SSPM[3:0] Register Definitions: MSSP Control © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 569 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.9.1 SSPxSTAT Name:  SSPxSTAT Address:  0x18F,0x199 MSSP Status Register Bit Access Reset 7 6 5 4 3 2 1 0 SMP CKE D/A P S R/W UA BF R/W R/W RO RO RO RO RO RO 0 0 0 0 0 0 0 0 Bit 7 – SMP Slew Rate Control bit Value 1 0 0 1 0 Mode SPI Master SPI Master SPI Slave I2C I2C Description Input data is sampled at the end of data output time Input data is sampled at the middle of data output time Keep this bit cleared in SPI Slave mode Slew rate control is disabled for Standard Speed mode (100 kHz and 1 MHz) Slew rate control is enabled for High-Speed mode (400 kHz) Bit 6 – CKE SPI: Clock select bit(4) I2C: SMBus Select bit Value 1 0 1 0 Mode SPI SPI I2C I2C Description Transmit occurs on the transition from active to Idle clock state Transmit occurs on the transition from Idle to active clock state Enables SMBus-specific inputs Disables SMBus-specific inputs Bit 5 – D/A Data/Address bit Value x 1 0 Mode SPI or I2C Master I2C Slave I2C Slave Description Reserved Indicates that the last byte received or transmitted was data Indicates that the last byte received or transmitted was address Bit 4 – P Stop bit(1) Value x 1 0 Mode SPI I2C I2C Description Reserved Stop bit was detected last Stop bit was not detected last Bit 3 – S Start bit(1) © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 570 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Value x 1 0 Mode SPI I2C I2C Description Reserved Start bit was detected last Start bit was not detected last Bit 2 – R/W Read/Write Information bit(2,3) Value x 1 0 1 0 Mode SPI I2C Slave I2C Slave I2C Master I2C Master Description Reserved Read Write Transmit is in progress Transmit is not in progress Bit 1 – UA Update Address bit (10-Bit Slave mode only) Value x 1 0 Mode Description All other modes Reserved I2C 10-bit Slave Indicates that the user needs to update the address in the SSPxADD register I2C 10-bit Slave Address does not need to be updated Bit 0 – BF Buffer Full Status bit(5) Value 1 0 1 0 Mode I2C Transmit I2C Transmit SPI and I2C Receive SPI and I2C Receive Description Character written to SSPxBUF has not been sent SSPxBUF is ready for next character Received character in SSPxBUF has not been read Received character in SSPxBUF has been read Note:  1. This bit is cleared on Reset and when SSPEN is cleared. 2. In I2C Slave mode this bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next Start bit, Stop bit or not ACK bit. 3. ORing this bit with SEN, RSEN, PEN, RCEN or ACKEN will indicate if the MSSP is in Active mode. 4. Polarity of clock state is set by the CKP bit. 5. I2C receive status does not include ACK and Stop bits. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 571 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.9.2 SSPxCON1 Name:  SSPxCON1 Address:  0x190,0x19A MSSP Control Register 1 Bit Access Reset 7 6 5 4 WCOL SSPOV SSPEN CKP 3 R/W/HS R/W/HS R/W R/W R/W 0 0 0 0 0 2 1 0 R/W R/W R/W 0 0 0 SSPM[3:0] Bit 7 – WCOL Write Collision Detect bit Value 1 Mode SPI 1 I2C Master transmit 1 I2C Slave transmit 0 SPI or I2C Master or Slave transmit Master or Slave receive x Description A write to the SSPxBUF register was attempted while the previous byte was still transmitting (must be cleared by software) A write to the SSPxBUF register was attempted while the I2C conditions were not valid for a transmission to be started (must be cleared by software) The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) No collision Don't care Bit 6 – SSPOV Receive Overflow Indicator bit(1) Value 1 Mode SPI Slave 1 I2C Receive 0 SPI Slave or I2C Receive SPI Master or I2C Master transmit x Description A byte is received while the SSPxBUF register is still holding the previous byte. The user must read SSPxBUF, even if only transmitting data, to avoid setting overflow. (must be cleared in software) A byte is received while the SSPxBUF register is still holding the previous byte (must be cleared in software) No overflow Don't care Bit 5 – SSPEN Master Synchronous Serial Port Enable bit.(2) © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 572 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Value 1 1 0 Mode Description SPI Enables the serial port. The SCKx, SDOx, SDIx, and SSx pin selections must be made with the PPS controls. Each signal must be configured with the corresponding TRIS control to the direction appropriate for the mode selected. I2C Enables the serial port. The SDAx and SCLx pin selections must be made with the PPS controls. Since both signals are bidirectional the PPS input pin and PPS output pin selections must be made that specify the same pin. Both pins must be configured as inputs with the corresponding TRIS controls. All Disables serial port and configures these pins as I/O port pins Bit 4 – CKP SCK Release Control bit Value 1 0 1 0 x Mode SPI SPI I2C Slave I2C Slave I2C Master Description Idle state for the clock is a high level Idle state for the clock is a low level Releases clock Holds clock low (clock stretch), used to ensure data setup time Unused in this mode Bits 3:0 – SSPM[3:0] Master Synchronous Serial Port Mode Select bits(4) Value 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Description I2C Slave mode: 10-bit address with Start and Stop bit interrupts enabled I2C Slave mode: 7-bit address with Start and Stop bit interrupts enabled Reserved - do not use Reserved - do not use I2C Firmware Controlled Master mode (slave Idle) SPI Master mode: Clock = FOSC/(4*(SSPxADD+1)). SSPxADD must be greater than 0.(3) Reserved - do not use I2C Master mode: Clock = FOSC/(4 * (SSPxADD + 1)) I2C Slave mode: 10-bit address I2C Slave mode: 7-bit address SPI Slave mode: Clock = SCKx pin. SSx pin control is disabled SPI Slave mode: Clock = SCKx pin. SSx pin control is enabled SPI Master mode: Clock = TMR2 output/2 SPI Master mode: Clock = Fosc/64 SPI Master mode: Clock = Fosc/16 SPI Master mode: Clock = Fosc/4 Note:  1. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2. When enabled, these pins must be properly configured as inputs or outputs. 3. SSPxADD = 0 is not supported. 4. Bit combinations not specifically listed here are either reserved or implemented in I2C mode only. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 573 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.9.3 SSPxCON2 Name:  SSPxCON2 Address:  0x191,0x19B Control Register for I2C Operation Only MSSP Control Register 2 Bit Access Reset 7 6 5 4 3 2 1 0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN R/W R/W/HC R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – GCEN General Call Enable bit (Slave mode only) Value x 1 0 Mode Master mode Slave mode Slave mode Description Don't care General call is enabled General call is not enabled Bit 6 – ACKSTAT Acknowledge Status bit (Master Transmit mode only) Value 1 0 Description Acknowledge was not received from slave Acknowledge was received from slave Bit 5 – ACKDT Acknowledge Data bit (Master Receive mode only)(1) Value 1 0 Description Not Acknowledge Acknowledge Bit 4 – ACKEN Acknowledge Sequence Enable bit(2) Value 1 0 Description Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; automatically cleared by hardware Acknowledge sequence is Idle Bit 3 – RCEN Receive Enable bit (Master Receive mode only)(2) Value 1 0 Description Enables Receive mode for I2C Receive is Idle Bit 2 – PEN Stop Condition Enable bit (Master mode only)(2) © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 574 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Value 1 0 Description Initiates Stop condition on SDAx and SCLx pins; automatically cleared by hardware Stop condition is Idle Bit 1 – RSEN Repeated Start Condition Enable bit (Master mode only)(2) Value 1 0 Description Initiates Repeated Start condition on SDAx and SCLx pins; automatically cleared by hardware Repeated Start condition is Idle Bit 0 – SEN Start Condition Enable bit (Master mode only)(2) Value 1 0 Description Initiates Start condition on SDAx and SCLx pins; automatically cleared by hardware Start condition is Idle Note:  1. The value that will be transmitted when the user initiates an Acknowledge sequence at the end of a receive. 2. If the I2C module is active, these bits may not be set (no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled). © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 575 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.9.4 SSPxCON3 Name:  SSPxCON3 Address:  0x192,0x19C MSSP Control Register 3 Bit Access Reset 7 6 5 4 3 2 1 0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN R/HS/HC R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bit 7 – ACKTIM Acknowledge Time Status bit Unused in Master mode. Value x 1 0 Mode SPI or I2C Master I2C Slave and AHEN = 1 or DHEN = 1 I2C Slave Description This bit is not used Eighth falling edge of SCL has occurred and the ACK/ NACK state is active ACK/NACK state is not active. Transitions low on ninth rising edge of SCL. Bit 6 – PCIE Stop Condition Interrupt Enable bit(1) Value x 1 0 Mode SPI or SSPM = 1111 or 0111 SSPM ≠ 1111 and SSPM ≠ 0111 SSPM ≠ 1111 and SSPM ≠ 0111 Description Don't care Enable interrupt on detection of Stop condition Stop detection interrupts are disabled Bit 5 – SCIE Start Condition Interrupt Enable bit Value x 1 0 Mode SPI or SSPM = 1111 or 0111 SSPM ≠ 1111 and SSPM ≠ 0111 SSPM ≠ 1111 and SSPM ≠ 0111 Description Don't care Enable interrupt on detection of Start condition Start detection interrupts are disabled Bit 4 – BOEN Buffer Overwrite Enable bit(2) Value 1 0 1 Mode SPI SPI I2C 0 I2C Description SSPxBUF is updated every time a new data byte is available, ignoring the BF bit If a new byte is receive with BF set then SSPOV is set and SSPxBUF is not updated SSPxBUF is updated every time a new data byte is available, ignoring the SSPOV effect on updating the buffer SSPxBUF is only updated when SSPOV is clear Bit 3 – SDAHT SDA Hold Time Selection bit © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 576 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module Value x 1 0 Mode SPI I2C I2C Description Not used in SPI mode Minimum of 300ns hold time on SDA after the falling edge of SCL Minimum of 100ns hold time on SDA after the falling edge of SCL Bit 2 – SBCDE Slave Mode Bus Collision Detect Enable bit Unused in Master mode. Value x 1 0 Mode SPI or I2C Master I2C Slave I2C Slave Description Don't care Collision detection is enabled Collision detection is not enabled Bit 1 – AHEN Address Hold Enable bit Value x 1 0 Mode Description 2 SPI or I C Master Don't care I2C Slave Address hold is enabled. As a result CKP is cleared after the eighth falling SCL edge of an address byte reception. Software must set the CKP bit to resume operation. I2C Slave Address hold is not enabled Bit 0 – DHEN Data Hold Enable bit Value x 1 0 Mode Description SPI or I2C Master Don't care I2C Slave Data hold is enabled. As a result CKP is cleared after the eighth falling SCL edge of a data byte reception. Software must set the CKP bit to resume operation. I2C Slave Data hold is not enabled Note:  1. This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled. 2. For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPxBUF. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 577 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.9.5 SSPxBUF Name:  SSPxBUF Address:  0x18C,0x196 MSSP Data Buffer Register Bit 7 6 5 4 3 2 1 0 BUF[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W x x x x x x x x Bits 7:0 – BUF[7:0] MSSP Input and Output Data Buffer bits © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 578 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.9.6 SSPxADD Name:  SSPxADD Address:  0x18D,0x197 MSSP Baud Rate Divider and Address Register Bit 7 6 5 4 3 2 1 0 ADD[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – ADD[7:0] • SPI and I2C Master: Baud rate divider • I2C Slave: Address bits Value Mode 3 to SPI and I2C Master 255 2,4,6,8 I2C 10-bit Slave MS Address n I2C 10-bit Slave LS Address 2*(1 to I2C 7-bit Slave 127) © 2018 Microchip Technology Inc. Description Baud rate divider. SCK/SCL pin clock period = ((n + 1) *4)/FOSC. Values less than 3 are not valid. Bits 7-3 and Bit 0 are not used and are don't care. Bits 2:1 are bits 9:8 of the 10-bit Slave Most Significant Address Bits 7:0 of 10-Bit Slave Least Significant Address Bit 0 is not used and is don't care. Bits 7:1 are the 7-bit Slave Address Datasheet Preliminary DS40002038B-page 579 PIC16(L)F18455/56 (MSSP) Master Synchronous Serial Port Module 35.9.7 SSPxMSK Name:  SSPxMSK Address:  0x18E,0x198 MSSP Address Mask Register Bit 7 6 5 4 3 2 1 MSK[6:0] Access Reset 0 MSK0 R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 7:1 – MSK[6:0] Mask bits Value 1 0 Mode Description I2C Slave The received address bit n is compared to SSPxADD bit n to detect I2C address match I2C Slave The received address bit n is not used to detect I2C address match Bit 0 – MSK0 Mask bit for I2C 10-bit Slave mode Value 1 0 x Mode Description I2C 10-bit Slave The received address bit 0 is compared to SSPxADD bit 0 to detect I2C address match 2 I C 10-bit Slave The received address bit 0 is not used to detect I2C address match SPI or I2C 7-bit Don't care © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 580 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 36. (EUSART) Enhanced Universal Synchronous Asynchronous Receiver Transmitter The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. The EUSART, also known as a Serial Communications Interface (SCI), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. Full-Duplex mode is useful for communications with peripheral systems, such as CRT terminals and personal computers. Half-Duplex Synchronous mode is intended for communications with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs or other microcontrollers. These devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. The EUSART module includes the following capabilities: • • • • • • • • • • • Full-duplex asynchronous transmit and receive Two-character input buffer One-character output buffer Programmable 8-bit or 9-bit character length Address detection in 9-bit mode Input buffer overrun error detection Received character framing error detection Half-duplex synchronous master Half-duplex synchronous slave Programmable clock polarity in Synchronous modes Sleep operation The EUSART module implements the following additional features, making it ideally suited for use in Local Interconnect Network (LIN) bus systems: • • • Automatic detection and calibration of the baud rate Wake-up on Break reception 13-bit Break character transmit Block diagrams of the EUSART transmitter and receiver are shown in Figure 36-1 and Figure 36-2. The operation of the EUSART module consists of six registers: • • • • • • Transmit Status and Control (36.6.2 TXxSTA) Receive Status and Control (36.6.1 RCxSTA) Baud Rate Control (36.6.3 BAUDxCON) Baud Rate Value (36.6.4 SPxBRG) Receive Data Register (36.6.5 RCxREG) Transmit Data Register (36.6.6 TXxREG) The RXx/DTx and TXx/CKx input pins are selected with the RXxPPS and TXxPPS registers, respectively. TXx, CKx, and DTx output pins are selected with each pin’s RxyPPS register. Since the RX input is coupled with the DT output in Synchronous mode, it is the user’s responsibility to select the same pin for both of these functions when operating in Synchronous mode. The EUSART control logic will control the data direction drivers automatically. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 581 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Figure 36-1. EUSART Transmit Block Diagram Rev. 10-000 113C 2/15/201 7 Data bu s TXIE 8 Inte rrupt TXREG register SYNC CSRC TXIF 8 RxyPP S(1) TXEN CKx Pi n PPS 1 MSb LSb (8) 0 0 RXx/DTx Pin Pin Buffer and Control PPS Transmit Shift Register (TSR) CKPPS (2) TX_out Bau d Rate Gene rato r TRMT FOSC ÷n TX9 n BRG16 +1 SPB RG H SPB RG L Multiplier x4 x16 x64 SYNC 1 x 0 0 0 BRGH x 1 1 0 0 BRG16 x 1 0 1 0 TX9D 0 TXx/CKx Pi n PPS 1 RxyPP S(2) SYNC CSRC Not e 1: In S ynchro nous mod e, the DT output an d RX inpu t PPS selectio ns should en able th e same pin. 2: In Master S yn chr onous mo de the TX output an d CK inpu t PPS selections shou ld e nable the sa me pin. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 582 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Figure 36-2. EUSART Receive Block Diagram Rev. 10-000 114B 2/15/201 7 CRE N OERR RXPPS (1) RSR Register MSb RXx/DTx pin Pin Buffer and Control PPS RCIDL SPE N Data Recove ry Stop (8) 7 LSb 1 0 Start SYNC CSRC PPS RX9 1 CKx Pi n 0 CKPPS (2) Bau d Rate Gene rato r FOSC ÷n FERR RX9D RCREG Register FIFO 8 BRG16 +1 SPB RG H SPB RG L Multiplier x4 x16 x64 SYNC 1 x 0 0 0 BRGH x 1 1 0 0 BRG16 x 1 0 1 0 n Data B us RCxIF RCxIE Inte rrupt Not e 1: In S ynchro nous mod e, the DT output an d RX inpu t PPS selectio ns should en able th e same pin. 2: In Master S yn chr onous mo de the TX output an d CK inpu t PPS selections shou ld e nable the sa me pin. 36.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH Mark state which represents a ‘1’ data bit, and a VOL Space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. An NRZ transmission port idles in the Mark state. Each character transmission consists of one Start bit followed by eight or nine data bits and is always terminated by one or more Stop bits. The Start bit is always a space and the Stop bits are always marks. The most common data format is eight bits. Each transmitted bit persists for a period of 1/(Baud Rate). An on-chip dedicated 8-bit/16-bit Baud Rate Generator is used to derive standard baud rate frequencies from the system oscillator. See Table 36-2 for examples of baud rate configurations. The EUSART transmits and receives the LSb first. The EUSART’s transmitter and receiver are functionally independent, but share the same data format and baud rate. Parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 36.1.1 EUSART Asynchronous Transmitter The Figure 36-1 is a simplified representation of the transmitter. The heart of the transmitter is the serial Transmit Shift Register (TSR), which is not directly accessible by software. The TSR obtains its data from the transmit buffer, which is the TXxREG register. 36.1.1.1 Enabling the Transmitter The EUSART transmitter is enabled for asynchronous operations by configuring the following three control bits: © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 583 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... • TXEN = 1 (enables the transmitter circuitry of the EUSART) • SYNC = 0 (configures the EUSART for asynchronous operation) • SPEN = 1 (enables the EUSART and automatically enables the output drivers for the RxyPPS selected as the TXx/CKx output) All other EUSART control bits are assumed to be in their default state. If the TXx/CKx pin is shared with an analog peripheral, the analog I/O function must be disabled by clearing the corresponding ANSEL bit. Important:  The TXxIF Transmitter Interrupt flag is set when the TXEN enable bit is set and the TSR is idle. 36.1.1.2 Transmitting Data A transmission is initiated by writing a character to the TXxREG register. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR register. If the TSR still contains all or part of a previous character, the new character data is held in the TXxREG until the Stop bit of the previous character has been transmitted. The pending character in the TXxREG is then transferred to the TSR in one TCY immediately following the Stop bit transmission. The transmission of the Start bit, data bits and Stop bit sequence commences immediately following the transfer of the data to the TSR from the TXxREG. 36.1.1.3 Transmit Data Polarity The polarity of the transmit data can be controlled with the SCKP bit of the BAUDxCON register. The default state of this bit is ‘0’ which selects high true transmit idle and data bits. Setting the SCKP bit to ‘1’ will invert the transmit data resulting in low true idle and data bits. The SCKP bit controls transmit data polarity in Asynchronous mode only. In Synchronous mode, the SCKP bit has a different function. See the 36.3.1.2 Clock Polarity section for more detail. 36.1.1.4 Transmit Interrupt Flag The TXxIF interrupt flag bit of the PIRx register is set whenever the EUSART transmitter is enabled and no character is being held for transmission in the TXxREG. In other words, the TXxIF bit is only clear when the TSR is busy with a character and a new character has been queued for transmission in the TXxREG. The TXxIF flag bit is not cleared immediately upon writing TXxREG. TXxIF becomes valid in the second instruction cycle following the write execution. Polling TXxIF immediately following the TXxREG write will return invalid results. The TXxIF bit is read-only, it cannot be set or cleared by software. The TXxIF interrupt can be enabled by setting the TXxIE interrupt enable bit of the PIEx register. However, the TXxIF flag bit will be set whenever the TXxREG is empty, regardless of the state of TXxIE enable bit. To use interrupts when transmitting data, set the TXxIE bit only when there is more data to send. Clear the TXxIE interrupt enable bit upon writing the last character of the transmission to the TXxREG. 36.1.1.5 TSR Status The TRMT bit of the TXxSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXxREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 584 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Important:  The TSR register is not mapped in data memory, so it is not available to the user. 36.1.1.6 Transmitting 9-Bit Characters The EUSART supports 9-bit character transmissions. When the TX9 bit of the TXxSTA register is set, the EUSART will shift nine bits out for each character transmitted. The TX9D bit of the TXxSTA register is the ninth, and Most Significant data bit. When transmitting 9-bit data, the TX9D data bit must be written before writing the eight Least Significant bits into the TXxREG. All nine bits of data will be transferred to the TSR shift register immediately after the TXxREG is written. A special 9-bit Address mode is available for use with multiple receivers. See the 36.1.2.7 Address Detection section for more information on the Address mode. 36.1.1.7 Asynchronous Transmission Setup 1. Initialize the SPxBRGH, SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see 36.2 EUSART Baud Rate Generator (BRG)). 2. Select the transmit output pin by writing the appropriate value to the RxyPPS register. 3. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 4. If 9-bit transmission is desired, set the TX9 control bit. A set ninth data bit will indicate that the eight Least Significant data bits are an address when the receiver is set for address detection. 5. Set SCKP bit if inverted transmit is desired. 6. Enable the transmission by setting the TXEN control bit. This will cause the TXxIF interrupt bit to be set. 7. If interrupts are desired, set the TXxIE interrupt enable bit of the PIEx register 8. An interrupt will occur immediately provided that the GIE and PEIE bits of the INTCON register are also set. 9. If 9-bit transmission is selected, the ninth bit should be loaded into the TX9D data bit. 10. Load 8-bit data into the TXxREG register. This will start the transmission. Figure 36-3. Asynchronous Transmission Rev. 10-000 115A 2/7/201 7 Word 1 Write to TXxREG BRG Output (Shift Clock) TXx/CKx pin TXxIF bit (Transmit Buffer Reg Empty Flag) TRMT bit (Transmit Shift Reg Empty Flag) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 585 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Figure 36-4. Asynchronous Transmission (Back-to-Back) Word 1 Rev. 10-000 116A 2/7/201 7 Word 2 Write to TXxREG BRG Output (Shift Clock) TXx/CKx pin TXxIF bit (Transmit Buffer Reg Empty Flag) TRMT bit (Transmit Shift Reg Empty Flag) 36.1.2 Start bit bit 0 bit 1 bit 7/8 Word 1 Stop bit Start bit bit 0 Word 2 1 TCY EUSART Asynchronous Receiver The Asynchronous mode is typically used in RS-232 systems. A simplified representation of the receiver is shown in the Figure 36-2. The data is received on the RXx/DTx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate. When all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character First-In-First-Out (FIFO) memory. The FIFO buffering allows reception of two complete characters and the start of a third character before software must start servicing the EUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCxREG register. 36.1.2.1 Enabling the Receiver The EUSART receiver is enabled for asynchronous operation by configuring the following three control bits: • CREN = 1 (enables the receiver circuitry of the EUSART) • SYNC = 0 (configures the EUSART for asynchronous operation) • SPEN = 1 (enables the EUSART) All other EUSART control bits are assumed to be in their default state. The user must set the RXxPPS register to select the RXx/DTx I/O pin and set the corresponding TRIS bit to configure the pin as an input. Important:  If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. 36.1.2.2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero. If it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the Start bit. If the Start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. The bit is then sampled by a majority detect circuit and the resulting ‘0’ or ‘1’ is shifted into the RSR. This repeats until all data bits have been sampled and shifted into the RSR. One final bit time is measured and the level sampled. This is the Stop bit, which is always a ‘1’. If the data © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 586 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... recovery circuit samples a ‘0’ in the Stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. See the 36.1.2.4 Receive Framing Error section for more information on framing errors. Immediately after all data bits and the Stop bit have been received, the character in the RSR is transferred to the EUSART receive FIFO and the RCxIF interrupt flag bit of the PIRx register is set. The top character in the FIFO is transferred out of the FIFO by reading the RCxREG register. Important:  If the receive FIFO is overrun, no additional characters will be received until the overrun condition is cleared. See the 36.1.2.5 Receive Overrun Error section for more information. 36.1.2.3 Receive Interrupts The RCxIF interrupt flag bit of the PIRx register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCxIF interrupt flag bit is read-only, it cannot be set or cleared by software. RCxIF interrupts are enabled by setting all of the following bits: • • • RCxIE, Interrupt Enable bit of the PIEx register PEIE, Peripheral Interrupt Enable bit of the INTCON register GIE, Global Interrupt Enable bit of the INTCON register The RCxIF interrupt flag bit will be set when there is an unread character in the FIFO, regardless of the state of interrupt enable bits. 36.1.2.4 Receive Framing Error Each character in the receive FIFO buffer has a corresponding framing error Status bit. A framing error indicates that a Stop bit was not seen at the expected time. The framing error status is accessed via the FERR bit of the RCxSTA register. The FERR bit represents the status of the top unread character in the receive FIFO. Therefore, the FERR bit must be read before reading the RCxREG. The FERR bit is read-only and only applies to the top unread character in the receive FIFO. A framing error (FERR = 1) does not preclude reception of additional characters. It is not necessary to clear the FERR bit. Reading the next character from the FIFO buffer will advance the FIFO to the next character and the next corresponding framing error. The FERR bit can be forced clear by clearing the SPEN bit of the RCxSTA register which resets the EUSART. Clearing the CREN bit of the RCxSTA register does not affect the FERR bit. A framing error by itself does not generate an interrupt. Important:  If all receive characters in the receive FIFO have framing errors, repeated reads of the RCxREG will not clear the FERR bit. 36.1.2.5 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before the FIFO is accessed. When this happens the OERR bit of the RCxSTA register is set. The characters already in the FIFO buffer can be read but no additional characters will be received until the error is cleared. The error must be cleared by either clearing the CREN bit of the RCxSTA register or by resetting the EUSART by clearing the SPEN bit of the RCxSTA register. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 587 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 36.1.2.6 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth and Most Significant data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. 36.1.2.7 Address Detection A special Address Detection mode is available for use when multiple receivers share the same transmission line, such as in RS-485 systems. Address detection is enabled by setting the ADDEN bit of the RCxSTA register. Address detection requires 9-bit character reception. When address detection is enabled, only characters with the ninth data bit set will be transferred to the receive FIFO buffer, thereby setting the RCxIF interrupt bit. All other characters will be ignored. Upon receiving an address character, user software determines if the address matches its own. Upon address match, user software must disable address detection by clearing the ADDEN bit before the next Stop bit occurs. When user software detects the end of the message, determined by the message protocol used, software places the receiver back into the Address Detection mode by setting the ADDEN bit. 36.1.2.8 Asynchronous Reception Setup 1. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see the 36.2 EUSART Baud Rate Generator (BRG) section). 2. Set the RXxPPS register to select the RXx/DTx input pin. 3. Clear the ANSEL bit for the RXx pin (if applicable). 4. Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. 5. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. 6. If 9-bit reception is desired, set the RX9 bit. 7. Enable reception by setting the CREN bit. 8. The RCxIF interrupt flag bit will be set when a character is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE interrupt enable bit was also set. 9. Read the RCxSTA register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 10. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. 11. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 36.1.2.9 9-Bit Address Detection Mode Setup This mode would typically be used in RS-485 systems. To set up an Asynchronous Reception with Address Detect Enable follow these steps: 1. 2. 3. 4. Initialize the SPxBRGH:SPxBRGL register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see the 36.2 EUSART Baud Rate Generator (BRG) section). Set the RXxPPS register to select the RXx input pin. Clear the ANSEL bit for the RXx pin (if applicable). Enable the serial port by setting the SPEN bit. The SYNC bit must be clear for asynchronous operation. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 588 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 5. 6. 7. 8. 9. 10. 11. 12. 13. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. Enable 9-bit reception by setting the RX9 bit. Enable address detection by setting the ADDEN bit. Enable reception by setting the CREN bit. The RCxIF interrupt flag bit will be set when a character with the ninth bit set is transferred from the RSR to the receive buffer. An interrupt will be generated if the RCxIE interrupt enable bit is also set. Read the RCxSTA register to get the error flags. The ninth data bit will always be set. Get the received eight Least Significant data bits from the receive buffer by reading the RCxREG register. Software determines if this is the device’s address. If an overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and generate interrupts. Figure 36-5. Asynchronous Reception Rev. 10-000 117A 2/8/201 7 RXx/DTx pin Start bit bit 0 Rcv Shift Reg Rcv Buffer Reg Word 1 bit 7/8 Stop bit Start bit bit 0 Word 2 bit 7/8 Stop bit Word 1 RCxREG Start bit bit 0 Word 3 bit 7/8 Stop bit Word 2 RCxREG RCIDL Read RCxREG RCxIF (Interrupt flag) OERR Flag CREN (software clear) Note: This timing diagram shows three bytes appearing on the RXx input. The OERR flag is set because the RCxREG is not read before the third word is received. 36.1.3 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (INTOSC). However, the INTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. The first (preferred) method uses the OSCTUNE register to adjust the INTOSC output. Adjusting the value in the OSCTUNE register allows for fine resolution changes to the system clock source. The other method adjusts the value in the Baud Rate Generator. This can be done automatically with the Auto-Baud Detect feature (see 36.2.1 Auto-Baud Detect). There may not be fine enough resolution when adjusting the Baud Rate Generator to compensate for a gradual change in the peripheral clock frequency. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 589 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 36.2 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDxCON register selects 16-bit mode. The SPxBRGH, SPxBRGL register pair determines the period of the free running baud rate timer. In Asynchronous mode the multiplier of the baud rate period is determined by both the BRGH bit of the TXxSTA register and the BRG16 bit of the BAUDxCON register. In Synchronous mode, the BRGH bit is ignored. Table 36-1 contains the formulas for determining the baud rate. Equation 36-1 provides a sample calculation for determining the baud rate and baud rate error. Typical baud rates and error values for various asynchronous modes have been computed and are shown in Table 36-2. It may be advantageous to use the high baud rate (BRGH = 1), or the 16-bit BRG (BRG16 = 1) to reduce the baud rate error. The 16-bit BRG mode is used to achieve slow baud rates for fast oscillator frequencies. The BRGH bit is used to achieve very high baud rates. Writing a new value to the SPxBRGH, SPxBRGL register pair causes the BRG timer to be reset (or cleared). This ensures that the BRG does not wait for a timer overflow before outputting the new baud rate. If the system clock is changed during an active receive operation, a receive error or data loss may result. To avoid this problem, check the status of the RCIDL bit to make sure that the receive operation is idle before changing the system clock. Equation 36-1. Calculating Baud Rate Error For a device with Fosc of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG: ��������������� = Solving for SPxBRG: ������ = ������ = ���� 64 × ������ + 1 ���� −1 64 × ��������������� 16000000 −1 64 × 9600 ������ = 25.042 ≃ 25 ������������������ = 16000000 64 × 25 + 1 ������������������ = 9615 ����� = ����� = ������������������ − ��������������� ��������������� 9615 − 9600 9600 ����� = 0.16 % © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 590 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Table 36-1. Baud Rate Formulas Configuration Bits BRG/EUSART Mode Baud Rate Formula 0 8-bit/Asynchronous FOSC/[64 (n+1)] 0 1 8-bit/Asynchronous 0 1 0 16-bit/Asynchronous 0 1 1 16-bit/Asynchronous 1 0 x 8-bit/Synchronous 1 1 x 16-bit/Synchronous SYNC BRG16 BRGH 0 0 0 FOSC/[16 (n+1)] FOSC/[4 (n+1)] Note: x = Don’t care, n = value of SPxBRGH:SPxBRGL register pair. Table 36-2. Sample Baud Rates for Asynchronous Modes SYNC = 0, BRGH = 0, BRG16 = 0 FOSC = 32.000 MHz FOSC = 20.000 MHz FOSC = 18.432 MHz FOSC = 11.0592 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Error value Rate Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — 1221 1.73 255 1200 0.00 239 1200 0.00 143 2400 2404 0.16 207 2404 0.16 129 2400 0.00 119 2400 0.00 71 9600 9615 0.16 51 9470 -1.36 32 9600 0.00 29 9600 0.00 17 10417 10417 0.00 47 10417 0.00 29 10286 -1.26 27 10165 -2.42 16 19.2k 19.23k 0.16 25 19.53k 1.73 15 19.20k 0.00 14 19.20k 0.00 8 57.6k 55.55k -3.55 3 — — — 57.60k 0.00 7 57.60k 0.00 2 115.2k — — — — — — — — — — — — SYNC = 0, BRGH = 0, BRG16 = 0 Fosc = 8.000 MHz Fosc = 4.000 MHz Fosc = 3.6864 MHz Fosc = 1.000 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Error value Rate Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) (decimal) 300 — — — 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 — — — 9600 9615 0.16 12 — — — 9600 0.00 5 — — — © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 591 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 10417 10417 0.00 11 10417 0.00 5 19.2k — — — — — — 57.6k — — — — — — 115.2k — — — — — — — — — — — — 19.20k 0.00 2 — — — 57.60k 0.00 0 — — — — — — — — — SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE Fosc = 32.000 MHz Actual Rate Fosc = 20.000 MHz % SPBRG Error value (decimal) Actual Rate Fosc = 18.432 MHz Fosc = 11.0592 MHz % SPBRG Actual % SPBRG Actual % SPBRG Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) 300 — — — — — — — — — — — — 1200 — — — — — — — — — — — — 2400 — — — — — — — — — — — — 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.82k -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.64k 2.12 16 113.64k -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 1, BRG16 = 0 Fosc = 8.000 MHz Fosc = 4.000 MHz Fosc = 3.6864 MHz Fosc = 1.000 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Error value Rate Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) (decimal) 300 — — — — — — — — — 300 0.16 207 1200 — — — 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 — — — 57.6k 55556 -3.55 8 — — — 57.60k 0.00 3 — — — 115.2k — — — — 115.2k 0.00 1 — — — BAUD RATE — — 10417 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 Fosc = 32.000 MHz © 2018 Microchip Technology Inc. Fosc = 20.000 MHz Fosc = 18.432 MHz Datasheet Preliminary Fosc = 11.0592 MHz DS40002038B-page 592 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Actual % SPBRG Rate Error value (decimal) Actual Rate % SPBRG Actual % SPBRG Actual % SPBRG Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 -0.01 4166 300.0 0.00 3839 300.0 0.00 2303 1200 1200 -0.02 3332 1200 -0.03 1041 1200 0.00 959 1200 0.00 575 2400 2401 -0.04 832 2399 -0.03 520 2400 0.00 479 2400 0.00 287 9600 9615 0.16 207 9615 0.16 129 9600 0.00 119 9600 0.00 71 10417 10417 0.00 191 10417 0.00 119 10378 -0.37 110 10473 0.53 65 19.2k 19.23k 0.16 103 19.23k 0.16 64 19.20k 0.00 59 19.20k 0.00 35 57.6k 57.14k -0.79 34 56.818 -1.36 21 57.60k 0.00 19 57.60k 0.00 11 115.2k 117.6k 2.12 16 113.636 -1.36 10 115.2k 0.00 9 115.2k 0.00 5 SYNC = 0, BRGH = 0, BRG16 = 1 Fosc = 8.000 MHz Fosc = 4.000 MHz Fosc = 3.6864 MHz Fosc = 1.000 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Error value Rate Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 — — — 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 — — — 57.6k 8 — — — 57.60k 0.00 3 — — — — — — — 115.2k 0.00 1 — — — 115.2k 55556 -3.55 — — 10417 0.00 5 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 Fosc = 32.000 MHz Fosc = 20.000 MHz Fosc = 18.432 MHz Fosc = 11.0592 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Error value Rate Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 26666 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 9215 1200 1200 0.00 6666 1200 -0.01 4166 1200 0.00 3839 1200 0.00 2303 2400 2400 0.01 3332 2400 0.02 2082 2400 0.00 1919 2400 0.00 1151 9600 9604 0.04 832 9597 -0.03 520 9600 0.00 479 9600 0.00 287 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 593 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 10417 10417 0.00 767 10417 0.00 479 10425 0.08 441 10433 0.16 264 19.2k 19.18k -0.08 416 19.23k 0.16 259 19.20k 0.00 239 19.20k 0.00 143 57.6k 57.55k -0.08 138 57.47k -0.22 86 57.60k 0.00 79 57.60k 0.00 47 115.2k 115.9k 0.64 68 116.3k 0.94 42 115.2k 0.00 39 115.2k 0.00 23 SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 Fosc = 8.000 MHz Fosc = 4.000 MHz Fosc = 3.6864 MHz Fosc = 1.000 MHz BAUD RATE Actual % SPBRG Actual % SPBRG Actual % SPBRG Actual % SPBRG Rate Error value Rate Error value Rate Error value Rate Error value (decimal) (decimal) (decimal) (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 — — — 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 — — — 10417 10417 36.2.1 Auto-Baud Detect The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge. Setting the ABDEN bit of the BAUDxCON register starts the auto-baud calibration sequence. While the ABD sequence takes place, the EUSART state machine is held in Idle. On the first rising edge of the receive line, after the Start bit, the SPxBRG begins counting up using the BRG counter clock as shown in Figure 36-6. The fifth rising edge will occur on the RXx pin at the end of the eighth bit period. At that time, an accumulated value totaling the proper BRG period is left in the SPxBRGH, SPxBRGL register pair, the ABDEN bit is automatically cleared and the RCxIF interrupt flag is set. The value in the RCxREG needs to be read to clear the RCxIF interrupt. RCxREG content should be discarded. When calibrating for modes that do not use the SPxBRGH register the user can verify that the SPxBRGL register did not overflow by checking for 00h in the SPxBRGH register. The BRG auto-baud clock is determined by the BRG16 and BRGH bits as shown in Table 36-3. During ABD, both the SPxBRGH and SPxBRGL registers are used as a 16-bit counter, independent of the BRG16 bit setting. While calibrating the baud rate period, the SPxBRGH and SPxBRGL registers are clocked at 1/8th the BRG base clock rate. The resulting byte measurement is the average bit time when clocked at full speed. Note:  © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 594 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 1. 2. 3. If the WUE bit is set with the ABDEN bit, auto-baud detection will occur on the byte following the Break character (see 36.2.3 Auto-Wake-up on Break). It is up to the user to determine that the incoming character baud rate is within the range of the selected BRG clock source. Some combinations of oscillator frequency and EUSART baud rates are not possible. During the auto-baud process, the auto-baud counter starts counting at one. Upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the SPxBRGH:SPxBRGL register pair. Table 36-3. BRG Counter Clock Rates BRG16 BRGH BRG Base Clock BRG ABD Clock 1 1 FOSC/4 FOSC/32 1 0 FOSC/16 FOSC/128 0 1 FOSC/16 FOSC/128 0 0 FOSC/64 FOSC/512 Note:  During the ABD sequence, SPxBRGL and SPxBRGH registers are both used as a 16-bit counter, independent of the BRG16 setting. Figure 36-6. Automatic Baud Rate Calibration Rev. 10-000 120A 2/13/201 7 BRG Value XXXXh 0000h 001Ch Edge #1 RXx/DTx pin Edge #2 Edge #3 Edge #4 Edge #5 start bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 BRG Clock ABDEN Auto cleared Set by user RCxIF bit (Interrupt Flag) Read RCxREG SPxBRGH:L 36.2.2 XXXXh 001Ch Auto-Baud Overflow During the course of automatic baud detection, the ABDOVF bit of the BAUDxCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RXx pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPxBRGH:SPxBRGL register pair. After the ABDOVF bit has been set, the counter continues to count until the fifth rising edge is detected on the RXx pin. Upon detecting the fifth RX edge, the hardware will set the RCxIF interrupt flag and clear the ABDEN bit of the BAUDxCON register. The RCxIF flag can be subsequently cleared by reading the RCxREG register. The ABDOVF flag of the BAUDxCON register can be cleared by software directly. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 595 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... To terminate the auto-baud process before the RCxIF flag is set, clear the ABDEN bit then clear the ABDOVF bit of the BAUDxCON register. The ABDOVF bit will remain set if the ABDEN bit is not cleared first. 36.2.3 Auto-Wake-up on Break During Sleep mode, all clocks to the EUSART are suspended. Because of this, the Baud Rate Generator is inactive and a proper character reception cannot be performed. The Auto-Wake-up feature allows the controller to wake-up due to activity on the RX/DT line. This feature is available only in Asynchronous mode. The Auto-Wake-up feature is enabled by setting the WUE bit of the BAUDxCON register. Once set, the normal receive sequence on RX/DT is disabled, and the EUSART remains in an Idle state, monitoring for a wake-up event independent of the CPU mode. A wake-up event consists of a high-to-low transition on the RX/DT line. (This coincides with the start of a Sync Break or a wake-up signal character for the LIN protocol.) The EUSART module generates an RCxIF interrupt coincident with the wake-up event. The interrupt is generated synchronously to the Q clocks in normal CPU operating modes as shown in Figure 36-7, and asynchronously if the device is in Sleep mode as shown in Figure 36-8. The interrupt condition is cleared by reading the RCxREG register. The WUE bit is automatically cleared by the low-to-high transition on the RX line at the end of the Break. This signals to the user that the Break event is over. At this point, the EUSART module is in Idle mode waiting to receive the next character. 36.2.3.1 Special Considerations Break Character To avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. When the wake-up is enabled the function works independent of the low time on the data stream. If the WUE bit is set and a valid non-zero character is received, the low time from the Start bit to the first rising edge will be interpreted as the wake-up event. The remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. Therefore, the initial character in the transmission must be all ‘0’s. This must be ten or more bit times, 13bit times recommended for LIN bus, or any number of bit times for standard RS-232 devices. Oscillator Start-up Time Oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., LP, XT or HS/PLL mode). The Sync Break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the EUSART. WUE Bit The wake-up event causes a receive interrupt by setting the RCxIF bit. The WUE bit is cleared in hardware by a rising edge on RX/DT. The interrupt condition is then cleared in software by reading the RCxREG register and discarding its contents. To ensure that no actual data is lost, check the RCIDL bit to verify that a receive operation is not in process before setting the WUE bit. If a receive operation is not occurring, the WUE bit may then be set just prior to entering the Sleep mode. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 596 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Figure 36-7. Auto-Wake-up Bit (WUE) Timing During Normal Operation Rev. 10-000 326A 2/13/201 7 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 FOSC WUE bit Bit set by user Auto cleared RXx/DTx line RCxIF Cleared due to user read of RCxREG Note 1: The EUSART remains in idle while the WUE bit is set. Figure 36-8. Auto-Wake-up Bit (WUE) Timings During Sleep Rev. 10-000 327A 2/13/201 7 q1 q2 q3 q4 q1 q2 q3 q4 q2 q1 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 FOSC WUE bit Bit set by user Auto cleared RXx/DTx line RCxIF Cleared due to user read of RCxREG Sleep command executed Sleep ends Note 1: The EUSART remains in idle while the WUE bit is set. 36.2.4 Break Character Sequence The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXxSTA register. The Break character transmission is then initiated by a write to the TXxREG. The value of data written to TXxREG will be ignored and all ‘0’s will be transmitted. The SENDB bit is automatically reset by hardware after the corresponding Stop bit is sent. This allows the user to preload the transmit FIFO with the next transmit byte following the Break character (typically, the Sync character in the LIN specification). The TRMT bit of the TXxSTA register indicates when the transmit operation is active or idle, just as it does during normal transmission. See Figure 36-9 for more detail. 36.2.4.1 Break and Sync Transmit Sequence The following sequence will start a message frame header made up of a Break, followed by an auto-baud Sync byte. This sequence is typical of a LIN bus master. 1. 2. 3. Configure the EUSART for the desired mode. Set the TXEN and SENDB bits to enable the Break sequence. Load the TXxREG with a dummy character to initiate transmission (the value is ignored). © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 597 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 4. 5. Write ‘55h’ to TXxREG to load the Sync character into the transmit FIFO buffer. After the Break has been sent, the SENDB bit is reset by hardware and the Sync character is then transmitted. When the TXxREG becomes empty, as indicated by the TXxIF, the next data byte can be written to TXxREG. 36.2.5 Receiving a Break Character The EUSART module can receive a Break character in two ways. The first method to detect a Break character uses the FERR bit of the RCxSTA register and the received data as indicated by RCxREG. The Baud Rate Generator is assumed to have been initialized to the expected baud rate. A Break character has been received when all three of the following conditions are true: • • • RCxIF bit is set FERR bit is set RCxREG = 00h The second method uses the Auto-Wake-up feature described in 36.2.3 Auto-Wake-up on Break. By enabling this feature, the EUSART will sample the next two transitions on RX/DT, cause an RCxIF interrupt, and receive the next data byte followed by another interrupt. Note that following a Break character, the user will typically want to enable the Auto-Baud Detect feature. For both methods, the user can set the ABDEN bit of the BAUDxCON register before placing the EUSART in Sleep mode. Figure 36-9. Send Break Character Sequence Dummy Write Rev. 10-000 118A 2/13/201 7 Write to TXxREG BRG Output (Shift Clock) TXx/CKx pin Start bit bit 0 36.3 bit 11 Stop bit Break TXxIF bit (Transmit Buffer Reg Empty Flag) TRMT bit (Transmit Shift Reg Empty Flag) SENDB (send break control bit) bit 1 SENDB sampled here Auto cleared EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 598 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... There are two signal lines in Synchronous mode: a bidirectional data line and a clock line. Slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and transmit shift registers. Since the data line is bidirectional, synchronous operation is half-duplex only. Halfduplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. The EUSART can operate as either a master or slave device. Start and Stop bits are not used in synchronous transmissions. 36.3.1 Synchronous Master Mode The following bits are used to configure the EUSART for synchronous master operation: • SYNC = 1 (configures the EUSART for synchronous operation) • CSRC = 1 (configures the EUSART as the master) • SREN = 0 (for transmit); SREN = 1 (recommended setting to receive 1 byte) • CREN = 0 (for transmit); CREN = 1 (to receive continuously) • SPEN = 1 (enables the EUSART) Important:  Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. 36.3.1.1 Master Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a master transmits the clock on the TX/CK line. The TXx/CKx pin output driver is automatically enabled when the EUSART is configured for synchronous transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One clock cycle is generated for each data bit. Only as many clock cycles are generated as there are data bits. 36.3.1.2 Clock Polarity A clock polarity option is provided for Microwire compatibility. Clock polarity is selected with the SCKP bit of the BAUDxCON register. Setting the SCKP bit sets the clock Idle state as high. When the SCKP bit is set, the data changes on the falling edge of each clock. Clearing the SCKP bit sets the Idle state as low. When the SCKP bit is cleared, the data changes on the rising edge of each clock. 36.3.1.3 Synchronous Master Transmission Data is transferred out of the device on the RXx/DTx pin. The RXx/DTx and TXx/CKx pin output drivers are automatically enabled when the EUSART is configured for synchronous master transmit operation. A transmission is initiated by writing a character to the TXxREG register. If the TSR still contains all or part of a previous character the new character data is held in the TXxREG until the last bit of the previous character has been transmitted. If this is the first character, or the previous character has been completely flushed from the TSR, the data in the TXxREG is immediately transferred to the TSR. The transmission of the character commences immediately following the transfer of the data to the TSR from the TXxREG. Each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. Note:  The TSR register is not mapped in data memory, so it is not available to the user. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 599 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 36.3.1.4 Synchronous Master Transmission Setup 1. Initialize the SPxBRGH, SPxBRGL register pair and the BRG16 bit to achieve the desired baud rate (see 36.2 EUSART Baud Rate Generator (BRG)). 2. Select the transmit output pin by writing the appropriate values to the RxyPPS register and RXxPPS register. Both selections should enable the same pin. 3. Select the clock output pin by writing the appropriate values to the RxyPPS register and CKxPPS register. Both selections should enable the same pin. 4. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 5. Disable Receive mode by clearing bits SREN and CREN. 6. Enable Transmit mode by setting the TXEN bit. 7. If 9-bit transmission is desired, set the TX9 bit. 8. If interrupts are desired, set the TXxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. 9. If 9-bit transmission is selected, the ninth bit should be loaded in the TX9D bit. 10. Start transmission by loading data to the TXxREG register. Figure 36-10. Synchronous Transmission Rev. 10-000 115A 2/7/201 7 Word 1 Write to TXxREG BRG Output (Shift Clock) TXx/CKx pin TXxIF bit (Transmit Buffer Reg Empty Flag) TRMT bit (Transmit Shift Reg Empty Flag) Start bit bit 0 bit 1 bit 7/8 Stop bit Word 1 1 TCY 36.3.1.5 Synchronous Master Reception Data is received at the RXx/DTx pin. The RXx/DTx pin output driver is automatically disabled when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCxSTA register) or the Continuous Receive Enable bit (CREN of the RCxSTA register). When SREN is set and CREN is clear, only as many clock cycles are generated as there are data bits in a single character. The SREN bit is automatically cleared at the completion of one character. When CREN is set, clocks are continuously generated until CREN is cleared. If CREN is cleared in the middle of a character the CK clock stops immediately and the partial character is discarded. If SREN and CREN are both set, then SREN is cleared at the completion of the first character and CREN takes precedence. To initiate reception, set either SREN or CREN. Data is sampled at the RXx/DTx pin on the trailing edge of the TX/CK clock pin and is shifted into the Receive Shift Register (RSR). When a complete character is received into the RSR, the RCxIF bit is set and the character is automatically transferred to the two character receive FIFO. The Least Significant eight bits of the top character in the receive FIFO are available in RCxREG. The RCxIF bit remains set as long as there are unread characters in the receive FIFO. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 600 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Note:  If the RX/DT function is on an analog pin, the corresponding ANSEL bit must be cleared for the receiver to function. 36.3.1.6 Receive Overrun Error The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCxREG is read to access the FIFO. When this happens the OERR bit of the RCxSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read, however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear then the error is cleared by reading RCxREG. If the overrun occurred when the CREN bit is set then the error condition is cleared by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. 36.3.1.7 Receiving 9-Bit Characters The EUSART supports 9-bit character reception. When the RX9 bit of the RCxSTA register is set the EUSART will shift nine bits into the RSR for each character received. The RX9D bit of the RCxSTA register is the ninth, and Most Significant, data bit of the top unread character in the receive FIFO. When reading 9-bit data from the receive FIFO buffer, the RX9D data bit must be read before reading the eight Least Significant bits from the RCxREG. 36.3.1.8 Synchronous Master Reception Setup 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Initialize the SPxBRGH:SPxBRGL register pair and set or clear the BRG16 bit, as required, to achieve the desired baud rate. Select the receive input pin by writing the appropriate values to the RxyPPS register and RXxPPS register. Both selections should enable the same pin. Select the clock output pin by writing the appropriate values to the RxyPPS register and CKxPPS register. Both selections should enable the same pin. Clear the ANSEL bit for the RXx pin (if applicable). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Ensure bits CREN and SREN are clear. If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. If 9-bit reception is desired, set bit RX9. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. Interrupt flag bit RCxIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCxIE was set. Read the RCxSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCxREG register. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 601 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Figure 36-11. Synchronous Reception (Master Mode, SREN) Rev. 10-000 121A 2/13/201 7 RXx/DTx pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TXx/CKx pin SCKP = 0 TXx/CKx pin SCKP = 1 Write to SREN SREN bit CREN bit ‘0’ ‘0’ RCxIF (Interrupt) Read RCxREG 36.3.2 Synchronous Slave Mode The following bits are used to configure the EUSART for synchronous slave operation: • SYNC = 1 (configures the EUSART for synchronous operation.) • CSRC = 0 (configures the EUSART as a slave) • SREN = 0 (for transmit); SREN = 1 (for single byte receive) • CREN = 0 (for transmit); CREN = 1 (recommended setting for continuous receive) • SPEN = 1 (enables the EUSART) Important:  Clearing the SREN and CREN bits of the RCxSTA register ensures that the device is in the Transmit mode, otherwise the device will be configured to receive. 36.3.2.1 Slave Clock Synchronous data transfers use a separate clock line, which is synchronous with the data. A device configured as a slave receives the clock on the TX/CK line. The TXx/CKx pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. Serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. One data bit is transferred for each clock cycle. Only as many clock cycles should be received as there are data bits. Important:  If the device is configured as a slave and the TX/CK function is on an analog pin, the corresponding ANSEL bit must be cleared. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 602 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 36.3.2.2 EUSART Synchronous Slave Transmit The operation of the Synchronous Master and Slave modes are identical (see 36.3.1.3 Synchronous Master Transmission), except in the case of the Sleep mode. If two words are written to the TXxREG and then the SLEEP instruction is executed, the following will occur: 1. 2. 3. The first character will immediately transfer to the TSR register and transmit. The second word will remain in the TXxREG register. The TXxIF bit will not be set. 4. After the first character has been shifted out of TSR, the TXxREG register will transfer the second character to the TSR and the TXxIF bit will now be set. If the PEIE and TXxIE bits are set, the interrupt will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will call the Interrupt Service Routine. 5. 36.3.2.3 Synchronous Slave Transmission Setup 1. 2. Set the SYNC and SPEN bits and clear the CSRC bit. Select the transmit output pin by writing the appropriate values to the RxyPPS register and RXxPPS register. Both selections should enable the same pin. 3. Select the clock input pin by writing the appropriate value to the CKxPPS register. 4. Clear the ANSEL bit for the CKx pin (if applicable). 5. Clear the CREN and SREN bits. 6. If interrupts are desired, set the TXxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. 7. If 9-bit transmission is desired, set the TX9 bit. 8. Enable transmission by setting the TXEN bit. 9. If 9-bit transmission is selected, insert the Most Significant bit into the TX9D bit. 10. Prepare for transmission by writing the Least Significant eight bits to the TXxREG register. The word will be transmitted in response to the Master clocks at the CKx pin. 36.3.2.4 EUSART Synchronous Slave Reception The operation of the Synchronous Master and Slave modes is identical (see 36.3.1.5 Synchronous Master Reception), with the following exceptions: • • • Sleep CREN bit is always set, therefore the receiver is never idle SREN bit, which is a “don’t care” in Slave mode A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep. Once the word is received, the RSR register will transfer the data to the RCxREG register. If the RCxIE enable bit is set, the interrupt generated will wake the device from Sleep and execute the next instruction. If the GIE bit is also set, the program will branch to the interrupt vector. 36.3.2.5 Synchronous Slave Reception Setup: 1. 2. 3. 4. 5. Set the SYNC and SPEN bits and clear the CSRC bit. Select the receive input pin by writing the appropriate value to the RXxPPS register. Select the clock input pin by writing the appropriate values to the CKxPPS register. Clear the ANSEL bit for both the TXx/CKx and RXx/DTx pins (if applicable). If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 603 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 6. 7. 8. If 9-bit reception is desired, set the RX9 bit. Set the CREN bit to enable reception. The RCxIF bit will be set when reception is complete. An interrupt will be generated if the RCxIE bit was set. 9. If 9-bit mode is enabled, retrieve the Most Significant bit from the RX9D bit of the RCxSTA register. 10. Retrieve the eight Least Significant bits from the receive FIFO by reading the RCxREG register. 11. If an overrun error occurs, clear the error by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit which resets the EUSART. 36.4 EUSART Operation During Sleep The EUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the Transmit or Receive Shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the Transmit and Receive Shift registers. 36.4.1 Synchronous Receive During Sleep To receive during Sleep, all the following conditions must be met before entering Sleep mode: • • • RCxSTA and TXxSTA Control registers must be configured for Synchronous Slave Reception (see 36.3.2.5 Synchronous Slave Reception Setup:). If interrupts are desired, set the RCxIE bit of the PIEx register and the GIE and PEIE bits of the INTCON register. The RCxIF interrupt flag must be cleared by reading RCxREG to unload any pending characters in the receive buffer. Upon entering Sleep mode, the device will be ready to accept data and clocks on the RXx/DTx and TXx/CKx pins, respectively. When the data word has been completely clocked in by the external device, the RCxIF interrupt flag bit of the PIRx register will be set. Thereby, waking the processor from Sleep. Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit of the INTCON register is also set, then the Interrupt Service Routine at address 004h will be called. 36.4.2 Synchronous Transmit During Sleep To transmit during Sleep, all the following conditions must be met before entering Sleep mode: • • • • The RCxSTA and TXxSTA Control registers must be configured for synchronous slave transmission (see 36.3.2.3 Synchronous Slave Transmission Setup). The TXxIF interrupt flag must be cleared by writing the output data to the TXxREG, thereby filling the TSR and transmit buffer. Interrupt enable bits TXxIE of the PIEx register and PEIE of the INTCON register must set. If interrupts are desired, set the GIEx bit of the INTCON register. Upon entering Sleep mode, the device will be ready to accept clocks on the TXx/CKx pin and transmit data on the RXx/DTx pin. When the data word in the TSR has been completely clocked out by the external device, the pending byte in the TXxREG will transfer to the TSR and the TXxIF flag will be set. Thereby, waking the processor from Sleep. At this point, the TXxREG is available to accept another character for transmission. Writing TXxREG will clear the TXxIF flag. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 604 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Upon waking from Sleep, the instruction following the SLEEP instruction will be executed. If the Global Interrupt Enable (GIE) bit is also set then the Interrupt Service Routine at address 0004h will be called. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 605 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 36.5 Register Summary - EUSART Address Name Bit Pos. 0x0119 RC1REG 7:0 0x011A TX1REG 7:0 TXREG[7:0] 7:0 SPBRGL[7:0] RCREG[7:0] 0x011B SP1BRG 0x011D RC1STA 7:0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0x011E TX1STA 7:0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0x011F BAUD1CON 7:0 ABDOVF RCIDL SCKP BRG16 WUE ABDEN RX9D 15:8 SPBRGH[7:0] 0x0120 ... Reserved 0x0A18 0x0A19 RC2REG 7:0 RCREG[7:0] 0x0A1A TX2REG 7:0 TXREG[7:0] 0x0A1B SP2BRG 0x0A1D RC2STA 7:0 0x0A1E TX2STA 7:0 0x0A1F BAUD2CON 7:0 36.6 7:0 SPBRGL[7:0] 15:8 SPBRGH[7:0] SPEN RX9 SREN CREN ADDEN FERR OERR CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D ABDOVF RCIDL SCKP BRG16 WUE ABDEN Register Definitions: EUSART Control © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 606 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 36.6.1 RCxSTA Name:  RCxSTA Address:  0x11D,0xA1D Receive Status and Control Register Bit Access Reset 7 6 5 4 3 2 1 0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D R/W R/W R/W R/W R/W RO R/HC R/HC 0 0 0 0 0 0 0 0 Bit 7 – SPEN Serial Port Enable bit Value 1 0 Description Serial port enabled Serial port disabled (held in Reset) Bit 6 – RX9 9-Bit Receive Enable bit Value 1 0 Description Selects 9-bit reception Selects 8-bit reception Bit 5 – SREN Single Receive Enable bit Controls reception. This bit is cleared by hardware when reception is complete Value 1 0 X Condition SYNC = 1 AND CSRC = 1 SYNC = 1 AND CSRC = 1 SYNC = 0 OR CSRC = 0 Description Start single receive Single receive is complete Don't care Bit 4 – CREN Continuous Receive Enable bit Value 1 0 1 0 Condition Description SYNC = 1 Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) SYNC = 1 Disables continuous receive SYNC = 0 Enables receiver SYNC = 0 Disables receiver Bit 3 – ADDEN Address Detect Enable bit Value 1 0 X Condition Description SYNC = 0 AND RX9 = 1 The receive buffer is loaded and the interrupt occurs only when the ninth received bit is set SYNC = 0 AND RX9 = 1 All bytes are received and interrupt always occurs. Ninth bit can be used as parity bit RX9 = 0 OR SYNC = 1 Don't care © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 607 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Bit 2 – FERR Framing Error bit Value 1 0 Description Unread byte in 36.6.5 RCxREG has a framing error Unread byte in 36.6.5 RCxREG does not have a framing error Bit 1 – OERR Overrun Error bit Value 1 0 Description Overrun error (can be cleared by clearing either SPEN or CREN bit) No overrun error Bit 0 – RX9D Ninth bit of Received Data This can be address/data bit or a parity bit which is determined by user firmware. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 608 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 36.6.2 TXxSTA Name:  TXxSTA Address:  0x11E,0xA1E Transmit Status and Control Register Bit Access Reset 7 6 5 4 3 2 1 0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D R/W R/W R/W R/W R/W R/W RO R/W 0 0 0 0 0 0 1 0 Bit 7 – CSRC Clock Source Select bit Value 1 0 X Condition SYNC= 1 SYNC= 1 SYNC= 0 Description Master mode (clock generated internally from BRG) Slave mode (clock from external source) Don't care Bit 6 – TX9 9-bit Transmit Enable bit Value 1 0 Description Selects 9-bit transmission Selects 8-bit transmission Bit 5 – TXEN Transmit Enable bit Enables transmitter(1) Value 1 0 Description Transmit enabled Transmit disabled Bit 4 – SYNC EUSART Mode Select bit Value 1 0 Description Synchronous mode Asynchronous mode Bit 3 – SENDB Send Break Character bit Value 1 0 X Condition SYNC= 0 SYNC= 0 SYNC= 1 Description Send Sync Break on next transmission (cleared by hardware upon completion) Sync Break transmission disabled or completed Don't care Bit 2 – BRGH High Baud Rate Select bit © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 609 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Value 1 0 X Condition SYNC= 0 SYNC= 0 SYNC= 1 Description High speed, if BRG16 = 1, baud rate is baudclk/4; else baudclk/16 Low speed Don't care Bit 1 – TRMT Transmit Shift Register (TSR) Status bit Value 1 0 Description TSR is empty TSR is not empty Bit 0 – TX9D Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note:  1. SREN and CREN bits override TXEN in Sync mode. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 610 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 36.6.3 BAUDxCON Name:  BAUDxCON Address:  0x11F,0xA1F Baud Rate Control Register Bit Access Reset 7 6 4 3 1 0 ABDOVF RCIDL 5 SCKP BRG16 2 WUE ABDEN RO RO RW RW RW RW 0 0 0 0 0 0 Bit 7 – ABDOVF Auto-Baud Detect Overflow bit Value 1 0 X Condition SYNC= 0 SYNC= 0 SYNC= 1 Description Auto-baud timer overflowed Auto-baud timer did not overflow Don't care Bit 6 – RCIDL Receive Idle Flag bit Value 1 0 X Condition SYNC= 0 SYNC= 0 SYNC= 1 Description Receiver is Idle Start bit has been received and the receiver is receiving Don't care Bit 4 – SCKP Synchronous Clock Polarity Select bit Value 1 0 1 0 Condition SYNC= 0 SYNC= 0 SYNC= 1 SYNC= 1 Description Idle state for transmit (TX) is a low level (transmit data inverted) Idle state for transmit (TX) is a high level (transmit data is non-inverted) Data is clocked on rising edge of the clock Data is clocked on falling edge of the clock Bit 3 – BRG16 16-bit Baud Rate Generator Select bit Value 1 0 Description 16-bit Baud Rate Generator is used 8-bit Baud Rate Generator is used Bit 1 – WUE Wake-up Enable bit Value 1 0 X Condition Description SYNC= 0 Receiver is waiting for a falling edge. Upon falling edge no character will be received and flag RCxIF will be set. WUE will automatically clear after RCxIF is set. SYNC= 0 Receiver is operating normally SYNC= 1 Don't care Bit 0 – ABDEN Auto-Baud Detect Enable bit © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 611 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... Value 1 0 X Condition SYNC= 0 SYNC= 0 SYNC= 1 Description Auto-Baud Detect mode is enabled (clears when auto-baud is complete) Auto-Baud Detect is complete or mode is disabled Don't care © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 612 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 36.6.4 SPxBRG Name:  SPxBRG Address:  0x11B,0xA1B Baud Rate Determination Register Bit 15 14 13 12 11 10 9 8 SPBRGH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 SPBRGL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 15:8 – SPBRGH[7:0] Baud Rate High Byte Register Bits 7:0 – SPBRGL[7:0] Baud Rate Low Byte Register © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 613 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 36.6.5 RCxREG Name:  RCxREG Address:  0x119,0xA19 Receive Data Register Bit 7 6 5 4 3 2 1 0 RCREG[7:0] Access Reset RO RO RO RO RO RO RO RO 0 0 0 0 0 0 0 0 Bits 7:0 – RCREG[7:0] Receive data © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 614 PIC16(L)F18455/56 (EUSART) Enhanced Universal Synchronous Asyn... 36.6.6 TXxREG Name:  TXxREG Address:  0x11A,0xA1A Transmit Data Register Bit 7 6 5 4 3 2 1 0 TXREG[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 7:0 – TXREG[7:0] Transmit Data © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 615 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37. (SMT) Signal Measurement Timer The SMT is a 24-bit counter with advanced clock and gating logic, which can be configured for measuring a variety of digital signal parameters such as pulse width, frequency and duty cycle, and the time difference between edges on two signals. Features of the SMT include: • 24-bit timer/counter • Two 24-bit measurement capture registers • One 24-bit period match register • Filename: Multi-mode operation, including relative timing measurement 10-000161E.vsd Title: Signal Measurement Timer v1 • Interrupt on period match and acquisition complete Last Edit: 10/12/2016 • First Multiple signal and window sources Used: clock, PIC18(L)F2x/4xK42 Notes: Below is the block diagram for the SMT module. Figure 37-1. Signal Measurement Timer Block Diagram Rev. 10-000161E 10/12/2016 Period Latch SMT_window SMT Clock Sync Circuit SMT_signal SMT Clock Sync Circuit Set SMTxPRAIF SMTxPR Control Logic Set SMTxIF Comparator Reset Enable CLKR 111 SOSC 110 MFINTOSC/16 101 MFINTOSC 100 LFINTOSC 011 HFINTOSC 010 FOSC 001 FOSC/4 000 SMTxTMR Window Latch 24-bit Buffer SMTxCPR 24-bit Buffer SMTxCPW Set SMTxPWAIF Prescaler CSEL 37.1 SMT Operation 37.1.1 Clock Source Selection The SMT clock source is selected by configuring the CSEL bits in the SMTxCLK register. The clock source can be prescaled using the PS bits of the SMTxCON0 register. The prescaled clock source is © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 616 PIC16(L)F18455/56 (SMT) Signal Measurement Timer used to clock both the counter and any synchronization logic used by the module. Refer the table below for possible clock source options. The polarity of the clock source can be selected using the CPOL bit in the SMTxCON0 register. Table 37-1. SMT Clock Source Selection 37.1.2 CSEL Clock Source 111 CLKREF output 110 SOSC 101 MFINTOSC (31.25kHz) 100 MFINTOSC (500kHz) 011 LFINTOSC 010 HFINTOSC 001 FOSC 000 FOSC/4 Signal and Window Source Selection The SMT signal and window sources are selected by configuring the SSEL bits in the SMTxSIG register and the WSEL bits in the SMTxWIN register. Refer the tables below for the possible selections. The polarity of the signal and window sources can be selected using the SPOL and WPOL bits in the SMTxCON0 register. Table 37-2. SMT Signal Selection SSEL SMT1 Signal Source SMT2 Signal Source 11111-11000 Reserved Reserved 10111 SMT2 overflow SMT1 overflow 10110 CCP5OUT CCP5OUT 10101 CLC4OUT CLC4OUT 10100 CLC3OUT CLC3OUT 10011 CLC2OUT CLC2OUT 10010 CLC1OUT CLC1OUT 10001 ZCDOUT ZCDOUT 10000 C2OUT C2OUT 01111 C1OUT C1OUT 01110 NCO1OUT NCO1OUT 01101 PWM7OUT PWM7OUT 01100 PWM6OUT PWM6OUT 01011 CCP4OUT CCP4OUT © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 617 PIC16(L)F18455/56 (SMT) Signal Measurement Timer SSEL SMT1 Signal Source SMT2 Signal Source 01010 CCP3OUT CCP3OUT 01001 CCP2OUT CCP2OUT 01000 CCP1OUT CCP1OUT 00111 TMR6 postscaled output TMR6 postscaled output 00110 TMR5 overflow TMR5 overflow 00101 TMR4 postscaled output TMR4 postscaled output 00100 TMR3 overflow TMR3 overflow 00011 TMR2 postscaled output TMR2 postscaled output 00010 TMR1 overflow TMR1 overflow 00001 TMR0 overflow TMR0 overflow 00000 Pin Selected by SMT1SIGPPS Pin Selected by SMT2SIGPPS Table 37-3. SMT Window Selection WSEL SMT1 Window Source SMT2 Window Source 11111-11001 Reserved Reserved 11000 CCP5OUT CCP5OUT 10111 NCO1OUT NCO1OUT 10110 SMT2_overflow SMT1_overflow 10101 CLKREFOUT CLKREFOUT 10100 CLC4OUT CLC4OUT 10011 CLC3OUT CLC3OUT 10010 CLC2OUT CLC2OUT 10001 CLC1OUT CLC1OUT 10000 ZCDOUT ZCDOUT 01111 C2OUT C2OUT 01110 C1OUT C1OUT 01101 PWM7OUT PWM7OUT 01100 PWM6OUT PWM6OUT 01011 CCP4OUT CCP4OUT 01010 CCP3OUT CCP3OUT 01001 CCP2OUT CCP2OUT 01000 CCP1OUT CCP1OUT © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 618 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37.1.3 WSEL SMT1 Window Source SMT2 Window Source 00111 TMR6_postscaled_out TMR6_postscaled_out 00110 TMR4_postscaled_out TMR4_postscaled_out 00101 TMR2_postscaled_out TMR2_postscaled_out 00100 TMR0_overflow TMR0_overflow 00011 SOSC SOSC 00010 MFINTOSC (31.25kHz) MFINTOSC (31.25kHz) 00001 LFINTOSC (31.25kHz) LFINTOSC (31.25kHz) 00000 Pin Selected by SMT1WINPPS Pin Selected by SMT1WINPPS Time Base The SMTxTMR is the 24-bit counter/timer used for measurement in each of the modes of the SMT. It can be reset to 0x000000 by setting the RST bit of the SMTxSTAT register. It can be written to and read by software. It is not guarded for atomic access, therefore reads and writes to the SMTxTMR should be made when the GO = 0. The counter can be prevented from a rollover using the STP bit in the SMTxCON0 register. When STP = 1, SMTxTMR will remain equal to SMTxPR. When STP = 0, SMTxTMR resets to 0x000000. 37.1.4 Capture Pulse Width and Period Registers The SMTxCPW and SMTxCPR registers are used to latch in the value of the SMTxTMR based on the mode of SMT operation. These registers can also be updated with the current value of the SMTxTMR value by setting the CPWUP and CPRUP bits of the SMTxSTAT register, respectively. 37.1.5 Status Information The SMT provides input status information for the user without requiring the need to deal with the polarity of the incoming signals. Go Status: Timer run status is determined by the TS bit of the SMTxSTAT register, and will be delayed in time by synchronizer delays in non-Counter modes. Signal Status:Signal status is determined by the AS bit of the SMTxSTAT register. This bit is used in all modes except Window Measure, Time of Flight and Capture modes, and is only valid when TS = 1, and will be delayed in time by synchronizer delays in non-Counter modes. Window Status: Window status is determined by the WS bit of the SMTxSTAT register. This bit is only used in Windowed Measure, Gated Counter and Gated Window Measure modes, and is only valid when TS = 1, and will be delayed in time by synchronizer delays in non-Counter modes. 37.1.6 Modes of Operation The modes of operation are mentioned in the table below. The following sections provide descriptions and examples of how the modes can be used. Note that all waveforms assume WPOL/SPOL/CPOL = 0. For all modes, the REPEAT bit controls whether the acquisition is repeated or single. When REPEAT = 0 (Single Acquisition mode), the timer will stop incrementing and the SMTxGO bit will be reset upon the completion of an acquisition. Otherwise, the timer will continue and allow for continued acquisitions to overwrite the previous ones until the timer is stopped in software. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 619 PIC16(L)F18455/56 (SMT) Signal Measurement Timer Table 37-4. Modes of Operation MODE Mode of operation Synchronous operation 0000 Timer Yes 0001 Gated Timer Yes 0010 Period and Duty Cycle Measurement Yes 0011 High and low time Measurement Yes 0100 Windowed Measurement Yes 0101 Gated Windowed Measurement Yes 0110 Time of Flight Measurement Yes 0111 Capture Yes 1000 Counter No 1001 Gated Counter No 1010 Windowed Counter No 1011-1111 Reserved - 37.1.6.1 Timer Mode Filename: 10-000174A.vsd Timer modeTIMER is the basic mode of operation where the SMTxTMR is used as a 24-bit timer. No data Title: MODE TIMING DIAGRAM Last Edit: 12/19/2013 acquisition takes place LECQ in this mode. The timer increments as long as the SMTxGO bit has been set First Used: PIC16(L)F1612/3 Notes: by software. No SMT window or SMT signal events affect the SMTxGO bit. Everything is synchronized to the SMT clock source. When the timer experiences a period match (SMTxTMR = SMTxPR), SMTxTMR is reset and the period match interrupt trips. See figure below. Figure 37-2. Timer Mode Timing Diagram Rev. 10-000 174A 12/19/201 3 SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxPR SMTxTMR 11 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 SMTxIF 37.1.6.2 Gated Timer Mode Gated Timer mode uses the signal input (SSEL) to control whether or not the SMTxTMR will increment. Upon a falling edge of the signal, the SMTxCPW register will update to the current value of the SMTxTMR. Example waveforms for both repeated and single acquisitions are provided in figures below. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 620 Filename: Title: Last Edit: First Used: Notes: 10-000176A.vsd GATED TIMER MODE REPEAT ACQUISITION TIMING DIAGRAM 12/19/2013 PIC16(L)F1612/3 LECQ PIC16(L)F18455/56 (SMT) Signal Measurement Timer Figure 37-3. Gated Timer Mode, Repeat Acquisition Timing Diagram Rev. 10-000 176A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync Filename: SMTxPR 10-000175A.vsd 0xFFFFFF Title: GATED TIMER MODE SINGLE ACQUISITION TIMING DIAGRAM Last Edit: SMTxTMR 12/19/2013 0 1 2 3 4 First Used: PIC16(L)F1612/3 LECQ Notes: SMTxCPW 5 6 7 5 7 SMTxPWAIF Figure 37-4. Gated Timer Mode, Single Acquisition Timing Diagram Rev. 10-000 175A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxPR SMTxTMR 0xFFFFFF 0 1 2 3 4 5 SMTxCPW 5 SMTxPWAIF 37.1.6.3 Period and Duty Cycle Measurement Mode In this mode, either the duty cycle or period (depending on polarity) of the input signal can be acquired relative to the SMT clock. The CPW register is updated on a falling edge of the signal, and the CPR register is updated on a rising edge of the signal, along with the SMTxTMR resetting to 0x000001. In addition, the SMTxGO bit is reset on a rising edge when the SMT is in single acquisition mode. See figures below. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 621 Filename: Title: Last Edit: First Used: Notes: 10-000177A.vsd PERIOD AND DUTY-CYCLE REPEAT ACQUISITION MODE TIMING DIAGRAM 12/19/2013 PIC16(L)F1612/3 LECQ PIC16(L)F18455/56 (SMT) Signal Measurement Timer Figure 37-5. Period and Duty-Cycle, Repeat Acquisition Mode Timing Diagram Rev. 10-000 177A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 6 7 8 Filename: SMTxCPW 10-000178A.vsd Title: PERIOD AND DUTY-CYCLE SINGLE ACQUISITION TIMING DIAGRAM Last Edit: SMTxCPR 12/19/2013 First Used: PIC16(L)F1612/3 LECQ Notes: SMTxPWAIF 9 10 11 1 2 3 4 5 5 2 11 SMTxPRAIF Figure 37-6. Period and Duty-Cycle, Single Acquisition Mode Timing Diagram Rev. 10-000 178A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 6 7 SMTxCPW 8 9 10 11 5 SMTxCPR 11 SMTxPWAIF SMTxPRAIF 37.1.6.4 High and Low Measurement Mode This mode measures the high and low pulse time of the signal relative to the SMT clock. It begins incrementing the SMTxTMR on a rising edge on the input signal, then updates the SMTxCPW register with the value and resets the SMTxTMR on a falling edge, starting to increment again. Upon observing another rising edge, it updates the SMTxCPR register with its current value and once again resets the SMTxTMR value and begins incrementing again. See the figures below. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 622 Filename: Title: Last Edit: First Used: Notes: 10-000180A.vsd HIGH AND LOW MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM 12/19/2013 PIC16(L)F1612/3 LECQ PIC16(L)F18455/56 (SMT) Signal Measurement Timer Figure 37-7. High and Low Measurement Mode, Repeat Acquisition Timing Diagram Rev. 10-000 180A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 1 2 3 Filename: SMTxCPW 10-000179A.vsd Title: HIGH AND LOW MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM Last Edit: SMTxCPR 12/19/2013 First Used: PIC16(L)F1612/3 LECQ Notes: SMTxPWAIF 4 5 6 1 2 1 2 3 5 2 6 SMTxPRAIF Figure 37-8. High and Low Measurement Mode, Single Acquisition Timing Diagram Rev. 10-000 179A 12/19/201 3 SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 1 2 SMTxCPW 3 4 5 6 5 SMTxCPR 6 SMTxPWAIF SMTxPRAIF 37.1.6.5 Windowed Measurement Mode This mode measures the duration of the window input (WSEL) to the SMT. It begins incrementing the timer on a rising edge of the window input and updates the SMTxCPR register with the value of the timer and resets the timer on a second rising edge. See figures below. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 623 Filename: Title: Last Edit: First Used: Notes: 10-000182A.vsd WINDOWED MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM 12/19/2013 PIC16(L)F1612/3 LECQ PIC16(L)F18455/56 (SMT) Signal Measurement Timer Figure 37-9. Windowed Measurement Mode, Repeat Acquisition Timing Diagram Rev. 10-000 182A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync Filename: 10-000181A.vsd Title: WINDOWED MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM Last Edit: SMTxTMR 12/19/2013 0 1 2 3 4 5 6 7 8 9 10 11 12 1 First Used: PIC16(L)F1612/3 LECQ Notes: SMTxCPR 2 3 4 5 6 7 8 1 12 2 3 4 8 SMTxPRAIF Figure 37-10. Windowed Measurement Mode, Single Acquisition Timing Diagram Rev. 10-000 181A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 SMTxCPR 12 SMTxPRAIF 37.1.6.6 Gated Window Measurement Mode This mode measures the duty cycle of the signal input over a known input window. It does so by incrementing the timer on each pulse of the clock signal while the signal input is high, updating the SMTxCPR register and resetting the timer on every rising edge of the window input after the first. See figures below. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 624 Filename: Title: Last Edit: First Used: Notes: 10-000184A.vsd GATED WINDOWED MEASURE MODE REPEAT ACQUISITION TIMING DIAGRAM 12/19/2013 PIC16(L)F1612/3 LECQ PIC16(L)F18455/56 (SMT) Signal Measurement Timer Figure 37-11. Gated Windowed Measurement Mode, Repeat Acquisition Timing Diagram Rev. 10-000 184A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync10-000183A.vsd Filename: Title: GATED WINDOWED MEASURE MODE SINGLE ACQUISITION TIMING DIAGRAM Last Edit:SMTxTMR 12/19/2013 0 1 2 3 4 5 6 First Used: PIC16(L)F1612/3 LECQ Notes: SMTxCPR 0 1 2 3 6 0 3 SMTxPRAIF Figure 37-12. Gated Windowed Measurement Mode, Single Acquisition Timing Diagram Rev. 10-000 183A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 SMTxCPR 6 6 SMTxPRAIF 37.1.6.7 Time of Flight Measurement Mode This mode measures the time interval between a rising edge on the window input and a rising edge on the signal input, beginning to increment the timer upon observing a rising edge on the window input, while updating the SMTxCPR register and resetting the timer upon observing a rising edge on the signal input. In the event of two rising edges of the window signal without a signal rising edge, it will update the SMTxCPW register with the current value of the timer and reset the timer value. See figures below. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 625 Title: Last Edit: First Used: Notes: TIME OF FLIGHT MODE REPEAT ACQUISITION TIMING DIAGRAM 4/22/2016 PIC16(L)F1612/3 LECQ PIC16(L)F18455/56 (SMT) Signal Measurement Timer Figure 37-13. Time of Flight Mode, Repeat Acquisition Timing Diagram Rev. 10-000186A 4/22/2016 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 Filename: 10-000185A.vsd Title: SMTxCPW TIME OF FLIGHT MODE SINGLE ACQUISITION TIMING DIAGRAM Last Edit: 4/26/2016 First Used: SMTxCPR PIC16(L)F1612/3 LECQ Notes: 1 2 3 4 5 6 7 8 2 9 10 11 12 13 1 13 4 SMTxPWAIF SMTxPRAIF Figure 37-14. Time of Flight Mode, Single Acquisition Timing Diagram Rev. 10-000185A 4/26/2016 SMTxWIN SMTxWIN_sync SMTx_signal SMTx_signalsync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 SMTxCPW SMTxCPR 4 SMTxPWAIF SMTxPRAIF 37.1.6.8 Capture Mode This mode captures the timer value based on a rising or falling edge on the window input and triggers an interrupt. This mimics the capture feature of a CCP module. The timer begins incrementing upon the SMTxGO bit being set, and updates the value of the SMTxCPR register on each rising edge of window signal, and updates the value of the SMTxCPW register on each falling edge of the window signal. The timer is not reset by any hardware conditions in this mode and must be reset by software, if desired. See figures below. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 626 Filename: Title: Last Edit: First Used: Notes: 10-000188A.vsd CAPTURE MODE REPEAT ACQUISITION TIMING DIAGRAM 12/19/2013 PIC16(L)F1612/3 LECQ PIC16(L)F18455/56 (SMT) Signal Measurement Timer Figure 37-15. Capture Mode, Repeat Acquisition Timing Diagram Rev. 10-000 188A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SMTxCPW 3 Filename: 10-000187A.vsd Title: CAPTURE MODE SINGLE ACQUISITION TIMING DIAGRAM 2 Last Edit: SMTxCPR 12/19/2013 First Used: PIC16(L)F1612/3 LECQ Notes: SMTxPWAIF 19 18 32 31 SMTxPRAIF Figure 37-16. Capture Mode, Single Acquisition Timing Diagram Rev. 10-000 187A 12/19/201 3 SMTxWIN SMTxWIN_sync SMTx Clock SMTxEN SMTxGO SMTxGO_sync SMTxTMR 0 1 2 3 SMTxCPW SMTxCPR 3 2 SMTxPWAIF SMTxPRAIF 37.1.6.9 Counter Mode This mode increments the timer on each pulse of the signal input. This mode is asynchronous to the SMT clock and uses the signal input as a time source. The SMTxCPW register will be updated with the current SMTxTMR value on the falling edge of the window input. See figure below. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 627 Title: Last Edit: First Used: Notes: COUNTER MODE TIMING DIAGRAM 4/12/2016 PIC16(L)F1612/3 LECQ PIC16(L)F18455/56 (SMT) Signal Measurement Timer Figure 37-17. Counter Mode Timing Diagram Rev. 10-000189A 4/12/2016 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 8 SMTxCPW Filename: Title: Last Edit: First 37.1.6.10Used: Gated Notes: 27 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 12 25 10-000190A.vsd GATED COUNTER MODE REPEAT ACQUISITION TIMING DIAGRAM 12/18/2013 PIC16(L)F1612/3 Counter ModeLECQ This mode counts pulses on the signal input, gated by the window input. It begins incrementing the timer upon seeing a rising edge of the window input and updates the SMTxCPW register upon a falling edge on the window input. See figures below. Figure 37-18. Gated Counter Mode, Repeat Acquisition Timing Diagram Rev. 10-000190A 12/18/2013 SMTxWIN SMTx_signal SMTxEN Filename: SMTxGO10-000191A.vsd Title: GATED COUNTER MODE SINGLE ACQUISITION TIMING DIAGRAM Last Edit: SMTxTMR12/18/2013 0 1 2 3 4 5 6 First Used: PIC16(L)F1612/3 LECQ Notes: SMTxCPW 7 8 9 10 11 12 8 13 13 SMTxPWAIF Figure 37-19. Gated Counter Mode, Single Acquisition Timing Diagram Rev. 10-000191A 12/18/2013 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 SMTxCPW 8 8 SMTxPWAIF 37.1.6.11 Windowed Counter Mode This mode counts pulses on the signal input, within a window dictated by the window input. It begins counting upon seeing a rising edge of the window input, updates the SMTxCPW register on a falling edge © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 628 Filename: Title: Last Edit: First Used: Notes: PIC16(L)F18455/56 10-000192A.vsd WINDOWED COUNTER MODE REPEAT ACQUISITION TIMING DIAGRAM 12/18/2013 PIC16(L)F1612/3 LECQ (SMT) Signal Measurement Timer of the window input, and updates the SMTxCPR register on each rising edge of the window input after the first. See figures below. Figure 37-20. Windowed Counter Mode, Repeat Acquisition Timing Diagram Rev. 10-000192A 12/18/2013 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 Filename: SMTxCPW 10-000193A.vsd Title: WINDOWED COUNTER MODE SINGLE ACQUISITION TIMING DIAGRAM Last Edit: SMTxCPR 12/18/2013 First Used: PIC16(L)F1612/3 LECQ Notes: SMTxPWAIF 2 3 4 9 5 5 16 SMTxPRAIF Figure 37-21. Windowed Counter Mode, Single Acquisition Timing Diagram Rev. 10-000193A 12/18/2013 SMTxWIN SMTx_signal SMTxEN SMTxGO SMTxTMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SMTxCPW 9 16 SMTxCPR SMTxPWAIF SMTxPRAIF 37.1.7 Interrupts The SMT has three interrupts: • Pulse Width Acquisition Interrupt (SMTxPWAIF): Interrupt triggers when SMTxCPW is updated • Period Acquisition Interrupt (SMTxPRAIF): Interrupt triggers when SMTxCPR is updated • Counter Period Match Interrupt (SMTxIF): Interrupt triggers when SMTxTMR equals SMTxPR Each of the above interrupts can be enabled/disabled using the corresponding bits in the PIEx register. 37.1.8 Operation During Sleep The SMT can operate during SLEEP, IDLE, and DOZE modes; provided that the clock and signal sources continue to function. System clock sources, like FOSC and FOSC/4, are disabled in Sleep. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 629 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37.2 Address 0x048C 0x048F 0x0492 Register Summary - SMT Control Name SMT1TMR SMT1CPR SMT1CPW Bit Pos. 7:0 TMRL[7:0] 15:8 TMRH[7:0] 23:16 TMRU[7:0] 7:0 CPRL[7:0] 15:8 CPRH[7:0] 23:16 CPRU[7:0] 7:0 CPWL[7:0] 15:8 CPWH[7:0] 23:16 CPWU[7:0] 7:0 PRL[7:0] 15:8 PRH[7:0] 0x0495 SMT1PR 0x0498 SMT1CON0 7:0 EN 0x0499 SMT1CON1 7:0 GO REPEAT 0x049A SMT1STAT 7:0 CPRUP CPWUP 0x049B SMT1CLK 7:0 0x049C SMT1SIG 7:0 SSEL[4:0] 0x049D SMT1WIN 7:0 WSEL[4:0] 23:16 PRU[7:0] STP WPOL SPOL CPOL PS[1:0] MODE[3:0] RST TS WS AS CSEL[2:0] 0x049E ... Reserved 0x050B 0x050C 0x050F 0x0512 0x0515 SMT2TMR SMT2CPR SMT2CPW SMT2PR 7:0 TMRL[7:0] 15:8 TMRH[7:0] 23:16 TMRU[7:0] 7:0 CPRL[7:0] 15:8 CPRH[7:0] 23:16 CPRU[7:0] 7:0 CPWL[7:0] 15:8 CPWH[7:0] 23:16 CPWU[7:0] 7:0 PRL[7:0] 15:8 PRH[7:0] 23:16 PRU[7:0] 0x0518 SMT2CON0 7:0 EN 0x0519 SMT2CON1 7:0 GO REPEAT STP 0x051A SMT2STAT 7:0 CPRUP CPWUP WPOL SPOL CPOL RST TS 0x051B SMT2CLK 7:0 0x051C SMT2SIG 7:0 SSEL[4:0] 0x051D SMT2WIN 7:0 WSEL[4:0] 37.3 PS[1:0] MODE[3:0] WS AS CSEL[2:0] Register Definitions: SMT Control © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 630 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37.3.1 SMTxCON0 Name:  SMTxCON0 Address:  0x498,0x518 SMT Control Register 0 Bit 7 Access Reset 5 4 3 2 EN 6 STP WPOL SPOL CPOL 1 0 R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 PS[1:0] Bit 7 – EN SMT Enable Bit Value 1 0 Description SMT is enabled SMT is disabled; internal states are reset, clock requests are disabled Bit 5 – STP SMT Counter Halt Enable bit Value 1 0 Condition Description When SMTxTMR = SMTxPR Counter remains SMTxPR; period match interrupt occurs when clocked When SMTxTMR = SMTxPR Counter resets to 0x000000; period match interrupt occurs when clocked Bit 4 – WPOL SMTxWIN Input Polarity Control bit Value 1 0 Description Window signal is active-low/falling edge enabled Window signal is active-high/rising edge enabled Bit 3 – SPOL SMTxSIG Input Polarity Control bit Value 1 0 Description SMT Signal is active-low/falling edge enabled SMT Signal is active-high/rising edge enabled Bit 2 – CPOL SMT Clock Input Polarity Control bit Value 1 0 Description SMTxTMR increments on the falling edge of the selected clock signal SMTxTMR increments on the rising edge of the selected clock signal Bits 1:0 – PS[1:0] SMT Prescale Select bits Value 11 10 01 00 Description Prescaler = 1:8 Prescaler = 1:4 Prescaler = 1:2 Prescaler = 1:1 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 631 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37.3.2 SMTxCON1 Name:  SMTxCON1 Address:  0x499,0x519 SMT Control Register 1 Bit Access Reset 7 6 GO REPEAT 5 4 3 R/W R/W R/W 0 0 0 2 1 0 R/W R/W R/W 0 0 0 MODE[3:0] Bit 7 – GO  SMT GO Data Acquisition Bit Value 1 0 Description Incrementing, acquiring data is enabled Incrementing, acquiring data is disabled Bit 6 – REPEAT SMT Repeat Acquisition Enable Bit Value 1 0 Description Repeat Data Acquisition mode is enabled Single Acquisition mode is enabled Bits 3:0 – MODE[3:0] SMT Operation Mode Select bits Value 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Description Reserved Reserved Reserved Reserved Reserved Windowed counter Gated counter Counter Capture Time of flight Gated windowed measurement Windowed measurement High and low time measurement Period and Duty-Cycle Acquisition Gated Timer Timer © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 632 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37.3.3 SMTxSTAT Name:  SMTxSTAT Address:  0x49A,0x51A SMT Status Register Bit Access Reset 7 6 2 1 0 CPRUP CPWUP 5 RST 4 3 TS WS AS R/W/HC R/W/HC R/W RO RO RO 0 0 0 0 0 0 Bit 7 – CPRUP  SMT Manual Period Buffer Update bit Value 1 0 Description Request update to SMTxCPR registers SMTxCPR registers update is complete Bit 6 – CPWUP SMT Manual Pulse Width Buffer Update bit Value 1 0 Description Request update to SMTxCPW registers SMTxCPW registers update is complete Bit 4 – RST SMT Manual Timer Reset bit Value 1 0 Description Request Reset to SMTxTMR registers SMTxTMR registers update is complete Bit 2 – TS SMT GO Value Status bit Value 1 0 Description SMTxTMR is incrementing SMTxTMR is not incrementing Bit 1 – WS SMT Window Status bit Value 1 0 Description SMT window is open SMT window is closed Bit 0 – AS SMT Signal Value Status bit Value 1 0 Description SMT acquisition is in progress SMT acquisition is not in progress © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 633 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37.3.4 SMTxCLK Name:  SMTxCLK Address:  0x49B,0x51B SMT Clock Selection Register Bit 7 6 5 4 3 2 1 0 CSEL[2:0] Access Reset R/W R/W R/W 0 0 0 Bits 2:0 – CSEL[2:0] SMT Clock Selection bits Table 37-5. SMT Clock Source Selection CSEL Clock Source 111 CLKREF output 110 SOSC 101 MFINTOSC (31.25kHz) 100 MFINTOSC (500kHz) 011 LFINTOSC 010 HFINTOSC 001 FOSC 000 FOSC/4 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 634 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37.3.5 SMTxWIN Name:  SMTxWIN Address:  0x49D,0x51D SMT Window Input Select Register Bit 7 6 5 4 3 2 1 0 WSEL[4:0] Access R/W R/W R/W R/W R/W 0 0 0 0 0 Reset Bits 4:0 – WSEL[4:0] SMT Window Selection bits Table 37-6. SMT Window Selection WSEL SMT1 Window Source SMT2 Window Source 11111-11001 Reserved Reserved 11000 CCP5OUT CCP5OUT 10111 NCO1OUT NCO1OUT 10110 SMT2_overflow SMT1_overflow 10101 CLKREFOUT CLKREFOUT 10100 CLC4OUT CLC4OUT 10011 CLC3OUT CLC3OUT 10010 CLC2OUT CLC2OUT 10001 CLC1OUT CLC1OUT 10000 ZCDOUT ZCDOUT 01111 C2OUT C2OUT 01110 C1OUT C1OUT 01101 PWM7OUT PWM7OUT 01100 PWM6OUT PWM6OUT 01011 CCP4OUT CCP4OUT 01010 CCP3OUT CCP3OUT 01001 CCP2OUT CCP2OUT 01000 CCP1OUT CCP1OUT 00111 TMR6_postscaled_out TMR6_postscaled_out 00110 TMR4_postscaled_out TMR4_postscaled_out 00101 TMR2_postscaled_out TMR2_postscaled_out 00100 TMR0_overflow TMR0_overflow © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 635 PIC16(L)F18455/56 (SMT) Signal Measurement Timer WSEL SMT1 Window Source SMT2 Window Source 00011 SOSC SOSC 00010 MFINTOSC (31.25kHz) MFINTOSC (31.25kHz) 00001 LFINTOSC (31.25kHz) LFINTOSC (31.25kHz) 00000 Pin Selected by SMT1WINPPS Pin Selected by SMT1WINPPS © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 636 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37.3.6 SMTxSIG Name:  SMTxSIG Address:  0x49C,0x51C SMT Signal Selection bits Bit 7 6 5 4 3 2 1 0 SSEL[4:0] Access R/W R/W R/W R/W R/W 0 0 0 0 0 Reset Bits 4:0 – SSEL[4:0] SMT Signal Selection bits Table 37-7. SMT Signal Selection SSEL SMT1 Signal Source SMT2 Signal Source 11111-11000 Reserved Reserved 10111 SMT2 overflow SMT1 overflow 10110 CCP5OUT CCP5OUT 10101 CLC4OUT CLC4OUT 10100 CLC3OUT CLC3OUT 10011 CLC2OUT CLC2OUT 10010 CLC1OUT CLC1OUT 10001 ZCDOUT ZCDOUT 10000 C2OUT C2OUT 01111 C1OUT C1OUT 01110 NCO1OUT NCO1OUT 01101 PWM7OUT PWM7OUT 01100 PWM6OUT PWM6OUT 01011 CCP4OUT CCP4OUT 01010 CCP3OUT CCP3OUT 01001 CCP2OUT CCP2OUT 01000 CCP1OUT CCP1OUT 00111 TMR6 postscaled output TMR6 postscaled output 00110 TMR5 overflow TMR5 overflow 00101 TMR4 postscaled output TMR4 postscaled output 00100 TMR3 overflow TMR3 overflow 00011 TMR2 postscaled output TMR2 postscaled output © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 637 PIC16(L)F18455/56 (SMT) Signal Measurement Timer SSEL SMT1 Signal Source SMT2 Signal Source 00010 TMR1 overflow TMR1 overflow 00001 TMR0 overflow TMR0 overflow 00000 Pin Selected by SMT1SIGPPS Pin Selected by SMT2SIGPPS © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 638 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37.3.7 SMTxTMR Name:  SMTxTMR Address:  0x48C,0x50C SMT Timer Register Bit 23 22 21 20 19 18 17 16 TMRU[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 TMRH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 TMRL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Bits 23:16 – TMRU[7:0] Upper byte of the SMT timer register Bits 15:8 – TMRH[7:0] High byte of the SMT timer register Bits 7:0 – TMRL[7:0] Lower byte of the SMT timer register © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 639 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37.3.8 SMTxCPR Name:  SMTxCPR Address:  0x48F,0x50F SMT Captured Period Register Bit 23 22 21 20 19 18 17 16 CPRU[7:0] Access Reset Bit RO RO RO RO RO RO RO RO x x x x x x x x 15 14 13 12 11 10 9 8 CPRH[7:0] Access RO RO RO RO RO RO RO RO Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 CPRL[7:0] Access Reset RO RO RO RO RO RO RO RO x x x x x x x x Bits 23:16 – CPRU[7:0] Upper byte of SMT capture period register Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Bits 15:8 – CPRH[7:0] High byte of SMT capture period register Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Bits 7:0 – CPRL[7:0] Lower byte of SMT capture period register Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 640 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37.3.9 SMTxCPW Name:  SMTxCPW Address:  0x492,0x512 SMT Captured Pulse Width Register Bit 23 22 21 20 19 18 17 16 CPWU[7:0] Access Reset Bit RO RO RO RO RO RO RO RO x x x x x x x x 15 14 13 12 11 10 9 8 CPWH[7:0] Access RO RO RO RO RO RO RO RO Reset x x x x x x x x Bit 7 6 5 4 3 2 1 0 CPWL[7:0] Access Reset RO RO RO RO RO RO RO RO x x x x x x x x Bits 23:16 – CPWU[7:0] Upper Byte of the captured pulse width register Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Bits 15:8 – CPWH[7:0] High Byte of the captured pulse width register Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu Bits 7:0 – CPWL[7:0] Lower Byte of the captured pulse width register Reset States: POR/BOR = xxxxxxxx All Other Resets = uuuuuuuu © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 641 PIC16(L)F18455/56 (SMT) Signal Measurement Timer 37.3.10 SMTxPR Name:  SMTxPR Address:  0x495,0x515 SMT Period Register Bit 23 22 21 20 19 18 17 16 PRU[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 15 14 13 12 11 10 9 8 PRH[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 1 1 1 1 1 1 1 Bit 7 6 5 4 3 2 1 0 PRL[7:0] Access Reset R/W R/W R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 1 1 Bits 23:16 – PRU[7:0] Upper byte of the SMT period register Bits 15:8 – PRH[7:0] High byte of the SMT period register Bits 7:0 – PRL[7:0] Lower byte of the SMT period register © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 642 PIC16(L)F18455/56 Register Summary 38. Register Summary Address Name Bit Pos. 0x00 INDF0 7:0 INDF0[7:0] 0x01 INDF1 7:0 INDF1[7:0] 0x02 PCL 7:0 0x03 STATUS 7:0 0x04 FSR0 0x06 FSR1 0x08 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] Z DC C BSR[5:0] 0x09 WREG 7:0 0x0A PCLATH 7:0 WREG[7:0] 0x0B INTCON 7:0 GIE PEIE 0x0C PORTA 7:0 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 0x0D PORTB 7:0 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 0x0E PORTC 7:0 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 0x0F Reserved 0x10 PORTE PCLATH[6:0] INTEDG 7:0 RE3 0x11 Reserved 0x12 TRISA 7:0 TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 0x13 TRISB 7:0 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 0x14 TRISC 7:0 TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 0x15 ... Reserved 0x17 0x18 LATA 7:0 LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 0x19 LATB 7:0 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 0x1A LATC 7:0 LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 Z DC C 0x1B ... Reserved 0x7F 0x80 INDF0 7:0 INDF0[7:0] 0x81 INDF1 7:0 INDF1[7:0] 0x82 PCL 7:0 0x83 STATUS 7:0 0x84 FSR0 0x86 FSR1 0x88 BSR 7:0 0x89 WREG 7:0 0x8A PCLATH 7:0 0x8B INTCON 7:0 0x8C ADLTH 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE © 2018 Microchip Technology Inc. PEIE INTEDG LTHL[7:0] Datasheet Preliminary DS40002038B-page 643 PIC16(L)F18455/56 Register Summary Address Name 0x8E ADUTH 0x90 ADERR 0x92 ADSTPT 0x94 ADFLTR Bit Pos. 15:8 LTHH[7:0] 7:0 UTHL[7:0] 15:8 UTHH[7:0] 7:0 ADERRL[7:0] 15:8 ERRH[7:0] 7:0 STPTL[7:0] 15:8 STPTH[7:0] 7:0 FLTRL[7:0] 15:8 FLTRH[7:0] 7:0 ACCL[7:0] 15:8 ACCH[7:0] 0x96 ADACC 0x99 ADCNT 7:0 0x9A ADRPT 7:0 RPT[7:0] 7:0 PREVL[7:0] 15:8 PREVH[7:0] 23:16 0x9B ADPREV 0x9D ADRES 0x9F ADPCH ACCU[1:0] CNT[7:0] 7:0 RESL[7:0] 15:8 RESH[7:0] 7:0 PCH[5:0] 0xA0 ... Reserved 0xFF 0x0100 INDF0 7:0 INDF0[7:0] 0x0101 INDF1 7:0 INDF1[7:0] 0x0102 PCL 7:0 PCL[7:0] 0x0103 STATUS 7:0 0x0104 0x0106 FSR0 FSR1 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] BSR 7:0 0x0109 WREG 7:0 0x010A PCLATH 7:0 0x010B INTCON ADACQ 0x010E ADCAP PD FSRL[7:0] 0x0108 0x010C TO 7:0 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 7:0 ACQL[7:0] 15:8 ACQH[4:0] 7:0 CAP[4:0] 7:0 PREL[7:0] 0x010F ADPRE 0x0111 ADCON0 7:0 ON CONT 0x0112 ADCON1 7:0 PPOL IPEN 0x0113 ADCON2 7:0 PSIS 0x0114 ADCON3 7:0 0x0115 ADSTAT 7:0 0x0116 ADREF 7:0 0x0117 ADACT 7:0 15:8 PREH[4:0] OV © 2018 Microchip Technology Inc. UTHR CS FRM GO GPOL DSEN CRS[2:0] ACLR MD[2:0] CALC[2:0] SOI TMD[2:0] LTHR MATH STAT[2:0] NREF PREF[1:0] ACT[4:0] Datasheet Preliminary DS40002038B-page 644 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x0118 ADCLK 7:0 0x0119 RC1REG 7:0 RCREG[7:0] CS[5:0] 0x011A TX1REG 7:0 TXREG[7:0] 0x011B SP1BRG 0x011D RC1STA 7:0 SPEN RX9 SREN CREN ADDEN FERR OERR 0x011E TX1STA 7:0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0x011F BAUD1CON 7:0 ABDOVF RCIDL SCKP BRG16 WUE ABDEN DC C 7:0 SPBRGL[7:0] 15:8 SPBRGH[7:0] RX9D 0x0120 ... Reserved 0x017F 0x0180 INDF0 7:0 INDF0[7:0] 0x0181 INDF1 7:0 INDF1[7:0] 0x0182 PCL 7:0 PCL[7:0] 0x0183 STATUS 7:0 0x0184 FSR0 0x0186 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0188 BSR 7:0 0x0189 WREG 7:0 0x018A PCLATH 7:0 Z BSR[5:0] WREG[7:0] PCLATH[6:0] 0x018B INTCON 7:0 0x018C SSP1BUF 7:0 GIE PEIE BUF[7:0] INTEDG 0x018D SSP1ADD 7:0 ADD[7:0] 0x018E SSP1MSK 7:0 0x018F SSP1STAT 7:0 SMP 0x0190 SSP1CON1 7:0 0x0191 SSP1CON2 7:0 0x0192 SSP1CON3 7:0 MSK[6:0] CKE D/A WCOL SSPOV SSPEN CKP GCEN ACKSTAT ACKDT ACKTIM PCIE SCIE MSK0 P S R/W UA BF ACKEN RCEN PEN RSEN SEN BOEN SDAHT SBCDE AHEN DHEN SSPM[3:0] 0x0193 ... Reserved 0x0195 0x0196 SSP2BUF 7:0 BUF[7:0] 0x0197 SSP2ADD 7:0 ADD[7:0] 0x0198 SSP2MSK 7:0 MSK[6:0] MSK0 0x0199 SSP2STAT 7:0 SMP CKE D/A P 0x019A SSP2CON1 7:0 WCOL SSPOV SSPEN CKP S 0x019B SSP2CON2 7:0 GCEN ACKSTAT ACKDT ACKEN RCEN 0x019C SSP2CON3 7:0 ACKTIM PCIE SCIE BOEN SDAHT R/W UA BF PEN RSEN SEN SBCDE AHEN DHEN SSPM[3:0] 0x019D ... Reserved 0x01FF 0x0200 INDF0 7:0 INDF0[7:0] 0x0201 INDF1 7:0 INDF1[7:0] 0x0202 PCL 7:0 PCL[7:0] © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 645 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x0203 STATUS 7:0 0x0204 FSR0 0x0206 FSR1 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] BSR 7:0 0x0209 WREG 7:0 0x020A PCLATH 7:0 0x020B INTCON TMR1 PD FSRL[7:0] 0x0208 0x020C TO 7:0 7:0 PCLATH[6:0] GIE PEIE INTEDG 15:8 TMRxH[7:0] T1CON 7:0 T1GCON 7:0 0x0210 TMR1GATE 7:0 0x0211 TMR1CLK 7:0 C BSR[5:0] TMRxL[7:0] 0x020F DC WREG[7:0] 7:0 0x020E Z CKPS[1:0] GE GPOL GTM SYNC GSPM GGO/DONE RD16 ON RD16 ON RD16 ON GVAL GSS[4:0] CS[4:0] 7:0 TMRxL[7:0] 0x0212 TMR3 0x0214 T3CON 7:0 0x0215 T3GCON 7:0 0x0216 TMR3GATE 7:0 GSS[4:0] 0x0217 TMR3CLK 7:0 CS[4:0] 0x0218 TMR5 0x021A T5CON 15:8 TMRxH[7:0] CKPS[1:0] GE GPOL GTM SYNC GSPM GGO/DONE 7:0 TMRxL[7:0] 15:8 TMRxH[7:0] 7:0 CKPS[1:0] GE GPOL SYNC 0x021B T5GCON 7:0 0x021C TMR5GATE 7:0 GSS[4:0] 0x021D TMR5CLK 7:0 CS[4:0] 0x021E CCPTMRS0 7:0 0x021F CCPTMRS1 7:0 C4TSEL[1:0] GTM GVAL GSPM GGO/DONE GVAL C3TSEL[1:0] C2TSEL[1:0] P7TSEL[1:0] P6TSEL[1:0] C1TSEL[1:0] 0x0220 ... Reserved 0x027F 0x0280 INDF0 7:0 INDF0[7:0] 0x0281 INDF1 7:0 INDF1[7:0] 0x0282 PCL 7:0 PCL[7:0] 0x0283 STATUS 7:0 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0284 FSR0 0x0286 FSR1 0x0288 BSR 7:0 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0289 WREG 7:0 0x028A PCLATH 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] 0x028B INTCON 7:0 0x028C T2TMR 7:0 GIE TxTMR[7:0] 0x028D T2PR 7:0 TxPR[7:0] © 2018 Microchip Technology Inc. PEIE INTEDG Datasheet Preliminary DS40002038B-page 646 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x028E T2CON 7:0 ON 0x028F T2HLT 7:0 PSYNC 0x0290 T2CLKCON 7:0 0x0291 T2RST 7:0 0x0292 T4TMR 7:0 CKPS[2:0] CPOL OUTPS[3:0] CSYNC MODE[4:0] CS[3:0] RSEL[3:0] TxTMR[7:0] 0x0293 T4PR 7:0 0x0294 T4CON 7:0 ON TxPR[7:0] 0x0295 T4HLT 7:0 PSYNC 0x0296 T4CLKCON 7:0 CS[3:0] 0x0297 T4RST 7:0 RSEL[3:0] 0x0298 T6TMR 7:0 0x0299 T6PR 7:0 0x029A T6CON 7:0 ON PSYNC CKPS[2:0] CPOL OUTPS[3:0] CSYNC MODE[4:0] TxTMR[7:0] TxPR[7:0] CKPS[2:0] 0x029B T6HLT 7:0 0x029C T6CLKCON 7:0 CS[3:0] 0x029D T6RST 7:0 RSEL[3:0] 0x029E Reserved 0x029F ADCPCON0 7:0 CPOL OUTPS[3:0] CSYNC MODE[4:0] CPON CPRDY 0x02A0 ... Reserved 0x02FF 0x0300 INDF0 7:0 INDF0[7:0] 0x0301 INDF1 7:0 INDF1[7:0] 0x0302 PCL 7:0 0x0303 STATUS 7:0 0x0304 FSR0 0x0306 FSR1 0x0308 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0309 WREG 7:0 0x030A PCLATH 7:0 0x030B INTCON 7:0 0x030C CCPR1 0x030E CCP1CON 7:0 0x030F CCP1CAP 7:0 PCLATH[6:0] GIE PEIE INTEDG CCPRL[7:0] CCPRH[7:0] EN OUT CCP2CON 7:0 0x0313 CCP2CAP 7:0 0x0314 CCPR3 FMT CCPRL[7:0] 15:8 CCPRH[7:0] EN OUT FMT 7:0 CCPRL[7:0] CCPRH[7:0] 0x0316 CCP3CON 7:0 CCP3CAP 7:0 0x0318 CCPR4 7:0 MODE[3:0] CTS[2:0] 15:8 0x0317 MODE[3:0] CTS[2:0] 7:0 0x0312 C WREG[7:0] 7:0 CCPR2 DC BSR[5:0] 15:8 0x0310 Z EN © 2018 Microchip Technology Inc. OUT FMT MODE[3:0] CTS[2:0] CCPRL[7:0] Datasheet Preliminary DS40002038B-page 647 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x031A CCP4CON 7:0 0x031B CCP4CAP 7:0 0x031C CCPR5 0x031E CCP5CON 7:0 0x031F CCP5CAP 7:0 15:8 CCPRH[7:0] EN OUT FMT MODE[3:0] CTS[2:0] 7:0 CCPRL[7:0] 15:8 CCPRH[7:0] EN OUT FMT MODE[3:0] CTS[2:0] 0x0320 ... Reserved 0x037F 0x0380 INDF0 7:0 INDF0[7:0] 0x0381 INDF1 7:0 INDF1[7:0] 0x0382 PCL 7:0 0x0383 STATUS 7:0 0x0384 FSR0 0x0386 FSR1 0x0388 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0389 WREG 7:0 0x038A PCLATH 7:0 0x038B INTCON 7:0 0x038C PWM6DC 0x038E PWM6CON 0x038F Reserved 0x0390 PWM7DC 0x0392 PWM7CON C WREG[7:0] PCLATH[6:0] GIE 7:0 PEIE INTEDG DCL[1:0] DCH[7:0] EN 7:0 OUT POL OUT POL DCL[1:0] 15:8 7:0 DC BSR[5:0] 15:8 7:0 Z DCH[7:0] EN 0x0393 ... Reserved 0x03FF 0x0400 INDF0 7:0 INDF0[7:0] 0x0401 INDF1 7:0 INDF1[7:0] 0x0402 PCL 7:0 0x0403 STATUS 7:0 0x0404 FSR0 0x0406 FSR1 0x0408 BSR 7:0 7:0 FSRL[7:0] FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0409 WREG 7:0 PCLATH 7:0 0x040B INTCON 7:0 ... PD 15:8 0x040A 0x040C PCL[7:0] TO Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 648 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x0480 INDF0 7:0 INDF0[7:0] 0x0481 INDF1 7:0 INDF1[7:0] 0x0482 PCL 7:0 0x0483 STATUS 7:0 0x0484 FSR0 0x0486 FSR1 0x0488 BSR 7:0 0x0489 WREG 7:0 0x048A PCLATH 7:0 0x048B INTCON 7:0 7:0 TMRL[7:0] 0x048C SMT1TMR 15:8 TMRH[7:0] 23:16 TMRU[7:0] 0x047F 0x048F 0x0492 SMT1CPR SMT1CPW PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 7:0 CPRL[7:0] 15:8 CPRH[7:0] 23:16 CPRU[7:0] 7:0 CPWL[7:0] 15:8 CPWH[7:0] 23:16 CPWU[7:0] 7:0 PRL[7:0] 15:8 PRH[7:0] 0x0495 SMT1PR 0x0498 SMT1CON0 7:0 EN 0x0499 SMT1CON1 7:0 GO REPEAT 0x049A SMT1STAT 7:0 CPRUP CPWUP 0x049B SMT1CLK 7:0 0x049C SMT1SIG 7:0 SSEL[4:0] 0x049D SMT1WIN 7:0 WSEL[4:0] 23:16 PRU[7:0] STP WPOL SPOL CPOL PS[1:0] MODE[3:0] RST TS WS AS CSEL[2:0] 0x049E ... Reserved 0x04FF 0x0500 INDF0 7:0 INDF0[7:0] 0x0501 INDF1 7:0 INDF1[7:0] 0x0502 PCL 7:0 0x0503 STATUS 7:0 0x0504 FSR0 0x0506 FSR1 0x0508 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0509 WREG 7:0 0x050A PCLATH 7:0 0x050B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE © 2018 Microchip Technology Inc. PEIE INTEDG Datasheet Preliminary DS40002038B-page 649 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 7:0 TMRL[7:0] 0x050C SMT2TMR 15:8 TMRH[7:0] 23:16 TMRU[7:0] 0x050F 0x0512 SMT2CPR SMT2CPW 7:0 CPRL[7:0] 15:8 CPRH[7:0] 23:16 CPRU[7:0] 7:0 CPWL[7:0] 15:8 CPWH[7:0] 23:16 CPWU[7:0] 7:0 PRL[7:0] 15:8 PRH[7:0] 0x0515 SMT2PR 0x0518 SMT2CON0 7:0 23:16 PRU[7:0] EN STP WPOL SPOL CPOL 0x0519 SMT2CON1 7:0 GO REPEAT 0x051A SMT2STAT 7:0 CPRUP CPWUP 0x051B SMT2CLK 7:0 0x051C SMT2SIG 7:0 SSEL[4:0] 0x051D SMT2WIN 7:0 WSEL[4:0] PS[1:0] MODE[3:0] RST TS WS AS CSEL[2:0] 0x051E ... Reserved 0x057F 0x0580 INDF0 7:0 INDF0[7:0] 0x0581 INDF1 7:0 INDF1[7:0] 0x0582 PCL 7:0 0x0583 STATUS 7:0 0x0584 FSR0 0x0586 FSR1 0x0588 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0589 WREG 7:0 PCLATH 7:0 0x058B INTCON 7:0 7:0 ACCL[7:0] 0x058C NCO1ACC 15:8 ACCH[7:0] PCLATH[6:0] GIE PEIE INTEDG ACCU[3:0] 7:0 INCL[7:0] 15:8 INCH[7:0] 0x0592 NCO1CON 7:0 0x0593 NCO1CLK 7:0 C WREG[7:0] 23:16 NCO1INC DC BSR[5:0] 0x058A 0x058F Z 23:16 INCU[3:0] EN OUT POL PWS[2:0] PFM CKS[3:0] 0x0594 ... Reserved 0x059B 0x059C TMR0L 7:0 TMR0L[7:0] 0x059D TMR0H 7:0 TMR0H[7:0] © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 650 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x059E T0CON0 7:0 0x059F T0CON1 7:0 T0EN T0OUT T0CS[2:0] T016BIT T0OUTPS[3:0] T0ASYNC T0CKPS[3:0] 0x05A0 ... Reserved 0x05FF 0x0600 INDF0 7:0 INDF0[7:0] 0x0601 INDF1 7:0 INDF1[7:0] 0x0602 PCL 7:0 0x0603 STATUS 7:0 0x0604 FSR0 0x0606 FSR1 0x0608 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0609 WREG 7:0 0x060A PCLATH 7:0 0x060B INTCON 7:0 0x060C CWG1CLK 7:0 0x060D CWG1ISM 7:0 0x060E CWG1DBR 7:0 0x060F CWG1DBF 7:0 0x0610 CWG1CON0 7:0 0x0611 CWG1CON1 7:0 0x0612 CWG1AS0 7:0 0x0613 CWG1AS1 7:0 0x0614 CWG1STR 7:0 0x0615 Reserved 0x0616 CWG2CLK 7:0 0x0617 CWG2ISM 7:0 0x0618 CWG2DBR 7:0 0x0619 CWG2DBF 7:0 0x061A CWG2CON0 7:0 0x061B CWG2CON1 7:0 0x061C CWG2AS0 7:0 0x061D CWG2AS1 7:0 0x061E CWG2STR 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG CS ISM[3:0] DBR[5:0] DBF[5:0] EN LD SHUTDOWN REN MODE[2:0] IN OVRD OVRC POLD LSBD[1:0] POLC POLB POLA LSAC[1:0] AS5E AS4E AS3E AS2E AS1E AS0E OVRB OVRA STRD STRC STRB STRA CS ISM[3:0] DBR[5:0] DBF[5:0] EN LD MODE[2:0] IN SHUTDOWN OVRD REN OVRC POLD LSBD[1:0] POLC POLB POLA LSAC[1:0] AS5E AS4E AS3E AS2E AS1E AS0E OVRB OVRA STRD STRC STRB STRA Z DC C 0x061F ... Reserved 0x067F 0x0680 INDF0 7:0 INDF0[7:0] 0x0681 INDF1 7:0 INDF1[7:0] 0x0682 PCL 7:0 0x0683 STATUS 7:0 0x0684 FSR0 0x0686 FSR1 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 651 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x0688 BSR 7:0 0x0689 WREG 7:0 0x068A PCLATH 7:0 0x068B INTCON 7:0 0x068C CWG3CLK 7:0 0x068D CWG3ISM 7:0 0x068E CWG3DBR 7:0 0x068F CWG3DBF 7:0 0x0690 CWG3CON0 7:0 0x0691 CWG3CON1 7:0 0x0692 CWG3AS0 7:0 0x0693 CWG3AS1 7:0 0x0694 CWG3STR 7:0 15:8 FSRH[7:0] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG CS ISM[3:0] DBR[5:0] DBF[5:0] EN LD MODE[2:0] IN SHUTDOWN OVRD REN OVRC POLD LSBD[1:0] POLC POLB POLA LSAC[1:0] AS5E AS4E AS3E AS2E AS1E AS0E OVRB OVRA STRD STRC STRB STRA Z DC C 0x0695 ... Reserved 0x06FF 0x0700 INDF0 7:0 INDF0[7:0] 0x0701 INDF1 7:0 INDF1[7:0] 0x0702 PCL 7:0 0x0703 STATUS 7:0 0x0704 0x0706 FSR0 FSR1 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0708 BSR 7:0 0x0709 WREG 7:0 0x070A PCLATH 7:0 0x070B INTCON 7:0 0x070C PIR0 7:0 0x070D PIR1 7:0 0x070E PIR2 7:0 0x070F PIR3 7:0 0x0710 PIR4 7:0 0x0711 PIR5 7:0 0x0712 PIR6 7:0 0x0713 PIR7 7:0 0x0714 PIR8 7:0 0x0715 Reserved 0x0716 PIE0 7:0 0x0717 PIE1 7:0 0x0718 PIE2 7:0 0x0719 PIE3 7:0 0x071A PIE4 7:0 0x071B PIE5 7:0 0x071C PIE6 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG TMR0IF OSFIF IOCIF CSWIF ADTIF ZCDIF C2IF C1IF BCL1IF SSP1IF RC2IF TX2IF CLC4IF CLC3IF RC1IF TX1IF BCL2IF TMR6IF TMR5IF TMR4IF CL24IF CLC1IF NVMIF NCO1IF CCP5IF SMT2PWAIF SMT2PRAIF TMR0IE OSFIE INTF CCP4IF SMT2IF SSP2IF TMR3IF TMR2IF TMR1IF TMR5GIF TMR3GIF TMR1GIF CCP3IF CCP2IF CCP1IF CWG3IF CWG2IF CWG1IF SMT1PWAIF SMT1PRAIF IOCIE ADTIE ZCDIE TX2IE CLC4IE CLC3IE © 2018 Microchip Technology Inc. RC1IE TX1IE BCL2IE TMR6IE TMR5IE TMR4IE CLC2IE CLC1IE CCP5IE SMT1IF INTE CSWIE RC2IE ADIF CCP4IE Datasheet Preliminary SSP2IE ADIE C2IE C1IE BCL1IE SSP1IE TMR3IE TMR2IE TMR1IE TMR5GIE TMR3GIE TMR1GIE CCP3IE CCP2IE CCP1IE DS40002038B-page 652 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x071D PIE7 7:0 0x071E PIE8 7:0 NVMIE NCO1IE SMT2PWAIE SMT2PRAIE CWG3IE SMT2IE CWG2IE SMT1PWAIE SMT1PRAIE CWG1IE SMT1IE 0x071F ... Reserved 0x077F 0x0780 INDF0 7:0 INDF0[7:0] 0x0781 INDF1 7:0 INDF1[7:0] 0x0782 PCL 7:0 0x0783 STATUS 7:0 0x0784 FSR0 0x0786 FSR1 0x0788 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] Z DC C BSR[5:0] 0x0789 WREG 7:0 0x078A PCLATH 7:0 WREG[7:0] 0x078B INTCON 7:0 GIE SYSCMD PCLATH[6:0] PEIE INTEDG 0x078C ... Reserved 0x0795 0x0796 PMD0 7:0 0x0797 PMD1 7:0 0x0798 PMD2 7:0 FVRMD TMR6MD TMR5MD 0x0799 PMD3 7:0 DAC1MD ADCMD PMD4 7:0 PWM7MD PWM6MD 0x079B PMD5 7:0 PMD6 7:0 0x079D PMD7 7:0 CLKRMD IOCMD TMR3MD TMR2MD TMR1MD TMR0MD C2MD C1MD ZCDMD CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD MSSP2MD MSSP1MD CLC3MD CLC2MD CLC1MD DSM1MD Z DC C NCO1MD 0x079A 0x079C NVMMD TMR4MD CWG3MD CWG2MD SMT2MD CWG1MD UART2MD UART1MD SMT1MD CLC4MD 0x079E ... Reserved 0x07FF 0x0800 INDF0 7:0 INDF0[7:0] 0x0801 INDF1 7:0 INDF1[7:0] 0x0802 PCL 7:0 PCL[7:0] 0x0803 STATUS 7:0 0x0804 FSR0 0x0806 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0808 BSR 7:0 0x0809 WREG 7:0 0x080A PCLATH 7:0 0x080B INTCON 7:0 0x080C WDTCON0 7:0 0x080D WDTCON1 7:0 0x080E WDTPSL 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] GIE © 2018 Microchip Technology Inc. PEIE INTEDG WDTPS[4:0] WDTCS[2:0] SEN WINDOW[2:0] PSCNTL[7:0] Datasheet Preliminary DS40002038B-page 653 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x080F WDTPSH 7:0 0x0810 WDTTMR 7:0 0x0811 BORCON 7:0 0x0812 VREGCON 7:0 0x0813 PCON0 7:0 0x0814 PCON1 7:0 PSCNTH[7:0] WDTTMR[4:0] STATE PSCNT[1:0] SBOREN BORRDY VREGPM STKOVF STKUNF WDTWV RWDT RMCLR RI POR BOR MEMV 0x0815 ... Reserved 0x0819 7:0 NVMADRL[7:0] 0x081A NVMADR 0x081C NVMDAT 0x081E NVMCON1 7:0 0x081F NVMCON2 7:0 NVMCON2[7:0] 15:8 NVMADRH[6:0] 7:0 NVMDATL[7:0] 15:8 NVMDATH[5:0] NVMREGS LWLO FREE WRERR WREN WR RD Z DC C 0x0820 ... Reserved 0x087F 0x0880 INDF0 7:0 INDF0[7:0] 0x0881 INDF1 7:0 INDF1[7:0] 0x0882 PCL 7:0 0x0883 STATUS 7:0 0x0884 FSR0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0886 FSR1 0x0888 BSR 7:0 0x0889 WREG 7:0 0x088A PCLATH 7:0 0x088B INTCON 7:0 GIE PEIE 0x088C CPUDOZE 7:0 IDLEN DOZEN 0x088D OSCCON1 7:0 NOSC[2:0] NDIV[3:0] 0x088E OSCCON2 7:0 COSC[2:0] CDIV[3:0] 0x088F OSCCON3 7:0 CSWHOLD SOSCPWR 0x0890 OSCSTAT 7:0 EXTOR HFOR MFOR LFOR SOR ADOR 0x0891 OSCEN 7:0 EXTOEN HFOEN MFOEN LFOEN SOSCEN ADOEN BSR[5:0] WREG[7:0] PCLATH[6:0] INTEDG ROI DOE DOZE[2:0] ORDY NOSCR PLLR 0x0892 OSCTUNE 7:0 0x0893 OSCFRQ 7:0 HFTUN[5:0] 0x0894 Reserved 0x0895 CLKRCON 7:0 0x0896 CLKRCLK 7:0 0x0897 MD1CON0 7:0 0x0898 MD1CON1 7:0 0x0899 MD1SRC 7:0 0x089A MD1CARL 7:0 CLS[3:0] 0x089B MD1CARH 7:0 CHS[3:0] HFFRQ[2:0] EN DC[1:0] DIV[2:0] CLK[3:0] EN © 2018 Microchip Technology Inc. OUT OPOL CHPOL CHSYNC BIT CLPOL CLSYNC SRCS[4:0] Datasheet Preliminary DS40002038B-page 654 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x089C ... Reserved 0x08FF 0x0900 INDF0 7:0 INDF0[7:0] 0x0901 INDF1 7:0 INDF1[7:0] 0x0902 PCL 7:0 PCL[7:0] 0x0903 STATUS 7:0 0x0904 FSR0 0x0906 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0908 BSR 7:0 0x0909 WREG 7:0 0x090A PCLATH 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] 0x090B INTCON 7:0 GIE PEIE 0x090C FVRCON 7:0 FVREN FVRRDY 0x090D Reserved 0x090E DAC1CON0 7:0 EN 0x090F DAC1CON1 7:0 INTEDG TSEN TSRNG CDAFVR[1:0] OE1 OE2 PSS[1:0] ADFVR[1:0] NSS DAC1R[4:0] 0x0910 ... Reserved 0x091E 0x091F ZCDCON 7:0 SEN OUT POL INTP INTN DC C 0x0920 ... Reserved 0x097F 0x0980 INDF0 7:0 INDF0[7:0] 0x0981 INDF1 7:0 INDF1[7:0] 0x0982 PCL 7:0 PCL[7:0] 0x0983 STATUS 7:0 0x0984 0x0986 FSR0 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0988 BSR 7:0 0x0989 WREG 7:0 0x098A PCLATH 7:0 0x098B INTCON 7:0 Z BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE EN OUT INTEDG 0x098C ... Reserved 0x098E 0x098F CMOUT 7:0 0x0990 CM1CON0 7:0 MC2OUT MC1OUT HYS SYNC 0x0991 CM1CON1 0x0992 CM1NCH 7:0 INTP INTN 7:0 NCH[2:0] 0x0993 CM1PCH 7:0 PCH[2:0] © 2018 Microchip Technology Inc. POL Datasheet Preliminary DS40002038B-page 655 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x0994 CM2CON0 7:0 HYS SYNC 0x0995 CM2CON1 7:0 INTP INTN 0x0996 CM2NCH 7:0 NCH[2:0] 0x0997 CM2PCH 7:0 PCH[2:0] EN OUT POL 0x0998 ... Reserved 0x09FF 0x0A00 INDF0 7:0 INDF0[7:0] 0x0A01 INDF1 7:0 INDF1[7:0] 0x0A02 PCL 7:0 0x0A03 STATUS 7:0 0x0A04 FSR0 0x0A06 FSR1 0x0A08 BSR 7:0 0x0A09 WREG 7:0 0x0A0A PCLATH 7:0 0x0A0B INTCON 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x0A0C ... Reserved 0x0A18 0x0A19 RC2REG 7:0 RCREG[7:0] 0x0A1A TX2REG 7:0 TXREG[7:0] 7:0 SPBRGL[7:0] 0x0A1B SP2BRG 0x0A1D RC2STA 7:0 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0x0A1E TX2STA 7:0 CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0x0A1F BAUD2CON 7:0 ABDOVF RCIDL SCKP BRG16 WUE ABDEN DC C 15:8 SPBRGH[7:0] 0x0A20 ... Reserved 0x0A7F 0x0A80 INDF0 7:0 INDF0[7:0] 0x0A81 INDF1 7:0 INDF1[7:0] 0x0A82 PCL 7:0 0x0A83 STATUS 7:0 0x0A84 FSR0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] FSR1 0x0A88 BSR 7:0 0x0A89 WREG 7:0 0x0A8A PCLATH 7:0 0x0A8B INTCON 7:0 ... PD 7:0 0x0A86 0x0A8C PCL[7:0] TO Z BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 656 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x0B00 INDF0 7:0 INDF0[7:0] 0x0B01 INDF1 7:0 INDF1[7:0] 0x0B02 PCL 7:0 0x0B03 STATUS 7:0 0x0B04 FSR0 0x0B06 FSR1 0x0B08 BSR 7:0 0x0B09 WREG 7:0 0x0B0A PCLATH 7:0 0x0B0B INTCON 7:0 0x0AFF PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x0B0C ... Reserved 0x0B7F 0x0B80 INDF0 7:0 INDF0[7:0] 0x0B81 INDF1 7:0 INDF1[7:0] 0x0B82 PCL 7:0 PCL[7:0] 0x0B83 STATUS 7:0 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0B84 FSR0 0x0B86 FSR1 0x0B88 BSR 7:0 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0B89 WREG 7:0 0x0B8A PCLATH 7:0 0x0B8B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x0B8C ... Reserved 0x0BFF 0x0C00 INDF0 7:0 INDF0[7:0] 0x0C01 INDF1 7:0 INDF1[7:0] 0x0C02 PCL 7:0 0x0C03 STATUS 7:0 0x0C04 0x0C06 FSR0 FSR1 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0C08 BSR 7:0 0x0C09 WREG 7:0 0x0C0A PCLATH 7:0 0x0C0B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x0C0C ... Reserved 0x0C7F © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 657 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x0C80 INDF0 7:0 INDF0[7:0] 0x0C81 INDF1 7:0 INDF1[7:0] 0x0C82 PCL 7:0 PCL[7:0] 0x0C83 STATUS 7:0 0x0C84 0x0C86 FSR0 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0C88 BSR 7:0 0x0C89 WREG 7:0 0x0C8A PCLATH 7:0 0x0C8B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x0C8C ... Reserved 0x0CFF 0x0D00 INDF0 7:0 INDF0[7:0] 0x0D01 INDF1 7:0 INDF1[7:0] 0x0D02 PCL 7:0 0x0D03 STATUS 7:0 0x0D04 FSR0 0x0D06 FSR1 0x0D08 BSR 7:0 0x0D09 WREG 7:0 0x0D0A PCLATH 7:0 0x0D0B INTCON 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x0D0C ... Reserved 0x0D7F 0x0D80 INDF0 7:0 INDF0[7:0] 0x0D81 INDF1 7:0 INDF1[7:0] 0x0D82 PCL 7:0 PCL[7:0] 0x0D83 STATUS 7:0 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0D84 FSR0 0x0D86 FSR1 0x0D88 BSR 7:0 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0D89 WREG 7:0 0x0D8A PCLATH 7:0 0x0D8B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x0D8C ... Reserved 0x0DFF 0x0E00 INDF0 7:0 © 2018 Microchip Technology Inc. INDF0[7:0] Datasheet Preliminary DS40002038B-page 658 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x0E01 INDF1 7:0 0x0E02 PCL 7:0 0x0E03 STATUS 7:0 0x0E04 FSR0 0x0E06 FSR1 0x0E08 BSR 7:0 INDF1[7:0] PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0E09 WREG 7:0 0x0E0A PCLATH 7:0 0x0E0B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x0E0C ... Reserved 0x0E7F 0x0E80 INDF0 7:0 INDF0[7:0] 0x0E81 INDF1 7:0 INDF1[7:0] 0x0E82 PCL 7:0 PCL[7:0] 0x0E83 STATUS 7:0 0x0E84 0x0E86 FSR0 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0E88 BSR 7:0 0x0E89 WREG 7:0 0x0E8A PCLATH 7:0 0x0E8B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x0E8C ... Reserved 0x0EFF 0x0F00 INDF0 7:0 INDF0[7:0] 0x0F01 INDF1 7:0 INDF1[7:0] 0x0F02 PCL 7:0 0x0F03 STATUS 7:0 0x0F04 FSR0 0x0F06 FSR1 0x0F08 BSR 7:0 0x0F09 WREG 7:0 0x0F0A PCLATH 7:0 0x0F0B INTCON 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x0F0C ... Reserved 0x0F7F 0x0F80 INDF0 7:0 INDF0[7:0] 0x0F81 INDF1 7:0 INDF1[7:0] © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 659 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x0F82 PCL 7:0 0x0F83 STATUS 7:0 0x0F84 FSR0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x0F86 FSR1 0x0F88 BSR 7:0 0x0F89 WREG 7:0 0x0F8A PCLATH 7:0 0x0F8B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x0F8C ... Reserved 0x0FFF 0x1000 INDF0 7:0 INDF0[7:0] 0x1001 INDF1 7:0 INDF1[7:0] 0x1002 PCL 7:0 0x1003 STATUS 7:0 0x1004 FSR0 0x1006 FSR1 0x1008 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1009 WREG 7:0 0x100A PCLATH 7:0 0x100B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x100C ... Reserved 0x107F 0x1080 INDF0 7:0 INDF0[7:0] 0x1081 INDF1 7:0 INDF1[7:0] 0x1082 PCL 7:0 PCL[7:0] 0x1083 STATUS 7:0 0x1084 0x1086 FSR0 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1088 BSR 7:0 0x1089 WREG 7:0 0x108A PCLATH 7:0 0x108B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x108C ... Reserved 0x10FF 0x1100 INDF0 7:0 INDF0[7:0] 0x1101 INDF1 7:0 INDF1[7:0] 0x1102 PCL 7:0 PCL[7:0] © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 660 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x1103 STATUS 7:0 0x1104 FSR0 0x1106 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1108 BSR 7:0 0x1109 WREG 7:0 0x110A PCLATH 7:0 0x110B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x110C ... Reserved 0x117F 0x1180 INDF0 7:0 INDF0[7:0] 0x1181 INDF1 7:0 INDF1[7:0] 0x1182 PCL 7:0 0x1183 STATUS 7:0 0x1184 FSR0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1186 FSR1 0x1188 BSR 7:0 0x1189 WREG 7:0 0x118A PCLATH 7:0 0x118B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x118C ... Reserved 0x11FF 0x1200 INDF0 7:0 INDF0[7:0] 0x1201 INDF1 7:0 INDF1[7:0] 0x1202 PCL 7:0 0x1203 STATUS 7:0 0x1204 FSR0 0x1206 FSR1 0x1208 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1209 WREG 7:0 0x120A PCLATH 7:0 0x120B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x120C ... Reserved 0x127F 0x1280 INDF0 7:0 INDF0[7:0] 0x1281 INDF1 7:0 INDF1[7:0] 0x1282 PCL 7:0 PCL[7:0] 0x1283 STATUS 7:0 © 2018 Microchip Technology Inc. TO PD Datasheet Preliminary Z DC C DS40002038B-page 661 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x1284 FSR0 0x1286 FSR1 0x1288 BSR 7:0 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1289 WREG 7:0 0x128A PCLATH 7:0 0x128B INTCON 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x128C ... Reserved 0x12FF 0x1300 INDF0 7:0 INDF0[7:0] 0x1301 INDF1 7:0 INDF1[7:0] 0x1302 PCL 7:0 PCL[7:0] 0x1303 STATUS 7:0 0x1304 FSR0 0x1306 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1308 BSR 7:0 0x1309 WREG 7:0 0x130A PCLATH 7:0 0x130B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x130C ... Reserved 0x137F 0x1380 INDF0 7:0 INDF0[7:0] 0x1381 INDF1 7:0 INDF1[7:0] 0x1382 PCL 7:0 0x1383 STATUS 7:0 0x1384 FSR0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1386 FSR1 0x1388 BSR 7:0 0x1389 WREG 7:0 0x138A PCLATH 7:0 0x138B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x138C ... Reserved 0x13FF 0x1400 INDF0 7:0 INDF0[7:0] 0x1401 INDF1 7:0 INDF1[7:0] 0x1402 PCL 7:0 0x1403 STATUS 7:0 0x1404 FSR0 7:0 © 2018 Microchip Technology Inc. PCL[7:0] TO PD Z DC C FSRL[7:0] Datasheet Preliminary DS40002038B-page 662 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 15:8 0x1406 FSR1 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1408 BSR 7:0 0x1409 WREG 7:0 0x140A PCLATH 7:0 0x140B INTCON 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x140C ... Reserved 0x147F 0x1480 INDF0 7:0 INDF0[7:0] 0x1481 INDF1 7:0 INDF1[7:0] 0x1482 PCL 7:0 0x1483 STATUS 7:0 0x1484 FSR0 0x1486 FSR1 0x1488 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1489 WREG 7:0 0x148A PCLATH 7:0 0x148B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x148C ... Reserved 0x14FF 0x1500 INDF0 7:0 INDF0[7:0] 0x1501 INDF1 7:0 INDF1[7:0] 0x1502 PCL 7:0 PCL[7:0] 0x1503 STATUS 7:0 0x1504 FSR0 0x1506 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1508 BSR 7:0 0x1509 WREG 7:0 0x150A PCLATH 7:0 0x150B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x150C ... Reserved 0x157F 0x1580 INDF0 7:0 INDF0[7:0] 0x1581 INDF1 7:0 INDF1[7:0] 0x1582 PCL 7:0 0x1583 STATUS 7:0 0x1584 FSR0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] © 2018 Microchip Technology Inc. Datasheet Preliminary Z DC C DS40002038B-page 663 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x1586 FSR1 0x1588 BSR 7:0 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1589 WREG 7:0 0x158A PCLATH 7:0 0x158B INTCON 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x158C ... Reserved 0x15FF 0x1600 INDF0 7:0 INDF0[7:0] 0x1601 INDF1 7:0 INDF1[7:0] 0x1602 PCL 7:0 0x1603 STATUS 7:0 0x1604 0x1606 FSR0 FSR1 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1608 BSR 7:0 0x1609 WREG 7:0 0x160A PCLATH 7:0 0x160B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x160C ... Reserved 0x167F 0x1680 INDF0 7:0 INDF0[7:0] 0x1681 INDF1 7:0 INDF1[7:0] 0x1682 PCL 7:0 0x1683 STATUS 7:0 0x1684 FSR0 0x1686 FSR1 0x1688 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1689 WREG 7:0 0x168A PCLATH 7:0 0x168B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x168C ... Reserved 0x16FF 0x1700 INDF0 7:0 INDF0[7:0] 0x1701 INDF1 7:0 INDF1[7:0] 0x1702 PCL 7:0 PCL[7:0] 0x1703 STATUS 7:0 0x1704 FSR0 0x1706 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] © 2018 Microchip Technology Inc. Datasheet Preliminary Z DC C DS40002038B-page 664 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x1708 BSR 7:0 0x1709 WREG 7:0 0x170A PCLATH 7:0 0x170B INTCON 7:0 15:8 FSRH[7:0] BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x170C ... Reserved 0x177F 0x1780 INDF0 7:0 INDF0[7:0] 0x1781 INDF1 7:0 INDF1[7:0] 0x1782 PCL 7:0 PCL[7:0] 0x1783 STATUS 7:0 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1784 FSR0 0x1786 FSR1 0x1788 BSR 7:0 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1789 WREG 7:0 0x178A PCLATH 7:0 0x178B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x178C ... Reserved 0x17FF 0x1800 INDF0 7:0 INDF0[7:0] 0x1801 INDF1 7:0 INDF1[7:0] 0x1802 PCL 7:0 0x1803 STATUS 7:0 0x1804 0x1806 FSR0 FSR1 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1808 BSR 7:0 0x1809 WREG 7:0 0x180A PCLATH 7:0 0x180B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x180C ... Reserved 0x187F 0x1880 INDF0 7:0 INDF0[7:0] 0x1881 INDF1 7:0 INDF1[7:0] 0x1882 PCL 7:0 0x1883 STATUS 7:0 0x1884 FSR0 0x1886 FSR1 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] © 2018 Microchip Technology Inc. Datasheet Preliminary Z DC C DS40002038B-page 665 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x1888 BSR 7:0 0x1889 WREG 7:0 0x188A PCLATH 7:0 0x188B INTCON 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x188C ... Reserved 0x18FF 0x1900 INDF0 7:0 INDF0[7:0] 0x1901 INDF1 7:0 INDF1[7:0] 0x1902 PCL 7:0 0x1903 STATUS 7:0 0x1904 FSR0 0x1906 FSR1 0x1908 BSR 7:0 0x1909 WREG 7:0 0x190A PCLATH 7:0 0x190B INTCON 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x190C ... Reserved 0x197F 0x1980 INDF0 7:0 INDF0[7:0] 0x1981 INDF1 7:0 INDF1[7:0] 0x1982 PCL 7:0 PCL[7:0] 0x1983 STATUS 7:0 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1984 FSR0 0x1986 FSR1 0x1988 BSR 7:0 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1989 WREG 7:0 0x198A PCLATH 7:0 0x198B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x198C ... Reserved 0x19FF 0x1A00 INDF0 7:0 INDF0[7:0] 0x1A01 INDF1 7:0 INDF1[7:0] 0x1A02 PCL 7:0 0x1A03 STATUS 7:0 0x1A04 FSR0 0x1A06 FSR1 0x1A08 BSR PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 © 2018 Microchip Technology Inc. Z DC C BSR[5:0] Datasheet Preliminary DS40002038B-page 666 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x1A09 WREG 7:0 0x1A0A PCLATH 7:0 0x1A0B INTCON 7:0 WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x1A0C ... Reserved 0x1A7F 0x1A80 INDF0 7:0 INDF0[7:0] 0x1A81 INDF1 7:0 INDF1[7:0] 0x1A82 PCL 7:0 PCL[7:0] 0x1A83 STATUS 7:0 0x1A84 0x1A86 FSR0 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1A88 BSR 7:0 0x1A89 WREG 7:0 0x1A8A PCLATH 7:0 0x1A8B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x1A8C ... Reserved 0x1AFF 0x1B00 INDF0 7:0 INDF0[7:0] 0x1B01 INDF1 7:0 INDF1[7:0] 0x1B02 PCL 7:0 0x1B03 STATUS 7:0 0x1B04 FSR0 0x1B06 FSR1 0x1B08 BSR 7:0 0x1B09 WREG 7:0 0x1B0A PCLATH 7:0 0x1B0B INTCON 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x1B0C ... Reserved 0x1B7F 0x1B80 INDF0 7:0 INDF0[7:0] 0x1B81 INDF1 7:0 INDF1[7:0] 0x1B82 PCL 7:0 PCL[7:0] 0x1B83 STATUS 7:0 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1B84 FSR0 0x1B86 FSR1 0x1B88 BSR 7:0 0x1B89 WREG 7:0 7:0 FSRL[7:0] 15:8 FSRH[7:0] © 2018 Microchip Technology Inc. Z DC C BSR[5:0] WREG[7:0] Datasheet Preliminary DS40002038B-page 667 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x1B8A PCLATH 7:0 0x1B8B INTCON 7:0 PCLATH[6:0] GIE PEIE INTEDG 0x1B8C ... Reserved 0x1BFF 0x1C00 INDF0 7:0 INDF0[7:0] 0x1C01 INDF1 7:0 INDF1[7:0] 0x1C02 PCL 7:0 0x1C03 STATUS 7:0 0x1C04 FSR0 0x1C06 FSR1 0x1C08 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1C09 WREG 7:0 0x1C0A PCLATH 7:0 0x1C0B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x1C0C ... Reserved 0x1C7F 0x1C80 INDF0 7:0 INDF0[7:0] 0x1C81 INDF1 7:0 INDF1[7:0] 0x1C82 PCL 7:0 PCL[7:0] 0x1C83 STATUS 7:0 0x1C84 0x1C86 FSR0 FSR1 TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1C88 BSR 7:0 0x1C89 WREG 7:0 0x1C8A PCLATH 7:0 0x1C8B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x1C8C ... Reserved 0x1CFF 0x1D00 INDF0 7:0 INDF0[7:0] 0x1D01 INDF1 7:0 INDF1[7:0] 0x1D02 PCL 7:0 0x1D03 STATUS 7:0 0x1D04 FSR0 0x1D06 FSR1 0x1D08 BSR 7:0 0x1D09 WREG 7:0 0x1D0A PCLATH 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] © 2018 Microchip Technology Inc. Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] Datasheet Preliminary DS40002038B-page 668 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x1D0B INTCON 7:0 GIE PEIE INTEDG 0x1D0C ... Reserved 0x1D7F 0x1D80 INDF0 7:0 INDF0[7:0] 0x1D81 INDF1 7:0 INDF1[7:0] 0x1D82 PCL 7:0 0x1D83 STATUS 7:0 0x1D84 FSR0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1D86 FSR1 0x1D88 BSR 7:0 0x1D89 WREG 7:0 0x1D8A PCLATH 7:0 0x1D8B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x1D8C ... Reserved 0x1DFF 0x1E00 INDF0 7:0 INDF0[7:0] 0x1E01 INDF1 7:0 INDF1[7:0] 0x1E02 PCL 7:0 0x1E03 STATUS 7:0 0x1E04 FSR0 0x1E06 FSR1 0x1E08 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1E09 WREG 7:0 0x1E0A PCLATH 7:0 0x1E0B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x1E0C ... Reserved 0x1E0E 0x1E0F CLCDATA 7:0 0x1E10 CLC1CON 7:0 EN MLC4OUT 0x1E11 CLC1POL 7:0 POL OUT INTP MLC3OUT INTN MLC2OUT MLC1OUT MODE[2:0] G4POL G3POL G2POL G1POL 0x1E12 CLC1SEL0 7:0 D1S[5:0] 0x1E13 CLC1SEL1 7:0 D2S[5:0] 0x1E14 CLC1SEL2 7:0 D3S[5:0] 0x1E15 CLC1SEL3 7:0 0x1E16 CLC1GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x1E17 CLC1GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x1E18 CLC1GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x1E19 CLC1GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 0x1E1A CLC2CON 7:0 EN OUT INTP INTN D4S[5:0] © 2018 Microchip Technology Inc. Datasheet Preliminary MODE[2:0] DS40002038B-page 669 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x1E1B CLC2POL 7:0 0x1E1C CLC2SEL0 7:0 POL G4POL D1S[5:0] G3POL 0x1E1D CLC2SEL1 7:0 D2S[5:0] 0x1E1E CLC2SEL2 7:0 D3S[5:0] 0x1E1F CLC2SEL3 7:0 D4S[5:0] G2POL G1POL 0x1E20 CLC2GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x1E21 CLC2GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x1E22 CLC2GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x1E23 CLC2GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 0x1E24 CLC3CON 7:0 EN OUT INTP INTN 0x1E25 CLC3POL 7:0 POL MODE[2:0] G4POL G3POL G2POL G1POL 0x1E26 CLC3SEL0 7:0 D1S[5:0] 0x1E27 CLC3SEL1 7:0 D2S[5:0] 0x1E28 CLC3SEL2 7:0 D3S[5:0] 0x1E29 CLC3SEL3 7:0 0x1E2A CLC3GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N D4S[5:0] 0x1E2B CLC3GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x1E2C CLC3GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x1E2D CLC3GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N 0x1E2E CLC4CON 7:0 EN OUT INTP 0x1E2F CLC4POL 7:0 POL INTN MODE[2:0] G4POL G3POL G2POL G1POL 0x1E30 CLC4SEL0 7:0 D1S[5:0] 0x1E31 CLC4SEL1 7:0 D2S[5:0] 0x1E32 CLC4SEL2 7:0 D3S[5:0] 0x1E33 CLC4SEL3 7:0 0x1E34 CLC4GLS0 7:0 G1D4T G1D4N G1D3T G1D3N G1D2T G1D2N G1D1T G1D1N 0x1E35 CLC4GLS1 7:0 G2D4T G2D4N G2D3T G2D3N G2D2T G2D2N G2D1T G2D1N 0x1E36 CLC4GLS2 7:0 G3D4T G3D4N G3D3T G3D3N G3D2T G3D2N G3D1T G3D1N 0x1E37 CLC4GLS3 7:0 G4D4T G4D4N G4D3T G4D3N G4D2T G4D2N G4D1T G4D1N Z DC C D4S[5:0] 0x1E38 ... Reserved 0x1E7F 0x1E80 INDF0 7:0 INDF0[7:0] 0x1E81 INDF1 7:0 INDF1[7:0] 0x1E82 PCL 7:0 PCL[7:0] 0x1E83 STATUS 7:0 15:8 FSRH[7:0] FSR0 0x1E86 FSR1 0x1E88 BSR 7:0 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1E89 WREG 7:0 0x1E8A PCLATH 7:0 0x1E8B INTCON 7:0 ... PD FSRL[7:0] 0x1E84 0x1E8C TO 7:0 BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG Reserved © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 670 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x1E8F PPSLOCK 7:0 0x1E90 INTPPS 7:0 PORT[1:0] PIN[2:0] 0x1E91 T0CKIPPS 7:0 PORT[1:0] PIN[2:0] 0x1E92 T1CKIPPS 7:0 PORT[1:0] PIN[2:0] 0x1E93 T1GPPS 7:0 PORT[1:0] PIN[2:0] 0x1E94 T3CKIPPS 7:0 PORT[1:0] PIN[2:0] 0x1E95 T3GPPS 7:0 PORT[1:0] PIN[2:0] 0x1E96 T5CKIPPS 7:0 PORT[1:0] PIN[2:0] 0x1E97 T5GPPS 7:0 PORT[1:0] PIN[2:0] 0x1E8E PPSLOCKED 0x1E98 ... Reserved 0x1E9B 0x1E9C T2INPPS 7:0 PORT[1:0] PIN[2:0] 0x1E9D T4INPPS 7:0 PORT[1:0] PIN[2:0] 0x1E9E T6INPPS 7:0 PORT[1:0] PIN[2:0] 0x1E9F ... Reserved 0x1EA0 0x1EA1 CCP1PPS 7:0 PORT[1:0] PIN[2:0] 0x1EA2 CCP2PPS 7:0 PORT[1:0] PIN[2:0] 0x1EA3 CCP3PPS 7:0 PORT[1:0] PIN[2:0] 0x1EA4 CCP4PPS 7:0 PORT[1:0] PIN[2:0] 0x1EA5 CCP5PPS 7:0 PORT[1:0] PIN[2:0] 0x1EA6 ... Reserved 0x1EA8 0x1EA9 SMT1WINPPS 7:0 PORT[1:0] PIN[2:0] 0x1EAA SMT1SIGPPS 7:0 PORT[1:0] PIN[2:0] 0x1EAB SMT2WINPPS 7:0 PORT[1:0] PIN[2:0] 0x1EAC SMT2SIGPPS 7:0 PORT[1:0] PIN[2:0] 0x1EAD ... Reserved 0x1EB0 0x1EB1 CWG1PPS 7:0 PORT[1:0] PIN[2:0] 0x1EB2 CWG2PPS 7:0 PORT[1:0] PIN[2:0] 0x1EB3 CWG3PPS 7:0 PORT[1:0] PIN[2:0] 0x1EB4 ... Reserved 0x1EB7 0x1EB8 MDCARLPPS 7:0 PORT[1:0] PIN[2:0] 0x1EB9 MDCARHPPS 7:0 PORT[1:0] PIN[2:0] 0x1EBA MDSRCPPS 7:0 PORT[1:0] PIN[2:0] 0x1EBB CLCIN0PPS 7:0 PORT[1:0] PIN[2:0] 0x1EBC CLCIN1PPS 7:0 PORT[1:0] PIN[2:0] 0x1EBD CLCIN2PPS 7:0 PORT[1:0] PIN[2:0] © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 671 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x1EBE CLCIN3PPS 7:0 PORT[1:0] PIN[2:0] 7:0 PORT[1:0] PIN[2:0] 0x1EBF ... Reserved 0x1EC2 0x1EC3 ADACTPPS 0x1EC4 Reserved 0x1EC5 SSP1CLKPPS 7:0 PORT[1:0] PIN[2:0] 0x1EC6 SSP1DATPPS 7:0 PORT[1:0] PIN[2:0] 0x1EC7 SSP1SSPPS 7:0 PORT[1:0] PIN[2:0] 0x1EC8 SSP2CLKPPS 7:0 PORT[1:0] PIN[2:0] 0x1EC9 SSP2DATPPS 7:0 PORT[1:0] PIN[2:0] 0x1ECA SSP2SSPPS 7:0 PORT[1:0] PIN[2:0] 0x1ECB RX1PPS 7:0 PORT[1:0] PIN[2:0] 0x1ECC CK1PPS 7:0 PORT[1:0] PIN[2:0] 0x1ECD RX2PPS 7:0 PORT[1:0] PIN[2:0] 0x1ECE CK2PPS 7:0 PORT[1:0] PIN[2:0] 0x1ECF ... Reserved 0x1EFF 0x1F00 INDF0 7:0 INDF0[7:0] 0x1F01 INDF1 7:0 INDF1[7:0] 0x1F02 PCL 7:0 0x1F03 STATUS 7:0 0x1F04 FSR0 0x1F06 FSR1 0x1F08 BSR 7:0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1F09 WREG 7:0 0x1F0A PCLATH 7:0 0x1F0B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x1F0C ... Reserved 0x1F0F 0x1F10 RA0PPS 7:0 PPS[5:0] 0x1F11 RA1PPS 7:0 PPS[5:0] 0x1F12 RA2PPS 7:0 PPS[5:0] 0x1F13 RA3PPS 7:0 PPS[5:0] 0x1F14 RA4PPS 7:0 PPS[5:0] 0x1F15 RA5PPS 7:0 PPS[5:0] 0x1F16 RA6PPS 7:0 PPS[5:0] 0x1F17 RA7PPS 7:0 PPS[5:0] 0x1F18 RB0PPS 7:0 PPS[5:0] 0x1F19 RB1PPS 7:0 PPS[5:0] 0x1F1A RB2PPS 7:0 PPS[5:0] 0x1F1B RB3PPS 7:0 PPS[5:0] © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 672 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. 0x1F1C RB4PPS 7:0 PPS[5:0] 0x1F1D RB5PPS 7:0 PPS[5:0] 0x1F1E RB6PPS 7:0 PPS[5:0] 0x1F1F RB7PPS 7:0 PPS[5:0] 0x1F20 RC0PPS 7:0 PPS[5:0] 0x1F21 RC1PPS 7:0 PPS[5:0] 0x1F22 RC2PPS 7:0 PPS[5:0] 0x1F23 RC3PPS 7:0 PPS[5:0] 0x1F24 RC4PPS 7:0 PPS[5:0] 0x1F25 RC5PPS 7:0 PPS[5:0] 0x1F26 RC6PPS 7:0 PPS[5:0] 0x1F27 RC7PPS 7:0 PPS[5:0] 0x1F28 ... Reserved 0x1F37 0x1F38 ANSELA 7:0 ANSELA7 ANSELA6 ANSELA5 ANSELA4 ANSELA3 ANSELA2 ANSELA1 ANSELA0 0x1F39 WPUA 7:0 WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 0x1F3A ODCONA 7:0 ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0x1F3B SLRCONA 7:0 SLRA7 SLRA6 SLRA5 SLRA4 SLRA3 SLRA2 SLRA1 SLRA0 0x1F3C INLVLA 7:0 INLVLA7 INLVLA6 INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 0x1F3D IOCAP 7:0 IOCAP7 IOCAP6 IOCAP5 IOCAP4 IOCAP3 IOCAP2 IOCAP1 IOCAP0 0x1F3E IOCAN 7:0 IOCAN7 IOCAN6 IOCAN5 IOCAN4 IOCAN3 IOCAN2 IOCAN1 IOCAN0 0x1F3F IOCAF 7:0 IOCAF7 IOCAF6 IOCAF5 IOCAF4 IOCAF3 IOCAF2 IOCAF1 IOCAF0 0x1F40 ... Reserved 0x1F42 0x1F43 ANSELB 7:0 ANSELB7 ANSELB6 ANSELB5 ANSELB4 ANSELB3 ANSELB2 ANSELB1 ANSELB0 0x1F44 WPUB 7:0 WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 0x1F45 ODCONB 7:0 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0x1F46 SLRCONB 7:0 SLRB7 SLRB6 SLRB5 SLRB4 SLRB3 SLRB2 SLRB1 SLRB0 0x1F47 INLVLB 7:0 INLVLB7 INLVLB6 INLVLB5 INLVLB4 INLVLB3 INLVLB2 INLVLB1 INLVLB0 0x1F48 IOCBP 7:0 IOCBP7 IOCBP6 IOCBP5 IOCBP4 IOCBP3 IOCBP2 IOCBP1 IOCBP0 0x1F49 IOCBN 7:0 IOCBN7 IOCBN6 IOCBN5 IOCBN4 IOCBN3 IOCBN2 IOCBN1 IOCBN0 0x1F4A IOCBF 7:0 IOCBF7 IOCBF6 IOCBF5 IOCBF4 IOCBF3 IOCBF2 IOCBF1 IOCBF0 0x1F4B ... Reserved 0x1F4D 0x1F4E ANSELC 7:0 ANSELC7 ANSELC6 ANSELC5 ANSELC4 ANSELC3 ANSELC2 ANSELC1 ANSELC0 0x1F4F WPUC 7:0 WPUC7 WPUC6 WPUC5 WPUC4 WPUC3 WPUC2 WPUC1 WPUC0 0x1F50 ODCONC 7:0 ODCC7 ODCC6 ODCC5 ODCC4 ODCC3 ODCC2 ODCC1 ODCC0 0x1F51 SLRCONC 7:0 SLRC7 SLRC6 SLRC5 SLRC4 SLRC3 SLRC2 SLRC1 SLRC0 0x1F52 INLVLC 7:0 INLVLC7 INLVLC6 INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 0x1F53 IOCCP 7:0 IOCCP7 IOCCP6 IOCCP5 IOCCP4 IOCCP3 IOCCP2 IOCCP1 IOCCP0 0x1F54 IOCCN 7:0 IOCCN7 IOCCN6 IOCCN5 IOCCN4 IOCCN3 IOCCN2 IOCCN1 IOCCN0 0x1F55 IOCCF 7:0 IOCCF7 IOCCF6 IOCCF5 IOCCF4 IOCCF3 IOCCF2 IOCCF1 IOCCF0 0x1F56 Reserved © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 673 PIC16(L)F18455/56 Register Summary Address Name Bit Pos. WPUE 7:0 WPUE3 INLVLE3 ... 0x1F64 0x1F65 0x1F66 ... Reserved 0x1F67 0x1F68 INLVLE 7:0 0x1F69 IOCEP 7:0 IOCEP3 0x1F6A IOCEN 7:0 IOCEN3 0x1F6B IOCEF 7:0 IOCEF3 0x1F6C ... Reserved 0x1F7F 0x1F80 INDF0 7:0 INDF0[7:0] 0x1F81 INDF1 7:0 INDF1[7:0] 0x1F82 PCL 7:0 0x1F83 STATUS 7:0 0x1F84 FSR0 PCL[7:0] TO PD 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 0x1F86 FSR1 0x1F88 BSR 7:0 0x1F89 WREG 7:0 0x1F8A PCLATH 7:0 0x1F8B INTCON 7:0 Z DC C BSR[5:0] WREG[7:0] PCLATH[6:0] GIE PEIE INTEDG 0x1F8C ... Reserved 0x1FE3 0x1FE4 STATUS_SHAD 7:0 0x1FE5 WREG_SHAD 7:0 0x1FE6 BSR_SHAD 7:0 0x1FE7 PCLATH_SHAD 7:0 0x1FE8 FSR0_SHAD 0x1FEA FSR1_SHAD 0x1FEC Reserved 0x1FED STKPTR 0x1FEE TOS TO PD DC C WREG[7:0] BSR[5:0] PCLATH[6:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 FSRL[7:0] 15:8 FSRH[7:0] 7:0 STKPTR[4:0] 7:0 TOSL[7:0] 15:8 TOSH[7:0] © 2018 Microchip Technology Inc. Z Datasheet Preliminary DS40002038B-page 674 PIC16(L)F18455/56 In-Circuit Serial Programming™ (ICSP™) 39. In-Circuit Serial Programming™ (ICSP™) ICSP™ programming allows customers to manufacture circuit boards with unprogrammed devices. Programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. Five pins are needed for ICSP™ programming: • • • • • ICSPCLK ICSPDAT MCLR/VPP VDD VSS In Program/Verify mode the program memory, User IDs and the Configuration Words are programmed through serial communications. The ICSPDAT pin is a bidirectional I/O used for transferring the serial data and the ICSPCLK pin is the clock input. For more information on ICSP™ refer to the “ Memory Programming Specification” (DS40001970). 39.1 High-Voltage Programming Entry Mode The device is placed into High-Voltage Programming Entry mode by holding the ICSPCLK and ICSPDAT pins low then raising the voltage on MCLR/VPP to VIHH. 39.2 Low-Voltage Programming Entry Mode ® The Low-Voltage Programming Entry mode allows the PIC Flash MCUs to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Words is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. Entry into the Low-Voltage Programming Entry mode requires the following steps: 1. 2. MCLR is brought to Vil. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. If low-voltage programming is enabled (LVP = 1), the MCLR Reset function is automatically enabled and cannot be disabled. See the MCLR Section for more information. The LVP bit can only be reprogrammed to ‘0’ by using the High-Voltage Programming mode. Related Links 8.4 MCLR Reset 39.3 Common Programming Interfaces Connection to a target device is typically done through an ICSP™ header. A commonly found connector on development tools is the RJ-11 in the 6P6C (6-pin, 6-connector) configuration. See Figure 39-1. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 675 PIC16(L)F18455/56 In-Circuit Serial Programming™ (ICSP™) Figure 39-1. ICD RJ-11 Style Connector Interface VDD ICSPDAT NC 2 4 6 ICSPCLK 1 3 5 Target VPP/MCLR VSS PC Board Bottom Side Pin Description* 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT 5 = ICSPCLK 6 = No Connect Another connector often found in use with the PICkit™ programmers is a standard 6-pin header with 0.1 inch spacing. Refer to Figure 39-2. For additional interface recommendations, refer to the specific device programmer manual prior to PCB design. It is recommended that isolation devices be used to separate the programming pins from other circuitry. The type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. See Figure 39-3 for more information. Figure 39-2. PICkit™ Programmer Style Connector Interface Pin 1 Indicator 1 2 3 4 5 6 Pin Description1 1 = VPP/MCLR 2 = VDD Target 3 = VSS (ground) 4 = ICSPDAT © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 676 PIC16(L)F18455/56 In-Circuit Serial Programming™ (ICSP™) 5 = ICSPCLK 6 = No Connect Note:  1. Note:  The 6-pin header (0.100" spacing) accepts 0.025" square pins. Figure 39-3. Typical Connection for ICSP™ Programming External Programming Signals Device to be Programmed VDD VDD VDD VPP MCLR/VPP VSS VSS Data ICSPDAT Clock ICSPCLK * * * To Normal Connections * Isolation devices (as required). © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 677 PIC16(L)F18455/56 Instruction Set Summary 40. Instruction Set Summary PIC16(L)F18455/56 devices incorporate the standard set of 50 PIC16 core instructions. Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The opcodes are broken into three broad categories: • Byte Oriented • Bit Oriented • Literal and Control The literal and control category contains the most varied instruction word format. ™ The Instruction Set table lists the instructions recognized by the MPASM assembler. All instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: • Subroutine entry takes two cycles (CALL, CALLW) • Returns from interrupts or subroutines take two cycles (RETURN, RETLW, RETFIE) • Program branching takes two cycles (GOTO, BRA, BRW, BTFSS, BTFSC, DECFSZ, INCSFZ) • One additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. One instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 MHz, this gives a nominal instruction execution rate of 1 MHz. All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a hexadecimal digit. 40.1 Read-Modify-Write Operations Any WRITE instruction that specifies a file register as part of the instruction performs a Read-Modify-Write (R-M-W) operation. The register is read, the data is modified, and the result is stored according to either the working (W) register, or the originating file register, depending on the state of the destination designator 'd' (see the table below for more information). A read operation is performed on a register even if the instruction writes to that register. Table 40-1. Opcode Field Descriptions Field f Description Register file address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit file register k Literal field, constant data or label x Don’t care location (= 0 or 1). The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. d Destination select; d = 0: store result in W, d = 1: store result in file register f. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 678 PIC16(L)F18455/56 Instruction Set Summary Field n mm Description FSR or INDF number. (0-1) Prepost increment-decrement mode selection Table 40-2. Abbreviation Descriptions Field Description PC Program Counter TO Time-Out bit C Carry bit DC Digit Carry bit Z Zero bit PD 40.2 Power-Down bit Standard Instruction Set Table 40-3. Instruction Set Mnemonic, Operands Description Cycles 14-Bit Opcode MSb Status Notes Affected LSb BYTE-ORIENTED OPERATIONS ADDWF f, d ADDWFC f, d Add WREG and f 1 00 0111 dfff ffff C, DC, Z 2 Add WREG and CARRY bit to f 1 11 1101 dfff ffff C, DC, Z 2 ANDWF f, d AND WREG with f 1 00 0101 dfff ffff Z 2 ASRF f, d Arithmetic Right Shift 1 11 0111 dfff ffff C, Z 2 LSLF f, d Logical Left Shift 1 11 0101 dfff ffff C, Z 2 LSRF f, d Logical Right Shift 1 11 0110 dfff ffff C, Z 2 CLRF f Clear f 1 00 0001 lfff ffff Z 2 CLRW – Clear WREG 1 00 0001 0000 00xx Z COMF f, d Complement f 1 00 1001 dfff ffff Z 2 DECF f, d Decrement f 1 00 0011 dfff ffff Z 2 INCF f, d Increment f 1 00 1010 dfff ffff Z 2 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 679 PIC16(L)F18455/56 Instruction Set Summary Mnemonic, Operands Description Cycles 14-Bit Opcode MSb Status Notes Affected LSb IORWF f, d Inclusive OR WREG with f 1 00 0100 dfff ffff Z 2 MOVF f, d Move f 1 00 1000 dfff ffff Z 2 MOVWF f Move WREG to f 1 00 0000 1fff ffff None 2 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 2 SUBWF f, d Subtract WREG from f 1 00 0010 dfff ffff C, DC, Z 2 Subtract WREG from f with borrow 1 11 1011 dfff ffff C, DC, Z 2 SUBWFB f, d SWAPF f, d Swap nibbles in f 1 00 1110 dfff ffff None 2 XORWF f, d Exclusive OR WREG with f 1 00 0110 dfff ffff Z 2 BYTE ORIENTED SKIP OPERATIONS DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff None 1, 2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff None 1, 2 BCF f, b Bit Clear f 1 01 00bb bfff ffff None 2 BSF f, b Bit Set f 1 01 01bb bfff ffff None 2 BIT-ORIENTED FILE REGISTER OPERATIONS BIT-ORIENTED SKIP OPERATIONS BTFSC f, b Bit Test f, Skip if Clear 1(2) 01 10bb bfff ffff None 1, 2 BTFSS f, b Bit Test f, Skip if Set 1(2) 1010 11bb bfff ffff None 1, 2 LITERAL OPERATIONS ADDLW k Add literal and WREG 1 11 1110 kkkk kkkk C, DC, Z ANDLW k AND literal with WREG 1 11 1001 kkkk kkkk Z IORLW k Inclusive OR literal with WREG 1 11 1000 kkkk kkkk Z MOVLB k Move literal to BSR 1 00 000 0k kkkk None MOVLP k Move literal to PCLATH 1 11 0001 1kkk kkkk None © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 680 PIC16(L)F18455/56 Instruction Set Summary Mnemonic, Operands Description Cycles 14-Bit Opcode MSb Status Notes Affected LSb MOVLW k Move literal to W 1 11 0000 kkkk kkkk None SUBLW k Subtract W from literal 1 11 1100 kkkk kkkk C, DC, Z XORLW k Exclusive OR literal with W 1 11 1010 kkkk kkkk Z CONTROL OPERATIONS BRA k Relative Branch 2 11 001k kkkk kkkk None BRW — Relative Branch with WREG 2 00 0000 0000 1011 None CALL k Call Subroutine 2 10 0kkk kkkk kkkk None CALLW — Call Subroutine with WREG 2 00 0000 0000 1010 None GOTO k Go to address 2 10 1kkk kkkk kkkk None RETFIE k Return from interrupt 2 00 0000 0000 1001 None RETLW k Return with literal in WREG 2 11 0100 kkkk kkkk None RETURN — Return from Subroutine 2 00 0000 0000 1000 None INHERENT OPERATIONS CLRWDT — Clear Watchdog Timer 1 00 0000 0110 0100 TO, PD NOP — No Operation 1 00 0000 0000 0000 None RESET — Software device Reset 1 00 0000 0000 0001 None SLEEP — Go into Standby or Idle mode 1 00 0000 0110 0011 TO, PD TRIS f Load TRIS register with WREG 1 00 0000 0110 0fff None C-COMPILER OPTIMIZED ADDFSR n, k MOVIW MOVWI Add Literal k to FSRn n, mm Move Indirect FSRn to WREG with pre/ post inc/dec modifier, mm k[n] Move INDFn to WREG, Indexed Indirect. n, mm Move WREG to Indirect FSRn with pre/ post inc/dec modifier, mm k[n] Move WREG to INDFn, Indexed Indirect. 1 © 2018 Microchip Technology Inc. 1 11 0001 0nkk kkkk None 1 00 0000 0001 0nmm Z 1 11 1111 0nkk kkkk Z 1 00 0000 0001 1nmm None 2, 3 11 1111 1nkk kkkk None 2 Datasheet Preliminary 2, 3 2 DS40002038B-page 681 PIC16(L)F18455/56 Instruction Set Summary Note:  1. If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 2. 3. 40.2.1 If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one additional instruction cycle. Details on MOVIW and MOVWI instruction descriptions are available in the next section. Standard Instruction Set ADDFSR Add Literal to FSRn Syntax: [ label ] ADDFSR FSRn, k Operands: -32 ≤ k ≤ 31; n ∈ [ 0, 1] Operation: FSR(n) + k → FSR(n) Status Affected: None Description: The signed 6-bit literal ‘k’ is added to the contents of the FSRnH:FSRnL register pair. FSRn is limited to the range 0000h-FFFFh. Moving beyond these bounds will cause the FSR to wrap-around. ADDLW ADD literal to W Syntax: [ label ] ADDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W. ADDWF ADD W to f Syntax: [ label ] ADDWF f, d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) + (f) → dest Status Affected: C, DC, Z Description: Add the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 682 PIC16(L)F18455/56 Instruction Set Summary ADDWFC ADD W and CARRY bit to f Syntax: [ label ] ADDWFC f {,d} Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) + (f) + (C) → dest Status Affected: C, DC, Z Description: Add W, the Carry flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’. ANDLW AND literal with W Syntax: [ label ] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. k → (W) Status Affected: Z Description: The contents of W are AND’ed with the 8-bit literal ‘k’. The result is placed in W. ANDWF AND W with f Syntax: [ label ] ANDWF f, d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .AND. (f) → dest Status Affected: Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. ASRF Arithmetic Right Shift Syntax: [ label ] ASRF f, d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] (f) → dest Operation: (f) → dest (f) → C © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 683 PIC16(L)F18455/56 Instruction Set Summary ASRF Arithmetic Right Shift Status Affected: C, Z The contents of register ‘f’ are shifted one bit to the right through the Carry flag. The MSb remains unchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. Description: Register f → C BCF Bit Clear f Syntax: [ label ] BCF f, b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 0 → f Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared. BRA Relative Branch Syntax: [ label ] BRA label [ label ] BRA $+k Operands: -256 ≤ label - PC + ≤ 255 -256 ≤ k ≤ 255 Operation: (PC) + 1 + k → PC Status Affected: None Description: Add the signed 9-bit literal ‘k’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + k. This instruction is a 2-cycle instruction. This branch has a limited range. BRW Relative Branch with W Syntax: [ label ] BRW Operands: None Operation: (PC) + (W) → PC © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 684 PIC16(L)F18455/56 Instruction Set Summary BRW Relative Branch with W Status Affected: None Description: Add the contents of W (unsigned) to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 1 + (W). This instruction is a 2-cycle instruction. BSF Bit Set f Syntax: [ label ] BSF f, b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: 1 → (f) Status Affected: None Description: Bit ‘b’ in register ‘f’ is set. BTFSC Bit Test File, Skip if Clear Syntax: [ label ] BTFSC f, b Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: skip if (f) = 0 Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘1’, the next instruction is executed. If bit ‘b’, in register ‘f’, is ‘0’, the next instruction is discarded, and a NOP is executed instead, making this a 2-cycle instruction. BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSS f, b Operands: 0 ≤ f ≤ 127 0≤b k Description C = 1, W ≤ k DC = 0, W[3:0] > k[3:0] DC = 1, W[3:0] ≤ k[3:0] SUBWF Subtract W from f Syntax: [ label ] SUBWF f, d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - (W) → (dest) Status Affected: C, DC, Z Description Subtract (2’s complement method) W register from register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f. C =0, W > f © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 698 PIC16(L)F18455/56 Instruction Set Summary SUBWF Subtract W from f C = 1, W ≤ f DC = 0, W[3:0] > f[3:0] DC = 1, W[3:0] ≤ f[3:0] SUBFWB Subtract W from f with Borrow Syntax: [ label ] SUBFWB f {,d} Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) – (f) – (B) → dest Status Affected: C, DC, Z Description: Subtract W and the BORROW flag (CARRY) from register ‘f’ (2’s complement method). If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in register ‘f’. SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f, d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) → dest, (f) → dest Status Affected: None Description: The upper and lower nibbles of register ‘f’ are exchanged. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in register ‘f’ (default). TRIS Load TRIS Register with W Syntax: [ label ] TRIS f Operands: 5≤f≤7 Operation: (W) → TRIS register ‘f’ Status Affected: None Description: Move data from W register to TRIS register. When ‘f’ = 5, TRISA is loaded. When ‘f’ = 6, TRISB is loaded. When ‘f’ = 7, TRISC is loaded. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 699 PIC16(L)F18455/56 Instruction Set Summary XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Description: The contents of W are XORed with the 8-bit literal ‘k’. The result is placed in W. XORWF Exclusive OR W with f Syntax: [ label ] XORWF f, d Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) .XOR. (f) → dest Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 700 PIC16(L)F18455/56 Development Support 41. Development Support ® ® The PIC microcontrollers (MCU) and dsPIC digital signal controllers (DSC) are supported with a full range of software and hardware development tools: • • • • • • • • 41.1 Integrated Development Environment ® – MPLAB X IDE Software Compilers/Assemblers/Linkers – MPLAB XC Compiler – MPASMTM Assembler – MPLINKTM Object Linker/ MPLIBTM Object Librarian – MPLAB Assembler/Linker/Librarian for Various Device Families Simulators – MPLAB X SIM Software Simulator Emulators – MPLAB REAL ICE™ In-Circuit Emulator In-Circuit Debuggers/Programmers – MPLAB ICD 3 – PICkit™ 3 Device Programmers – MPLAB PM3 Device Programmer Low-Cost Demonstration/Development Boards, Evaluation Kits and Starter Kits Third-party development tools MPLAB X Integrated Development Environment Software The MPLAB X IDE is a single, unified graphical user interface for Microchip and third-party software, and ® ® hardware development tool that runs on Windows , Linux and Mac OS X. Based on the NetBeans IDE, MPLAB X IDE is an entirely new IDE with a host of free software components and plug-ins for highperformance application development and debugging. Moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. With complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, MPLAB X IDE is flexible and friendly enough for new users. With the ability to support multiple tools on multiple projects with simultaneous debugging, MPLAB X IDE is also suitable for the needs of experienced users. Feature-Rich Editor: • • • • Color syntax highlighting Smart code completion makes suggestions and provides hints as you type Automatic code formatting based on user-defined rules Live parsing User-Friendly, Customizable Interface: © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 701 PIC16(L)F18455/56 Development Support • • Fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. Call graph window Project-Based Workspaces: • • • • Multiple projects Multiple tools Multiple configurations Simultaneous debugging sessions File History and Bug Tracking: • • 41.2 Local file history feature Built-in support for Bugzilla issue tracker MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE. The free MPLAB XC Compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. MPLAB XC Compilers include an assembler, linker and utilities. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. MPLAB XC Compiler uses the assembler to produce its object file. Notable features of the assembler include: • • • • • • 41.3 Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. ® The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code, and COFF files for debugging. The MPASM Assembler features include: • • Integration into MPLAB X IDE projects User-defined macros to streamline assembly code © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 702 PIC16(L)F18455/56 Development Support • • 41.4 Conditional assembly for multipurpose source files Directives that allow complete control over the assembly process MPLINK Object Linker/MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • • • 41.5 Efficient linking of single libraries instead of many smaller files Enhanced code maintainability by grouping related modules together Flexible creation of libraries with easy module listing, replacement, deletion and extraction MPLAB Assembler, Linker and Librarian for Various Device Families MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC DSC devices. MPLAB XC Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • 41.6 Support for the entire device instruction set Support for fixed-point and floating-point data Command-line interface Rich directive set Flexible macro language MPLAB X IDE compatibility MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB X SIM Software Simulator fully supports symbolic debugging using the MPLAB XC Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 703 PIC16(L)F18455/56 Development Support 41.7 MPLAB REAL ICE In-Circuit Emulator System The MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs all 8, 16 and 32-bit MCU, and DSC devices with the easy-to-use, powerful graphical user interface of the MPLAB X IDE. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ-11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB X IDE. MPLAB REAL ICE offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 41.8 MPLAB ICD 3 In-Circuit Debugger System The MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost-effective, high-speed hardware debugger/programmer for Microchip Flash DSC and MCU devices. It debugs and programs PIC Flash microcontrollers and dsPIC DSCs with the powerful, yet easy-to-use graphical user interface of the MPLAB IDE. The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a highspeed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 41.9 PICkit 3 In-Circuit Debugger/Programmer The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB IDE. The MPLAB PICkit 3 is connected to the design engineer’s PC using a full-speed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the Reset line to implement in-circuit debugging and In-Circuit Serial Programming™ (ICSP™). 41.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at Vddmin and Vddmax for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages, and a modular, detachable socket assembly to support various package types. The ICSP cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an MMC card for file storage and data applications. 41.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 704 PIC16(L)F18455/56 Development Support areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, ® Microchip has a line of evaluation kits and demonstration software for analog filter design, KeeLoq ® ® security ICs, CAN, IrDA , PowerSmart battery management, SEEVAL evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 41.12 Third-Party Development Tools Microchip also offers a great collection of tools from third-party vendors. These tools are carefully selected to offer good value and unique functionality. • • • • • Device Programmers and Gang Programmers from companies, such as SoftLog and CCS Software Tools from companies, such as Gimpel and Trace Systems Protocol Analyzers from companies, such as Saleae and Total Phase ® Demonstration Boards from companies, such as MikroElektronika, Digilent and Olimex ® Embedded Ethernet Solutions from companies, such as EZ Web Lynx, WIZnet and IPLogika © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 705 PIC16(L)F18455/56 Electrical Specifications 42. Electrical Specifications 42.1 Absolute Maximum Ratings(†) Parameter Ambient temperature under bias Storage temperature Voltage on pins with respect to VSS • Rating -40°C to +125°C -65°C to +150°C on VDD pin: PIC16LF18455/56 -0.3V to +4.0V PIC16F18455/56 -0.3V to +6.5V • on MCLR pin: -0.3V to +9.0V • on all other pins: -0.3V to (VDD + 0.3V) Maximum current • on VSS pin(1) • on VDD pin(1) • on any standard I/O pin -40°C ≤ TA ≤ +85°C 85°C < TA ≤ +125°C -40°C ≤ TA ≤ +85°C 85°C < TA ≤ +125°C 250 mA 120 mA 250 mA 85 mA ±50 mA Clamp current, IK (VPIN < 0 or VPIN > VDD) Total power dissipation(2) ±20 mA 800 mW Important:  1. Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be limited by the device package power dissipation characterizations, see Thermal Characteristics to calculate device specifications. 2. Power dissipation is calculated as follows: PDIS = VDD x {IDD - Σ IOH} + Σ {(VDD - VOH) x IOH} + Σ (VOI x IOL) NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for extended periods may affect device reliability. 42.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: © 2018 Microchip Technology Inc. VDDMIN ≤ VDD ≤ VDDMAX Datasheet Preliminary DS40002038B-page 706 PIC16(L)F18455/56 Electrical Specifications TA_MIN ≤ TA ≤ TA_MAX Operating Temperature: Parameter Ratings VDD — Operating Supply Voltage(1) VDDMIN (FOSC ≤ 16 MHz) PIC16LF18455/56 VDDMIN (FOSC ≤ 32 MHz) VDDMAX VDDMIN (FOSC ≤ 16 MHz) PIC16F18455/56 VDDMIN (FOSC ≤ 32 MHz) VDDMAX TA — Operating Ambient Temperature Range TA_MIN Industrial Temperature TA_MAX TA_MIN Extended Temperature TA_MAX Note:  1. See Parameter D002, DC Characteristics: Supply Voltage. +1.8V +2.5V +3.6V +2.3V +2.5V +5.5V -40°C +85°C -40°C +125°C Figure 42-1. Voltage Frequency Graph, -40°C ≤ TA≤ +125°C, for PIC16F18455/56 only Rev. 30-000069C 10/27/2016 VDD (V) 5.5 2.5 2.3 0 4 10 16 32 Frequency (MHz) Note:  1. The shaded region indicates the permissible combinations of voltage and frequency. 2. Refer to 42.4.1 External Clock/Oscillator Timing Requirements for each Oscillator mode’s supported frequencies. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 707 PIC16(L)F18455/56 Electrical Specifications Figure 42-2. Voltage Frequency Graph, -40°C ≤ TA≤ +125°C, for PIC16LF18455/56 Devices only VDD (V) Rev. 30-000070B 10/27/2017 3.6 2.5 1.8 4 0 10 16 32 Frequency (MHz) Note:  1. The shaded region indicates the permissible combinations of voltage and frequency. 2. Refer to 42.4.1 External Clock/Oscillator Timing Requirements for each Oscillator mode’s supported frequencies. Related Links 42.3.1 Supply Voltage 42.3 DC Characteristics 42.3.1 Supply Voltage Table 42-1.  PIC16LF18455/56 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions 1.8 — 3.6 V FOSC ≤ 16 MHz 2.5 — 3.6 V FOSC > 16 MHz Supply Voltage D002 VDD RAM Data Retention(1) © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 708 PIC16(L)F18455/56 Electrical Specifications PIC16LF18455/56 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. D003 VDR Characteristic Min. Typ.† Max. Units Conditions 1.5 — — V Device in Sleep mode — 1.6 — V BOR or LPBOR disabled(3) — 0.8 — V BOR or LPBOR disabled(3) — V/ms BOR or LPBOR disabled(3) Power-on Reset Release Voltage(2) D004 VPOR Power-on Reset Rearm Voltage(2) D005 VPORR VDD Rise Rate to ensure internal Power-on Reset signal(2) D006 SVDD 0.05 — † - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2. See the following figure, POR and POR REARM with Slow Rising VDD. 3. Please see 42.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications for BOR and LPBOR trip point information. PIC16F18455/56 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions 2.3 — 5.5 V FOSC ≤ 16 MHz 2.5 — 5.5 V FOSC > 16 MHz 1.7 — — V Device in Sleep mode — 1.6 — V BOR or LPBOR disabled(3) Supply Voltage D002 VDD RAM Data Retention(1) D003 VDR Power-on Reset Release Voltage(2) D004 VPOR Power-on Reset Rearm Voltage(2) © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 709 PIC16(L)F18455/56 Electrical Specifications PIC16F18455/56 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. D005 VPORR Characteristic Min. Typ.† Max. Units Conditions — 1.5 — V BOR or LPBOR disabled(3) — V/ms BOR or LPBOR disabled(3) VDD Rise Rate to ensure internal Power-on Reset signal(2) D006 SVDD — 0.05 † - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. This is the limit to which VDD can be lowered in Sleep mode without losing RAM data. 2. See the following figure, POR and POR REARM with Slow Rising VDD. 3. Please see 42.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power Brown-Out Reset Specifications for BOR and LPBOR trip point information. Figure 42-3. POR and POR Rearm with Slow Rising VDD Rev. 30-000071A 4/6/2017 VDD VPOR VPORR SVDD VSS NPOR(1) POR REARM VSS TVLOW(3) TPOR(2) Note:  1. When NPOR is low, the device is held in Reset.  2. TPOR 1 μs typical. 3. TVLOW 2.7 μs typical. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 710 PIC16(L)F18455/56 Electrical Specifications 42.3.2 Supply Current (IDD)(1,2,4) Table 42-2.  PIC16LF18455/56 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics D100 IDDXT4 D101 Conditions Min. Typ.† Max. Units XT = 4 MHz — 556.5 845.3 μA 3.0V IDDHFO16 HFINTOSC = 16 MHz — 2.1 3.05 mA 3.0V D102 IDDHFOPLL HFINTOSC = 32 MHz — 3.8 5.8 mA 3.0V D103 IDDHSPLL32 HS+PLL = 32 MHz — 3.8 5.8 mA 3.0V IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 1.68 2.1 mA 3.0V IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.47 — mA 3.0V D104 D105 VDD Note † - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled. 2. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3. IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (see CPUDOZE register). 4. PMD bits are all in the default state, no modules are disabled. PIC16F18455/56 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics D100 IDDXT4 D101 IDDHFO16 Conditions Min. Typ.† Max. Units XT = 4 MHz — 588 887.25 μA 3.0V HFINTOSC = 16 MHz — 2.3 3.15 mA 3.0V © 2018 Microchip Technology Inc. Datasheet Preliminary VDD Note DS40002038B-page 711 PIC16(L)F18455/56 Electrical Specifications PIC16F18455/56 only Standard Operating Conditions (unless otherwise stated) Conditions Param. No. Sym. Device Characteristics Min. Typ.† Max. Units D102 IDDHFOPLL HFINTOSC = 32 MHz — 3.9 5.9 mA 3.0V D103 IDDHSPLL32 HS+PLL = 32 MHz — 3.9 6.0 mA 3.0V D104 IDDIDLE IDLE mode, HFINTOSC = 16 MHz — 1.9 2.2 mA 3.0V IDDDOZE(3) DOZE mode, HFINTOSC = 16 MHz, Doze Ratio = 16 — 1.7 — mA 3.0V D105 VDD Note † - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail-to-rail; all I/O pins are outputs driven low; MCLR = VDD; WDT disabled. 2. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3. IDDDOZE = [IDDIDLE*(N-1)/N] + IDDHFO16/N where N = DOZE Ratio (see CPUDOZE register). 4. PMD bits are all in the default state, no modules are disabled. Related Links 11.5.2 CPUDOZE 42.3.3 Power-Down Current (IPD)(1,2) Table 42-3.  PIC16LF18455/56 only Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics D200 IPD D201 IPD_WDT Conditions Min. Typ.† Max. +85°C Max. +125°C Units IPD Base — 0.06 2 9 μA 3.0V Low-Frequency Internal Oscillator/WDT — 0.8 3.0 11 μA 3.0V © 2018 Microchip Technology Inc. Datasheet Preliminary VDD Note DS40002038B-page 712 PIC16(L)F18455/56 Electrical Specifications PIC16LF18455/56 only Standard Operating Conditions (unless otherwise stated) Conditions Param. No. Sym. Device Characteristics Min. Typ.† Max. +85°C Max. +125°C Units D202 IPD_SOSC Secondary Oscillator (SOSC) — 0.6 5 11 μA 3.0V D203 IPD_FVR FVR — 33 74 76 μA 3.0V D204 IPD_BOR Brown-out Reset (BOR) — 10 17 19 μA 3.0V D205 IPD_LPBOR Low-Power Brown-out Reset (LPBOR) — 0.5 3.0 10 μA 3.0V D207 IPD_ADCA ADC - Nonconverting — 0.06 2 9 μA 3.0V IPD_CMP Comparator — D208 VDD Note ADC not converting (4) 30 48 56 μA 3.0V † - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The peripheral ∆ current can be determined by subtracting the base IDD or IPDcurrent from this limit. Max. values should be used when calculating total current consumption. 2. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to VSS. 3. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available. 4. ADC clock source is FRC. PIC16F18455/56 only Standard Operating Conditions (unless otherwise stated), VREGPM = 1 Param. No. Sym. Device Characteristics D200 D200A D201 IPD IPD Base IPD_WDT Low-Frequency Internal Oscillator/WDT © 2018 Microchip Technology Inc. Conditions Min. Typ.† Max. +85°C Max. +125°C Units — 0.4 3 12 μA 3.0V — 18 25 30 μA 3.0V — 0.9 4 14 μA 3.0V Datasheet Preliminary VDD Note VREGPM = 0 DS40002038B-page 713 PIC16(L)F18455/56 Electrical Specifications PIC16F18455/56 only Standard Operating Conditions (unless otherwise stated), VREGPM = 1 Conditions Param. No. Sym. Device Characteristics Min. Typ.† Max. +85°C Max. +125°C Units D202 IPD_SOSC Secondary Oscillator (SOSC) — 0.8 5.5 13 μA 3.0V D203 IPD_FVR FVR — 28 70 75 μA 3.0V D204 IPD_BOR Brown-out Reset (BOR) — 14 18 20 μA 3.0V D207 IPD_ADCA ADC - Nonconverting — 0.4 3 12 μA 3.0V IPD_CMP Comparator — D208 VDD Note ADC not converting (4) 33 49 57 μA 3.0V † - Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. The peripheral current is the sum of the base IDD and the additional current consumed when this peripheral is enabled. The peripheral ∆ current can be determined by subtracting the base IDD or IPDcurrent from this limit. Max. values should be used when calculating total current consumption. 2. The power-down current in Sleep mode does not depend on the oscillator type. Power-down current is measured with the part in Sleep mode with all I/O pins in high-impedance state and tied to VSS. 3. 4. All peripheral currents listed are on a per-peripheral basis if more than one instance of a peripheral is available. ADC clock source is FRC. 42.3.4 I/O Ports Table 42-4.  Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics Min. Typ.† Max. Units Conditions — — 0.8 V 4.5V≤VDD≤5.5V — — 0.15 VDD V 1.8V≤VDD≤4.5V 2.0V≤VDD≤5.5V Input Low Voltage VIL D300 I/O PORT: • with TTL buffer D301 D302 • with Schmitt Trigger buffer — — 0.2 VDD V D303 • with I2C levels — — 0.3 VDD V D304 • with SMBus levels — — 0.8 V © 2018 Microchip Technology Inc. Datasheet Preliminary 2.7V≤VDD≤5.5V DS40002038B-page 714 PIC16(L)F18455/56 Electrical Specifications Standard Operating Conditions (unless otherwise stated) Param. No. Sym. D305 Device Characteristics MCLR Min. Typ.† Max. Units Conditions — — 0.2 VDD V 2.0 — — V 4.5V≤VDD≤5.5V 0.25 VDD +0.8 — — V 1.8V≤VDD≤4.5V 2.0V≤VDD≤5.5V Input High Voltage VIH I/O PORT: D320 • with TTL buffer D321 D322 • with Schmitt Trigger buffer 0.8VDD — — V D323 • with I2C levels 0.7 VDD — — V D324 • with SMBus levels 2.1 — — V 0.7 VDD — — V — ±5 ±125 nA VSS≤VPIN≤VDD, Pin at high-impedance, 85°C — ±5 ±1000 nA VSS≤VPIN≤VDD, Pin at high-impedance, 125°C — ±50 ±200 nA VSS≤VPIN≤VDD, Pin at high-impedance, 85°C 25 120 200 μA VDD=3.0V, VPIN=VSS — — 0.6 V IOL = 8 mA, VDD = 5.0V IOL = 6 mA, VDD = 3.3V D325 MCLR 2.7V≤VDD≤5.5V Input Leakage Current(1) D340 IIL I/O PORTS D341 MCLR(2) D342 Weak Pull-up Current D350 IPUR Output Low Voltage D360 VOL Standard I/O PORTS IOL = 1.8 mA, VDD = 1.8V D360A High-Drive I/O PORTS — — — 0.6 0.6 — V V I OL — 0.6 — V = 10 mA, V DD = 2.3V, HIDCx = 1 IOL = 32 mA, VDD = 3.0V, HIDCx = 1 IOL = 51 mA, VDD = 5.0V, HIDCx = 1 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 715 PIC16(L)F18455/56 Electrical Specifications Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Device Characteristics Min. Typ.† Max. Units VDD-0.7 — — V Conditions Output High Voltage D370 VOH Standard I/O PORTS IOH = 3.5 mA, VDD = 5.0V IOH = 3 mA, VDD = 3.3V IOH = 1 mA, VDD = 1.8V D370A High-Drive I/O PORTS VDD-0.7 — VDD-0.7 — — V V VDD-0.7 — V IOH = 10 mA, VDD = 2.3V, HIDCx = 1 IOH = 37 mA, VDD = 3.0V, HIDCx = 1 IOH = 54 mA, VDD = 5.0V, HIDCx = 1 All I/O Pins D380 CIO — 5 50 pF † - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Negative current is defined as current sourced by the pin. 2. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 42.3.5 Memory Programming Specifications Table 42-5.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Device Characteristics Min. Typ† Max. Units Conditions High Voltage Entry Programming Mode Specifications MEM01 VIHH Voltage on MCLR/VPP pin to enter programming mode 8 — 9 V (Note 2, Note 3) MEM02 IPPGM Current on MCLR/VPP pin during programming mode — 1 — mA (Note 2) — — — V (Note 4) Programming Mode Specifications MEM10 VBE VDD for Bulk Erase © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 716 PIC16(L)F18455/56 Electrical Specifications Standard Operating Conditions (unless otherwise stated) Param No. MEM11 Sym. IDDPGM Device Characteristics Supply Current during Programming operation Min. Typ† Max. Units — — 10 mA 100k — — E/W Conditions Data EEPROM Memory Specifications MEM20 ED DataEE Byte Endurance MEM21 TD_RET Characteristic Retention MEM22 MEM23 MEM24 ND_REF VD_RW TD_BEW Year Provided no other specifications are violated — 40 Total Erase/Write Cycles before Refresh — — VDD for Read or Erase/Write operation VDDMIN — VDDMAX V — 4.0 5.0 ms 10k — — E/W -40°C≤Ta≤ +85°C (Note 1) Provided no other specifications are violated Byte Erase and Write Cycle Time — -40°C≤TA≤ +85°C 100k E/W Program Flash Memory Specifications MEM30 MEM32 EP TP_RET Flash Memory Cell Endurance Characteristic Retention — 40 — Year MEM33 VP_RD VDD for Read operation VDDMIN — VDDMAX V MEM34 VP_REW VDD for Row Erase or Write operation VDDMIN — VDDMAX V MEM35 TP_REW Self-Timed Row Erase or Self-Timed Write — 2.0 2.5 ms † - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 717 PIC16(L)F18455/56 Electrical Specifications Standard Operating Conditions (unless otherwise stated) Param No. 1. 2. 3. 4. Sym. Device Characteristics Min. Typ† Max. Units Conditions Flash Memory Cell Endurance for the Flash memory is defined as: One Row Erase operation and one Self-Timed Write. Required only if CONFIG4, bit LVP is disabled. ® The MPLAB ICD2 does not support variable VPP output. Circuitry to limit the ICD2 VPP voltage must be placed between the ICD2 and target system when programming or debugging with the ICD2. Refer to the "PIC16(L)F184XX Memory Programming Specification" document for description. Related Links 4.7.4 CONFIG4 42.3.6 Thermal Characteristics Table 42-6.  Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +125°C Param No. Sym. TH01 TH02 θJA θJC Characteristic Typ. Units Conditions Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case 55 °C/W 28-pin SPDIP package 74 °C/W 28-pin SOIC package 67.1 °C/W 28-pin SSOP package — °C/W 28-pin VQFN 4x4 mm package 36 °C/W 28-pin SPDIP package 19 °C/W 28-pin SOIC package 23.9 °C/W 28-pin SSOP package — °C/W 28-pin VQFN 4x4 mm package TH03 TJMAX Maximum Junction Temperature — °C TJMAX (2) = TAMAX + (PDMAX x θJA) TH04 PD Power Dissipation — W PD = PINTERNAL+PI/O TH05 PINTERNAL Internal Power Dissipation — W PINTERNAL = IDDxVDD(1) TH06 PI/O I/O Power Dissipation — W PI/O=Σ(IOL*VOL)+Σ(IOH*(VDDVOH)) TH07 PDER Derated Power — W PDER = PDMAX (TJ-TA)/θJA(2) Note:  1. IDD is current to run the chip alone without driving any load on the output pins. 2. TA = Ambient Temperature, TJ = Junction Temperature. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 718 Filename: Title: Last Edit: First Used: Note: 42.4 PIC16(L)F18455/56 10-000133A.vsd LOAD CONDITION 8/1/2013 PIC16F1508/9 Electrical Specifications AC Characteristics Figure 42-4. Load Conditions Rev. 10-000133A 8/1/2013 Load Condition Pin CL VSS Legend: CL=50 pF for all pins 42.4.1 External Clock/Oscillator Timing Requirements Figure 42-5. Clock Timing Rev. 30-000072A 4/6/2017 Q4 Q1 Q2 Q3 Q4 Q1 CLKIN OS2 OS1 OS2 OS20 CLKOUT (CLKOUT Mode) Note:  See table below. Table 42-7.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions ECL Oscillator OS1 FECL Clock Frequency — — 500 kHz OS2 TECL_DC Clock Duty Cycle 40 — 60 % ECM Oscillator OS3 FECM Clock Frequency — — 4 MHz OS4 TECM_DC Clock Duty Cycle 40 — 60 % ECH Oscillator OS5 FECH Clock Frequency — — 32 MHz OS6 TECH_DC Clock Duty Cycle 40 — 60 % Clock Frequency — — 100 kHz LP Oscillator OS7 FLP © 2018 Microchip Technology Inc. Datasheet Preliminary Note 4 DS40002038B-page 719 PIC16(L)F18455/56 Electrical Specifications Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions Clock Frequency — — 4 MHz Note 4 Clock Frequency — — 20 MHz Note 4 Clock Frequency 32.4 32.768 33.1 kHz Note 4 (Note 2, Note 3) XT Oscillator OS8 FXT HS Oscillator OS9 FHS Secondary Oscillator OS10 FSEC System Oscillator OS20 FOSC System Clock Frequency — — 32 MHz OS21 FCY Instruction Frequency — FOSC/4 — MHz OS22 TCY Instruction Period 125 1/FCY — ns * These parameters are characterized but not tested. † - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min” values with an external clock applied to OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 2. The system clock frequency (FOSC) is selected by the “main clock switch controls” as described in the “Oscillator Module (with Fail-Safe Clock Monitor)” section. 3. The system clock frequency (FOSC) must meet the voltage requirements defined in the "Standard Operating Conditions" section. 4. LP, XT and HS oscillator modes require an appropriate crystal or resonator to be connected to the device. For clocking the device with the external square wave, one of the EC mode selections must be used. Related Links 9. Oscillator Module (with Fail-Safe Clock Monitor) 42.2 Standard Operating Conditions © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 720 PIC16(L)F18455/56 Electrical Specifications 42.4.2 Internal Oscillator Parameters(1) Table 42-8.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic OS50 FHFOSC Precision Calibrated HFINTOSC Frequency Min. Typ. † Max. Units Conditions — 4 — MHz (Note 2) 8 12 16 32 OS51 FHFOSCLP Low-Power Optimized HFINTOSC Frequency — 1 — MHz — 2 — MHz OS52 FMFOSC Internal Calibrated MFINTOSC Frequency — 500 — kHz OS53 FLFOSC Internal LFINTOSC Frequency — 31 — kHz OS54 THFOSCST HFINTOSC Wakeup from Sleep Start-up Time — 11 20 μs VREGPM=0 — 85 — μs VREGPM=1 LFINTOSC Wakeup from Sleep Start-up Time — 0.2 — ms OS56 TLFOSCST † - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. To ensure these oscillator frequency tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. 2. See the figure below. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 721  PIC16(L)F18455/56  Electrical Specifications Figure 42-6. Precision Calibrated HFINTOSC Frequency Accuracy Over Device VDD and Temperature 125 ± 5% Temperature (°C) 85 ± 3% 60 ± 2% 0 ± 5% -40 1.8 2.3 2.0 3.5 3.0 4.0 4.5 5.0 5.5 VDD (V) 42.4.3 PLL Specifications Table 42-9.   Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units PLL01 FPLLIN PLL Input Frequency Range 4 — 16 MHz PLL02 FPLLOUT PLL Output Frequency Range 16 — 32 MHz PLL03 FPLLST PLL Lock Time from Start-up — 200 — μs PLL04 FPLLJIT PLL Output Frequency Stability (Jitter) -0.25 — 0.25 % Conditions (Note 1) * - These parameters are characterized but not tested. † - Data in “Typ” column is at 5.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. The output frequency of the PLL must meet the FOSC requirements listed in Parameter D002. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 722 PIC16(L)F18455/56 Electrical Specifications 42.4.4 I/O and CLKOUT Timing Specifications Figure 42-7. CLKOUT and I/O Timing Rev. 30-000074A 4/6/2017 Cycle Write Fetch Q1 Q4 Read Execute Q2 Q3 FOSC IO2 IO1 IO10 CLKOUT IO8 IO7 IO4 IO5 I/O pin (Input) IO3 I/O pin (Output) New Value Old Value IO7, IO8 Table 42-10. I/O and CLKOUT Timing Specifications Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions IO1* TCLKOUTH CLKOUT rising edge delay (rising edge FOSC (Q1 cycle) to falling edge CLKOUT — — 70 ns IO2* TCLKOUTL CLKOUT falling edge delay (rising edge FOSC (Q3 cycle) to rising edge CLKOUT — — 72 ns IO3* TIO_VALID Port output valid time (rising edge FOSC (Q1 cycle) to port valid) — 50 70 ns IO4* TIO_SETUP Port input setup time (Setup time before rising edge FOSC – Q2 cycle) 20 — — ns IO5* TIO_HOLD Port input hold time (Hold time after rising edge FOSC – Q2 cycle) 50 — — ns IO6* TIOR_SLREN Port I/O rise time, slew rate enabled — 25 — ns VDD=3.0V IO7* TIOR_SLRDIS Port I/O rise time, slew rate disabled — 5 — ns VDD=3.0V IO8* TIOF_SLREN Port I/O fall time, slew rate enabled — 25 — ns VDD=3.0V IO9* TIOF_SLRDIS Port I/O fall time, slew rate disabled — 5 — ns VDD=3.0V IO10* TINT INT pin high or low time to trigger an interrupt 25 — — ns IO11* TIOC Interrupt-on-Change minimum high or low time to trigger interrupt 25 — — ns * - These parameters are characterized but not tested. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 723 PIC16(L)F18455/56 Electrical Specifications 42.4.5 Reset, WDT, Oscillator Start-up Timer, Power-up Timer, Brown-Out Reset and Low-Power BrownOut Reset Specifications Figure 42-8. Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Rev. 30-000075A 4/6/2017 VDD MCLR RST01 Internal POR RST04 PWRT Time-out RST05 OSC Start-up Time Internal Reset(1) Watchdog Timer Reset(1) RST03 RST02 RST02 I/O pins Note:  1. Asserted low. Figure 42-9. Brown-out Reset Timing and Characteristics Rev. 30-000076A 4/6/2017 VDD VBOR and VHYST VBOR (Device in Brown-out Reset) (Device not in Brown-out Reset) RST08 Reset (due to BOR) RST04(1) Note:  1. Only if PWRTE bit in the Configuration Word register is programmed to ‘1’; 2 ms delay if PWRTE = 0. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 724 PIC16(L)F18455/56 Electrical Specifications Table 42-11.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units RST01* TMCLR MCLR Pulse Width Low to ensure Reset 2 — — μs RST02* TIOZ I/O high-impedance from Reset detection — — 2 μs RST03 TWDT Watchdog Timer Time-out Period — 16 — ms RST04* TPWRT Power-up Timer Period — 65 — ms RST05 TOST Oscillator Start-up Timer Period(1, 2) — 1024 — TOSC RST06 VBOR Brown-out Reset Voltage 2.55 2.7 2.85 2.30 2.45 2.60(3) V V 1.80 1.90 2.05 V Conditions 1:512 Prescaler BORV=0 BORV=1(F devices only) BORV=1(LF Devices only) RST07 VBORHYS Brown-out Reset Hysteresis — 40 — mV RST08 TBORDC Brown-out Reset Response Time — 3 — μs RST09 VLPBOR Low-Power Brownout Reset Voltage 1.8 1.9 2.2 V * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. By design, the Oscillator Start-up Timer (OST) counts the first 1024 cycles, independent of frequency. 2. To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as possible. 0.1 μF and 0.01 μF values in parallel are recommended. 3. This value corresponds to VBORMAX © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 725 PIC16(L)F18455/56 Electrical Specifications 42.4.6 Temperature Indicator Requirements Table 42-12.  Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic TS01 TACQMIN Minimum ADC Acquisition Time Delay TS02 Mv Voltage Sensitivity Min. Max. Units Conditions — 25 — μs High Range — -3.684 — mV/°C TSRNG = 1 Low Range — -3.456 — mV/°C TSRNG = 0 * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 42.4.7 Analog-To-Digital Converter (ADC) Accuracy Specifications(1,2) Table 42-13.  Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C, TAD = 1μs Param No. Sym. Characteristic Min. Typ. † Max. AD01 NR AD02 Units Conditions Resolution — — 12 bit EIL Integral Error — ±0.2 ±1.0 Lsb ADCREF+=3.0V, ADCREF- = 0V AD03 EDL Differential Error — ±1.0 ±1.0 Lsb ADCREF+=3.0V, ADCREF- = 0V AD04 EOFF Offset Error — 0.5 6.5 Lsb ADCREF+=3.0V, ADCREF- = 0V AD05 EGN Gain Error — ±0.2 ±6.0 Lsb ADCREF+=3.0V, ADCREF- = 0V AD06 VADREF ADC Reference Voltage (ADREF+ - ADREF-) 1.8 — VDD V AD07 VAIN Full-Scale Range ADREF- — ADREF+ V AD08 ZAIN Recommended Impedance of Analog Voltage Source — 10 — kΩ AD09 RVREF ADC Voltage Reference Ladder Impedance — 50 — kΩ * - These parameters are characterized but not tested. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 726 PIC16(L)F18455/56 Electrical Specifications Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C, TAD = 1μs Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Total Absolute Error is the sum of the offset, gain and integral non-linearity (INL) errors. 2. The ADC conversion result never decreases with an increase in the input and has no missing codes. 42.4.8 Analog-to-Digital Converter (ADC) Conversion Timing Specifications Table 42-14.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic AD20 TAD ADC Clock Period AD21 AD22 TCNV Conversion Time(1) Min. Typ. † Max. Units Conditions 1 — 9 μs Using FOSC as the ADC clock source ADCS = 1 — 2 — μs Using FRC as the ADC clock source ADCS = 0 — 13TAD+3TCY — — Using FOSC as the ADC clock source ADCS = 1 — 16TAD+2TCY — — Using FRC as the ADC clock source ADCS = 0 AD23 TACQ Acquisition Time — 2 — μs AD24 THCD Sample and Hold Capacitor Disconnect Time — 2TAD+1TCY — — Using FOSC as the ADC clock source ADCS = 1 — 3TAD+2TCY — — Using FRC as the ADC clock source ADCS = 0 * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Does not apply for the ADCRC oscillator. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 727 PIC16(L)F18455/56 Electrical Specifications Figure 42-10. ADC Conversion Timing (ADC Clock FOSC-Based) Rev. 30-000077B 12/04/2017 BSF ADCON0, GO AD24 1 TCY AD22 Q4 11 ADC Data 10 9 8 3 2 1 0 NEW_DATA OLD_DATA ADRES 1 TCY ADIF GO Sample DONE Sampling Stopped AD23 Figure 42-11. ADC Conversion Timing (ADC Clock from ADCRC) Rev. 30-000078B 12/04/2017 BSF ADCON0, GO AD24 1 TCY AD22 Q4 AD20 ADC_clk 11 ADC Data 10 9 8 3 OLD_DATA ADRES 1 0 NEW_DATA 1 TCY ADIF GO Sample 2 DONE AD23 Sampling Stopped Note:  1. If the ADC clock source is selected as ADCRC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 728 PIC16(L)F18455/56 Electrical Specifications 42.4.9 Comparator Specifications Table 42-15.  Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions CM01 VIOFF Input Offset Voltage — ±30 — mV VICM = VDD/2 CM02 VICM Input Common Mode Range GND — VDD V CM03 CMRR Common Mode Input Rejection Ratio — 50 — dB CM04 VHYST Comparator Hysteresis 15 25 35 mV CM05 TRESP(1) Response Time, Rising Edge — 300 600 ns Response Time, Falling Edge — 220 500 ns Mode Change to Valid Output — — 10 ns CM06* TMCV2VO(2) * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. 2. A mode change includes changing any of the control register values, including module enable. 42.4.10 5-Bit DAC Specifications Table 42-16.  Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param No. Sym. Characteristic Min. Typ. † Max. Units DSB01 VLSB Step Size — (VDACREF+VDACREF-)/32 — V DSB02 VACC Absolute Accuracy — — ±0.5 LSb © 2018 Microchip Technology Inc. Datasheet Preliminary Conditions DS40002038B-page 729 PIC16(L)F18455/56 Electrical Specifications Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param No. Sym. Characteristic Min. Typ. † Max. Units DSB03* RUNIT Unit Resistor Value — 5000 — Ω DSB04* TST Settling Time(1) — — 10 μs Conditions * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. Settling time measured while DACR transitions from ‘00000’ to ‘01111’. 42.4.11 Fixed Voltage Reference (FVR) Specifications Table 42-17.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions FVR01 VFVR1 1x Gain (1.024V) -4 — +4 % VDD≥2.5V, -40°C to 85°C FVR02 VFVR2 2x Gain (2.048V) -4 — +4 % VDD≥2.5V, -40°C to 85°C FVR03 VFVR4 4x Gain (4.096V) -5 — +5 % VDD≥4.75V, -40°C to 85°C FVR04 TFVRST FVR Start-up Time — 60 — μs 42.4.12 Zero-Cross Detect (ZCD) Specifications Table 42-18.  Standard Operating Conditions (unless otherwise stated) VDD = 3.0V, TA = 25°C Param No. Sym. Characteristic Min. Typ. † Max. Units ZC01 VPINZC Voltage on Zero Cross Pin — 0.75 — V ZC02 IZCD_MAX Maximum source or sink current — — 600 μA ZC03 TRESPH Response Time, Rising Edge — 1 — μs TRESPL Response Time, Falling Edge — 1 — μs Conditions † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 730 PIC16(L)F18455/56 Electrical Specifications 42.4.13 Timer0 and Timer1 External Clock Requirements Table 42-19.  Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40°C≤TA≤+125°C Param No. Sym. Characteristic 40* TT0H T0CKI High Pulse Width No Prescaler T0CKI Low Pulse Width No Prescaler 41* TT0L Min. Typ. † Max. 0.5TCY +20 — — ns 10 — — ns 0.5TCY +20 — — ns 10 — — ns Greater of: 20 or (TCY +40)/N — — ns Synchronous, No Prescaler 0.5TCY +20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns 0.5TCY +20 — — ns Synchronous, with Prescaler 15 — — ns Asynchronous 30 — — ns Synchronous Greater of: 30 or (TCY +40)/N — — ns Asynchronous 60 — — ns 2 TOSC — 7 TOSC — With Prescaler With Prescaler 42* TT0P T0CKI Period 45* TT1H T1CKI High Time 46* 47* 49* TT1L TT1P T1CKI Synchronous, Low Time No Prescaler T1CKI Input Period TCKEZTMR1 Delay from External Clock Edge to Timer Increment Units Conditions N = Prescale value N = Prescale value Timers in Sync mode * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 731 PIC16(L)F18455/56 Electrical Specifications Figure 42-12. Timer0 and Timing1 External Clock Timings Rev. 30-000079A 4/6/2017 T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 42.4.14 Capture/Compare/PWM Requirements (CCP) Table 42-20.  Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40°C≤TA≤+125°C Param No. Sym. Characteristic CC01* TCCL CCPx Input Low Time No Prescaler 0.5TCY+20 CCPx Input High Time No Prescaler 0.5TCY+20 CC02* CC03* TCCH TCCP CCPx Input Period Min. With Prescaler With Prescaler Typ. † Max. — — ns — — ns — — ns 20 — — ns (3TCY +40)/N — — ns 20 Units Conditions N = Prescale value * - These parameters are characterized but not tested. † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 732 PIC16(L)F18455/56 Electrical Specifications Figure 42-13. Capture/Compare/PWM Timings (CCP) Rev. 30-000080A 4/6/2017 CCPx (Capture mode) CC01 CC02 CC03 Note:  Refer to Figure 42-4 for load conditions. 42.4.15 Configurable Logic Cell (CLC) Characteristics Table 42-21.  Standard Operating Conditions (unless otherwise stated) Operating Temperature: -40°C≤TA≤+125°C Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions CLC01* TCLCIN CLC input time — 7 OS5 ns (Note1) CLC02* TCLC CLC module input to output propagation time — 24 — ns VDD = 1.8V — 12 — ns VDD > 3.6V CLC output time Rise Time — OS7 — — (Note1) Fall Time — OS8 — — (Note1) — 32 FOSC CLC03* CLC04* TCLCOUT FCLCMAX CLC maximum switching frequency MHz * - These parameters are characterized but not tested. † - Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note:  1. See “I/O and CLKOUT Timing Specifications” for OS5, OS7 and OS8 rise and fall times. Figure 42-14. CLC Propagation Timing Rev. 30-000153A 10/27/2017 CLCxINn CLC Input time CLCxINn CLC Input time CLC01 LCx_in[n](1) LCx_in[n](1) CLC Module LCx_out(1) CLC Output time CLCx CLC Module LCx_out(1) CLC Output time CLCx CLC02 CLC03 Related Links © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 733 PIC16(L)F18455/56 Electrical Specifications 42.4.4 I/O and CLKOUT Timing Specifications 42.4.16 EUSART Synchronous Transmission Requirements Table 42-22.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic US120 TCKH2DTV SYNC XMIT (Master and Slave) — 80 ns 3.0V≤VDD≤5.5V Clock high to data-out valid — 100 ns 1.8V≤VDD≤5.5V Clock out rise time and fall time — 45 ns 3.0V≤VDD≤5.5V (Master mode) — 50 ns 1.8V≤VDD≤5.5V Data-out rise time and fall time — 45 ns 3.0V≤VDD≤5.5V — 50 ns 1.8V≤VDD≤5.5V US121 TCKRF US122 TDTRF Min. Max. Units Conditions Figure 42-15. EUSART Synchronous Transmission (Master/Slave) Timing Rev. 30-000081A 4/6/2017 CK US121 US121 DT US122 US120 Note:  Refer to Figure 42-4 for load conditions. 42.4.17 EUSART Synchronous Receive Requirements Table 42-23.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Max. Units Conditions US125 TDTV2CKL SYNC RCV (Master and Slave) 10 — ns 15 — ns Data-setup before CK ↓ (DT hold time) US126 TCKL2DTL Data-hold after CK ↓ (DT hold time) Figure 42-16. EUSART Synchronous Receive (Master/Slave) Timing Rev. 30-000082A 4/6/2017 CK US125 DT US126 Note:  Refer to Figure 42-4 for load conditions. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 734 PIC16(L)F18455/56 Electrical Specifications 42.4.18 SPI Mode Requirements Table 42-24.  Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. SP70* TSSL2SCH, SS↓ to SCK↓ or SCK↑ input 2.25*TCY — — ns TSSL2SCL Units Conditions SP71* TSCH SCK input high time (Slave mode) TCY + 20 — — ns SP72* TSCL SCK input low time (Slave mode) TCY + 20 — — ns SP73* TDIV2SCH, Setup time of SDI data input to SCK edge 100 — — ns Hold time of SDI data input to SCK edge 100 — — ns SDO data output rise time — 10 25 ns 3.0V≤VDD≤5.5V — 25 50 ns 1.8V≤VDD≤5.5V TDIV2SCL SP74* TSCH2DIL, TSCL2DIL SP75* TDOR SP76* TDOF SDO data output fall time — 10 25 ns SP77* TSSH2DOZ SS↑ to SDO output high-impedance 10 — 50 ns SP78* TSCR SCK output rise time (Master mode) — 10 25 ns 3.0V≤VDD≤5.5V — 25 50 ns 1.8V≤VDD≤5.5V SP79* TSCF SCK output fall time (Master mode) — 10 25 ns SP80* TSCH2DOV, SDO data output valid after SCK edge — — 50 ns 3.0V≤VDD≤5.5V — — 145 ns 1.8V≤VDD≤5.5V SDO data output setup to SCK edge 1 TCY — — ns — — 50 ns 1.5 TCY + 40 — — ns TSCL2DOV SP81* TDOV2SCH, TDOV2SCL SP82* TSSL2DOV SDO data output valid after SS↓ edge SP83* TSCH2SSH, SS ↑after SCK edge TSCL2SSH * - These parameters are characterized but not tested. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 735 PIC16(L)F18455/56 Electrical Specifications Standard Operating Conditions (unless otherwise stated) Param No. Sym. Characteristic Min. Typ. † Max. Units Conditions † Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Figure 42-17. SPI Master Mode Timing (CKE = 0, SMP = 0) Rev. 30-000083A 4/6/2017 SS SP81 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note:  Refer to Figure 42-4 for load conditions. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 736 PIC16(L)F18455/56 Electrical Specifications Figure 42-18. SPI Master Mode Timing (CKE = 1, SMP = 1) Rev. 30-000084A 4/6/2017 SS SP81 SCK (CKP = 0) SP71 SP72 SP79 SP73 SCK (CKP = 1) SP80 SDO MSb SP78 LSb bit 6 - - - - - -1 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note:  Refer to Figure 42-4 for load conditions. Figure 42-19. SPI Slave Mode Timing (CKE = 0) Rev. 30-000085A 4/6/2017 SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 SDO MSb bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note:  Refer to Figure 42-4 for load conditions. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 737 PIC16(L)F18455/56 Electrical Specifications Figure 42-20. SPI Slave Mode Timing (CKE = 1) Rev. 30-000086A 4/6/2017 SP82 SS SP70 SP83 SCK (CKP = 0) SP71 SP72 SCK (CKP = 1) SP80 MSb SDO bit 6 - - - - - -1 LSb SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 Note:  Refer to Figure 42-4 for load conditions. 42.4.19 I2C Bus Start/Stop Bits Requirements Table 42-25.  Standard Operating Conditions (unless otherwise stated) Param. No. Sym. SP90* SP91* SP92* SP93* Characteristic Min. Typ. † Max. Units Conditions TSU:STA Start condition 100 kHz mode Setup time 400 kHz mode 4700 — — 600 — — THD:STA Start condition 100 kHz mode Hold time 400 kHz mode 4000 — — 600 — — TSU:STO Stop condition 100 kHz mode Setup time 400 kHz mode 4700 — — 600 — — THD:STO Stop condition 100 kHz mode Hold time 4000 — — © 2018 Microchip Technology Inc. Datasheet Preliminary ns Only relevant for Repeated Start Setup time 400 kHz mode 600 condition ns After this period, the first clock Hold time 400 kHz mode 600 — — pulse is generated ns ns DS40002038B-page 738 PIC16(L)F18455/56 Electrical Specifications Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ. † Max. Units Conditions 400 kHz mode 600 — — * - These parameters are characterized but not tested. Figure 42-21. I2C Bus Start/Stop Bits Timing Rev. 30-000087A 4/6/2017 SCL SP93 SP91 SP90 SP92 SDA Stop Condition Start Condition Note:  Refer to Figure 42-4 for load conditions. 42.4.20 I2C Bus Data Requirements Table 42-26.  Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic SP100* THIGH Clock high time SP101* TLOW Clock low time © 2018 Microchip Technology Inc. Min. Max. Units 100 kHz mode 4.0 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — μs Device must operate at a minimum of 10 MHz SSP module 1.5TCY — 100 kHz mode 4.7 — μs Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — μs Device must operate at a minimum of 10 MHz Datasheet Preliminary Conditions DS40002038B-page 739 PIC16(L)F18455/56 Electrical Specifications Standard Operating Conditions (unless otherwise stated) Param. No. SP102* SP103* SP106* SP107* SP109* SP110* SP111 Sym. TR TF THD:DAT TSU:DAT TAA TBUF CB Characteristic Min. Max. SSP module 1.5TCY — SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1CB 300 ns SDA and SCL fall time 100 kHz mode — 250 ns 400 kHz mode 20 + 0.1CB 250 ns Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 μs 100 kHz mode 250 — ns 400 kHz mode 100 — ns Output valid from clock 100 kHz mode — 3500 ns 400 kHz mode — — ns Bus free time 100 kHz mode 4.7 — μs 400 kHz mode 1.3 — μs — 400 pF Data input setup time Bus capacitive loading Units Conditions CB is specified to be from 10-400 pF CB is specified to be from 10-400 pF (Note 2) (Note 1) Time the bus must be free before a new transmission can start * - These parameters are characterized but not tested. Note:  1. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. 2. A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the requirement TSU:DAT≥250 ns must then be met. This will automatically be the case © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 740 PIC16(L)F18455/56 Electrical Specifications Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Max. Units Conditions if the device does not stretch the low period of the SCL signal. If such a device does stretch the low period of the SCL signal, it must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification), before the SCL line is released. Figure 42-22. I2C Bus Data Timing Rev. 30-000088A 4/6/2017 SP103 SCL SP100 SP90 SP102 SP101 SP106 SP107 SP91 SDA In SP92 SP110 SP109 SP109 SDA Out Note:  Refer to Figure 42-4 for load conditions. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 741 PIC16(L)F18455/56 DC and AC Characteristics Graphs and Tables 43. DC and AC Characteristics Graphs and Tables The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. Unless otherwise noted, all graphs apply to both the L and LF devices. Note:  The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. Note:  “Typical” represents the mean of the distribution at 25°C. “Maximum”, “Max.”, “Minimum” or “Min.” represents (mean + 3σ) or (mean - 3σ) respectively, where σ is a standard deviation, over each temperature range. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 742 PIC16(L)F18455/56 DC and AC Characteristics Graphs and Tables Graphs Figure 43-1. High Range Temperature Indicator Figure 43-2. Low Range Temperature Indicator Voltage Sensitivity Across Temperature Voltage Sensitivity Across Temperature -2.300 -3.450 -3.500 -2.350 -3.550 -2.400 Slope (mV/C) -3.600 Slope (mV/C) 43.1 -3.650 -3.700 -3.750 -2.450 -2.500 -3.800 -2.550 -3.850 -3.900 -2.600 -60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 Typical +3 Sigma © 2018 Microchip Technology Inc. 20 40 60 80 100 120 140 Temperature (oC) Temperature (oC) -3 Sigma Typical Datasheet Preliminary +3 Sigma -3 Sigma DS40002038B-page 743 PIC16(L)F18455/56 Packaging Information 44. Packaging Information Package Marking Information Rev. 30-009000A 5/17/2017 Legend: XX...X Y YY WW NNN Pe3 * Note: Customer-specific information or Microchip part number Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code b - free JEDEC ® designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Rev. 30-009028A 5/17/2017 28-Lead SPDIP (.300”) Example PIC16F18455 /SP e3 1526017 Rev. 30-009028B 5/17/2017 28-Lead SOIC (7.50 mm) Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX PIC16F18455 /SO e3 1526017 YYWWNNN © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 744 PIC16(L)F18455/56 Packaging Information Rev. 30-009028C 5/17/2017 28-Lead SSOP (5.30 mm) Example PIC16F18455 /SS e3 1526017 Rev. 30-009028F 4/2/2018 28-Lead VQFN (4x4x1 mm) Example PIN 1 PIN 1 PIC16 /STX e 526017 3 44.1 Package Details The following sections give the technical details of the packages. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 745 M PIC16(L)F18455/56 Packaging Diagrams and Parameters Packaging Information 28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB Units Dimension Limits Number of Pins INCHES MIN NOM N MAX 28 Pitch e Top to Seating Plane A – – .200 Molded Package Thickness A2 .120 .135 .150 Base to Seating Plane A1 .015 – – Shoulder to Shoulder Width E .290 .310 .335 Molded Package Width E1 .240 .285 .295 Overall Length D 1.345 1.365 1.400 Tip to Seating Plane L .110 .130 .150 Lead Thickness c .008 .010 .015 b1 .040 .050 .070 b .014 .018 .022 eB – – Upper Lead Width Lower Lead Width Overall Row Spacing § .100 BSC .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic. 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-070B © 2007 Microchip Technology Inc. © 2018 Microchip Technology Inc. DS00049AR-page 57 Datasheet Preliminary DS40002038B-page 746 M Note: PIC16(L)F18455/56 Packaging Diagrams and Parameters Packaging Information For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009 Microchip Technology Inc. DS00049BC-page 110 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 747 M PIC16(L)F18455/56 Packaging Diagrams and Parameters Packaging Information Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009 Microchip Technology Inc. © 2018 Microchip Technology Inc. DS00049BC-page 109 Datasheet Preliminary DS40002038B-page 748 M Note: PIC16(L)F18455/56 Packaging Diagrams and Parameters Packaging Information For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009 Microchip Technology Inc. DS00049BC-page 104 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 749 M PIC16(L)F18455/56 Packaging Diagrams and Parameters Packaging Information 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 Units Dimension Limits Number of Pins MILLIMETERS MIN NOM N MAX 28 Pitch e Overall Height A – 0.65 BSC – 2.00 Molded Package Thickness A2 1.65 1.75 1.85 Standoff A1 0.05 – – Overall Width E 7.40 7.80 8.20 Molded Package Width E1 5.00 5.30 5.60 Overall Length D 9.90 10.20 10.50 Foot Length L 0.55 0.75 0.95 Footprint L1 1.25 REF Lead Thickness c 0.09 – Foot Angle φ 0° 4° 0.25 8° Lead Width b 0.22 – 0.38 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-073B © 2007 Microchip Technology Inc. DS00049AR-page 116 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 750 M PIC16(L)F18455/56 Packaging Diagrams and Parameters Packaging Information Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2009 Microchip Technology Inc. © 2018 Microchip Technology Inc. DS00049BC-page 97 Datasheet Preliminary DS40002038B-page 751 PIC16(L)F18455/56 Packaging Information 28-Lead Very Thin Plastic Quad Flat, No Lead (STX) - 4x4 mm Body [VQFN] With 2.65x2.65 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D NOTE 1 A B N 1 2 E (DATUM B) (DATUM A) 2X 0.10 C 2X TOP VIEW 0.10 C 0.10 C C A A SEATING PLANE 28X (A3) 0.08 C SIDE VIEW 0.10 C A B D2 L 0.10 C A B E2 2 1 CH (K) N NOTE 1 28X b 0.07 e C A B BOTTOM VIEW Microchip Technology Drawing C04-456 Rev A Sheet 1 of 2 © 2017 Microchip Technology Inc. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 752 PIC16(L)F18455/56 Packaging Information 28-Lead Very Thin Plastic Quad Flat, No Lead (STX) - 4x4 mm Body [VQFN] With 2.65x2.65 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits N Number of Terminals e Pitch Overall Height A Standoff A1 A3 Terminal Thickness Overall Length D Exposed Pad Length D2 E Overall Width Exposed Pad Width E2 Exposed Pad Corner Chamfer CH b Terminal Width L Terminal Length Terminal-to-Exposed-Pad K MIN 0.80 0.00 2.55 2.55 0.15 0.30 MILLIMETERS NOM 28 0.40 BSC 0.90 0.02 0.127 REF 4.00 BSC 2.65 4.00 BSC 2.65 0.25 0.20 0.40 0.275 REF MAX 1.00 0.05 2.75 2.75 0.25 0.50 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-456 Rev A Sheet 2 of 2 © 2017 Microchip Technology Inc. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 753 PIC16(L)F18455/56 Packaging Information 28-Lead Very Thin Plastic Quad Flat, No Lead (STX) - 4x4 mm Body [VQFN] With 2.65x2.65 mm Exposed Pad Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging C1 X2 EV ØV C2 Y2 EV G1 Y1 SILK SCREEN G2 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Optional Center Pad Width X2 Optional Center Pad Length Y2 Contact Pad Spacing C1 Contact Pad Spacing C2 Contact Pad Width (X28) X1 Contact Pad Length (X28) Y1 Contact Pad to Center Pad (X28) G1 Contact Pad to Contact Pad (X24) G2 Thermal Via Diameter V Thermal Via Pitch EV MIN MILLIMETERS NOM 0.40 BSC MAX 2.75 2.75 4.00 4.00 0.20 0.80 0.23 0.20 0.30 1.00 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-2456 Rev A © 2017 Microchip Technology Inc. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 754 PIC16(L)F18455/56 Revision History 45. Revision History Date Revision Comment 5/2018 A Initial release of this document. 6/2018 B Minor corrections to electrical specs and removed EOL packages QFN and UQFN. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 755 PIC16(L)F18455/56 The Microchip Web Site Microchip provides online support via our web site at http://www.microchip.com/. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • • • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives Customer Change Notification Service Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at http://www.microchip.com/. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. Customer Support Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 756 PIC16(L)F18455/56 Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device [X](1) –X /XX Tape Temperature and Reel Range Device: Tape & Reel Option: Temperature Range: Package: Pattern: Package PIC16F18455, PIC16LF1845, PIC16F18456, PIC16LF18456 Blank = Tube T = Tape & Reel I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) SP = 28-lead, SPDIP SO = 28-lead SOIC SS = 28-lead SSOP STX = 28-lead VQFN 4x4x1 mm QTP, SQTP, Code or Special Requirements (blank otherwise) Examples: • PIC16F18455- E/P Extended temperature PDIP package Note:  1. Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. 2. Small form-factor packaging options may be available. Please check http://www.microchip.com/ packaging for small-form factor package availability, or contact your local Sales Office. Microchip Devices Code Protection Feature Note the following details of the code protection feature on Microchip devices: • • • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 757 PIC16(L)F18455/56 Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Legal Notice Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, CryptoAuthentication, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2018, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 758 PIC16(L)F18455/56 ISBN: 978-1-5224-3260-9 Quality Management System Certified by DNV ISO/TS 16949 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California ® ® and India. The Company’s quality system processes and procedures are for its PIC MCUs and dsPIC ® DSCs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 759 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 Australia - Sydney Tel: 61-2-9868-6733 China - Beijing Tel: 86-10-8569-7000 China - Chengdu Tel: 86-28-8665-5511 China - Chongqing Tel: 86-23-8980-9588 China - Dongguan Tel: 86-769-8702-9880 China - Guangzhou Tel: 86-20-8755-8029 China - Hangzhou Tel: 86-571-8792-8115 China - Hong Kong SAR Tel: 852-2943-5100 China - Nanjing Tel: 86-25-8473-2460 China - Qingdao Tel: 86-532-8502-7355 China - Shanghai Tel: 86-21-3326-8000 China - Shenyang Tel: 86-24-2334-2829 China - Shenzhen Tel: 86-755-8864-2200 China - Suzhou Tel: 86-186-6233-1526 China - Wuhan Tel: 86-27-5980-5300 China - Xian Tel: 86-29-8833-7252 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 India - Bangalore Tel: 91-80-3090-4444 India - New Delhi Tel: 91-11-4160-8631 India - Pune Tel: 91-20-4121-0141 Japan - Osaka Tel: 81-6-6152-7160 Japan - Tokyo Tel: 81-3-6880- 3770 Korea - Daegu Tel: 82-53-744-4301 Korea - Seoul Tel: 82-2-554-7200 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 Malaysia - Penang Tel: 60-4-227-8870 Philippines - Manila Tel: 63-2-634-9065 Singapore Tel: 65-6334-8870 Taiwan - Hsin Chu Tel: 886-3-577-8366 Taiwan - Kaohsiung Tel: 886-7-213-7830 Taiwan - Taipei Tel: 886-2-2508-8600 Thailand - Bangkok Tel: 66-2-694-1351 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 Finland - Espoo Tel: 358-9-4520-820 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-67-3636 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Israel - Ra’anana Tel: 972-9-744-7705 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7289-7561 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 © 2018 Microchip Technology Inc. Datasheet Preliminary DS40002038B-page 760 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microchip: PIC16F18456-I/SS PIC16F18456-I/SO PIC16LF18456-I/SS PIC16F18455-E/SS PIC16F18455-I/SP PIC16F18455I/SS PIC16F18455T-I/SO PIC16F18455T-I/SS PIC16F18455-I/SO PIC16F18455-E/SO PIC16F18455-E/SP PIC16LF18455-I/SO PIC16LF18455-E/SO PIC16F18456-I/SP PIC16LF18455T-I/SO PIC16F18456-E/SP PIC16F18456T-I/SO PIC16F18456-E/SO PIC16F18456-E/SS PIC16LF18456T-I/SO PIC16LF18456-E/SO PIC16LF18456-I/SO PIC16F18456-E/STX PIC16LF18455-I/SP PIC16LF18456T-I/SS PIC16F18455-E/STX PIC16LF18455-E/STX PIC16F18456-I/STX PIC16LF18455-E/SS PIC16LF18456-E/SP PIC16F18456T-I/SS PIC16LF18455-I/STX PIC16LF18455T-I/STX PIC16LF18455T-I/SS PIC16F18455T-I/STX PIC16LF18455-I/SS PIC16F18456T-I/STX PIC16LF18456-E/SS PIC16F18455-I/STX PIC16LF18455-E/SP PIC16LF18456-I/STX PIC16LF18456-E/STX PIC16LF18456-I/SP PIC16LF18456T-I/STX