PIC32MZ1024EFG100-250I/PT

PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 32-bit MCUs (up to 2 MB Live-Update Flash and 512 KB SRAM) with FPU, Audio and Graphics Interfaces, HS USB, Ethernet, and Advanced Analog Operating Conditions Advanced Analog Features • 2.1V to 3.6V, -40ºC to +85ºC, DC to 252 MHz • 2.1V to 3.6V, -40ºC to +125ºC, DC to 180 MHz • 12-bit ADC module: - 18 Msps with up to six Sample and Hold (S&H) circuits (five dedicated and one shared) - Up to 48 analog inputs - Can operate during Sleep and Idle modes - Multiple trigger sources - Six Digital Comparators and six Digital Filters • Two comparators with 32 programmable voltage references • Temperature sensor with ±2ºC accuracy Core: 252 MHz (up to 415 DMIPS) M-Class • • • • • 16 KB I-Cache, 4 KB D-Cache FPU for 32-bit and 64-bit floating point math MMU for optimum embedded OS execution microMIPS™ mode for up to 35% smaller code size DSP-enhanced core: - Four 64-bit accumulators - Single-cycle MAC, saturating, and fractional math - IEEE 754-compliant • Code-efficient (C and Assembly) architecture Clock Management • Programmable PLLs and oscillator clock sources • Fail-Safe Clock Monitor (FSCM) • Independent Watchdog Timers (WDT) and Deadman Timer (DMT) • Fast wake-up and start-up Power Management • Low-power modes (Sleep and Idle) • Integrated Power-on Reset (POR) and Brown-out Reset (BOR) Memory Interfaces • 50 MHz External Bus Interface (EBI) • 50 MHz Serial Quad Interface (SQI) • Two CAN modules (with dedicated DMA channels): - 2.0B Active with DeviceNet™ addressing support • Six UART modules (25 Mbps): - Supports up to LIN 2.1 and IrDA® protocols • Six 4-wire SPI modules (up to 50 MHz) • SQI configurable as an additional SPI module (50 MHz) • Five I2C modules (up to 1 Mbaud) with SMBus support • Parallel Host Port (PMP) • Peripheral Pin Select (PPS) to enable function remap Timers/Output Compare/Input Capture • • • • Nine 16-bit or up to four 32-bit timers/counters Nine Output Compare (OC) modules Nine Input Capture (IC) modules Real-Time Clock and Calendar (RTCC) module Input/Output Audio and Graphics Interfaces • • • • Communication Interfaces Graphics interfaces: EBI or PMP Audio data communication: I2S, LJ, and RJ Audio control interfaces: SPI and I2C Audio host clock: Fractional clock frequencies with USB synchronization • 5V-tolerant pins with up to 32 mA source/sink • Selectable open drain, pull-ups, pull-downs, and slew rate controls • External interrupts on all I/O pins • PPS to enable function remap Qualification and Class B Support High-Speed (HS) Communication Interfaces  (with Dedicated DMA) • AEC-Q100 REVH (Grade 1 -40ºC to +125ºC) • Class B Safety Library, IEC 60730 • Back-up internal oscillator • USB 2.0 Hi-Speed On-The-Go (OTG) controller • 10/100 Mbps Ethernet MAC with MII and RMII interface Debugger Development Support Security Features • Crypto Engine with RNG for data encryption/decryption and authentication (AES, 3DES, SHA, MD5, and HMAC) • Advanced memory protection: - Peripheral and memory region access control • • • • • Software and Tools Support • • • • • Direct Memory Access (DMA) • Eight channels with automatic data size detection • Programmable Cyclic Redundancy Check (CRC) In-circuit and in-application programming 4-wire MIPS® Enhanced JTAG interface Unlimited software and 12 complex breakpoints IEEE 1149.2-compatible (JTAG) boundary scan Non-intrusive hardware-based instruction trace C/C++ compiler with native DSP/fractional and FPU support MPLAB® Harmony Integrated Software Framework TCP/IP, USB, Graphics, and mTouch™ middleware MFi, Android™, and Bluetooth® audio frameworks RTOS Kernels: Express Logic ThreadX, FreeRTOS™, OPENRTOS®, Micriµm® µC/OS™, and SEGGER embOS® Packages Type QFN TQFP TFBGA VTLA LQFP Pin Count 64 64 100 144 100 144 124 144 I/O Pins (up to) 53 53 78 120 78 120 98 120 Contact/Lead Pitch 0.50 mm 0.50 mm 0.40 mm 0.50 mm 0.40 mm 0.65 mm 0.50 mm 0.50 mm 0.50 mm Dimensions 9x9x0.9 mm 10x10x1 mm 12x12x1 mm 14x14x1 mm 16x16x1 mm 7x7x1.2 mm 7x7x1.2 mm 9x9x0.9 mm 20x20x1.40 mm  2015-2021 Microchip Technology Inc. DS60001320H-page 1 PIC32MZ EF FAMILY FEATURES Y 8/18 PIC32MZ0512EFE100 0 N Y 8/12 2 N Y 8/16 2 Y Y 8/18 0 N Y 8/12 8/16 128 PIC32MZ0512EFK100 100 PIC32MZ1024EFE100 PIC32MZ1024EFF100 160 51 9/9/9 6 6 5 2 N Y PIC32MZ1024EFK100 2 Y Y 8/18 PIC32MZ0512EFE124 0 N Y 8/12 2 N Y 8/16 2 Y Y 8/18 0 N Y 8/12 8/16 PIC32MZ0512EFF124 1024 TQFP, TFBGA 512 256 128 PIC32MZ0512EFK124 124 PIC32MZ1024EFE124 PIC32MZ1024EFF124 160 53 9/9/9 6 6 5  2015-2021 Microchip Technology Inc. 2 N Y PIC32MZ1024EFK124 2 Y Y 8/18 PIC32MZ0512EFE144 0 N Y 8/12 2 N Y 8/16 2 Y Y 8/18 0 N Y 8/12 2 N Y 8/16 2 Y Y 8/18 PIC32MZ0512EFF144 1024 VTLA 512 256 128 PIC32MZ0512EFK144 144 PIC32MZ1024EFE144 PIC32MZ1024EFF144 1024 LQFP, TQFP, TFBGA 160 256 PIC32MZ1024EFK144 Note 1: 2: 3: Eight out of nine timers are remappable. Four out of five external interrupts are remappable. This device is available with a 252 MHz speed rating. 53 9/9/9 6 6 5 Trace Y Y JTAG 8/16 N 2 I/O Pins 8/12 Ethernet Y RTCC N SQI 8/18 0 EBI Y 2 512 256 Y PMP 5 8/16 2 I2C 4 8/12 Y USB 2.0 HS OTG 6 Y N Analog Comparators 9/9/9 N 2 PIC32MZ1024EFK064 PIC32MZ0512EFF100 1024 34 0 ADC (Channels) PIC32MZ1024EFF064 160 DMA Channels (Programmable/ Dedicated) 64 PIC32MZ1024EFE064 TQFP, QFN RNG PIC32MZ0512EFK064 Crypto PIC32MZ0512EFE064 PIC32MZ0512EFF064 CAN 2.0B External Interrupts(2) SPI/I2S UART Timers/ Capture/ Compare(1) Remappable Pins Boot Flash Memory (KB) 128 Packages Data Memory (KB) 512 Pins Program Memory (KB) Device Remappable Peripherals 24 2 Y 4 Y N Y Y Y 46 Y Y 40 2 Y 5 Y Y Y Y Y 78 Y Y 48 2 Y 5 Y Y Y Y Y 97 Y Y 48 2 Y 5 Y Y Y Y Y 120 Y Y PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 2 TABLE 1: PIC32MZ EF FAMILY FEATURES (CONTINUED) 8/16 2 N Y PIC32MZ2048EFM064 2 Y Y 8/18 PIC32MZ1024EFG100 0 N Y 8/12 2 N Y 8/16 2 Y Y 8/18 0 N Y 8/12 8/16 PIC32MZ1024EFH100 1024 PIC32MZ1024EFM100 512 PIC32MZ2048EFG100 PIC32MZ2048EFH100(3) 100 TQFP, TFBGA 160 51 9/9/9 6 6 5 2048 2 N Y PIC32MZ2048EFM100 2 Y Y 8/18 PIC32MZ1024EFG124 0 N Y 8/12 2 N Y 8/16 2 Y Y 8/18 0 N Y 8/12 8/16 PIC32MZ1024EFH124 1024 PIC32MZ1024EFM124 512 PIC32MZ2048EFG124 PIC32MZ2048EFH124 124 VTLA 160 53 9/9/9 6 6 5 2 N Y PIC32MZ2048EFM124 2 Y Y 8/18 PIC32MZ1024EFG144 0 N Y 8/12 2 N Y 8/16 2 Y Y 8/18 0 N Y 8/12 2 N Y 8/16 2 Y Y 8/18 PIC32MZ1024EFH144 2048 1024 PIC32MZ1024EFM144 512 PIC32MZ2048EFG144 PIC32MZ2048EFH144(3) 144 LQFP, TQFP, TFBGA 160 2048 PIC32MZ2048EFM144 DS60001320H-page 3 Note 1: 2: 3: Eight out of nine timers are remappable. Four out of five external interrupts are remappable. This device is available with a 252 MHz speed rating. 53 9/9/9 6 6 5 Trace 8/12 JTAG Y I/O Pins N Ethernet 2048 8/18 0 RTCC 5 Y SQI 4 Y EBI 6 8/16 2 PMP 9/9/9 8/12 Y I2C 34 Y N USB 2.0 HS OTG 160 N 2 Analog Comparators PIC32MZ2048EFH064(3) 64 0 ADC (Channels) 512 PIC32MZ2048EFG064 TQFP, QFN DMA Channels (Programmable/ Dedicated) PIC32MZ1024EFM064 RNG 1024 Crypto PIC32MZ1024EFG064 PIC32MZ1024EFH064 CAN 2.0B External Interrupts(2) SPI/I2S UART Timers/ Capture/ Compare(1) Remappable Pins Boot Flash Memory (KB) Packages Pins Data Memory (KB) Program Memory (KB) Device Remappable Peripherals 24 2 Y 4 Y N Y Y Y 46 Y Y 40 2 Y 5 Y Y Y Y Y 78 Y Y 48 2 Y 5 Y Y Y Y Y 97 Y Y 48 2 Y 5 Y Y Y Y Y 120 Y Y PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 1: PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Device Pin Tables TABLE 2: PIN NAMES FOR 64-PIN QFN AND TQFP DEVICES 64-PIN QFN(4) AND TQFP (TOP VIEW) PIC32MZ0512EF(E/F/K)064 PIC32MZ1024EF(G/H/M)064 PIC32MZ1024EF(E/F/K)064 PIC32MZ2048EF(G/H/M)064 64 Pin # Full Pin Name 64 1 QFN(4) TQFP Pin # 1 Full Pin Name 1 AN17/ETXEN/RPE5/PMD5/RE5 33 VBUS 2 AN16/ETXD0/PMD6/RE6 34 VUSB3V3 3 AN15/ETXD1/PMD7/RE7 35 VSS 4 AN14/C1IND/RPG6/SCK2/PMA5/RG6 36 D- 5 AN13/C1INC/RPG7/SDA4/PMA4/RG7 37 D+ 6 AN12/C2IND/RPG8/SCL4/PMA3/RG8 38 RPF3/USBID/RF3 7 VSS 39 VDD 8 VDD 40 VSS 9 MCLR 41 RPF4/SDA5/PMA9/RF4 10 AN11/C2INC/RPG9/PMA2/RG9 42 RPF5/SCL5/PMA8/RF5 11 AN45/C1INA/RPB5/RB5 43 AERXD0/ETXD2/RPD9/SDA1/PMCS2/PMA15/RD9 12 AN4/C1INB/RB4 44 ECOL/RPD10/SCL1/SCK4/RD10 13 AN3/C2INA/RPB3/RB3 45 AERXCLK/AEREFCLK/ECRS/RPD11/PMCS1/PMA14/RD11 14 AN2/C2INB/RPB2/RB2 46 AERXD1/ETXD3/RPD0/RTCC/INT0/RD0 15 PGEC1/VREF-/CVREF-/AN1/RPB1/RB1 47 SOSCI/RPC13/RC13 16 PGED1/VREF+/CVREF+/AN0/RPB0/PMA6/RB0 48 SOSCO/RPC14/T1CK/RC14 17 PGEC2/AN46/RPB6/RB6 49 EMDIO/AEMDIO/RPD1/SCK1/RD1 18 PGED2/AN47/RPB7/RB7 50 ETXERR/AETXEN/RPD2/SDA3/RD2 19 AVDD 51 AERXERR/ETXCLK/RPD3/SCL3/RD3 20 AVss 52 SQICS0/RPD4/PMWR/RD4 21 AN48/RPB8/PMA10/RB8 53 SQICS1/RPD5/PMRD/RD5 22 AN49/RPB9/PMA7/RB9 54 VDD 23 TMS/CVREFOUT/AN5/RPB10/PMA13/RB10 55 VSS 24 TDO/AN6/PMA12/RB11 56 ERXD3/AETXD1/RPF0/RF0 25 VSS 57 TRCLK/SQICLK/ERXD2/AETXD0/RPF1/RF1 26 VDD 58 TRD0/SQID0/ERXD1/PMD0/RE0 27 TCK/AN7/PMA11/RB12 59 VSS 28 TDI/AN8/RB13 60 VDD TRD1/SQID1/ERXD0/PMD1/RE1 29 AN9/RPB14/SCK3/PMA1/RB14 61 30 AN10/EMDC/AEMDC/RPB15/OCFB/PMA0/RB15 62 TRD2/SQID2/ERXDV/ECRSDV/AECRSDV/PMD2/RE2 31 OSC1/CLKI/RC12 63 TRD3/SQID3/ERXCLK/EREFCLK/RPE3/PMD3/RE3 OSC2/CLKO/RC15 64 AN18/ERXERR/PMD4/RE4 32 Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin Select (PPS)” for restrictions. Every I/O port pin (RBx-RGx) can be used as a change notification pin (CNBx-CNGx). See Section 12.0 “I/O Ports” for more information. Shaded pins are 5V tolerant. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS60001320H-page 4  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 3: PIN NAMES FOR 100-PIN TQFP DEVICES 100-PIN TQFP (TOP VIEW) PIC32MZ0512EF(E/F/K)100 PIC32MZ1024EF(G/H/M)100 PIC32MZ1024EF(E/F/K)100 PIC32MZ2048EF(G/H/M)100 Package Pin # Full Pin Name Package Pin # Full Pin Name 1 AN23/AERXERR/RG15 36 VSS 2 EBIA5/AN34/PMA5/RA5 37 VDD 3 EBID5/AN17/RPE5/PMD5/RE5 38 TCK/EBIA19/AN29/RA1 4 EBID6/AN16/PMD6/RE6 39 TDI/EBIA18/AN30/RPF13/SCK5/RF13 5 EBID7/AN15/PMD7/RE7 40 TDO/EBIA17/AN31/RPF12/RF12 6 EBIA6/AN22/RPC1/PMA6/RC1 41 EBIA11/AN7/ERXD0/AECRS/PMA11/RB12 7 EBIA12/AN21/RPC2/PMA12/RC2 42 AN8/ERXD1/AECOL/RB13 8 EBIWE/AN20/RPC3/PMWR/RC3 43 EBIA1/AN9/ERXD2/AETXD3/RPB14/SCK3/PMA1/RB14 9 EBIOE/AN19/RPC4/PMRD/RC4 44 EBIA0/AN10/ERXD3/AETXD2/RPB15/OCFB/PMA0/RB15 10 AN14/C1IND/ECOL/RPG6/SCK2/RG6 45 VSS 11 EBIA4/AN13/C1INC/ECRS/RPG7/SDA4/PMA4/RG7 46 VDD 12 EBIA3/AN12/C2IND/ERXDV/ECRSDV/AERXDV/ AECRSDV/ RPG8/SCL4/PMA3/RG8 47 AN32/AETXD0/RPD14/RD14 13 Vss 48 AN33/AETXD1/RPD15/SCK6/RD15 14 VDD 49 OSC1/CLKI/RC12 15 MCLR 50 OSC2/CLKO/RC15 16 EBIA2/AN11/C2INC/ERXCLK/EREFCLK/AERXCLK/ AEREFCLK/RPG9/PMA2/RG9 51 VBUS 17 TMS/EBIA16/AN24/RA0 52 VUSB3V3 18 AN25/AERXD0/RPE8/RE8 53 VSS 19 AN26/AERXD1/RPE9/RE9 54 D- 20 AN45/C1INA/RPB5/RB5 55 D+ 21 AN4/C1INB/RB4 56 RPF3/USBID/RF3 22 AN3/C2INA/RPB3/RB3 57 EBIRDY3/RPF2/SDA3/RF2 23 AN2/C2INB/RPB2/RB2 58 EBIRDY2/RPF8/SCL3/RF8 24 PGEC1/AN1/RPB1/RB1 59 EBICS0/SCL2/RA2 25 PGED1/AN0/RPB0/RB0 60 EBIRDY1/SDA2/RA3 26 PGEC2/AN46/RPB6/RB6 61 EBIA14/PMCS1/PMA14/RA4 27 PGED2/AN47/RPB7/RB7 62 VDD 28 VREF-/CVREF-/AN27/AERXD2/RA9 63 VSS 29 VREF+/CVREF+/AN28/AERXD3/RA10 64 EBIA9/RPF4/SDA5/PMA9/RF4 30 AVDD 65 EBIA8/RPF5/SCL5/PMA8/RF5 31 AVSS 66 AETXCLK/RPA14/SCL1/RA14 32 EBIA10/AN48/RPB8/PMA10/RB8 67 AETXEN/RPA15/SDA1/RA15 33 EBIA7/AN49/RPB9/PMA7/RB9 68 EBIA15/RPD9/PMCS2/PMA15/RD9 34 EBIA13/CVREFOUT/AN5/RPB10/PMA13/RB10 69 RPD10/SCK4/RD10 35 AN6/ERXERR/AETXERR/RB11 70 EMDC/AEMDC/RPD11/RD11 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin Select (PPS)” for restrictions. Every I/O port pin (RAx-RJx) can be used as a change notification pin (CNAx-CNJx). See Section 12.0 “I/O Ports” for more information. Shaded pins are 5V tolerant.  2015-2021 Microchip Technology Inc. DS60001320H-page 5 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 3: PIN NAMES FOR 100-PIN TQFP DEVICES (CONTINUED) 100-PIN TQFP (TOP VIEW) PIC32MZ0512EF(E/F/K)100 PIC32MZ1024EF(G/H/M)100 PIC32MZ1024EF(E/F/K)100 PIC32MZ2048EF(G/H/M)100 Package Pin # Full Pin Name Package Pin # Full Pin Name 71 EMDIO/AEMDIO/RPD0/RTCC/INT0/RD0 86 EBID10/ETXD0/RPF1/PMD10/RF1 72 SOSCI/RPC13/RC13 87 EBID9/ETXERR/RPG1/PMD9/RG1 73 SOSCO/RPC14/T1CK/RC14 88 EBID8/RPG0/PMD8/RG0 74 VDD 89 TRCLK/SQICLK/RA6 75 VSS 90 TRD3/SQID3/RA7 76 RPD1/SCK1/RD1 91 EBID0/PMD0/RE0 77 EBID14/ETXEN/RPD2/PMD14/RD2 92 VSS 78 EBID15/ETXCLK/RPD3/PMD15/RD3 93 VDD 79 EBID12/ETXD2/RPD12/PMD12/RD12 94 EBID1/PMD1/RE1 80 EBID13/ETXD3/PMD13/RD13 95 TRD2/SQID2/RG14 81 SQICS0/RPD4/RD4 96 TRD1/SQID1/RG12 82 SQICS1/RPD5/RD5 97 TRD0/SQID0/RG13 83 VDD 98 EBID2/PMD2/RE2 84 VSS 99 EBID3/RPE3/PMD3/RE3 85 EBID11/ETXD1/RPF0/PMD11/RF0 100 EBID4/AN18/PMD4/RE4 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin Select (PPS)” for restrictions. Every I/O port pin (RAx-RJx) can be used as a change notification pin (CNAx-CNJx). See Section 12.0 “I/O Ports” for more information. Shaded pins are 5V tolerant. DS60001320H-page 6  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 4: PIN NAMES FOR 100-PIN TFBGA DEVICES 100-PIN TFBGA (BOTTOM VIEW) PIC32MZ0512EF(E/F/K)100 PIC32MZ1024EF(G/H/M)100 PIC32MZ1024EF(E/F/K)100 PIC32MZ2048EF(G/H/M)100 Pin # Full Pin Name Pin # Full Pin Name A1 PGED1/AN0/RPB0/RB0 D6 EBIA4/AN13/C1INC/ECRS/RPG7/SDA4/PMA4/RG7 A2 PGEC1/AN1/RPB1/RB1 D7 VSS A3 AN25/AERXD0/RPE8/RE8 D8 EBID1/PMD1/RE1 A4 AN26/AERXD1/RPE9/RE9 D9 TRD2/SQID2/RG14 A5 Vdd D10 Vdd A6 EBIWE/AN20/RPC3/PMWR/RC3 E1 EBIA13/CVrefout/AN5/RPB10/PMA13/RB10 A7 EBIA12/AN21/RPC2/PMA12/RC2 E2 EBIA7/AN49/RPB9/PMA7/RB9 A8 EBIA5/AN34/PMA5/RA5 E3 EBIA10/AN48/RPB8/PMA10/RB8 A9 AN23/AERXERR/RG15 E4 Vss A10 EBID3/RPE3/PMD3/RE3 E5 TCK/EBIA19/AN29/RA1 B1 PGEC2/AN46/RPB6/RB6 E6 VSS B2 AN2/C2INB/RPB2/RB2 E7 EBID0/PMD0/RE0 B3 AN4/C1INB/RB4 E8 EBID8/RPG0/PMD8/RG0 B4 AN45/C1INA/RPB5/RB5 E9 TRCLK/SQICLK/RA6 B5 MCLR E10 TRD3/SQID3/RA7 B6 EBIOE/AN19/RPC4/PMRD/RC4 F1 VDD B7 EBIA6/AN22/RPC1/PMA6/RC1 F2 TDI/EBIA18/AN30/RPF13/SCK5/RF13 B8 EBID5/AN17/RPE5/PMD5/RE5 F3 AN6/ERXERR/AETXERR/RB11 B9 EBID4/AN18/PMD4/RE4 F4 EBIA0/AN10/ERXD3/AETXD2/RPB15/OCFB/PMA0/RB15 B10 EBID2/PMD2/RE2 F5 EBIRDY3/RPF2/SDA3/RF2 C1 PGED2/AN47/RPB7/RB7 F6 EBIA9/RPF4/SDA5/PMA9/RF4 C2 Vref-/CVref-/AN27/AERXD2/RA9 F7 Vss C3 AN3/C2INA/RPB3/RB3 F8 EBID11/ETXD1/RPF0/PMD11/RF0 C4 TMS/EBIA16/AN24/RA0 F9 EBID10/ETXD0/RPF1/PMD10/RF1 C5 EBIA3/AN12/C2IND/ERXDV/ECRSDV/AERXDV/ AECRSDV/RPG8/SCL4/PMA3/RG8 F10 EBID9/ETXERR/RPG1/PMD9/RG1 C6 AN14/C1IND/ECOL/RPG6/SCK2/RG6 G1 TDO/EBIA17/AN31/RPF12/RF12 C7 EBID7/AN15/PMD7/RE7 G2 EBIA11/AN7/ERXD0/AECRS/PMA11/RB12 C8 EBID6/AN16/PMD6/RE6 G3 EBIA1/AN9/ERXD2/AETXD3/RPB14/SCK3/PMA1/RB14 C9 TRD1/SQID1/RG12 G4 Vss C10 TRD0/SQID0/RG13 G5 EBIRDY2/RPF8/SCL3/RF8 D1 AVDD G6 EBIA8/RPF5/SCL5/PMA8/RF5 D2 Vref+/CVref+/AN28/AERXD3/RA10 G7 EBID13/ETXD3/PMD13/RD13 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin Select (PPS)” for restrictions. Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 12.0 “I/O Ports” for more information. Shaded pins are 5V tolerant.  2015-2021 Microchip Technology Inc. DS60001320H-page 7 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 4: PIN NAMES FOR 100-PIN TFBGA DEVICES (CONTINUED) 100-PIN TFBGA (BOTTOM VIEW) PIC32MZ0512EF(E/F/K)100 PIC32MZ1024EF(G/H/M)100 PIC32MZ1024EF(E/F/K)100 PIC32MZ2048EF(G/H/M)100 Pin # Full Pin Name D3 AVss D4 Pin # Full Pin Name G8 SQICS0/RPD4/RD4 EBIA2/AN11/C2INC/ERXCLK/EREFCLK/AERXCLK/AEREFCLK/RPG9/PMA2/RG9 G9 SQICS1/RPD5/RD5 D5 Vss G10 Vdd H1 Vdd J6 AETXEN/RPA15/SDA1/RA15 H2 AN8/ERXD1/AECOL/RB13 J7 RPD10/SCK4/RD10 H3 Vbus J8 EMDIO/AEMDIO/RPD0/RTCC/INT0/RD0 H4 Vss J9 Vss H5 EBICS0/SCL2/RA2 J10 Vdd H6 EBIA14/PMCS1/PMA14/RA4 K1 OSC1/CLKI/RC12 H7 EBID12/ETXD2/RPD12/PMD12/RD12 K2 OSC2/CLKO/RC15 H8 EBID15/ETXCLK/RPD3/PMD15/RD3 K3 D- H9 EBID14/ETXEN/RPD2/PMD14/RD2 K4 D+ H10 RPD1/SCK1/RD1 K5 Vdd J1 AN33/AETXD1/RPD15/SCK6/RD15 K6 AETXCLK/RPA14/SCL1/RA14 J2 AN32/AETXD0/RPD14/RD14 K7 EBIA15/RPD9/PMCS2/PMA15/RD9 J3 Vusb3v3 K8 EMDC/AEMDC/RPD11/RD11 J4 RPF3/USBID/RF3 K9 SOSCI/RPC13/RC13 J5 EBIRDY1/SDA2/RA3 K10 SOSCO/RPC14/T1CK/RC14 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin Select (PPS)” for restrictions. Every I/O port pin (RAx-RGx) can be used as a change notification pin (CNAx-CNGx). See Section 12.0 “I/O Ports” for more information. Shaded pins are 5V tolerant. DS60001320H-page 8  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 5: PIN NAMES FOR 124-PIN VTLA DEVICES 124-PIN VTLA (BOTTOM VIEW) A34 A17 PIC32MZ0512EF(E/F/K)124 PIC32MZ1024EF(G/H/M)124 PIC32MZ1024EF(E/F/K)124 PIC32MZ2048EF(G/H/M)124 B1 Full Pin Name B56 B41 A51 A1 A68 Polarity Indicator Package Pin # B29 B13 Package Pin # Full Pin Name A1 No Connect A35 VBUS A2 AN23/RG15 A36 VUSB3V3 A3 EBID5/AN17/RPE5/PMD5/RE5 A37 D- A4 EBID7/AN15/PMD7/RE7 A38 RPF3/USBID/RF3 A5 AN35/ETXD0/RJ8 A39 EBIRDY2/RPF8/SCL3/RF8 A6 EBIA12/AN21/RPC2/PMA12/RC2 A40 ERXD3/RH9 A7 EBIOE/AN19/RPC4/PMRD/RC4 A41 EBICS0/SCL2/RA2 A8 EBIA4/AN13/C1INC/RPG7/SDA4/PMA4/RG7 A42 EBIA14/PMCS1/PMA14/RA4 VSS A9 VSS A43 A10 MCLR A44 EBIA8/RPF5/SCL5/PMA8/RF5 A11 TMS/EBIA16/AN24/RA0 A45 RPA15/SDA1/RA15 A12 AN26/RPE9/RE9 A46 RPD10/SCK4/RD10 A13 AN4/C1INB/RB4 A47 ECRS/RH12 A14 AN3/C2INA/RPB3/RB3 A48 RPD0/RTCC/INT0/RD0 A15 VDD A49 SOSCO/RPC14/T1CK/RC14 A16 AN2/C2INB/RPB2/RB2 A50 VDD A17 PGEC1/AN1/RPB1/RB1 A51 VSS A18 PGED1/AN0/RPB0/RB0 A52 RPD1/SCK1/RD1 A19 PGED2/AN47/RPB7/RB7 A53 EBID15/RPD3/PMD15/RD3 A20 VREF+/CVREF+/AN28/RA10 A54 EBID13/PMD13/RD13 A21 AVSS A55 EMDIO/RJ1 A22 AN39/ETXD3/RH1 A56 SQICS0/RPD4/RD4 ETXEN/RPD6/RD6 A23 EBIA7/AN49/RPB9/PMA7/RB9 A57 A24 AN6/RB11 A58 VDD A25 VDD A59 EBID11/RPF0/PMD11/RF0 A26 TDI/EBIA18/AN30/RPF13/SCK5/RF13 A60 EBID9/RPG1/PMD9/RG1 A27 EBIA11/AN7/PMA11/RB12 A61 TRCLK/SQICLK/RA6 A28 EBIA1/AN9/RPB14/SCK3/PMA1/RB14 A62 RJ4 A29 VSS A63 VSS EBID1/PMD1/RE1 A30 AN40/ERXERR/RH4 A64 A31 AN42/ERXD2/RH6 A65 TRD1/SQID1/RG12 A32 AN33/RPD15/SCK6/RD15 A66 EBID2/SQID2/PMD2/RE2 A33 OSC2/CLKO/RC15 A67 EBID4/AN18/PMD4/RE4 A34 No Connect A68 No Connect Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin Select (PPS)” for restrictions. Every I/O port pin (RAx-RJx) can be used as a change notification pin (CNAx-CNJx). See Section 12.0 “I/O Ports” for more information. Shaded pins are 5V tolerant. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.  2015-2021 Microchip Technology Inc. DS60001320H-page 9 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 5: PIN NAMES FOR 124-PIN VTLA DEVICES (CONTINUED) 124-PIN VTLA (BOTTOM VIEW) A34 A17 PIC32MZ0512EF(E/F/K)124 PIC32MZ1024EF(G/H/M)124 PIC32MZ1024EF(E/F/K)124 PIC32MZ2048EF(G/H/M)124 B13 B1 Full Pin Name B41 B56 A51 A1 A68 Polarity Indicator Package Pin # B29 Package Pin # Full Pin Name B1 EBIA5/AN34/PMA5/RA5 B29 VSS B2 EBID6/AN16/PMD6/RE6 B30 D+ B3 EBIA6/AN22/RPC1/PMA6/RC1 B31 RPF2/SDA3/RF2 B4 AN36/ETXD1/RJ9 B32 ERXD0/RH8 B5 EBIWE/AN20/RPC3/PMWR/RC3 B33 ECOL/RH10 B6 AN14/C1IND/RPG6/SCK2/RG6 B34 EBIRDY1/SDA2/RA3 B7 EBIA3/AN12/C2IND/RPG8/SCL4/PMA3/RG8 B35 VDD B8 VDD B36 EBIA9/RPF4/SDA5/PMA9/RF4 B9 EBIA2/AN11/C2INC/RPG9/PMA2/RG9 B37 RPA14/SCL1/RA14 B10 AN25/RPE8/RE8 B38 EBIA15/RPD9/PMCS2/PMA15/RD9 B11 AN45/C1INA/RPB5/RB5 B39 EMDC/RPD11/RD11 B12 AN37/ERXCLK/EREFCLK/RJ11 B40 ERXDV/ECRSDV/RH13 B13 VSS B41 SOSCI/RPC13/RC13 B14 PGEC2/AN46/RPB6/RB6 B42 EBID14/RPD2/PMD14/RD2 B15 VREF-/CVREF-/AN27/RA9 B43 EBID12/RPD12/PMD12/RD12 B16 AVDD B44 ETXERR/RJ0 B17 AN38/ETXD2/RH0 B45 EBIRDY3/RJ2 B18 EBIA10/AN48/RPB8/PMA10/RB8 B46 SQICS1/RPD5/RD5 B19 EBIA13/CVREFOUT/AN5/RPB10/PMA13/RB10 B47 ETXCLK/RPD7/RD7 B20 VSS B48 VSS B21 TCK/EBIA19/AN29/RA1 B49 EBID10/RPF1/PMD10/RF1 B22 TDO/EBIA17/AN31/RPF12/RF12 B50 EBID8/RPG0/PMD8/RG0 B23 AN8/RB13 B51 TRD3/SQID3/RA7 B24 EBIA0/AN10/RPB15/OCFB/PMA0/RB15 B52 EBID0/PMD0/RE0 B25 VDD B53 VDD B26 AN41/ERXD1/RH5 B54 TRD2/SQID2/RG14 B27 AN32/AETXD0/RPD14/RD14 B55 TRD0/SQID0/RG13 B28 OSC1/CLKI/RC12 B56 EBID3/RPE3/PMD3/RE3 Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin Select (PPS)” for restrictions. Every I/O port pin (RAx-RJx) can be used as a change notification pin (CNAx-CNJx). See Section 12.0 “I/O Ports” for more information. Shaded pins are 5V tolerant. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS60001320H-page 10  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 6: PIN NAMES FOR 144-PIN TQFP DEVICES 144-PIN LQFP AND TQFP (TOP VIEW) PIC32MZ0512EF(E/F/K)144 PIC32MZ1024EF(G/H/M)144 PIC32MZ1024EF(E/F/K)144 PIC32MZ2048EF(G/H/M)144 144 1 Pin Number Full Pin Name Pin Number Full Pin Name 1 AN23/RG15 37 PGEC2/AN46/RPB6/RB6 2 EBIA5/AN34/PMA5/RA5 38 PGED2/AN47/RPB7/RB7 3 EBID5/AN17/RPE5/PMD5/RE5 39 VREF-/CVREF-/AN27/RA9 4 EBID6/AN16/PMD6/RE6 40 VREF+/CVREF+/AN28/RA10 5 EBID7/AN15/PMD7/RE7 41 AVDD 6 EBIA6/AN22/RPC1/PMA6/RC1 42 AVSS 7 AN35/ETXD0/RJ8 43 AN38/ETXD2/RH0 8 AN36/ETXD1/RJ9 44 AN39/ETXD3/RH1 9 EBIBS0/RJ12 45 EBIRP/RH2 10 EBIBS1/RJ10 46 RH3 11 EBIA12/AN21/RPC2/PMA12/RC2 47 EBIA10/AN48/RPB8/PMA10/RB8 12 EBIWE/AN20/RPC3/PMWR/RC3 48 EBIA7/AN49/RPB9/PMA7/RB9 13 EBIOE/AN19/RPC4/PMRD/RC4 49 CVREFOUT/AN5/RPB10/RB10 14 AN14/C1IND/RPG6/SCK2/RG6 50 AN6/RB11 15 AN13/C1INC/RPG7/SDA4/RG7 51 EBIA1/PMA1/RK1 16 AN12/C2IND/RPG8/SCL4/RG8 52 EBIA3/PMA3/RK2 17 VSS 53 EBIA17/RK3 18 VDD 54 VSS 19 EBIA16/RK0 55 VDD 20 MCLR 56 TCK/AN29/RA1 21 EBIA2/AN11/C2INC/RPG9/PMA2/RG9 57 TDI/AN30/RPF13/SCK5/RF13 22 TMS/AN24/RA0 58 TDO/AN31/RPF12/RF12 23 AN25/RPE8/RE8 59 AN7/RB12 24 AN26/RPE9/RE9 60 AN8/RB13 25 AN45/C1INA/RPB5/RB5 61 AN9/RPB14/SCK3/RB14 26 AN4/C1INB/RB4 62 AN10/RPB15/OCFB/RB15 27 AN37/ERXCLK/EREFCLK/RJ11 63 VSS 28 EBIA13/PMA13/RJ13 64 VDD 29 EBIA11/PMA11/RJ14 65 AN40/ERXERR/RH4 30 EBIA0/PMA0/RJ15 66 AN41/ERXD1/RH5 31 AN3/C2INA/RPB3/RB3 67 AN42/ERXD2/RH6 32 VSS 68 EBIA4/PMA4/RH7 33 VDD 69 AN32/RPD14/RD14 34 AN2/C2INB/RPB2/RB2 70 AN33/RPD15/SCK6/RD15 35 PGEC1/AN1/RPB1/RB1 71 OSC1/CLKI/RC12 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin Select (PPS)” for restrictions. Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 “I/O Ports” for more information. Shaded pins are 5V tolerant.  2015-2021 Microchip Technology Inc. DS60001320H-page 11 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 6: PIN NAMES FOR 144-PIN TQFP DEVICES (CONTINUED) 144-PIN LQFP AND TQFP (TOP VIEW) PIC32MZ0512EF(E/F/K)144 PIC32MZ1024EF(G/H/M)144 PIC32MZ1024EF(E/F/K)144 PIC32MZ2048EF(G/H/M)144 144 1 Pin Number Full Pin Name Pin Number Full Pin Name 36 PGED1/AN0/RPB0/RB0 72 OSC2/CLKO/RC15 73 VBUS 109 RPD1/SCK1/RD1 74 VUSB3V3 110 EBID14/RPD2/PMD14/RD2 75 VSS 111 EBID15/RPD3/PMD15/RD3 76 D- 112 EBID12/RPD12/PMD12/RD12 77 D+ 113 EBID13/PMD13/RD13 78 RPF3/USBID/RF3 114 ETXERR/RJ0 79 SDA3/RPF2/RF2 115 EMDIO/RJ1 80 SCL3/RPF8/RF8 116 EBIRDY3/RJ2 81 ERXD0/RH8 117 EBIA22/RJ3 82 ERXD3/RH9 118 SQICS0/RPD4/RD4 83 ECOL/RH10 119 SQICS1/RPD5/RD5 84 EBIRDY2/RH11 120 ETXEN/RPD6/RD6 85 SCL2/RA2 121 ETXCLK/RPD7/RD7 86 EBIRDY1/SDA2/RA3 122 VDD 87 EBIA14/PMCS1/PMA14/RA4 123 VSS 88 VDD 124 EBID11/RPF0/PMD11/RF0 89 VSS 125 EBID10/RPF1/PMD10/RF1 90 EBIA9/RPF4/SDA5/PMA9/RF4 126 EBIA21/RK7 91 EBIA8/RPF5/SCL5/PMA8/RF5 127 EBID9/RPG1/PMD9/RG1 92 EBIA18/RK4 128 EBID8/RPG0/PMD8/RG0 93 EBIA19/RK5 129 TRCLK/SQICLK/RA6 94 EBIA20/RK6 130 TRD3/SQID3/RA7 95 RPA14/SCL1/RA14 131 EBICS0/RJ4 96 RPA15/SDA1/RA15 132 EBICS1/RJ5 97 EBIA15/RPD9/PMCS2/PMA15/RD9 133 EBICS2/RJ6 98 RPD10/SCK4/RD10 134 EBICS3/RJ7 99 EMDC/RPD11/RD11 135 EBID0/PMD0/RE0 100 ECRS/RH12 136 VSS 101 ERXDV/ECRSDV/RH13 137 VDD 102 RH14 138 EBID1/PMD1/RE1 103 EBIA23/RH15 139 TRD2/SQID2/RG14 104 RPD0/RTCC/INT0/RD0 140 TRD1/SQID1/RG12 105 SOSCI/RPC13/RC13 141 TRD0/SQID0/RG13 106 SOSCO/RPC14/T1CK/RC14 142 EBID2/PMD2/RE2 107 VDD 143 EBID3/RPE3/PMD3/RE3 108 VSS 144 EBID4/AN18/PMD4/RE4 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin Select (PPS)” for restrictions. Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 “I/O Ports” for more information. Shaded pins are 5V tolerant. DS60001320H-page 12  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 7: PIN NAMES FOR 144-PIN TFBGA DEVICES 144-PIN TFBGA (BOTTOM VIEW) PIC32MZ0512EF(E/F/K)144 PIC32MZ1024EF(G/H/M)144 PIC32MZ1024EF(E/F/K)144 PIC32MZ2048EF(G/H/M)144 Pin Number Full Pin Name Pin Number Full Pin Name A12 AN23/RG15 B1 PGEC2/AN46/RPB6/RB6 B12 EBIA5/AN34/PMA5/RA5 C1 PGED2/AN47/RPB7/RB7 A11 EBID5/AN17/RPE5/PMD5/RE5 D2 VREF-/CVREF-/AN27/RA9 B11 EBID6/AN16/PMD6/RE6 D3 VREF+/CVREF+/AN28/RA10 B10 EBID7/AN15/PMD7/RE7 D1 AVDD A10 EBIA6/AN22/RPC1/PMA6/RC1 E4 AVSS C9 AN35/ETXD0/RJ8 E1 AN38/ETXD2/RH0 B9 AN36/ETXD1/RJ9 E2 AN39/ETXD3/RH1 A9 EBIBS0/RJ12 E3 EBIRP/RH2 A8 EBIBS1/RJ10 F4 RH3 B8 EBIA12/AN21/RPC2/PMA12/RC2 F3 EBIA10/AN48/RPB8/PMA10/RB8 C8 EBIWE/AN20/RPC3/PMWR/RC3 F2 EBIA7/AN49/RPB9/PMA7/RB9 D8 EBIOE/AN19/RPC4/PMRD/RC4 F1 CVREFOUT/AN5/RPB10/RB10 B7 AN14/C1IND/RPG6/SCK2/RG6 G1 AN6/RB11 C7 AN13/C1INC/RPG7/SDA4/RG7 G2 EBIA1/PMA1/RK1 D7 AN12/C2IND/RPG8/SCL4/RG8 G3 EBIA3/PMA3/RK2 D6 VSS G4 EBIA17/RK3 A7 VDD H4 VSS C6 EBIA16/RK0 H1 VDD B6 MCLR H2 TCK/AN29/RA1 A6 EBIA2/AN11/C2INC/RPG9/PMA2/RG9 H3 TDI/AN30/RPF13/SCK5/RF13 D5 TMS/AN24/RA0 J4 TDO/AN31/RPF12/RF12 A5 AN25/RPE8/RE8 J3 AN7/RB12 B5 AN26/RPE9/RE9 J2 AN8/RB13 C5 AN45/C1INA/RPB5/RB5 J1 AN9/RPB14/SCK3/RB14 A4 AN4/C1INB/RB4 K2 AN10/RPB15/OCFB/RB15 B4 AN37/ERXCLK/EREFCLK/RJ11 K4 VSS C4 EBIA13/PMA13/RJ13 K1 VDD C3 EBIA11/PMA11/RJ14 K3 AN40/ERXERR/RH4 B3 EBIA0/PMA0/RJ15 M3 AN41/ERXD1/RH5 C2 AN3/C2INA/RPB3/RB3 L3 AN42/ERXD2/RH6 D4 VSS L2 EBIA4/PMA4/RH7 A3 VDD M2 AN32/RPD14/RD14 B2 AN2/C2INB/RPB2/RB2 L1 AN33/RPD15/SCK6/RD15 A2 PGEC1/AN1/RPB1/RB1 M1 OSC1/CLKI/RC12 A1 PGED1/AN0/RPB0/RB0 N1 OSC2/CLKO/RC15 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin Select (PPS)” for restrictions. Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 “I/O Ports” for more information. Shaded pins are 5V tolerant.  2015-2021 Microchip Technology Inc. DS60001320H-page 13 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 7: PIN NAMES FOR 144-PIN TFBGA DEVICES (CONTINUED) 144-PIN TFBGA (BOTTOM VIEW) PIC32MZ0512EF(E/F/K)144 PIC32MZ1024EF(G/H/M)144 PIC32MZ1024EF(E/F/K)144 PIC32MZ2048EF(G/H/M)144 Pin Number Full Pin Name Pin Number Full Pin Name N2 VBUS M13 RPD1/SCK1/RD1 N3 VUSB3V3 L12 EBID14/RPD2/PMD14/RD2 L4 VSS L13 EBID15/RPD3/PMD15/RD3 N4 D- K13 EBID12/RPD12/PMD12/RD12 N5 D+ K12 EBID13/PMD13/RD13 M4 RPF3/USBID/RF3 J11 ETXERR/RJ0 M5 SDA3/RPF2/RF2 J12 EMDIO/RJ1 L5 SCL3/RPF8/RF8 J13 EBIRDY3/RJ2 K5 ERXD0/RH8 H13 EBIA22/RJ3 K6 ERXD3/RH9 H12 SQICS0/RPD4/RD4 L6 ECOL/RH10 H11 SQICS1/RPD5/RD5 M6 EBIRDY2/RH11 J10 ETXEN/RPD6/RD6 N6 SCL2/RA2 H10 ETXCLK/RPD7/RD7 M7 EBIRDY1/SDA2/RA3 G13 VDD L7 EBIA14/PMCS1/PMA14/RA4 G10 VSS N7 VDD G12 EBID11/RPF0/PMD11/RF0 K7 VSS G11 EBID10/RPF1/PMD10/RF1 K8 EBIA9/RPF4/SDA5/PMA9/RF4 F10 EBIA21/RK7 L8 EBIA8/RPF5/SCL5/PMA8/RF5 F11 EBID9/RPG1/PMD9/RG1 M8 EBIA18/RK4 F12 EBID8/RPG0/PMD8/RG0 N8 EBIA19/RK5 F13 TRCLK/SQICLK/RA6 K9 EBIA20/RK6 E13 TRD3/SQID3/RA7 L9 RPA14/SCL1/RA14 E12 EBICS0/RJ4 M9 RPA15/SDA1/RA15 E11 EBICS1/RJ5 N9 EBIA15/RPD9/PMCS2/PMA15/RD9 E10 EBICS2/RJ6 N10 RPD10/SCK4/RD10 D11 EBICS3/RJ7 M10 EMDC/RPD11/RD11 D10 EBID0/PMD0/RE0 L10 ECRS/RH12 D9 VSS K11 ERXDV/ECRSDV/RH13 D13 VDD L11 RH14 C10 EBID1/PMD1/RE1 M11 EBIA23/RH15 D12 TRD2/SQID2/RG14 N11 RPD0/RTCC/INT0/RD0 C11 TRD1/SQID1/RG12 N12 SOSCI/RPC13/RC13 C12 TRD0/SQID0/RG13 M12 SOSCO/RPC14/T1CK/RC14 C13 EBID2/PMD2/RE2 N13 VDD B13 EBID3/RPE3/PMD3/RE3 K10 VSS A13 EBID4/AN18/PMD4/RE4 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 12.4 “Peripheral Pin Select (PPS)” for restrictions. Every I/O port pin (RAx-RKx) can be used as a change notification pin (CNAx-CNKx). See Section 12.0 “I/O Ports” for more information. Shaded pins are 5V tolerant. DS60001320H-page 14  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Table of Content 1.0 Device Overview ....................................................................................................................................................................... 21 2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 45 3.0 CPU ........................................................................................................................................................................................... 55 4.0 Memory Organization ................................................................................................................................................................. 75 5.0 Flash Program Memory ........................................................................................................................................................... 113 6.0 Resets ...................................................................................................................................................................................... 123 7.0 CPU Exceptions and Interrupt Controller ................................................................................................................................. 129 8.0 Oscillator Configuration ............................................................................................................................................................ 167 9.0 Prefetch Module ....................................................................................................................................................................... 183 10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 187 11.0 Hi-Speed USB with On-The-Go (OTG) .................................................................................................................................... 211 12.0 I/O Ports ................................................................................................................................................................................... 261 13.0 Timer1 297 14.0 Timer2/3, Timer4/5, Timer6/7, and Timer8/9 ........................................................................................................................... 301 15.0 Deadman Timer (DMT) ............................................................................................................................................................ 307 16.0 Watchdog Timer (WDT) ........................................................................................................................................................... 317 17.0 Input Capture ........................................................................................................................................................................... 321 18.0 Output Compare ...................................................................................................................................................................... 325 19.0 Serial Peripheral Interface (SPI) and Inter-IC Sound (I2S) ...................................................................................................... 331 20.0 Serial Quad Interface (SQI) ..................................................................................................................................................... 341 21.0 Inter-Integrated Circuit (I2C)..................................................................................................................................................... 369 22.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 377 23.0 Parallel Host Port (PMP) .......................................................................................................................................................... 385 24.0 External Bus Interface (EBI) .................................................................................................................................................... 399 25.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 407 26.0 Crypto Engine .......................................................................................................................................................................... 417 27.0 Random Number Generator (RNG) ......................................................................................................................................... 437 28.0 12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) ........................................ 443 29.0 Controller Area Network (CAN) ................................................................................................................................................ 501 30.0 Ethernet Controller ................................................................................................................................................................... 539 31.0 Comparator .............................................................................................................................................................................. 583 32.0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 587 33.0 Power-Saving Features .......................................................................................................................................................... 591 34.0 Special Features ...................................................................................................................................................................... 597 35.0 Instruction Set .......................................................................................................................................................................... 621 36.0 Development Support .............................................................................................................................................................. 623 37.0 Electrical Characteristics .......................................................................................................................................................... 627 38.0 Extended Temperature Electrical Characteristics .................................................................................................................... 679 39.0 252 MHz Electrical Characteristics .......................................................................................................................................... 685 40.0 AC and DC Characteristics Graphs ......................................................................................................................................... 691 41.0 Packaging Information ............................................................................................................................................................. 693 42.0 Product Identification System .................................................................................................................................................. 762 Customer Support ............................................................................................................................................................................. 759 Customer Change Notification Service ............................................................................................................................................. 759 The Microchip Web Site .................................................................................................................................................................... 759  2015-2021 Microchip Technology Inc. DS60001320H-page 15 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS60001320H-page 16  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Referenced Sources This device data sheet is based on the following individual sections of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note: • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • To access the following documents, browse the documentation section of the Microchip web site (www.microchip.com). Section 1. “Introduction” (DS60001127) Section 7. “Resets” (DS60001118) Section 8. “Interrupt Controller” (DS60001108) Section 9. “Watchdog, Deadman, and Power-up Timers” (DS60001114) Section 10. “Power-Saving Features” (DS60001130) Section 12. “I/O Ports” (DS60001120) Section 13. “Parallel Master Port (PMP)” (DS60001128) Section 14. “Timers” (DS60001105) Section 15. “Input Capture” (DS60001122) Section 16. “Output Compare” (DS60001111) Section 19. “Comparator” (DS60001110) Section 20. “Comparator Voltage Reference (CVREF)” (DS60001109) Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107) Section 22. “12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)” (DS60001344) Section 23. “Serial Peripheral Interface (SPI)” (DS60001106) Section 24. “Inter-Integrated Circuit (I2C)” (DS60001116) Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125) Section 31. “Direct Memory Access (DMA) Controller” (DS60001117) Section 32. “Configuration” (DS60001124) Section 33. “Programming and Diagnostics” (DS60001129) Section 34. “Controller Area Network (CAN)” (DS60001154) Section 35. “Ethernet Controller” (DS60001155) Section 41. “Prefetch Module for Devices with L1 CPU Cache” (DS60001183) Section 42. “Oscillators with Enhanced PLL” (DS60001250) Section 46. “Serial Quad Interface (SQI)” (DS60001244) Section 47. “External Bus Interface (EBI)” (DS60001245) Section 48. “Memory Organization and Permissions” (DS60001214) Section 49. “Crypto Engine (CE) and Random Number Generator (RNG)” (DS60001246) Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192) Section 51. “Hi-Speed USB with On-The-Go (OTG)” (DS60001326) Section 52. “Flash Program Memory with Support for Live Update” (DS60001193)  2015-2021 Microchip Technology Inc. DS60001320H-page 17 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320H-page 18  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 1.0 DEVICE OVERVIEW Note: This data sheet contains device-specific information for PIC32MZ EF devices. This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). FIGURE 1-1: Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MZ EF family of devices. Table 1-21 through Table 1-22 list the pinout I/O descriptions for the pins shown in the device pin tables (see Table 2 through Table 6). PIC32MZ EF FAMILY BLOCK DIAGRAM OSC2/CLKO OSC1/CLKI POSC/SOSC Oscillators FRC/LPRC Oscillators DIVIDERS Power-on Reset SYSCLK 6 PLL-USB PBCLKx Timing Generation MCLR Oscillator Start-up Timer Precision Band Gap Reference PLL VDD, VSS Power-up Timer Voltage Regulator PORTA Watchdog Timer PORTB Brown-out Reset PORTC PORTD PORTE PORTF EVIC PORTH PORTJ Ethernet Controller CAN1 CAN2 I-Cache D-Cache SQI DMAC M-Class Core HS USB INT MIPS32® CRYPTO EJTAG PORTG PORTK Peripheral Bus 5 System Bus I/F I1, I2 I3, I5, I14 T12 I12, T11 I7 T10 I4 I6 I11 I10 I8 I9 T9 Peripheral Bus 4 T8 System Bus Peripheral Bus 1 CFG PPS ICD WDT DMT RTCC Note: Flash Controller T1 Flash Prefetch Cache T2 T3 Data Ram Bank 1 Data Ram Bank 2 T4 T13 128 140-bit wide Dual Panel Flash Memory CVREF JTAG BSCAN T7 Peripheral Bus 3 Timer1-9 128 PFM Flash Wrapper and ECC T6 Peripheral Bus 2 RNG I13 EBI T5 SPI1-6 OC1-9 I2C1-5 IC1-9 UART1-6 Comparator 1-2 PMP 6 S&H SAR ADC Not all features are available on all devices. Refer to TABLE 1: “PIC32MZ EF Family Features” for the list of features by device.  2015-2021 Microchip Technology Inc. DS60001320H-page 19 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-1: ADC PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type Description A1 I Analog Analog Input Channels A2 I Analog 144-pin 144-pin TQFP/ TFBGA LQFP 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA AN0 16 25 A1 A18 36 AN1 15 24 A2 A17 35 Pin Name AN2 14 23 B2 A16 34 B2 I Analog AN3 13 22 C3 A14 31 C2 I Analog AN4 12 21 B3 A13 26 A4 I Analog AN5 23 34 E1 B19 49 F1 I Analog AN6 24 35 F3 A24 50 G1 I Analog AN7 27 41 G2 A27 59 J3 I Analog AN8 28 42 H2 B23 60 J2 I Analog AN9 29 43 G3 A28 61 J1 I Analog AN10 30 44 F4 B24 62 K2 I Analog AN11 10 16 D4 B9 21 A6 I Analog AN12 6 12 C5 B7 16 D7 I Analog AN13 5 11 D6 A8 15 C7 I Analog AN14 4 10 C6 B6 14 B7 I Analog AN15 3 5 C7 A4 5 B10 I Analog AN16 2 4 C8 B2 4 B11 I Analog AN17 1 3 B8 A3 3 A11 I Analog AN18 64 100 B9 A67 144 A13 I Analog AN19 — 9 B6 A7 13 D8 I Analog AN20 — 8 A6 B5 12 C8 I Analog AN21 — 7 A7 A6 11 B8 I Analog AN22 — 6 B7 B3 6 A10 I Analog AN23 — 1 A9 A2 1 A12 I Analog AN24 — 17 C4 A11 22 D5 I Analog AN25 — 18 A3 B10 23 A5 I Analog AN26 — 19 A4 A12 24 B5 I Analog AN27 — 28 C2 B15 39 D2 I Analog AN28 — 29 D2 A20 40 D3 I Analog AN29 — 38 E5 B21 56 H2 I Analog AN30 — 39 F2 A26 57 H3 I Analog AN31 — 40 G1 B22 58 J4 I Analog AN32 — 47 J2 B27 69 M2 I Analog AN33 — 48 J1 A32 70 L1 I Analog AN34 — 2 A8 B1 2 B12 I Analog AN35 — — — A5 7 C9 I Analog Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer DS60001320H-page 20 Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-1: ADC PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA 144-pin 144-pin TQFP/ TFBGA LQFP Pin Type Buffer Type Description Analog Input Channels AN36 — — — B4 8 B9 I Analog AN37 — — — B12 27 B4 I Analog AN38 — — — B17 43 E1 I Analog AN39 — — — A22 44 E2 I Analog AN40 — — — A30 65 K3 I Analog AN41 — — — B26 66 M3 I Analog AN42 — — — A31 67 L3 I Analog AN45 11 20 B4 B11 25 C5 I Analog AN46 17 26 B1 B14 37 B1 I Analog AN47 18 27 C1 A19 38 C1 I Analog AN48 21 32 E3 B18 47 F3 I Analog AN49 22 33 E2 A23 48 F2 I Analog Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer  2015-2021 Microchip Technology Inc. Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input DS60001320H-page 21 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-2: OSCILLATOR PINOUT I/O DESCRIPTIONS Pin Number 144-pin 144-pin TQFP/ TFBGA LQFP Pin Type 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA CLKI 31 49 K1 B28 71 M1 I CLKO 32 50 K2 A33 72 N1 O OSC1 31 49 K1 B28 71 M1 I OSC2 32 50 K2 A33 72 N1 O SOSCI 47 72 K9 B41 105 N12 I SOSCO 48 73 K10 A49 106 M12 O Pin Name REFCLKI1 PPS PPS PPS PPS REFCLKI3 PPS PPS PPS PPS REFCLKI4 PPS PPS PPS PPS REFCLKO1 PPS PPS PPS PPS REFCLKO3 PPS PPS PPS PPS REFCLKO4 PPS PPS PPS PPS Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer TABLE 1-3: PPS PPS PPS PPS PPS PPS Buffer Type Description ST/CMOS External clock source input. Always associated with OSC1 pin function. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. — 32.768 low-power oscillator crystal output. — Reference Clock Generator Inputs 1-4 — PPS I PPS I PPS I — PPS O — PPS O — PPS O — Analog = Analog input O = Output PPS = Peripheral Pin Select Reference Clock Generator Outputs 1-4 P = Power I = Input IC1 THROUGH IC9 PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type PPS I ST PPS I ST PPS PPS I ST PPS PPS I ST PPS PPS PPS I ST PPS PPS PPS PPS I ST PPS PPS PPS PPS PPS I ST PPS PPS PPS PPS PPS PPS I ST PPS PPS PPS PPS PPS PPS I ST 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA IC1 PPS PPS PPS PPS PPS IC2 PPS PPS PPS PPS PPS IC3 PPS PPS PPS PPS IC4 PPS PPS PPS PPS IC5 PPS PPS PPS IC6 PPS PPS IC7 PPS IC8 IC9 Pin Name 144-pin 144-pin TQFP/ TFBGA LQFP Description Input Capture Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer DS60001320H-page 22 Analog = Analog input O = Output PPS = Peripheral Pin Select Input Capture Inputs 1-9 P = Power I = Input  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-4: OC1 THROUGH OC9 PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type PPS O — PPS O — PPS PPS O — PPS PPS O — PPS PPS PPS O — PPS PPS PPS PPS O — PPS PPS PPS PPS PPS O — PPS PPS PPS PPS PPS PPS O — OC9 PPS PPS PPS PPS PPS PPS O — OCFA PPS PPS PPS PPS PPS PPS I ST Output Compare Fault A Input OCFB 30 44 F4 B24 62 K2 I ST Output Compare Fault B Input 144-pin 144-pin TQFP/ TFBGA LQFP 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA OC1 PPS PPS PPS PPS PPS OC2 PPS PPS PPS PPS PPS OC3 PPS PPS PPS PPS OC4 PPS PPS PPS PPS OC5 PPS PPS PPS OC6 PPS PPS OC7 PPS OC8 Pin Name Description Output Compare Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer TABLE 1-5: Analog = Analog input O = Output PPS = Peripheral Pin Select Output Compare Outputs 1-9 P = Power I = Input EXTERNAL INTERRUPTS PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type N11 I ST External Interrupt 0 PPS I ST External Interrupt 1 PPS I ST External Interrupt 2 PPS PPS I ST External Interrupt 3 PPS PPS I ST External Interrupt 4 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA INT0 46 71 J8 A48 104 INT1 PPS PPS PPS PPS PPS INT2 PPS PPS PPS PPS PPS INT3 PPS PPS PPS PPS INT4 PPS PPS PPS PPS Pin Name 144-pin 144-pin TQFP/ TFBGA LQFP Description External Interrupts Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer  2015-2021 Microchip Technology Inc. Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input DS60001320H-page 23 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type Description D5 I/O ST PORTA is a bidirectional I/O port H2 I/O ST 85 N6 I/O ST 86 M7 I/O ST 87 L7 I/O ST ST 144-pin 144-pin TQFP/ TFBGA LQFP 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA RA0 — 17 C4 A11 22 RA1 — 38 E5 B21 56 RA2 — 59 H5 A41 RA3 — 60 J5 B34 RA4 — 61 H6 A42 Pin Name PORTA RA5 — 2 A8 B1 2 B12 I/O RA6 — 89 E9 A61 129 F13 I/O ST RA7 — 90 E10 B51 130 E13 I/O ST RA9 — 28 C2 B15 39 D2 I/O ST RA10 — 29 D2 A20 40 D3 I/O ST RA14 — 66 K6 B37 95 L9 I/O ST RA15 — 67 J6 A45 96 M9 I/O ST PORTB RB0 16 25 A1 A18 36 A1 I/O ST RB1 15 24 A2 A17 35 A2 I/O ST RB2 14 23 B2 A16 34 B2 I/O ST RB3 13 22 C3 A14 31 C2 I/O ST RB4 12 21 B3 A13 26 A4 I/O ST RB5 11 20 B4 B11 25 C5 I/O ST RB6 17 26 B1 B14 37 B1 I/O ST RB7 18 27 C1 A19 38 C1 I/O ST RB8 21 32 E3 B18 47 F3 I/O ST RB9 22 33 E2 A23 48 F2 I/O ST RB10 23 34 E1 B19 49 F1 I/O ST RB11 24 35 F3 A24 50 G1 I/O ST RB12 27 41 G2 A27 59 J3 I/O ST RB13 28 42 H2 B23 60 J2 I/O ST RB14 29 43 G3 A28 61 J1 I/O ST RB15 30 44 F4 B24 62 K2 I/O ST RC1 — 6 B7 B3 6 A10 I/O ST RC2 — 7 A7 A6 11 B8 I/O ST RC3 — 8 A6 B5 12 C8 I/O ST RC4 — 9 B6 A7 13 D8 I/O ST RC12 31 49 K1 B28 71 M1 I/O ST RC13 47 72 K9 B41 105 N12 I/O ST RC14 48 73 K10 A49 106 M12 I/O ST 32 50 K2 A33 72 N1 I/O ST PORTB is a bidirectional I/O port PORTC RC15 Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer DS60001320H-page 24 Analog = Analog input O = Output PPS = Peripheral Pin Select PORTC is a bidirectional I/O port P = Power I = Input  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type N11 I/O ST M13 I/O ST 144-pin 144-pin TQFP/ TFBGA LQFP 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA RD0 46 71 J8 A48 104 RD1 49 76 H10 A52 109 RD2 50 77 H9 B42 110 L12 I/O ST RD3 51 78 H8 A53 111 L13 I/O ST ST Pin Name Description PORTD RD4 52 81 G8 A56 118 H12 I/O RD5 53 82 G9 B46 119 H11 I/O ST RD6 — — — A57 120 J10 I/O ST RD7 — — — B47 121 H10 I/O ST RD9 43 68 K7 B38 97 N9 I/O ST RD10 44 69 J7 A46 98 N10 I/O ST RD11 45 70 K8 B39 99 M10 I/O ST RD12 — 79 H7 B43 112 K13 I/O ST RD13 — 80 G7 A54 113 K12 I/O ST RD14 — 47 J2 B27 69 M2 I/O ST RD15 — 48 J1 A32 70 L1 I/O ST PORTD is a bidirectional I/O port PORTE RE0 58 91 E7 B52 135 D10 I/O ST RE1 61 94 D8 A64 138 C10 I/O ST RE2 62 98 B10 A66 142 C13 I/O ST RE3 63 99 A10 B56 143 B13 I/O ST RE4 64 100 B9 A67 144 A13 I/O ST RE5 1 3 B8 A3 3 A11 I/O ST RE6 2 4 C8 B2 4 B11 I/O ST RE7 3 5 C7 A4 5 B10 I/O ST RE8 — 18 A3 B10 23 A5 I/O ST RE9 — 19 A4 A12 24 B5 I/O ST PORTE is a bidirectional I/O port PORTF RF0 56 85 F8 A59 124 G12 I/O ST RF1 57 86 F9 B49 125 G11 I/O ST RF2 — 57 F5 B31 79 M5 I/O ST RF3 38 56 J4 A38 78 M4 I/O ST RF4 41 64 F6 B36 90 K8 I/O ST RF5 42 65 G6 A44 91 L8 I/O ST RF8 — 58 G5 A39 80 L5 I/O ST RF12 — 40 G1 B22 58 J4 I/O ST RF13 — 39 F2 A26 57 H3 I/O ST Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer  2015-2021 Microchip Technology Inc. Analog = Analog input O = Output PPS = Peripheral Pin Select PORTF is a bidirectional I/O port P = Power I = Input DS60001320H-page 25 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type F12 I/O ST F11 I/O ST 14 B7 I/O ST 15 C7 I/O ST D7 I/O ST 21 A6 I/O ST 140 C11 I/O ST 141 C12 I/O ST 139 D12 I/O ST 1 A12 I/O ST 144-pin 144-pin TQFP/ TFBGA LQFP 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA RG0 — 88 E8 B50 128 RG1 — 87 F10 A60 127 RG6 4 10 C6 B6 RG7 5 11 D6 A8 RG8 6 12 C5 B7 16 RG9 10 16 D4 B9 RG12 — 96 C9 A65 RG13 — 97 C10 B55 RG14 — 95 D9 B54 RG15 — 1 A9 A2 Pin Name Description PORTG PORTG is a bidirectional I/O port PORTH RH0 — — — B17 43 E1 I/O ST RH1 — — — A22 44 E2 I/O ST RH2 — — — — 45 E3 I/O ST RH3 — — — — 46 F4 I/O ST RH4 — — — A30 65 K3 I/O ST RH5 — — — B26 66 M3 I/O ST RH6 — — — A31 67 L3 I/O ST RH7 — — — — 68 L2 I/O ST RH8 — — — B32 81 K5 I/O ST RH9 — — — A40 82 K6 I/O ST RH10 — — — B33 83 L6 I/O ST RH11 — — — — 84 M6 I/O ST RH12 — — — A47 100 L10 I/O ST RH13 — — — B40 101 K11 I/O ST RH14 — — — — 102 L11 I/O ST RH15 — — — — 103 M11 I/O ST PORTH is a bidirectional I/O port PORTJ RJ0 — — — B44 114 J11 I/O ST RJ1 — — — A55 115 J12 I/O ST RJ2 — — — B45 116 J13 I/O ST RJ3 — — — — 117 H13 I/O ST RJ4 — — — A62 131 E12 I/O ST RJ5 — — — — 132 E11 I/O ST RJ6 — — — — 133 E10 I/O ST RJ7 — — — — 134 D11 I/O ST RJ8 — — — A5 7 C9 I/O ST RJ9 — — — B4 8 B9 I/O ST RJ10 — — — — 10 A8 I/O ST RJ11 — — — B12 27 B4 I/O ST RJ12 — — — — 9 A9 I/O ST RJ13 — — — — 28 C4 I/O ST RJ14 — — — — 29 C3 I/O ST RJ15 — — — — 30 B3 I/O ST Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer DS60001320H-page 26 Analog = Analog input O = Output PPS = Peripheral Pin Select PORTJ is a bidirectional I/O port P = Power I = Input  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-6: PORTA THROUGH PORTK PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type Description C6 I/O ST PORTK is a bidirectional I/O port G2 I/O ST G3 I/O ST G4 I/O ST 92 M8 I/O ST — 93 N8 I/O ST — 94 K9 I/O ST — 126 F10 I/O ST 144-pin 144-pin TQFP/ TFBGA LQFP 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA RK0 — — — — 19 RK1 — — — — 51 RK2 — — — — 52 RK3 — — — — 53 RK4 — — — — RK5 — — — RK6 — — — RK7 — — — Pin Name PORTK Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer  2015-2021 Microchip Technology Inc. Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input DS60001320H-page 27 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-7: TIMER1 THROUGH TIMER9 AND RTCC PINOUT I/O DESCRIPTIONS Pin Number 144-pin 144-pin TQFP/ TFBGA LQFP Pin Type Buffer Type 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA T1CK 48 73 K10 A49 106 M12 I ST Timer1 External Clock Input T2CK PPS PPS PPS PPS PPS PPS I ST Timer2 External Clock Input T3CK PPS PPS PPS PPS PPS PPS I ST Timer3 External Clock Input T4CK PPS PPS PPS PPS PPS PPS I ST Timer4 External Clock Input T5CK PPS PPS PPS PPS PPS PPS I ST Timer5 External Clock Input T6CK PPS PPS PPS PPS PPS PPS I ST Timer6 External Clock Input T7CK PPS PPS PPS PPS PPS PPS I ST Timer7 External Clock Input T8CK PPS PPS PPS PPS PPS PPS I ST Timer8 External Clock Input T9CK PPS PPS PPS PPS PPS PPS I ST Timer9 External Clock Input O — Real-Time Clock Alarm/Seconds Output Pin Name Description Timer1 through Timer9 Real-Time Clock and Calendar RTCC Legend: 46 71 J8 A48 CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer DS60001320H-page 28 104 N11 Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-8: UART1 THROUGH UART6 PINOUT I/O DESCRIPTIONS Pin Number 144-pin 144-pin TQFP/ TFBGA LQFP Pin Type Buffer Type 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA U1RX PPS PPS PPS PPS PPS PPS I ST UART1 Receive U1TX PPS PPS PPS PPS PPS PPS O — UART1 Transmit Pin Name 124-pin VTLA Description Universal Asynchronous Receiver Transmitter 1 U1CTS PPS PPS PPS PPS PPS PPS I ST UART1 Clear to Send U1RTS PPS PPS PPS PPS PPS PPS O — UART1 Ready to Send U2RX PPS PPS PPS PPS PPS PPS I ST UART2 Receive U2TX PPS PPS PPS PPS PPS PPS O — UART2 Transmit U2CTS PPS PPS PPS PPS PPS PPS I ST UART2 Clear To Send U2RTS PPS PPS PPS PPS PPS PPS O — UART2 Ready To Send U3RX PPS PPS PPS PPS PPS PPS I ST UART3 Receive U3TX PPS PPS PPS PPS PPS PPS O — UART3 Transmit U3CTS PPS PPS PPS PPS PPS PPS I ST UART3 Clear to Send U3RTS PPS PPS PPS PPS PPS PPS O — UART3 Ready to Send U4RX PPS PPS PPS PPS PPS PPS I ST UART4 Receive U4TX PPS PPS PPS PPS PPS PPS O — UART4 Transmit U4CTS PPS PPS PPS PPS PPS PPS I ST UART4 Clear to Send U4RTS PPS PPS PPS PPS PPS PPS O — UART4 Ready to Send U5RX PPS PPS PPS PPS PPS PPS I ST UART5 Receive U5TX PPS PPS PPS PPS PPS PPS O — UART5 Transmit U5CTS PPS PPS PPS PPS PPS PPS I ST UART5 Clear to Send U5RTS PPS PPS PPS PPS PPS PPS O — UART5 Ready to Send U6RX PPS PPS PPS PPS PPS PPS I ST UART6 Receive U6TX PPS PPS PPS PPS PPS PPS O — UART6 Transmit U6CTS PPS PPS PPS PPS PPS PPS I ST UART6 Clear to Send U6RTS PPS PPS PPS PPS PPS PPS O — UART6 Ready to Send Universal Asynchronous Receiver Transmitter 2 Universal Asynchronous Receiver Transmitter 3 Universal Asynchronous Receiver Transmitter 4 Universal Asynchronous Receiver Transmitter 5 Universal Asynchronous Receiver Transmitter 6 Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer  2015-2021 Microchip Technology Inc. Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input DS60001320H-page 29 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-9: SPI1 THROUGH SPI 6 PINOUT I/O DESCRIPTIONS Pin Number Pin Name 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA 49 76 H10 A52 144-pin 144-pin TQFP/ TFBGA LQFP Pin Type Buffer Type Description Serial Peripheral Interface 1 SCK1 109 M13 I/O ST SPI1 Synchronous Serial Clock Input/Output SDI1 PPS PPS PPS PPS PPS PPS I ST SPI1 Data In SDO1 PPS PPS PPS PPS PPS PPS O — SPI1 Data Out SS1 PPS PPS PPS PPS PPS PPS I/O ST SPI1 Client Synchronization Or Frame Pulse I/O 4 10 C6 B6 I/O ST SPI2 Synchronous Serial Clock Input/output Serial Peripheral Interface 2 SCK2 14 B7 SDI2 PPS PPS PPS PPS PPS PPS I ST SPI2 Data In SDO2 PPS PPS PPS PPS PPS PPS O — SPI2 Data Out SS2 PPS PPS PPS PPS PPS PPS I/O ST SPI2 Client Synchronization Or Frame Pulse I/O 29 43 G3 A28 I/O ST SPI3 Synchronous Serial Clock Input/Output Serial Peripheral Interface 3 SCK3 61 J1 SDI3 PPS PPS PPS PPS PPS PPS I ST SPI3 Data In SDO3 PPS PPS PPS PPS PPS PPS O — SPI3 Data Out SS3 PPS PPS PPS PPS PPS PPS I/O ST SPI3 Client Synchronization Or Frame Pulse I/O 44 69 J7 A46 I/O ST SPI4 Synchronous Serial Clock Input/Output Serial Peripheral Interface 4 SCK4 98 N10 SDI4 PPS PPS PPS PPS PPS PPS I ST SPI4 Data In SDO4 PPS PPS PPS PPS PPS PPS O — SPI4 Data Out SS4 PPS PPS PPS PPS PPS PPS I/O ST SPI4 Client Synchronization Or Frame Pulse I/O — 39 F2 A26 I/O ST SPI5 Synchronous Serial Clock Input/Output Serial Peripheral Interface 5 SCK5 57 H3 SDI5 — PPS PPS PPS PPS PPS I ST SPI5 Data In SDO5 — PPS PPS PPS PPS PPS O — SPI5 Data Out SS5 — PPS PPS PPS PPS PPS I/O ST SPI5 Client Synchronization Or Frame Pulse I/O SCK6 — 48 J1 A32 I/O ST SPI6 Synchronous Serial Clock Input/Output Serial Peripheral Interface 6 70 L1 SDI6 — PPS PPS PPS PPS PPS I ST SPI6 Data In SDO6 — PPS PPS PPS PPS PPS O — SPI6 Data Out SS6 — PPS PPS PPS PPS PPS I/O ST SPI6 Client Synchronization Or Frame Pulse I/O Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer DS60001320H-page 30 Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-10: I2C1 THROUGH I2C5 PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type L9 I/O ST I2C1 Synchronous Serial Clock Input/Output M9 I/O ST I2C1 Synchronous Serial Data Input/Output N6 I/O ST I2C2 Synchronous Serial Clock Input/Output M7 I/O ST I2C2 Synchronous Serial Data Input/Output L5 I/O ST I2C3 Synchronous Serial Clock Input/Output M5 I/O ST I2C3 Synchronous Serial Data Input/Output D7 I/O ST I2C4 Synchronous Serial Clock Input/Output C7 I/O ST I2C4 Synchronous Serial Data Input/Output L8 I/O ST I2C5 Synchronous Serial Clock Input/Output K8 I/O ST I2C5 Synchronous Serial Data Input/Output 144-pin 144-pin TQFP/ TFBGA LQFP 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA SCL1 44 66 K6 B37 95 SDA1 43 67 J6 A45 96 SCL2 — 59 H5 A41 85 SDA2 — 60 J5 B34 86 SCL3 51 58 G5 A39 80 SDA3 50 57 F5 B31 79 SCL4 6 12 C5 B7 16 SDA4 5 11 D6 A8 15 SCL5 42 65 G6 A44 91 SDA5 41 64 F6 B36 90 Pin Name Description Inter-Integrated Circuit 1 Inter-Integrated Circuit 2 Inter-Integrated Circuit 3 Inter-Integrated Circuit 4 Inter-Integrated Circuit 5 Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer TABLE 1-11: Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input COMPARATOR 1, COMPARATOR 2 AND CVREF PINOUT I/O DESCRIPTIONS Pin Number Buffer Type 100-pin TQFP 100-pin TFBGA CVREF+ 16 29 D2 A20 40 D3 I Analog Comparator Voltage Reference (High) Input CVREF- 15 28 C2 B15 39 D2 I Analog Comparator Voltage Reference (Low) Input CVREFOUT 23 34 E1 B19 49 F1 O Analog Comparator Voltage Reference Output C1INA 11 20 B4 B11 25 C5 I Analog Comparator 1 Positive Input C1INB 12 21 B3 A13 26 A4 I Analog C1INC 5 11 D6 A8 15 C7 I Analog Comparator 1 Selectable Negative Input 124-pin VTLA 144-pin 144-pin TQFP/ TFBGA LQFP Pin Type 64-pin QFN/ TQFP Pin Name Description Comparator Voltage Reference Comparator 1 C1IND 4 10 C6 B6 14 B7 I Analog C1OUT PPS PPS PPS PPS PPS PPS O — Comparator 1 Output Comparator 2 Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer  2015-2021 Microchip Technology Inc. Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input DS60001320H-page 31 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-11: COMPARATOR 1, COMPARATOR 2 AND CVREF PINOUT I/O DESCRIPTIONS Pin Number 64-pin QFN/ TQFP 100-pin TQFP C2INA 13 C2INB 14 C2INC 10 Pin Name Pin Type Buffer Type C2 I Analog Comparator 2 Positive Input B2 I Analog A6 I Analog Comparator 2 Selectable Negative Input 144-pin 144-pin TQFP/ TFBGA LQFP 100-pin TFBGA 124-pin VTLA 22 B2 A14 31 23 C3 A16 34 16 D4 B9 21 C2IND 6 12 C5 B7 16 D7 I Analog C2OUT PPS PPS PPS PPS PPS PPS O — Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer DS60001320H-page 32 Analog = Analog input O = Output PPS = Peripheral Pin Select Description Comparator 2 Output P = Power I = Input  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-12: PMP PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type B3 I/O TTL/ST Parallel Host Port Address bit 0 Input (Buffered Client modes) and Output (Host modes) G2 I/O TTL/ST Parallel Host Port Address bit 1 Input (Buffered Client modes) and Output (Host modes) 144-pin 144-pin TQFP/ TFBGA LQFP 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA PMA0 30 44 F4 B24 30 PMA1 29 43 G3 A28 51 PMA2 10 16 D4 B9 21 A6 O — PMA3 6 12 C5 B7 52 G3 O — PMA4 5 11 D6 A8 68 L2 O — PMA5 4 2 A8 B1 2 B12 O — PMA6 16 6 B7 B3 6 A10 O — PMA7 22 33 E2 A23 48 F2 O — PMA8 42 65 G6 A44 91 L8 O — Pin Name Description Parallel Host Port Address (Demultiplexed Host modes) PMA9 41 64 F6 B36 90 K8 O — PMA10 21 32 E3 B18 47 F3 O — PMA11 27 41 G2 A27 29 C3 O — PMA12 24 7 A7 A6 11 B8 O — PMA13 23 34 E1 B19 28 C4 O — PMA14 45 61 H6 A42 87 L7 O — PMA15 43 68 K7 B38 97 N9 O — PMCS1 45 61 H6 A42 87 L7 O — Parallel Host Port Chip Select 1 Strobe PMCS2 43 68 K7 B38 97 N9 O — Parallel Host Port Chip Select 2 Strobe PMD0 58 91 E7 B52 135 D10 I/O TTL/ST PMD1 61 94 D8 A64 138 C10 I/O TTL/ST PMD2 62 98 B10 A66 142 C13 I/O TTL/ST Parallel Host Port Data (Demultiplexed Host mode) or Address/ Data (Multiplexed Host modes) PMD3 63 99 A10 B56 143 B13 I/O TTL/ST PMD4 64 100 B9 A67 144 A13 I/O TTL/ST TTL/ST PMD5 1 3 B8 A3 3 A11 I/O PMD6 2 4 C8 B2 4 B11 I/O TTL/ST PMD7 3 5 C7 A4 5 B10 I/O TTL/ST PMD8 — 88 E9 B50 128 F12 I/O TTL/ST PMD9 — 87 F10 A60 127 F11 I/O TTL/ST PMD10 — 86 F9 B49 125 G11 I/O TTL/ST PMD11 — 85 F8 A59 124 G12 I/O TTL/ST PMD12 — 79 H7 B43 112 K13 I/O TTL/ST PMD13 — 80 G7 A54 113 K12 I/O TTL/ST PMD14 — 77 H9 B42 110 L12 I/O TTL/ST PMD15 — 78 H8 A53 111 L13 I/O TTL/ST PMALL 30 44 F4 B24 30 B3 O — Parallel Host Port Address Latch Enable Low Byte (Multiplexed Host modes) PMALH 29 43 G3 A28 51 G2 O — Parallel Host Port Address Latch Enable High Byte (Multiplexed Host modes) PMRD 53 9 B6 A7 13 D8 O — Parallel Host Port Read Strobe PMWR 52 8 A6 B5 12 C8 O — Parallel Host Port Write Strobe Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer  2015-2021 Microchip Technology Inc. Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input DS60001320H-page 33 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-13: EBI PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type B3 O — G2 O — A6 O — G3 O — L2 O — 2 B12 O — 6 A10 O — A23 48 F2 O — G6 A44 91 L8 O — F6 B36 90 K8 O — 32 E3 B18 47 F3 O — — 41 G2 A27 29 C3 O — — 7 A7 A6 11 B8 O — 64-pin QFN/ TQFP 100-pin TQFP EBIA0 — EBIA1 — EBIA2 EBIA3 Pin Name 144-pin 144-pin TQFP/ TFBGA LQFP 100-pin TFBGA 124-pin VTLA 44 F4 B24 30 43 G3 A28 51 — 16 D4 B9 21 — 12 C5 B7 52 EBIA4 — 11 D6 A8 68 EBIA5 — 2 A8 B1 EBIA6 — 6 B7 B3 EBIA7 — 33 E2 EBIA8 — 65 EBIA9 — 64 EBIA10 — EBIA11 EBIA12 EBIA13 — 34 E1 B19 28 C4 O — EBIA14 — 61 H6 A42 87 L7 O — EBIA15 — 68 K7 B38 97 N9 O — EBIA16 — 17 C4 A11 19 C6 O — EBIA17 — 40 G1 B22 53 G4 O — EBIA18 — 39 F2 A26 92 M8 O — EBIA19 — 38 E5 B21 93 N8 O — EBIA20 — — — — 94 K9 O — EBIA21 — — — — 126 F10 O — EBIA22 — — — — 117 H13 O — EBIA23 — — — — 103 M11 O — EBID0 — 91 E7 B52 135 D10 I/O ST EBID1 — 94 D8 A64 138 C10 I/O ST EBID2 — 98 B10 A66 142 C13 I/O ST EBID3 — 99 A10 B56 143 B13 I/O ST EBID4 — 100 B9 A67 144 A13 I/O ST EBID5 — 3 B8 A3 3 A11 I/O ST EBID6 — 4 C8 B2 4 B11 I/O ST ST EBID7 — 5 C7 A4 5 B10 I/O EBID8 — 88 E8 B50 128 F12 I/O ST EBID9 — 87 F10 A60 127 F11 I/O ST EBID10 — 86 F9 B49 125 G11 I/O ST EBID11 — 85 F8 A59 124 G12 I/O ST EBID12 — 79 H7 B43 112 K13 I/O ST EBID13 — 80 G7 A54 113 K12 I/O ST EBID14 — 77 H9 B42 110 L12 I/O ST EBID15 — 78 H8 A53 111 L13 I/O ST EBIBS0 — — — — 9 A9 O — EBIBS1 — — — — 10 A8 O — EBICS0 — 59 H5 A41 131 E12 O — EBICS1 — — — — 132 E11 O — EBICS2 — — — — 133 E10 O — EBICS3 — — — — 134 D11 O — Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer DS60001320H-page 34 Analog = Analog input O = Output PPS = Peripheral Pin Select Description External Bus Interface Address Bus External Bus Interface Data I/O Bus External Bus Interface Byte Select External Bus Interface Chip Select P = Power I = Input  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-13: EBI PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Type Buffer Type D8 O — External Bus Interface Output Enable M7 I ST External Bus Interface Ready Input 144-pin 144-pin TQFP/ TFBGA LQFP 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA EBIOE — 9 B6 A7 13 EBIRDY1 — 60 J5 B34 86 Pin Name Description EBIRDY2 — 58 G5 A39 84 M6 I ST EBIRDY3 — 57 F5 B45 116 J13 I ST EBIRP — — — — 45 E3 O — External Bus Interface Flash Reset Pin EBIWE — 8 A6 B5 12 C8 O — External Bus Interface Write Enable Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer  2015-2021 Microchip Technology Inc. Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input DS60001320H-page 35 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-14: USB PINOUT I/O DESCRIPTIONS Pin Number Pin Name 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA 144-pin 144-pin TQFP/ TFBGA LQFP Pin Type Buffer Type Description VBUS 33 51 H3 A35 73 N2 I Analog VUSB3V3 34 52 J3 A36 74 N3 P — D+ 37 55 K4 B30 77 N5 I/O Analog USB D+ D- 36 54 K3 A37 76 N4 I/O Analog USB D- USBID 38 56 J4 A38 78 M4 I ST Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer TABLE 1-15: Analog = Analog input O = Output PPS = Peripheral Pin Select USB bus power monitor USB internal transceiver supply. If the USB module is not used, this pin must be connected to VSS. When connected to VSS, the shared pin functions on USBID will not be available. USB OTG ID detect P = Power I = Input CAN1 AND CAN2 PINOUT I/O DESCRIPTIONS Pin Number Buffer Type 100-pin TQFP 100-pin TFBGA 124-pin VTLA C1TX PPS PPS PPS PPS PPS PPS O — CAN1 Bus Transmit Pin C1RX PPS PPS PPS PPS PPS PPS I ST CAN1 Bus Receive Pin C2TX PPS PPS PPS PPS PPS PPS O — CAN2 Bus Transmit Pin C2RX PPS PPS PPS PPS PPS PPS I ST CAN2 Bus Receive Pin Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer DS60001320H-page 36 144-pin 144-pin TQFP/ TFBGA LQFP Pin Type 64-pin QFN/ TQFP Pin Name Analog = Analog input O = Output PPS = Peripheral Pin Select Description P = Power I = Input  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-16: ETHERNET MII I/O DESCRIPTIONS Pin Number Pin Name 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA 144-pin 144-pin TQFP/ TFBGA LQFP Pin Type Buffer Type Description ERXD0 61 41 G2 B32 81 K5 I ST Ethernet Receive Data 0 ERXD1 58 42 H2 B26 66 M3 I ST Ethernet Receive Data 1 ERXD2 57 43 G3 A31 67 L3 I ST Ethernet Receive Data 2 ERXD3 56 44 F4 A40 82 K6 I ST Ethernet Receive Data 3 ERXERR 64 35 F3 A30 65 K3 I ST Ethernet Receive Error Input ERXDV 62 12 C5 B40 101 K11 I ST Ethernet Receive Data Valid ERXCLK 63 16 D4 B12 27 B4 I ST Ethernet Receive Clock ETXD0 2 86 F9 A5 7 C9 O — Ethernet Transmit Data 0 ETXD1 3 85 F8 B4 8 B9 O — Ethernet Transmit Data 1 ETXD2 43 79 H7 B17 43 E1 O — Ethernet Transmit Data 2 ETXD3 46 80 G7 A22 44 E2 O — Ethernet Transmit Data 3 ETXERR 50 87 F10 B44 114 J11 O — Ethernet Transmit Error ETXEN 1 77 H9 A57 120 J10 O — Ethernet Transmit Enable ETXCLK 51 78 H8 B47 121 H10 I ST Ethernet Transmit Clock ECOL 44 10 C6 B33 83 L6 I ST Ethernet Collision Detect ECRS 45 11 D6 A47 100 L10 I ST Ethernet Carrier Sense EMDC 30 70 K8 B39 99 M10 O — Ethernet Management Data Clock 49 71 J8 A55 115 J12 I/O — Ethernet Management Data EMDIO Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer TABLE 1-17: Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input ETHERNET RMII PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type K5 I ST Ethernet Receive Data 0 M3 I ST Ethernet Receive Data 1 K3 I ST Ethernet Receive Error Input 7 C9 O — Ethernet Transmit Data 0 B4 8 B9 O — Ethernet Transmit Data 1 H9 A57 120 J10 O — Ethernet Transmit Enable K8 B39 99 M10 O — Ethernet Management Data Clock 71 J8 A55 115 J12 I/O — Ethernet Management Data 16 D4 B12 27 B4 I ST Ethernet Reference Clock 12 C5 B40 101 K11 I ST Ethernet Carrier Sense Data Valid 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA ERXD0 61 41 G2 B32 81 ERXD1 58 42 H2 B26 66 ERXERR 64 35 F3 A30 65 ETXD0 2 86 F9 A5 ETXD1 3 85 F8 ETXEN 1 77 EMDC 30 70 EMDIO 49 EREFCLK 63 ECRSDV 62 Pin Name 144-pin 144-pin TQFP/ TFBGA LQFP Description Ethernet MII Interface Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer  2015-2021 Microchip Technology Inc. Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input DS60001320H-page 37 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-18: ALTERNATE ETHERNET MII PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type — I ST Alternate Ethernet Receive Data 0 — — I ST Alternate Ethernet Receive Data 1 — — — I ST Alternate Ethernet Receive Data 2 D2 — — — I ST Alternate Ethernet Receive Data 3 1 A9 — — — I ST Alternate Ethernet Receive Error Input — 12 C5 — — — I ST Alternate Ethernet Receive Data Valid AERXCLK — 16 D4 — — — I ST Alternate Ethernet Receive Clock AETXD0 — 47 J2 — — — O — Alternate Ethernet Transmit Data 0 AETXD1 — 48 J1 — — — O — Alternate Ethernet Transmit Data 1 AETXD2 — 44 F4 — — — O — Alternate Ethernet Transmit Data 2 AETXD3 — 43 G3 — — — O — Alternate Ethernet Transmit Data 3 AETXERR — 35 F3 — — — O — Alternate Ethernet Transmit Error AECOL — 42 H2 — — — I ST Alternate Ethernet Collision Detect AECRS — 41 G2 — — — I ST Alternate Ethernet Carrier Sense AETXCLK — 66 K6 — — — I ST Alternate Ethernet Transmit Clock AEMDC — 70 K8 — — — O — Alternate Ethernet Management Data Clock AEMDIO — 71 J8 — — — I/O — Alternate Ethernet Management Data AETXEN — 67 J6 — — — O — Alternate Ethernet Transmit Enable 144-pin 144-pin TQFP/ TFBGA LQFP 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA AERXD0 — 18 A3 — — AERXD1 — 19 A4 — AERXD2 — 28 C2 AERXD3 — 29 AERXERR — AERXDV Pin Name Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer DS60001320H-page 38 Analog = Analog input O = Output PPS = Peripheral Pin Select Description P = Power I = Input  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-19: ALTERNATE ETHERNET RMII PINOUT I/O DESCRIPTIONS Pin Number Pin Type Buffer Type Description — I ST Alternate Ethernet Receive Data 0 — — I ST Alternate Ethernet Receive Data 1 — — — I ST Alternate Ethernet Receive Error Input J2 — — — O — Alternate Ethernet Transmit Data 0 48 J1 — — — O — Alternate Ethernet Transmit Data 1 30 70 K8 — — — O — Alternate Ethernet Management Data Clock AEMDIO 49 71 J8 — — — I/O — Alternate Ethernet Management Data AETXEN 50 67 J6 — — — O — Alternate Ethernet Transmit Enable AEREFCLK 45 16 D4 — — — I ST Alternate Ethernet Reference Clock AECRSDV 62 12 C5 — — — I ST Alternate Ethernet Carrier Sense Data Valid 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA AERXD0 43 18 A3 — — AERXD1 46 19 A4 — AERXERR 51 1 A9 AETXD0 57 47 AETXD1 56 AEMDC Pin Name Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer  2015-2021 Microchip Technology Inc. 144-pin 144-pin TQFP/ TFBGA LQFP Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input DS60001320H-page 39 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-20: SQI1 PINOUT I/O DESCRIPTIONS Pin Number 64-pin QFN/ TQFP 100-pin TQFP SQICLK 57 SQICS0 52 SQICS1 53 Pin Name 144-pin 144-pin TQFP/ TFBGA LQFP Pin Type Buffer Type Description 100-pin TFBGA 124-pin VTLA 89 E9 A61 129 F13 O — Serial Quad Interface Clock 81 G8 A56 118 H12 O — Serial Quad Interface Chip Select 0 82 G9 B46 119 H11 O — Serial Quad Interface Chip Select 1 SQID0 58 97 C10 B55 141 C12 I/O ST Serial Quad Interface Data 0 SQID1 61 96 C9 A65 140 C11 I/O ST Serial Quad Interface Data 1 SQID2 62 95 D9 B54 139 D12 I/O ST Serial Quad Interface Data 2 SQID3 63 90 E10 B51 130 E13 I/O ST Serial Quad Interface Data 3 Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer TABLE 1-21: Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input POWER, GROUND, AND VOLTAGE REFERENCE PINOUT I/O DESCRIPTIONS Pin Number 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA AVDD 19 30 D1 B16 AVSS 20 31 D3 A21 VDD 8, 26, 39, 54, 60 14, 37, 46, 62, 74, 83, 93 VSS 7, 25, 35, 40, 55, 59 13, 36, 45, 53, 63, 75, 84, 92 VREF+ 16 29 VREF- 15 28 Pin Name Legend: Power and Ground 41 D1 42 E4 A5, F1, B8, A15, 18, 33, A7, A3 H1, A25, 55, 64, H1, K1 K5,J10, B25, 88, 107, N7, N13 G10, D10 B35, 122, 137 G13, A50, D13 A58, B53 D5, E4, A9, B13, 17, 32, D6, D4, G4, H4, B20, 54, 63, H4, K4, J9, F7, B29, 75, 89, L4, K7, D7 A29, 108, K10, A43, 123, 136 G10, D9 A51, B48, A63 Voltage Reference D2 A20 40 D3 C2 B15 CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer DS60001320H-page 40 144-pin 144-pin TQFP/ TFBGA LQFP 39 D2 Pin Type Buffer Type P P P P P — P — Ground reference for logic, I/O pins, and USB. This pin must be connected at all times. I Analog I Analog Analog Voltage Reference (High) Input Analog Voltage Reference (Low) Input P = Power I = Input Analog = Analog input O = Output PPS = Peripheral Pin Select Description Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules. This pin must be connected at all times Positive supply for peripheral logic and I/O pins. This pin must be connected at all times.  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 1-22: JTAG, TRACE, AND PROGRAMMING/DEBUGGING PINOUT I/O DESCRIPTIONS Pin Number 144-pin 144-pin TQFP/ TFBGA LQFP Pin Type Buffer Type 64-pin QFN/ TQFP 100-pin TQFP 100-pin TFBGA 124-pin VTLA TCK 27 38 E5 B21 56 H2 I ST JTAG Test Clock Input Pin TDI 28 39 F2 A26 57 H3 I ST JTAG Test Data Input Pin TDO 24 40 G1 B22 58 J4 O — JTAG Test Data Output Pin TMS 23 17 C4 A11 22 D5 I ST JTAG Test Mode Select Pin TRCLK 57 89 E9 A61 129 F13 O — Trace Clock TRD0 58 97 C10 B55 141 C12 O — Trace Data bits 0-3 TRD1 61 96 C9 A65 140 C11 O — TRD2 62 95 D9 B54 139 D12 O — TRD3 63 90 E10 B51 130 E13 O — Pin Name Description JTAG Trace Programming/Debugging PGED1 16 25 A1 A18 36 A1 I/O ST Data I/O pin for Programming/ Debugging Communication Channel 1 PGEC1 15 24 A2 A17 35 A2 I ST Clock input pin for Programming/ Debugging Communication Channel 1 PGED2 18 27 C1 A19 38 C1 I/O ST Data I/O pin for Programming/ Debugging Communication Channel 2 PGEC2 17 26 B1 B14 37 B1 I ST Clock input pin for Programming/ Debugging Communication Channel 2 MCLR 9 15 B5 A10 20 B6 I/P ST Master Clear (Reset) input. This pin is an active-low Reset to the device. Legend: CMOS = CMOS-compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = Transistor-transistor Logic input buffer  2015-2021 Microchip Technology Inc. Analog = Analog input O = Output PPS = Peripheral Pin Select P = Power I = Input DS60001320H-page 41 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320H-page 42  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS Note 1: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2.1 Basic Connection Requirements Getting started with the PIC32MZ EF family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins (see 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins, even if the ADC module is not used (see 2.2 “Decoupling Capacitors”) • MCLR pin (see 2.3 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins, used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see 2.4 “ICSP Pins”) • OSC1 and OSC2 pins, when external oscillator source is used (see 2.7 “External Oscillator Pins”) The following pin(s) may be required as well: VREF+/VREF- pins, used when external voltage reference for the ADC module is implemented. Note: The AVDD and AVSS pins must be connected, regardless of ADC use and the ADC voltage reference source.  2015-2021 Microchip Technology Inc. 2.2 Decoupling Capacitors The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A value of 0.1 µF (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (lowESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. DS60001320H-page 43 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION VDD 0.1 µF Ceramic VSS VDD VDD VSS MCLR VDD VSS VDD C PIC32 VSS VSS VUSB3V3(1) VDD VSS VDD Connect(2) VDD 0.1 µF Ceramic VSS VSS AVSS AVDD VDD 0.1 µF Ceramic 0.1 µF Ceramic 0.1 µF Ceramic L1(2) Note Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: • Device Reset • Device programming and debugging R R1 2.3 1: If the USB module is not used, this pin must be connected to VSS. When connected to VSS, the shared pin functions on USBID will not be available. 2: As an option, instead of a hard-wired connection, an inductor (L1) can be substituted between VDD and AVDD to improve ADC noise rejection. The inductor impedance should be less than 1 and the inductor capacity greater than 10 mA.  Where: Pulling The MCLR pin low generates either a device Reset or a POR, depending on the setting of the SMCLR bit (DEVCFG0). Figure 2-2 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as illustrated in Figure 2-2, it is recommended that the capacitor C be isolated from the MCLR pin during programming and debugging operations. Place the components illustrated in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD (i.e., ADC conversion rate/2) 2 1 L =  ----------------------  2f C  2.2.1 BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 µF to 47 µF. This capacitor should be located as close to the device as possible. DS60001320H-page 44 R 0.1 µF(2) ICSP™ F CNV f = -------------2 1 f = ---------------------- 2 LC  Note 1 5 4 2 3 6 VDD VSS NC 10k C R1(1) 1 k MCLR PIC32 PGECx(3) PGEDx(3) 1: 470 R1  1k will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met without interfering with the Debug/Programmer tools. 2: The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during POR. 3: No pull-ups or bypass capacitors are allowed on active debug/program PGECx/PGEDx pins.  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2.4 ICSP Pins 2.6 Trace The PGECx and PGEDx pins are used for ICSP and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. The trace pins can be connected to a hardware trace-enabled programmer to provide a compressed real-time instruction trace. When used for trace, the TRD3, TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a 22 Ohm series resistor between the trace pins and the trace connector. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. 2.7 Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 3 or MPLAB REAL ICE™. For more information on ICD 3 and REAL ICE connection requirements, refer to the following documents that are available from the Microchip web site. • “Using MPLAB® ICD 3” (poster) (DS50001765) • “MPLAB® ICD 3 Design Advisory” (DS50001764) • “MPLAB® REAL ICE™ In-Circuit Debugger User’s Guide” (DS50001616) • “Using MPLAB® REAL ICE™ Emulator” (poster) (DS50001749) 2.5 External Oscillator Pins Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure 2-3. FIGURE 2-3: SUGGESTED OSCILLATOR CIRCUIT PLACEMENT JTAG The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input voltage low (VIL) requirements.  2015-2021 Microchip Technology Inc. Oscillator Secondary Guard Trace Guard Ring Main Oscillator 2.8 Unused I/Os Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternatively, inputs can be reserved by connecting the pin to VSS through a 1k to 10k resistor and configuring the pin as an input. DS60001320H-page 45 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2.9 Designing for High-Speed Peripherals The PIC32MZ EF family devices have peripherals that operate at frequencies much higher than typical for an embedded environment. Table 2-1 lists the peripherals that produce high-speed signals on their external pins: TABLE 2-1: PERIPHERALS THAT PRODUCE HS SIGNALS ON EXTERNAL PINS Peripheral High-Speed Signal Pins Maximum Speed on Signal Pin EBI EBIAx, EBIDx 50 MHz SQI1 SQICLK, SQICSx, SQIDx 50 MHz HS USB D+, D- 480 MHz Due to these high-speed signals, it is important to consider several factors when designing a product that uses these peripherals, as well as the PCB on which these components will be placed. Adhering to these recommendations will help achieve the following goals: • Minimize the effects of electromagnetic interference to the proper operation of the product • Ensure signals arrive at their intended destination at the same time • Minimize crosstalk • Maintain signal integrity • Reduce system noise • Minimize ground bounce and power sag 2.9.1 2.9.1.1 SYSTEM DESIGN Impedance Matching When selecting parts to place on high-speed buses, particularly the SQI bus, if the impedance of the peripheral device does not match the impedance of the pins on the PIC32MZ EF device to which it is connected, signal reflections could result, thereby degrading the quality of the signal. If it is not possible to select a product that matches impedance, place a series resistor at the load to create the matching impedance. See Figure 2-4 for an example. FIGURE 2-4: SERIES RESISTOR PIC32MZ 50 DS60001320H-page 46 2.9.1.2 PCB Layout Recommendations The following list contains recommendations that will help ensure the PCB layout will promote the goals previously listed. • Component Placement - Place bypass capacitors as close to their component power and ground pins as possible, and place them on the same side of the PCB - Devices on the same bus that have larger setup times should be placed closer to the PIC32MZ EF device • Power and Ground - Multi-layer PCBs will allow separate power and ground planes - Each ground pin should be connected to the ground plane individually - Place bypass capacitor vias as close to the pad as possible (preferably inside the pad) - If power and ground planes are not used, maximize width for power and ground traces - Use low-ESR, surface-mount bypass capacitors • Clocks and Oscillators - Place crystals as close as possible to the PIC32MZ EF device OSC/SOSC pins - Do not route high-speed signals near the clock or oscillator - Avoid via usage and branches in clock lines (SQICLK) - Place termination resistors at the end of clock lines • Traces - Higher-priority signals should have the shortest traces - Match trace lengths for parallel buses (EBIAx, EBIDx, SQIDx) - Avoid long run lengths on parallel traces to reduce coupling - Make the clock traces as straight as possible - Use rounded turns rather than right-angle turns - Have traces on different layers intersect on right angles to minimize crosstalk - Maximize the distance between traces, preferably no less than three times the trace width - Power traces should be as short and as wide as possible - High-speed traces should be placed close to the ground plane SQI Flash Device  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2.9.1.3 EMI/EMC/EFT (IEC 61000-4-4 and IEC 61000-4-2) Suppression Considerations The use of LDO regulators is preferred to reduce overall system noise and provide a cleaner power source. However, when utilizing switching Buck/Boost regulators as the local power source for PIC32MZ EF devices, as well as in electrically noisy environments or test conditions required for IEC 61000-4-4 and IEC 61000-4-2, users should evaluate the use of T-Filters (i.e., L-C-L) on the power pins, as shown in Figure 2-5. In addition to a more stable power source, use of this type of T-Filter can greatly reduce susceptibility to EMI sources and events. FIGURE 2-5: EMI/EMC/EFT SUPPRESSION CIRCUIT Ferrite Chip SMD DCR = 0.15ȍ(max) 600 ma ISAT 300ȍ@ 100 MHz PN#:  VDD 0.01 μF Ferrite Chips 0.1 μF VSS VDD VDD VSS 0.1 μF VSS VDD VSS VDD VSS 0.1 μF PIC32MZ VSS 0.1 μF VSS VDD AVDD AVSS 0.1 μF VSS VUSB3V3 VDD 0.1 μF VDD 0.1 μF 0.1 μF 0.1 μF Ferrite Chips VDD 0.01 μF  2015-2021 Microchip Technology Inc. DS60001320H-page 47 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2.10 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-8 and Figure 2-9. FIGURE 2-6: AUDIO PLAYBACK APPLICATION PMD USB Host PMP USB Display PMWR PIC32 I2S SPI Stereo Headphones 3 REFCLKO 3 Audio Codec Speaker 3 MMC SD SDI FIGURE 2-7: LOW-COST CONTROLLERLESS (LCC) GRAPHICS APPLICATION WITH PROJECTED CAPACITIVE TOUCH PIC32 Microchip mTouch™ Library Microchip GFX Library ADC ANx Render LCD Display Refresh DMA Projected Capacitive Touch Overlay EBI SRAM DS60001320H-page 48 External Frame Buffer  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2.11 2.11.1 Considerations when Interfacing to Remotely Powered Circuits is limited to meet the respective injection current specifications defined by the parameters, such as DI60a, DI60b, and DI60c as shown in Table 37-10. NON-5V TOLERANT INPUT PINS Figure 2-8 illustrates an example of a remote circuit using an independent power source which is powered while connected to a PIC32 non-5V tolerant circuit that is not powered. A quick review of the section “Absolute Maximum Rating” in Electrical Characteristics chapter indicates that the voltage on any non-5V tolerant pin may not exceed VDD + 0.3V. The exception is, if the input current FIGURE 2-8: PIC32 NON-5V TOLERANT CIRCUIT EXAMPLE PIC32 Non-5V Tolerant Pin Architecture On/Off 9'' $16(/ ,2,1 $15% ,2287 5HPRWH *1' 75,6 &38/2*,& 5HPRWH 9d9,+ d 9 3,& 32:(5 6833/< Current Flow 966 Without proper signal isolation on non-5V tolerant pins, the remote signal can power the PIC32 device through the high side ESD protection diodes. Besides violating the absolute maximum rating specification, when VDD of the PIC32 device is restored and ramping up or ramping down, it can also negatively affect the internal Power-on Reset (POR) and Brown-out Reset (BOR) circuits, which can lead to improper initialization of internal PIC32 logic circuits. In these cases, it is recommended to implement digital or analog signal isolation as shown in Figure 2-9. This is indicative of all industry microcontrollers and not only Microchip products.  2015-2021 Microchip Technology Inc. DS60001320H-page 49 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 2-9: EXAMPLE DIGITAL/ANALOG SIGNAL ISOLATION CIRCUITS PIC32 VDD Digital Isolator External VDD REMOTE_IN IN1 REMOTE_OUT OUT1 External VDD IN REMOTE_IN PIC32 PIC32 VDD Digital Isolator Conn PIC32 VSS VSS PIC32 VDD Opto Digital ISOLATOR External VDD PIC32 VDD Analog / Digital Isolator ENB Conn IN1 Analog_IN2 Analog_OUT2 PIC32 External_VDD1 ENB PIC32 ^ Analog_IN1 REMOTE_IN Analog Switch VSS VSS TABLE 2-2: EXAMPLES OF DIGITAL ISOLATORS WITH OPTIONAL LEVEL TRANSLATION Example Digital/Analog Signal Isolation Circuits Inductive Coupling Capacitive Coupling Opto Coupling Analog/Digital Coupling — — — — — ADuM7241/40 ARZ (1 Mbps) X ADuM7241/40 ARZ (25 Mbps) X — — ISO721 — — — — X — — — — — — — — LTV-829S (2 Chan) LTV-849S (4 Chan) FSA266/NC7WB66 DS60001320H-page 50 X X  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 2.11.2 5V TOLERANT INPUT PINS The internal high side diode on 5V tolerant pins is bussed to an internal floating node, rather than being connected to VDD, as shown in Figure 2-10. The voltage on these pins, if VDD < 2.1V (usually during power up/power down), should not exceed 3.2V relative to VSS of the PIC32 device. The voltage of 3.6V or higher (when VDD < 2.1V) will violate the absolute maximum specification and will stress the oxide layer separatiing the high side floating node, which impacts device reliability. FIGURE 2-10: If a remotely powered "digital-only" signal can be guaranteed to always be ≤ 3.2V relative to VSS on the PIC32 device side, a 5V tolerant pin can be used without the need for a digital isolator. This is assuming there is no ground loop issue, that is, the logic ground of the two circuits is not at the same absolute level, and remote logic low inputs is not less than VSS - 0.3V. Once VDD >= 2.1V, the pin can be operated up to 5.5V. PIC32 5V TOLERANT PIN ARCHITECTURE EXAMPLE PIC32 5V Tolerant Pin Architecture )ORDWLQJ%XV 2[LGH%9 9 LI9'' 9 2;,'( On/Off 9'' $16(/ ,2,1 5* ,2287 5HPRWH *1' 75,6 &38/2*,& 5HPRWH 9,+ 9 3,& 32:(5 6833/< 966  2015-2021 Microchip Technology Inc. DS60001320H-page 51 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320H-page 52  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 3.0 CPU Note 1: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: The Series 5 Warrior M-class CPU core resources are available at: www.imgtec.com. The MIPS32® M-Class Core is the heart of the PIC32MZ EF family device processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. Key features include: • 5-stage pipeline • 32-bit address and data paths • MIPS32 Enhanced Architecture (Release 5): - Multiply-accumulate and multiply-subtract instructions - Targeted multiply instruction - Zero/One detect instructions - WAIT instruction - Conditional move instructions (MOVN, MOVZ) - Vectored interrupts - Programmable exception vector base - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions - Virtual memory support • microMIPS™ compatible instruction set: - Improves code size density over MIPS32, while maintaining MIPS32 performance. - Supports all MIPS32 instructions (except branchlikely instructions) - Fifteen additional 32-bit instructions and 39 16-bit instructions corresponding to commonly-used MIPS32 instructions - Stack pointer implicit in instruction - MIPS32 assembly and ABI compatible • MMU with Translation Lookaside Buffer (TLB) mechanism: - 16 dual-entry fully associative Joint TLB - 4-entry fully associative Instruction and Data TLB - 4 KB pages  2015-2021 Microchip Technology Inc. • Separate L1 data and instruction caches: - 16 KB 4-way Instruction Cache (I-Cache) - 4 KB 4-way Data Cache (D-Cache) • Autonomous Multiply/Divide Unit (MDU): - Maximum issue rate of one 32x32 multiply per clock - Early-in iterative divide. Minimum 12 and maximum 38 clock latency (dividend (rs) sign extension-dependent) • Power Control: - Minimum frequency: 0 MHz - Low-Power mode (triggered by WAIT instruction) - Extensive use of local gated clocks • EJTAG Debug and Instruction Trace: - Support for single stepping - Virtual instruction and data address/value breakpoints - Hardware breakpoint supports both address match and address range triggering. - Eight instruction and four data complex breakpoints • iFlowtrace® version 2.0 support: - Real-time instruction program counter - Special events trace capability - Two performance counters with 34 userselectable countable events - Disabled if the processor enters Debug mode - Program Counter sampling • Four Watch registers: - Instruction, Data Read, Data Write options - Address match masking options • DSP ASE Extension: - Native fractional format data type operations - Register Single Instruction Multiple Data (SIMD) operations (add, subtract, multiply, shift) - GPR-based shift - Bit manipulation - Compare-Pick - DSP Control Access - Indexed-Load - Branch - Multiplication of complex operands - Variable bit insertion and extraction - Virtual circular buffers - Arithmetic saturation and overflow handling - Zero-cycle overhead saturation and rounding operations • Floating Point Unit (FPU): - 1985 IEEE-754 compliant Floating Point Unit - Supports single and double precision datatypes - 2008 IEEE-754 compatibility control of NaN handling and Abs/Neg instructions - Runs at 1:1 core/FPU clock ratio DS60001320H-page 53 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family A block diagram of the PIC32MZ EF family processor core is shown in Figure 3-1. FIGURE 3-1: PIC32MZ EF FAMILY MICROPROCESSOR CORE BLOCK DIAGRAM M-Class Microprocessor Core PBCLK7 Decode (MIPS32®/microMIPS™) microMIPS™ I-Cache Controller I-Cache GPR (8 sets) Execution Unit ALU/Shift Atomic/LdSt DSP ASE Enhanced MDU (with DSP ASE) FPU (Single & Double) MMU (TLB) BIU System Bus D-Cache Controller D-Cache System Interface Debug/Profiling System Coprocessor Interrupt Interface 2-wire Debug DS60001320H-page 54 Break Points iFlowtrace® Fast Debug Channel Performance Counters Sampling Secure Debug Power Management EJTAG  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 3.1 Architecture Overview The MIPS32 M-Class Microprocessor core in PIC32MZ EF family devices contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: • • • • • • • • • • • Execution unit General Purpose Register (GPR) Multiply/Divide Unit (MDU) System control coprocessor (CP0) Floating Point Unit (FPU) Memory Management Unit (MMU) Instruction/Data cache controllers Power Management Instructions and data caches microMIPS support Enhanced JTAG (EJTAG) controller 3.1.1 3.1.2 MULTIPLY/DIVIDE UNIT (MDU) The processor core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations, and DSP ASE multiply instructions. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. EXECUTION UNIT The processor core execution unit implements a load/ store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. Seven additional register file shadow sets (containing thirty-two registers) are added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: • 32-bit adder used for calculating the data address • Address unit for calculating the next instruction address • Logic for branch determination and branch target address calculation • Load aligner • Trap condition comparator • Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results TABLE 3-1: • Leading Zero/One detect unit for implementing the CLZ and CLO instructions • Arithmetic Logic Unit (ALU) for performing arithmetic and bitwise logical operations • Shifter and store aligner • DSP ALU and logic block for performing DSP instructions, such as arithmetic/shift/compare operations The high-performance MDU consists of a 32x32 booth recoded multiplier, four pairs of result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (‘32’ of 32x32) represents the rs operand. The second number (‘32’ of 32x32) represents the rt operand. The MDU supports execution of one multiply or multiply-accumulate operation every clock cycle. Divide operations are implemented with a simple 1-bitper-clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit wide rs, 15 iterations are skipped and for a 24-bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation has completed. Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the processor core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. MIPS32® M-CLASS MICROPROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode MULT/MULTU, MADD/MADDU, MSUB/MSUBU (HI/LO destination) MUL (GPR destination) DIV/DIVU  2015-2021 Microchip Technology Inc. Operand Size (mul rt) (div rs) Latency Repeat Rate 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits 5 5 5 5 12/14 20/22 28/30 36/38 1 1 1 1 12/14 20/22 28/30 36/38 DS60001320H-page 55 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family The MIPS architecture defines that the result of a multiply or divide operation be placed in one of four pairs of HI and LO registers. Using the Move-From-HI (MFHI) and Move-From-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. Two other instructions, Multiply-Add (MADD) and Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. The MDU also implements various shift instructions operating on the HI/LO register and multiply instructions as defined in the DSP ASE. The MDU supports all of the data types required for this purpose and includes three extra HI/LO registers as defined by the ASE. TABLE 3-3: Register Number Register Name Index Random EntryLo0 EntryLo1 Context/ UserLocal 5 PageMask/ PageGrain Wired HWREna 8 9 10 11 TABLE 3-2: DSP-RELATED LATENCIES AND REPEAT RATES Op code Latency Repeat Rate Multiply and dot-product without saturation after accumulation 5 1 Multiply and dot-product with saturation after accumulation 5 1 Multiply without accumulation 5 1 3.1.3 SYSTEM CONTROL  COPROCESSOR (CP0) In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation and cache protocols, the exception control system, the processor’s diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as cache size and set associativity, and the presence of options like microMIPS is also available by accessing the CP0 registers, as listed in Table 3-3. Refer to the “Series 5 Warrior M-class CPU core” resources which are available at: www.imgtec.com for more information. COPROCESSOR 0 REGISTERS 0 1 2 3 4 6 7 Table 3-2 lists the latencies and repeat rates for the DSP multiply and dot-product operations. The approximate latencies and repeat rates are listed in terms of pipeline clocks. BadVAddr BadInstr BadInstrP Count EntryHi Compare DS60001320H-page 56 Function Index into the TLB array (MPU only). Randomly generated index into the TLB array (MPU only). Low-order portion of the TLB entry for even-numbered virtual pages (MPU only). Low-order portion of the TLB entry for odd-numbered virtual pages (MPU only). Pointer to the page table entry in memory (MPU only). User information that can be written by privileged software and read via the RDHWR instruction. PageMask controls the variable page sizes in TLB entries. PageGrain enables support of 1 KB pages in the TLB (MPU only). Controls the number of fixed (i.e., wired) TLB entries (MPU only). Enables access via the RDHWR instruction to selected hardware registers in  Non-privileged mode. Reports the address for the most recent address-related exception. Reports the instruction that caused the most recent exception. Reports the branch instruction if a delay slot caused the most recent exception. Processor cycle count. High-order portion of the TLB entry (MPU only). Core timer interrupt control.  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 3-3: Register Number 12 13 14 15 16 17 18 19 20-22 23 24 25 26 27 28 29 30 COPROCESSOR 0 REGISTERS (CONTINUED) Register Name Function Status IntCtl SRSCtl SRSMap View_IPL Processor status and control. Interrupt control of vector spacing. Shadow register set control. Shadow register mapping control. Allows the Priority Level to be read/written without extracting or inserting that bit from/to the Status register. SRSMAP2 Contains two 4-bit fields that provide the mapping from a vector number to the shadow set number to use when servicing such an interrupt. GuestCtl0 Control of Virtualized Guest OS GTOffset Guest Timer Offset Cause Describes the cause of the last exception. NestedExc Contains the error and exception level status bit values that existed prior to the current exception. View_RIPL Enables read access to the RIPL bit that is available in the Cause register. EPC Program counter at last exception. NestedEPC Contains the exception program counter that existed prior to the current exception. PRID Processor identification and revision Ebase Exception base address of exception vectors. CDMMBase Common device memory map base. Config Configuration register. Config1 Configuration register 1. Config2 Configuration register 2. Config3 Configuration register 3. Config4 Configuration register 4. Config5 Configuration register 5. Config7 Configuration register 7. LLAddr Load link address (MPU only). WatchLo Low-order watchpoint address (MPU only). WatchHi High-order watchpoint address (MPU only). Reserved Reserved in the PIC32 core. Debug EJTAG debug register. TraceControl EJTAG trace control. TraceControl2 EJTAG trace control 2. UserTraceData1 EJTAG user trace data 1 register. TraceBPC EJTAG trace breakpoint register. Debug2 Debug control/exception status 1. DEPC Program counter at last debug exception. UserTraceData2 EJTAG user trace data 2 register. PerfCtl0 Performance counter 0 control. PerfCnt0 Performance counter 0. PerfCtl1 Performance counter 1 control. PerfCnt1 Performance counter 1. ErrCtl Software test enable of way-select and data RAM arrays for I-Cache and D-Cache (MPU only). Reserved Reserved in the PIC32 core. TagLo/DataLo Low-order portion of cache tag interface (MPU only). Reserved Reserved in the PIC32 core. ErrorEPC Program counter at last error exception.  2015-2021 Microchip Technology Inc. DS60001320H-page 57 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 3-3: Register Number 31 COPROCESSOR 0 REGISTERS (CONTINUED) Register Name DeSave KScratchn DS60001320H-page 58 Function Debug exception save. Scratch Registers for Kernel Mode  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 3.1.4 FLOATING POINT UNIT (FPU) The Floating Point Unit (FPU), Coprocessor (CP1), implements the MIPS Instruction Set Architecture for floating point computation. The implementation supports the ANSI/IEEE Standard 754 (IEEE for Binary Floating Point Arithmetic) for 32-bit and 64-bit floating point data formats. The FPU can be programmed to have thirty-two 32-bit or 64-bit floating point registers used for floating point operations. The performance is optimized for 32-bit formats. Most instructions have one FPU cycle throughput and four FPU cycle latency. The FPU implements the multiplyadd (MADD) and multiply-sub (MSUB) instructions with intermediate rounding after the multiply function. The result is guaranteed to be the same as executing a MUL and an ADD instruction separately, but the instruction latency, instruction fetch, dispatch bandwidth, and the total number of register accesses are improved. IEEE denormalized input operands and results are supported by hardware for some instructions. IEEE denormalized results are not supported by hardware in general, but a fast flush-to-zero mode is provided to optimize performance. The fast flush-to-zero mode is enabled through the FCCR register, and use of this mode is recommended for best performance when denormalized results are generated. The FPU has a separate pipeline for floating point instruction execution. This pipeline operates in parallel with the integer core pipeline and does not stall when the integer pipeline stalls. This allows long-running FPU operations, such as divide or square root, to be partially masked by system stalls and/or other integer unit instructions. Arithmetic instructions are always dispatched and completed in order, but loads and stores can complete out of order. The exception model is “precise” at all times. Table 3-4 contains the floating point instruction latencies and repeat rates for the processor core. In this table, 'Latency' refers to the number of FPU cycles necessary for the first instruction to produce the result needed by the second instruction. The “Repeat Rate” refers to the maximum rate at which an instruction can be executed per FPU cycle.  2015-2021 Microchip Technology Inc. TABLE 3-4: FPU INSTRUCTION LATENCIES AND REPEAT RATES Latency (FPU Cycles) Repeat Rate (FPU Cycles) ABS.[S,D], NEG.[S,D], ADD.[S,D], SUB.[S,D], C.cond.[S,D], MUL.S 4 1 MADD.S, MSUB.S, NMADD.S, NMSUB.S, CABS.cond.[S,D] 4 1 CVT.D.S, CVT.PS.PW, CVT.[S,D].[W,L] 4 1 CVT.S.D, CVT.[W,L].[S,D], CEIL.[W,L].[S,D], FLOOR.[W,L].[S,D], ROUND.[W,L].[S,D], TRUNC.[W,L].[S,D] 4 1 MOV.[S,D], MOVF.[S,D], MOVN.[S,D], MOVT.[S,D], MOVZ.[S,D] 4 1 MUL.D 5 2 MADD.D, MSUB.D, NMADD.D, NMSUB.D 5 2 RECIP.S 13 10 RECIP.D 26 21 RSQRT.S 17 14 RSQRT.D 36 31 DIV.S, SQRT.S 17 14 DIV.D, SQRT.D 32 29 MTC1, DMTC1, LWC1, LDC1, LDXC1, LUXC1, LWXC1 4 1 MFC1, DMFC1, SWC1, SDC1, SDXC1, SUXC1, SWXC1 1 1 Op code Legend: S = Single (32-bit) D = Double (64-bit)  W = Word (32-bit) L = Long word (64-bit) DS60001320H-page 59 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family The FPU implements a high-performance 7-stage pipeline: • Decode, register read and unpack (FR stage) • Multiply tree, double pumped for double (M1 stage) • Multiply complete (M2 stage) • Addition first step (A1 stage) • Addition second and final step (A2 stage) • Packing to IEEE format (FP stage) • Register writeback (FW stage) The FPU implements a bypass mechanism that allows the result of an operation to be forwarded directly to the instruction that needs it without having to write the result to the FPU register and then read it back. Table 3-5 lists the Coprocessor 1 Registers for the FPU. TABLE 3-5: FPU (CP1) REGISTERS Register Register Number Name Function 0 FIR Floating Point implementation register. Contains information that identifies the FPU. 25 FCCR Floating Point condition codes register. 26 FEXR Floating Point exceptions register. 28 FENR Floating Point enables register. 31 FCSR Floating Point Control and Status register. 3.2 Power Management The processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or halting the clocks, which reduces system power consumption during Idle periods. 3.2.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more information on power management, see Section 33.0 “Power-Saving Features”. 3.2.2 LOCAL CLOCK GATING The majority of the power consumed by the processor core is in the clock tree and clocking registers. The PIC32MZ family makes extensive use of local gatedclocks to reduce this dynamic power consumption. DS60001320H-page 60 3.3 3.3.1 L1 Instruction and Data Caches INSTRUCTION CACHE (I-CACHE) The I-Cache is an on-core memory block of 16 Kbytes. Because the I-Cache is virtually indexed, the virtual-tophysical address translation occurs in parallel with the cache access rather than having to wait for the physical address translation. The tag holds 22 bits of physical address, a valid bit, and a lock bit. The LRU replacement bits are stored in a separate array. The I-Cache block also contains and manages the instruction line fill buffer. Besides accumulating data to be written to the cache, instruction fetches that reference data in the line fill buffer are serviced either by a bypass of that data, or data coming from the external interface. The I-Cache control logic controls the bypass function. The processor core supports I-Cache locking. Cache locking allows critical code or data segments to be locked into the cache on a per-line basis, enabling the system programmer to maximize the efficiency of the system cache. The cache locking function is always available on all I-Cache entries. Entries can then be marked as locked or unlocked on a per entry basis using the CACHE instruction. 3.3.2 DATA CACHE (D-CACHE) The D-Cache is an on-core memory block of 4 Kbytes. This virtually indexed, physically tagged cache is protected. Because the D-Cache is virtually indexed, the virtual-to-physical address translation occurs in parallel with the cache access. The tag holds 22 bits of physical address, a valid bit, and a lock bit. There is an additional array holding dirty bits and LRU replacement algorithm bits for each set of the cache. In addition to I-Cache locking, the processor core also supports a D-Cache locking mechanism identical to the I-Cache. Critical data segments are locked into the cache on a per-line basis. The locked contents can be updated on a store hit, but cannot be selected for replacement on a cache miss. The D-Cache locking function is always available on all D-Cache entries. Entries can then be marked as locked or unlocked on a per-entry basis using the CACHE instruction. 3.3.3 ATTRIBUTES The processor core I-Cache and D-Cache attributes are listed in the Configuration registers (see Register 3-1 through Register 3-4).  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 3.4 EJTAG Debug Support The processor core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the processor core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification specify which registers are selected and how they are used. 3.5 3.6 microMIPS ISA The processor core supports the microMIPS ISA, which contains all MIPS32 ISA instructions (except for branch-likely instructions) in a new 32-bit encoding scheme, with some of the commonly used instructions also available in 16-bit encoded format. This ISA improves code density through the additional 16-bit instructions while maintaining a performance similar to MIPS32 mode. In microMIPS mode, 16-bit or 32-bit instructions will be fetched and recoded to legacy MIPS32 instruction opcodes in the pipeline’s I stage, so that the processor core can have the same microAptiv UP microarchitecture. Because the microMIPS instruction stream can be intermixed with 16-bit halfword or 32-bit word size instructions on halfword or word boundaries, additional logic is in place to address the word misalignment issues, thus minimizing performance loss. MIPS DSP ASE Extension The MIPS DSP Application-Specific Extension Revision 2 is an extension to the MIPS32 architecture. This extension comprises new integer instructions and states that include new HI/LO accumulator register pairs and a DSP control register. This extension is crucial in a wide range of DSP, multimedia, and DSPlike algorithms covering Audio and Video processing applications. The extension supports native fractional format data type operations, register Single Instruction Multiple Data (SIMD) operations, such as add, subtract, multiply, and shift. In addition, the extension includes the following features that are essential in making DSP algorithms computationally efficient: • • • • Support for multiplication of complex operands Variable bit insertion and extraction Implementation and use of virtual circular buffers Arithmetic saturation and overflow handling support • Zero cycle overhead saturation and rounding operations  2015-2021 Microchip Technology Inc. DS60001320H-page 61 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 3.7 M-Class Core Configuration Register 3-1 through Register 3-4 show the default configuration of the M-Class core, which is included on the PIC32MZ EF family of devices. REGISTER 3-1: Bit Range 31:24 23:16 15:8 7:0 CONFIG: CONFIGURATION REGISTER; CP0 REGISTER 16, SELECT 0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 r-1 U-0 U-0 U-0 U-0 U-0 U-0 R-0 — — — — — — — ISP R-1 R-0 R-0 R-1 R-0 U-0 DSP UDI SB MDU — R-0 R-0 R-0 R-0 BE AT R-0 R-1 U-0 U-0 U-0 U-0 — — — — Legend: R = Readable bit -n = Value at POR R-0 r = Reserved bit W = Writable bit ‘1’ = Bit is set R-0 MM R-1 AR MT Bit 24/16/8/0 BM R-0 R-0 MT R/W-0 R/W-1 R/W-0 K0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31 Reserved: This bit is hardwired to ‘1’ to indicate the presence of the Config1 register. bit 30-25 Unimplemented: Read as ‘0’ bit 24 ISP: Instruction Scratch Pad RAM bit 0 = Instruction Scratch Pad RAM is not implemented bit 23 DSP: Data Scratch Pad RAM bit 0 = Data Scratch Pad RAM is not implemented bit 22 UDI: User-defined bit 0 = CorExtend User-Defined Instructions are not implemented bit 21 SB: SimpleBE bit 1 = Only Simple Byte Enables are allowed on the internal bus interface bit 20 MDU: Multiply/Divide Unit bit 0 = Fast, high-performance MDU bit 19 Unimplemented: Read as ‘0’ bit 18-17 MM: Merge Mode bits 10 = Merging is allowed bit 16 BM: Burst Mode bit 0 = Burst order is sequential bit 15 BE: Endian Mode bit 0 = Little-endian bit 14-13 AT: Architecture Type bits 00 = MIPS32 bit 12-10 AR: Architecture Revision Level bits 001 = MIPS32 Release 2 bit 9-7 MT: MMU Type bits 001 = M-Class MPU Microprocessor core uses a TLB-based MMU bit 6-3 Unimplemented: Read as ‘0’ bit 2-0 K0: Kseg0 Coherency Algorithm bits 011 = Cacheable, non-coherent, write-back, write allocate 010 = Uncached 001 = Cacheable, non-coherent, write-through, write allocate 000 = Cacheable, non-coherent, write-through, no write allocate All other values are not used and mapped to other values. 100, 101, and 110 are mapped to 010. 111 is mapped to 010. DS60001320H-page 62  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 3-2: Bit Range 31:24 23:16 15:8 7:0 CONFIG1: CONFIGURATION REGISTER 1; CP0 REGISTER 16, SELECT 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 r-1 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 R-1 R-1 R-1 R-1 — R-0 MMU Size R-1 R-0 R-0 IS R-0 R-1 R-1 IS R-0 IL R-0 R-0 R-0 DS Bit 24/16/8/0 R-1 R-1 IA R-1 R-1 R-0 DL R-1 DA R-1 U-0 U-0 R-1 R-1 R-0 R-1 R-1 DA — — PC WR CA EP FP Legend: R = Readable bit -n = Value at POR r = Reserved bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31 Reserved: This bit is hardwired to a ‘1’ to indicate the presence of the Config2 register. bit 30-25 MMU Size: Contains the number of TLB entries minus 1 001111 = 16 TLB entries bit 24-22 IS: Instruction Cache Sets bits 010 = Contains 256 instruction cache sets per way bit 21-19 IL: Instruction-Cache Line bits 011 = Contains instruction cache line size of 16 bytes bit 18-16 IA!(K|DM) EBASE+0x180 transition). EJTAG debug hardware instruction break matched. 0xBFC0_0480 A reference to an address that is in one of the EBASE+0x180 Watch registers (fetch). Fetch address alignment error. Fetch reference to EBASE+0x180 protected address. Fetch TLB miss or fetch TLB hit to page with V = 0. EBASE if Status.EXL = 0 EBASE+0x180 if Status.EXL == 1 An instruction fetch matched a valid TLB entry that EBASE+0x180 had the XI bit set. Instruction fetch bus error. EBASE+0x180 Deferred Watch  2015-2021 Microchip Technology Inc. DIB WATCH AdEL TLBL TLBL Execute Inhibit IBE 0xBFC0_0000 BEV, ERL BEV, SR, ERL — — — — — — DSS DINT — — BEV, NMI, ERL MCHECK, EXL IPL — — — 0x18 _general_exception_handler — 0x00 See Table 7-2. WP, EXL — 0x17 _general_exception_handler — EXL DIB — — 0x17 — _general_exception_handler EXL — 0x04 _general_exception_handler — — — — 0x02 0x02 — _general_exception_handler EXL — 0x14 _general_exception_handler EXL — 0x06 _general_exception_handler _on_reset _on_reset — — _nmi_handler PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 128 7.1 Exception Type (In Order of Priority) Instruction Validity Exceptions Execute Exception Tr DDBL/DDBS WATCH AdEL AdES TLBL TLBS DBE DDBL CBrk MIPS32® M-CLASS MICROPROCESSOR CORE EXCEPTION TYPES (CONTINUED) Description Branches to Status Bits Set An instruction could not be completed because it was not allowed to access the required resources (Coprocessor Unusable) or was illegal (Reserved Instruction). If both exceptions occur on the same instruction, the Coprocessor Unusable Exception takes priority over the Reserved Instruction Exception. An instruction-based exception occurred: Integer overflow, trap, system call, breakpoint, floating point, or DSP ASE state disabled exception. Execution of a trap (when trap condition is true). EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value). A reference to an address that is in one of the Watch registers (data). Load address alignment error. User mode load reference to kernel address. Store address alignment error. User mode store to kernel address. Load TLB miss or load TLB hit to page with V = 0. Store TLB miss or store TLB hit to page with V = 0. Load or store bus error. EJTAG data hardware breakpoint matched in load data compare. EJTAG complex breakpoint. EBASE+0x180 EXL — EBASE+0x180 EXL — EBASE+0x180 0xBFC0_0480 EXL — — DDBL or DDBS 0x0D — _general_exception_handler — EBASE+0x180 EXL — 0x17 _general_exception_handler EBASE+0x180 EXL — 0x04 _general_exception_handler EBASE+0x180 EXL — 0x05 _general_exception_handler EBASE+0x180 EBASE+0x180 EBASE+0x180 0xBFC0_0480 EXL EXL EXL — — — — DDBL 0x02 0x03 0x07 — _general_exception_handler _general_exception_handler _general_exception_handler — 0xBFC0_0480 — DIBIMPR, DDBLIMPR, and/or DDBSIMPR — — DS60001320H-page 129 Lowest Priority Debug Bits EXCCODE Set 0x0A or 0x0B XC32 Function Name _general_exception_handler 0x08-0x0C _general_exception_handler PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-1: Interrupts For details on the Variable Offset feature, refer to 8.5.2 “Variable Offset” in Section 8. “Interrupt Controller” (DS60001108) of the “PIC32 Family Reference Manual”. The PIC32MZ EF family uses variable offsets for vector spacing. This allows the interrupt vector spacing to be configured according to application needs. A unique interrupt vector offset can be set for each vector using its associated OFFx register. TABLE 7-2: Table 7-2 provides the Interrupt IRQ, vector and bit location information. INTERRUPT IRQ, VECTOR, AND BIT LOCATION Interrupt Source(1) XC32 Vector Name IRQ # Vector # Interrupt Bit Location Flag Enable Persistent Sub-priority Interrupt Priority Highest Natural Order Priority  2015-2021 Microchip Technology Inc. Core Timer Interrupt _CORE_TIMER_VECTOR 0 OFF000 IFS0 IEC0 IPC0 IPC0 No Core Software Interrupt 0 _CORE_SOFTWARE_0_VECTOR 1 OFF001 IFS0 IEC0 IPC0 IPC0 No Core Software Interrupt 1 _CORE_SOFTWARE_1_VECTOR 2 OFF002 IFS0 IEC0 IPC0 IPC0 No External Interrupt 0 _EXTERNAL_0_VECTOR 3 OFF003 IFS0 IEC0 IPC0 IPC0 No Timer1 _TIMER_1_VECTOR 4 OFF004 IFS0 IEC0 IPC1 IPC1 No Input Capture 1 Error _INPUT_CAPTURE_1_ERROR_VECTOR 5 OFF005 IFS0 IEC0 IPC1 IPC1 Yes Input Capture 1 _INPUT_CAPTURE_1_VECTOR 6 OFF006 IFS0 IEC0 IPC1 IPC1 Yes Output Compare 1 _OUTPUT_COMPARE_1_VECTOR 7 OFF007 IFS0 IEC0 IPC1 IPC1 No External Interrupt 1 _EXTERNAL_1_VECTOR 8 OFF008 IFS0 IEC0 IPC2 IPC2 No Timer2 _TIMER_2_VECTOR 9 OFF009 IFS0 IEC0 IPC2 IPC2 No Input Capture 2 Error _INPUT_CAPTURE_2_ERROR_VECTOR 10 OFF010 IFS0 IEC0 IPC2 IPC2 Yes Input Capture 2 _INPUT_CAPTURE_2_VECTOR 11 IPC2 Yes Output Compare 2 _OUTPUT_COMPARE_2_VECTOR 12 OFF012 IFS0 IEC0 IPC3 IPC3 No External Interrupt 2 _EXTERNAL_2_VECTOR 13 OFF013 IFS0 IEC0 IPC3 IPC3 No Timer3 _TIMER_3_VECTOR 14 OFF014 IFS0 IEC0 IPC3 IPC3 No Input Capture 3 Error _INPUT_CAPTURE_3_ERROR_VECTOR 15 OFF015 IFS0 IEC0 IPC3 IPC3 Yes Input Capture 3 _INPUT_CAPTURE_3_VECTOR 16 OFF016 IFS0 IEC0 IPC4 IPC4 Yes Output Compare 3 _OUTPUT_COMPARE_3_VECTOR 17 OFF017 IFS0 IEC0 IPC4 IPC4 No External Interrupt 3 _EXTERNAL_3_VECTOR 18 OFF018 IFS0 IEC0 IPC4 IPC4 No Timer4 _TIMER_4_VECTOR 19 OFF019 IFS0 IEC0 IPC4 IPC4 No Input Capture 4 Error _INPUT_CAPTURE_4_ERROR_VECTOR 20 OFF020 IFS0 IEC0 IPC5 IPC5 Yes Input Capture 4 _INPUT_CAPTURE_4_VECTOR 21 OFF021 IFS0 IEC0 IPC5 IPC5 Yes Note 1: 2: 3: 4: OFF011 IFS0 IEC0 IPC2 Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals. This interrupt source is not available on 64-pin devices. This interrupt source is not available on 100-pin devices. This interrupt source is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 130 7.2 INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) XC32 Vector Name IRQ # Vector # Interrupt Bit Location Flag Enable Priority Sub-priority Persistent Interrupt DS60001320H-page 131 Output Compare 4 _OUTPUT_COMPARE_4_VECTOR 22 OFF022 IFS0 IEC0 IPC5 IPC5 No External Interrupt 4 _EXTERNAL_4_VECTOR 23 OFF023 IFS0 IEC0 IPC5 IPC5 No Timer5 _TIMER_5_VECTOR 24 OFF024 IFS0 IEC0 IPC6 IPC6 No Input Capture 5 Error _INPUT_CAPTURE_5_ERROR_VECTOR 25 OFF025 IFS0 IEC0 IPC6 IPC6 Yes Input Capture 5 _INPUT_CAPTURE_5_VECTOR 26 OFF026 IFS0 IEC0 IPC6 IPC6 Yes Output Compare 5 _OUTPUT_COMPARE_5_VECTOR 27 OFF027 IFS0 IEC0 IPC6 IPC6 No Timer6 _TIMER_6_VECTOR 28 OFF028 IFS0 IEC0 IPC7 IPC7 No Input Capture 6 Error _INPUT_CAPTURE_6_ERROR_VECTOR 29 OFF029 IFS0 IEC0 IPC7 IPC7 Yes Input Capture 6 _INPUT_CAPTURE_6_VECTOR 30 OFF030 IFS0 IEC0 IPC7 IPC7 Yes Output Compare 6 _OUTPUT_COMPARE_6_VECTOR 31 OFF031 IFS0 IEC0 IPC7 IPC7 No Timer7 _TIMER_7_VECTOR 32 OFF032 IFS1 IEC1 IPC8 IPC8 No Input Capture 7 Error _INPUT_CAPTURE_7_ERROR_VECTOR 33 OFF033 IFS1 IEC1 IPC8 IPC8 Yes Input Capture 7 _INPUT_CAPTURE_7_VECTOR 34 OFF034 IFS1 IEC1 IPC8 IPC8 Yes Output Compare 7 _OUTPUT_COMPARE_7_VECTOR 35 OFF035 IFS1 IEC1 IPC8 IPC8 No Timer8 _TIMER_8_VECTOR 36 OFF036 IFS1 IEC1 IPC9 IPC9 No Input Capture 8 Error _INPUT_CAPTURE_8_ERROR_VECTOR 37 OFF037 IFS1 IEC1 IPC9 IPC9 Yes Input Capture 8 _INPUT_CAPTURE_8_VECTOR 38 OFF038 IFS1 IEC1 IPC9 IPC9 Yes Output Compare 8 _OUTPUT_COMPARE_8_VECTOR 39 OFF039 IFS1 IEC1 IPC9 IPC9 No Timer9 _TIMER_9_VECTOR 40 OFF040 IFS1 IEC1 IPC10 IPC10 No Input Capture 9 Error _INPUT_CAPTURE_9_ERROR_VECTOR 41 OFF041 IFS1 IEC1 IPC10 IPC10 Yes Input Capture 9 _INPUT_CAPTURE_9_VECTOR 42 OFF042 IFS1 IEC1 IPC10 IPC10 Yes Output Compare 9 _OUTPUT_COMPARE_9_VECTOR 43 OFF043 IFS1 IEC1 IPC10 IPC10 No ADC Global Interrupt _ADC_VECTOR 44 OFF044 IFS1 IEC1 IPC11 IPC11 Yes ADC FIFO Data Ready Interrupt _ADC_FIFO_VECTOR 45 OFF045 IFS1 IEC1 IPC11 IPC11 Yes ADC Digital Comparator 1 _ADC_DC1_VECTOR 46 OFF046 IFS1 IEC1 IPC11 IPC11 Yes ADC Digital Comparator 2 _ADC_DC2_VECTOR 47 OFF047 IFS1 IEC1 IPC11 IPC11 Yes ADC Digital Comparator 3 _ADC_DC3_VECTOR 48 OFF048 IFS1 IEC1 IPC12 IPC12 Yes ADC Digital Comparator 4 _ADC_DC4_VECTOR 49 OFF049 IFS1 IEC1 IPC12 IPC12 Yes Note 1: 2: 3: 4: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals. This interrupt source is not available on 64-pin devices. This interrupt source is not available on 100-pin devices. This interrupt source is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-2: INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) XC32 Vector Name IRQ # Vector # Interrupt Bit Location Flag Enable Persistent Sub-priority Interrupt Priority  2015-2021 Microchip Technology Inc. ADC Digital Comparator 5 _ADC_DC5_VECTOR 50 OFF050 IFS1 IEC1 IPC12 IPC12 Yes ADC Digital Comparator 6 _ADC_DC6_VECTOR 51 OFF051 IFS1 IEC1 IPC12 IPC12 Yes ADC Digital Filter 1 _ADC_DF1_VECTOR 52 OFF052 IFS1 IEC1 IPC13 IPC13 Yes ADC Digital Filter 2 _ADC_DF2_VECTOR 53 OFF053 IFS1 IEC1 IPC13 IPC13 Yes ADC Digital Filter 3 _ADC_DF3_VECTOR 54 OFF054 IFS1 IEC1 IPC13 IPC13 Yes ADC Digital Filter 4 _ADC_DF4_VECTOR 55 OFF055 IFS1 IEC1 IPC13 IPC13 Yes ADC Digital Filter 5 _ADC_DF5_VECTOR 56 OFF056 IFS1 IEC1 IPC14 IPC14 Yes ADC Digital Filter 6 _ADC_DF6_VECTOR 57 OFF057 IFS1 IEC1 IPC14 IPC14 Yes ADC Fault _ADC_FAULT_VECTOR 58 OFF058 IFS1 IEC1 IPC14 IPC14 No ADC Data 0 _ADC_DATA0_VECTOR 59 OFF059 IFS1 IEC1 IPC14 IPC14 Yes ADC Data 1 _ADC_DATA1_VECTOR 60 OFF060 IFS1 IEC1 IPC15 IPC15 Yes ADC Data 2 _ADC_DATA2_VECTOR 61 OFF061 IFS1 IEC1 IPC15 IPC15 Yes ADC Data 3 _ADC_DATA3_VECTOR 62 OFF062 IFS1 IEC1 IPC15 IPC15 Yes ADC Data 4 _ADC_DATA4_VECTOR 63 OFF063 IFS1 IEC1 IPC15 IPC15 Yes ADC Data 5 _ADC_DATA5_VECTOR 64 OFF064 IFS2 IEC2 IPC16 IPC16 Yes ADC Data 6 _ADC_DATA6_VECTOR 65 OFF065 IFS2 IEC2 IPC16 IPC16 Yes ADC Data 7 _ADC_DATA7_VECTOR 66 OFF066 IFS2 IEC2 IPC16 IPC16 Yes ADC Data 8 _ADC_DATA8_VECTOR 67 OFF067 IFS2 IEC2 IPC16 IPC16 Yes ADC Data 9 _ADC_DATA9_VECTOR 68 OFF068 IFS2 IEC2 IPC17 IPC17 Yes ADC Data 10 _ADC_DATA10_VECTOR 69 OFF069 IFS2 IEC2 IPC17 IPC17 Yes ADC Data 11 _ADC_DATA11_VECTOR 70 OFF070 IFS2 IEC2 IPC17 IPC17 Yes ADC Data 12 _ADC_DATA12_VECTOR 71 OFF071 IFS2 IEC2 IPC17 IPC17 Yes ADC Data 13 _ADC_DATA13_VECTOR 72 OFF072 IFS2 IEC2 IPC18 IPC18 Yes ADC Data 14 _ADC_DATA14_VECTOR 73 OFF073 IFS2 IEC2 IPC18 IPC18 Yes ADC Data 15 _ADC_DATA15_VECTOR 74 OFF074 IFS2 IEC2 IPC18 IPC18 Yes ADC Data 16 _ADC_DATA16_VECTOR 75 OFF075 IFS2 IEC2 IPC18 IPC18 Yes ADC Data 17 _ADC_DATA17_VECTOR 76 OFF076 IFS2 IEC2 IPC19 IPC19 Yes ADC Data 18 _ADC_DATA18_VECTOR 77 OFF077 IFS2 IEC2 IPC19 IPC19 Yes Note 1: 2: 3: 4: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals. This interrupt source is not available on 64-pin devices. This interrupt source is not available on 100-pin devices. This interrupt source is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 132 TABLE 7-2: INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) XC32 Vector Name IRQ # Vector # Interrupt Bit Location Flag Enable Priority Sub-priority Persistent Interrupt ADC Data 19(2) _ADC_DATA19_VECTOR 78 OFF078 IFS2 IEC2 IPC19 IPC19 Yes ADC Data 20(2) _ADC_DATA20_VECTOR 79 OFF079 IFS2 IEC2 IPC19 IPC19 Yes (2) _ADC_DATA21_VECTOR 80 OFF080 IFS2 IEC2 IPC20 IPC20 Yes ADC Data 22(2) _ADC_DATA22_VECTOR 81 OFF081 IFS2 IEC2 IPC20 IPC20 Yes ADC Data 23(2) _ADC_DATA23_VECTOR 82 OFF082 IFS2 IEC2 IPC20 IPC20 Yes ADC Data 24(2) _ADC_DATA24_VECTOR 83 OFF083 IFS2 IEC2 IPC20 IPC20 Yes 25(2) _ADC_DATA25_VECTOR 84 OFF084 IFS2 IEC2 IPC21 IPC21 Yes ADC Data 26(2) _ADC_DATA26_VECTOR 85 OFF085 IFS2 IEC2 IPC21 IPC21 Yes ADC Data 27(2) _ADC_DATA27_VECTOR 86 OFF086 IFS2 IEC2 IPC21 IPC21 Yes ADC Data 28(2) _ADC_DATA28_VECTOR 87 OFF087 IFS2 IEC2 IPC21 IPC21 Yes (2) _ADC_DATA29_VECTOR 88 OFF088 IFS2 IEC2 IPC22 IPC22 Yes ADC Data 30(2) _ADC_DATA30_VECTOR 89 OFF089 IFS2 IEC2 IPC22 IPC22 Yes ADC Data 31(2) _ADC_DATA31_VECTOR 90 OFF090 IFS2 IEC2 IPC22 IPC22 Yes ADC Data 32(2) _ADC_DATA32_VECTOR 91 OFF091 IFS2 IEC2 IPC22 IPC22 Yes (2) _ADC_DATA33_VECTOR 92 OFF092 IFS2 IEC2 IPC23 IPC23 Yes ADC Data 34(2) _ADC_DATA34_VECTOR 93 OFF093 IFS2 IEC2 IPC23 IPC23 Yes ADC Data 35(2,3) _ADC_DATA35_VECTOR 94 OFF094 IFS2 IEC2 IPC23 IPC23 Yes ADC Data 36(2,3) _ADC_DATA36_VECTOR 95 OFF095 IFS2 IEC2 IPC23 IPC23 Yes 37(2,3) _ADC_DATA37_VECTOR 96 OFF096 IFS3 IEC3 IPC24 IPC24 Yes ADC Data 38(2,3) _ADC_DATA38_VECTOR 97 OFF097 IFS3 IEC3 IPC24 IPC24 Yes ADC Data 39(2,3) _ADC_DATA39_VECTOR 98 OFF098 IFS3 IEC3 IPC24 IPC24 Yes ADC Data 40(2,3) _ADC_DATA40_VECTOR 99 OFF099 IFS3 IEC3 IPC24 IPC24 Yes (2,3) _ADC_DATA41_VECTOR 100 OFF100 IFS3 IEC3 IPC25 IPC25 Yes ADC Data 42(2,3) _ADC_DATA42_VECTOR 101 OFF101 IFS3 IEC3 IPC25 IPC25 Yes ADC Data 43 _ADC_DATA43_VECTOR 102 OFF102 IFS3 IEC3 IPC25 IPC25 Yes ADC Data 44 _ADC_DATA44_VECTOR 103 OFF103 IFS3 IEC3 IPC25 IPC25 Yes Core Performance Counter Interrupt _CORE_PERF_COUNT_VECTOR 104 OFF104 IFS3 IEC3 IPC26 IPC26 No Core Fast Debug Channel Interrupt _CORE_FAST_DEBUG_CHAN_VECTOR 105 OFF105 IFS3 IEC3 IPC26 IPC26 Yes ADC Data 21 ADC Data ADC Data 29 ADC Data 33 ADC Data ADC Data 41 DS60001320H-page 133 Note 1: 2: 3: 4: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals. This interrupt source is not available on 64-pin devices. This interrupt source is not available on 100-pin devices. This interrupt source is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-2: INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) XC32 Vector Name IRQ # Vector # Interrupt Bit Location Flag Enable Persistent Sub-priority Interrupt Priority System Bus Protection Violation _SYSTEM_BUS_PROTECTION_VECTOR 106 OFF106 IFS3 IEC3 IPC26 IPC26 Yes Crypto Engine Event _CRYPTO_VECTOR Yes Reserved — 107 OFF107 IFS3 IEC3 IPC26 IPC26 108 — — — — — — SPI1 Fault _SPI1_FAULT_VECTOR 109 OFF109 IFS3 IEC3 IPC27 IPC27 Yes SPI1 Receive Done _SPI1_RX_VECTOR 110 OFF110 IFS3 IEC3 IPC27 IPC27 Yes SPI1 Transfer Done _SPI1_TX_VECTOR 111 OFF111 IFS3 IEC3 IPC27 IPC27 Yes UART1 Fault _UART1_FAULT_VECTOR 112 OFF112 IFS3 IEC3 IPC28 IPC28 Yes UART1 Receive Done _UART1_RX_VECTOR 113 OFF113 IFS3 IEC3 IPC28 IPC28 Yes UART1 Transfer Done _UART1_TX_VECTOR 114 OFF114 IFS3 IEC3 IPC28 IPC28 Yes I2C1 Bus Collision Event _I2C1_BUS_VECTOR 115 OFF115 IFS3 IEC3 IPC28 IPC28 Yes I2C1 Client Event _I2C1_SLAVE_VECTOR 116 OFF116 IFS3 IEC3 IPC29 IPC29 Yes I2C1 Host Event _I2C1_MASTER_VECTOR 117 OFF117 IFS3 IEC3 IPC29 IPC29 Yes PORTA Input Change Interrupt(2)  2015-2021 Microchip Technology Inc. _CHANGE_NOTICE_A_VECTOR 118 OFF118 IFS3 IEC3 IPC29 IPC29 Yes PORTB Input Change Interrupt _CHANGE_NOTICE_B_VECTOR 119 OFF119 IFS3 IEC3 IPC29 IPC29 Yes PORTC Input Change Interrupt _CHANGE_NOTICE_C_VECTOR 120 OFF120 IFS3 IEC3 IPC30 IPC30 Yes PORTD Input Change Interrupt _CHANGE_NOTICE_D_VECTOR 121 OFF121 IFS3 IEC3 IPC30 IPC30 Yes PORTE Input Change Interrupt _CHANGE_NOTICE_E_VECTOR 122 OFF122 IFS3 IEC3 IPC30 IPC30 Yes PORTF Input Change Interrupt _CHANGE_NOTICE_F_VECTOR 123 OFF123 IFS3 IEC3 IPC30 IPC30 Yes PORTG Input Change Interrupt _CHANGE_NOTICE_G_VECTOR 124 OFF124 IFS3 IEC3 IPC31 IPC31 Yes PORTH Input Change Interrupt(2,3) _CHANGE_NOTICE_H_VECTOR 125 OFF125 IFS3 IEC3 IPC31 IPC31 Yes (2,3) PORTJ Input Change Interrupt _CHANGE_NOTICE_J_VECTOR 126 OFF126 IFS3 IEC3 IPC31 IPC31 Yes PORTK Input Change Interrupt(2,3,4) _CHANGE_NOTICE_K_VECTOR 127 OFF127 IFS3 IEC3 IPC31 IPC31 Yes Parallel Host Port _PMP_VECTOR 128 OFF128 IFS4 IEC4 IPC32 IPC32 Yes Parallel Host Port Error _PMP_ERROR_VECTOR 129 OFF129 IFS4 IEC4 IPC32 IPC32 Yes Comparator 1 Interrupt _COMPARATOR_1_VECTOR 130 OFF130 IFS4 IEC4 IPC32 IPC32 No Comparator 2 Interrupt _COMPARATOR_2_VECTOR 131 OFF131 IFS4 IEC4 IPC32 IPC32 No USB General Event _USB1_VECTOR 132 OFF132 IFS4 IEC4 IPC33 IPC33 Yes USB DMA Event _USB1_DMA_VECTOR 133 OFF133 IFS4 IEC4 IPC33 IPC33 Yes Note 1: 2: 3: 4: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals. This interrupt source is not available on 64-pin devices. This interrupt source is not available on 100-pin devices. This interrupt source is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 134 TABLE 7-2: INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) XC32 Vector Name IRQ # Vector # Interrupt Bit Location Flag Enable Priority Sub-priority Persistent Interrupt DMA Channel 0 _DMA0_VECTOR 134 OFF134 IFS4 IEC4 IPC33 IPC33 No DMA Channel 1 _DMA1_VECTOR 135 OFF135 IFS4 IEC4 IPC33 IPC33 No DMA Channel 2 _DMA2_VECTOR 136 OFF136 IFS4 IEC4 IPC34 IPC34 No DMA Channel 3 _DMA3_VECTOR 137 OFF137 IFS4 IEC4 IPC34 IPC34 No DMA Channel 4 _DMA4_VECTOR 138 OFF138 IFS4 IEC4 IPC34 IPC34 No DMA Channel 5 _DMA5_VECTOR 139 OFF139 IFS4 IEC4 IPC34 IPC34 No DMA Channel 6 _DMA6_VECTOR 140 OFF140 IFS4 IEC4 IPC35 No DMA Channel 7 _DMA7_VECTOR 141 OFF141 IFS4 IEC4 IPC35 IPC35 No SPI2 Fault _SPI2_FAULT_VECTOR 142 OFF142 IFS4 IEC4 IPC35 IPC35 Yes SPI2 Receive Done _SPI2_RX_VECTOR 143 OFF143 IFS4 IEC4 IPC35 IPC35 Yes SPI2 Transfer Done _SPI2_TX_VECTOR 144 OFF144 IFS4 IEC4 IPC36 IPC36 Yes UART2 Fault _UART2_FAULT_VECTOR 145 OFF145 IFS4 IEC4 IPC36 IPC36 Yes UART2 Receive Done _UART2_RX_VECTOR 146 OFF146 IFS4 IEC4 IPC36 IPC36 Yes UART2 Transfer Done _UART2_TX_VECTOR 147 OFF147 IFS4 IEC4 IPC36 IPC36 Yes I2C2 Bus Collision Event _I2C2_BUS_VECTOR 148 OFF148 IFS4 IEC4 IPC37 IPC37 Yes I2C2 Client Event(2) _I2C2_SLAVE_VECTOR 149 OFF149 IFS4 IEC4 IPC37 IPC37 Yes I2C2 Host Event(2) _I2C2_MASTER_VECTOR 150 OFF150 IFS4 IEC4 IPC37 IPC37 Yes Control Area Network 1 _CAN1_VECTOR 151 OFF151 IFS4 IEC4 IPC37 IPC37 Yes Control Area Network 2 _CAN2_VECTOR 152 OFF152 IFS4 IEC4 IPC38 IPC38 Yes Ethernet Interrupt _ETHERNET_VECTOR 153 OFF153 IFS4 IEC4 IPC38 IPC38 Yes SPI3 Fault _SPI3_FAULT_VECTOR 154 OFF154 IFS4 IEC4 IPC38 IPC38 Yes SPI3 Receive Done _SPI3_RX_VECTOR 155 OFF155 IFS4 IEC4 IPC38 IPC38 Yes SPI3 Transfer Done _SPI3_TX_VECTOR 156 OFF156 IFS4 IEC4 IPC39 IPC39 Yes UART3 Fault _UART3_FAULT_VECTOR 157 OFF157 IFS4 IEC4 IPC39 IPC39 Yes UART3 Receive Done _UART3_RX_VECTOR 158 OFF158 IFS4 IEC4 IPC39 IPC39 Yes UART3 Transfer Done _UART3_TX_VECTOR 159 OFF159 IFS4 IEC4 IPC39 IPC39 Yes I2C3 Bus Collision Event _I2C3_BUS_VECTOR 160 OFF160 IFS5 IEC5 IPC40 IPC40 Yes I2C3 Client Event _I2C3_SLAVE_VECTOR 161 OFF161 IFS5 IEC5 IPC40 IPC40 Yes (2) DS60001320H-page 135 Note 1: 2: 3: 4: IPC35 Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals. This interrupt source is not available on 64-pin devices. This interrupt source is not available on 100-pin devices. This interrupt source is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-2: INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) XC32 Vector Name IRQ # Vector # Interrupt Bit Location Flag Enable Persistent Sub-priority Interrupt Priority  2015-2021 Microchip Technology Inc. I2C3 Host Event _I2C3_MASTER_VECTOR 162 OFF162 IFS5 IEC5 IPC40 IPC40 Yes SPI4 Fault _SPI4_FAULT_VECTOR 163 OFF163 IFS5 IEC5 IPC40 IPC40 Yes SPI4 Receive Done _SPI4_RX_VECTOR 164 OFF164 IFS5 IEC5 IPC41 IPC41 Yes SPI4 Transfer Done _SPI4_TX_VECTOR 165 OFF165 IFS5 IEC5 IPC41 IPC41 Yes Real Time Clock _RTCC_VECTOR 166 OFF166 IFS5 IEC5 IPC41 IPC41 No Flash Control Event _FLASH_CONTROL_VECTOR 167 OFF167 IFS5 IEC5 IPC41 IPC41 No Prefetch Module SEC Event _PREFETCH_VECTOR 168 OFF168 IFS5 IEC5 IPC42 IPC42 Yes SQI1 Event _SQI1_VECTOR 169 OFF169 IFS5 IEC5 IPC42 IPC42 Yes UART4 Fault _UART4_FAULT_VECTOR 170 OFF170 IFS5 IEC5 IPC42 IPC42 Yes UART4 Receive Done _UART4_RX_VECTOR 171 OFF171 IFS5 IEC5 IPC42 IPC42 Yes UART4 Transfer Done _UART4_TX_VECTOR 172 OFF172 IFS5 IEC5 IPC43 IPC43 Yes I2C4 Bus Collision Event _I2C4_BUS_VECTOR 173 OFF173 IFS5 IEC5 IPC43 IPC43 Yes I2C4 Client Event _I2C4_SLAVE_VECTOR 174 OFF174 IFS5 IEC5 IPC43 IPC43 Yes I2C4 Host Event _I2C4_MASTER_VECTOR 175 OFF175 IFS5 IEC5 IPC43 IPC43 Yes SPI5 Fault(2) _SPI5_FAULT_VECTOR 176 OFF176 IFS5 IEC5 IPC44 IPC44 Yes SPI5 Receive Done(2) _SPI5_RX_VECTOR 177 OFF177 IFS5 IEC5 IPC44 IPC44 Yes (2) SPI5 Transfer Done _SPI5_TX_VECTOR 178 OFF178 IFS5 IEC5 IPC44 IPC44 Yes UART5 Fault _UART5_FAULT_VECTOR 179 OFF179 IFS5 IEC5 IPC44 IPC44 Yes UART5 Receive Done _UART5_RX_VECTOR 180 OFF180 IFS5 IEC5 IPC45 IPC45 Yes UART5 Transfer Done _UART5_TX_VECTOR 181 OFF181 IFS5 IEC5 IPC45 IPC45 Yes I2C5 Bus Collision Event _I2C5_BUS_VECTOR 182 OFF182 IFS5 IEC5 IPC45 IPC45 Yes I2C5 Client Event _I2C5_SLAVE_VECTOR 183 OFF183 IFS5 IEC5 IPC45 IPC45 Yes I2C5 Host Event _I2C5_MASTER_VECTOR 184 OFF184 IFS5 IEC5 IPC46 IPC46 Yes SPI6 Fault(2) _SPI6_FAULT_VECTOR 185 OFF185 IFS5 IEC5 IPC46 IPC46 Yes Done(2) _SPI6_RX_VECTOR 186 OFF186 IFS5 IEC5 IPC46 IPC46 Yes SPI6 Transfer Done(2) _SPI6_TX_VECTOR 187 OFF187 IFS5 IEC5 IPC46 IPC46 Yes UART6 Fault _UART6_FAULT_VECTOR 188 OFF188 IFS5 IEC5 IPC47 IPC47 Yes UART6 Receive Done _UART6_RX_VECTOR 189 OFF189 IFS5 IEC5 IPC47 IPC47 Yes SPI6 Receive Note 1: 2: 3: 4: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals. This interrupt source is not available on 64-pin devices. This interrupt source is not available on 100-pin devices. This interrupt source is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 136 TABLE 7-2: INTERRUPT IRQ, VECTOR, AND BIT LOCATION (CONTINUED) Interrupt Source(1) UART6 Transfer Done Reserved XC32 Vector Name _UART6_TX_VECTOR — IRQ # Vector # Interrupt Bit Location Flag Enable Priority Sub-priority 190 OFF190 IFS5 IEC5 IPC47 IPC47 191 — — — — — IPC48 IPC48 Yes IPC48 Yes _ADC_EOS_VECTOR 192 OFF192 IFS6 IEC6 ADC Analog Circuits Ready _ADC_ARDY_VECTOR 193 OFF193 IFS6 IEC6 IPC48 ADC Update Ready _ADC_URDY_VECTOR 194 OFF194 IFS6 IEC6 IPC48 IPC48 — ADC Group Early Interrupt Request Reserved _ADC_EARLY_VECTOR — 195 — — — 196 OFF196 IFS6 IEC6 197 — — — Yes — ADC End of Scan Ready Reserved Persistent Interrupt Yes — — — IPC49 IPC49 Yes — — — ADC0 Early Interrupt _ADC0_EARLY_VECTOR 198 OFF198 IFS6 IEC6 IPC49 IPC49 Yes ADC1 Early Interrupt _ADC1_EARLY_VECTOR 199 OFF199 IFS6 IEC6 IPC49 IPC49 Yes ADC2 Early Interrupt _ADC2_EARLY_VECTOR 200 OFF200 IFS6 IEC6 IPC50 Yes ADC3 Early Interrupt _ADC2_EARLY_VECTOR 201 OFF201 IFS6 IEC6 IPC50 IPC50 Yes ADC4 Early Interrupt _ADC4_EARLY_VECTOR 202 OFF202 IFS6 IEC6 IPC50 IPC50 Reserved Reserved IPC50 — 203 — — — — — 204 — — — — — Yes — — — IPC51 Yes ADC7 Early Interrupt _ADC7_EARLY_VECTOR 205 OFF205 IFS6 IEC6 IPC51 ADC0 Warm Interrupt _ADC0_WARM_VECTOR 206 OFF206 IFS6 IEC6 IPC51 IPC51 Yes ADC1 Warm Interrupt _ADC1_WARM_VECTOR 207 OFF207 IFS6 IEC6 IPC51 IPC51 Yes ADC2 Warm Interrupt _ADC2_WARM_VECTOR 208 OFF208 IFS6 IEC6 IPC52 Yes ADC3 Warm Interrupt _ADC3_WARM_VECTOR 209 OFF209 IFS6 IEC6 IPC52 IPC52 Yes ADC4 Warm Interrupt _ADC4_WARM_VECTOR 210 OFF210 IFS6 IEC6 IPC52 IPC52 Reserved Reserved ADC7 Warm Interrupt IPC52 — 211 — — — — — 212 — — — — _ADC7_WARM_VECTOR 213 OFF213 IFS6 IEC6 IPC53 Lowest Natural Order Priority DS60001320H-page 137 Note 1: 2: 3: 4: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MZ EF Family Features” for the list of available peripherals. This interrupt source is not available on 64-pin devices. This interrupt source is not available on 100-pin devices. This interrupt source is not available on 124-pin devices. — Yes — — — IPC53 Yes PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-2: Interrupt Control Registers 0000 INTCON 0010 PRISS 0020 INTSTAT 0030 IPTMR 0040 IFS0 (6) 0070 IFS3 29/13 28/12 15:0 — — — MVEC 0090 IFS5 00A0 IFS6 24/8 — TPC 23/7 22/6 21/5 — — — — — — — — 0000 — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000 PRI7SS PRI6SS PRI5SS 15:0 PRI3SS PRI2SS PRI1SS 31:16 — — — — — 15:0 — — — — — — — — — — — 20/4 19/3 18/2 17/1 16/0 PRI4SS — SRIPL 0000 — — — SS0 0000 — — — — 0000 SIRQ 31:16 0000 0000 IPTMR 15:0 0000 31:16 OC6IF IC6IF IC6EIF T6IF OC5IF IC5IF IC5EIF T5IF INT4IF OC4IF IC4IF IC4EIF T4IF INT3IF OC3IF IC3IF 0000 15:0 IC3EIF T3IF INT2IF OC2IF IC2IF IC2EIF T2IF INT1IF OC1IF IC1IF IC1EIF T1IF INT0IF CS1IF CS0IF CTIF 0000 ADCD3IF ADCD2IF ADCD1IF ADCD0IF ADCFLTIF ADCIF OC9IF ADCDF6IF ADCDF5IF ADCDF4IF ADCDF3IF ADCDF2IF ADCDF1IF ADCDC6IF ADCDC5IF IC9IF IC9EIF IC7IF IC7EIF ADCD31IF ADCD30IF ADCD29IF ADCD28IF ADCD27IF ADCD26IF ADCD25IF ADCD24IF ADCD23IF ADCD22IF ADCD21IF 0000 15:0 ADCD20IF ADCD19IF ADCD18IF ADCD17IF ADCD16IF ADCD13IF ADCD12IF ADCD11IF ADCD10IF ADCD5IF 0000 31:16 CNKIF(8) SPI1TXIF T9IF ADCD15IF ADCD14IF CNJIF CNHIF CNGIF CNFIF CNEIF CNDIF CNCIF SPI1RXIF SPI1EIF — CRPTIF(7) SBIF CFDCIF CPCIF OC8IF CNBIF IC8IF CNAIF IC8EIF I2C1MIF T8IF OC7IF ADCDC4IF ADCDC3IF 0000 31:16 ADCD36IF ADCD35IF ADCD34IF ADCD33IF ADCD32IF 0000 ADCD8IF ADCD7IF ADCD6IF I2C1SIF I2C1BIF U1TXIF U1RXIF ADCD39IF ADCD38IF ADCD37IF 0000 SPI2TXIF 0000 ADCD44IF ADCD43IF ADCD42IF ADCD41IF ADCD40IF U3TXIF U3RXIF U3EIF SPI3TXIF SPI3RXIF SPI3EIF ETHIF CAN2IF(3) U2TXIF U2RXIF U2EIF 15:0 SPI2RXIF SPI2EIF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF DMA0IF USBDMAIF USBIF CMP2IF CMP1IF PMPEIF 31:16 — U6TXIF U6RXIF U6EIF I2C5MIF I2C5SIF I2C5BIF U5TXIF U5RXIF U5EIF 15:0 I2C4MIF I2C4SIF I2C4BIF U4TXIF U4RXIF U4EIF SQI1IF PREIF FCEIF RTCCIF SPI4TXIF SPI4RXIF SPI4EIF I2C3MIF I2C3SIF 31:16 — — — — — — — — — — ADC7WIF — — ADC4WIF ADC3WIF SPI6TXIF(2) SPI6RXIF(2) SPI6EIF(2) T7IF ADCD9IF 31:16 CAN1IF(3) I2C2MIF(2) I2C2SIF(2) I2C2BIF(2) U1EIF PMPIF 0000 0000 SPI5TXIF(2) SPI5RXIF(2) SPI5EIF(2) 0000 I2C3BIF 0000 ADC2WIF 0000  2015-2021 Microchip Technology Inc. ADC0WIF ADC7EIF — — ADC4EIF ADC3EIF ADC2EIF ADC1EIF ADC0EIF — ADCGRPIF — 31:16 OC6IE IC6IE IC6EIE T6IE OC5IE IC5IE IC5EIE T5IE INT4IE OC4IE IC4IE IC4EIE T4IE INT3IE OC3IE IC3IE 0000 15:0 IC3EIE T3IE INT2IE OC2IE IC2IE IC2EIE T2IE INT1IE OC1IE IC1IE IC1EIE T1IE INT0IE CS1IE CS0IE CTIE 0000 ADCD3IE ADCD2IE ADCD1IE ADCD0IE ADCFLTIE ADCIE OC9IE 15:0 ADCDC2IE ADCDC1IE ADCFIFOIE (5) 25/9 31:16 31:16 ADCD4IE 00D0 IEC1 26/10 NMIKEY 15:0 ADC1WIF 00C0 IEC0 27/11 All Resets 30/14 31:16 15:0 0080 IFS4 Note 31/15 15:0 ADCDC2IF ADCDC1IF ADCFIFOIF 0060 IFS2(5) Legend: Bits 31:16 ADCD4IF 0050 IFS1 00E0 IEC2 INTERRUPT REGISTER MAP Bit Range Register Name(1) Virtual Address (BF81_#) TABLE 7-3: IC9IE ADCURDYIF ADCARDYIF ADCEOSIF 0000 ADCDF6IE ADCDF5IE ADCDF4IE ADCDF3IE ADCDF2IE ADCDF1IE ADCDC6IE ADCDC5IE IC9EIE T9IE OC8IE IC8IE IC8EIE T8IE OC7IE IC7IE ADCDC4IE ADCDC3IE 0000 IC7EIE T7IE 0000 31:16 ADCD36IE ADCD35IE ADCD34IE ADCD33IE ADCD32IE ADCD31IE ADCD30IE ADCD29IE ADCD28IE ADCD27IE ADCD26IE ADCD25IE ADCD24IE ADCD23IE ADCD22IE ADCD21IE 0000 15:0 ADCD20IE ADCD19IE ADCD18IE ADCD17IE ADCD16IE ADCD15IE ADCD14IE ADCD13IE ADCD12IE ADCD11IE ADCD10IE ADCD9IE ADCD7IE ADCD6IE ADCD8IE ADCD5IE 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 138 7.3 0100 IEC4 0110 IEC5 0120 IEC6 0140 IPC0 0150 IPC1 0160 IPC2 0170 IPC3 0180 IPC4 0190 IPC5 01A0 IPC6 01B0 IPC7 01C0 IPC8 01D0 IPC9 01E0 IPC10 DS60001320H-page 139 Legend: Note Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 CNKIE CNJIE CNHIE CNGIE CNFIE CNEIE CNDIE CNCIE 15:0 SPI1TXIE SPI1RXIE SPI1EIE — CRPTIE(7) SBIE CFDCIE CPCIE 31:16 U3TXIE 23/7 22/6 21/5 20/4 19/3 CNBIE CNAIE I2C1MIE I2C1SIE I2C1BIE U3RXIE U3EIE SPI3TXIE SPI3RXIE SPI3EIE ETHIE CAN2IE(3) SPI2EIE DMA7IE DMA6IE DMA5IE DMA4IE DMA3IE DMA2IE DMA1IE DMA0IE USBDMAIE 31:16 — U6TXIE U6RXIE U6EIE I2C5MIE I2C5SIE I2C5BIE 15:0 I2C4MIE I2C4SIE I2C4BIE U4TXIE U4RXIE U4EIE SQI1IE PREIE FCEIE 31:16 — — — — — — — — — — — ADC4EIE ADC3EIF ADC2EIE 15:0 ADC1WIE U1TXIE ADCD44IE ADCD43IE ADCD42IE ADCD41IE ADCD40IE 15:0 SPI2RXIE SPI6TXIE(2) SPI6RXIE(2) SPI6EIE(2) 18/2 CAN1IE(3) I2C2MIE(2) I2C2SIE(2) I2C2BIE(2) ADCD39IE 17/1 16/0 U1RXIE U1EIE 0000 ADCD38IE ADCD37IE 0000 U2TXIE U2RXIE U2EIE USBIE CMP2IE CMP1IE PMPEIE U5TXIE U5RXIE U5EIE RTCCIE SPI4TXIE SPI4RXIE SPI4EIE I2C3MIE I2C3SIE — ADC7WIE — — ADC4WIE ADC3WIE ADCGRPIE — All Resets Bit Range Register Name(1) Virtual Address (BF81_#) 00F0 IEC3(6) INTERRUPT REGISTER MAP (CONTINUED) SPI2TXIE 0000 PMPIE 0000 SPI5TXIE(2) SPI5RXIE(2) SPI5EIE(2) 0000 I2C3BIE 0000 ADC2WIE 0000 ADC0WIE ADC7EIE ADC1EIE ADC0EIE — 31:16 — — — INT0IP INT0IS — — — CS1IP ADCURDYIE ADCARDYIE ADCEOSIE 0000 CS1IS 0000 15:0 — — — CS0IP CS0IS — — — CTIP CTIS 0000 31:16 — — — OC1IP OC1IS — — — IC1IP IC1IS 0000 15:0 — — — IC1EIP IC1EIS — — — T1IP T1IS 0000 31:16 — — — IC2IP IC2IS — — — IC2EIP IC2EIS 0000 15:0 — — — T2IP T2IS — — — INT1IP INT1IS 0000 31:16 — — — IC3EIP IC3EIS — — — T3IP T3IS 0000 15:0 — — — INT2IP INT2IS — — — OC2IP OC2IS 0000 31:16 — — — T4IP T4IS — — — INT3IP INT3IS 0000 15:0 — — — OC3IP OC3IS — — — IC3IP IC3IS 0000 31:16 — — — INT4IP INT4IS — — — OC4IP OC4IS 0000 15:0 — — — IC4IP IC4IS — — — IC4EIP IC4EIS 0000 31:16 — — — OC5IP OC5IS — — — IC5IP IC5IS 0000 15:0 — — — IC5EIP IC5EIS — — — T5IP T5IS 0000 31:16 — — — OC6IP OC6IS — — — IC6IP IC6IS 0000 15:0 — — — IC6EIP IC6EIS — — — T6IP T6IS 0000 31:16 — — — OC7IP OC7IS — — — IC7IP IC7IS 0000 15:0 — — — IC7EIP IC7EIS — — — T7IP T7IS 0000 31:16 — — — OC8IP OC8IS — — — IC8IP IC8IS 0000 15:0 — — — IC8EIP IC8EIS — — — T8IP T8IS 0000 31:16 — — — OC9IP OC9IS — — — IC9IP IC9IS 0000 15:0 — — — IC9EIP IC9EIS — — — T9IP T9IS 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-3: 0200 IPC12 0210 IPC13 0220 IPC14 0230 IPC15 0240 IPC16 0250 IPC17 0260 IPC18 0270 IPC19 0280 IPC20 0290 IPC21 02A0 IPC22  2015-2021 Microchip Technology Inc. 02B0 IPC23 02C0 IPC24 02D0 IPC25 Legend: Note Bits 31/15 30/14 29/13 28/12 27/11 31:16 — — — ADCDC2IP 15:0 — — — ADCFIFOIP 31:16 — — — ADCDC6IP 15:0 — — — 31:16 — — 15:0 — 31:16 26/10 25/9 24/8 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Virtual Address (BF81_#) 01F0 IPC11 INTERRUPT REGISTER MAP (CONTINUED) 23/7 22/6 21/5 ADCDC2IS — — — ADCDC1IP ADCDC1IS 0000 ADCFIFOIS — — — ADCIP ADCIS 0000 ADCDC6IS — — — ADCDC5IP ADCDC5IS 0000 ADCDC4IP ADCDC4IS — — — ADCDC3IP ADCDC3IS 0000 — ADCDF4IP ADCDF4IS — — — ADCDF3IP ADCDF3IS 0000 — — ADCDF2IP ADCDF2IS — — — ADCDF1IP ADCDF1IS 0000 — — — ADCD0IP ADCD0IS — — — ADCDFLTIP ADCDFLTIS 0000 15:0 — — — ADCDF6IP ADCDF6IS — — — ADCDF5IP ADCDF5IS 0000 31:16 — — — ADCD4IP ADCD4IS — — — ADCD3IP ADCD3IS 0000 15:0 — — — ADCD2IP ADCD2IS — — — ADCD1IP ADCD1IS 0000 31:16 — — — ADCD8IP ADCD8IS — — — ADCD7IP ADCD7IS 0000 15:0 — — — ADCD6IP ADCD6IS — — — ADCD5IP ADCD5IS 0000 31:16 — — — ADCD12IP ADCD12IS — — — ADCD11IP ADCD11IS 0000 15:0 — — — ADCD10IP ADCD10IS — — — ADCD9IP ADCD9IS 0000 31:16 — — — ADCD16IP ADCD16IS — — — ADCD15IP ADCD15IS 0000 15:0 — — — ADCD14IP ADCD14IS — — — ADCD13IP ADCD13IS 0000 31:16 — — — ADCD20IP(2) ADCD20IS(2) — — — ADCD19IP(2) ADCD19IS(2) 0000 15:0 — — — ADCD18IP ADCD18IS — — — ADCD17IP ADCD17IS 0000 31:16 — — — ADCD24IP(2) ADCD24IS(2) — — — ADCD23IP(2) ADCD23IS(2) 0000 15:0 — — — ADCD22IP(2) ADCD22IS(2) — — — ADCD21IP(2) ADCD21IS(2) 0000 31:16 — — — ADCD28IP(2) ADCD28IS(2) — — — ADCD27IP(2) ADCD27IS(2) 0000 15:0 — — — ADCD26IP(2) ADCD26IS(2) — — — ADCD25IP(2) ADCD25IS(2) 0000 31:16 — — — ADCD32IP(2) ADCD32IS(2) — — — ADCD31IP(2) ADCD31IS(2) 0000 15:0 — — — ADCD30IP(2) ADCD30IS(2) — — — ADCD29IP(2) ADCD29IS(2) 0000 31:16 — — — ADCD36IP(2,4) ADCD36IS(2,4) — — — ADCD35IP(2,4) ADCD35IS(2,4) 0000 15:0 — — — ADCD34IP(2) ADCD34IS(2) — — — ADCD33IP(2) ADCD33IS(2) 0000 31:16 — — — ADCD40IP(2,4) ADCD40IS(2,4) — — — ADCD39IP(2,4) ADCD39IS(2,4) 0000 15:0 — — — ADCD38IP(2,4) ADCD38IS(2,4) — — — ADCD37IP(2,4) ADCD37IS(2,4) 0000 31:16 — — — ADCD44IP ADCD44IS — — — ADCD43IP ADCD43IS 0000 15:0 — — — ADCD42IP(2,4) ADCD42IS(2,4) — — — ADCD41IP(2,4) ADCD41IS(2,4) 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 140 TABLE 7-3: 02F0 IPC27 0300 IPC28 0310 IPC29 0320 IPC30 0330 IPC31 0340 IPC32 0350 IPC33 0360 IPC34 0370 IPC35 0380 IPC36 0390 IPC37 03A0 IPC38 03B0 IPC39 03C0 IPC40 DS60001320H-page 141 Legend: Note Bits 31/15 30/14 29/13 28/12 27/11 31:16 — — — CRPTIP(7) 15:0 — — — CFDCIP 31:16 — — — 15:0 — — 31:16 — 15:0 26/10 25/9 24/8 20/4 23/7 22/6 21/5 CRPTIS(7) — — — SBIP SBIS 0000 CFDCIS — — — CPCIP CPCIS 0000 SPI1TXIP SPI1TXIS — — — SPI1RXIP SPI1RXIS 0000 — SPI1EIP SPI1EIS — — — — 0000 — — I2C1BIP I2C1BIS — — — U1TXIP U1TXIS 0000 — — — U1RXIP U1RXIS — — — U1EIP U1EIS 0000 31:16 — — — CNBIP CNBIS — — — CNAIP(2) CNAIS(2) 0000 15:0 — — — I2C1MIP I2C1MIS — — — I2C1SIP I2C1SIS 0000 31:16 — — — CNFIP CNFIS — — — CNEIP CNEIS 0000 15:0 — — — CNDIP CNDIS — — — CNCIP CNCIS 0000 31:16 — — — CNKIP(2,4,8) CNKIS(2,4,8) — — — CNJIP(2,4) CNJIS(2,4) 0000 15:0 — — — CNHIP(2,4) CNHIS(2,4) — — — CNGIP CNGIS 0000 31:16 — — — CMP2IP CMP2IS — — — CMP1IP CMP1IS 0000 15:0 — — — PMPEIP PMPEIS — — — PMPIP PMPIS 0000 31:16 — — — DMA1IP DMA1IS — — — DMA0IP DMA0IS 0000 15:0 — — — USBDMAIP USBDMAIS — — — USBIP USBIS 0000 31:16 — — — DMA5IP DMA5IS — — — DMA4IP DMA4IS 0000 15:0 — — — DMA3IP DMA3IS — — — DMA2IP DMA2IS 0000 31:16 — — — SPI2RXIP SPI2RXIS — — — SPI2EIP SPI2EIS 0000 15:0 — — — DMA7IP DMA7IS — — — DMA6IP DMA6IS 0000 31:16 — — — U2TXIP U2TXIS — — — U2RXIP U2RXIS 0000 15:0 — — — U2EIP U2EIS — — — SPI2TXIP SPI2TXIS 0000 31:16 — — — CAN1IP(3) CAN1IS(3) — — — I2C2MIP(2) I2C2MIS(2) 0000 15:0 — — — I2C2SIP(2) I2C2SIS(2) — — — I2C2BIP(2) I2C2BIS(2) 0000 31:16 — — — SPI3RXIP SPI3RXIS — — — SPI3EIP SPI3EIS 0000 15:0 — — — ETHIP ETHIS — — — CAN2IP(3) CAN2IS(3) 0000 31:16 — — — U3TXIP U3TXIS — — — U3RXIP U3RXIS 0000 15:0 — — — U3EIP U3EIS — — — SPI3TXIP SPI3TXIS 0000 31:16 — — — SPI4EIP SPI4EIS — — — I2C3MIP I2C3MIS 0000 15:0 — — — I2C3SIP I2C3SIS — — — I2C3BIP I2C3BIS 0000 — 19/3 — 18/2 — 17/1 16/0 All Resets Bit Range Register Name(1) Virtual Address (BF81_#) 02E0 IPC26 INTERRUPT REGISTER MAP (CONTINUED) — x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-3: 03E0 IPC42 03F0 IPC43 0400 IPC44 0410 IPC45 0420 IPC46 0430 IPC47 0440 IPC48 0450 IPC49 0460 IPC50 0470 IPC51 0480 IPC52  2015-2021 Microchip Technology Inc. 0490 IPC53 0540 OFF000 0544 OFF001 Legend: Note Bits 31/15 30/14 29/13 28/12 23/7 22/6 21/5 31:16 — — — FCEIP 15:0 — — — SPI4TXIP FCEIS — — — RTCCIP RTCCIS 0000 SPI4TXIS — — — SPI4RXIP SPI4RXIS 31:16 — — — U4RXIP 0000 U4RXIS — — — U4EIP U4EIS 15:0 — — — 0000 SQI1IP SQI1IS — — — PREIP PREIS 31:16 — — 0000 — I2C4MIP I2C4MIS — — — I2C4SIP I2C4SIS 15:0 — 0000 — — I2C4BIP I2C4BIS — — — U4TXIP U4TXIS 31:16 0000 — — — U5EIP U5EIS — — — SPI5TXIP(2) SPI5TXIS(2) 0000 15:0 — — — SPI5RXIP(2) SPI5RXIS(2) — — — SPI5EIP(2) SPI5EIS(2) 0000 31:16 — — — I2C5SIP I2C5SIS — — — I2C5BIP I2C5BIS 0000 15:0 — — — U5TXIP U5TXIS — — — U5RXIP U5RXIS 0000 31:16 — — — SPI6TXIP(2) SPI6TXIS(2) — — — SPI6RXIP(2) SPI6RXIS(2) 0000 15:0 — — — SPI6EIP(2) SPI6EIS(2) — — — I2C5MIP I2C5MIS 0000 31:16 — — — — — — U6TXIP U6TXIS 0000 15:0 — — — U6RXIS — — — U6EIP U6EIS 0000 31:16 — — — — — — — ADCURDYIP ADCURDYIS 0000 15:0 — — — ADCARDYIP ADCARDYIS — — — ADCEOSIP ADCEOSIS 0000 31:16 — — — ADC1EIP ADC1EIS ADC0EIP ADC0EIS 0000 15:0 — — — — — — — — ADCGRPIP ADCGRPIS 0000 31:16 — — — — — — — — ADC4EIP ADC4EIS 0000 15:0 — — — ADC3EIP ADC3EIS ADC2EIP ADC2EIS 0000 31:16 — — — ADC1WIP ADC1WIS ADC0WIP ADC0WIS 0000 15:0 — — — ADC7EIP ADC7EIS — — 0000 31:16 — — — 15:0 — — — 31:16 — — — 15:0 — — — 31:16 — — — — 27/11 — 26/10 — U6RXIP — — — — — — ADC3WIP — — — ADC7WIP — — — 25/9 — 15:0 — — — 20/4 — 19/3 — 18/2 — — — — — — 16/0 ADC4WIP ADC4WIS 0000 ADC3WIS ADC2WIP ADC2WIS 0000 — — — — — — — 0000 ADC7WIS — — — — — 0000 — — — VOFF — — — — — VOFF — 17/1 — 15:0 31:16 24/8 All Resets Bit Range Register Name(1) Virtual Address (BF81_#) 03D0 IPC41 INTERRUPT REGISTER MAP (CONTINUED) — — VOFF — — — — — — — VOFF — 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 142 TABLE 7-3: 054C OFF003 0550 OFF004 0554 OFF005 0558 OFF006 055C OFF007 0560 OFF008 0564 OFF009 0568 OFF010 056C OFF011 0570 OFF012 0574 OFF013 0578 OFF014 057C OFF015 0580 OFF016 DS60001320H-page 143 Legend: Note 31:16 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets Bit Range Register Name(1) Virtual Address (BF81_#) 0548 OFF002 INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-3: 0588 OFF018 058C OFF019 0590 OFF020 0594 OFF021 0598 OFF022 059C OFF023 05A0 OFF024 05A4 OFF025 05A8 OFF026 05AC OFF027 05B0 OFF028  2015-2021 Microchip Technology Inc. 05B4 OFF029 05B8 OFF030 05BC OFF031 Legend: Note 31:16 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets Bit Range Register Name(1) Virtual Address (BF81_#) 0584 OFF017 INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 144 TABLE 7-3: 05C4 OFF033 05C8 OFF034 05CC OFF035 05D0 OFF036 05D4 OFF037 05D8 OFF038 05DC OFF039 05E0 OFF040 05E4 OFF041 05E8 OFF042 05EC OFF043 05F0 OFF044 05F4 OFF045 05F8 OFF046 DS60001320H-page 145 Legend: Note 31:16 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets Bit Range Register Name(1) Virtual Address (BF81_#) 05C0 OFF032 INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-3: 0600 OFF048 0604 OFF049 0608 OFF050 060C OFF051 0610 OFF052 0614 OFF053 0618 OFF054 061C OFF055 0620 OFF056 0624 OFF057 0628 OFF058  2015-2021 Microchip Technology Inc. 062C OFF059 0630 OFF060 0634 OFF061 Legend: Note 31:16 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets Bit Range Register Name(1) Virtual Address (BF81_#) 05FC OFF047 INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 146 TABLE 7-3: 063C OFF063 0640 OFF064 0644 OFF065 0648 OFF066 064C OFF067 0650 OFF068 0654 OFF069 0658 OFF070 065C OFF071 0660 OFF072 0664 OFF073 0668 OFF074 066C OFF075 0670 OFF076 DS60001320H-page 147 Legend: Note 31:16 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets Bit Range Register Name(1) Virtual Address (BF81_#) 0638 OFF062 INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-3: (2) 0678 OFF078 067C 0680 OFF080(2) (2) 0684 OFF081 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 31:16 — — — — — — — 068C OFF083(2) (2) 0690 OFF084 31:16 — — — — — — — — — — — — 0694 OFF085(2) (2) 0698 OFF086 — — — — — — 069C OFF087 31:16 06A0 OFF088(2)  2015-2021 Microchip Technology Inc. (2) — — — — — — 06A4 OFF089 06A8 OFF090(2) — — — — — — 06AC OFF091(2) 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 (2) 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets 31/15 15:0 0688 OFF082(2) Note 31:16 Bits 15:0 OFF079(2) Legend: Bit Range Register Name(1) Virtual Address (BF81_#) 0674 OFF077(2) INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 148 TABLE 7-3: 06B4 OFF093(2) 06B8 OFF094(2,4) (2,4) 06BC OFF095 OFF097(2,4) (2,4) 06C8 OFF098 OFF100(2,4) 06D4 OFF101(2,4) 06D8 OFF102 06DC OFF103 06E0 OFF104 06E4 OFF105 06E8 OFF106 DS60001320H-page 149 Legend: Note 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — 31:16 — — — — — — 31:16 — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets 31/15 15:0 06CC OFF099(2,4) 06D0 31:16 Bits 15:0 06C0 OFF096(2,4) 06C4 Bit Range Register Name(1) Virtual Address (BF81_#) 06B0 OFF092(2) INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-3: 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — — — — — — — — 0700 OFF112 — — — — — — 0704 OFF113 0708 OFF114 — — — — — — 070C OFF115 0710 OFF116 — — — — — — 0714 OFF117 071C OFF119  2015-2021 Microchip Technology Inc. 0720 OFF120 0724 OFF121 0728 OFF122 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 (2) — — — 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets 31/15 15:0 31:16 06FC OFF111 Note Bits 15:0 06F8 OFF110 Legend: 31:16 31:16 06F4 OFF109 0718 OFF118 Bit Range Register Name(1) Virtual Address (BF81_#) 06EC OFF107(7) INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 150 TABLE 7-3: 31:16 (2,4) 0738 OFF126 0750 OFF132 0754 OFF133 0758 OFF134 075C OFF135 0760 OFF136 0764 OFF137 DS60001320H-page 151 Legend: Note 29/13 28/12 27/11 26/10 25/9 — — — — — — — 31:16 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets 30/14 15:0 073C OFF127(2,4,8) 074C OFF131 31/15 15:0 0734 OFF125(2,4) 0748 OFF130 Bits 15:0 0730 OFF124 0744 OFF129 Bit Range Virtual Address (BF81_#) Register Name(1) 31:16 072C OFF123 0740 OFF128 INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-3: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 31:16 0770 OFF140 — — — — — — — 0774 OFF141 — — — — — — 0778 OFF142 077C OFF143 — — — — — — 0780 OFF144 0784 OFF145 — — — — — — 0788 OFF146 078C OFF147 — — — — — — 0790 OFF148 31:16 0794 OFF149(2)  2015-2021 Microchip Technology Inc. (2) — — — — — — 0798 OFF150 079C OFF151(3) — — — — — — 07A0 OFF152(3) 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 (2) — VOFF 15:0 31:16 — — — 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets Bits 15:0 076C OFF139 Note Bit Range Virtual Address (BF81_#) Register Name(1) 31:16 0768 OFF138 Legend: INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 152 TABLE 7-3: 07A8 OFF154 07AC OFF155 07B0 OFF156 07B4 OFF157 07B8 OFF158 07BC OFF159 07C0 OFF160 07C4 OFF161 07C8 OFF162 07CC OFF163 07D0 OFF164 07D4 OFF165 07D8 OFF166 07DC OFF167 DS60001320H-page 153 Legend: Note 31:16 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets Bit Range Register Name(1) Virtual Address (BF81_#) 07A4 OFF153 INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-3: 31:16 31:16 31:16 31:16 31:16 26/10 25/9 — — — — — — — 31:16 07FC OFF175 — — — — — — — 0800 OFF176(2) (2) — — — — — — 0804 OFF177 31:16 — — — — — — — — — — — —  2015-2021 Microchip Technology Inc. 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — — — 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 (2) 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets 27/11 15:0 07F8 OFF174 Note 28/12 15:0 07F4 OFF173 Legend: 29/13 15:0 07F0 OFF172 0818 OFF182 30/14 15:0 07EC OFF171 0814 OFF181 31/15 15:0 07E8 OFF170 0810 OFF180 Bits 15:0 07E4 OFF169 080C OFF179 Bit Range Virtual Address (BF81_#) Register Name(1) 31:16 07E0 OFF168 0808 OFF178 INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 154 TABLE 7-3: 31:16 (2) 0828 OFF186 0844 OFF193 0848 OFF194 0850 OFF196 0858 OFF198 085C OFF199 0860 OFF200 DS60001320H-page 155 Legend: Note 29/13 28/12 27/11 26/10 25/9 — — — — — — — 31:16 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 — VOFF 15:0 31:16 — — — 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets 30/14 15:0 082C OFF187(2) 0840 OFF192 31/15 15:0 0824 OFF185(2) 0838 OFF190 Bits 15:0 0820 OFF184 0834 OFF189 Bit Range Virtual Address (BF81_#) Register Name(1) 31:16 081C OFF183 0830 OFF188 INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1: 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 7-3: 0868 OFF202 0874 OFF205 0878 OFF206 087C OFF207 0880 OFF208 0884 OFF209 0888 OFF210 0894 OFF213 Legend: Note 31:16 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — VOFF VOFF VOFF VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — — — — — — — VOFF — VOFF — VOFF — 16/0 — VOFF — 17/1 — VOFF 15:0 31:16 18/2 VOFF 15:0 31:16 19/3 — — 15:0 31:16 20/4 VOFF 15:0 31:16 21/5 — — 15:0 31:16 22/6 VOFF 15:0 31:16 23/7 VOFF 15:0 31:16 24/8 VOFF — — — — — — — VOFF — All Resets Bit Range Register Name(1) Virtual Address (BF81_#) 0864 OFF201 INTERRUPT REGISTER MAP (CONTINUED) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 1:  2015-2021 Microchip Technology Inc. 2: 3: 4: 5: 6: 7: 8: All registers in this table with the exception of the OFFx registers, have corresponding CLR, SET, and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. This bit or register is not available on 64-pin devices. This bit or register is not available on devices without a CAN module. This bit or register is not available on 100-pin devices. Bits 31 and 30 are not available on 64-pin and 100-pin devices; bits 29 through 14 are not available on 64-pin devices. Bits 31, 30, 29, and bits 5 through 0 are not available on 64-pin and 100-pin devices; bit 31 is not available on 124-pin devices; bit 22 is not available on 64-pin devices. This bit or register is not available on devices without a Crypto module. This bit or register is not available on 124-pin devices. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 156 TABLE 7-3: PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-1: Bit Range 31:24 23:16 15:8 7:0 INTCON: INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 U-0 NMIKEY U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 — — — MVEC — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set TPC U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 NMIKEY: Non-Maskable Interrupt Key bits When the correct key (0x4E) is written, a software NMI will be generated. The status is indicated by the GNMI bit (RNMICON). bit 23-13 Unimplemented: Read as ‘0’ bit 12 MVEC: Multi Vector Configuration bit 1 = Interrupt controller configured for multi vectored mode 0 = Interrupt controller configured for single vectored mode bit 11 Unimplemented: Read as ‘0’ bit 10-8 TPC: Interrupt Proximity Timer Control bits 111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer 110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer 101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer 100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer 011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer 010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer 001 = Interrupts of group priority 1 start the Interrupt Proximity timer 000 = Disables Interrupt Proximity timer bit 7-5 Unimplemented: Read as ‘0’ bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 2 INT2EP: External Interrupt 2 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge  2015-2021 Microchip Technology Inc. DS60001320H-page 157 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-2: Bit Range PRISS: PRIORITY SHADOW SELECT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 31:24 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 PRI7SS(1) R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRI1SS(1) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRI4SS(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRI2SS(1) PRI3SS 7:0 Bit 25/17/9/1 PRI6SS(1) PRI5SS(1) 15:8 Bit 26/18/10/2 R/W-0 U-0 U-0 U-0 R/W-0 — — — SS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 PRI7SS: Interrupt with Priority Level 7 Shadow Set bits(1) 1xxx = Reserved (by default, an interrupt with a priority level of 7 uses Shadow Set 0) 0111 = Interrupt with a priority level of 7 uses Shadow Set 7 0110 = Interrupt with a priority level of 7 uses Shadow Set 6 • • • 0001 = Interrupt with a priority level of 7 uses Shadow Set 1 0000 = Interrupt with a priority level of 7 uses Shadow Set 0 bit 27-24 PRI6SS: Interrupt with Priority Level 6 Shadow Set bits(1) 1xxx = Reserved (by default, an interrupt with a priority level of 6 uses Shadow Set 0) 0111 = Interrupt with a priority level of 6 uses Shadow Set 7 0110 = Interrupt with a priority level of 6 uses Shadow Set 6 • • • 0001 = Interrupt with a priority level of 6 uses Shadow Set 1 0000 = Interrupt with a priority level of 6 uses Shadow Set 0 bit 23-20 PRI5SS: Interrupt with Priority Level 5 Shadow Set bits(1) 1xxx = Reserved (by default, an interrupt with a priority level of 5 uses Shadow Set 0) 0111 = Interrupt with a priority level of 5 uses Shadow Set 7 0110 = Interrupt with a priority level of 5 uses Shadow Set 6 • • • 0001 = Interrupt with a priority level of 5 uses Shadow Set 1 0000 = Interrupt with a priority level of 5 uses Shadow Set 0 bit 19-16 PRI4SS: Interrupt with Priority Level 4 Shadow Set bits(1) 1xxx = Reserved (by default, an interrupt with a priority level of 4 uses Shadow Set 0) 0111 = Interrupt with a priority level of 4 uses Shadow Set 7 0110 = Interrupt with a priority level of 4 uses Shadow Set 6 • • • 0001 = Interrupt with a priority level of 4 uses Shadow Set 1 0000 = Interrupt with a priority level of 4 uses Shadow Set 0 Note 1: These bits are ignored if the MVEC bit (INTCON) = 0. DS60001320H-page 158  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-2: PRISS: PRIORITY SHADOW SELECT REGISTER (CONTINUED) bit 15-12 PRI3SS: Interrupt with Priority Level 3 Shadow Set bits(1) 1xxx = Reserved (by default, an interrupt with a priority level of 3 uses Shadow Set 0) 0111 = Interrupt with a priority level of 3 uses Shadow Set 7 0110 = Interrupt with a priority level of 3 uses Shadow Set 6 • • • bit 11-8 0001 = Interrupt with a priority level of 3 uses Shadow Set 1 0000 = Interrupt with a priority level of 3 uses Shadow Set 0 PRI2SS: Interrupt with Priority Level 2 Shadow Set bits(1) 1xxx = Reserved (by default, an interrupt with a priority level of 2 uses Shadow Set 0) 0111 = Interrupt with a priority level of 2 uses Shadow Set 7 0110 = Interrupt with a priority level of 2 uses Shadow Set 6 • • • bit 7-4 0001 = Interrupt with a priority level of 2 uses Shadow Set 1 0000 = Interrupt with a priority level of 2 uses Shadow Set 0 PRI1SS: Interrupt with Priority Level 1 Shadow Set bits(1) 1xxx = Reserved (by default, an interrupt with a priority level of 1 uses Shadow Set 0) 0111 = Interrupt with a priority level of 1 uses Shadow Set 7 0110 = Interrupt with a priority level of 1 uses Shadow Set 6 • • • bit 3-1 bit 0 0001 = Interrupt with a priority level of 1 uses Shadow Set 1 0000 = Interrupt with a priority level of 1 uses Shadow Set 0 Unimplemented: Read as ‘0’ SS0: Single Vector Shadow Register Set bit 1 = Single vector is presented with a shadow set 0 = Single vector is not presented with a shadow set Note 1: These bits are ignored if the MVEC bit (INTCON) = 0.  2015-2021 Microchip Technology Inc. DS60001320H-page 159 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-3: Bit Range 31:24 23:16 15:8 7:0 INTSTAT: INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — R-0 R-0 R-0 R-0 R-0 SRIPL(1) R-0 R-0 R-0 SIRQ Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-11 Unimplemented: Read as ‘0’ bit 10-8 SRIPL: Requested Priority Level bits for Single Vector Mode bits(1) 111-000 = The priority level of the latest interrupt presented to the CPU bit 7-0 SIRQ: Last Interrupt Request Serviced Status bits 11111111-00000000 = The last interrupt request number serviced by the CPU Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode. REGISTER 7-4: Bit Range 31:24 23:16 15:8 7:0 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPTMR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPTMR R/W-0 IPTMR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPTMR Legend: R = Readable bit -n = Value at POR bit 31-0 IPTMR: INTERRUPT PROXIMITY TIMER REGISTER Bit 31/23/15/7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IPTMR: Interrupt Proximity Timer Reload bits Used by the Interrupt Proximity Timer as a reload value when the Interrupt Proximity timer is triggered by an interrupt event. DS60001320H-page 160  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-5: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 IFSx: INTERRUPT FLAG STATUS REGISTER Bit 30/22/14/6 Note: 31:24 23:16 15:8 7:0 Note: Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS23 IFS22 IFS21 IFS20 IFS19 IFS18 IFS17 IFS16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS15 IFS14 IFS13 IFS12 IFS11 IFS10 IFS9 IFS8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IFS7 IFS6 IFS5 IFS4 IFS3 IFS2 IFS1 IFS0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IFS31-IFS0: Interrupt Flag Status bits 1 = Interrupt request has occurred 0 = No interrupt request has occurred This register represents a generic definition of the IFSx register. Refer to Table 7-2 for the exact bit definitions. Bit 31/23/15/7 IECx: INTERRUPT ENABLE CONTROL REGISTER Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC31 IEC30 IEC29 IEC28 IEC27 IEC26 IEC25 IEC24 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC23 IEC22 IEC21 IEC20 IEC19 IEC18 IEC17 IEC16 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC15 IEC14 IEC13 IEC12 IEC11 IEC10 IEC9 IEC8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IEC7 IEC6 IEC5 IEC4 IEC3 IEC2 IEC1 IEC0 Legend: R = Readable bit -n = Value at POR bit 31-0 Bit 26/18/10/2 R/W-0 REGISTER 7-6: Bit Range Bit Bit 28/20/12/4 27/19/11/3 IFS31 Legend: R = Readable bit -n = Value at POR bit 31-0 Bit 29/21/13/5 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IEC31-IEC0: Interrupt Enable bits 1 = Interrupt is enabled 0 = Interrupt is disabled This register represents a generic definition of the IECx register. Refer to Table 7-2 for the exact bit definitions.  2015-2021 Microchip Technology Inc. DS60001320H-page 161 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-7: Bit Range IPCx: INTERRUPT PRIORITY CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — 31:24 23:16 15:8 7:0 Legend: R = Readable bit -n = Value at POR Bit Bit 28/20/12/4 27/19/11/3 W = Writable bit ‘1’ = Bit is set R/W-0 R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 IP3 R/W-0 R/W-0 IS3 R/W-0 IP2 R/W-0 R/W-0 R/W-0 IP0 R/W-0 IS2 R/W-0 IP1 R/W-0 R/W-0 R/W-0 R/W-0 IS1 R/W-0 R/W-0 R/W-0 IS0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-26 IP3: Interrupt Priority bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 25-24 IS3: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 23-21 Unimplemented: Read as ‘0’ bit 20-18 IP2: Interrupt Priority bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 IS2: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 15-13 Unimplemented: Read as ‘0’ Note: This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit definitions. DS60001320H-page 162  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-7: IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED) bit 12-10 IP1: Interrupt Priority bits 111 = Interrupt priority is 7 • • • bit 9-8 bit 7-5 bit 4-2 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS1: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as ‘0’ IP0: Interrupt Priority bits 111 = Interrupt priority is 7 • • • bit 1-0 Note: 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS0: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 This register represents a generic definition of the IPCx register. Refer to Table 7-2 for the exact bit definitions.  2015-2021 Microchip Technology Inc. DS60001320H-page 163 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 7-8: Bit Range 31:24 23:16 15:8 7:0 OFFx: INTERRUPT VECTOR ADDRESS OFFSET REGISTER (x = 0-190) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 U-0 U-0 — — — — U-0 U-0 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — U-0 U-0 R/W-0 R/W-0 — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 VOFF R/W-0 R/W-0 R/W-0 U-0 VOFF R/W-0 Legend: R = Readable bit -n = Value at POR R/W-0 R/W-0 R/W-0 R/W-0 VOFF W = Writable bit ‘1’ = Bit is set — U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 17-1 VOFF: Interrupt Vector ‘x’ Address Offset bits bit 0 Unimplemented: Read as ‘0’ DS60001320H-page 164  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 8.0 Note: OSCILLATOR CONFIGURATION This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The PIC32MZ EF oscillator system has the following modules and features: • A total of five external and internal oscillator options as clock sources • On-Chip PLL with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources • On-Chip user-selectable divisor postscaler on select oscillator sources • Software-controllable switching between  various clock sources • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown with dedicated Back-up FRC (BFRC) • Dedicated On-Chip PLL for USB peripheral • Flexible reference clock output • Multiple clock branches for peripherals for better performance flexibility • Clock switch/slew control with output divider A block diagram of the oscillator system is shown in Figure 8-1. The clock distribution is provided in Table 8-1. Note:  2015-2021 Microchip Technology Inc. Devices that support 252 MHz operation should be configured for SYSCLK 60Mhz. Note: Writes to this register require an unlock sequence. Refer to Section 42. “Oscillators with Enhanced PLL” (DS60001250) in the “PIC32 Family Reference Manual” for details. DS60001320H-page 178  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 8-7: Bit Range 31:24 23:16 15:8 7:0 SLEWCON: OSCILLATOR SLEW CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R-0, HS, HC — — — — — UPEN DNEN BUSY Legend: SYSDIV(1) R/W-0 R/W-1 R/W-0 SLWDIV HC = Hardware Cleared HS = Hardware Set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-20 Unimplemented: Read as ‘0’ bit 19-16 SYSDIV: System Clock Divide Control bits(1) 1111 = SYSCLK is divided by 16 1110 = SYSCLK is divided by 15 • • • 0010 = SYSCLK is divided by 3 0001 = SYSCLK is divided by 2 0000 = SYSCLK is not divided bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 SLWDIV: Slew Divisor Steps Control bits These bits control the maximum division steps used when slewing during a frequency change. 111 = Steps are divide by 128, 64, 32, 16, 8, 4, 2, and then no divisor 110 = Steps are divide by 64, 32, 16, 8, 4, 2, and then no divisor 101 = Steps are divide by 32, 16, 8, 4, 2, and then no divisor 100 = Steps are divide by 16, 8, 4, 2, and then no divisor 011 = Steps are divide by 8, 4, 2, and then no divisor 010 = Steps are divide by 4, 2, and then no divisor 001 = Steps are divide by 2, and then no divisor 000 = No divisor is used during slewing bit 7-3 Unimplemented: Read as ‘0’ bit 2 UPEN: Upward Slew Enable bit 1 = Slewing enabled for switching to a higher frequency 0 = Slewing disabled for switching to a higher frequency bit 1 DNEN: Downward Slew Enable bit 1 = Slewing enabled for switching to a lower frequency 0 = Slewing disabled for switching to a lower frequency bit 0 BUSY: Clock Switching Slewing Active Status bit 1 = Clock frequency is being actively slewed to the new frequency 0 = Clock switch has reached its final value Note: Note 1: The steps apply in reverse order (i.e., 2, 4, 8, etc.) during a downward frequency change. The SYSDIV bit settings are ignored if both UPEN and DNEN = 0, and SYSCLK will be divided by 1.  2015-2021 Microchip Technology Inc. DS60001320H-page 179 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 8-8: Bit Range 31:24 23:16 15:8 7:0 CLKSTAT: OSCILLATOR CLOCK STATUS REGISTER Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit Bit 28/20/12/4 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R-0 R-0 U-0 R-0 R-0 — — LPRCRDY SOSCRDY — POSCRDY DIVSPLLRDY R-0 FRCRDY Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-6 Unimplemented: Read as ‘0’ bit 5 LPRCRDY: Low-Power RC (LPRC) Oscillator Ready Status bit 1 = LPRC is stable and ready 0 = LPRC is disabled or not operating bit 4 SOSCRDY: Secondary Oscillator (SOSC) Ready Status bit 1 = SOSC is stable and ready 0 = SOSC is disabled or not operating bit 3 Unimplemented: Read as ‘0’ bit 2 POSCRDY: Primary Oscillator (POSC) Ready Status bit 1 = POSC is stable and ready 0 = POSC is disabled or not operating bit 1 DIVSPLLRDY: Divided System PLL Ready Status bit 1 = Divided System PLL is ready 0 = Divided System PLL is not ready bit 0 FRCRDY: Fast RC (FRC) Oscillator Ready Status bit 1 = FRC is stable and ready 0 = FRC is disabled for not operating DS60001320H-page 180 x = Bit is unknown  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 9.0 PREFETCH MODULE Note: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 41. “Prefetch Module for Devices with L1 CPU Cache” (DS60001183) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The Prefetch module is a performance enhancing module that is included in the PIC32MZ EF family of devices. When running at high-clock rates, Wait states must be inserted into Program Flash Memory (PFM) read transactions to meet the access time of the PFM. Wait states can be hidden to the core by prefetching and storing instructions in a temporary holding area that the CPU can access quickly. Although the data path to the CPU is 32 bits wide, the data path to the PFM is 128 bits wide. This wide data path provides the same bandwidth to the CPU as a 32-bit path running at four times the frequency. FIGURE 9-1: The Prefetch module holds a subset of PFM in temporary holding spaces known as lines. Each line contains a tag and data field. Normally, the lines hold a copy of what is currently in memory to make instructions or data available to the CPU without Flash Wait states. The following are key features of the Prefetch module: • • • • • • • 4x16 byte fully-associative lines One line for CPU instructions One line for CPU data Two lines for peripheral data 16-byte parallel memory fetch Configurable predictive prefetch Error detection and correction A simplified block diagram of the Prefetch module is shown in Figure 9-1. PREFETCH MODULE BLOCK DIAGRAM SYSCLK CPU Prefetch Buffer Data CPU Tag Bus Control Line Control Program Flash Memory (PFM)  2015-2021 Microchip Technology Inc. DS60001320H-page 181 Prefetch Control Registers Virtual Address (BF8E_#) Register Name(1) TABLE 9-1: 0000 PRECON 0010 PREFETCH REGISTER MAP PRESTAT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — — — — — PFMSECEN — — — — 15:0 — — — — — — — — — — 31:16 — — — — PFMDED PFMSEC — — — — 15:0 — — — — — — — — 21/5 20/4 19/3 18/2 — — — — PREFEN — — — — PFMSECCNT 17/1 16/0 — — PFMWS — — All Resets Bit Range Bits 0000 0007 — 0000 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information.  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 182 9.1 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 9-1: Bit Range PRECON: PREFETCH MODULE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 31:24 23:16 15:8 7:0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 U-0 U-0 — — — — — PFMSECEN — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 — — PREFEN — R/W-1 (1) PFMWS Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-27 Unimplemented: Read as ‘0’ bit 26 PFMSECEN: Flash SEC Interrupt Enable bit 1 = Generate an interrupt when the PFMSEC bit (PRESTAT) is set 0 = Do not generate an interrupt when the PFMSEC bit is set bit 25-6 Unimplemented: Read as ‘0’ bit 5-4 PREFEN: Predictive Prefetch Enable bits 11 = Enable predictive prefetch for any address 10 = Enable predictive prefetch for CPU instructions and CPU data 01 = Enable predictive prefetch for CPU instructions only 00 = Disable predictive prefetch bit 3 Unimplemented: Read as ‘0’ bit 2-0 PFMWS: PFM Access Time Defined in Terms of SYSCLK Wait States bits(1) 111 = Seven Wait states • • • 010 = Two Wait states 001 = One Wait state 000 = Zero Wait states Note 1: For the Wait states to SYSCLK relationship, refer to Table 37-13 in Section37.0 “Electrical Characteristics”.  2015-2021 Microchip Technology Inc. DS60001320H-page 183 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 9-2: Bit Range 31:24 23:16 15:8 7:0 PRESTAT: PREFETCH MODULE STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — R/W-0, HS R/W-0, HS U-0 U-0 PFMDED PFMSEC — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS PFMSECCNT Legend: HS = Hardware Set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 Unimplemented: Read as ‘0’ bit 27 PFMDED: Flash Double-bit Error Detected (DED) Status bit This bit is set in hardware and can only be cleared (i.e., set to ‘0’) in software. 1 = A DED error has occurred 0 = A DED error has not occurred bit 26 PFMSEC: Flash Single-bit Error Corrected (SEC) Status bit 1 = A SEC error occurred when PFMSECCNT was equal to zero 0 = A SEC error has not occurred bit 25-8 Unimplemented: Read as ‘0’ bit 7-0 PFMSECCNT: Flash SEC Count bits 11111111 - 00000000 = SEC count DS60001320H-page 184  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 10.0 Note: DIRECT MEMORY ACCESS (DMA) CONTROLLER This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. “Direct Memory Access (DMA) Controller” (DS60001117) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The Direct Memory Access (DMA) Controller is a bus host module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the device such as SPI, UART, PMP, etc., or memory itself. The following are key features of the DMA Controller: • Eight identical channels, each featuring: - Auto-increment source and destination address registers - Source and destination pointers - Memory to memory and memory to peripheral transfers • Automatic word-size detection: - Transfer granularity, down to byte level - Bytes need not be word-aligned at source and destination • Fixed priority channel arbitration FIGURE 10-1: INT Controller Peripheral Bus • Flexible DMA channel operating modes: - Manual (software) or automatic (interrupt) DMA requests - One-Shot or Auto-Repeat Block Transfer modes - Channel-to-channel chaining • Flexible DMA requests: - A DMA request can be selected from any of the peripheral interrupt sources - Each channel can select any (appropriate) observable interrupt as its DMA request source - A DMA transfer abort can be selected from any of the peripheral interrupt sources - Up to 2-byte Pattern (data) match transfer termination • Multiple DMA channel status interrupts: - DMA channel block transfer complete - Source empty or half empty - Destination full or half full - DMA transfer aborted due to an external event - Invalid DMA address generated • DMA debug support features: - Most recent error address accessed by a DMA channel - Most recent DMA channel to transfer data • CRC Generation module: - CRC module can be assigned to any of the available channels - CRC module is highly configurable DMA BLOCK DIAGRAM System IRQ Address Decoder SE Channel 0 Control I0 Channel 1 Control I1 DMA SYSCLK L Y Bus Interface System Bus + Bus Arbitration I2 Global Control (DMACON) Channel n Control In SE L Channel Priority Arbitration  2015-2021 Microchip Technology Inc. DS60001320H-page 185 DMA Control Registers Virtual Address (BF81_#) Register Name(1) TABLE 10-1: 1000 DMACON 1010 DMASTAT DMA GLOBAL REGISTER MAP 1020 DMAADDR 31/15 30/14 29/13 31:16 — — — 15:0 ON — — 31:16 RDWR — — — 15:0 — — — — All Resets Bit Range Bits 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — — — — — — — 0000 — — — — — — — — — SUSPEND DMABUSY 31:16 DMACH 0000 0000 DMAADDR 15:0 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. DMA CRC REGISTER MAP 1030 DCRCCON 1040 DCRCDATA  2015-2021 Microchip Technology Inc. 1050 DCRCXOR 31/15 30/14 31:16 — — 15:0 — — 31:16 15:0 31:16 15:0 29/13 28/12 BYTO — 27/11 WBO 26/10 25/9 24/8 — — BITO PLEN 23/7 — CRCEN DCRCDATA DCRCXOR 22/6 21/5 20/4 19/3 18/2 — — — — — — — CRCAPP CRCTYP 17/1 16/0 — — CRCCH All Resets Bit Range Bits Register Name(1) Virtual Address (BF81_#) TABLE 10-2: 0000 0000 0000 0000 0000 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 186 10.1 Virtual Address (BF81_#) 1070 DCH0ECON DCH0INT 1090 DCH0SSA 10A0 DCH0DSA 10B0 DCH0SSIZ 10C0 DCH0DSIZ 10D0 DCH0SPTR 10E0 DCH0DPTR 10F0 DCH0CSIZ 1100 DCH0CPTR 1110 DCH0DAT 1120 DCH1CON 1130 DCH1ECON DS60001320H-page 187 1140 DCH1INT 1150 DCH1SSA 1160 DCH1DSA 31/15 30/14 29/13 15:0 CHBUSY — CHPIGNEN — 31:16 — — — 31:16 28/12 27/11 26/10 25/9 24/8 23/7 — — CHPATLEN — — CHCHNS CHEN CHAED — — — — CHPIGN — 15:0 CHSIRQ 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — CHCHN CHAEN — — — — CHEDET — 0000 CHPRI 0000 FF00 CHAIRQ CFORCE CABORT All Resets Bit Range Register Name(1) Bits 1060 DCH0CON 1080 DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP 00FF PATEN SIRQEN AIRQEN — — — 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 31:16 — — — — — — — — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — — — — — — — — 0000 CHEN CHAED CHCHN CHAEN — CHEDET CHPRI 0000 FF00 — — — — — — — — — — — — — — — — — — — — — — — 0000 0000 0000 0000 CHCPTR 15:0 — — 0000 CHPDAT 31:16 CHPIGN 15:0 CHBUSY — CHPIGNEN — CHPATLEN — — CHCHNS 31:16 — — — — — — — — 15:0 CHSIRQ 0000 0000 CHCSIZ 15:0 31:16 — CHDPTR 15:0 31:16 0000 — CHSPTR 15:0 31:16 — CHDSIZ 15:0 31:16 — CHSSIZ 15:0 31:16 0000 0000 CHDSA 15:0 31:16 0000 CHSSA 15:0 0000 0000 CHAIRQ CFORCE CABORT 00FF PATEN SIRQEN AIRQEN — — — 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 15:0 31:16 15:0 CHSSA CHDSA 0000 0000 0000 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 10-3: Virtual Address (BF81_#) 1180 DCH1DSIZ 1190 DCH1SPTR 11A0 DCH1DPTR 11B0 DCH1CSIZ 11C0 DCH1CPTR 11D0 DCH1DAT 11E0 DCH2CON 11F0 DCH2ECON DCH2INT 1210 DCH2SSA 1220 DCH2DSA  2015-2021 Microchip Technology Inc. 1230 DCH2SSIZ 1240 DCH2DSIZ 1250 DCH2SPTR 1260 DCH2DPTR 1270 DCH2CSIZ 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — — — — — — — — 0000 CHEN CHAED CHCHN CHAEN — CHEDET CHPRI 0000 FF00 — — — — — — — — — — — — — — — — — — — — — — — — 0000 0000 0000 0000 CHCPTR 15:0 — — 0000 CHPDAT 31:16 CHPIGN 15:0 CHBUSY — CHPIGNEN — CHPATLEN — — CHCHNS 31:16 — — — — — — — — 15:0 CHSIRQ 0000 0000 CHCSIZ 15:0 31:16 21/5 CHDPTR 15:0 31:16 22/6 CHSPTR 15:0 31:16 23/7 CHDSIZ 15:0 31:16 24/8 CHSSIZ — All Resets Bit Range Register Name(1) Bits 1170 DCH1SSIZ 1200 DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED) 0000 0000 CHAIRQ CFORCE CABORT 00FF PATEN SIRQEN AIRQEN — — — 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 31:16 — — — — — — — — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — 15:0 — 0000 — — — — — — — — — — — — — — — — 0000 — — — — — — — — — — — — — — — — 0000 — — — — — — — — — 0000 — — — — — — — 0000 0000 CHDPTR — — CHCSIZ 0000 0000 CHSPTR 15:0 31:16 — CHDSIZ 15:0 31:16 0000 CHSSIZ 15:0 31:16 0000 CHDSA 15:0 31:16 0000 CHSSA 15:0 0000 0000 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 188 TABLE 10-3: Virtual Address (BF81_#) 1290 DCH2DAT 12A0 DCH3CON 12B0 DCH3ECON DCH3INT 12D0 DCH3SSA 12E0 DCH3DSA 12F0 DCH3SSIZ 1300 DCH3DSIZ 1310 DCH3SPTR 1320 DCH3DPTR 1330 DCH3CSIZ 1340 DCH3CPTR 1350 DCH3DAT DS60001320H-page 189 1360 DCH4CON 1370 DCH4ECON 1380 DCH4INT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — — — — — — — — — 0000 CHEN CHAED CHCHN CHAEN — CHEDET CHPRI 0000 FF00 CHCPTR — — — — — — — 15:0 — — CHPIGN 15:0 CHBUSY — CHPIGNEN — CHPATLEN — — CHCHNS 31:16 — — — — — — — — 15:0 CHSIRQ 0000 0000 CHPDAT 31:16 All Resets Bit Range Register Name(1) Bits 1280 DCH2CPTR 12C0 DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED) 0000 0000 CHAIRQ CFORCE CABORT 00FF PATEN SIRQEN AIRQEN — — — 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 31:16 — — — — — — — — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — — — — — — — — 0000 CHEN CHAED CHCHN CHAEN — CHEDET CHPRI 0000 FF00 — — — — — — — — — — — — — — — — — — — — — — — 0000 0000 0000 0000 CHCPTR 15:0 — — 0000 CHPDAT 31:16 CHPIGN 15:0 CHBUSY — CHPIGNEN — CHPATLEN — — CHCHNS 31:16 — — — — — — — — 15:0 CHSIRQ 0000 0000 CHCSIZ 15:0 31:16 0000 — CHDPTR 15:0 31:16 — CHSPTR 15:0 31:16 — CHDSIZ 15:0 31:16 0000 CHSSIZ 15:0 31:16 0000 CHDSA 15:0 31:16 0000 CHSSA 15:0 0000 0000 CHAIRQ CFORCE CABORT 00FF PATEN SIRQEN AIRQEN — — — 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 10-3: Virtual Address (BF81_#) 13A0 DCH4DSA 13B0 DCH4SSIZ 13C0 DCH4DSIZ 13D0 DCH4SPTR 13E0 DCH4DPTR 13F0 DCH4CSIZ 1400 DCH4CPTR 1410 DCH4DAT 1420 DCH5CON 1430 DCH5ECON DCH5INT  2015-2021 Microchip Technology Inc. 1450 DCH5SSA 1460 DCH5DSA 1470 DCH5SSIZ 1480 DCH5DSIZ 1490 DCH5SPTR 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 31:16 — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — — — — — 17/1 16/0 0000 0000 0000 — — 0000 — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — — — — — — — — 0000 CHEN CHAED CHCHN CHAEN — CHEDET CHPRI 0000 FF00 — — — — — — — — — — — — — — — — — — — — — — — 0000 0000 0000 0000 CHCPTR 15:0 — — 0000 CHPDAT 31:16 CHPIGN 15:0 CHBUSY — CHPIGNEN — CHPATLEN — — CHCHNS 31:16 — — — — — — — — 15:0 CHSIRQ 0000 0000 CHCSIZ 15:0 31:16 18/2 CHDPTR 15:0 31:16 19/3 CHSPTR 15:0 31:16 20/4 CHDSIZ 15:0 31:16 21/5 CHSSIZ 15:0 31:16 22/6 CHDSA 15:0 31:16 23/7 CHSSA 15:0 31:16 24/8 All Resets Bit Range Register Name(1) Bits 1390 DCH4SSA 1440 DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED) 0000 0000 CHAIRQ CFORCE CABORT 00FF PATEN SIRQEN AIRQEN — — — 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 15:0 31:16 — — — — — — — — — — — — — — 15:0 31:16 15:0 0000 — — 0000 — — — — — — — — — — — — — — 0000 — — — — — — — 0000 CHSSIZ 15:0 31:16 0000 CHDSA 15:0 31:16 0000 CHSSA — — 0000 CHDSIZ — — — — — — — — — CHSPTR 0000 0000 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 190 TABLE 10-3: Virtual Address (BF81_#) 14B0 DCH5CSIZ 14C0 DCH5CPTR 14D0 DCH5DAT 14E0 DCH6CON 14F0 DCH6ECON DCH6INT 1510 DCH6SSA 1520 DCH6DSA 1530 DCH6SSIZ 1540 DCH6DSIZ 1550 DCH6SPTR 1560 DCH6DPTR 1570 DCH6CSIZ 1580 DCH6CPTR DS60001320H-page 191 1590 DCH6DAT 15A0 DCH7CON 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 — — — — — — — 15:0 31:16 — — — — — — 15:0 31:16 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — — — — — — — — 0000 CHEN CHAED CHCHN CHAEN — CHEDET CHPRI 0000 FF00 — — — — — — — — — — — — — — — — — — 0000 CHCPTR 15:0 — — 0000 CHPDAT 31:16 CHPIGN 15:0 CHBUSY — CHPIGNEN — CHPATLEN — — CHCHNS 31:16 — — — — — — — — 15:0 CHSIRQ 0000 0000 CHCSIZ 15:0 31:16 24/8 CHDPTR — All Resets Bit Range Register Name(1) Bits 14A0 DCH5DPTR 1500 DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED) 0000 0000 CHAIRQ CFORCE CABORT 00FF PATEN SIRQEN AIRQEN — — — 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 31:16 — — — — — — — — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — 0000 — — — — — — — — — — — — — — — 0000 CHEN CHAED CHCHN CHAEN — CHEDET CHPRI 0000 — — — — — — — — — — — — — — — — — — — — — — — 0000 0000 0000 0000 CHCPTR 15:0 — 0000 CHPDAT 31:16 15:0 CHBUSY — CHPIGN — CHPIGNEN — CHPATLEN — — CHCHNS 0000 0000 CHCSIZ 15:0 31:16 0000 — CHDPTR 15:0 31:16 — CHSPTR 15:0 31:16 — CHDSIZ 15:0 31:16 0000 CHSSIZ 15:0 31:16 0000 CHDSA 15:0 31:16 0000 CHSSA 15:0 0000 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 10-3: Virtual Address (BF81_#) DCH7INT 15D0 DCH7SSA 15E0 DCH7DSA 15F0 DCH7SSIZ 1600 DCH7DSIZ 1610 DCH7SPTR 1620 DCH7DPTR 1630 DCH7CSIZ 1640 DCH7CPTR 1650 DCH7DAT 31:16 31/15 30/14 29/13 — — — 15:0 28/12 27/11 26/10 25/9 24/8 — — — — — CHSIRQ 23/7 22/6 21/5 20/4 PATEN SIRQEN 19/3 18/2 17/1 16/0 AIRQEN — — — CHAIRQ CFORCE CABORT All Resets Bit Range Register Name(1) Bits 15B0 DCH7ECON 15C0 DMA CHANNEL 0 THROUGH CHANNEL 7 REGISTER MAP (CONTINUED) 00FF FF00 31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000 15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000 31:16 31:16 — — — — — — — — — — — — — — 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — 0000 — — — — — — — — — 0000 — — — — — — — — — 0000 — — — — — — — — — 0000 — — — — — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — 0000 0000 0000 0000 CHCPTR — — CHPDAT 0000 0000 CHCSIZ 15:0 31:16 0000 — CHDPTR 15:0 31:16 — CHSPTR 15:0 31:16 — CHDSIZ 15:0 31:16 0000 CHSSIZ 15:0 31:16 0000 CHDSA 15:0 31:16 0000 CHSSA 15:0 0000 0000 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information.  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 192 TABLE 10-3: PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 DMACON: DMA CONTROLLER CONTROL REGISTER Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0 ON — — SUSPEND DMABUSY — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: DMA On bit 1 = DMA module is enabled 0 = DMA module is disabled bit 14-13 Unimplemented: Read as ‘0’ bit 12 SUSPEND: DMA Suspend bit 1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus 0 = DMA operates normally bit 11 DMABUSY: DMA Module Busy bit 1 = DMA module is active and is transferring data 0 = DMA module is disabled and not actively transferring data bit 10-0 Unimplemented: Read as ‘0’  2015-2021 Microchip Technology Inc. DS60001320H-page 193 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-2: Bit Range 31:24 23:16 15:8 7:0 DMASTAT: DMA STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 RDWR — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 — — — — — DMACH Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31 x = Bit is unknown RDWR: Read/Write Status bit 1 = Last DMA bus access when an error was detected was a read 0 = Last DMA bus access when an error was detected was a write bit 30-3 Unimplemented: Read as ‘0’ bit 2-0 DMACH: DMA Channel bits These bits contain the value of the most recent active DMA channel when an error was detected. REGISTER 10-3: Bit Range 31:24 23:16 15:8 7:0 DMAADDR: DMA ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-0 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR R-0 R-0 DMAADDR R-0 R-0 R-0 R-0 R-0 DMAADDR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 DMAADDR: DMA Module Address bits These bits contain the address of the most recent DMA access when an error was detected. DS60001320H-page 194  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-4: Bit Range 31:24 23:16 15:8 7:0 DCRCCON: DMA CRC CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 R/W-0 R/W-0 — — U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 U-0 U-0 R/W-0 WBO(1) — — BITO U-0 U-0 U-0 U-0 U-0 — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BYTO PLEN R/W-0 R/W-0 R/W-0 U-0 U-0 CRCEN CRCAPP(1) CRCTYP — — R/W-0 CRCCH Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as ‘0’ bit 29-28 BYTO: CRC Byte Order Selection bits 11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order per half-word) 10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per half-word) 01 = Endian byte swap on word boundaries (i.e., reverse source byte order) 00 = No swapping (i.e., source byte order) bit 27 WBO: CRC Write Byte Order Selection bit(1) 1 = Source data is written to the destination re-ordered as defined by BYTO 0 = Source data is written to the destination unaltered bit 26-25 Unimplemented: Read as ‘0’ bit 24 BITO: CRC Bit Order Selection bit When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode): 1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected) 0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected) When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode): 1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected) 0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected) bit 23-13 Unimplemented: Read as ‘0’ bit 12-8 PLEN: Polynomial Length bits(1) When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode): These bits are unused. When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode): Denotes the length of the polynomial – 1. bit 7 CRCEN: CRC Enable bit 1 = CRC module is enabled and channel transfers are routed through the CRC module 0 = CRC module is disabled and channel transfers proceed normally Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.  2015-2021 Microchip Technology Inc. DS60001320H-page 195 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) bit 6 CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA 0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination bit 5 CRCTYP: CRC Type Selection bit 1 = The CRC module will calculate an IP header checksum 0 = The CRC module will calculate a LFSR CRC bit 4-3 Unimplemented: Read as ‘0’ bit 2-0 CRCCH: CRC Channel Select bits 111 = CRC is assigned to Channel 7 110 = CRC is assigned to Channel 6 101 = CRC is assigned to Channel 5 100 = CRC is assigned to Channel 4 011 = CRC is assigned to Channel 3 010 = CRC is assigned to Channel 2 001 = CRC is assigned to Channel 1 000 = CRC is assigned to Channel 0 Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. DS60001320H-page 196  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-5: Bit Range 31:24 23:16 15:8 7:0 DCRCDATA: DMA CRC DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA R/W-0 R/W-0 DCRCDATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 DCRCDATA: CRC Data Register bits Writing to this register will seed the CRC generator. Reading from this register will return the current value of the CRC. Bits greater than PLEN will return ‘0’ on any read. When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode): Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value). When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode): Bits greater than PLEN will return ‘0’ on any read. REGISTER 10-6: Bit Range 31:24 23:16 15:8 7:0 DCRCXOR: DMA CRCXOR ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR R/W-0 R/W-0 DCRCXOR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 DCRCXOR: CRC XOR Register bits When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode): This register is unused. When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode): 1 = Enable the XOR input to the Shift register 0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in the register  2015-2021 Microchip Technology Inc. DS60001320H-page 197 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-7: Bit Range 31:24 23:16 15:8 7:0 DCHxCON: DMA CHANNEL x CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 CHPIGN U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 CHBUSY — CHIPGNEN — CHPATLEN — — CHCHNS(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 CHEN(2) CHAED CHCHN CHAEN — CHEDET CHPRI Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 CHPIGN: Channel Register Data bits Pattern Terminate mode: Any byte matching these bits during a pattern match may be ignored during the pattern match determination when the CHPIGNEN bit is set. If a byte is read that is identical to this data byte, the pattern match logic will treat it as a “don’t care” when the pattern matching logic is enabled and the CHPIGEN bit is set. bit 23-16 Unimplemented: Read as ‘0’ bit 15 CHBUSY: Channel Busy bit 1 = Channel is active or has been enabled 0 = Channel is inactive or has been disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CHPIGNEN: Enable Pattern Ignore Byte bit 1 = Treat any byte that matches the CHPIGN bits as a “don’t care” when pattern matching is enabled 0 = Disable this feature bit 12 Unimplemented: Read as ‘0’ bit 11 CHPATLEN: Pattern Length bit 1 = 2 byte length 0 = 1 byte length bit 10-9 Unimplemented: Read as ‘0’ bit 8 CHCHNS: Chain Channel Selection bit(1) 1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete) 0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete) bit 7 CHEN: Channel Enable bit(2) 1 = Channel is enabled 0 = Channel is disabled bit 6 CHAED: Channel Allow Events If Disabled bit 1 = Channel start/abort events will be registered, even if the channel is disabled 0 = Channel start/abort events will be ignored if the channel is disabled bit 5 CHCHN: Channel Chain Enable bit 1 = Allow channel to be chained 0 = Do not allow channel to be chained Note 1: 2: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1). When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended. DS60001320H-page 198  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-7: DCHxCON: DMA CHANNEL x CONTROL REGISTER (CONTINUED) bit 4 CHAEN: Channel Automatic Enable bit 1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete 0 = Channel is disabled on block transfer complete bit 3 Unimplemented: Read as ‘0’ bit 2 CHEDET: Channel Event Detected bit 1 = An event has been detected 0 = No events have been detected bit 1-0 CHPRI: Channel Priority bits 11 = Channel has priority 3 (highest) 10 = Channel has priority 2 01 = Channel has priority 1 00 = Channel has priority 0 Note 1: 2: The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1). When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended.  2015-2021 Microchip Technology Inc. DS60001320H-page 199 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-8: Bit Range 31:24 23:16 DCHxECON: DMA CHANNEL x EVENT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 (1) R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 CHAIRQ 15:8 R/W-1 CHSIRQ(1) 7:0 S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 CFORCE CABORT PATEN SIRQEN AIRQEN — — — Legend: R = Readable bit -n = Value at POR S = Settable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23-16 CHAIRQ: Channel Transfer Abort IRQ bits(1) 11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag • • • bit 15-8 00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag 00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag CHSIRQ: Channel Transfer Start IRQ bits(1) 11111111 = Interrupt 255 will initiate a DMA transfer • • • bit 2-0 00000001 = Interrupt 1 will initiate a DMA transfer 00000000 = Interrupt 0 will initiate a DMA transfer CFORCE: DMA Forced Transfer bit 1 = A DMA transfer is forced to begin when this bit is written to a ‘1’ 0 = This bit always reads ‘0’ CABORT: DMA Abort Transfer bit 1 = A DMA transfer is aborted when this bit is written to a ‘1’ 0 = This bit always reads ‘0’ PATEN: Channel Pattern Match Abort Enable bit 1 = Abort transfer and clear CHEN on pattern match 0 = Pattern match is disabled SIRQEN: Channel Start IRQ Enable bit 1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs 0 = Interrupt number CHSIRQ is ignored and does not start a transfer AIRQEN: Channel Abort IRQ Enable bit 1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs 0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer Unimplemented: Read as ‘0’ Note 1: See Table 7-2: “Interrupt IRQ, Vector, and Bit Location” for the list of available interrupt IRQ sources. bit 7 bit 6 bit 5 bit 4 bit 3 DS60001320H-page 200  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-9: Bit Range 31:24 23:16 15:8 7:0 DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23 CHSDIE: Channel Source Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 16 CHERIE: Channel Address Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 15-8 Unimplemented: Read as ‘0’ bit 7 CHSDIF: Channel Source Done Interrupt Flag bit 1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ) 0 = No interrupt is pending bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit 1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2) 0 = No interrupt is pending  2015-2021 Microchip Technology Inc. DS60001320H-page 201 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-9: DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER (CONTINUED) bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit 1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ) 0 = No interrupt is pending bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2) 0 = No interrupt is pending bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit 1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a pattern match event occurs 0 = No interrupt is pending bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit 1 = A cell transfer has been completed (CHCSIZ bytes have been transferred) 0 = No interrupt is pending bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit 1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted 0 = No interrupt is pending bit 0 CHERIF: Channel Address Error Interrupt Flag bit 1 = A channel address error has been detected  Either the source or the destination address is invalid. 0 = No interrupt is pending DS60001320H-page 202  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-10: DCHxSSA: DMA CHANNEL x SOURCE START ADDRESS REGISTER Bit Range Bit 31/23/15/7 Bit 30/22/14/6 R/W-0 R/W-0 31:24 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA R/W-0 23:16 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA R/W-0 15:8 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA R/W-0 7:0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 x = Bit is unknown CHSSA Channel Source Start Address bits Channel source start address. Note: This must be the physical address of the source. REGISTER 10-11: DCHxDSA: DMA CHANNEL x DESTINATION START ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA R/W-0 R/W-0 CHDSA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA R/W-0 CHDSA Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 CHDSA: Channel Destination Start Address bits Channel destination start address. Note: This must be the physical address of the destination.  2015-2021 Microchip Technology Inc. DS60001320H-page 203 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-12: DCHxSSIZ: DMA CHANNEL x SOURCE SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSIZ 7:0 R/W-0 CHSSIZ Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHSSIZ: Channel Source Size bits 1111111111111111 = 65,535 byte source size • • • 0000000000000010 = 2 byte source size 0000000000000001 = 1 byte source size 0000000000000000 = 65,536 byte source size REGISTER 10-13: DCHxDSIZ: DMA CHANNEL x DESTINATION SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSIZ 7:0 R/W-0 CHDSIZ Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHDSIZ: Channel Destination Size bits 1111111111111111 = 65,535 byte destination size • • • 0000000000000010 = 2 byte destination size 0000000000000001 = 1 byte destination size 0000000000000000 = 65,536 byte destination size DS60001320H-page 204  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-14: DCHxSPTR: DMA CHANNEL x SOURCE POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHSPTR 7:0 R-0 R-0 CHSPTR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHSPTR: Channel Source Pointer bits 1111111111111111 = Points to byte 65,535 of the source • • • 0000000000000001 = Points to byte 1 of the source 0000000000000000 = Points to byte 0 of the source Note: When in Pattern Detect mode, this register is reset on a pattern detect. REGISTER 10-15: DCHxDPTR: DMA CHANNEL x DESTINATION POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHDPTR 7:0 R-0 R-0 CHDPTR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHDPTR: Channel Destination Pointer bits 1111111111111111 = Points to byte 65,535 of the destination • • • 0000000000000001 = Points to byte 1 of the destination 0000000000000000 = Points to byte 0 of the destination  2015-2021 Microchip Technology Inc. DS60001320H-page 205 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-16: DCHxCSIZ: DMA CHANNEL x CELL-SIZE REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHCSIZ 7:0 R/W-0 CHCSIZ Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHCSIZ: Channel Cell-Size bits 1111111111111111 = 65,535 bytes transferred on an event • • • 0000000000000010 = 2 bytes transferred on an event 0000000000000001= 1 byte transferred on an event 0000000000000000 = 65,536 bytes transferred on an event REGISTER 10-17: DCHxCPTR: DMA CHANNEL x CELL POINTER REGISTER Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 CHCPTR 7:0 R-0 R-0 CHCPTR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHCPTR: Channel Cell Progress Pointer bits 1111111111111111 = 65,535 bytes have been transferred since the last event • • • 0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event Note: When in Pattern Detect mode, this register is reset on a pattern detect. DS60001320H-page 206  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 10-18: DCHxDAT: DMA CHANNEL x PATTERN DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHPDAT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHPDAT Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHPDAT: Channel Data Register bits Pattern Terminate mode: Data to be matched must be stored in this register to allow terminate on match. All other modes: Unused.  2015-2021 Microchip Technology Inc. DS60001320H-page 207 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320H-page 208  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 11.0 HI-SPEED USB WITH ONTHE-GO (OTG) Note: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 51. “Hi-Speed USB with On-The-Go (OTG)” (DS60001326) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 embedded host, device, or OTG implementation with a minimum of external components. The module supports Hi-Speed, Full-Speed, or LowSpeed in any of the operating modes. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller. The USB module consists of the RAM controller, packet encode/decode, UTM synchronization, endpoint control, a dedicated USB DMA controller, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32 USB OTG module is presented in Figure 11-1. The USB module includes the following features: • USB Hi-Speed, Full-Speed, and Low-Speed support for host and device • USB OTG support with one or more Hi-Speed, Full-Speed, or Low-Speed device • Integrated signaling resistors • Integrated analog comparators for VBUS monitoring • Integrated USB transceiver • Transaction handshaking performed by hardware • Integrated 8-channel DMA to access system RAM and Flash • Seven transmit endpoints and seven receive endpoints, in addition to Endpoint 0 • Session Request Protocol (SRP) and Host Negotiation Protocol (HNP) support • Suspend and resume signaling support • Dynamic FIFO sizing • Integrated RAM for the FIFOs, eliminating the need for system RAM for the FIFOs • Link power management support Note 1: The implementation and use of the USB specifications, as well as other third party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations. 2: If the USB module is used, the Primary Oscillator (POSC) is limited to either 12 MHz or 24 MHz.  2015-2021 Microchip Technology Inc. DS60001320H-page 209 PIC32MZ EF FAMILY USB INTERFACE DIAGRAM USBCLK POSC (12 MHz or 24 MHz only) USB PLL UPLLFSEL Endpoint Control EP0 Control Host EPO Control Function EP1 - EP7 Control Combine Endpoints DMA Requests Transmit Receive Host Transaction Scheduler Interrupt Control Interrupts EP Reg Decoder Common Regs D+ UTM Synchronization Packet Encode/Decode D- Data Sync Packet Encode HS Negotiation Packet Decode HNP/SRP CRC Gen/Check USBID VUSB3V3  2015-2021 Microchip Technology Inc. VBUS USB 2.0 HS PHY RAM Controller RX Buff RX Buff TX Buff TX Buff Cycle Control Timers Link Power Management RAM Cycle Control FIFO Decoder System Bus Client mode PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 210 FIGURE 11-1: USB OTG Control Registers TABLE 11-1: USB REGISTER MAP 1 31:16 3000 USBCSR0 3004 USBCSR1 3008 USBCSR2 300C USBCSR3 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 — — — — — — EP7TXIF EP6TXIF EP5TXIF EP4TXIF — — ISOUPD(1) SOFT CONN(1) —(2) —(2) 31:16 — — — — — 15:0 — — — — — SOFIE 15:0 HSEN HSMODE 31:16 VBUSERRIE SESSRQIE DISCONIE CONNIE 15:0 — 31:16 FORCEHST 15:0 — — — FIFOACC — FORCEFS FORCEHS — — — RESET 3010 31:16 USB IE0CSR0(3) — — — — — — — — — — — — — 31:16 USB 301C IE0CSR3(3) 15:0 MPRXEN MPTXEN BIGEND HBRXEN — — — — ISO(1) 3010 31:16 AUTOSET USB IENCSR0(4) MODE — 15:0 31:16 AUTOCLR USB 3014 IENCSR1(4) AUTORQ(2) 15:0 DS60001320H-page 211 31:16 USB 301C IENCSR3(1,3) 15:0 DMA REQEN —(2) EP7TXIE EP6TXIE EP5TXIE EP4TXIE EP3TXIE EP2TXIE EP1TXIE EP0IE 00FF — EP7RXIF EP6RXIF EP5RXIF EP4RXIF EP3RXIF EP2RXIF EP1RXIF — 0000 RESETIE RESUMEIE DISCONIF CONNIF SOFIF RESETIF EP3RXIE EP2RXIE SUSPIE VBUSERRIF SESSREQIF — — EP7RXIE EP6RXIE EP5RXIE EP4RXIE NAK — — — — — —(1) —(1) DATA TGGL(2) — FLSHFIFO — — — — — DMA REQMD SVCRPR(1) SEND STALL(1) EP1RXIE — ENDPOINT 0000 DATAEND(1) SENT STALL(1) RXSTALL(2) NAK TMOUT(2) STATPKT(2) REQPKT(2) ERROR(2) SETUP PKT(2) — — — — — SPEED(2) — — — RXPKT RDY — — — 0000 — — — 0000 RXCNT 0000 — — — — — — — xx00 — — — — — — — 0000 SENT STALL(1) SEND STALL(1) FIFONE RXSTALL(2) SETUPPKT(2) TXPKT RDY — — —(1) —(1) INCOMP TX(1) DTWREN(2) DATA TGGL(2) NAK TMOUT(2) PIDERR(2) DMA REQMD —(1) DATA TWEN(2) DATA TGGL(2) INCOM PRX CLRDT FLUSH UNDER RUN(1) ERROR(2) CLRDT RXSTALL(2) REQPKT(2) SPEED(2) — DATAERR(1) OVERRUN(1) FLUSH DERRNAKT(1) ERROR(2) FIFOFULL TXFIFOSZ RXINTERV — — SPEED 0000 0000 RXPKT RDY 0000 0000 PROTOCOL TEP 0000 RXCNT RXFIFOSZ 0000 0000 SENTSTALL(1) SENDSTALL(1) RXMAXP TXINTERV(2) 0000 — — —(1) 0000 TXPKT RDY TXMAXP DISNYET(1) 00FE 0000 SETUP END(1) — HBTXEN DYNFIFOS SOFTCONE UTMIDWID — SVC SETEND(1) 2000 RESUMEIF SUSPIF 0600 RFRMNUM MULT — —(2) —(2) TESTJ FRC DATTG —(2) 0000 — NAKLIM(2) DMA REQEN EP0IF — —(2) — — EP1TXIF — —(2) TESTK — EP2TXIF — —(2) — — EP3TXIF — — MULT ISO(1) 31:16 USB 3018 IENCSR2(4) 15:0 — 16/0 SUSPEN DISPING(2) DTWREN(2) 15:0 17/1 SUSP MODE RESUME — 31:16 USB 3018 IE0CSR2(3) 15:0 18/2 FUNC(1) PACKET —(1) 19/3 All Resets Bit Range Register Name Virtual Address Bits 0000 — — PROTOCOL — — TEP — — 0000 0000 3020 USB FIFO0 31:16 DATA 0000 15:0 DATA 0000 3024 USB FIFO1 31:16 DATA 0000 15:0 DATA 0000 Legend: Note 1: 2: 3: 4: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0). Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7). PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. 11.1 USB REGISTER MAP 1 (CONTINUED) Virtual Address Register Name Bit Range All Resets Bits 3028 USB FIFO2 31:16 DATA 0000 15:0 DATA 0000 302C USB FIFO3 31:16 DATA 0000 15:0 DATA 0000 3030 USB FIFO4 31:16 DATA 0000 15:0 DATA 0000 3034 USB FIFO5 31:16 DATA 0000 15:0 DATA 0000 3038 USB FIFO6 31:16 DATA 0000 15:0 DATA 0000 303C USB FIFO7 31:16 DATA 0000 15:0 DATA 3060 USBOTG 31/15 30/14 29/13 28/12 27/11 31:16 — — — RXDPB 15:0 — — — — 26/10 25/9 24/8 23/7 RXFIFOSZ — — TXEDMA RXEDMA 22/6 21/5 — — BDEV FSDEV LSDEV USB FIFOA 31:16 — — — RXFIFOAD 15:0 — — — TXFIFOAD 306C USB HWVER 31:16 — — — 15:0 RC 3078 USB INFO 31:16 31:16 — — — — VERMAJOR — — — 15:0 RAMBITS —  2015-2021 Microchip Technology Inc. 3080 — 15:0 — — — NRSTX 3084 USB E0RXA 31:16 — 15:0 — 3088 USB E1TXA 31:16 — 15:0 — 308C USB E1RXA 31:16 — 15:0 — 3090 USB E2TXA 31:16 — 15:0 — 3094 USB E2RXA 31:16 — 15:0 — 3098 USB E3TXA 31:16 — 15:0 — — — — — — — RXHUBPRT — — — — — — — TXHUBPRT — — — — — — — RXHUBPRT — — — — — — — TXHUBPRT — — — — — — — RXHUBPRT — — — — — — — TXHUBPRT — — — 16/0 TXDPB TXFIFOSZ VBUS 0000 HOSTMODE HOSTREQ SESSION 0080 0000 — — — — — — — — — x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0). Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7). — 0000 0800 WTCON WTID 3C5C RXENDPTS TXENDPTS 8C77 NRST TXHUBPRT — 17/1 0000 FSEOF 31:16 18/2 VERMINOR DMACHANS USB E0TXA Legend: Note 1: 2: 3: 4: — VPLEN 15:0 USB 307C EOFRST — 19/3 0000 — 3064 — 20/4 LSEOF 0072 HSEOF 7780 MULTTRAN TXHUBADD 0000 — TXFADDR 0000 MULTTRAN RXHUBADD — — — — — 0000 — — — 0000 MULTTRAN TXHUBADD 0000 — TXFADDR 0000 MULTTRAN RXHUBADD 0000 — RXFADDR 0000 MULTTRAN TXHUBADD 0000 — TXFADDR 0000 MULTTRAN RXHUBADD 0000 — RXFADDR 0000 MULTTRAN TXHUBADD 0000 — TXFADDR 0000 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 212 TABLE 11-1: USB REGISTER MAP 1 (CONTINUED) Bit Range 309C USB E3RXA 31:16 — 15:0 — 30A0 US BE4TXA 31:16 — 15:0 — 30A4 USB E4RXA 31:16 — 15:0 — 30A8 USB E5TXA 31:16 — 15:0 — 30AC USB E5RXA 31:16 — 15:0 — 30B0 USB E6TXA 31:16 — 15:0 — 30B4 USB E6RXA 31:16 — 15:0 — 30B8 USB E7TXA 31:16 — 15:0 — 30BC USB E7RXA 31:16 — 15:0 — 3100 USB E0CSR0 31:16 3108 USB E0CSR2 31:16 USB 310C E0CSR3 31:16 3110 USB E1CSR0 31:16 3114 USB E1CSR1 31:16 3118 USB E1CSR2 31:16 311C USB E1CSR3 31:16 3120 USB E2CSR0 31:16 3124 USB E2CSR1 31:16 Legend: Note 1: 2: 3: 4: 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 31/15 30/14 29/13 28/12 — — — 27/11 26/10 25/9 24/8 — — — RXHUBPRT — TXHUBPRT — — — — — — — RXHUBPRT — — — — — — — TXHUBPRT — — — — — — — RXHUBPRT — — — — — — — TXHUBPRT — — — — — — — RXHUBPRT — — — — — — — TXHUBPRT — — — — — — — RXHUBPRT — — — — — — — 23/7 22/6 20/4 19/3 18/2 17/1 16/0 MULTTRAN RXHUBADD 0000 — RXFADDR 0000 MULTTRAN TXHUBADD 0000 — TXFADDR 0000 MULTTRAN RXHUBADD 0000 — RXFADDR 0000 MULTTRAN TXHUBADD 0000 — TXFADDR 0000 MULTTRAN RXHUBADD 0000 — RXFADDR 0000 MULTTRAN TXHUBADD 0000 — TXFADDR 0000 MULTTRAN RXHUBADD 0000 — RXFADDR 0000 MULTTRAN TXHUBADD 0000 — TXFADDR 0000 MULTTRAN RXHUBADD 0000 — RXFADDR 0000 Indexed by the same bits in USBIE0CSR0 Indexed by the same bits in USBIE0CSR2 Indexed by the same bits in USBIE0CSR3 Indexed by the same bits in USBIE1CSR0 Indexed by the same bits in USBIE1CSR1 Indexed by the same bits in USBIE1CSR2 Indexed by the same bits in USBIE1CSR3 Indexed by the same bits in USBIE2CSR0 Indexed by the same bits in USBIE2CSR1 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0). Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7). 21/5 All Resets Register Name DS60001320H-page 213 Virtual Address Bits 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 11-1: USB REGISTER MAP 1 (CONTINUED) Bit Range 3128 USB E2CSR2 31:16 USB 312C E2CSR3 31:16 3130 USB E3CSR0 31:16 3134 USB E3CSR1 31:16 3138 USB E3CSR2 31:16 USB 313C E3CSR3 31:16 3140 USB E4CSR0 31:16 3144 USB E4CSR1 31:16 3148 USB E4CSR2 31:16 USB 314C E4CSR3 31:16 3150 USB E5CSR0 31:16 3154 USB E5CSR1 31:16 3158 USB E5CSR2 31:16 USB 315C E5CSR3 31:16 3160 USB E6CSR0 31:16 3164 USB E6CSR1 31:16 3168 USB E6CSR2 31:16 USB 316C E6CSR3 31:16 Legend: Note 1: 2: 3: 4: 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 15:0 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 Indexed by the same bits in USBIE2CSR2 Indexed by the same bits in USBIE2CSR3 Indexed by the same bits in USBIE3CSR0 Indexed by the same bits in USBIE3CSR1 Indexed by the same bits in USBIE3CSR2 Indexed by the same bits in USBIE3CSR3 Indexed by the same bits in USBIE4CSR0 Indexed by the same bits in USBIE4CSR1 Indexed by the same bits in USBIE4CSR2 Indexed by the same bits in USBIE4CSR3 Indexed by the same bits in USBIE5CSR0 Indexed by the same bits in USBIE5CSR1 Indexed by the same bits in USBIE5CSR2 Indexed by the same bits in USBIE5CSR3 Indexed by the same bits in USBIE6CSR0 Indexed by the same bits in USBIE6CSR1 Indexed by the same bits in USBIE6CSR2 Indexed by the same bits in USBIE6CSR3 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0). Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7). 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Register Name  2015-2021 Microchip Technology Inc. Virtual Address Bits 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 214 TABLE 11-1: USB REGISTER MAP 1 (CONTINUED) Register Name Bit Range DS60001320H-page 215 Virtual Address All Resets Bits 3170 USB E7CSR0 31:16 3174 USB E7CSR1 31:16 3178 USB E7CSR2 31:16 USB 317C E7CSR3 31:16 3200 USB DMAINT 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — DMA8IF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF 3204 USB DMA1C 31:16 — — — — — — — — — — — — 15:0 — — — — — 3208 USB DMA1A 31:16 DMAADDR 0000 15:0 DMAADDR 0000 320C USB DMA1N 31:16 DMACOUNT 0000 15:0 DMACOUNT 3214 USB DMA2C 31:16 — — — — — 15:0 — — — — — 3218 USB DMA2A 31:16 DMAADDR 0000 15:0 DMAADDR 0000 321C USB DMA2N 31:16 DMACOUNT 0000 15:0 DMACOUNT 3224 USB DMA3C 31:16 — — — — — 15:0 — — — — — 3228 USB DMA3A 31:16 DMAADDR 0000 15:0 DMAADDR 0000 322C USB DMA3N 31:16 DMACOUNT 0000 15:0 DMACOUNT 3234 USB DMA4C 31:16 — — — — — 15:0 — — — — — 3238 USB DMA4A 31:16 DMAADDR 0000 15:0 DMAADDR 0000 323C USB DMA4N 31:16 DMACOUNT 0000 15:0 DMACOUNT 3244 USB DMA5C 31:16 — — — — — 15:0 — — — — — Legend: Note 1: 2: 3: 4: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0000 Indexed by the same bits in USBIE7CSR0 15:0 0000 0000 Indexed by the same bits in USBIE7CSR1 15:0 0000 0000 Indexed by the same bits in USBIE7CSR2 15:0 0000 0000 Indexed by the same bits in USBIE7CSR3 15:0 DMABRSTM — — DMABRSTM — — — — x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0). Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7). — — — DMADIR — 0000 DMAEN 0000 — — — DMAIE DMAMODE DMADIR — 0000 DMAEN 0000 — — — DMAIE DMAMODE DMADIR — 0000 DMAEN 0000 0000 — — — DMAEP — — DMAMODE 0000 — DMAERR DMAERR — DMAEP — — — DMAEP — — DMAIE 0000 DMA1IF 0000 0000 — DMAERR — DMABRSTM DMAEP DMAERR — DMABRSTM — — — DMABRSTM — DMAERR 0000 — — — — DMAIE DMAMODE DMADIR — 0000 DMAEN 0000 0000 — — DMAEP — — — — DMAIE DMAMODE DMADIR — 0000 DMAEN 0000 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 11-1: USB REGISTER MAP 1 (CONTINUED) Register Name Bit Range  2015-2021 Microchip Technology Inc. Virtual Address All Resets Bits 3248 USB DMA5A 31:16 DMAADDR 0000 15:0 DMAADDR 0000 324C USB DMA5N 31:16 DMACOUNT 0000 15:0 DMACOUNT 3254 USB DMA6C 31:16 — — — — — 15:0 — — — — — 3258 USB DMA6A 31:16 DMAADDR 0000 15:0 DMAADDR 0000 325C USB DMA6N 31:16 DMACOUNT 0000 15:0 DMACOUNT 3264 USB DMA7C 31:16 — — — — — 15:0 — — — — — 3268 USB DMA7A 31:16 DMAADDR 0000 15:0 DMAADDR 0000 326C USB DMA7N 31:16 DMACOUNT 0000 15:0 DMACOUNT 3274 USB DMA8C 31:16 — — — — — 15:0 — — — — — 3278 USB DMA8A 31:16 DMAADDR 0000 15:0 DMAADDR 0000 327C USB DMA8N 31:16 DMACOUNT 0000 15:0 DMACOUNT 3304 USB E1RPC 31:16 3308 USB E2RPC 31:16 330C USB E3RPC 31:16 3310 USB E4RPC 31:16 3314 USB E5RPC 31:16 3318 USB E6RPC 31:16 331C USB E7RPC 31:16 Legend: Note 1: 2: 3: 4: 31/15 — 30/14 — 29/13 — 28/12 — 27/11 — 26/10 — 25/9 — DMABRSTM — 23/7 — 22/6 — 15:0 — — — — — DMAEP — 18/2 17/1 16/0 — — — DMAIE DMAMODE DMADIR — — — — DMAIE DMAMODE DMADIR — — — — — — — — 15:0 — — — — DMAIE DMAMODE DMADIR — — — — — — — — 15:0 — 0000 — — — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — — — 15:0 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0). Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7). — — — — — — — — — RQPKTCNT 0000 0000 0000 0000 RQPKTCNT — 0000 0000 RQPKTCNT — 0000 0000 RQPKTCNT — 0000 0000 RQPKTCNT — 0000 DMAEN 0000 RQPKTCNT — 0000 DMAEN 0000 RQPKTCNT — 0000 DMAEN 0000 0000 — DMAERR — — DMAEP — 19/3 0000 — DMAERR — 20/4 DMAEP — — 21/5 0000 — DMAERR — DMABRSTM — — — DMABRSTM — 24/8 0000 0000 0000 0000 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 216 TABLE 11-1: USB REGISTER MAP 1 (CONTINUED) Register Name Bit Range 3340 USB DPBFD 31:16 3344 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 — — — — — — — — EP7TXD EP6TXD EP5TXD EP4TXD EP3TXD 15:0 — — — — — — — — EP7RXD EP6RXD EP5RXD EP4RXD EP3RXD 31:16 USB TMCON1 15:0 31:16 USB 3348 TMCON2 15:0 3360 3364 31:16 USB LPMR1 USB LPMR2 Legend: Note 1: 2: 3: 4: 15:0 22/6 21/5 20/4 19/3 18/2 17/1 16/0 EP2TXD EP1TXD — 0000 EP2RXD EP1RXD — 0000 THHSRTN 05E6 TUCH 4074 — — — — — — — — — — — — — — — — — — — — — — — — — LPM ERRIE LPM RESIE — 15:0 31:16 23/7 ENDPOINT — — — — — LPMACKIE LPMNYIE LPMSTIE LPMTOIE — — — RMTWAK — — — — — — — — — LPMFADDR — — — LPMNAK(1) LPMEN —(2) —(2) LPMRES LPMXMT —(2) LPMERR(1) —(2) 0000 0000 LNKSTATE — — — THSBT HIRD — All Resets Virtual Address Bits 0000 0000 0000 — — — — — LPMRES LPMNC LPMACK LPMNY LPMST 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Device mode. Host mode. Definition for Endpoint 0 (ENDPOINT (USBCSR) = 0). Definition for Endpoints 1-7 (ENDPOINT (USBCSR) = 1 through 7). TABLE 11-2: USB REGISTER MAP 2 Register Name 4000 USB CRCON Legend: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — USBIF USBRF USBWKUP — — — — — — — — 0100 15:0 — — — — — — USB IDOVEN USB IDVAL PHYIDEN VBUS MONEN ASVAL MONEN BSVAL MONEN SEND MONEN USBIE USBRIE USB WKUPEN 8000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Virtual Address Bit Range Bits DS60001320H-page 217 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 11-1: PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-1: Bit Range 31:24 23:16 15:8 7:0 USBCSR0: USB CONTROL STATUS REGISTER 0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS EP7TXIF EP6TXIF EP5TXIF EP4TXIF EP3TXIF EP2TXIF EP1TXIF EP0IF R/W-0 R/W-0 R/W-1 R-0, HS R-0 R/W-0 R-0, HC R/W-0 ISOUPD SOFTCONN HSEN HSMODE RESET RESUME SUSPMODE SUSPEN — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — — — — Legend: FUNC HS = Hardware Set — HC = Hardware Cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23-17 EP7TXIF:EP1TXIF: Endpoint ‘n’ TX Interrupt Flag bit 1 = Endpoint has a transmit interrupt to be serviced 0 = No interrupt event bit 16 EP0IF: Endpoint 0 Interrupt bit 1 = Endpoint 0 has an interrupt to be serviced 0 = No interrupt event All EPxTX and EP0 bits are cleared when the byte is read. Therefore, these bits must be read independently from the remaining bits in this register to avoid accidental clearing. bit 15 ISOUPD: ISO Update bit (Device mode only; unimplemented in Host mode) 1 = USB module will wait for a SOF token from the time TXPKTRDY is set before sending the packet 0 = No change in behavior This bit only affects endpoints performing isochronous transfers when in Device mode. This bit is unimplemented in Host mode. bit 14 SOFTCONN: Soft Connect/Disconnect Feature Selection bit 1 = The USB D+/D- lines are enabled and active 0 = The USB D+/D- lines are disabled and are tri-stated This bit is only available in Device mode. bit 13 HSEN: Hi-Speed Enable bit 1 = The USB module will negotiate for Hi-Speed mode when the device is reset by the hub 0 = Module only operates in Full-Speed mode bit 12 HSMODE: Hi-Speed Mode Status bit 1 = Hi-Speed mode successfully negotiated during USB reset 0 = Module is not in Hi-Speed mode In Device mode, this bit becomes valid when a USB reset completes. In Host mode, it becomes valid when the RESET bit is cleared. bit 11 RESET: Module Reset Status bit 1 = Reset signaling is present on the bus 0 = Normal module operation In Device mode, this bit is read-only. In Host mode, this bit is read/write. DS60001320H-page 218  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-1: bit 10 USBCSR0: USB CONTROL STATUS REGISTER 0 (CONTINUED) RESUME: Resume from Suspend control bit 1 = Generate Resume signaling when the device is in Suspend mode 0 = Stop Resume signaling In Device mode, the software should clear this bit after 10 ms (a maximum of 15 ms) to end Resume signaling. In Host mode, the software should clear this bit after 20 ms. bit 9 SUSPMODE: Suspend Mode status bit 1 = The USB module is in Suspend mode 0 = The USB module is in Normal operations This bit is read-only in Device mode. In Host mode, it can be set by software, and is cleared by hardware. bit 8 SUSPEN: Suspend Mode Enable bit 1 = Suspend mode is enabled 0 = Suspend mode is not enabled bit 7 Unimplemented: Read as ‘0’ bit 6-0 FUNC: Device Function Address bits These bits are only available in Device mode. This field is written with the address received through a SET_ADDRESS command, which will then be used for decoding the function address in subsequent token packets.  2015-2021 Microchip Technology Inc. DS60001320H-page 219 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-2: Bit Range 31:24 23:16 15:8 7:0 USBCSR1: USB CONTROL STATUS REGISTER 1 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 EP7TXIE EP6TXIE EP5TXIE EP4TXIE EP3TXIE EP2TXIE EP1TXIE EP0IE U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS U-0 EP7RXIF EP6RXIF EP5RXIF EP4RXIF EP3RXIF EP2RXIF EP1RXIF — Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23-17 EP7TXIE:EP1TXIE: Endpoint ‘n’ Transmit Interrupt Enable bits 1 = Endpoint Transmit interrupt events are enabled 0 = Endpoint Transmit interrupt events are not enabled bit 16 EP0IE: Endpoint 0 Interrupt Enable bit 1 = Endpoint 0 interrupt events are enabled 0 = Endpoint 0 interrupt events are not enabled bit 15-8 Unimplemented: Read as ‘0’ bit 7-1 bit 0 EP7RXIF:EP1RXIF: Endpoint ‘n’ RX Interrupt bit 1 = Endpoint has a receive event to be serviced 0 = No interrupt event Unimplemented: Read as ‘0’ DS60001320H-page 220  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-3: Bit Range 31:24 23:16 15:8 7:0 USBCSR2: USB CONTROL STATUS REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 VBUSERRIE SESSRQIE DISCONIE R-0, HS R-0, HS Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 CONNIE SOFIE RESETIE RESUMEIE SUSPIE R-0, HS VBUSERRIF SESSRQIF DISCONIF R-0, HS R-0, HS R-0, HS R-0, HS R-0, HS CONNIF SOFIF RESETIF RESUMEIF SUSPIF U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 EP7RXIE EP6RXIE EP5RXIE EP4RXIE EP3RXIE EP2RXIE EP1RXIE — Legend: R = Readable bit -n = Value at POR HS = Hardware Set W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31 VBUSERRIE: VBUS Error Interrupt Enable bit 1 = VBUS error interrupt is enabled 0 = VBUS error interrupt is disabled bit 30 SESSRQIE: Session Request Interrupt Enable bit 1 = Session request interrupt is enabled 0 = Session request interrupt is disabled bit 29 DISCONIE: Device Disconnect Interrupt Enable bit 1 = Device disconnect interrupt is enabled 0 = Device disconnect interrupt is disabled bit 28 CONNIE: Device Connection Interrupt Enable bit 1 = Device connection interrupt is enabled 0 = Device connection interrupt is disabled bit 27 SOFIE: Start of Frame Interrupt Enable bit 1 = Start of Frame event interrupt is enabled 0 = Start of Frame event interrupt is disabled bit 26 RESETIE: Reset/Babble Interrupt Enable bit 1 = Interrupt when reset (Device mode) or Babble (Host mode) is enabled 0 = Reset/Babble interrupt is disabled bit 25 RESUMEIE: Resume Interrupt Enable bit 1 = Resume signaling interrupt is enabled 0 = Resume signaling interrupt is disabled bit 24 SUSPIE: Suspend Interrupt Enable bit 1 = Suspend signaling interrupt is enabled 0 = Suspend signaling interrupt is disabled bit 23 VBUSERRIF: VBUS Error Interrupt bit 1 = VBUS has dropped below the VBUS valid threshold during a session 0 = No interrupt bit 22 SESSRQIF: Session Request Interrupt bit 1 = Session request signaling has been detected 0 = No session request detected bit 21 DISCONIF: Device Disconnect Interrupt bit 1 = In Host mode, indicates when a device disconnect is detected. In Device mode, indicates when a session ends. 0 = No device disconnect detected bit 20 CONNIF: Device Connection Interrupt bit 1 = In Host mode, indicates when a device connection is detected 0 = No device connection detected  2015-2021 Microchip Technology Inc. DS60001320H-page 221 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-3: USBCSR2: USB CONTROL STATUS REGISTER 2 (CONTINUED) bit 19 SOFIF: Start of Frame Interrupt bit 1 = A new frame has started 0 = No start of frame detected bit 18 RESETIF: Reset/Babble Interrupt bit 1 = In Host mode, indicates babble is detected. In Device mode, indicates reset signaling is detected on the bus. 0 = No reset/babble detected bit 17 RESUMEIF: Resume Interrupt bit 1 = Resume signaling is detected on the bus while USB module is in Suspend mode 0 = No Resume signaling detected bit 16 SUSPIF: Suspend Interrupt bit 1 = Suspend signaling is detected on the bus (Device mode) 0 = No suspend signaling detected bit 15-8 Unimplemented: Read as ‘0’ bit 7-1 EP7RXIE:EP1RXIE: Endpoint ‘n’ Receive Interrupt Enable bit 1 = Receive interrupt is enabled for this endpoint 0 = Receive interrupt is not enabled bit 0 Unimplemented: Read as ‘0’ DS60001320H-page 222  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-4: Bit Range 31:24 23:16 15:8 7:0 USBCSR3: USB CONTROL STATUS REGISTER 3 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FORCEHST FIFOACC FORCEFS FORCEHS PACKET TESTK TESTJ NAK U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — U-0 U-0 U-0 U-0 U-0 ENDPOINT — — — — — R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RFRMUM R-0 R-0 R-0 RFRMNUM Legend: R = Readable bit -n = Value at POR HC = Hardware Cleared W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31 FORCEHST: Test Mode Force Host Select bit 1 = Forces USB module into Host mode, regardless of whether it is connected to any peripheral 0 = Normal operation bit 30 FIFOACC: Test Mode Endpoint 0 FIFO Transfer Force bit 1 = Transfers the packet in the Endpoint 0 TX FIFO to the Endpoint 0 RX FIFO 0 = No transfer bit 29 FORCEFS: Test mode Force Full-Speed Mode Select bit This bit is only active if FORCEHST = 1. 1 = Forces USB module into Full-Speed mode. Undefined behavior if FORCEHS = 1. 0 = If FORCEHS = 0, places USB module into Low-Speed mode. bit 28 FORCEHS: Test mode Force Hi-Speed Mode Select bit This bit is only active if FORCEHST = 1. 1 = Forces USB module into Hi-Speed mode. Undefined behavior if FORCEFS = 1. 0 = If FORCEFS = 0, places USB module into Low-Speed mode. bit 27 PACKET: Test_Packet Test Mode Select bit This bit is only active if module is in Hi-Speed mode. 1 = The USB module repetitively transmits on the bus a 53-byte test packet. Test packet must be loaded into the Endpoint 0 FIFO before the test mode is entered. 0 = Normal operation bit 26 TESTK: Test_K Test Mode Select bit 1 = Enters Test_K test mode. The USB module transmits a continuous K on the bus. 0 = Normal operation This bit is only active if the USB module is in Hi-Speed mode. bit 25 TESTJ: Test_J Test Mode Select bit 1 = Enters Test_J test mode. The USB module transmits a continuous J on the bus. 0 = Normal operation This bit is only active if the USB module is in Hi-Speed mode. bit 24 NAK: Test_SE0_NAK Test Mode Select bit 1 = Enter Test_SE0_NAK test mode. The USB module remains in Hi-Speed mode but responds to any valid IN token with a NAK 0 = Normal operation This mode is only active if module is in Hi-Speed mode. bit 23-20 Unimplemented: Read as ‘0’  2015-2021 Microchip Technology Inc. DS60001320H-page 223 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-4: USBCSR3: USB CONTROL STATUS REGISTER 3 (CONTINUED) bit 19-16 ENDPOINT: Endpoint Registers Select bits 1111 = Reserved • • • 1000 = Reserved 0111 = Endpoint 7 • • • 0000 = Endpoint 0 These bits select which endpoint registers are accessed through addresses 3010-301F. bit 15-11 Unimplemented: Read as ‘0’ bit 10-0 RFRMNUM: Last Received Frame Number bits DS60001320H-page 224  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-5: Bit Range USBIE0CSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 0) Bit 31/23/15/7 U-0 31:24 23:16 15:8 7:0 Bit Bit 30/22/14/6 29/21/13/5 U-0 U-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0, HC R/W-0 R/W-0, HC — — — DISPING DTWREN DATATGGL R-0 — — — — R/W-0, HC R/W-0, HC R/W-0, HC R/C-0, HS SVCSETEND SVCRPR SENDSTALL SETUPEND R/W-0, HS R-0, HS DATAEND SENTSTALL NAKTMOUT STATPKT REQPKT ERROR SETUPPKT RXSTALL U-0 U-0 U-0 U-0 U-0 U-0 FLSHFIFO R-0 TXPKTRDY RXPKTRDY U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit -n = Value at POR HC = Hardware Cleared W = Writable bit ‘1’ = Bit is set HS = Hardware Set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 Unimplemented: Read as ‘0’ bit 27 DISPING: Disable Ping tokens control bit (Host mode) 1 = USB Module will not issue PING tokens in data and status phases of a Hi-Speed Control transfer 0 = Ping tokens are issued bit 26 DTWREN: Data Toggle Write Enable bit (Host mode) 1 = Enable the current state of the Endpoint 0 data toggle to be written. Automatically cleared. 0 = Disable data toggle write bit 25 DATATGGL: Data Toggle bit (Host mode) When read, this bit indicates the current state of the Endpoint 0 data toggle. If DTWREN = 1, this bit is writable with the desired setting. If DTWREN = 0, this bit is read-only. bit 24 FLSHFIFO: Flush FIFO Control bit 1 = Flush the next packet to be transmitted/read from the Endpoint 0 FIFO. The FIFO pointer is reset and the TXPKTRDY/RXPKTRDY bit is cleared. Automatically cleared when the operation completes. Should only be used when TXPKTRDY/RXPKTRDY = 1. 0 = No Flush operation bit 23 SVCSETEND: Clear SETUPEND Control bit (Device mode) 1 = Clear the SETUPEND bit in this register. This bit is automatically cleared. 0 = Do not clear NAKTMOUT: NAK Time-out Control bit (Host mode) 1 = Endpoint 0 is halted following the receipt of NAK responses for longer than the time set by the NAKLIM bits (USBICSR) 0 = Allow the endpoint to continue bit 22 SVCRPR: Serviced RXPKTRDY Clear Control bit (Device mode) 1 = Clear the RXPKTRDY bit in this register. This bit is automatically cleared. 0 = Do not clear STATPKT: Status Stage Transaction Control bit (Host mode) 1 = When set at the same time as the TXPKTRDY or REQPKT bit is set, performs a status stage transaction 0 = Do not perform a status stage transaction  2015-2021 Microchip Technology Inc. DS60001320H-page 225 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-5: bit 21 USBIE0CSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 0) (CONTINUED) SENDSTALL: Send Stall Control bit (Device mode) 1 = Terminate the current transaction and transmit a STALL handshake. This bit is automatically cleared. 0 = Do not send STALL handshake. REQPKT: IN transaction Request Control bit (Host mode) 1 = Request an IN transaction. This bit is cleared when the RXPKTRDY bit is set. 0 = Do not request an IN transaction bit 20 SETUPEND: Early Control Transaction End Status bit (Device mode) 1 = A control transaction ended before the DATAEND bit has been set. An interrupt will be generated and the FIFO flushed at this time. 0 = Normal operation This bit is cleared by writing a ‘1’ to the SVCSETEND bit in this register. ERROR: No Response Error Status bit (Host mode) 1 = Three attempts have been made to perform a transaction with no response from the peripheral. An interrupt is generated. 0 = Clear this flag. Software must write a ‘0’ to this bit to clear it. bit 19 DATAEND: End of Data Control bit (Device mode) The software sets this bit when: • Setting TXPKTRDY for the last data packet • Clearing RXPKTRDY after unloading the last data packet • Setting TXPKTRDY for a zero length data packet Hardware clears this bit. SETUPPKT: Send a SETUP token Control bit (Host mode) 1 = When set at the same time as the TXPKTRDY bit is set, the module sends a SETUP token instead of an OUT token for the transaction 0 = Normal OUT token operation Setting this bit also clears the Data Toggle. bit 18 SENTSTALL: STALL sent status bit (Device mode) 1 = STALL handshake has been transmitted 0 = Software clear of bit RXSTALL: STALL handshake received Status bit (Host mode) 1 = STALL handshake was received 0 = Software clear of bit bit 17 TXPKTRDY: TX Packet Ready Control bit 1 = Data packet has been loaded into the FIFO. It is cleared automatically. 0 = No data packet is ready for transmit bit 16 RXPKTRDY: RX Packet Ready Status bit 1 = Data packet has been received. Interrupt is generated (when enabled) when this bit is set. 0 = No data packet has been received This bit is cleared by setting the SVCRPR bit. bit 15-0 Unimplemented: Read as ‘0’ DS60001320H-page 226  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-6: Bit Range 31:24 23:16 15:8 7:0 USBIE0CSR2: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 2 (ENDPOINT 0) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 U-0 U-0 U-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 U-0 U-0 U-0 — — — SPEED Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — — — NAKLIM U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — Legend: R = Readable bit -n = Value at POR RXCNT W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-24 NAKLIM: Endpoint 0 NAK Limit bits The number of frames/microframes (Hi-Speed transfers) after which Endpoint 0 should time-out on receiving a stream of NAK responses. bit 23-22 SPEED: Operating Speed Control bits 11 = Low-Speed 10 = Full-Speed 01 = Hi-Speed 00 = Reserved bit 21-7 Unimplemented: Read as ‘0’ bit 6-0 RXCNT: Receive Count bits The number of received data bytes in the Endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid while RXPKTRDY is set.  2015-2021 Microchip Technology Inc. DS60001320H-page 227 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-7: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 USBIE0CSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3 (ENDPOINT 0) Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-x R-1 R-0 R-x R-x R-0 R-x R-x MPRXEN MPTXEN BIGEND HBRXEN HBTXEN U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set DYNFIFOS SOFTCONE UTMIDWID U-0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31 MPRXEN: Automatic Amalgamation Option bit 1 = Automatic amalgamation of bulk packets is done 0 = No automatic amalgamation bit 30 MPTXEN: Automatic Splitting Option bit 1 = Automatic splitting of bulk packets is done 0 = No automatic splitting bit 29 BIGEND: Byte Ordering Option bit 1 = Big Endian ordering 0 = Little Endian ordering bit 28 HBRXEN: High-bandwidth RX ISO Option bit 1 = High-bandwidth RX ISO endpoint support is selected 0 = No High-bandwidth RX ISO support bit 27 HBTXEN: High-bandwidth TX ISO Option bit 1 = High-bandwidth TX ISO endpoint support is selected 0 = No High-bandwidth TX ISO support bit 26 DYNFIFOS: Dynamic FIFO Sizing Option bit 1 = Dynamic FIFO sizing is supported 0 = No Dynamic FIFO sizing bit 25 SOFTCONE: Soft Connect/Disconnect Option bit 1 = Soft Connect/Disconnect is supported 0 = Soft Connect/Disconnect is not supported bit 24 UTMIDWID: UTMI+ Data Width Option bit Always ‘0’, indicating 8-bit UTMI+ data width bit 23-0 Unimplemented: Read as ‘0’ DS60001320H-page 228  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-8: Bit Range 31:24 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AUTOSET ISO — R/W-0, HS R/W-0, HC 23:16 INCOMPTX NAKTMOUT 15:8 7:0 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 MODE R/W-0 R/W-0 R/W-0 — DMAREQEN FRCDATTG DMAREQMD DATAWEN R/W-0, HS R/W-0 R/W-0 R/W-0, HS R/W-0 R/W-0, HC FLUSH UNDERRUN ERROR FIFONE TXPKTRDY R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MULT R/W-0 — DATATGGL R/W-0 SENTSTALL SENDSTALL RXSTALL SETUPPKT CLRDT R/W-0 TXMAXP R/W-0 R/W-0 TXMAXP Legend: R = Readable bit -n = Value at POR bit 31 USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 1-7) W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown AUTOSET: Auto Set Control bit 1 = TXPKTRDY will be automatically set when data of the maximum packet size (value in TXMAXP) is loaded into the TX FIFO. If a packet of less than the maximum packet size is loaded, then TXPKTRDY will have to be set manually. 0 = TXPKTRDY must be set manually for all packet sizes ISO: Isochronous TX Endpoint Enable bit (Device mode) 1 = Enables the endpoint for Isochronous transfers 0 = Disables the endpoint for Isochronous transfers and enables it for Bulk or Interrupt transfers. This bit only has an effect in Device mode. In Host mode, it always returns zero. MODE: Endpoint Direction Control bit 1 = Endpoint is TX 0 = Endpoint is RX This bit only has any effect where the same endpoint FIFO is used for both TX and RX transactions. DMAREQEN: Endpoint DMA Request Enable bit 1 = DMA requests are enabled for this endpoint 0 = DMA requests are disabled for this endpoint FRCDATTG: Force Endpoint Data Toggle Control bit 1 = Forces the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received. 0 = No forced behavior DMAREQMD: Endpoint DMA Request Mode Control bit 1 = DMA Request Mode 1 0 = DMA Request Mode 0 This bit must not be cleared either before or in the same cycle as the above DMAREQEN bit is cleared. DATAWEN: Data Toggle Write Enable bit (Host mode) 1 = Enable the current state of the TX Endpoint data toggle (DATATGGL) to be written 0 = Disables writing the DATATGGL bit DATATGGL: Data Toggle Control bit (Host mode) When read, this bit indicates the current state of the TX Endpoint data toggle. If DATAWEN = 1, this bit may be written with the required setting of the data toggle. If DATAWEN = 0, any value written to this bit is ignored.  2015-2021 Microchip Technology Inc. DS60001320H-page 229 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-8: bit 23 USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 1-7) (CONTINUED) INCOMPTX: Incomplete TX Status bit (Device mode) 1 = For high-bandwidth Isochronous endpoint, a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts 0 = Normal operation In anything other than isochronous transfers, this bit will always return 0. bit 22 bit 21 bit 20 NAKTMOUT: NAK Time-out status bit (Host mode) 1 = TX endpoint is halted following the receipt of NAK responses for longer than the NAKLIM setting 0 = Written by software to clear this bit CLRDT: Clear Data Toggle Control bit 1 = Resets the endpoint data toggle to 0 0 = Do not clear the data toggle SENTSTALL: STALL handshake transmission status bit (Device mode) 1 = STALL handshake is transmitted. The FIFO is flushed and the TXPKTRDY bit is cleared. 0 = Written by software to clear this bit RXSTALL: STALL receipt bit (Host mode) 1 = STALL handshake is received. Any DMA request in progress is stopped, the FIFO is completely flushed and the TXPKTRDY bit is cleared. 0 = Written by software to clear this bit SENDSTALL: STALL handshake transmission control bit (Device mode) 1 = Issue a STALL handshake to an IN token 0 = Terminate stall condition This bit has no effect when the endpoint is being used for Isochronous transfers. SETUPPKT: Definition bit (Host mode) 1 = When set at the same time as the TXPKTRDY bit is set, send a SETUP token instead of an OUT token for the transaction. This also clears the Data Toggle. bit 19 bit 18 bit 17 bit 16 0 = Normal OUT token for the transaction FLUSH: FIFO Flush control bit 1 = Flush the latest packet from the endpoint TX FIFO. The FIFO pointer is reset, TXPKTRDY is cleared and an interrupt is generated. 0 = Do not flush the FIFO UNDERRUN: Underrun status bit (Device mode) 1 = An IN token has been received when TXPKTRDY is not set. 0 = Written by software to clear this bit. ERROR: Handshake failure status bit (Host mode) 1 = Three attempts have been made to send a packet and no handshake packet has been received 0 = Written by software to clear this bit. FIFONE: FIFO Not Empty status bit 1 = There is at least 1 packet in the TX FIFO 0 = TX FIFO is empty TXPKTRDY: TX Packet Ready Control bit The software sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. This bit is also automatically cleared prior to loading a second packet into a double-buffered FIFO. DS60001320H-page 230  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-8: USBIENCSR0: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 0 (ENDPOINT 1-7) (CONTINUED) bit 15-11 MULT: Multiplier Control bits For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT+1 for the payload size. For Bulk endpoints, MULT can be up to 32 and defines the number of “USB” packets of the specified payload into which a single data packet placed in the FIFO should be split, prior to transfer. The data packet is required to be an exact multiple of the payload specified by TXMAXP. For Isochronous/Interrupts endpoints operating in Hi-Speed mode, MULT may be either 2 or 3 and specifies the maximum number of such transactions that can take place in a single microframe. bit 10-0 TXMAXP: Maximum TX Payload per transaction Control bits This field sets the maximum payload (in bytes) transmitted in a single transaction. The value is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in Full-Speed and Hi-Speed operations. TXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1.  2015-2021 Microchip Technology Inc. DS60001320H-page 231 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-9: USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1 (ENDPOINT 1-7) Bit Bit Range 31/23/15/7 R/W-0 31:24 15:8 7:0 Bit 29/21/13/5 R/W-0 R/W-0 ISO AUTOCLR AUTORQ R/W-0, HC 23:16 Bit 30/22/14/6 R/W-0, HS DMAREQEN R/W-0 SENTSTALL SENDSTALL CLRDT RXSTALL REQPKT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0, HC R-0 R/W-0 — — DISNYET PIDERR DMAREQMD R/W-0, HC DATATWEN DATATGGL R-0, HS R/W-0, HS DATAERR OVERRUN DERRNAKT ERROR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLUSH MULT R/W-0 INCOMPRX R-0, HS, HC R/W-0, HS FIFOFULL RXPKTRDY R/W-0 R/W-0 RXMAXP R/W-0 R/W-0 RXMAXP Legend: R = Readable bit -n = Value at POR HC = Hardware Cleared W = Writable bit ‘1’ = Bit is set HS = Hardware Set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31 AUTOCLR: RXPKTRDY Automatic Clear Control bit 1 = RXPKTRDY will be automatically cleared when a packet of RXMAXP bytes has been unloaded from the RX FIFO. When packets of less than the maximum packet size are unloaded, RXPKTRDY will have to be cleared manually. When using a DMA to unload the RX FIFO, data is read from the RX FIFO in 4-byte chunks regardless of the RXMAXP. 0 = No automatic clearing of RXPKTRDY This bit should not be set for high-bandwidth Isochronous endpoints. bit 30 ISO: Isochronous Endpoint Control bit (Device mode) 1 = Enable the RX endpoint for Isochronous transfers 0 = Enable the RX endpoint for Bulk/Interrupt transfers AUTORQ: Automatic Packet Request Control bit (Host mode) 1 = REQPKT will be automatically set when RXPKTRDY bit is cleared. 0 = No automatic packet request This bit is automatically cleared when a short packet is received. bit 29 DMAREQEN: DMA Request Enable Control bit 1 = Enable DMA requests for the RX endpoint. 0 = Disable DMA requests for the RX endpoint. bit 28 DISNYET: Disable NYET Handshakes Control/PID Error Status bit (Device mode) 1 = In Bulk/Interrupt transactions, disables the sending of NYET handshakes. All successfully received RX packets are ACKed including at the point at which the FIFO becomes full. 0 = Normal operation. In Bulk/Interrupt transactions, this bit only has any effect in Hi-Speed mode, in which mode it should be set for all Interrupt endpoints. PIDERR: PID Error Status bit (Host mode) 1 = In ISO transactions, this indicates a PID error in the received packet. 0 = No error bit 27 DMAREQMD: DMA Request Mode Selection bit 1 = DMA Request Mode 1 0 = DMA Request Mode 0 DS60001320H-page 232  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-9: USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1 (ENDPOINT 1-7) (CONTINUED) bit 26 DATATWEN: Data Toggle Write Enable Control bit (Host mode) 1 = DATATGGL can be written 0 = DATATGGL is not writable bit 25 DATATGGL: Data Toggle bit (Host mode) When read, this bit indicates the current state of the endpoint data toggle. If DATATWEN = 1, this bit may be written with the required setting of the data toggle. If DATATWEN = 0, any value written to this bit is ignored. bit 24 INCOMPRX: Incomplete Packet Status bit 1 = The packet in the RX FIFO during a high-bandwidth Isochronous/Interrupt transfer is incomplete because parts of the data were not received 0 = Written by then software to clear this bit In anything other than Isochronous transfer, this bit will always return 0. bit 23 CLRDT: Clear Data Toggle Control bit 1 = Reset the endpoint data toggle to 0 0 = Leave endpoint data toggle alone bit 22 SENTSTALL: STALL Handshake Status bit (Device mode) 1 = STALL handshake is transmitted 0 = Written by the software to clear this bit RXSTALL: STALL Handshake Receive Status bit (Host mode) 1 = A STALL handshake has been received. An interrupt is generated. 0 = Written by the software to clear this bit bit 21 SENDSTALL: STALL Handshake Control bit (Device mode) 1 = Issue a STALL handshake 0 = Terminate stall condition REQPKT: IN Transaction Request Control bit (Host mode) 1 = Request an IN transaction. 0 = No request This bit is cleared when RXPKTRDY is set. bit 20 FLUSH: Flush FIFO Control bit 1 = Flush the next packet to be read from the endpoint RX FIFO. The FIFO pointer is reset and the RXPKTRDY bit is cleared. This should only be used when RXPKTRDY is set. If the FIFO is doublebuffered, FLUSH may need to be set twice to completely clear the FIFO. 0 = Normal FIFO operation This bit is automatically cleared. bit 19 DATAERR: Data Packet Error Status bit (Device mode) 1 = The data packet has a CRC or bit-stuff error. 0 = No data error This bit is cleared when RXPKTRDY is cleared. This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. DERRNAKT: Data Error/NAK Time-out Status bit (Host mode) 1 = The data packet has a CRC or bit-stuff error. In Bulk mode, the RX endpoint is halted following the receipt of NAK responses for longer than the time set as the NAK limit. 0 = No data or NAK time-out error  2015-2021 Microchip Technology Inc. DS60001320H-page 233 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-9: bit 18 USBIENCSR1: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 1 (ENDPOINT 1-7) (CONTINUED) OVERRUN: Data Overrun Status bit (Device mode) 1 = An OUT packet cannot be loaded into the RX FIFO. 0 = Written by software to clear this bit This bit is only valid when the endpoint is operating in ISO mode. In Bulk mode, it always returns zero. ERROR: No Data Packet Received Status bit (Host mode) 1 = Three attempts have been made to receive a packet and no data packet has been received. An interrupt is generated. 0 = Written by the software to clear this bit. This bit is only valid when the RX endpoint is operating in Bulk or Interrupt mode. In ISO mode, it always returns zero. bit 17 FIFOFULL: FIFO Full Status bit 1 = No more packets can be loaded into the RX FIFO 0 = The RX FIFO has at least one free space bit 16 RXPKTRDY: Data Packet Reception Status bit 1 = A data packet has been received. An interrupt is generated. 0 = Written by software to clear this bit when the packet has been unloaded from the RX FIFO. bit 15-11 MULT: Multiplier Control bits For Isochronous/Interrupt endpoints or of packet splitting on Bulk endpoints, multiplies TXMAXP by MULT+1 for the payload size. For Bulk endpoints, MULT can be up to 32 and defines the number of “USB” packets of the specified payload into which a single data packet placed in the FIFO should be split, prior to transfer. The data packet is required to be an exact multiple of the payload specified by TXMAXP. For Isochronous/Interrupts endpoints operating in Hi-Speed mode, MULT may be either 2 or 3 and specifies the maximum number of such transactions that can take place in a single microframe. bit 10-0 RXMAXP: Maximum RX Payload Per Transaction Control bits This field sets the maximum payload (in bytes) transmitted in a single transaction. The value is subject to the constraints placed by the USB Specification on packet sizes for Bulk, Interrupt and Isochronous transfers in Full-Speed and Hi-Speed operations. RXMAXP must be set to an even number of bytes for proper interrupt generation in DMA Mode 1. Note: Transfer size greater than RxMaxP is handled by DMA Mode 1 only. DS60001320H-page 234  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-10: USBIENCSR2: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 2 (ENDPOINT 1-7) Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 7:0 R/W-0 R/W-0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0 R-0 TXINTERV R/W-0 R/W-0 R/W-0 SPEED U-0 U-0 — — R-0 R-0 R/W-0 R/W-0 PROTOCOL R-0 TEP R-0 R-0 R-0 RXCNT R-0 R-0 R-0 R-0 RXCNT Legend: R = Readable bit -n = Value at POR HC = Hardware Cleared W = Writable bit ‘1’ = Bit is set HS = Hardware Set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 TXINTERV: Endpoint TX Polling Interval/NAK Limit bits (Host mode) For Interrupt and Isochronous transfers, this field defines the polling interval for the endpoint. For Bulk endpoints, this field sets the number of frames/microframes after which the endpoint should time out on receiving a stream of NAK responses. The following table describes the valid values and interpretation for these bits: Transfer Type Speed Valid Values (m) Low/Full 0x01 to 0xFF Polling interval is ‘m’ frames. High 0x01 to 0x10 Polling interval is 2(m-1) frames. Isochronous Full or High 0x01 to 0x10 Polling interval is 2(m-1) frames/microframes. Bulk Full or High 0x02 to 0x10 NAK limit is 2(m-1) frames/microframes. A value of ‘0’ or ‘1’ disables the NAK time-out function. Interrupt Interpretation bit 23-22 SPEED: TX Endpoint Operating Speed Control bits (Host mode) 11 = Low-Speed 10 = Full-Speed 01 = Hi-Speed 00 = Reserved bit 21-20 PROTOCOL: TX Endpoint Protocol Control bits 11 = Interrupt 10 = Bulk 01 = Isochronous 00 = Control bit 19-16 TEP: TX Target Endpoint Number bits This value is the endpoint number contained in the TX endpoint descriptor returned to the USB module during device enumeration. bit 15-14 Unimplemented: Read as ‘0’ bit 13-0 RXCNT: Receive Count bits The number of received data bytes in the endpoint RX FIFO. The value returned changes as the contents of the FIFO change and is only valid while RXPKTRDY is set.  2015-2021 Microchip Technology Inc. DS60001320H-page 235 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-11: USBIENCSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3 (ENDPOINT 1-7) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-x R-x R-x R-x R-x R-x R-x R-x RXFIFOSZ TXFIFOSZ U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXINTERV R/W-0 R/W-0 R/W-0 SPEED Legend: R = Readable bit -n = Value at POR R/W-0 R/W-0 PROTOCOL W = Writable bit ‘1’ = Bit is set TEP U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 RXFIFOSZ: Receive FIFO Size bits 1111 = Reserved 1110 = Reserved 1101 = 8192 bytes 1100 = 4096 bytes • • • 0011 = 8 bytes 0010 = Reserved 0001 = Reserved 0000 = Reserved or endpoint has not been configured This register only has this interpretation when dynamic sizing is not selected. It is not valid where dynamic FIFO sizing is used. bit 27-24 TXFIFOSZ: Transmit FIFO Size bits 1111 = Reserved 1110 = Reserved 1101 = 8192 bytes 1100 = 4096 bytes • • • 0011 = 8 bytes 0010 = Reserved 0001 = Reserved 0000 = Reserved or endpoint has not been configured This register only has this interpretation when dynamic sizing is not selected. It is not valid where dynamic FIFO sizing is used. bit 23-16 Unimplemented: Read as ‘0’ DS60001320H-page 236  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-11: USBIENCSR3: USB INDEXED ENDPOINT CONTROL STATUS REGISTER 3 (ENDPOINT 1-7) (CONTINUED) bit 15-8 RXINTERV: Endpoint RX Polling Interval/NAK Limit bits For Interrupt and Isochronous transfers, this field defines the polling interval for the endpoint. For Bulk endpoints, this field sets the number of frames/microframes after which the endpoint should time out on receiving a stream of NAK responses. The following table describes the valid values and meaning for this field: Transfer Type Speed Valid Values (m) Low/Full 0x01 to 0xFF Polling interval is ‘m’ frames. High 0x01 to 0x10 Polling interval is 2(m-1) frames. Isochronous Full or High 0x01 to 0x10 Polling interval is 2(m-1) frames/microframes. Bulk Full or High 0x02 to 0x10 NAK limit is 2(m-1) frames/microframes. A value of ‘0’ or ‘1’ disables the NAK time-out function. Interrupt bit 7-6 SPEED: RX Endpoint Operating Speed Control bits 11 = Low-Speed 10 = Full-Speed 01 = Hi-Speed 00 = Reserved bit 5-4 PROTOCOL: RX Endpoint Protocol Control bits 11 = Interrupt 10 = Bulk 01 = Isochronous 00 = Control bit 3-0 TEP: RX Target Endpoint Number bits Interpretation This value is the endpoint number contained in the TX endpoint descriptor returned to the USB module during device enumeration.  2015-2021 Microchip Technology Inc. DS60001320H-page 237 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-12: USBFIFOx: USB FIFO DATA REGISTER ‘x’ (‘x’ = 0-7) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA R/W-0 R/W-0 R/W-0 R/W-0 DATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATA Legend: R = Readable bit -n = Value at POR bit 31-0 R/W-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DATA: USB Transmit/Receive FIFO Data bits Writes to this register loads data into the TxFIFO for the corresponding endpoint. Reading from this register unloads data from the RxFIFO for the corresponding endpoint. Transfers may be 8-bit, 16-bit or 32-bit as required, and any combination of access is allowed provided the data accessed is contiguous. However, all transfers associated with one packet must be of the same width so that data is consistently byte-, word- or double-word aligned. The last transfer may contain fewer bytes than the previous transfers in order to complete an odd-byte or odd-word transfer. DS60001320H-page 238  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — RXDPB U-0 U-0 U-0 R/W-0 — — — TXDPB U-0 U-0 U-0 U-0 RXFIFOSZ R/W-0 R/W-0 TXFIFOSZ U-0 U-0 R/W-0 R/W-0 RXEDMA — — — — — — TXEDMA R-1 R-0 R-0 R-0 R-0 R-0 R/W-0, HC BDEV FSDEV LSDEV VBUS HOSTMODE HOSTREQ R/W-0 SESSION Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28 RXDPB: RX Endpoint Double-packet Buffering Control bit 1 = Double-packet buffer is supported. This doubles the size set in RXFIFOSZ. 0 = Double-packet buffer is not supported bit 27-24 RXFIFOSZ: RX Endpoint FIFO Packet Size bits The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission) 1111 = Reserved • • • 1010 = Reserved 1001 = 4096 bytes 1000 = 2048 bytes 0111 = 1024 bytes 0110 = 512 bytes 0101 = 256 bytes 0100 = 128 bytes 0011 = 64 bytes 0010 = 32 bytes 0001 = 16 bytes 0000 = 8 bytes bit 23-21 Unimplemented: Read as ‘0’ bit 20 TXDPB: TX Endpoint Double-packet Buffering Control bit 1 = Double-packet buffer is supported. This doubles the size set in TXFIFOSZ. 0 = Double-packet buffer is not supported  2015-2021 Microchip Technology Inc. DS60001320H-page 239 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER (CONTINUED) bit 19-16 TXFIFOSZ: TX Endpoint FIFO packet size bits The maximum packet size to allowed for (before any splitting within the FIFO of Bulk/High-Bandwidth packets prior to transmission) 1111 = Reserved • • • 1010 = Reserved 1001 = 4096 bytes 1000 = 2048 bytes 0111 = 1024 bytes 0110 = 512 bytes 0101 = 256 bytes 0100 = 128 bytes 0011 = 64 bytes 0010 = 32 bytes 0001 = 16 bytes 0000 = 8 bytes bit 15-10 Unimplemented: Read as ‘0’ bit 9 TXEDMA: TX Endpoint DMA Assertion Control bit 1 = DMA_REQ signal for all IN endpoints will be deasserted when MAXP-8 bytes have been written to an endpoint. This is Early mode. 0 = DMA_REQ signal for all IN endpoints will be deasserted when MAXP bytes have been written to an endpoint. This is Late mode. bit 8 RXEDMA: RX Endpoint DMA Assertion Control bit 1 = DMA_REQ signal for all OUT endpoints will be deasserted when MAXP-8 bytes have been written to an endpoint. This is Early mode. 0 = DMA_REQ signal for all OUT endpoints will be deasserted when MAXP bytes have been written to an endpoint. This is Late mode. bit 7 BDEV: USB Device Type bit 1 = USB is operating as a ‘B’ device 0 = USB is operating as an ‘A’ device bit 6 FSDEV: Full-Speed/Hi-Speed device detection bit (Host mode) 1 = A Full-Speed or Hi-Speed device has been detected being connected to the port 0 = No Full-Speed or Hi-Speed device detected bit 5 LSDEV: Low-Speed Device Detection bit (Host mode) 1 = A Low-Speed device has been detected being connected to the port 0 = No Low-Speed device detected bit 4-3 VBUS: VBUS Level Detection bits 11 = Above VBUS Valid 10 = Above AValid, below VBUS Valid 01 = Above Session End, below AValid 00 = Below Session End bit 2 HOSTMODE: Host Mode bit 1 = USB module is acting as a Host 0 = USB module is not acting as a Host bit 1 HOSTREQ: Host Request Control bit ‘B’ device only: 1 = USB module initiates the Host Negotiation when Suspend mode is entered. This bit is cleared when Host Negotiation is completed. 0 = Host Negotiation is not taking place DS60001320H-page 240  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-13: USBOTG: USB OTG CONTROL/STATUS REGISTER (CONTINUED) bit 0 SESSION: Active Session Control/Status bit ‘A’ device: 1 = Start a session 0 = End a session ‘B’ device: 1 = (Read) Session has started or is in progress, (Write) Initiate the Session Request Protocol 0 = When USB module is in Suspend mode, clearing this bit will cause a software disconnect Clearing this bit when the USB module is not suspended will result in undefined behavior.  2015-2021 Microchip Technology Inc. DS60001320H-page 241 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-14: USBFIFOA: USB FIFO ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RXFIFOAD R/W-0 R/W-0 RXFIFOAD U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXFIFOAD R/W-0 R/W-0 R/W-0 TXFIFOAD Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-16 RXFIFOAD: Receive Endpoint FIFO Address bits Start address of the endpoint FIFO in units of 8 bytes as follows: 1111111111111 = 0xFFF8 • • • 0000000000010 = 0x0010 0000000000001 = 0x0008 0000000000000 = 0x0000 bit 15-13 Unimplemented: Read as ‘0’ bit 12-0 TXFIFOAD: Transmit Endpoint FIFO Address bits Start address of the endpoint FIFO in units of 8 bytes as follows: 1111111111111 = 0xFFF8 • • • 0000000000010 = 0x0010 0000000000001 = 0x0008 0000000000000 = 0x0000 DS60001320H-page 242  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-15: USBHWVER: USB HARDWARE VERSION REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R-0 R-0 R-0 R-1 R-0 R-0 R-0 RC R-0 VERMAJOR R-0 R-0 R-0 VERMINOR R-0 R-0 R-0 R-0 VERMINOR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 RC: Release Candidate bit 1 = USB module was created using a release candidate 0 = USB module was created using a full release bit 14-10 VERMAJOR: USB Module Major Version number bits This read-only number is the Major version number for the USB module. bit 9-0 VERMINOR: USB Module Minor Version number bits This read-only number is the Minor version number for the USB module.  2015-2021 Microchip Technology Inc. DS60001320H-page 243 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-16: USBINFO: USB INFORMATION REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 VPLEN R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 WTCON R-1 R-0 R-0 WTID R-0 R-1 DMACHANS R-0 R-1 R-1 RXENDPTS Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set R-1 R-0 R-0 RAMBITS R-1 R-0 R-1 R-1 R-1 TXENDPTS U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 VPLEN: VBUS pulsing charge length bits Sets the duration of the VBUS pulsing charge in units of 546.1 µs. (The default setting corresponds to 32.77 ms.) bit 23-20 WTCON: Connect/Disconnect filter control bits Sets the wait to be applied to allow for the connect/disconnect filter in units of 533.3 ns. The default setting corresponds to 2.667 µs. bit 19-6 WTID: ID delay valid control bits Sets the delay to be applied from IDPULLUP being asserted to IDDIG being considered valid in units of 4.369ms. The default setting corresponds to 52.43ms. bit 15-12 DMACHANS: DMA Channels bits These read-only bits provide the number of DMA channels in the USB module. For the PIC32MZ EF family, this number is 8. bit 11-8 RAMBITS: RAM address bus width bits These read-only bits provide the width of the RAM address bus. For the PIC32MZ EF family, this number is 12. bit 7-4 RXENDPTS: Included RX Endpoints bits This read-only register gives the number of RX endpoints in the design. For the PIC32MZ EF family, this number is 7. bit 3-0 TXENDPTS: Included TX Endpoints bits These read-only bits provide the number of TX endpoints in the design. For the PIC32MZ EF family, this number is 7. DS60001320H-page 244  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-17: USBEOFRST: USB END-OF-FRAME/SOFT RESET CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — NRSTX NRST R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R.W-0 R/W-1 R/W-0 R.W-1 R/W-1 R/W-1 R.W-0 R/W-0 R/W-0 LSEOF R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 FSEOF R/W-1 R/W-0 Legend: R = Readable bit -n = Value at POR R/W-0 R/W-0 R/W-0 HSEOF W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-26 Unimplemented: Read as ‘0’ bit 25 NRSTX: Reset of XCLK Domain bit 1 = Reset the XCLK domain, which is clock recovered from the received data by the PHY 0 = Normal operation bit 24 NRST: Reset of CLK Domain bit 1 = Reset the CLK domain, which is clock recovered from the peripheral bus 0 = Normal operation bit 23-16 LSEOF: Low-Speed EOF bits These bits set the Low-Speed transaction in units of 1.067 µs (default setting is 121.6 µs) prior to the EOF to stop new transactions from beginning. bit 15-8 FSEOF: Full-Speed EOF bits These bits set the Full-Speed transaction in units of 533.3 µs (default setting is 63.46 µs) prior to the EOF to stop new transactions from beginning. bit 7-0 HSEOF: Hi-Speed EOF bits These bits set the Hi-Speed transaction in units of 133.3 µs (default setting is 17.07µs) prior to the EOF to stop new transactions from beginning.  2015-2021 Microchip Technology Inc. DS60001320H-page 245 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-18: USBExTXA: USB ENDPOINT ‘x’ TRANSMIT ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — R/W-0 TXHUBPRT R/W-0 R/W-0 R/W-0 MULTTRAN R/W-0 TXHUBADD U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — Legend: R = Readable bit -n = Value at POR TXFADDR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31 Unimplemented: Read as ‘0’ bit 30-24 TXHUBPRT: TX Hub Port bits (Host mode) When a Low-Speed or Full-Speed device is connected to this endpoint through a Hi-Speed USB 2.0 hub, this field records the port number of that USB 2.0 hub. bit 23 MULTTRAN: TX Hub Multiple Translators bit (Host mode) 1 = The USB 2.0 hub has multiple transaction translators 0 = The USB 2.0 hub has a single transaction translator bit 22-16 TXHUBADD: TX Hub Address bits (Host mode) When a Low-Speed or Full-Speed device is connected to this endpoint through a Hi-Speed USB 2.0 hub, these bits record the address of the USB 2.0 hub. bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 TXFADDR: TX Functional Address bits (Host mode) Specifies the address for the target function that is be accessed through the associated endpoint. It needs to be defined for each TX endpoint that is used. DS60001320H-page 246  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-19: USBExRXA: USB ENDPOINT ‘x’ RECEIVE ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — R/W-0 RXHUBPRT R/W-0 R/W-0 R/W-0 MULTTRAN R/W-0 RXHUBADD U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — Legend: R = Readable bit -n = Value at POR RXFADDR HC = Hardware Cleared W = Writable bit ‘1’ = Bit is set HS = Hardware Set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31 Unimplemented: Read as ‘0’ bit 30-24 RXHUBPRT: RX Hub Port bits (Host mode) When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, this field records the port number of that USB 2.0 hub. bit 23 MULTTRAN: RX Hub Multiple Translators bit (Host mode) 1 = The USB 2.0 hub has multiple transaction translators 0 = The USB 2.0 hub has a single transaction translator bit 22-16 TXHUBADD: RX Hub Address bits (Host mode) When a Low-Speed or Full-Speed device is connected to this endpoint via a Hi-Speed USB 2.0 hub, these bits record the address of the USB 2.0 hub. bit 15-7 Unimplemented: Read as ‘0’ bit 6-0 RXFADDR: RX Functional Address bits (Host mode) Specifies the address for the target function that is be accessed through the associated endpoint. It needs to be defined for each RX endpoint that is used.  2015-2021 Microchip Technology Inc. DS60001320H-page 247 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-20: USBDMAINT: USB DMA INTERRUPT REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS DMA8IF DMA7IF DMA6IF DMA5IF DMA4IF DMA3IF DMA2IF DMA1IF Legend: R = Readable bit -n = Value at POR bit 31-8 bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ DMAxIF: DMA Channel ‘x’ Interrupt bit 1 = The DMA channel has an interrupt event 0 = No interrupt event All bits are cleared on a read of the register. DS60001320H-page 248  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-21: USBDMAxC: USB DMA CHANNEL ‘x’ CONTROL REGISTER (‘x’ = 1-8) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 DMABRSTM — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAIE DMAMODE DMADIR DMAEN DMAEP Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set DMAERR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-11 Unimplemented: Read as ‘0’ bit 10-9 DMABRSTM: DMA Burst Mode Selection bit 11 = Burst Mode 3: INCR16, INCR8, INCR4 or unspecified length 10 = Burst Mode 2: INCR8, INCR4 or unspecified length 01 = Burst Mode 1: INCR4 or unspecified length 00 = Burst Mode 0: Bursts of unspecified length bit 8 DMAERR: Bus Error bit 1 = A bus error has been observed on the input 0 = The software writes this to clear the error bit 7-4 DMAEP: DMA Endpoint Assignment bits These bits hold the endpoint that the DMA channel is assigned to. Valid values are 0-7. bit 3 DMAIE: DMA Interrupt Enable bit 1 = Interrupt is enabled for this channel 0 = Interrupt is disabled for this channel bit 2 DMAMODE: DMA Transfer Mode bit 1 = DMA Mode1 Transfers 0 = DMA Mode0 Transfers bit 1 DMADIR: DMA Transfer Direction bit 1 = DMA Read (TX endpoint) 0 = DMA Write (RX endpoint) bit 0 DMAEN: DMA Enable bit 1 = Enable the DMA transfer and start the transfer 0 = Disable the DMA transfer  2015-2021 Microchip Technology Inc. DS60001320H-page 249 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-22: USBDMAxA: USB DMA CHANNEL ‘x’ MEMORY ADDRESS REGISTER (‘x’ = 1-8) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 DMAADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMAADDR Legend: R = Readable bit -n = Value at POR bit 31-0 Bit 28/20/12/4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DMAADDR: DMA Memory Address bits This register identifies the current memory address of the corresponding DMA channel. The initial memory address written to this register during initialization must have a value such that its modulo 4 value is equal to ‘0’. The lower two bits of this register are read only and cannot be set by software. As the DMA transfer progresses, the memory address will increment as bytes are transferred. REGISTER 11-23: USBDMAxN: USB DMA CHANNEL ‘x’ COUNT REGISTER (‘X’ = 1-8) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMACOUNT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMACOUNT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMACOUNT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DMACOUNT Legend: R = Readable bit -n = Value at POR bit 31-0 Bit 28/20/12/4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DMACOUNT: DMA Transfer Count bits This register identifies the current DMA count of the transfer. Software will set the initial count of the transfer which identifies the entire transfer length. As the count progresses this count is decremented as bytes are transferred. DS60001320H-page 250  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-24: USBExRPC: USB ENDPOINT ‘x’ REQUEST PACKET COUNT REGISTER (HOST MODE ONLY) (‘x’ = 1-7) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RQPKTCNT R/W-0 R/W-0 RQPKTCNT Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 RQPKTCNT: Request Packet Count bits Sets the number of packets of size MAXP that are to be transferred in a block transfer. This register is only available in Host mode when AUTOREQ is set. REGISTER 11-25: USBDPBFD: USB DOUBLE PACKET BUFFER DISABLE REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 EP7TXD EP6TXD EP5TXD EP4TXD EP3TXD EP2TXD EP1TXD — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 EP7RXD EP6RXD EP5RXD EP4RXD EP3RXD EP2RXD EP1RXD — Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0” bit 23-17 EP7TXD:EP1TXD: TX Endpoint ‘x’ Double Packet Buffer Disable bits 1 = TX double packet buffering is disabled for endpoint ‘x’ 0 = TX double packet buffering is enabled for endpoint ‘x’ bit 16-8 Unimplemented: Read as ‘0’ bit 7-1 EP7RXD:EP1RXD: RX Endpoint ‘x’ Double Packet Buffer Disable bits 1 = RX double packet buffering is disabled for endpoint ‘x’ 0 = RX double packet buffering is enabled for endpoint ‘x’ bit 0 Unimplemented: Read as ‘0’  2015-2021 Microchip Technology Inc. DS60001320H-page 251 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-26: USBTMCON1: USB TIMING CONTROL REGISTER 1 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 THHSRTN R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 THHSRTN R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 TUCH R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 TUCH Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 THHSRTN:: Hi-Speed Resume Signaling Delay bits These bits set the delay from the end of Hi-Speed resume signaling (acting as a Host) to enable the UTM normal operating mode. bit 15-0 TUCH: Chirp Time-out bits These bits set the chirp time-out. This number, when multiplied by 4, represents the number of USB module clock cycles before the time-out occurs. Note: Use of this register will allow the Hi-Speed time-out to be set to values that are greater than the maximum specified in the USB 2.0 specification, making the USB module non-compliant. REGISTER 11-27: USBTMCON2: USB TIMING CONTROL REGISTER 2 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set THBST U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as ‘0’ bit 3-0 THBST: High Speed Time-out Adder bits These bits represent the value to be added to the minimum high speed time-out period of 736 bit times. The time-out period can be increased in increments of 64 Hi-Speed bit times (133 ns). Note: Use of this register will allow the Hi-Speed time-out to be set to values that are greater than the maximum specified in the USB 2.0 specification, making the USB module non-compliant. DS60001320H-page 252  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-28: USBLPMR1: USB LINK POWER MANAGEMENT CONTROL  REGISTER 1 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 — — U-0 U-0 U-0 R/W-0 — — — LPMNAK R-0 R-0 R-0 R-0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 R/W-0 R/W-0 R/W-0 LPMERRIE LPMRESIE LPMACKIE ENDPOINT R-0 R-0 R-0 R-0 HIRD Legend: R = Readable bit -n = Value at POR HC = Hardware Cleared W = Writable bit ‘1’ = Bit is set R/W-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 LPMNYIE LPMSTIE LPMTOIE R/W-0 LPMEN R/W-0, HC R/W-0, HC LPMRES LPMXMT U-0 U-0 U-0 R-0 — — — RMTWAK R-0 R-0 R-0 R-0 LNKSTATE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as ‘0’ bit 29 LPMERRIE: LPM Error Interrupt Enable bit 1 = LPMERR interrupt is enabled 0 = LPMERR interrupt is disabled bit 28 LPMRESIE: LPM Resume Interrupt Enable bit 1 = LPMRES interrupt is enabled 0 = LPMRES interrupt is disabled bit 27 LPMACKIE: LPM Acknowledge Interrupt Enable bit 1 = Enable the LPMACK Interrupt 0 = Disable the LPMACK Interrupt bit 26 LPMNYIE: LPM NYET Interrupt Enable bit 1 = Enable the LPMNYET Interrupt 0 = Disable the LPMNYET Interrupt bit 25 LPMSTIE: LPM STALL Interrupt Enable bit 1 = Enable the LPMST Interrupt 0 = Disable the LPMST Interrupt bit 24 LPMTOIE: LPM Time-out Interrupt Enable bit 1 = Enable the LPMTO Interrupt 0 = Disable the LPMTO Interrupt bit 23-21 Unimplemented: Read as ‘0’ bit 20 LPMNAK: LPM-only Transaction Setting bit 1 = All endpoints will respond to all transactions other than a LPM transaction with a NAK 0 = Normal transaction operation Setting this bit to ‘1’ will only take effect after the USB module as been LPM suspended. bit 19-18 LPMEN: LPM Enable bits (Device mode) 11 = LPM Extended transactions are supported 10 = LPM and Extended transactions are not supported 01 = LPM mode is not supported but Extended transactions are supported 00 = LPM Extended transactions are supported bit 17 LPMRES: LPM Resume bit 1 = Initiate resume (remote wake-up). Resume signaling is asserted for 50 µs. 0 = No resume operation This bit is self-clearing.  2015-2021 Microchip Technology Inc. DS60001320H-page 253 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-28: USBLPMR1: USB LINK POWER MANAGEMENT CONTROL  REGISTER 1 (CONTINUED) bit 16 LPMXMT: LPM Transition to the L1 State bit When in Device mode: 1 = USB module will transition to the L1 state upon the receipt of the next LPM transaction. LPMEN must be set to ‘0b11. Both LPMXMT and LPMEN must be set in the same cycle. 0 = Maintain current state When LPMXMT and LPMEN are set, the USB module can respond in the following ways: • If no data is pending (all TX FIFOs are empty), the USB module will respond with an ACK. The bit will self clear and a software interrupt will be generated. • If data is pending (data resides in at least one TX FIFO), the USB module will respond with a NYET. In this case, the bit will not self clear however a software interrupt will be generated. When in Host mode: 1 = USB module will transmit an LPM transaction. This bit is self clearing, and will be immediately cleared upon receipt of any Token or three time-outs have occurred. 0 = Maintain current state bit 15-12 ENDPOINT: LPM Token Packet Endpoint bits This is the endpoint in the token packet of the LPM transaction. bit 11-9 Unimplemented: Read as ‘0’ bit 8 RMTWAK: Remote Wake-up Enable bit This bit is applied on a temporary basis only and is only applied to the current suspend state. 1 = Remote wake-up is enabled 0 = Remote wake-up is disabled bit 7-4 HIRD: Host Initiated Resume Duration bits The minimum time the host will drive resume on the bus. The value in this register corresponds to an actual resume time of: bit 3-0 LNKSTATE: Link State bits This value is provided by the host to the peripheral to indicate what state the peripheral must transition to after the receipt and acceptance of a LPM transaction. The only valid value for this register is ‘1’ for Sleep State (L1). All other values are reserved. Resume Time = 50 µs + HIRD * 75 µs. The resulting range is 50 µs to 1200 µs. DS60001320H-page 254  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-29: USBLPMR2: USB LINK POWER MANAGEMENT CONTROL REGISTER 2 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R-0 R-0, HS — — — LPMFADDR Legend: R = Readable bit -n = Value at POR LPMERRIF LPMRESIF HS = Hardware Set W = Writable bit ‘1’ = Bit is set R-0, HS R-0, HS R-0, HS R-0, HS LPMNCIF LPMACKIF LPMNYIF LPMSTIF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as ‘0’ bit 14-8 LPMFADDR: LPM Payload Function Address bits These bits contain the address of the LPM payload function. bit 7-6 Unimplemented: Read as ‘0’ bit 5 LPMERRIF: LPM Error Interrupt Flag bit (Device mode) 1 = An LPM transaction was received that had a LINKSTATE field that is not supported. The response will be a STALL. 0 = No error condition bit 4 LPMRESIF: LPM Resume Interrupt Flag bit 1 = The USB module has resumed (for any reason) 0 = No Resume condition bit 3 LPMNCIF: LPM NC Interrupt Flag bit When in Device mode: 1 = The USB module received a LPM transaction and responded with a NYET due to data pending in the RX FIFOs. 0 = No NC interrupt condition When in Host mode: 1 = A LPM transaction is transmitted and has failed to complete. The transaction will have failed because a timeout occurred or there were bit errors in the response for three attempts. 0 = No NC interrupt condition bit 2 LPMACKIF: LPM ACK Interrupt Flag bit When in Device mode: 1 = A LPM transaction was received and the USB Module responded with an ACK 0 = No ACK interrupt condition When in Host mode: 1 = The LPM transaction is transmitted and the device responds with an ACK 0 = No ACK interrupt condition bit 1 LPMNYIF: LPM NYET Interrupt Flag bit When in Device mode: 1 = A LPM transaction is received and the USB Module responded with a NYET 0 = No NYET interrupt flag When in Host mode: 1 = A LPM transaction is transmitted and the device responded with an NYET 0 = No NYET interrupt flag  2015-2021 Microchip Technology Inc. DS60001320H-page 255 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-29: USBLPMR2: USB LINK POWER MANAGEMENT CONTROL REGISTER 2 bit 0 LPMSTIF: LPM STALL Interrupt Flag bit When in Device mode: 1 = A LPM transaction was received and the USB Module responded with a STALL 0 = No Stall condition When in Host mode: 1 = A LPM transaction was transmitted and the device responded with a STALL 0 = No Stall condition DS60001320H-page 256  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-30: USBCRCON: USB CLOCK/RESET CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 R-0, HS, HC R-0, HS, HC R/W-1, HS — — — — — USBIF USBRF USBWKUP U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — r-1 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — USB IDOVEN USB IDVAL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PHYIDEN VBUS MONEN ASVAL MONEN BSVAL MONEN SEND MONEN USBIE USBRIE USB WKUPEN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-27 Unimplemented: Read as ‘0’ bit 26 USBIF: USB General Interrupt Flag bit 1 = An event on the USB Bus has occurred 0 = No interrupt from USB module or interrupts have not been enabled bit 25 USBRF: USB Resume Flag bit 1 = Resume from Suspend state. Device wake-up activity can be started. 0 = No Resume activity detected during Suspend, or not in Suspend state bit 24 USBWK: USB Activity Status bit 1 = Connect, disconnect, or other activity on USB detected since last cleared 0 = No activity detected on USB Note: This bit should be cleared just prior to entering sleep, but it should be checked that no activity has already occurred on USB before actually entering sleep. bit 23-14 Unimplemented: Read as ‘0’ bit 15 Reserved: Read as ‘1’ bit 14-10 Unimplemented: Read as ‘0’ bit 9 USBIDOVEN: USB ID Override Enable bit 1 = Enable use of USBIDVAL bit 0 = Disable use of USBIDVAL and instead use the PHY value bit 8 USBIDVAL: USB ID Value bit 1 = ID override value is 1 0 = ID override value is 0 bit 7 PHYIDEN: PHY ID Monitoring Enable bit 1 = Enable monitoring of the ID bit from the USB PHY 0 = Disable monitoring of the ID bit from the USB PHY bit 6 VBUSMONEN: VBUS Monitoring for OTG Enable bit 1 = Enable monitoring for VBUS in VBUS Valid range (between 4.4V and 4.75V) 0 = Disable monitoring for VBUS in VBUS Valid range bit 5 ASVALMONEN: A-Device VBUS Monitoring for OTG Enable bit 1 = Enable monitoring for VBUS in Session Valid range for A-device (between 0.8V and 2.0V) 0 = Disable monitoring for VBUS in Session Valid range for A-device bit 4 BSVALMONEN: B-Device VBUS Monitoring for OTG Enable bit 1 = Enable monitoring for VBUS in Session Valid range for B-device (between 0.8V and 4.0V) 0 = Disable monitoring for VBUS in Session Valid range for B-device  2015-2021 Microchip Technology Inc. DS60001320H-page 257 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 11-30: USBCRCON: USB CLOCK/RESET CONTROL REGISTER (CONTINUED) bit 3 SENDMONEN: Session End VBUS Monitoring for OTG Enable bit 1 = Enable monitoring for VBUS in Session End range (between 0.2V and 0.8V) 0 = Disable monitoring for VBUS in Session End range bit 2 USBIE: USB General Interrupt Enable bit 1 = Enables general interrupt from USB module 0 = Disables general interrupt from USB module bit 1 USBRIE: USB Resume Interrupt Enable bit 1 = Enable remote resume from suspend Interrupt 0 = Disable interrupt to a Remote Devices USB resume signaling bit 0 USBWKUPEN: USB Activity Detection Interrupt Enable bit 1 = Enable interrupt for detection of activity on USB bus in Sleep mode 0 = Disable interrupt for detection of activity on USB bus in Sleep mode DS60001320H-page 258  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 12.0 I/O PORTS Note: Some of the key features of the I/O ports are: • Individual output pin open-drain enable/disable • Individual input pin weak pull-up and pull-down • Monitor selective inputs and generate interrupt when change in pin state is detected • Operation during Sleep and Idle modes • Fast bit manipulation using CLR, SET and INV registers Figure 12-1 illustrates a block diagram of a typical multiplexed I/O port. This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “I/O Ports” (DS60001120) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). General purpose I/O pins are the simplest of peripherals. They allow the PIC32MZ EF family device to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE Peripheral Module PIO Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data Port Control RD ODC PBCLK4 Data Bus D PBCLK4 Q ODC CK EN Q WR ODC 1 RD TRIS 0 0 I/O Cell 1 D Q 1 TRIS CK EN Q WR TRIS 0 Output Multiplexers D Q I/O Pin LAT CK EN Q WR LAT WR PORT RD LAT 1 RD PORT 0 Sleep Q Q D CK Q Q D CK PBCLK4 Synchronization Peripheral Input Legend: Note: R Peripheral Input Buffer R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details. This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here.  2015-2021 Microchip Technology Inc. DS60001320H-page 259 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 12.1 Parallel I/O (PIO) Ports All port pins have up to 14 registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins write the latch. 12.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORTx, LATx, and TRISx registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired 5V-tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. Refer to the pin name tables (Table 2 through Table 6) for the available pins and their functionality. 12.1.2 CONFIGURING ANALOG AND DIGITAL PORT PINS The ANSELx register controls the operation of the analog port pins. The port pins that are to function as analog inputs must have their corresponding ANSEL and TRIS bits set. In order to use port pins for I/O functionality with digital modules, such as Timers, UARTs, etc., the corresponding ANSELx bit must be cleared. The ANSELx register has a default value of 0xFFFF; therefore, all pins that share analog functions are analog (not digital) by default. If the TRIS bit is cleared (output) while the ANSELx bit is set, the digital output level (VOH or VOL) is converted by an analog peripheral, such as the ADC module or Comparator module. When the PORT register is read, all pins configured as analog input channels are read as cleared (a low level). Pins configured as digital inputs do not convert an analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. DS60001320H-page 260 12.1.3 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be an NOP. 12.1.4 INPUT CHANGE NOTIFICATION The input change notification function of the I/O ports allows the PIC32MZ EF devices to generate interrupt requests to the processor in response to a change-ofstate on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Every I/O port pin can be selected (enabled) for generating an interrupt request on a change-of-state. Seven control registers are associated with the CN functionality of each I/O port. The CNENx/CNNEx registers contain the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. CNENx enables a mismatch CN interrupt condition when the EDGEDETECT bit (CNCONx) is not set. When the EDGEDETECT bit is set, CNNEx controls the negative edge while CNENx controls the positive. The CNSTATx/CNFx registers indicate the status of change notice based on the setting of the EDGEDETECT bit. If the EDGEDETECT bit is set to ‘0’, the CNSTATx register indicates whether a change occurred on the corresponding pin since the last read of the PORTx bit. If the EDGEDETECT bit is set to ‘1’, the CNFx register indicates whether a change has occurred and through the CNNEx/CNENx registers the edge type of the change that occurred is also indicated. Each I/O pin also has a weak pull-up and a weak pull-down connected to it. The pull-ups act as a current source or sink source connected to the pin, and eliminate the need for external resistors when push-button or keypad devices are connected. The pull-ups and pull-downs are enabled separately using the CNPUx and the CNPDx registers, which contain the control bits for each of the pins. Setting any of the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins. Note: Pull-ups and pull-downs on change notification pins should always be disabled when the port pin is configured as a digital output. An additional control register (CNCONx) is shown in Register 12-3.  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 12.2 Registers for Slew Rate Control Some I/O pins can be configured for various types of slew rate control on its associated port. This is controlled by the Slew Rate Control bits in the SRCON1x and SRCON0x registers that are associated with each I/O port. The slew rate control is configured using the corresponding bit in each register, as shown in Table 12-1. As an example, writing 0x0001, 0x0000 to SRCON1A and SRCON0A, respectively, will enable slew rate control on the RA0 pin and sets the slew rate to the slow edge rate. TABLE 12-1: SLEW RATE CONTROL BIT SETTINGS SRCON1x SRCON0x Description 1 1 Slew rate control is enabled and is set to the slowest edge rate. 1 0 Slew rate control is enabled and is set to the slow edge rate. 0 1 Slew rate control is enabled and is set to the medium edge rate. 0 0 Slew rate control is disabled and is set to the fastest edge rate. Note: By default, all of the Port pins are set to the fastest edge rate. 12.3 CLR, SET, and INV Registers Every I/O module register has a corresponding CLR (clear), SET (set) and INV (invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as ‘1’ are modified. Bits specified as ‘0’ are not modified. Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read. 12.4 Peripheral Pin Select (PPS) A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin-count devices. In an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only option.  2015-2021 Microchip Technology Inc. PPS configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the device to their entire application, rather than trimming the application to fit the device. The PPS configuration feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of most digital peripherals to these I/O pins. PPS is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. 12.4.1 AVAILABLE PINS The number of available pins is dependent on the particular device and its pin count. Pins that support the PPS feature include the designation “RPn” in their full pin designation, where “RP” designates a remappable peripheral and “n” is the remappable port number. 12.4.2 AVAILABLE PERIPHERALS The peripherals managed by the PPS are all digitalonly peripherals. These include general serial communications (UART, SPI, and CAN), general purpose timer clock inputs, timer-related peripherals (input capture and output compare), interrupt-on-change inputs, and reference clocks (input and output). In comparison, some digital-only peripheral modules are never included in the PPS feature. This is because the peripheral’s function requires special I/O circuitry on a specific port and cannot be easily connected to multiple pins. These modules include I2C among others. A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). A key difference between remappable and non-remappable peripherals is that remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non-remappable peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Remappable peripherals never take priority over any analog functions associated with the pin. DS60001320H-page 261 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 12.4.3 CONTROLLING PPS PPS features are controlled through two sets of SFRs: one to map peripheral inputs, and one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on whether an input or output is being mapped. 12.4.4 INPUT MAPPING The inputs of the PPS options are mapped on the basis of the peripheral. That is, a control register associated with a peripheral dictates the pin it will be mapped to. The [pin name]R registers, where [pin name] refers to the peripheral pins listed in Table 12-2, are used to configure peripheral input mapping (see Register 12-1). Each register contains sets of 4 bit fields. Programming these bit fields with an appropriate value maps the RPn pin with the corresponding value to that peripheral. For any given device, the valid range of values for any bit field is shown in Table 12-2. For example, Figure 12-2 illustrates the remappable pin selection for the U1RX input. FIGURE 12-2: REMAPPABLE INPUT EXAMPLE FOR U1RX U1RXR 0 RPD2 1 RPG8 2 RPF4 U1RX input to peripheral n RPn Note: For input only, PPS functionality does not have priority over TRISx settings. Therefore, when configuring RPn pin for input, the corresponding bit in the TRISx register must also be configured for input (set to ‘1’). DS60001320H-page 262  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 12-2: INPUT PIN SELECTION Peripheral Pin [pin name]R SFR [pin name]R bits INT3 INT3R INT3R T2CK T2CKR T2CKR T6CK T6CKR T6CKR IC3 IC3R IC3R Note 1: 2: 3: IC7 IC7R IC7R U1RX U1RXR U1RXR U2CTS U2CTSR U2CTSR U5RX U5RXR U5RXR U6CTS U6CTSR U6CTSR SDI1 SDI1R SDI1R SDI3 SDI3R SDI3R SDI5(1) SDI5R(1) SDI5R(1) SS6(1) SS6R(1) SS6R(1) REFCLKI1 REFCLKI1R REFCLKI1R INT4 INT4R INT4R T5CK T5CKR T5CKR T7CK T7CKR T7CKR IC4 IC4R IC4R IC8 IC8R IC8R U3RX U3RXR U3RXR U4CTS U4CTSR U4CTSR SDI2 SDI2R SDI2R SDI4 SDI4R SDI4R C1RX(3) C1RXR(3) C1RXR(3) REFCLKI4 REFCLKI4R REFCLKI4R INT2 INT2R INT2R T3CK T3CKR T3CKR T8CK T8CKR T8CKR IC2 IC2R IC2R IC5 IC5R IC5R IC9 IC9R IC9R U1CTS U1CTSR U1CTSR U2RX U2RXR U2RXR U5CTS U5CTSR U5CTSR SS1 SS1R SS1R SS3 SS3R SS3R SS4 SS4R SS4R SS5(1) SS5R(1) SS5R(1) C2RX(3) C2RXR(3) C2RXR(3) [pin name]R Value to RPn Pin Selection 0000 = RPD2 0001 = RPG8 0010 = RPF4 0011 = RPD10 0100 = RPF1 0101 = RPB9 0110 = RPB10 0111 = RPC14 1000 = RPB5 1001 = Reserved 1010 = RPC1(1) 1011 = RPD14(1) 1100 = RPG1(1) 1101 = RPA14(1) 1110 = RPD6(2) 1111 = Reserved 0000 = RPD3 0001 = RPG7 0010 = RPF5 0011 = RPD11 0100 = RPF0 0101 = RPB1 0110 = RPE5 0111 = RPC13 1000 = RPB3 1001 = Reserved 1010 = RPC4(1) 1011 = RPD15(1) 1100 = RPG0(1) 1101 = RPA15(1) 1110 = RPD7(2) 1111 = Reserved 0000 = RPD9 0001 = RPG6 0010 = RPB8 0011 = RPB15 0100 = RPD4 0101 = RPB0 0110 = RPE3 0111 = RPB7 1000 = Reserved 1001 = RPF12(1) 1010 = RPD12(1) 1011 = RPF8(1) 1100 = RPC3(1) 1101 = RPE9(1) 1110 = Reserved 1111 = Reserved This selection is not available on 64-pin devices. This selection is not available on 64-pin or 100-pin devices. This selection is not available on devices without a CAN module..  2015-2021 Microchip Technology Inc. DS60001320H-page 263 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 12-2: INPUT PIN SELECTION (CONTINUED) Peripheral Pin [pin name]R SFR [pin name]R bits INT1 INT1R INT1R T4CK T4CKR T4CKR T9CK T9CKR T9CKR IC1 IC1R IC1R IC6 IC6R IC6R U3CTS U3CTSR U3CTSR U4RX U4RXR U4RXR U6RX U6RXR U6RXR SS2 SS2R SS2R SDI6(1) Note 1: 2: 3: (1) SDI6R [pin name]R Value to RPn Pin Selection SDI6R(1) OCFA OCFAR OCFAR REFCLKI3 REFCLKI3R REFCLKI3R 0000 = RPD1 0001 = RPG9 0010 = RPB14 0011 = RPD0 0100 = Reserved 0101 = RPB6 0110 = RPD5 0111 = RPB2 1000 = RPF3 (3) 1001 = RPF13(1) 1010 = No Connect 1011 = RPF2(1) 1100 = RPC2(1) 1101 = RPE8(1) 1110 = Reserved 1111 = Reserved This selection is not available on 64-pin devices. This selection is not available on 64-pin or 100-pin devices. This selection is not available on devices without a CAN module.. DS60001320H-page 264  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 12.4.5 OUTPUT MAPPING 12.4.6.1 In contrast to inputs, the outputs of the PPS options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPnR registers (Register 12-2) are used to control output mapping. Like the [pin name]R registers, each register contains sets of 4 bit fields. The value of the bit field corresponds to one of the peripherals, and that peripheral’s output is mapped to the pin (see Table 12-3 and Figure 12-3). A null output is associated with the output register reset value of ‘0’. This is done to ensure that remappable outputs remain disconnected from all output pins by default. FIGURE 12-3: EXAMPLE OF MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPF0 RPF0R Default U1TX Output U2RTS Output 0 1 2 RPF0 Control Register Lock Under normal operation, writes to the RPnR and [pin name]R registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK Configuration bit (CFGCON). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear the IOLOCK bit, an unlock sequence must be executed. Refer to Section 42. “Oscillators with Enhanced PLL” in the “PIC32 Family Reference Manual” for details. 12.4.6.2 Configuration Bit Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the RPnR and [pin name]R registers. The IOL1WAY Configuration bit (DEVCFG3) blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure does not execute, and the PPS control registers cannot be written to. The only way to clear the bit and reenable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Output Data 14 REFCLKO1 12.4.6 15 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC32MZ EF devices include two features to prevent alterations to the peripheral map: • Control register lock sequence • Configuration bit select lock  2015-2021 Microchip Technology Inc. DS60001320H-page 265 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 12-3: OUTPUT PIN SELECTION RPn Port Pin RPnR SFR RPD2 RPD2R RPD2R RPG8 RPG8R RPG8R RPF4 RPF4R RPF4R RPD10 RPD10R RPD10R RPF1 RPF1R RPF1R RPB9 RPB9R RPB9R RPB10 RPB10R RPB10R RPC14 RPC14R RPC14R RPB5 RPB5R RPB5R RPC1(1) RPC1R(1) RPC1R(1) RPD14(1) RPD14R(1) RPD14R(1) RPG1(1) RPG1R(1) RPG1R(1) RPA14(1) RPA14R(1) RPA14R(1) RPD6(2) RPD6R(2) RPD6R(2) RPD3 RPD3R RPD3R RPG7 RPG7R RPG7R RPF5 RPF5R RPF5R RPD11 RPD11R RPD11R RPF0 RPF0R RPF0R RPB1 RPB1R RPB1R RPE5 RPE5R RPE5R RPC13 RPC13R RPC13R RPB3 RPB3R RPB3R RPC4(1) RPC4R(1) RPC4R(1) RPD15(1) RPD15R(1) RPD15R(1) RPG0(1) RPG0R(1) RPG0R(1) RPA15(1) RPA15R(1) RPA15R(1) RPD7(2) RPD7R(2) RPD7R(2) Note 1: 2: 3: 4: RPnR Value to Peripheral Selection RPnR bits 0000 = No Connect 0001 = U3TX 0010 = U4RTS 0011 = Reserved 0100 = Reserved 0101 = SDO1 0110 = SDO2 0111 = SDO3 1000 = Reserved 1001 = SDO5(1) 1010 = SS6(1) 1011 = OC3 1100 = OC6 1101 = REFCLKO4 1110 = C2OUT 1111 = C1TX(3) 0000 = No Connect 0001 = U1TX 0010 = U2RTS 0011 = U5TX 0100 = U6RTS 0101 = SDO1 0110 = SDO2 0111 = SDO3 1000 = SDO4 1001 = SDO5(1) 1010 = Reserved 1011 = OC4 1100 = OC7 1101 = Reserved 1110 = Reserved 1111 = REFCLKO1 This selection is not available on 64-pin devices. This selection is not available on 64-pin or 100-pin devices. This selection is not available on devices without a CAN module. This selection is not available when VUSB3V3 pin is connected to VSS. DS60001320H-page 266  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 12-3: OUTPUT PIN SELECTION (CONTINUED) RPn Port Pin RPnR SFR RPD9 RPD9R RPD9R RPG6 RPG6R RPG6R RPB8 RPB8R RPB8R RPB15 RPB15R RPB15R RPD4 RPD4R RPD4R RPB0 RPB0R RPB0R RPE3 RPE3R RPE3R RPB7 RPB7R RPB7R RPF12(1) RPF12R(1) RPF12R(1) RPD12(1) RPD12R(1) RPD12R(1) RPF8(1) RPF8R(1) RPF8R(1) RPC3(1) RPC3R(1) RPC3R(1) RPE9(1) RPE9R(1) RPE9R(1) RPD1 RPD1R RPD1R RPG9 RPG9R RPG9R RPB14 RPB14R RPB14R RPD0 RPD0R RPD0R RPB6 RPB6R RPB6R RPD5 RPD5R RPD5R RPB2 RPB2R RPB2R RPF3(4) RPF3R(4) RPF3R RPF13(1) RPF13R(1) RPF13R(1) RPC2(1) RPC2R(1) RPC2R(1) RPE8(1) RPE8R(1) RPE8R(1) RPF2(1) RPF2R(1) RPF2R(1) Note 1: 2: 3: 4: RPnR Value to Peripheral Selection RPnR bits 0000 = No Connect 0001 = U3RTS 0010 = U4TX 0011 = Reserved 0100 = U6TX 0101 = SS1 0110 = Reserved 0111 = SS3 1000 = SS4 1001 = SS5(1) 1010 = SDO6(1) 1011 = OC5 1100 = OC8 1101 = Reserved 1110 = C1OUT 1111 = REFCLKO3 0000 = No Connect 0001 = U1RTS 0010 = U2TX 0011 = U5RTS 0100 = U6TX 0101 = Reserved 0110 = SS2 0111 = Reserved 1000 = SDO4 1001 = Reserved 1010 = SDO6(1) 1011 = OC2 1100 = OC1 1101 = OC9 1110 = Reserved 1111 = C2TX(3) This selection is not available on 64-pin devices. This selection is not available on 64-pin or 100-pin devices. This selection is not available on devices without a CAN module. This selection is not available when VUSB3V3 pin is connected to VSS.  2015-2021 Microchip Technology Inc. DS60001320H-page 267 I/O Ports Control Registers ANSELA 0010 0020 0030 0040 TRISA PORTA LATA ODCA 0050 CNPUA 0060 CNPDA 0070 CNCONA 0080 CNENA  2015-2021 Microchip Technology Inc. 0090 CNSTATA 00A0 CNNEA 00B0 CNFA 00C0 SRCON0A 00D0 SRCON1A Legend: Note 1: Bits 31/15 30/14 29/13 28/12 27/11 31:16 — — — — — 15:0 — — — — — 31:16 — — — — — — — 15:0 TRISA15 TRISA14 26/10 25/9 24/8 23/7 22/6 — — — — ANSA10 ANSA9 — — — — — — TRISA10 TRISA9 16/0 All Resets Register Name(1) 0000 PORTA REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY Bit Range Virtual Address (BF86_#) TABLE 12-4: — — 0000 ANSA1 ANSA0 0623 — — 0000 TRISA2 TRISA1 TRISA0 C6FF 21/5 20/4 19/3 18/2 — — — — — — ANSA5 — — — — — — — — — — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 17/1 31:16 — — — — — — — — — — — — — — — — 0000 15:0 RA15 RA14 — — — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 LATA15 LATA14 — — — LATA10 LATA9 — LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 — — — ODCA10 ODCA9 — ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000 — — — — — — — — — — — — — — 0000 15:0 CNPUA15 CNPUA14 — — — 31:16 15:0 31:16 ODCA15 ODCA14 — — — — CNPUA10 CNPUA9 — — — — — — 15:0 CNPDA15 CNPDA14 — — — 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ON — — — EDGEDETECT — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — 0000 CNPDA10 CNPDA9 — CNPUA7 CNPUA6 CNPUA5 CNPUA4 CNPUA3 CNPUA2 CNPUA1 CNPUA0 0000 — — — — — — — 15:0 CNENA15 CNENA14 — — — 31:16 — — — — — — — — — — — — — CN STATA10 CN STATA9 — CN STATA7 CN STATA6 CN STATA5 CN STATA4 CN STATA3 CN STATA2 CN STATA1 — — — — — — — — — — 15:0 31:16 — — CN CN STATA15 STATA14 — — — — — CNENA10 CNENA9 — — 0000 CNPDA7 CNPDA6 CNPDA5 CNPDA4 CNPDA3 CNPDA2 CNPDA1 CNPDA0 0000 CNENA7 CNENA6 CNENA5 CNENA4 CNENA3 CNENA2 CNENA1 CNENA0 0000 — 0000 CN 0000 STATA0 — — — 15:0 CNNEA15 CNNEA14 — — — 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNFA15 CNFA14 — — — CNFA10 CNFA9 — CNFA7 CNFA76 CNFA5 CNFA4 CNFA3 CNFA2 CNFA71 CNFA0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — SR0A7 SR0A6 — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — SR1A7 SR0A6 — — — — — — 0000 CNNEA10 CNNEA9 — — 0000 CNNEA7 CNNEA6 CNNEA5 CNNEA4 CNNEA3 CNNEA2 CNNEA1 CNNEA0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 268 12.5 0120 TRISB PORTB 0130 LATB 0140 ODCB 0150 CNPUB 0160 CNPDB 0180 CNENB 0190 CNSTATB 01A0 CNNEB 01B0 CNFB 01C0 SRCON0B 01D0 SRCON1B DS60001320H-page 269 Legend: Note 1: 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ANSB15 ANSB14 ANSB13 ANSB12 ANSB11 ANSB10 ANSB9 ANSB8 ANSB7 ANSB6 ANSB5 ANSB41 ANSB3 ANSB2 ANSB1 ANSB0 FFFF 31:16 — — — — — — — — — — — — — — — — 0000 15:0 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF 31:16 — — — — — — — — — — — — — — — — 0000 15:0 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12 CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6 CNPUB5 31:16 — — — — — — — — — — — 15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12 CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6 CNPDB5 31:16 0170 CNCONB 31/15 All Resets Bit Range Register Name(1) Virtual Address (BF86_#) Bits 0100 ANSELB 0110 PORTB REGISTER MAP — — — CNPUB4 — CNPDB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000 — — — — 0000 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000 — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 15:0 ON — — — EDGE DETECT 31:16 — — — — — 15:0 CNENB15 CNENB14 CNENB13 CNENB12 CNENB11 CNENB10 CNENB9 CNENB8 CNENB7 CNENB6 CNENB5 CNENB4 CNENB3 CNENB2 CNENB1 CNENB0 0000 31:16 — — — — — — — — — — — — — — — 15:0 CN STATB15 CN STATB14 CN STATB13 CN STATB12 CN STATB11 CN STATB10 CN STATB9 CN STATB8 CN STATB7 CN STATB6 CN STATB5 CN STATB4 CN STATB3 CN STATB2 CN STATB1 31:16 — — — — — — — — — — — — — — 15:0 CNNEB15 CNNEB14 CNNEB13 CNNEB12 CNNEB11 CNNEB10 CNNEB9 CNNEB8 CNNEB7 CNNEB6 CNNEB5 — CNNEB4 — 0000 CN 0000 STATB0 — 0000 CNNEB3 CNNEB2 CNNEB1 CNNEB0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNFB15 CNFB14 CNFB13 CNFB12 CNFB11 CNFB10 CNFB9 CNFB8 CNFB7 CNFB6 CNFB5 CNFB4 CNFB3 CNFB2 CNFB1 CNFB0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — SR0B14 — — — SR0B10 SR0B9 SR0B8 — — SR0B5 — SR0B3 — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — SR1B14 — — — SR1B10 SR1B9 SR1B8 — — SR1B5 — SR1B3 — — — 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 12-5: 0230 PORTC LATC 0240 ODCC 0250 CNPUC 0260 CNPDC 0270 CNCONC 0280 CNENC 0290 CNSTATC 02A0 02B0 CNNEC CNFC  2015-2021 Microchip Technology Inc. Legend: Note 1: 17/1 16/0 All Resets 0220 TRISC Bit Range Register Name(1) Virtual Address (BF86_#) Bits 0200 ANSELC 0210 PORTC REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY — — — 0000 ANSC2 ANSC1 — 001E — — — 0000 TRISC3 TRISC2 TRISC1 — F01E — — — — — 0000 — RC4 RC3 RC2 RC1 — xxxx — — — — — — — 0000 — — — LATC4 LATC3 LATC2 LATC1 — xxxx — — — — — — — — — 0000 — — — — — ODCC4 ODCC3 ODCC2 ODCC1 — 0000 — — — — — — — — — — — 0000 — — — — — — — CNPUC4 CNPUC3 CNPUC2 CNPUC1 — 0000 — — — — — — — — — — — — — 0000 CNPDC13 CNPDC12 — — — — — — — CNPDC4 CNPDC3 CNPDC2 CNPDC1 — 0000 — — — — — — — — — — — — — — — 0000 — — — EDGE DETECT — — — — — — — — — — — 0000 — — — — — — — — 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — — — 15:0 — — — — — — — — — — — ANSC4 ANSC3 31:16 — — — — — — — — — — — — — 15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — TRISC4 31:16 — — — — — — — — — — — 15:0 RC15 RC14 RC13 RC12 — — — — — — 31:16 — — — — — — — — — 15:0 LATC15 LATC14 LATC13 LATC12 — — — — 31:16 — — — — — — — 15:0 ODCC15 ODCC14 ODCC13 ODCC12 — — 31:16 — — — — — 15:0 CNPUC15 CNPUC14 CNPUC13 CNPUC12 31:16 — — — 15:0 CNPDC15 CNPDC14 31:16 — 15:0 ON 31:16 — — 15:0 CNENC15 CNENC14 CNENC13 CNENC12 31:16 — — — — 20/4 19/3 18/2 — — — — — 0000 CNENC4 CNENC3 CNENC2 CNENC1 — 0000 — — — — — 0000 — 0000 — — — — — — — 15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12 — — — — — — — 31:16 — — — — — — — — — — — — — — — 0000 15:0 CNNEC15 CNNEC14 CNNEC13 CNNEC12 — — — — — — — CNNEC4 CNNEC3 CNNEC2 CNNEC1 — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNFC15 CNFC14 CNFC13 CNFC12 — — — — — — — CNFC4 CNFC3 CNFC2 CNFC1 — 0000 CNSTATC4 CNSTATC3 CNSTATC2 CNSTATC1 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 270 TABLE 12-6: Virtual Address (BF86_#) Register Name(1) 0210 TRISC 0220 PORTC LATC 0240 ODCC 0260 CNPUC CNPDC 0270 CNCONC 0280 CNENC 0290 CNSTATC 02A0 02B0 CNNEC CNFC Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits 0230 0250 PORTC REGISTER MAP FOR 64-PIN DEVICES ONLY 31:16 — — — — — — — — — — — — — — — — 0000 15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — — — — — — F000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 RC15 RC14 RC13 RC12 — — — — — — — — — — — — xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 LATC15 LATC14 LATC13 LATC12 — — — — — — — — — — — — xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ODCC15 ODCC14 ODCC13 ODCC12 — — — — — — — — — — — — xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNPUC15 CNPUC14 CNPUC13 CNPUC12 — — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNPDC15 CNPDC14 CNPDC13 CNPDC12 — — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ON — — — EDGE DETECT — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNENC15 CNENC14 CNENC13 CNENC12 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNSTATC15 CNSTATC14 CNSTATC13 CNSTATC12 — — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — 0000 15:0 CNNEC15 CNNEC14 CNNEC13 CNNEC12 — — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNFC15 CNFC14 CNFC13 CNFC12 — — — — — — — — — — — — 0000 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. DS60001320H-page 271 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 12-7: 0310 TRISD 0320 PORTD LATD 0340 ODCD 0350 CNPUD 0360 CNPDD 0370 CNCOND 0380 CNEND 0390 CNSTATD 03A0  2015-2021 Microchip Technology Inc. 03B0 CNNED CNFD Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Virtual Address (BF86_#) Bits 0300 ANSELD 0330 PORTD REGISTER MAP FOR 124-PIN AND 144-PIN DEVICES ONLY 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ANSD15 ANSD14 — — — — — — — — — — — — — — C000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 — TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FEFF 31:16 — — — — — — — — — — — — — — — — 0000 15:0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 — RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 — LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 — ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 31:16 — — — — — — — — — — — — — — — 15:0 CNPUD15 CNPUD14 CNPUD13 CNPUD12 CNPUD11 CNPUD10 CNPUD9 — 31:16 — — — — — — — — ODCD0 0000 — 0000 CNPUD7 CNPUD6 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000 — — — — — — — — 0000 15:0 CNPDD15 CNPDD14 CNPDD13 CNPDD12 CNPDD11 CNPDD10 CNPDD9 — 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ON — — — EDGE DETECT — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNEND15 CNEND14 CNEND13 CNEND12 CNEND11 CNEND10 CNEND9 — 31:16 — — 15:0 CN STATD15 CN STATD14 31:16 — — — — — 15:0 CNNED15 CNNED14 CNNED13 CNNED12 31:16 — — — 15:0 CNFD15 CNFD14 CNFD13 — — — — CNEND7 CNEND6 CNEND5 CNEND4 CNEND3 CNEND2 CNEND1 CNEND0 0000 — — — — — — — — CN STATD9 — CN STATD7 CN STATD6 CN STATD5 CN STATD4 CN STATD3 CN STATD2 CN STATD1 — — — — — — — — — — — CNNED11 CNNED10 CNNED9 — CNNED7 CNNED6 CNNED5 CNNED4 CNNED3 CNNED2 CNNED1 CNNED0 0000 — — — — — — — — — — — — — 0000 CNFD12 CNFD11 CNFD10 CNFD9 — CNFD7 CNFD6 CNFD5 CNFD4 CNFD3 CNFD2 CNFD1 CNFD0 0000 CN CN CN CN STATD13 STATD12 STATD11 STATD10 — CNPDD7 CNPDD6 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000 — 0000 CN 0000 STATD0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 272 TABLE 12-8: 0310 TRISD 0320 PORTD 0330 LATD 0340 ODCD 0350 CNPUD 0360 CNPDD 0370 CNCOND CNEND 0390 CNSTATD 03A0 CNNED 03B0 CNFD Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name(1) Virtual Address (BF86_#) Bits 0300 ANSELD 0380 PORTD REGISTER MAP FOR 100-PIN DEVICES ONLY 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ANSD15 ANSD14 — — — — — — — — — — — — — — C000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 — — — TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FE3F 31:16 — — — — — — — — — — — — — — — — 0000 15:0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 — — — RD5 RD4 RD3 RD2 RD1 RD0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 LATD15 LATD14 LATD13 LATD12 LATD11 LATD10 LATD9 — — — LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 — — — ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 31:16 — — — — — — — — — — — — — — — 15:0 CNPUD15 CNPUD14 CNPUD13 CNPUD12 CNPUD11 CNPUD10 CNPUD9 — — — 31:16 — — — 15:0 CNPDD15 CNPDD14 CNPDD13 CNPDD12 CNPDD11 CNPDD10 CNPDD9 — — — — 31:16 — — — — — — — — — ODCD0 0000 — 0000 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000 — — — — — — 0000 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000 — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 15:0 CNEND15 CNEND14 CNEND13 CNEND12 CNEND11 CNEND10 CNEND9 — — — 31:16 — — — — — — — — — — — — — — — 15:0 CN STATD15 CN STATD14 CN STATD13 CN STATD12 CN STATD11 CN STATD10 CN STATD9 — — — CN STATD5 CN STATD4 CN STATD3 CN STATD2 CN STATD1 15:0 ON — — — EDGE DETECT 31:16 — — — — — CNEND5 CNEND4 CNEND3 CNEND2 CNEND1 CNEND0 0000 31:16 — — — — — — — — — — — — — — — 15:0 CNNED15 CNNED14 CNNED13 CNNED12 CNNED11 CNNED10 CNNED9 — — — CNNED5 CNNED4 CNNED3 CNNED2 CNNED1 — 0000 CN 0000 STATD0 — 0000 CNNED0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNFD15 CNFD14 CNFD13 CNFD12 CNFD11 CNFD10 CNFD9 — — — CNFD5 CNFD4 CNFD3 CNFD2 CNFD1 CNFD0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. DS60001320H-page 273 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 12-9: Virtual Address (BF86_#) Register Name(1) 0310 TRISD 0320 PORTD 0340 LATD ODCD 0350 CNPUD 0360 CNPDD 0370 CNCOND 0380 CNEND 0390 CNSTATD 03A0 CNNED 03B0 CNFD  2015-2021 Microchip Technology Inc. Legend: Note 1: Bit Range 31/15 30/14 29/13 28/12 27/11 31:16 — — — — — 15:0 — — — — TRISD11 31:16 — — — — — 15:0 — — — — 31:16 — — — 15:0 — — 31:16 — 15:0 16/0 All Resets 0330 Bits — — 0000 TRISD1 TRISD0 0E3F — — 0000 RD2 RD1 RD0 xxxx — — — — 0000 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx — — — — — — 0000 — ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000 — — — — — — — — 0000 — — — — — — — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 26/10 25/9 24/8 23/7 22/6 — — — — — — — — — TRISD10 TRISD9 — — — TRISD5 TRISD4 TRISD3 TRISD2 — — — — — — — — — RD11 RD10 RD9 — — — RD5 RD4 RD3 — — — — — — — — — — — LATD11 LATD10 LATD9 — — — LATD5 — — — — — — — — — — — — — ODCD11 ODCD10 ODCD9 — — 31:16 — — — — — — — — 15:0 — — — — 31:16 — — — — 15:0 — — — — 31:16 — — — — — — EDGE DETECT — CNPUD11 CNPUD10 CNPUD9 — — — CNPDD11 CNPDD10 CNPDD9 15:0 ON — — — 31:16 — — — — 15:0 — — — — 31:16 — — — — — — — CN STATD10 CN STATD9 — — — — CNEND11 CNEND10 CNEND9 21/5 20/4 19/3 18/2 17/1 CNPUD5 CNPUD4 CNPUD3 CNPUD2 CNPUD1 CNPUD0 0000 — — — — — — 0000 CNPDD5 CNPDD4 CNPDD3 CNPDD2 CNPDD1 CNPDD0 0000 CNEND5 CNEND4 CNEND3 CNEND2 CNEND1 CNEND0 0000 — — — — — — — — — 0000 — — CN STATD5 CN STATD4 CN STATD3 CN STATD2 CN STATD1 CN STATD0 0000 — — — — — — — — 0000 — — — 15:0 — — — — CN STATD11 31:16 — — — — — 15:0 — — — — 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — CNFD11 CNFD10 CNFD9 — — — CNFD5 CNFD4 CNFD3 CNFD2 CNFD1 CNFD0 0000 CNNED11 CNNED10 CNNED9 CNNED5 CNNED4 CNNED3 CNNED2 CNNED1 CNNED0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 274 TABLE 12-10: PORTD REGISTER MAP FOR 64-PIN DEVICES ONLY Virtual Address (BF86_#) Register Name(1) 0400 ANSELE TRISE 0420 PORTE 0430 LATE 0440 ODCE 0450 CNPUE 0460 CNPDE 0470 CNCONE 0480 CNENE 0490 CNSTATE 04A0 CNNEE 04B0 CNFE 04C0 SRCON0E 04D0 SRCON1E DS60001320H-page 275 Legend: Note 1: Bit Range 20/4 19/3 18/2 17/1 16/0 All Resets 0410 Bits — — — — — — 0000 ANSE5 ANSE4 — — — — 03F0 — — — — — — 0000 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF — — — — — — — — 0000 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx — — — — — — — — — — 0000 — LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx — — — — — — — — — — — — 0000 — — — ODCE9 ODCE8 ODCE7 ODCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000 — — — — — — — — — — — — — — 0000 — — — — — CNPUE6 CNPUE5 — — — — — — — — — — — — — — — — — — — — 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 31:16 — — — — — — — — — — 15:0 — — — — — — ANSE9 ANSE8 ANSE7 ANSE6 31:16 — — — — — — — — — — 15:0 — — — — — — TRISE9 TRISE8 TRISE7 31:16 — — — — — — — — 15:0 — — — — — — RE9 31:16 — — — — — — 15:0 — — — — — 31:16 — — — — 15:0 — — — 31:16 — — 15:0 — 31:16 15:0 31:16 CNPUE9 CNPUE8 CNPUE7 — — — 22/6 21/5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000 — — CNPDE6 CNPDE5 — — — — — — — — 0000 CNPDE9 CNPDE8 CNPDE7 — — — — — 0000 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 0000 15:0 ON — — — EDGE DETECT — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — CNENE6 CNENE5 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — CN STATE9 CN STATE8 CN STATE7 CN STATE6 CN STATE5 CN STATE4 CN STATE3 CN STATE2 CN STATE1 31:16 — — — — — — — — — — — — — 15:0 — — — — — — 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — CNFE9 CNFE8 CNFE7 CNFE6 CNFE5 CNFE4 CNFE3 CNFE2 CNFE1 CNFE0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — SR0E3 SR0E2 SR0E1 SR0E0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — SR1E3 SR1E2 SR1E1 SR1E0 0000 CNENE9 CNENE8 CNENE7 CNNEE9 CNNEE8 CNNEE7 — — CNNEE6 CNNEE5 CNENE4 CNENE3 CNENE2 CNENE1 CNENE0 0000 — 0000 CN 0000 STATE0 — 0000 CNNEE4 CNNEE3 CNNEE2 CNNEE1 CNNEE0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 12-11: PORTE REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY Virtual Address (BF86_#) Register Name(1) 0400 ANSELE 0410 TRISE 0430 PORTE LATE 0440 ODCE 0450 CNPUE 0460 CNPDE 0470 CNCONE 0480 CNENE 0490 CNSTATE  2015-2021 Microchip Technology Inc. 04A0 CNNEE 04B0 CNFE 04C0 SRCON0E 04D0 SRCON1E Legend: Note 1: Bit Range 20/4 19/3 18/2 17/1 16/0 All Resets 0420 Bits — — — — — — 0000 ANSE5 ANSE4 — — — — 00F0 — — — — — — 0000 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 00FF — — — — — — — — 0000 — RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx — — — — — — — — — — 0000 — — — LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx — — — — — — — — — — — — 0000 — — — — — ODCE7 ODCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000 — — — — — — — — — — — — — — 0000 — — — — — — — CNPUE7 CNPUE6 CNPUE5 — — — — — — — — — — — — — — — — — — — CNPDE7 CNPDE6 CNPDE5 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ON — — — EDGE DETECT — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — CNENE7 CNENE6 CNENE5 31:16 — — — — — — — — — — — — — — — CN STATE7 CN STATE6 CN STATE5 CN STATE4 CN STATE3 CN STATE2 CN STATE1 — — — — 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — — — — — — — — — — 15:0 — — — — — — — — ANSE7 ANSE6 31:16 — — — — — — — — — — 15:0 — — — — — — — — TRISE7 31:16 — — — — — — — — 15:0 — — — — — — — 31:16 — — — — — — 15:0 — — — — — 31:16 — — — — 15:0 — — — 31:16 — — 15:0 — 31:16 15:0 21/5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000 — — — — — 0000 CNPDE4 CNPDE3 CNPDE2 CNPDE1 CNPDE0 0000 CNENE4 CNENE3 CNENE2 CNENE1 CNENE0 0000 — 0000 CN 0000 STATE0 15:0 — — — — — — — — 31:16 — — — — — — — — — — — 15:0 — — — — — — — — CNNEE7 CNNEE6 CNNEE5 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — CNFE7 CNFE6 CNFE5 CNFE4 CNFE3 CNFE2 CNFE1 CNFE0 0000 31:16 — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — SR0E3 SR0E2 SR0E1 SR0E0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — SR1E3 SR1E2 SR1E1 SR1E0 0000 — 0000 CNNEE4 CNNEE3 CNNEE2 CNNEE1 CNNEE0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 276 TABLE 12-12: PORTE REGISTER MAP FOR 64-PIN DEVICES ONLY 0510 TRISF 0520 PORTF 0530 LATF 0540 ODCF 0550 CNPUF 0560 CNPDF 0570 CNCONF 0580 CNENF 0590 CNSTATF 05A0 CNNEF 05B0 CNFF 05C0 SRCON0F 05D0 SRCON1F DS60001320H-page 277 Legend: Note 1: 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 0500 ANSELF Bit Range Register Name(1) Virtual Address (BF86_#) Bits — — — — — — — — — — — — — — 0000 ANSF13 ANSF12 — — — — — — — — — — — — 3000 — — — — — — — — — — — — — — 0000 — TRISF13 TRISF12 — — — TRISF8 — — TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 313F — — — — — — — — — — — — — — — — 0000 15:0 — — RF13 RF12 — — — RF8 — — RF5 RF4 RF3 RF2 RF1 RF0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — LATF13 LATF12 — — — LATF8 — — LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — ODCF13 ODCF12 — — — ODCF8 — — ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — CNPUF8 — — CNPUF5 CNPUF4 CNPUF3 CNPUF2 CNPUF1 31:16 — — — — — — — — — — — — — 15:0 — — — — — CNPDF8 — — CNPDF5 CNPDF4 CNPDF3 CNPDF2 CNPDF1 31:16 — — — — — — — — — — — — — — — 0000 31/15 30/14 31:16 — — 15:0 — — 31:16 — — 15:0 — 31:16 29/13 CNPUF13 CNPUF12 — — CNPDF13 CNPDF12 — CNPUF0 0000 — 0000 CNPDF0 0000 15:0 ON — — — EDGE DETECT — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — CNENF8 — — CNENF5 CNENF4 CNENF3 CNENF2 CNENF1 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — CN STATF13 CN STATF12 — — — CN STATF8 — — CN STATF5 CN STATF4 CN STATF3 CN STATF2 CN STATF1 CN STATF0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — CNNEF8 — — CNNEF5 CNNEF4 CNNEF3 CNNEF2 CNNEF1 31:16 — — — — — — — — — — 15:0 — — CNFF13 CNFF12 31:16 — — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — 15:0 — — — — — — — CNENF13 CNENF12 CNNEF13 CNNEF12 CNENF0 0000 CNNEF0 0000 — — — — — — 0000 CNFF5 CNFF4 CNFF3 CNFF2 CNFF1 CNFF0 0000 — — — — — — — 0000 — — — — — — SR0F1 SR0F0 0000 — — — — — — — — — 0000 — — — — — — — SR1F1 SR1F0 0000 CNFF8 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 12-13: PORTF REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY Virtual Address (BF86_#) Register Name(1) 0510 TRISF 0520 PORTF 0540 LATF ODCF 0550 CNPUF 0560 CNPDF 0570 CNCONF 0580 CNENF 0590 CNSTATF 05A0 CNNEF 05B0 CNFF  2015-2021 Microchip Technology Inc. 05C0 SRCON0F 05D0 SRCON1F Legend: Note 1: Bit Range 16/0 All Resets 0530 Bits — — 0000 TRISF1 TRISF0 003B — — 0000 — RF1 RF0 xxxx — — — — 0000 LATF4 LATF3 — LATF1 LATF0 xxxx — — — — — — 0000 — ODCF5 ODCF4 ODCF3 — ODCF1 ODCF0 0000 — — — — — — — — 0000 — — — CNPUF5 CNPUF4 CNPUF3 — CNPUF1 — — — — — — — — — — — — — CNPDF5 CNPDF4 CNPDF3 — CNPDF1 — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — 0000 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 31:16 — — — — — — — — — — — 15:0 — — — — — — — — — — TRISF5 31:16 — — — — — — — — — — — 15:0 — — — — — — — — — — 31:16 — — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — 15:0 — — — — — — 31:16 — — — — — 15:0 — — — — 31:16 — — — 15:0 — — — 31:16 — — — 20/4 19/3 18/2 — — — TRISF4 TRISF3 — — — — RF5 RF4 RF3 — — — — — LATF5 — — — — — — — — — — — — — — — — — — — — 17/1 CNPUF0 0000 — 0000 CNPDF0 0000 15:0 ON — — — EDGE DETECT 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — CNENF5 CNENF4 CNENF3 — CNENF1 31:16 — — — — — — — — — — — — — — — — 0000 CN STATF4 CN STATF3 CN STATF0 0000 — 0000 CNENF0 0000 15:0 — — — — — — — — — — CN STATF5 — CN STATF1 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — CNNEF5 CNNEF4 CNNEF3 — CNNEF1 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — CNFF5 CNFF4 CNFF3 — CNFF1 CNFF0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — — — SR0F1 SR0F0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — — — SR1F1 SR2F0 0000 CNNEF0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 278 TABLE 12-14: PORTF REGISTER MAP FOR 64-PIN DEVICES ONLY 0610 TRISG 0620 PORTG 0630 LATG 0640 ODCG 0650 CNPUG 0660 CNPDG 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 0600 ANSELG Bit Range Register Name(1) Virtual Address (BF86_#) Bits — — — — — — — — 0000 ANSG7 ANSG6 — — — — — — 83C0 — — — — — — — — 0000 TRISG8 TRISG7 TRISG6 — — — — TRISG1 TRISG0 F3C3 — — — — — — — — — — 0000 — RG9 RG8 RG7 RG6 — — — — RG1 RG0 xxxx — — — — — — — — — — — — 0000 LATG12 — — LATG9 LATG8 LATG7 LATG6 — — — — LATG1 LATG0 xxxx — — — — — — — — — — — — — — 0000 ODCG14 ODCG13 ODCG12 — — ODCG9 ODCG8 ODCG7 ODCG6 — — — — ODCG1 ODCG0 0000 — — — — — — — — — — — — — — — 0000 15:0 CNPUG15 CNPUG14 CNPUG13 CNPUG12 — — CNPUG9 CNPUG8 CNPUG7 CNPUG6 — — — — 31:16 — — — — — — — — — — — — CNPDG9 CNPDG8 CNPDG7 CNPDG6 — — — — — — — — — — — — — — — — — 0000 31/15 30/14 29/13 28/12 27/11 26/10 31:16 — — — — — — — — 15:0 ANSG15 — — — — — ANSG9 ANSG8 31:16 — — — — — — — — 15:0 TRISG15 — — TRISG9 31:16 — — — — — — 15:0 RG15 RG14 RG13 RG12 — 31:16 — — — — 15:0 LATG15 LATG14 LATG13 31:16 — — 15:0 ODCG15 31:16 — 0680 CNENG 0690 CNSTATG 06A0 CNNEG 06B0 CNFG 06C0 SRCON0G 06D0 SRCON1G DS60001320H-page 279 Legend: Note 1: — — — 15:0 CNPDG15 CNPDG14 CNPDG13 CNPDG12 31:16 0670 CNCONG — TRISG14 TRISG13 TRISG12 — — — 25/9 24/8 23/7 CNPUG1 CNPUG0 0000 — — 0000 CNPDG1 CNPDG0 0000 15:0 ON — — — EDGE DETECT — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNENG15 CNENG14 CNENG13 CNENG12 — — CNENG9 CNENG8 CNENG7 CNENG6 — — — — 31:16 — — — — — — — — — — — — 15:0 CN STATG15 — — CN STATG9 CN STATG8 CN STATG7 CN STATG6 — — — — CN STATG1 31:16 — — — — CN CN CN STATG14 STATG13 STATG12 — — — CNENG1 CNENG0 0000 — — 0000 CN 0000 STATG0 — — — — — — — — — — 15:0 CNNEG15 CNNEG14 CNNEG13 CNNEG12 — — CNNEG9 CNNEG8 CNNEG7 CNNEG6 — — — — — 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNFG15 CNFG14 CNFG13 CNFG12 — — CNFG9 CNFG8 CNFG7 CNFG6 — — — — CNFG1 CNFG0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — SR0G14 SR0G13 SR0G12 — — SR0G9 — — SR0G6 — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — SR1G14 SR1G13 SR1G12 — — SR1G9 — — SR1G6 — — — — — — 0000 0000 CNNEG1 CNNEG0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 12-15: PORTG REGISTER MAP FOR 100-PIN, 124-PIN, AND 144-PIN DEVICES ONLY 0610 0620 0630 TRISG PORTG LATG 0640 ODCG 0650 CNPUG 0660 CNPDG 0670 CNCONG 0680 CNENG 0690 CNSTATG 06A0  2015-2021 Microchip Technology Inc. 06B0 CNNEG CNFG 06C0 SRCON0G 06D0 SRCON1G Legend: Note 1: 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets 0600 ANSELG Bit Range Register Name(1) Virtual Address (BF86_#) Bits — — — — — — — — 0000 ANSG7 ANSG6 — — — — — — 03C0 — — — — — — — — 0000 TRISG8 TRISG7 TRISG6 — — — — — — 03C0 — — — — — — — — — — 0000 — RG9 RG8 RG7 RG6 — — — — — — xxxx — — — — — — — — — — — — 0000 — — — LATG9 LATG8 LATG7 LATG6 — — — — — — xxxx — — — — — — — — — — — — — — 0000 — — — — — ODCG9 ODCG8 ODCG7 ODCG6 — — — — — — 0000 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — CNPUG9 CNPUG8 CNPUG7 CNPUG6 — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — CNPDG9 CNPDG8 CNPDG7 CNPDG6 — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ON — — — EDGE DETECT — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — CNENG9 CNENG8 CNENG7 CNENG6 — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 CN STATG8 CN STATG7 CN STATG6 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — — 15:0 — — — — — — ANSG9 ANSG8 31:16 — — — — — — — — 15:0 — — — — — — TRISG9 31:16 — — — — — — 15:0 — — — — — 31:16 — — — — 15:0 — — — 31:16 — — 15:0 — 31:16 23/7 15:0 — — — — — — CN STATG9 — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — CNNEG9 CNNEG8 CNNEG7 CNNEG6 — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — CNFG9 CNFG8 CNFG7 CNFG6 — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — SR0G9 — — SR0G6 — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — SR1G9 — — SR1G6 — — — — — — 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 280 TABLE 12-16: PORTG REGISTER MAP FOR 64-PIN DEVICES ONLY 0710 TRISH 0720 PORTH 0730 LATH 0740 ODCH 0750 CNPUH 0760 CNPDH 0770 CNCONH 0780 CNENH 0790 CNSTATH 07A0 CNNEH 07B0 CNFH Legend: Note 1: 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 31:16 — — — — — — — — — — 15:0 — — — — — — — — — ANSH6 31:16 — — — — — — — — — — 15:0 — — TRISH13 TRISH12 — TRISH10 TRISH9 TRISH8 — TRISH6 31:16 — — — — — — — — — — 15:0 — — RH13 RH12 — RH10 RH9 RH8 — RH6 31:16 — — — — — — — — — — 15:0 — — LATH13 LATH12 — LATH10 LATH9 LATH8 — 31:16 — — — — — — — — 15:0 — — ODCH13 ODCH12 — ODCH10 ODCH9 31:16 — — — — — — — 15:0 — — 31:16 — — 15:0 — — 31:16 — — CNPUH13 CNPUH12 — — CNPDH13 CNPDH12 — — — — CNPUH10 CNPUH9 — — CNPDH10 CNPDH9 0000 18/2 — — — — — ANSH5 ANSH4 — — ANSH1 — — — — — TRISH5 TRISH4 — — TRISH1 — — — — — — 0000 RH5 RH4 — — RH1 RH0 xxxx — — — — — — 0000 LATH6 LATH5 LATH4 — — LATH1 LATH0 xxxx — — — — — — — — 0000 ODCH8 — ODCH6 ODCH5 ODCH4 — — ODCH1 — — — — — — — — — — — — — — — CNPDH8 — CNPUH6 CNPUH5 CNPUH4 — — — CNPDH6 CNPDH5 CNPDH4 17/1 — 19/3 — 21/5 16/0 20/4 CNPUH8 22/6 All Resets 0700 ANSELH Bit Range Register Name(1) Virtual Address (BF86_#) Bits — ANSH0 0073 — 0000 TRISH0 3773 ODCH0 0000 — 0000 CNPUH1 CNPUH0 0000 — — 0000 CNPDH1 CNPDH0 0000 — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 CNENH8 — — — — — — CN STATH1 15:0 ON — — — EDGE DETECT 31:16 — — — — — 15:0 — — 31:16 — — — — — — — — — — — — CN STATH13 CN STATH12 — CN STATH10 CN STATH9 CN STATH8 — CN STATH6 CN STATH5 CN STATH4 — — — — — — — — — — — — — — CNENH13 CNENH12 — CNENH10 CNENH9 15:0 — — 31:16 — — 15:0 — — 31:16 — — — — — — 15:0 — — CNFH13 CNFH12 — CNFH10 CNNEH13 CNNEH12 — CNENH6 CNENH5 CNENH4 CNENH1 CNENH0 0000 — — CNNEH8 — — — — — — — — — — CNFH9 CNFH8 — CNFH6 CNFH5 CNFH4 — — CNFH1 CNNEH10 CNNEH9 CNNEH6 CNNEH5 CNNEH4 — — 0000 CN 0000 STATH0 — 0000 CNNEH1 CNNEH0 0000 — 0000 CNFH0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. DS60001320H-page 281 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 12-17: PORTH REGISTER MAP FOR 124-PIN DEVICES ONLY 0710 TRISH 0720 PORTH 0730 LATH 0740 ODCH 0750 CNPUH 0760 CNPDH 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 31:16 — — — — — — — — — — 15:0 — — — — — — — — — ANSH6 0780 CNENH  2015-2021 Microchip Technology Inc. 07A0 CNNEH 07B0 CNFH Legend: Note 1: 20/4 19/3 18/2 17/1 — — — — — ANSH5 ANSH4 — — ANSH1 — — — — — — — — — — — — — — — 15:0 TRISH15 TRISH14 TRISH13 TRISH12 TRISH11 TRISH10 TRISH9 TRISH8 TRISH7 TRISH6 TRISH5 TRISH4 TRISH3 TRISH2 TRISH1 16/0 — 0000 ANSH0 0073 — 0000 TRISH0 FFFF 31:16 — — — — — — — — — — — — — — — — 0000 15:0 RH15 RH14 RH13 RH12 RH11 RH10 RH9 RH8 RH7 RH6 RH5 RH4 RH3 RH2 RH1 RH0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 LATH15 LATH14 LATH13 LATH12 LATH11 LATH10 LATH9 LATH8 LATH7 LATH6 LATH5 LATH4 LATH3 LATH2 LATH1 LATH0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ODCH15 ODCH14 ODCH13 ODCH12 ODCH11 ODCH10 ODCH9 ODCH8 ODCH7 ODCH6 ODCH5 ODCH4 ODCH3 ODCH2 ODCH1 31:16 — — — — — — — — — — — — — 15:0 CNPUH15 CNPUH14 CNPUH13 CNPUH12 CNPUH11 CNPUH10 CNPUH9 31:16 — — — — — — — 15:0 CNPDH15 CNPDH14 CNPDH13 CNPDH12 CNPDH11 CNPDH10 CNPDH9 — — — — — — — — — — 0000 CNPDH6 CNPDH5 CNPDH4 CNPDH3 CNPDH2 CNPDH1 CNPDH0 0000 — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — — — — 0000 — — 31:16 — — — — — 15:0 CNENH15 CNENH14 CNENH13 CNENH12 CNENH11 CNENH10 CNENH9 — — CNPDH7 0000 — — 31:16 — CNPDH8 — CNPUH6 CNPUH5 CNPUH4 CNPUH3 CNPUH2 CNPUH1 CNPUH0 0000 — ON — — CNPUH7 — 15:0 CN 15:0 STATH15 — CNPUH8 ODCH0 0000 — EDGE DETECT 31:16 0790 CNSTATH 21/5 31:16 31:16 0770 CNCONH 22/6 All Resets 0700 ANSELH Bit Range Register Name(1) Virtual Address (BF86_#) Bits — — CNENH8 CNENH7 CNENH6 CNENH5 CNENH4 CNENH3 CNENH2 CNENH1 CNENH0 0000 — — — — — — — — — — — — — — CN STATH14 CN STATH13 CN STATH12 CN STATH11 CN STATH10 CN STATH9 CN STATH8 CN STATH7 CN STATH6 CN STATH5 CN STATH4 CN STATH3 CN STATH2 CN STATH1 — — — — — — — — — — — — 15:0 CNNEH15 CNNEH14 CNNEH13 CNNEH12 CNNEH11 CNNEH10 CNNEH9 — — CNNEH8 CNNEH7 — 0000 CN 0000 STATH0 — 0000 CNNEH6 CNNEH5 CNNEH4 CNNEH3 CNNEH2 CNNEH1 CNNEH0 0000 31:16 — — — — — — — — — — — — — — — 15:0 CNFH15 CNFH14 CNFH13 CNFH12 CNFH11 CNFH10 CNFH9 CNFH8 CNFH7 CNFH6 CNFH5 CNFH4 CNFH3 CNFH2 CNFH1 — 0000 CNFH0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 282 TABLE 12-18: PORTH REGISTER MAP FOR 144-PIN DEVICES ONLY 0800 ANSELJ 0810 TRISJ 0820 PORTJ 0830 LATJ 0840 ODCJ 0850 CNPUJ 0860 CNPDJ 0870 CNCONJ 0880 CNENJ 08A0 CNNEJ 08B0 CNFJ Legend: Note 1: 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — 0000 ANSJ9 ANSJ8 — — — — — — — — 0B00 — — — — — — — — — — 0000 TRISJ9 TRISJ8 — — — TRISJ4 — TRISJ2 TRISJ1 — — — — — — — — — — 0000 RJ9 RJ8 — — — RJ4 — RJ2 RJ1 RJ0 xxxx — — — — — — — — — — 0000 — LATJ9 LATJ8 — — — LATJ4 — LATJ2 LATJ1 LATJ0 xxxx — — — — — — — — — — — — 0000 ODCJ11 — ODCJ9 ODCJ8 — — — ODCJ4 — ODCJ2 ODCJ1 — — — — — — — — — — — — — CNPUJ11 — CNPUJ9 CNPUJ8 — — — CNPUJ4 — — — — — — — — — — — — CNPDJ11 — CNPDJ9 CNPDJ8 — — — CNPDJ4 — — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 CNENJ9 CNENJ8 31/15 30/14 29/13 28/12 27/11 26/10 31:16 — — — 15:0 — — — — — — — ANSJ11 — 31:16 — — — — — — 15:0 — — — — TRISJ11 — 31:16 15:0 — — — — — — — — — — RJ11 — 31:16 — — — — — — 15:0 — — — — LATJ11 31:16 — — — — 15:0 — — — — 31:16 — — — 15:0 — — — 31:16 — — — 15:0 — — — 31:16 — — — 15:0 ON — — — EDGE DETECT 31:16 — — — — — 15:0 31:16 0890 CNSTATJ 24/8 All Resets Bit Range Register Name(1) Virtual Address (BF86_#) Bits CNENJ11 — — — 25/9 CNENJ4 — — — — — CN STATJ11 — CN STATJ9 CN STATJ8 — — — TRISJ0 0B17 ODCJ0 0000 — 0000 CNPUJ2 CNPUJ1 CNPUJ0 0000 — — — 0000 CNPDJ2 CNPDJ1 CNPDJ0 0000 CNENJ2 CNENJ1 CNENJ0 0000 — — — — — — — CN STATJ4 — CN STATJ2 CN STATJ1 — — 15:0 — — — — 31:16 — — — — — — — — — — — — — 15:0 — — — — CNNEJ11 — CNNEJ9 CNNEJ8 — — — CNNEJ4 — 31:16 — — — — — — — — — — — — — 15:0 — — — — CNFJ11 — CNFJ9 CNFJ8 — — — CNFJ4 — 0000 CN 0000 STATJ0 — 0000 CNNEJ2 CNNEJ1 CNNEJ0 0000 — — — 0000 CNFJ2 CNFJ1 CNFJ0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. DS60001320H-page 283 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 12-19: PORTJ REGISTER MAP FOR 124-PIN DEVICES ONLY 0800 ANSELJ 0810 TRISJ 0820 PORTJ 0830 LATJ 0840 ODCJ 0850 CNPUJ 0860 CNPDJ 31/15 30/14 29/13 28/12 31:16 — — — 15:0 — — — 31:16 — — 15:0 TRISJ15 TRISJ14 0880 CNENJ 0890 CNSTATJ 08A0 CNNEJ  2015-2021 Microchip Technology Inc. 08B0 CNFJ Legend: Note 1: 26/10 — — — — ANSJ11 — — — — — TRISJ13 TRISJ12 TRISJ11 TRISJ10 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — 0000 ANSJ9 ANSJ8 — — — — — — — — 0B00 — — — — — — — — — — 0000 TRISJ9 TRISJ8 TRISJ7 TRISJ6 TRISJ5 TRISJ4 TRISJ3 TRISJ2 TRISJ1 25/9 TRISJ0 FFFF 31:16 — — — — — — — — — — — — — — — — 0000 15:0 RJ15 RJ14 RJ13 RJ12 RJ11 RJ10 RJ9 RJ8 RJ7 RJ6 RJ5 RJ4 RJ3 RJ2 RJ1 RJ0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 LATJ15 LATJ14 LATJ13 LATJ12 LATJ11 LATJ10 LATJ9 LATJ8 LATJ7 LATJ6 LATJ5 LATJ4 LATJ3 LATJ2 LATJ1 LATJ0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ODCJ15 ODCJ14 ODCJ13 ODCJ12 ODCJ11 ODCJ10 ODCJ9 ODCJ18 ODCJ7 ODCJ6 ODCJ5 ODCJ4 ODCJ3 ODCJ2 ODCJ1 31:16 — — — — — — — — — — — 15:0 CNPUJ15 CNPUJ14 CNPUJ13 CNPUJ12 CNPUJ11 CNPUJ10 31:16 — — — — — — 15:0 CNPDJ15 CNPDJ14 CNPDJ13 CNPDJ12 CNPDJ11 CNPDJ10 31:16 0870 CNCONJ 27/11 All Resets Bit Range Register Name(1) Virtual Address (BF86_#) Bits — — — — — — — CNPUJ9 CNPUJ8 CNPUJ7 CNPUJ6 — — — — CNPDJ9 CNPDJ8 CNPDJ7 CNPDJ6 ODCJ0 0000 — 0000 CNPUJ5 CNPUJ4 CNPUJ3 CNPUJ2 CNPUJ1 CNPUJ0 0000 — — — — — — 0000 CNPDJ5 CNPDJ4 CNPDJ3 CNPDJ2 CNPDJ1 CNPDJ0 0000 — — — — — — — — — — — — — 0000 — — — — — — — — — — — 0000 — — — — — — — 0000 15:0 ON — — — EDGE DETECT 31:16 — — — — — 15:0 CNENJ15 CNENJ14 CNENJ13 CNENJ12 CNENJ11 CNENJ10 — — — — CNENJ9 CNENJ8 CNENJ7 CNENJ6 CNENJ5 CNENJ4 CNENJ3 CNENJ2 CNENJ1 CNENJ0 0000 31:16 — — — — — — — — — — — — — — — 15:0 CN STATJ15 CN STATJ14 CN STATJ13 CN STATJ12 CN STATJ11 CN STATJ10 CN STATJ9 CN STATJ8 CN STATJ7 CN STATJ6 CN STATJ5 CN STATJ4 CN STATJ3 CN STATJ2 CN STATJ1 31:16 — — — — — — — — — — — 15:0 CNNEJ15 CNNEJ14 CNNEJ13 CNNEJ12 CNNEJ11 CNNEJ10 — — — — CNNEJ9 CNNEJ8 CNNEJ7 CNNEJ6 — 0000 CN 0000 STATJ0 — 0000 CNNEJ5 CNNEJ4 CNNEJ3 CNNEJ2 CNNEJ1 CNNEJ0 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 CNFJ15 CNFJ14 CNFJ13 CNFJ12 CNFJ11 CNFJ10 CNFJ9 CNFJ8 CNFJ7 CNFJ6 CNFJ5 CNFJ4 CNFJ3 CNFJ2 CNFJ1 CNFJ0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 284 TABLE 12-20: PORTJ REGISTER MAP FOR 144-PIN DEVICES ONLY Virtual Address (BF86_#) Register Name(1) 0910 TRISK 0920 PORTK 0930 LATK 0940 ODCK 0950 CNPUK 0960 CNPDK 0970 CNCONK 0980 CNENK 0990 CNSTATK 09A0 CNNEK 09B0 CNFK Legend: Note 1: 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Bits — 0000 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — TRISK7 TRISK6 TRISK5 TRISK4 TRISK3 TRISK2 TRISK1 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — RK7 RK6 RK5 RK4 RK3 RK2 RK1 RK0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — LATK7 LATK6 LATK5 LATK4 LATK3 LATK2 LATK1 LATK0 xxxx 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — ODCK7 ODCK6 ODCK5 ODCK4 ODCK3 ODCK2 ODCK1 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — CNPUK7 31:16 — — — — — — — — — 15:0 — — — — — — — — CNPDK7 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ON — — — EDGE DETECT — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — CNENK7 31:16 — — — — — — — — — — — — — — — CN STATK7 CN STATK6 CN STATK5 CN STATK4 CN STATK3 CN STATK2 CN STATK1 — — — — — — TRISK0 00FF ODCK0 0000 — 0000 CNPUK6 CNPUK5 CNPUK4 CNPUK3 CNPUK2 CNPUK1 CNPUK0 0000 — — — — — — — 0000 CNPDK6 CNPDK5 CNPDK4 CNPDK3 CNPDK2 CNPDK1 CNPDK0 0000 CNENK6 CNENK5 CNENK4 CNENK3 CNENK2 CNENK1 CNENK0 0000 15:0 — — — — — — — — 31:16 — — — — — — — — — 15:0 — — — — — — — — CNNEK7 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — CNFK7 CNFK6 CNFK5 CNFK4 CNFK3 CNFK2 CNFK1 — 0000 CN 0000 STATK0 — 0000 CNNEK6 CNNEK5 CNNEK4 CNNEK3 CNNEK2 CNNEK1 CNNEK0 0000 — 0000 CNFK0 0000 x = Unknown value on Reset; — = Unimplemented, read as ‘0’; Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8, and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. DS60001320H-page 285 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 12-21: PORTK REGISTER MAP FOR 144-PIN DEVICES ONLY 1408 140C 1410 1418 141C 1420 1424 1428 142C  2015-2021 Microchip Technology Inc. 1430 1434 1438 143C 1440 Legend: Note 1: 2: INT1R INT2R INT3R INT4R T2CKR T3CKR T4CKR T5CKR T6CKR T7CKR T8CKR T9CKR IC1R IC2R IC3R All Resets Bit Range Register Name Virtual Address (BF80_#) 1404 Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register is not available on 64-pin devices. This register is not available on devices without a CAN module. INT1R — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 INT2R — 0000 INT3R — 0000 INT4R — 0000 T2CKR — 0000 T3CKR — 0000 T4CKR — 0000 T5CKR — 0000 T6CKR — 0000 T7CKR — 0000 T8CKR — 0000 T9CKR — 0000 IC1R — 0000 IC2R — IC3R 0000 0000 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 286 TABLE 12-22: PERIPHERAL PIN SELECT INPUT REGISTER MAP 1444 IC4R 1448 IC5R 144C IC6R 1450 IC7R 1454 IC8R 1458 IC9R 1460 OCFAR 1468 146C U1RXR U1CTSR 1470 1474 U2RXR U2CTSR 1478 147C U3RXR U3CTSR DS60001320H-page 287 1480 1484 U4RXR U4CTSR Legend: Note 1: 2: All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register is not available on 64-pin devices. This register is not available on devices without a CAN module. IC4R — — — — — — — — — — — — — 0000 IC5R — 0000 IC6R — 0000 IC7R — 0000 IC8R — 0000 IC9R — 0000 OCFAR — — — — — 0000 U1RXR — 0000 U1CTSR — — — — — 0000 U2RXR — 0000 U2CTSR — — — — — 0000 U3RXR — 0000 U3CTSR — — — — — 0000 U4RXR — U4CTSR 0000 0000 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 12-22: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED) 1488 148C U5RXR U5CTSR 1490 1494 U6RXR U6CTSR 149C SDI1R 14A0 SS1R 14A8 SDI2R 14AC SS2R 14B4 SDI3R 14B8 SS3R  2015-2021 Microchip Technology Inc. 14C0 SDI4R 14C4 SS4R 14CC SDI5R(1) 14D0 SS5R(1) 14D8 SDI6R(1) Legend: Note 1: 2: All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register is not available on 64-pin devices. This register is not available on devices without a CAN module. U5RXR — — — 0000 U5CTSR — — — — — 0000 U6RXR — 0000 U6CTSR — — — — — — — — — — — — — — — — — — — — — — — 0000 SDI1R — 0000 SS1R — 0000 SDI2R — 0000 SS2R — 0000 SDI3R — 0000 SS3R — 0000 SDI4R — 0000 SS4R — 0000 SDI5R — 0000 SS5R — SDI6R 0000 0000 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 288 TABLE 12-22: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED) 14DC 14E0 14E4 14E8 14F0 14F4 SS6R(1) C1RXR(2) C2RXR(2) REFCLKI1R REFCLKI3R REFCLKI4R Legend: Note 1: 2: All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — — 0000 — 0000 — 0000 — 0000 — 0000 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — 31:16 — — — — — — — — — — — — 15:0 — — — — — — — — — — — — x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register is not available on 64-pin devices. This register is not available on devices without a CAN module. SS6R — — — — — — — 0000 C1RXR — 0000 C2RXR — 0000 REFCLKI1R — — — 0000 REFCLKI3R — — — REFCLKI4R 0000 0000 DS60001320H-page 289 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 12-22: PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8  2015-2021 Microchip Technology Inc. 31:16 — — — — — — — — — — — — — — — — 15:0 31:16 — — — — — — — — (1) 153C RPA15R 15:0 — — — — — — — — — — — — — — — — 31:16 1540 RPB0R — — — — — — — — 15:0 31:16 — — — — — — — — 1544 RPB1R — — — — — — — — 15:0 31:16 — — — — — — — — 1548 RPB2R 15:0 — — — — — — — — — — — — — — — — 31:16 154C RPB3R — — — — — — — — 15:0 31:16 — — — — — — — — 1554 RPB5R — — — — — — — — 15:0 31:16 — — — — — — — — 1558 RPB6R 15:0 — — — — — — — — — — — — — — — — 31:16 155C RPB7R — — — — — — — — 15:0 31:16 — — — — — — — — 1560 RPB8R — — — — — — — — 15:0 31:16 — — — — — — — — 1564 RPB9R 15:0 — — — — — — — — — — — — — — — — 31:16 1568 RPB10R — — — — — — — — 15:0 31:16 — — — — — — — — 1578 RPB14R — — — — — — — — 15:0 — — — — — — — — 31:16 157C RPB15R — — — — — — — — 15:0 31:16 — — — — — — — — (1) 1584 RPC1R — — — — — — — — 15:0 31:16 — — — — — — — — (1) 1588 RPC2R 15:0 — — — — — — — — 31:16 — — — — — — — — (1) 158C RPC3R — — — — — — — — 15:0 31:16 — — — — — — — — (1) 1590 RPC4R 15:0 — — — — — — — — Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register is not available on 64-pin devices. 2: This register is not available on 64-pin and 100-pin devices. 1538 RPA14R(1) 23/7 22/6 21/5 20/4 19/3 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 18/2 17/1 — — RPA14R — — RPA15R — — RPB0R — — RPB1R — — RPB2R — — RPB3R — — RPB5R — — RPB6R — — RPB7R — — RPB8R — — RPB9R — — RPB10R — — RPB14R — — RPB15R — — RPC1R — — RPC2R — — RPC3R — — RPC4R 16/0 — — — — — — — — — — — — — — — — — — All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 290 TABLE 12-23: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 DS60001320H-page 291 — — — — — — — — 31:16 — — — — — — — — 15:0 31:16 — — — — — — — — 15B8 RPC14R — — — — — — — — 15:0 31:16 — — — — — — — — 15C0 RPD0R 15:0 — — — — — — — — — — — — — — — — 31:16 15C4 RPD1R — — — — — — — — 15:0 31:16 — — — — — — — — 15C8 RPD2R — — — — — — — — 15:0 31:16 — — — — — — — — 15CC RPD3R 15:0 — — — — — — — — — — — — — — — — 31:16 15D0 RPD4R — — — — — — — — 15:0 31:16 — — — — — — — — 15D4 RPD5R — — — — — — — — 15:0 31:16 — — — — — — — — (2) 15D8 RPD6R 15:0 — — — — — — — — 31:16 — — — — — — — — (2) 15DC RPD7R — — — — — — — — 15:0 31:16 — — — — — — — — 15E4 RPD9R — — — — — — — — 15:0 31:16 — — — — — — — — 15E8 RPD10R 15:0 — — — — — — — — — — — — — — — — 31:16 15EC RPD11R — — — — — — — — 15:0 31:16 — — — — — — — — (1) 15F0 RPD12R 15:0 — — — — — — — — — — — — — — — — (1) 31:16 15F8 RPD14R — — — — — — — — 15:0 — — — — — — — — (1) 31:16 15FC RPD15R — — — — — — — — 15:0 31:16 — — — — — — — — 160C RPE3R 15:0 — — — — — — — — — — — — — — — — 31:16 1614 RPE5R — — — — — — — — 15:0 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register is not available on 64-pin devices. 2: This register is not available on 64-pin and 100-pin devices. 15B4 RPC13R 23/7 22/6 21/5 20/4 19/3 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 18/2 17/1 — — RPC13R — — RPC14R — — RPD0R — — RPD1R — — RPD2R — — RPD3R — — RPD4R — — RPD5R — — RPD6R — — RPD7R — — RPD9R — — RPD10R — — RPD11R — — RPD12R — — RPD14R — — RPD15R — — RPE3R — — RPE5R 16/0 — — — — — — — — — — — — — — — — — — All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 12-23: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8  2015-2021 Microchip Technology Inc. 31:16 — — — — — — — — — — — — — — — — 15:0 31:16 — — — — — — — — (1) 1624 RPE9R — — — — — — — — 15:0 31:16 — — — — — — — — 1640 RPF0R 15:0 — — — — — — — — — — — — — — — — 31:16 1644 RPF1R — — — — — — — — 15:0 31:16 — — — — — — — — (1) 1648 RPF2R — — — — — — — — 15:0 31:16 — — — — — — — — 164C RPF3R 15:0 — — — — — — — — — — — — — — — — 31:16 1650 RPF4R — — — — — — — — 15:0 31:16 — — — — — — — — 1654 RPF5R — — — — — — — — 15:0 31:16 — — — — — — — — (1) 1660 RPF8R 15:0 — — — — — — — — — — — — — — — — (1) 31:16 1670 RPF12R — — — — — — — — 15:0 — — — — — — — — (1) 31:16 1674 RPF13R — — — — — — — — 15:0 31:16 — — — — — — — — (1) 1680 RPG0R 15:0 — — — — — — — — 31:16 — — — — — — — — (1) 1684 RPG1R — — — — — — — — 15:0 31:16 — — — — — — — — 1698 RPG6R 15:0 — — — — — — — — — — — — — — — — 31:16 169C RPG7R — — — — — — — — 15:0 31:16 — — — — — — — — 16A0 RPG8R — — — — — — — — 15:0 31:16 — — — — — — — — 16A4 RPG9R 15:0 — — — — — — — — Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register is not available on 64-pin devices. 2: This register is not available on 64-pin and 100-pin devices. 1620 RPE8R(1) 23/7 22/6 21/5 20/4 19/3 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 18/2 17/1 — — RPE8R — — RPE9R — — RPF0R — — RPF1R — — RPF2R — — RPF3R — — RPF4R — — RPF5R — — RPF8R — — RPG12R — — RPG0R — — RPG1R — — RPG1R — — RPG6R — — RPG7R — — RPG8R — — RPG9R 16/0 — — — — — — — — — — — — — — — — — All Resets Bit Range Register Name Virtual Address (BF80_#) Bits 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 292 TABLE 12-23: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 12-1: Bit Range 31:24 23:16 15:8 7:0 [pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — [pin name]R Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as ‘0’ bit 3-0 [pin name]R: Peripheral Pin Select Input bits Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 12-2 for input pin selection values. Note: Register values can only be changed if the IOLOCK Configuration bit (CFGCON) = 0. REGISTER 12-2: Bit Range 31:24 23:16 15:8 7:0 RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — RPnR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-4 Unimplemented: Read as ‘0’ bit 3-0 RPnR: Peripheral Pin Select Output bits See Table 12-3 for output pin selection values. Note: x = Bit is unknown Register values can only be changed if the IOLOCK Configuration bit (CFGCON) = 0.  2015-2021 Microchip Technology Inc. DS60001320H-page 293 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 12-3: Bit Range 31:24 23:16 15:8 7:0 CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A – K) Bit Bit 31/23/15/7 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 ON — — — EDGEDETECT — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Change Notice (CN) Control ON bit 1 = CN is enabled 0 = CN is disabled bit 14-12 Unimplemented: Read as ‘0’ bit 11 EDGEDETECT: Change Notification Style bit 1 = Edge Style. Detect edge transitions (CNFx used for CN Event). 0 = Mismatch Style. Detect change from last PORTx read (CNSTATx used for CN Event). bit 10-0 Unimplemented: Read as ‘0’ DS60001320H-page 294  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 13.0 Note: TIMER1 The following modes are supported by Timer1: • • • • This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (DS60001105) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 13.1 Additional Supported Features • Selectable clock prescaler • Timer operation during Sleep and Idle modes • Fast bit manipulation using CLR, SET and INV registers • Asynchronous mode can be used with the SOSC to function as a real-time clock • ADC event trigger PIC32MZ EF devices feature one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Low-Power Secondary Oscillator (SOSC) for real-time clock applications. FIGURE 13-1: Synchronous Internal Timer Synchronous Internal Gated Timer Synchronous External Timer Asynchronous External Timer TIMER1 BLOCK DIAGRAM PR1 Equal Trigger to ADC 16-bit Comparator TSYNC 1 Reset T1IF Event Flag Sync TMR1 0 0 1 Q TGATE D Q TGATE TCS ON SOSCO/T1CK x1 SOSCEN(1) SOSCI Gate Sync PBCLK3 10 00 Prescaler 1, 8, 64, 256 2 TCKPS Note 1: The default state of the SOSCEN bit (OSCCON) during a device Reset is controlled by the FSOSCEN bit in Configuration Word, DEVCFG1.  2015-2021 Microchip Technology Inc. DS60001320H-page 295 Timer1 Control Register Virtual Address (BF84_#) TABLE 13-1: TMR1 0020 PR1 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 31:16 — — — 15:0 ON — SIDL 31:16 — — — — — — — — TWDIS TWIP — — — — — 15:0 31:16 15:0 23/7 22/6 21/5 20/4 19/3 — — — — — — — TGATE — TCKPS — — — — — — — — — — — 18/2 17/1 16/0 — — — 0000 TSYNC TCS — 0000 — — — 0000 — — — TMR1 — — — — — — — — — PR1 All Resets Register Name(1) Bit Range Bits 0000 T1CON 0010 TIMER1 REGISTER MAP 0000 0000 FFFF Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information.  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 296 13.2 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 13-1: Bit Range 31:24 23:16 15:8 7:0 T1CON: TYPE A TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0 ON — SIDL TWDIS TWIP — — — R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 TGATE — — TSYNC TCS — TCKPS Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Timer On bit 1 = Timer is enabled 0 = Timer is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation even in Idle mode bit 12 TWDIS: Asynchronous Timer Write Disable bit 1 = Writes to TMR1 are ignored until pending write operation completes 0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality) bit 11 TWIP: Asynchronous Timer Write in Progress bit In Asynchronous Timer mode: 1 = Asynchronous write to TMR1 register in progress 0 = Asynchronous write to TMR1 register complete In Synchronous Timer mode: This bit is read as ‘0’. bit 10-8 Unimplemented: Read as ‘0’ bit 7 TGATE: Timer Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6 Unimplemented: Read as ‘0’ bit 5-4 TCKPS: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value bit 3 Unimplemented: Read as ‘0’  2015-2021 Microchip Technology Inc. DS60001320H-page 297 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED) bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored. bit 1 TCS: Timer Clock Source Select bit 1 = External clock from T1CKI pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as ‘0’ DS60001320H-page 298  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 14.0 Note: TIMER2/3, TIMER4/5, TIMER6/7, AND TIMER8/9 Four 32-bit synchronous timers are available by combining Timer2 with Timer3, Timer4 with Timer5, Timer6 with Timer7, and Timer8 with Timer9. This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (DS60001105) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The 32-bit timers can operate in one of three modes: • Synchronous internal 32-bit timer • Synchronous internal 32-bit gated timer • Synchronous external 32-bit timer 14.1 Additional Supported Features • Selectable clock prescaler • Timers operational during CPU idle • Time base for Input Capture and Output Compare modules (Timer2 through Timer7 only) • ADC event trigger (Timer3 and Timer5 only) • Fast bit manipulation using CLR, SET, and INV registers The PIC32MZ EF family of devices features eight synchronous 16-bit timers (default) that can operate as a free-running interval timer for various timing applications and counting external events. The following modes are supported: • Synchronous internal 16-bit timer • Synchronous internal 16-bit gated timer • Synchronous external 16-bit timer FIGURE 14-1: TIMER2 THROUGH TIMER9 BLOCK DIAGRAM (16-BIT) Reset Trigger to ADC (1) Equal Sync TMRx Comparator x 16 PRx TxIF Event Flag 0 1 TGATE Q TGATE D Q TCS ON TxCK x1 Gate Sync PBCLK3 Note 1: 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS The ADC event trigger is available on Timer3 and Timer5 only.  2015-2021 Microchip Technology Inc. DS60001320H-page 299 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 14-2: TIMER2/3, TIMER4/5, TIMER6/7, AND TIMER8/9 BLOCK DIAGRAM (32-BIT) Reset TMRy(2) MS Half Word ADC Event Trigger(1) TMRx(2) LS Half Word 32-bit Comparator Equal PRy(2) TyIF Event Flag(2) Sync PRx(2) 0 1 TGATE Q D TGATE Q TCS ON TxCK(2) x1 Gate Sync PBCLK3 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 10 00 3 TCKPS Note 1: 2: ADC event trigger is available only on the Timer2/3 and TImer4/5 pairs. In this diagram, ‘x’ represents Timer2, 4, 6, or 8, and ‘y’ represents Timer3, 5, 7, or 9. DS60001320H-page 300  2015-2021 Microchip Technology Inc. Timer2-Timer9 Control Registers Virtual Address (BF84_#) TABLE 14-1: 0210 TMR2 0220 PR2 TMR3 TMR4 27/11 26/10 25/9 24/8 ON — — — — — — — SIDL — — — — 31:16 — — — — — — — 15:0 — — — — — — — 0A10 TMR6 — TGATE — — — — — — — — — — — — 15:0 ON — SIDL — — — — — TGATE 31:16 — — — — — — — — — 15:0 20/4 — — TCKPS 19/3 18/2 17/1 16/0 — — — — 0000 T32 — TCS — 0000 0000 — — — — — — — — — — — — — — — — — — — — — 0000 — — TCS — 0000 0000 0000 — — — — — — — — — TCKPS — — — — — — — — — — — — — — — — — — — — — 0000 T32 — TCS — 0000 0000 0000 PR3 31:16 — — — — — — — — — 15:0 ON — SIDL — — — — — TGATE 31:16 — — — — — — — — — 15:0 — — — — — — — — TCKPS — — — — — — — — — — — — — — — — — — — — — 0000 — — TCS — 0000 0000 0000 PR4 31:16 — — — — — — — — — 15:0 ON — SIDL — — — — — TGATE 31:16 — — — — — — — — — 15:0 — — — — — — — — TCKPS — — — — — — — — — — — — — — — — — — — — — 0000 T32 — TCS — 0000 0000 0000 PR5 31:16 — — — — — — — — — 15:0 ON — SIDL — — — — — TGATE 31:16 — — — — — — — — — 15:0 DS60001320H-page 301 — — — — — — — — TCKPS — — — — — — — — — — — — — — — — — — — — — 0000 — — TCS — 0000 0000 PR6 31:16 — — — — — — — — — 15:0 ON — SIDL — — — — — TGATE 0000 FFFF TMR6 — 0000 FFFF TMR5 — 0000 FFFF TMR4 — 0000 FFFF TMR3 15:0 0C00 T7CON — — — 31:16 PR6 — 21/5 PR2 15:0 0A00 T6CON 22/6 31:16 31:16 PR5 23/7 TMR2 15:0 TMR5 0A20 — 15:0 31:16 PR4 0820 28/12 15:0 0800 T5CON 0810 31:16 31:16 PR3 0620 29/13 15:0 0600 T4CON 0610 30/14 31:16 0400 T3CON 0420 31/15 All Resets Register Name(1) Bit Range Bits 0200 T2CON 0410 TIMER2 THROUGH TIMER9 REGISTER MAP 0000 FFFF TCKPS Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. 14.2 Virtual Address (BF84_#) 0C20 0E10 TMR8 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 T32 — TCS — 0000 0000 TMR7 — — — — — — — TMR9 — — — — — — — — — — 15:0 ON — SIDL — — — — — TGATE 31:16 — — — — — — — — — 15:0 — — — — — — — — — — — — — — — — — 15:0 ON — SIDL — — — — — TGATE 31:16 — — — — — — — — — 15:0 31:16 15:0 TCKPS — — — — — — — — — — — — — — — — — — — — — 0000 — — TCS — 0000 0000 0000 PR8 31:16 — — — — — — — — PR9 0000 FFFF TCKPS — — — — — — — — — — — — — — TMR9 — 0000 FFFF TMR8 — 0000 0000 PR7 15:0 1000 T9CON — 31:16 31:16 PR8 PR9 30/14 15:0 0E00 T8CON 1020 31/15 15:0 31:16 PR7 0E20 31:16 All Resets Register Name(1) Bit Range Bits 0C10 TMR7 1010 TIMER2 THROUGH TIMER9 REGISTER MAP (CONTINUED) 0000 0000 FFFF Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information.  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 302 TABLE 14-1: PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 14-1: Bit Range 31:24 23:16 15:8 7:0 TxCON: TYPE B TIMER CONTROL REGISTER (‘x’ = 2-9) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON(1) — SIDL(2) — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 T32(3) — TCS(1) — TGATE(1) TCKPS(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Timer On bit(1) 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit(2) 1 = Discontinue operation when device enters Idle mode 0 = Continue operation even in Idle mode x = Bit is unknown bit 12-8 Unimplemented: Read as ‘0’ bit 7 TGATE: Timer Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored and is read as ‘0’. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled bit 6-4 TCKPS: Timer Input Clock Prescale Select bits(1) 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value bit 3 T32: 32-Bit Timer Mode Select bit(3) 1 = Odd numbered and even numbered timers form a 32-bit timer 0 = Odd numbered and even numbered timers form separate 16-bit timers Note 1: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5, Timer7, and Timer9). All timer functions are set through the even numbered timers. While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. This bit is available only on even numbered timers (Timer2, Timer4, Timer6, and Timer8). 2: 3:  2015-2021 Microchip Technology Inc. DS60001320H-page 303 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 14-1: TxCON: TYPE B TIMER CONTROL REGISTER (‘x’ = 2-9) (CONTINUED) bit 2 Unimplemented: Read as ‘0’ bit 1 TCS: Timer Clock Source Select bit(1) 1 = External clock from TxCK pin 0 = Internal peripheral clock bit 0 Unimplemented: Read as ‘0’ Note 1: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, Timer5, Timer7, and Timer9). All timer functions are set through the even numbered timers. While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. This bit is available only on even numbered timers (Timer2, Timer4, Timer6, and Timer8). 2: 3: DS60001320H-page 304  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 15.0 DEADMAN TIMER (DMT) Note: The DMT consists of a 32-bit counter with a time-out count match value as specified by the DMTCNT bits in the DEVCFG1 Configuration register. This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog, Deadman, and Power-up Timers” (DS60001114) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). A Deadman Timer is typically used in mission critical and safety critical applications, where any single failure of the software functionality and sequencing must be detected. Figure 15-1 shows a block diagram of the Deadman Timer module. The primary function of the Deadman Timer (DMT) is to reset the processor in the event of a software malfunction. The DMT is a free-running instruction fetch timer, which is clocked whenever an instruction fetch occurs until a count match occurs. Instructions are not fetched when the processor is in Sleep mode. FIGURE 15-1: DEADMAN TIMER BLOCK DIAGRAM “improper sequence” flag ON Instruction Fetched Strobe Force DMT Event System Reset Counter Initialization Value PBCLK7 Clock “Proper Clear Sequence” Flag ON 32-bit counter ON 32 DMT event to NMI(3) DMT Count Reset Load System Reset (COUNTER) = DMT Max Count(1)  (COUNTER)  DMT Window Interval(2) Window Interval Open Note 1: 2: 3: DMT Max Count is controlled by the DMTCNT bits in the DEVCFG1 Configuration register. DMT Window Interval is controlled by the DMTINTV bits in the DEVCFG1 Configuration register. Refer to Section 6.0 “Resets” for more information.  2015-2021 Microchip Technology Inc. DS60001320H-page 305 Deadman Timer Control Registers Virtual Address (BF80_#) Register Name TABLE 15-1: 0A00 DMTCON DEADMAN TIMER REGISTER MAP 0A10 DMTPRECLR 0A20 DMTCLR 0A30 DMTSTAT 0A40 DMTCNT 0A60 DMTPSCNT 0A70 DMTPSINTV Legend: All Resets Bit Range Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 — — — — — — — — — — — — — — — — 0000 15:0 ON — — — — — — — — — — — — — — — x000 31:16 — — — — — — — — — — — — — — — — 0000 — — — — — — — — 0000 — — — — — — — — 0000 — 15:0 STEP1 31:16 — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — BAD1 BAD2 DMTEVENT — — — — 31:16 15:0 31:16 15:0 31:16 15:0 STEP2 COUNTER PSCNT PSINTV x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0000 0000 WINOPN 0000 0000 0000 0000 00xx 0000 000x  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 306 15.1 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 15-1: Bit Range DMTCON: DEADMAN TIMER CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 31:24 23:16 — R/W-y (1,2) 15:8 ON 7:0 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: y = Value set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Deadman Timer Module Enable bit(1) 1 = Deadman Timer module is enabled 0 = Deadman Timer module is disabled x = Bit is unknown The reset value of this bit is determined by the setting of the FDMTEN bit (DEVCFG1). bit 13-0 Note 1: 2: Unimplemented: Read as ‘0’ This bit only has control when FDMTEN (DEVCFG1) = 0. Once set, the DMTCON.ON bit cannot be disabled by software. REGISTER 15-2: Bit Range DMTPRECLR: DEADMAN TIMER PRECLEAR REGISTER Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 31:24 23:16 15:8 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — STEP1 7:0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-8 STEP1: Preclear Enable bits 01000000 = Enables the Deadman Timer Preclear (Step 1) All other write patterns = Set BAD1 flag. These bits are cleared when a DMT reset event occurs. STEP1 is also cleared if the STEP2 bits are loaded with the correct value in the correct sequence.  2015-2021 Microchip Technology Inc. DS60001320H-page 307 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 15-2: bit 7-0 DMTPRECLR: DEADMAN TIMER PRECLEAR REGISTER (CONTINUED) Unimplemented: Read as ‘0’ DS60001320H-page 308  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 15-3: Bit Range Bit 30/22/14/6 U-0 U-0 31:24 23:16 15:8 7:0 DMTCLR: DEADMAN TIMER CLEAR REGISTER Bit 31/23/15/7 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STEP2 Legend: R = Readable bit -n = Value at POR bit 31-8 bit 7-0 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ STEP2: Clear Timer bits 00001000 = Clears STEP1, STEP2 and the Deadman Timer if, and only if, preceded by correct loading of STEP1 bits in the correct sequence. The write to these bits may be verified by reading DMTCNT and observing the counter being reset. All other write patterns = Set BAD2 bit, the value of STEP1 will remain unchanged, and the new value being written STEP2 will be captured. These bits are also cleared when a DMT reset event occurs. If the STEP2 bits are written without preceding with a correct loading of STEP1 bits, the BAD1 bit is set.  2015-2021 Microchip Technology Inc. DS60001320H-page 309 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 15-4: Bit Range Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 31:24 23:16 15:8 7:0 DMTSTAT: DEADMAN TIMER STATUS REGISTER Bit 31/23/15/7 bit 6 bit 5 bit 4-1 bit 0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HC, HS R-0, HC, HS R-0, HC, HS U-0 U-0 U-0 U-0 R-0, HC, HS BAD1 BAD2 DMTEVENT — — — — WINOPN Legend: R = Readable bit -n = Value at POR bit 31-8 bit 7 Bit Bit Bit 28/20/12/4 27/19/11/3 26/18/10/2 HC = Hardware Cleared W = Writable bit ‘1’ = Bit is set HS = Hardware Set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ BAD1: Bad STEP1 Value Detect bit 1 = Incorrect STEP1 value or out of sequence write to STEP2 was detected 0 = Incorrect STEP1 value was not detected BAD2: Bad STEP2 Value Detect bit 1 = Incorrect STEP2 value was detected 0 = Incorrect STEP2 value was not detected DMTEVENT: Deadman Timer Event bit 1 = Deadman timer event was detected (counter expired or bad STEP1 or STEP2 value was entered prior to counter increment) 0 = Deadman timer even was not detected Unimplemented: Read as ‘0’ WINOPN: Deadman Timer Clear Window bit 1 = Deadman timer clear window is open 0 = Deadman timer clear window is not open DS60001320H-page 310  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 15-5: Bit Range DMTCNT: DEADMAN TIMER COUNT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 31:24 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 COUNTER 7:0 R-0 R-0 COUNTER Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown COUNTER: Read current contents of DMT counter REGISTER 15-6: DMTPSCNT: POST STATUS CONFIGURE DMT COUNT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 R-0 R-0 31:24 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 R-0 R-0 R-0 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-y R-y R-y PSCNT R-0 23:16 R-0 R-0 R-0 R-0 PSCNT R-0 15:8 R-0 R-0 R-0 R-0 PSCNT R-0 7:0 R-0 R-0 R-y R-y PSCNT Legend: R = Readable bit -n = Value at POR bit 31-8 R-0 Bit 24/16/8/0 COUNTER 15:8 Bit Range R-0 Bit 25/17/9/1 COUNTER 23:16 bit 31-8 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 W = Writable bit ‘1’ = Bit is set y = Value set from Configuration bits on POR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PSCNT: DMT Instruction Count Value Configuration Status bits This is always the value of the DMTCNT bits in the DEVCFG1 Configuration register.  2015-2021 Microchip Technology Inc. DS60001320H-page 311 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 15-7: Bit Range DMTPSINTV: POST STATUS CONFIGURE DMT INTERVAL STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 31:24 R-0 R-0 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-y R-y R-y PSINTV 23:16 R-0 R-0 PSINTV 15:8 R-0 R-0 PSINTV 7:0 R-0 R-0 PSINTV Legend: R = Readable bit -n = Value at POR bit 31-8 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 W = Writable bit ‘1’ = Bit is set y = Value set from Configuration bits on POR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PSINTV: DMT Window Interval Configuration Status bits This is always the value of the DMTINTV bits in the DEVCFG1 Configuration register. DS60001320H-page 312  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES:  2015-2021 Microchip Technology Inc. DS60001320H-page 313 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 314  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 16.0 Note: WATCHDOG TIMER (WDT) When enabled, the Watchdog Timer (WDT) operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog, Deadman, and Power-up Timers” (DS60001114) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). FIGURE 16-1: The following are key features of the WDT module: • Configuration or software controlled • User-configurable time-out period • Can wake the device from Sleep or Idle WATCHDOG TIMER BLOCK DIAGRAM LPRC ON Clock 32-bit Counter WDTCLRKEY = 0x5743 ON Wake ON Reset Event 32 0 1 WDT Counter Reset WDT Event to NMI(1) Power Save Decoder RUNDIV (WDTCON) Note 1: Refer to 6.0 “Resets” for more information.  2015-2021 Microchip Technology Inc. DS60001320H-page 315 Watchdog Timer Control Registers 0800 WDTCON(1) Legend: Note 1: WATCHDOG TIMER REGISTER MAP 31/15 30/14 29/13 ON — — 28/12 27/11 26/10 31:16 15:0 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 — — — — — WDTCLRKEY RUNDIV — — 16/0 All Resets Bit Range Bits Register Name Virtual Address (BF80_#) TABLE 16-1: 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See 12.0 “I/O Ports” for more information. WDTWINEN xx00  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 316 16.1 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 16-1: Bit Range 31:24 23:16 15:8 7:0 WDTCON: WATCHDOG TIMER CONTROL REGISTER Bit 31/23/15/7 W-0 Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 W-0 W-0 W-0 Bit Bit 27/19/11/3 26/18/10/2 W-0 Bit 25/17/9/1 Bit 24/16/8/0 W-0 W-0 W-0 W-0 W-0 W-0 R-y R-y R-y WDTCLRKEY W-0 W-0 W-0 W-0 W-0 R/W-y (1) U-0 U-0 — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — WDTWINEN WDTCLRKEY ON R-y R-y RUNDIV Legend: y = Values set from Configuration bits on POR R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 WDTCLRKEY: Watchdog Timer Clear Key bits To clear the Watchdog Timer to prevent a time-out, software must write the value 0x5743 to this location using a single 16-bit write. bit 15 ON: Watchdog Timer Enable bit(1) 1 = The WDT is enabled 0 = The WDT is disabled bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 RUNDIV: Watchdog Timer Postscaler Value bits On reset, these bits are set to the values of the WDTPS Configuration bits in DEVCFG1. bit 7-1 Unimplemented: Read as ‘0’ bit 0 WDTWINEN: Watchdog Timer Window Enable bit 1 = Enable windowed Watchdog Timer 0 = Disable windowed Watchdog Timer Note 1: This bit only has control when the FWDTEN bit (DEVCFG1) = 0.  2015-2021 Microchip Technology Inc. DS60001320H-page 317 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320H-page 318  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 17.0 INPUT CAPTURE Note: • Prescaler capture event modes: - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. “Input Capture” (DS60001122) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). Each input capture channel can select between one of six 16-bit timers for the time base, or two of six 16-bit timers together to form a 32-bit timer. The selected timer can use either an internal or external clock. Other operational features include: • Device wake-up from capture pin during Sleep and Idle modes • Interrupt on input capture event • 4-word FIFO buffer for capture values; Interrupt optionally generated after 1, 2, 3, or 4 buffer locations are filled • Input capture can also be used to provide additional sources of external interrupts The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The Input Capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. Capture events are caused by the following: • Capture timer value on every edge (rising and falling), specified edge first FIGURE 17-1: INPUT CAPTURE BLOCK DIAGRAM FEDGE Specified/Every Edge Mode ICM 110 PBCLK3 Prescaler Mode (16th Rising Edge) 101 Prescaler Mode (4th Rising Edge) 100 Timerx(2) Timery(2) C32/ICTMR CaptureEvent ICx(1) Rising Edge Mode 011 Falling Edge Mode 010 Edge Detection Mode 001 To CPU FIFO Control ICxBUF(1) FIFO ICI ICM Set Flag ICxIF(1) (In IFSx Register) /N Sleep/Idle Wake-up Mode 001 111 Note 1: An ‘x’ in a signal, register or bit name denotes the number of the capture channel. 2: See Table 17-1 for Timerx and Timery selections.  2015-2021 Microchip Technology Inc. DS60001320H-page 319 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family The timer source for each Input Capture module depends on the setting of the ICACLK bit in the CFGCON register. The available configurations are shown in Table 17-1. TABLE 17-1: TIMER SOURCE CONFIGURATIONS Input Capture Module Timerx Timery ICACLK (CFGCON) = 0 IC1 • • • IC9 Timer2 • • • Timer2 Timer3 • • • Timer3 ICACLK (CFGCON) = 1 IC1 Timer4 Timer5 IC2 Timer4 Timer5 IC3 Timer4 Timer5 IC4 Timer2 Timer3 IC5 Timer2 Timer3 IC6 Timer2 Timer3 IC7 Timer6 Timer7 IC8 Timer6 Timer7 IC9 Timer6 Timer7 DS60001320H-page 320  2015-2021 Microchip Technology Inc. Input Capture Control Registers INPUT CAPTURE 1 THROUGH INPUT CAPTURE 9 REGISTER MAP 2000 IC1CON(1) 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — DS60001320H-page 321 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI ICOV ICBNE ICM 31:16 2010 IC1BUF IC1BUF 15:0 31:16 — — — — — — — — — — — — — — — — 2200 IC2CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI ICOV ICBNE ICM 31:16 2210 IC2BUF IC2BUF 15:0 31:16 — — — — — — — — — — — — — — — — 2400 IC3CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI ICOV ICBNE ICM 31:16 2410 IC3BUF IC3BUF 15:0 31:16 — — — — — — — — — — — — — — — — 2600 IC4CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI ICOV ICBNE ICM 31:16 2610 IC4BUF IC4BUF 15:0 31:16 — — — — — — — — — — — — — — — — 2800 IC5CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI ICOV ICBNE ICM 31:16 2810 IC5BUF IC5BUF 15:0 31:16 — — — — — — — — — — — — — — — — 2A00 IC6CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI ICOV ICBNE ICM 31:16 2A10 IC6BUF IC6BUF 15:0 31:16 — — — — — — — — — — — — — — — — 2C00 IC7CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI ICOV ICBNE ICM 31:16 2C10 IC7BUF IC7BUF 15:0 31:16 — — — — — — — — — — — — — — — — 2E00 IC8CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI ICOV ICBNE ICM 31:16 2E10 IC8BUF IC8BUF 15:0 31:16 — — — — — — — — — — — — — — — — 3000 IC9CON(1) 15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI ICOV ICBNE ICM 31:16 3010 IC9BUF IC9BUF 15:0 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. All Resets Bit Range Bits Register Name Virtual Address (BF84_#) TABLE 17-2: 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx 0000 0000 xxxx xxxx PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. 17.1 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 17-1: Bit Range 31:24 23:16 15:8 7:0 ICXCON: INPUT CAPTURE X CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 bit 14 bit 13 bit 12-10 bit 9 bit 8 bit 7 bit 6-5 bit 4 bit 3 bit 2-0 Note 1: Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 — SIDL — — — FEDGE C32 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 ICOV ICBNE ON R/W-0 (1) ICTMR ICI Legend: R = Readable bit W = Writable bit -n = Bit Value at POR: (‘0’, ‘1’, x = unknown) bit 31-16 bit 15 Bit 25/17/9/1 ICM U = Unimplemented bit P = Programmable bit r = Reserved bit Unimplemented: Read as ‘0’ ON: Input Capture Module Enable bit 1 = Module is enabled 0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications Unimplemented: Read as ‘0’ SIDL: Stop in Idle Control bit 1 = Halt in CPU Idle mode 0 = Continue to operate in CPU Idle mode Unimplemented: Read as ‘0’ FEDGE: First Capture Edge Select bit (only used in mode 6, ICM = 110) 1 = Capture rising edge first 0 = Capture falling edge first C32: 32-bit Capture Select bit 1 = 32-bit timer resource capture 0 = 16-bit timer resource capture ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON) is ‘1’)(1) 0 = Timery is the counter source for capture 1 = Timerx is the counter source for capture ICI: Interrupt Control bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow is occurred 0 = No input capture overflow is occurred ICBNE: Input Capture Buffer Not Empty Status bit (read-only) 1 = Input capture buffer is not empty; at least one more capture value can be read 0 = Input capture buffer is empty ICM: Input Capture Mode Select bits 111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode) 110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter 101 = Prescaled Capture Event mode – every sixteenth rising edge 100 = Prescaled Capture Event mode – every fourth rising edge 011 = Simple Capture Event mode – every rising edge 010 = Simple Capture Event mode – every falling edge 001 = Edge Detect mode – every edge (rising and falling) 000 = Input Capture module is disabled Refer to Table 17-1 for Timerx and Timery selections. DS60001320H-page 322  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating 18.0 OUTPUT COMPARE Note: When a match occurs, the Output Compare module generates an event based on the selected mode of operation. This data sheet summarizes the features of the PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. “Output Compare” (DS60001111), which is available from the Documentation > Reference Manual section of the Microchip PIC32 web site (www.microchip.com/pic32). The following are some of the key features of the Output Compare module: • Multiple Output Compare modules in a device • Programmable interrupt generation on compare event • Single and Dual Compare modes • Single and continuous output pulse generation • Pulse-Width Modulation (PWM) mode • Hardware-based PWM Fault detection and automatic output disable • Programmable selection of 16-bit or 32-bit time bases • Can operate from either of two available 16-bit time bases or a single 32-bit time base • ADC event trigger The Output Compare module is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the Output Compare module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. FIGURE 18-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) Trigger to ADC(4) Output Logic OCxR(1) 3 OCM Mode Select Comparator 0 16 PBCLK3 Timerx(3) OCTSEL 1 0 S R Output Enable Q OCx(1) Output Enable Logic OCFA or OCFB(2) 1 16 Timery(3)  2015-2021 Microchip Technology Inc. Timerx(3) Rollover Timery(3) Rollover DS60001320H-page 323 PIC32MZ Embedded Connectivity with Floating The timer source for each Output Compare module depends on the setting of the OCACLK bit in the CFGCON register. The available configurations are shown in Table 18-1. TABLE 18-1: TIMER SOURCE CONFIGURATIONS Output Compare Module Timerx Timery OCACLK (CFGCON) = 0 OC1 • • • OC9 Timer2 • • • Timer 2 Timer3 • • • Timer 3 OCACLK (CFGCON) = 1 OC1 Timer4 Timer5 OC2 Timer4 Timer5 OC3 Timer4 Timer5 OC4 Timer2 Timer3 OC5 Timer2 Timer3 OC6 Timer2 Timer3 OC7 Timer6 Timer7 OC8 Timer6 Timer7 OC9 Timer6 Timer7 DS60001320H-page 324  2015-2021 Microchip Technology Inc. Output Compare Control Registers Virtual Address (BF84_#) TABLE 18-2: 4010 OC1R OC1RS 4200 OC2CON 4210 4220 OC2R OC2RS 4400 OC3CON 4410 4420 OC3R 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — 15:0 ON — — — — — — — — — — — SIDL — — — — — — — OC32 31:16 4610 OC4R 4620 OC4RS 4800 OC5CON 4810 OC5R DS60001320H-page 325 OC5RS 21/5 20/4 19/3 18/2 — — — OCFLT OCTSEL 31:16 0000 xxxx xxxx — — — — — — — — — — — — 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL 31:16 — — — OCM 31:16 xxxx xxxx xxxx OC2RS 15:0 xxxx 31:16 — — — — — — — — — — — — — 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL 31:16 — — — OCM xxxx xxxx xxxx OC3RS xxxx 31:16 — — — — — — — — — — — — — 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL 31:16 — — — OCM 31:16 15:0 xxxx xxxx xxxx OC4RS xxxx 31:16 — — — — — — — — — — — — — 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OC5R OC5RS 0000 0000 OC4R 15:0 0000 0000 OC3R 15:0 0000 0000 OC2R 15:0 0000 xxxx — 15:0 — xxxx 31:16 31:16 — OCM OC1RS 15:0 15:0 16/0 OC1R 15:0 31:16 17/1 All Resets 31/15 31:16 OC3RS 15:0 4600 OC4CON 4820 Bit Range Register Name(1) Bits 4000 OC1CON 4020 OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP — — OCM — 0000 0000 xxxx xxxx xxxx xxxx Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating  2015-2021 Microchip Technology Inc. 18.1 Virtual Address (BF84_#) 4A10 OC6R OC6RS 4C00 OC7CON 4C10 OC7R 4C20 OC7RS 4E00 OC8CON 4E10 OC8R 4E20 OC8RS 5000 OC9CON 5010 5020 OC9R 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 — 15:0 ON — — — — — — — — — — — SIDL — — — — — — — OC32 31:16 21/5 20/4 19/3 18/2 — — — OCFLT OCTSEL 31:16 — 0000 xxxx xxxx xxxx — — — — — — — — — — — — — 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL 31:16 — — — OCM 31:16 xxxx xxxx xxxx OC7RS 15:0 xxxx 31:16 — — — — — — — — — — — — — 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL 31:16 — — — OCM 31:16 15:0 xxxx xxxx xxxx OC8RS xxxx 31:16 — — — — — — — — — — — — — 15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OC9R OC9RS 0000 0000 OC8R 15:0 0000 0000 OC7R 15:0 0000 xxxx 31:16 31:16 OC9RS 15:0 — OCM OC6RS 15:0 15:0 16/0 OC6R 15:0 31:16 17/1 All Resets Bit Range Register Name(1) Bits 4A00 OC6CON 4A20 OUTPUT COMPARE 1 THROUGH OUTPUT COMPARE 9 REGISTER MAP (CONTINUED) — — OCM — 0000 0000 xxxx xxxx xxxx  2015-2021 Microchip Technology Inc. Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating DS60001320H-page 326 TABLE 18-2: PIC32MZ Embedded Connectivity with Floating REGISTER 18-1: Bit Range 31:24 23:16 15:8 7:0 OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON — SIDL — — — — — U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 — — OC32 OCFLT(1) OCTSEL(2) OCM Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Output Compare Peripheral On bit 1 = Output Compare peripheral is enabled 0 = Output Compare peripheral is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters Idle mode 0 = Continue operation in Idle mode bit 12-6 Unimplemented: Read as ‘0’ bit 5 OC32: 32-bit Compare Mode bit 1 = OCxR and/or OCxRS are used for comparisions to the 32-bit timer source 0 = OCxR and OCxRS are used for comparisons to the 16-bit timer source bit 4 OCFLT: PWM Fault Condition Status bit(1) 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred bit 3 OCTSEL: Output Compare Timer Select bit(2) 1 = Timery is the clock source for this Output Compare module 0 = Timerx is the clock source for this Output Compare module bit 2-0 OCM: Output Compare Mode Select bits 111 = PWM mode on OCx; Fault pin enabled 110 = PWM mode on OCx; Fault pin disabled 101 = Initialize OCx pin low; generate continuous output pulses on OCx pin 100 = Initialize OCx pin low; generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high; compare event forces OCx pin low 001 = Initialize OCx pin low; compare event forces OCx pin high 000 = Output compare peripheral is disabled but continues to draw current Note 1: 2: This bit is only used when OCM = ‘111’. It is read as ‘0’ in all other modes. Refer to Table 18-1 for Timerx and Timery selections.  2015-2021 Microchip Technology Inc. DS60001320H-page 327 PIC32MZ Embedded Connectivity with Floating NOTES: DS60001320H-page 328  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family The SPI/I2S module is compatible with Motorola® SPI and SIOP interfaces. 19.0 SERIAL PERIPHERAL INTERFACE (SPI) AND INTER-IC SOUND (I2S) Note: The following are key features of the SPI module: • • • • • Host and Client modes support Four different clock formats Enhanced Framed SPI protocol support User-configurable 8-bit, 16-bit and 32-bit data width Separate SPI FIFO buffers for receive and transmit - FIFO buffers act as 4/8/16-level deep FIFOs based on 32/16/8-bit data width • Programmable interrupt event on every 8-bit,  16-bit and 32-bit data transfer • Operation during Sleep and Idle modes • Audio Codec Support: - I2S protocol - Left-justified - Right-justified - PCM This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. “Serial Peripheral Interface (SPI)” (DS60001106) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/ PIC32). The SPI/I2S module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices, as well as digital audio devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters, and so on. SPI/I2S MODULE BLOCK DIAGRAM FIGURE 19-1: Internal Data Bus SPIxBUF Read Write SPIxRXB FIFO FIFOs Share Address SPIxBUF SPIxTXB FIFO Transmit Receive SPIxSR SDIx bit 0 SDOx SSx/FSYNC Client Select and Frame Sync Control Shift Control Clock Control MCLKSEL Edge Select SCKx Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.  2015-2021 Microchip Technology Inc. REFCLKO1 Baud Rate Generator PBCLK2 MSTEN DS60001320H-page 329 SPI Control Registers SPI1 THROUGH SPI6 REGISTER MAP 1000 SPI1CON 1010 SPI1STAT 1020 SPI1BUF 1030 SPI1BRG 1040 SPI1CON2 1200 SPI2CON 1210 SPI2STAT 1220 SPI2BUF 1230 SPI2BRG 1240 SPI2CON2  2015-2021 Microchip Technology Inc. 1400 SPI3CON 1410 SPI3STAT 1420 SPI3BUF 1430 SPI3BRG 1440 SPI3CON2 31/15 30/14 29/13 28/12 27/11 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW 15:0 ON — SIDL DISSDO MODE32 31:16 — — — 15:0 — — — 26/10 25/9 24/8 FRMCNT MODE16 SMP 23/7 SPIBUSY — — 20/4 — — — SSEN CKP MSTEN DISSDI — — — SRMT SPIROV SPIRBE SPITUR 31:16 21/5 MCLKSEL CKE RXBUFELM FRMERR 22/6 19/3 18/2 17/1 — — SPIFE STXISEL 16/0 ENHBUF 0000 SRXISEL TXBUFELM — SPITBE — 31:16 — — — 15:0 — — — 31:16 — — — — — — — FRM ERREN SPI ROVEN SPI TUREN 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW DISSDO MODE32 SPI 15:0 SGNEXT — 15:0 ON — SIDL 31:16 — — — 15:0 — — — — — — — — SPIRBF 0008 0000 0000 — — — — — — — — — — — — — — — — BRG — IGNROV — MODE16 — SMP AUDEN — — — — — — — SSEN CKP MSTEN DISSDI — — — SRMT SPIROV SPIRBE CKE SPIBUSY — — SPITUR 31:16 AUDMOD SPIFE STXISEL SRXISEL TXBUFELM — SPITBE — 31:16 — — — — — — — 15:0 — — — — — — — 31:16 — — — — — — — — FRM ERREN SPI ROVEN SPI TUREN 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW DISSDO MODE32 SPI 15:0 SGNEXT — 15:0 ON — SIDL 31:16 — — — 15:0 — — — IGNROV — — SMP — SPIRBF 0008 FRMERR SPIBUSY — — 31:16 0000 — — — — — — — — — — — — — — — — AUDEN — — — — — — — SSEN CKP MSTEN DISSDI — — — SRMT SPIROV SPIRBE CKE SPITUR AUDMOD SPIFE STXISEL SPITBE — SRXISEL 31:16 — — — — — — — 15:0 — — — — — — — 31:16 — — — — — — — — FRM ERREN SPI ROVEN SPI TUREN SPI 15:0 SGNEXT — IGNROV — — IGNTUR — AUDEN 0000 SPIRBF 0008 0000 0000 — — — — — — — — — — — — — AUD MONO — BRG — 0000 0000 SPITBF DATA 15:0 0000 ENHBUF 0000 TXBUFELM — 0000 0000 MCLKSEL RXBUFELM 0000 0000 AUD MONO IGNTUR 0000 0000 SPITBF BRG FRMCNT MODE16 — 0000 ENHBUF 0000 DATA 15:0 0000 0000 MCLKSEL RXBUFELM FRMERR — AUD MONO IGNTUR FRMCNT 0000 0000 SPITBF DATA 15:0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF82_#) TABLE 19-1: — — — — 0000 0000 AUDMOD 0000 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 330 19.1 1600 SPI4CON 1610 SPI4STAT 1620 SPI4BUF 1630 SPI4BRG 1640 SPI4CON2 1800 SPI5CON 1810 SPI5STAT 1820 SPI5BUF 1830 SPI5BRG 1840 SPI5CON2 1A00 SPI6CON 1A10 SPI6STAT 1A20 SPI6BUF 1A30 SPI6BRG DS60001320H-page 331 1A40 SPI6CON2 31/15 30/14 29/13 28/12 27/11 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW 15:0 ON — SIDL DISSDO MODE32 31:16 — — — 15:0 — — — 26/10 25/9 24/8 FRMCNT MODE16 SMP 23/7 SPIBUSY — — 20/4 — — — SSEN CKP MSTEN DISSDI — — — SRMT SPIROV SPIRBE SPITUR 31:16 21/5 MCLKSEL CKE RXBUFELM FRMERR 22/6 19/3 18/2 17/1 — — SPIFE STXISEL 16/0 ENHBUF 0000 SRXISEL TXBUFELM — SPITBE — 31:16 — — — — — — — 15:0 — — — — — — — 31:16 — — — — — — — — FRM ERREN SPI ROVEN SPI TUREN 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW 15:0 ON — SIDL DISSDO MODE32 31:16 — — — 15:0 — — — SPI 15:0 SGNEXT — IGNROV — SPIRBF 0008 0000 — — IGNTUR SMP AUDEN SPIBUSY — — — — — — — — — — — — — — — — AUD MONO — — — — — — — SSEN CKP MSTEN DISSDI — — — SRMT SPIROV SPIRBE SPITUR 31:16 — MCLKSEL CKE RXBUFELM FRMERR 0000 — BRG FRMCNT MODE16 — AUDMOD SPIFE STXISEL SPITBE — — — — — — — — 15:0 — — — — — — — 31:16 — — — — — — — — — — — 15:0 SPI SGNEXT — — FRM ERREN SPI ROVEN SPI TUREN IGNROV IGNTUR AUDEN — — 31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW 15:0 ON — SIDL DISSDO MODE32 31:16 — — — 15:0 — — — SMP 0000 SPITBF SPIRBF 0008 SPIBUSY — — 31:16 — — — — — — — — — — — — AUD MONO — — — MCLKSEL — — — SSEN CKP MSTEN DISSDI — — — SRMT SPIROV SPIRBE RXBUFELM FRMERR — BRG CKE SPITUR AUDMOD SPIFE STXISEL SPITBE — 31:16 — — — — — — — 15:0 — — — — — — — 31:16 — — — — — — — — FRM ERREN SPI ROVEN SPI TUREN SPI 15:0 SGNEXT — IGNROV — — IGNTUR — AUDEN 0000 0000 0000 SPITBF SPIRBF 0008 0000 0000 — — — — — — — — — — — — — AUD MONO — BRG — 0000 ENHBUF 0000 SRXISEL TXBUFELM — 0000 0000 DATA 15:0 0000 0000 — FRMCNT 0000 0000 31:16 MODE16 — 0000 ENHBUF 0000 SRXISEL TXBUFELM — 0000 0000 DATA 15:0 0000 0000 SPITBF DATA 15:0 All Resets Bit Range Bits Register Name(1) Virtual Address (BF82_#) SPI1 THROUGH SPI6 REGISTER MAP (CONTINUED) — — — — 0000 0000 AUDMOD 0000 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 19-1: PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 19-1: Bit Range 31:24 23:16 15:8 7:0 SPIxCON: SPI CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 FRMCNT R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 MCLKSEL(1) — — — — — SPIFE ENHBUF(1) R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ON — SIDL DISSDO(4) MODE32 MODE16 SMP CKE(2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSEN CKP(3) MSTEN DISSDI(4) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set STXISEL SRXISEL U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31 FRMEN: Framed SPI Support bit 1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output) 0 = Framed SPI support is disabled bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only) 1 = Frame sync pulse input (Client mode) 0 = Frame sync pulse output (Host mode) bit 29 FRMPOL: Frame Sync / Client Select Polarity bit (Framed SPI or Host Transmit modes only) 1 = Frame pulse or SSx pin is active-high 0 = Frame pulse or SSx is active-low bit 28 MSSEN: Host Mode Client Select Enable bit 1 = Client select SPI support is enabled. The SS pin is automatically driven during transmission in  Host mode. Polarity is determined by the FRMPOL bit. 0 = Client select SPI support is disabled. bit 27 FRMSYPW: Frame Sync Pulse Width bit 1 = Frame sync pulse is one character wide 0 = Frame sync pulse is one clock wide bit 26-24 FRMCNT: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in Framed mode. 111 = Reserved 110 = Reserved 101 = Generate a frame sync pulse on every 32 data characters 100 = Generate a frame sync pulse on every 16 data characters 011 = Generate a frame sync pulse on every 8 data characters 010 = Generate a frame sync pulse on every 4 data characters 001 = Generate a frame sync pulse on every 2 data characters 000 = Generate a frame sync pulse on every data character bit 23 MCLKSEL: Host Clock Enable bit(1) 1 = REFCLKO1 is used by the Baud Rate Generator 0 = PBCLK2 is used by the Baud Rate Generator bit 22-18 Unimplemented: Read as ‘0’ Note 1: 2: 3: 4: This bit can only be written when the ON bit = 0. Refer to Section 37.0 “Electrical Characteristics” for maximum clock frequency requirements. This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1). When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual value of the CKP bit. This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see Section 12.4 “Peripheral Pin Select (PPS)” for more information). DS60001320H-page 332  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 19-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED) bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only) 1 = Frame synchronization pulse coincides with the first bit clock 0 = Frame synchronization pulse precedes the first bit clock bit 16 ENHBUF: Enhanced Buffer Enable bit(1) 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled bit 15 ON: SPI/I2S Module On bit 1 = SPI/I2S module is enabled 0 = SPI/I2S module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters in Idle mode 0 = Continue operation in Idle mode bit 12 DISSDO: Disable SDOx pin bit(4) 1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register 0 = SDOx pin is controlled by the module bit 11-10 MODE: 32/16-Bit Communication Select bits When AUDEN = 1: MODE32 MODE16 Communication 1 1 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame 1 0 32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame 0 1 16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame 0 0 16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame When AUDEN = 0: MODE32 MODE16 Communication 1 x 32-bit 0 1 16-bit 0 0 8-bit SMP: SPI Data Input Sample Phase bit Host mode (MSTEN = 1): 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Client mode (MSTEN = 0): SMP value is ignored when SPI is used in Client mode. The module always uses SMP = 0. CKE: SPI Clock Edge Select bit(2) 1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit) 0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit) SSEN: Client Select Enable (Client mode) bit 1 = SSx pin is used for Client mode 0 = SSx pin is not used for Client mode, pin is controlled by the port function. CKP: Clock Polarity Select bit(3) 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 9 bit 8 bit 7 bit 6 Note 1: 2: 3: 4: This bit can only be written when the ON bit = 0. Refer to Section 37.0 “Electrical Characteristics” for maximum clock frequency requirements. This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1). When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual value of the CKP bit. This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see Section 12.4 “Peripheral Pin Select (PPS)” for more information).  2015-2021 Microchip Technology Inc. DS60001320H-page 333 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 19-1: bit 5 SPIxCON: SPI CONTROL REGISTER (CONTINUED) MSTEN: Host Mode Enable bit 1 = Host mode 0 = Client mode DISSDI: Disable SDI bit(4) 1 = SDI pin is not used by the SPI module (pin is controlled by PORT function) 0 = SDI pin is controlled by the SPI module STXISEL: SPI Transmit Buffer Empty Interrupt Mode bits 11 = Interrupt is generated when the buffer is not full (has one or more empty elements) 10 = Interrupt is generated when the buffer is empty by one-half or more 01 = Interrupt is generated when the buffer is completely empty 00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are  complete SRXISEL: SPI Receive Buffer Full Interrupt Mode bits 11 = Interrupt is generated when the buffer is full 10 = Interrupt is generated when the buffer is full by one-half or more 01 = Interrupt is generated when the buffer is not empty 00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty) bit 4 bit 3-2 bit 1-0 Note 1: 2: 3: 4: This bit can only be written when the ON bit = 0. Refer to Section 37.0 “Electrical Characteristics” for maximum clock frequency requirements. This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1). When AUDEN = 1, the SPI/I2S module functions as if the CKP bit is equal to ‘1’, regardless of the actual value of the CKP bit. This bit present for legacy compatibility and is superseded by PPS functionality on these devices (see Section 12.4 “Peripheral Pin Select (PPS)” for more information). DS60001320H-page 334  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 19-2: Bit Range 31:24 23:16 15:8 7:0 SPIxCON2: SPI CONTROL REGISTER 2 Bit 31/23/15/7 Bit Bit 30/22/14/6 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — U-0 — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SPISGNEXT — — FRMERREN SPIROVEN R/W-0 U-0 U-0 U-0 R/W-0 U-0 AUDEN(1) — — — AUDMONO(1,2) — Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set SPITUREN IGNROV R/W-0 IGNTUR R/W-0 AUDMOD(1,2) U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit 1 = Data from RX FIFO is sign extended 0 = Data from RX FIFO is not sign extended bit 14-13 Unimplemented: Read as ‘0’ bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit 1 = Frame Error overflow generates error events 0 = Frame Error does not generate error events bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit 1 = Receive overflow generates error events 0 = Receive overflow does not generate error events bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit 1 = Transmit Underrun Generates Error Events 0 = Transmit Underrun Does Not Generates Error Events bit 9 IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions) 1 = A ROV is not a critical error; during ROV data in the FIFO is not overwritten by receive data 0 = A ROV is a critical error which stop SPI operation bit 8 IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions) 1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty 0 = A TUR is a critical error which stop SPI operation bit 7 AUDEN: Enable Audio CODEC Support bit(1) 1 = Audio protocol is enabled 0 = Audio protocol is disabled bit 6-5 Unimplemented: Read as ‘0’ bit 3 AUDMONO: Transmit Audio Data Format bit(1,2) 1 = Audio data is mono (Each data word is transmitted on both left and right channels) 0 = Audio data is stereo bit 2 Unimplemented: Read as ‘0’ bit 1-0 AUDMOD: Audio Protocol Mode bit(1,2) 11 = PCM/DSP mode 10 = Right Justified mode 01 = Left Justified mode 00 = I2S mode Note 1: 2: This bit can only be written when the ON bit = 0. This bit is only valid for AUDEN = 1.  2015-2021 Microchip Technology Inc. DS60001320H-page 335 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 19-3: Bit Range 31:24 23:16 15:8 7:0 SPIxSTAT: SPI STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0 — — — U-0 U-0 U-0 R-0 R-0 — — — U-0 U-0 U-0 R/C-0, HS R-0 U-0 U-0 R-0 — — — FRMERR SPIBUSY — — SPITUR RXBUFELM R-0 R-0 R-0 TXBUFELM R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0 SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF Legend: C = Clearable bit HS = Set in hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-24 RXBUFELM: Receive Buffer Element Count bits (valid only when ENHBUF = 1) bit 23-21 Unimplemented: Read as ‘0’ bit 20-16 TXBUFELM: Transmit Buffer Element Count bits (valid only when ENHBUF = 1) bit 15-13 Unimplemented: Read as ‘0’ bit 12 FRMERR: SPI Frame Error status bit 1 = Frame error is detected 0 = No Frame error is detected This bit is only valid when FRMEN = 1. bit 11 SPIBUSY: SPI Activity Status bit 1 = SPI peripheral is currently busy with some transactions 0 = SPI peripheral is currently idle bit 10-9 Unimplemented: Read as ‘0’ bit 8 SPITUR: Transmit Under Run bit 1 = Transmit buffer has encountered an underrun condition 0 = Transmit buffer has no underrun condition This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling the module. bit 7 SRMT: Shift Register Empty bit (valid only when ENHBUF = 1) 1 = When SPI module shift register is empty 0 = When SPI module shift register is not empty bit 6 SPIROV: Receive Overflow Flag bit 1 = A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred This bit is set in hardware; can only be cleared (= 0) in software. bit 5 SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1) 1 = RX FIFO is empty (CRPTR = SWPTR) 0 = RX FIFO is not empty (CRPTR SWPTR) bit 4 Unimplemented: Read as ‘0’ DS60001320H-page 336  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 19-3: SPIxSTAT: SPI STATUS REGISTER bit 3 SPITBE: SPI Transmit Buffer Empty Status bit 1 = Transmit buffer, SPIxTXB is empty 0 = Transmit buffer, SPIxTXB is not empty Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR. Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB. bit 2 Unimplemented: Read as ‘0’ bit 1 SPITBF: SPI Transmit Buffer Full Status bit 1 = Transmit is not yet started, SPITXB is full 0 = Transmit buffer is not full Standard Buffer Mode: Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB. Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR. Enhanced Buffer Mode: Set when CWPTR + 1 = SRPTR; cleared otherwise bit 0 SPIRBF: SPI Receive Buffer Full Status bit 1 = Receive buffer, SPIxRXB is full 0 = Receive buffer, SPIxRXB is not full Standard Buffer Mode: Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB. Enhanced Buffer Mode: Set when SWPTR + 1 = CRPTR; cleared otherwise  2015-2021 Microchip Technology Inc. DS60001320H-page 337 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320H-page 338  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 20.0 Note: SERIAL QUAD INTERFACE (SQI) This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 46. “Serial Quad Interface (SQI)” (DS60001244) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The SQI module is a synchronous serial interface that provides access to serial Flash memories and other serial devices. The SQI module supports Single Lane (identical to SPI), Dual Lane, and Quad Lane modes. The following are key feature of the SQI module: • • • • Supports Single, Dual, and Quad Lane modes Supports Single Data Rate (SDR) mode Programmable command sequence eXecute-In-Place (XIP) FIGURE 20-1: • Data transfer: - Programmed I/O mode (PIO) - Buffer descriptor DMA • Supports SPI Mode 0 and Mode 3 • Programmable Clock Polarity (CPOL) and Clock Phase (CPHA) bits • Supports up to two Chip Selects • Supports up to four bytes of Flash address • Programmable interrupt thresholds • 32-byte transmit data buffer • 32-byte receive data buffer • 4-word controller buffer Note: Once the SQI module is configured, external devices are memory mapped into KSEG2 and KSEG3 (see Figure 4-1 through Figure 4-4 in Section 4.0 “Memory Organization” for more information). The MMU must be enabled and the TLB must be set up to access this memory (refer to Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192) of the “PIC32 Family Reference Manual” for more information). SQI MODULE BLOCK DIAGRAM PBCLK5(2) REFCLKO2(1) (TBC) SQID0 Control Buffer SQID1 System Bus Bus Client Bus Host Note Control and Status Registers (PIO) DMA SQID2 Transmit Buffer SQID3 SQI Host Interface SQICLK SQICS0 Receive Buffer SQICS1 1: When configuring the REFCLKO2 clock source, a value of ‘0’ for the ROTRIM bits must be selected. 2: This clock source is only used for SQI Special Function Register (SFR) access.  2015-2021 Microchip Technology Inc. DS60001320H-page 339 SQI Control Registers Register Name Bit Range SERIAL QUADRATURE INTERFACE (SQI) REGISTER MAP Virtual Address (BF8E_#) TABLE 20-1: 2000 SQI1 XCON1 31:16 2004 SQI1 XCON2 31:16 — — — — — 15:0 — — — — DEVSEL 31:16 — — — — — — 15:0 — — — BURSTEN — HOLD WP — — — 31:16 — — — — — — — SCHECK — DASSERT 2008 SQI1CFG 200C SQI1CON 31/15 30/14 — — 15:0 29/13 28/12 27/11 26/10 — — — — READOPCODE 25/9 24/8 — — TYPEDATA — — — 23/7 22/6 21/5 DUMMYBYTES TYPEDUMMY — — 15:0 19/3 18/2 ADDRBYTES TYPEMODE — MODEBYTES CSEN 20/4 — 17/1 READOPCODE 0000 TYPEADDR — TYPECMD — — — RXFIFO RST TXFIFO RST RESET MODECODE SQIEN — DATAEN LSBF CPOL DEVSEL CPHA MODE LANEMODE — — — — — 2010 2014 31:16 SQI1 CMDTHR 15:0 — — — — — — 31:16 — — — 15:0 — — — 31:16 — — — — — — — — 31:16 — — — — — — — — — — — — — — — 15:0 — — — — DMAEIF PKT COMPIF BD DONEIF CON THRIF CON EMPTYIF CON FULLIF RX THRIF RX FULLIF RX EMPTYIF TX THRIF TX FULLIF CLKDIV — — — — — TXCMDTHR — — — — — TXINTTHR 0000 0000 0000 — 2018 — 0000 0000 CMDINIT TXRXCOUNT — 0000 0000 CON FIFORST 31:16 SQI1 CLKCON 15:0 SQI1 INTTHR 16/0 All Resets Bits — — — — — CLKDIV — — — — — — STABLE EN 0000 — — — — — — — — 0000 — — — — — — — — — — — — 0000 RXCMDTHR — — — 0000 RXINTTHR 0000 0000 — — — — — — — — — — — DMAEIE PKT COMPIE BD DONEIE CON THRIE CON EMPTYIE CON FULLIE RX THRIE RX FULLIE RX EMPTYIE TX THRIE TX FULLIE 0000  2015-2021 Microchip Technology Inc. 201C SQI1 INTEN 2020 SQI1 INTSTAT 2024 SQI1 TXDATA 31:16 TXDATA 0000 15:0 TXDATA 0000 2028 SQI1 RXDATA 31:16 RXDATA 0000 15:0 RXDATA 202C SQI1 STAT1 31:16 — — — — — — — — — — TXFIFOFREE,5:0> 15:0 — — — — — — — — — — RXFIFOCNT 2030 SQI1 STAT2 31:16 — — — — — — — — — — — — — — 15:0 — — — — SDID3 SDID2 SDID1 SDID0 — RXUN TXOV 00x0 2034 SQI1 BDCON 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — — — — — — — — — START POLLEN DMAEN 0000 2038 15:0 SQI1BD 31:16 CURADD 15:0 SQI1BD 31:16 2040 BASEADD 15:0 CONAVAIL TX 0000 EMPTYIE — 0000 TX 0000 EMPTYIF 0000 0000 0000 CMDSTAT 0000 BDCURRADDR 0000 BDCURRADDR 0000 BDADDR 0000 BDADDR 0000 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 340 20.1 Virtual Address (BF8E_#) Register Name Bit Range SERIAL QUADRATURE INTERFACE (SQI) REGISTER MAP (CONTINUED) 2044 SQI1BD STAT 31:16 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 — — — — — — — — — — 15:0 21/5 — — — — — — SQI1BD 31:16 2050 RXDSTAT 15:0 — — — — — — — — — — — 31:16 — — — — — — — — — — — 15:0 — — — — — — — — — — — 31:16 — — — — — — — — — — — 15:0 — — — — DMAEISE 31:16 — — — — 15:0 — — 31:16 SQI1 2060 MEMSTAT 15:0 — — SQI1 XCON3 31:16 — — — INIT1 SCHECK SQI1 XCON4 31:16 — — — INIT2 SCHECK SQI1INT SIGEN 205C SQI1 TAPCON 2064 2068 — — DMA START 16/0 DMAACTV 0000 — — — — — — — — — — — — — — — POLLCON TXSTATE — — — — — RXSTATE — — — CON THRISE — — — — — TXBUFCNT — — — INIT1TYPE INIT1CMD2 INIT2COUNT INIT2CMD2 INIT2TYPE 0000 RXCURBUFLEN CON CON EMPTYISE FULLISE — — RX THRISE — — — — — 0000 — — — — — — THRES — — RX RX FULLISE EMPTYISE — — — TX THRISE — STATPOS TYPESTAT 0000 0000 0000 TX TX 0000 FULLISE EMPTYISE — — CLKOUTDLY STATDATA INIT1COUNT 0000 RXBUFCNT DATAOUTDLY — 0000 TXCURBUFLEN — 0000 0000 — — PKT BD DONEISE DONEISE — CLKINDLY 15:0 15:0 17/1 0000 SQI1BD 31:16 204C TXDSTAT 15:0 2058 18/2 BDCON — SQI1THR 19/3 BDSTATE SQI1BD 31:16 2048 POLLCON 15:0 2054 20/4 All Resets Bits STATBYTES 0000 0000 0000 0000 INIT1CMD3 0000 INIT1CMD1 0000 INIT2CMD3 0000 INIT2CMD1 0000 DS60001320H-page 341 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 20-1: PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-1: Bit Range SQI1XCON1: SQI XIP CONTROL REGISTER 1 Bit Bit 31/23/15/7 30/22/14/6 31:24 23:16 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DUMMYBYTES R/W-0 15:8 R/W-0 R/W-0 ADDRBYTES R/W-0 R/W-0 READOPCODE R/W-0 R/W-0 READOPCODE R/W-0 7:0 R/W-0 R/W-0 TYPEDUMMY R/W-0 TYPEMODE R/W-0 TYPEDATA R/W-0 R/W-0 R/W-0 TYPEADDR R/W-0 TYPECMD Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23-21 DUMMYBYTES: Transmit Dummy Bytes bits 111 = Transmit seven dummy bytes after the address bytes • • • 011 = Transmit three dummy bytes after the address bytes 010 = Transmit two dummy bytes after the address bytes 001 = Transmit one dummy bytes after the address bytes 000 = Transmit zero dummy bytes after the address bytes bit 20-18 ADDRBYTES: Address Cycle bits 111 = Reserved • • • 101 = Reserved 100 = Four address bytes 011 = Three address bytes 010 = Two address bytes 001 = One address bytes 000 = Zero address bytes bit 17-10 READOPCODE: Op code Value for Read Operation bits These bits contain the 8-bit op code value for read operation. bit 9-8 TYPEDATA: SQI Type Data Enable bits The boot controller will receive the data in Single Lane, Dual Lane, or Quad Lane. 11 = Reserved 10 = Quad Lane mode data is enabled 01 = Dual Lane mode data is enabled 00 = Single Lane mode data is enabled bit 7-6 TYPEDUMMY: SQI Type Dummy Enable bits The boot controller will send the dummy in Single Lane, Dual Lane, or Quad Lane. 11 = Reserved 10 = Quad Lane mode dummy is enabled 01 = Dual Lane mode dummy is enabled 00 = Single Lane mode dummy is enabled DS60001320H-page 342  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-1: SQI1XCON1: SQI XIP CONTROL REGISTER 1 (CONTINUED) bit 5-4 TYPEMODE: SQI Type Mode Enable bits The boot controller will send the mode in Single Lane, Dual Lane, or Quad Lane. 11 = Reserved 10 = Quad Lane mode is enabled 01 = Dual Lane mode is enabled 00 = Single Lane mode is enabled bit 3-2 TYPEADDR: SQI Type Address Enable bits The boot controller will send the address in Single Lane, Dual Lane, or Quad Lane. 11 = Reserved 10 = Quad Lane mode address is enabled 01 = Dual Lane mode address is enabled 00 = Single Lane mode address is enabled bit 1-0 TYPECMD: SQI Type Command Enable bits The boot controller will send the command in Single Lane, Dual Lane, or Quad Lane. 11 = Reserved 10 = Quad Lane mode command is enabled 01 = Dual Lane mode command is enabled 00 = Single Lane mode command is enabled  2015-2021 Microchip Technology Inc. DS60001320H-page 343 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-2: Bit Range 31:24 23:16 15:8 7:0 SQI1XCON2: SQI XIP CONTROL REGISTER 2 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — R/W-0 R/W-0 R/W-0 DEVSEL R/W-0 R/W-0 R/W-0 MODEBYTES R/W-0 R/W-0 MODECODE Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-12 Unimplemented: Read as ‘0’ bit 11-10 DEVSEL: Device Select bits 11 = Reserved 10 = Reserved 01 = Device 1 is selected 00 = Device 0 is selected bit 9-8 MODEBYTES: Mode Byte Cycle Enable bits 11 = Three cycles 10 = Two cycles 01 = One cycle 00 = Zero cycles bit 7-0 MODECODE: Mode Code Value bits These bits contain the 8-bit code value for the mode bits. DS60001320H-page 344  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-3: Bit Range 31:24 23:16 15:8 7:0 SQI1CFG: SQI CONFIGURATION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — R/W-0 U-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC CON FIFORST RX FIFORST TX FIFORST RESET U-0 SQIEN — DATAEN CSEN U-0 r-0 r-0 R/W-0 r-0 R/W-0 R/W-0 — — — BURSTEN(1) — HOLD WP — U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — LSBF CPOL CPHA MODE Legend: HC = Hardware Cleared r = Reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-26 Unimplemented: Read as ‘0’ bit 25-24 CSEN: Chip Select Output Enable bits 11 = Chip Select 0 and Chip Select 1 are used 10 = Chip Select 1 is used (Chip Select 0 is not used) 01 = Chip Select 0 is used (Chip Select 1 is not used) 00 = Chip Select 0 and Chip Select 1 are not used bit 23 SQIEN: SQI Enable bit 1 = SQI module is enabled 0 = SQI module is disabled bit 22 Unimplemented: Read as ‘0’ bit 21-20 DATAEN: Data Output Enable bits 11 = Reserved 10 = SQID3-SQID0 outputs are enabled 01 = SQID1 and SQID0 data outputs are enabled 00 = SQID0 data output is enabled bit 19 CONFIFORST: Control FIFO Reset bit 1 = A reset pulse is generated clearing the control FIFO 0 = A reset pulse is not generated bit 18 RXFIFORST: Receive FIFO Reset bit 1 = A reset pulse is generated clearing the receive FIFO 0 = A reset pulse is not generated bit 17 TXFIFORST: Transmit FIFO Reset bit 1 = A reset pulse is generated clearing the transmit FIFO 0 = A reset pulse is not generated bit 16 RESET: Software Reset Select bit This bit is automatically cleared by the SQI module. All of the internal state machines and FIFO pointers are reset by this reset pulse. 1 = A reset pulse is generated 0 = A reset pulse is not generated bit 15 Unimplemented: Read as ‘0’ bit 14-13 Reserved: Must be programmed as ‘0’ Note 1: This bit must be programmed as ‘1’.  2015-2021 Microchip Technology Inc. DS60001320H-page 345 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-3: SQI1CFG: SQI CONFIGURATION REGISTER (CONTINUED) bit 12 BURSTEN: Burst Configuration bit(1) 1 = Burst is enabled 0 = Burst is not enabled bit 11 Reserved: Must be programmed as ‘0’ bit 10 HOLD: Hold bit In Single Lane or Dual Lane mode, this bit is used to drive the SQID3 pin, which can be used for devices with a HOLD input pin. The meaning of the values for this bit will depend on the device to which SQID3 is connected. bit 9 WP: Write Protect bit In Single Lane or Dual Lane mode, this bit is used to drive the SQID2 pin, which can be used with devices with a write-protect pin. The meaning of the values for this bit will depend on the device to which SQID2 is connected. bit 8-6 Unimplemented: Read as ‘0’ bit 5 LSBF: Data Format Select bit 1 = LSB is sent or received first 0 = MSB is sent or received first bit 4 CPOL: Clock Polarity Select bit 1 = Active-low SQICLK (SQICLK high is the Idle state) 0 = Active-high SQICLK (SQICLK low is the Idle state) bit 3 CPHA: Clock Phase Select bit 1 = SQICLK starts toggling at the start of the first data bit 0 = SQICLK starts toggling at the middle of the first data bit bit 2-0 MODE: Mode Select bits 111 = Reserved • • • 100 = Reserved 011 = XIP mode is selected (when this mode is entered, the module behaves as if executing in place (XIP), but uses the register data to control timing) 010 = DMA mode is selected 001 = CPU mode is selected (the module is controlled by the CPU in PIO mode. This mode is entered when leaving Boot or XIP mode) 000 = Reserved Note 1: This bit must be programmed as ‘1’. DS60001320H-page 346  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-4: Bit Range 31:24 23:16 15:8 7:0 SQI1CON: SQI CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 U-0 U-0 U-0 U-0 U-0 U-0 r-0 R/W-0 — — — — — — — SCHECK U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — DASSERT R/W-0 R/W-0 DEVSEL R/W-0 R/W-0 LANEMODE R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 CMDINIT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXRXCOUNT R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXRXCOUNT Legend: r = Reserved R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-26 Unimplemented: Read as ‘0’ bit 25 Reserved: Must be programmed as ‘0’ bit 24 SCHECK: Flash Status Check bit 1 = Check the status of the Flash 0 = Do not check the status of the Flash bit 23 Unimplemented: Read as ‘0’ bit 22 DASSERT: Chip Select Assert bit 1 = Chip Select is deasserted after transmission or reception of the specified number of bytes 0 = Chip Select is not deasserted after transmission or reception of the specified number of bytes bit 21-20 DEVSEL: SQI Device Select bits 11 = Reserved 10 = Reserved 01 = Select Device 1 00 = Select Device 0 bit 19-18 LANEMODE: SQI Lane Mode Select bits 11 = Reserved 10 = Quad Lane mode 01 = Dual Lane mode 00 = Single Lane mode bit 17-16 CMDINIT: Command Initiation Mode Select bits If it is Transmit, commands are initiated based on a write to the transmit register or the contents of TX FIFO. If CMDINIT is Receive, commands are initiated based on reads to the read register or RX FIFO availability. 11 = Reserved 10 = Receive 01 = Transmit 00 = Idle bit 15-0 TXRXCOUNT: Transmit/Receive Count bits These bits specify the total number of bytes to transmit or receive (based on CMDINIT).  2015-2021 Microchip Technology Inc. DS60001320H-page 347 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-5: Bit Range 31:24 23:16 15:8 7:0 SQI1CLKCON: SQI CLOCK CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CLKDIV(1) R/W-0 R/W-0 R/W-0 CLKDIV(1) U-0 U-0 U-0 U-0 U-0 U-0 R-0 R/W-0 — — — — — — STABLE EN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-19 Unimplemented: Read as ‘0’ bit 18-8 CLKDIV: SQI Clock TSQI Frequency Select bit(1) 10000000000 = Base clock TBC is divided by 2048 01000000000 = Base clock TBC is divided by 1024 00100000000 = Base clock TBC is divided by 512 00010000000 = Base clock TBC is divided by 256 00001000000 = Base clock TBC is divided by 128 00000100000 = Base clock TBC is divided by 64 00000010000 = Base clock TBC is divided by 32 00000001000 = Base clock TBC is divided by 16 00000000100 = Base clock TBC is divided by 8 00000000010 = Base clock TBC is divided by 4 00000000001 = Base clock TBC is divided by 2 00000000000 = Base clock TBC bit 7-2 Unimplemented: Read as ‘0’ bit 1 STABLE: TSQI Clock Stable Select bit This bit is set to ‘1’ when the SQI clock, TSQI, is stable after writing a ‘1’ to the EN bit. 1 = TSQI clock is stable 0 = TSQI clock is not stable bit 0 EN: TSQI Clock Enable Select bit When clock oscillation is stable, the SQI module will set the STABLE bit to ‘1’. 1 = Enable the SQI clock (TSQI) (when clock oscillation is stable, the SQI module sets the STABLE bit to ‘1’) 0 = Disable the SQI clock (TSQI) (the SQI module should stop its clock to enter a low power state); SFRs can still be accessed, as they use PBCLK5 Note 1: Refer to Table 37-34 in 37.0 “Electrical Characteristics” for the maximum clock frequency specifications. Setting these bits to ‘00000000000’ specifies the highest frequency of the SQI clock. DS60001320H-page 348  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-6: Bit Range 31:24 23:16 15:8 7:0 SQI1CMDTHR: SQI COMMAND THRESHOLD REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — U-0 U-0 U-0 R/W-0 R/W-0 — — — TXCMDTHR R/W-0 R/W-0 R/W-0 RXCMDTHR(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-13 Unimplemented: Read as ‘0’ bit 12-8 TXCMDTHR: Transmit Command Threshold bits In transmit initiation mode, the SQI module performs a transmit operation when transmit command threshold bytes are present in the TX FIFO. These bits should usually be set to ‘1’ for normal Flash commands, and set to a higher value for page programming. For 16-bit mode, the value should be a multiple of 2. bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RXCMDTHR: Receive Command Threshold bits(1) In receive initiation mode, the SQI module attempts to perform receive operations to fetch the receive command threshold number of bytes in the receive buffer. If space for these bytes is not present in the FIFO, the SQI will not initiate a transfer. For 16-bit mode, the value should be a multiple of 2. If software performs any reads, thereby reducing the FIFO count, hardware would initiate a receive transfer to make the FIFO count equal to the value in these bits. If software would not like any more words latched into the FIFO, command initiation mode needs to be changed to Idle before any FIFO reads by software. In the case of Boot/XIP mode, the SQI module will use the System Bus burst size, instead of the receive command threshold value. Note 1: These bits should only be programmed when a receive is not active (i.e., during Idle mode or a transmit).  2015-2021 Microchip Technology Inc. DS60001320H-page 349 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-7: Bit Range 31:24 23:16 15:8 7:0 SQI1INTTHR: SQI INTERRUPT THRESHOLD REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — U-0 U-0 U-0 R/W-0 R/W-0 — — — TXINTTHR R/W-0 R/W-0 R/W-0 RXINTTHR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-13 Unimplemented: Read as ‘0’ bit 12-8 TXINTTHR: Transmit Interrupt Threshold bits A transmit interrupt is set when the transmit FIFO has more space than the set number of bytes. For 16-bit mode, the value should be a multiple of 2. bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 RXINTTHR: Receive Interrupt Threshold bits A receive interrupt is set when the receive FIFO count is larger than or equal to the set number of bytes. For 16-bit mode, the value should be multiple of 2. DS60001320H-page 350  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-8: Bit Range 31:24 23:16 15:8 7:0 SQI1INTEN: SQI INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — DMAEIE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CONEMPTYIE CONFULLIE RXTHRIE RXFULLIE RXEMPTYIE Legend: R = Readable bit -n = Value at POR HS = Hardware Set W = Writable bit ‘1’ = Bit is set PKTCOMPIE BDDONEIE CONTHRIE R/W-0 TXTHRIE R/W-0 R/W-0 TXFULLIE TXEMPTYIE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-12 Unimplemented: Read as ‘0’ bit 11 DMAEIE: DMA Bus Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 10 PKTCOMPIE: DMA Buffer Descriptor Packet Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 9 BDDONEIE: DMA Buffer Descriptor Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 8 CONTHRIE: Control Buffer Threshold Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 7 CONEMPTYIE: Control Buffer Empty Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 CONFULLIE: Control Buffer Full Interrupt Enable bit This bit enables an interrupt when the receive FIFO buffer is full. 1 = Interrupt is enabled 0 = Interrupt is disabled bit 5 RXTHRIE: Receive Buffer Threshold Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 4 RXFULLIE: Receive Buffer Full Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 3 RXEMPTYIE: Receive Buffer Empty Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 2 TXTHRIE: Transmit Threshold Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 1 TXFULLIE: Transmit Buffer Full Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 0 TXEMPTYIE: Transmit Buffer Empty Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled  2015-2021 Microchip Technology Inc. DS60001320H-page 351 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-9: Bit Range 31:24 23:16 15:8 7:0 SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS — — — — DMA EIF PKT COMPIF BD DONEIF CON THRIF R/W-1, HS R/W-0, HS R/W-1, HS R/W-0, HS R/W-1, HS R/W-1, HS R/W-0, HS R/W-1, HS CON EMPTYIF CON FULLIF RX EMPTYIF TXTHRIF TXFULLIF TX EMPTYIF RXTHRIF(1) RXFULLIF Legend: HS = Hardware Set R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-12 Unimplemented: Read as ‘0’ bit 11 DMAEIF: DMA Bus Error Interrupt Flag bit 1 = DMA bus error has occurred 0 = DMA bus error has not occurred bit 10 PKTCOMPIF: DMA Buffer Descriptor Processor Packet Completion Interrupt Flag bit 1 = DMA BD packet is complete 0 = DMA BD packet is in progress bit 9 BDDONEIF: DMA Buffer Descriptor Done Interrupt Flag bit 1 = DMA BD process is done 0 = DMA BD process is in progress bit 8 CONTHRIF: Control Buffer Threshold Interrupt Flag bit 1 = The control buffer has more than THRES words of space available 0 = The control buffer has less than THRES words of space available bit 7 CONEMPTYIF: Control Buffer Empty Interrupt Flag bit 1 = Control buffer is empty 0 = Control buffer is not empty bit 6 CONFULLIF: Control Buffer Full Interrupt Flag bit 1 = Control buffer is full 0 = Control buffer is not full bit 5 RXTHRIF: Receive Buffer Threshold Interrupt Flag bit(1) 1 = Receive buffer has more than RXINTTHR words of space available 0 = Receive buffer has less than RXINTTHR words of space available bit 4 RXFULLIF: Receive Buffer Full Interrupt Flag bit 1 = Receive buffer is full 0 = Receive buffer is not full bit 3 RXEMPTYIF: Receive Buffer Empty Interrupt Flag bit 1 = Receive buffer is empty 0 = Receive buffer is not empty Note 1: In Boot/XIP mode, the POR value of the receive buffer threshold is zero. Therefore, this bit will be set to a ‘1’, immediately after a POR until a read request on the System Bus is received. Note: The bits in the register are cleared by writing a '1' to the corresponding bit position. DS60001320H-page 352  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-9: SQI1INTSTAT: SQI INTERRUPT STATUS REGISTER (CONTINUED) bit 2 TXTHRIF: Transmit Buffer Threshold Interrupt Flag bit 1 = Transmit buffer has more than TXINTTHR words of space available 0 = Transmit buffer has less than TXINTTHR words of space available bit 1 TXFULLIF: Transmit Buffer Full Interrupt Flag bit 1 = The transmit buffer is full 0 = The transmit buffer is not full bit 0 TXEMPTYIF: Transmit Buffer Empty Interrupt Flag bit 1 = The transmit buffer is empty 0 = The transmit buffer has content Note 1: In Boot/XIP mode, the POR value of the receive buffer threshold is zero. Therefore, this bit will be set to a ‘1’, immediately after a POR until a read request on the System Bus is received. Note: The bits in the register are cleared by writing a '1' to the corresponding bit position.  2015-2021 Microchip Technology Inc. DS60001320H-page 353 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-10: SQI1TXDATA: SQI TRANSMIT DATA BUFFER REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXDATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXDATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXDATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXDATA Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 x = Bit is unknown TXDATA: Transmit Command Data bits Data is loaded into this register before being transmitted. Prior to the data transfer, the data in TXDATA is loaded into the shift register (SFDR). Multiple writes to TXDATA can occur while a transfer is in progress. There can be a maximum of eight commands that can be queued. REGISTER 20-11: SQI1RXDATA: SQI RECEIVE DATA BUFFER REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-0 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RXDATA R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 RXDATA R-0 R-0 RXDATA R-0 R-0 R-0 R-0 R-0 RXDATA Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 x = Bit is unknown RXDATA: Receive Data Buffer bits At the end of a data transfer, the data in the shift register is loaded into the RXDATA register. This register works like a FIFO. The depth of the receive buffer is eight words. DS60001320H-page 354  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-12: SQI1STAT1: SQI STATUS REGISTER 1 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 U-0 — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0 — — Legend: R = Readable bit -n = Value at POR bit 31-22 bit 21-16 bit 15-6 bit 5-0 TXFIFOFREE RXFIFOCNT W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ TXFIFOFREE: Transmit FIFO Available Word Space bits Unimplemented: Read as ‘0’ RXFIFOCNT: Number of words of read data in the FIFO  2015-2021 Microchip Technology Inc. DS60001320H-page 355 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-13: SQI1STAT2: SQI STATUS REGISTER 2 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 U-0 U-0 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0 — — — — — — CMDSTAT U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — R-0 R-0 R-0 R-0 R-0 U-0 R-0 R-0 CONAVAIL SQID3 SQID2 SQID1 SQID0 — RXUN TXOV Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set CONAVAIL U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-18 Unimplemented: Read as ‘0’ bit 17-16 CMDSTAT: Current Command Status bits These bits indicate the current command status. 11 = Reserved 10 = Receive 01 = Transmit 00 = Idle bit 15-12 Unimplemented: Read as ‘0’ bit 11-7 CONAVAIL: Control FIFO Space Available bits These bits indicate the available control Word space. 11111 = 32 bytes are available 11110 = 31 bytes are available • • • bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00001 = 1 byte is available 00000 = No bytes are available SQID3: SQID3 Status bit 1 = Data is present on SQID3 0 = Data is not present on SQID3 SQID2: SQID2 Status bit 1 = Data is present on SQID2 0 = Data is not present on SQID2 SQID1: SQID1 Status bit 1 = Data is present on SQID1 0 = Data is not present on SQID1 SQID0: SQID0 Status bit 1 = Data is present on SQID0 0 = Data is not present on SQID0 Unimplemented: Read as ‘0’ RXUN: Receive FIFO Underflow Status bit 1 = Receive FIFO Underflow has occurred 0 = Receive FIFO underflow has not occurred TXOV: Transmit FIFO Overflow Status bit 1 = Transmit FIFO overflow has occurred 0 = Transmit FIFO overflow has not occurred DS60001320H-page 356  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-14: SQI1BDCON: SQI BUFFER DESCRIPTOR CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — START POLLEN DMAEN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-3 Unimplemented: Read as ‘0’ bit 2 START: Buffer Descriptor Processor Start bit 1 = Start the buffer descriptor processor 0 = Disable the buffer descriptor processor bit 1 POLLEN: Buffer Descriptor Poll Enable bit 1 = BDP poll is enabled 0 = BDP poll is not enabled bit 0 DMAEN: DMA Enable bit 1 = DMA is enabled 0 = DMA is disabled x = Bit is unknown REGISTER 20-15: SQI1BDCURADD: SQI BUFFER DESCRIPTOR CURRENT ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BDCURRADDR R-0 R-0 BDCURRADDR R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BDCURRADDR R-0 R-0 BDCURRADDR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 x = Bit is unknown BDCURRADDR: Current Buffer Descriptor Address bits These bits contain the address of the current descriptor being processed by the Buffer Descriptor Processor.  2015-2021 Microchip Technology Inc. DS60001320H-page 357 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-16: SQI1BDBASEADD: SQI BUFFER DESCRIPTOR BASE ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDADDR R/W-0 BDADDR R/W-0 R/W-0 BDADDR R/W-0 R/W-0 BDADDR Legend: R = Readable bit -n = Value at POR bit 31-0 R/W-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown BDADDR: DMA Base Address bits These bits contain the physical address of the root buffer descriptor. This register should be updated only when the DMA is idle. REGISTER 20-17: SQI1BDSTAT: SQI BUFFER DESCRIPTOR STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R-x R-x R-x R-x R-x R-x — — R-x R-x BDSTATE R-x R-x R-x DMASTART DMAACTV R-x R-x R-x R-x R-x R-x BDCON R-x Legend: R = Readable bit -n = Value at POR R-x R-x R-x R-x BDCON W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-22 Unimplemented: Read as ‘0’ bit 21-18 BDSTATE: DMA Buffer Descriptor Processor State Status bits These bits return the current state of the buffer descriptor processor: 5 = Fetched buffer descriptor is disabled 4 = Descriptor is done 3 = Data phase 2 = Buffer descriptor is loading 1 = Descriptor fetch request is pending 0 = Idle bit 17 DMASTART: DMA Buffer Descriptor Processor Start Status bit 1 = DMA has started 0 = DMA has not started bit 16 DMAACTV: DMA Buffer Descriptor Processor Active Status bit 1 = Buffer Descriptor Processor is active 0 = Buffer Descriptor Processor is idle bit 15-0 BDCON: DMA Buffer Descriptor Control Word bits These bits contain the current buffer descriptor control word. DS60001320H-page 358  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-18: SQI1BDPOLLCON: SQI BUFFER DESCRIPTOR POLL CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POLLCON R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POLLCON Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 POLLCON: Buffer Descriptor Processor Poll Status bits These bits indicate the number of cycles the BDP would wait before refetching the descriptor control word if the previous descriptor fetched was disabled. REGISTER 20-19: SQI1BDTXDSTAT: SQI BUFFER DESCRIPTOR DMA TRANSMIT STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R-x R-x R-x R-x U-0 R-x R-x R-x R-x U-0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — U-0 U-0 U-0 TXSTATE — R-x TXBUFCNT U-0 — — — — — — — — R-x R-x R-x R-x R-x R-x R-x R-x TXCURBUFLEN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-25 TXSTATE: Current DMA Transmit State Status bits These bits provide information on the current DMA receive states. bit 24-21 Unimplemented: Read as ‘0’ bit 20-16 TXBUFCNT: DMA Buffer Byte Count Status bits These bits provide information on the internal FIFO space. bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 TXCURBUFLEN: Current DMA Transmit Buffer Length Status bits These bits provide the length of the current DMA transmit buffer.  2015-2021 Microchip Technology Inc. DS60001320H-page 359 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-20: SQI1BDRXDSTAT: SQI BUFFER DESCRIPTOR DMA RECEIVE STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 R-x R-x R-x R-x U-0 R-x R-x R-x R-x — — — U-0 U-0 U-0 RXSTATE — R-x — — — U-0 U-0 U-0 U-0 U-0 RXBUFCNT U-0 U-0 U-0 — — — — — — — — R-x R-x R-x R-x R-x R-x R-x R-x RXCURBUFLEN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-25 RXSTATE: Current DMA Receive State Status bits These bits provide information on the current DMA receive states. bit 24-21 Unimplemented: Read as ‘0’ bit 20-16 RXBUFCNT: DMA Buffer Byte Count Status bits These bits provide information on the internal FIFO space. bit 15-8 Unimplemented: Read as ‘0’ bit 7-0 RXCURBUFLEN: Current DMA Receive Buffer Length Status bits These bits provide the length of the current DMA receive buffer. REGISTER 20-21: SQI1THR: SQI THRESHOLD CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — THRES Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-5 Unimplemented: Read as ‘0’ bit 4-0 THRES: SQI Control Threshold Value bits The SQI control threshold interrupt is asserted when the amount of space indicated by THRES is available in the SQI control buffer. DS60001320H-page 360  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-22: SQI1INTSIGEN: SQI INTERRUPT SIGNAL ENABLE REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — DMAEISE PKT DONEISE BD DONEISE CON THRISE R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CON EMPTYISE CON FULLISE RX THRISE RX FULLISE RX EMPTYISE TX THRISE TX FULLISE TX EMPTYISE Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-12 Unimplemented: Read as ‘0’ bit 11 DMAEISE: DMA Bus Error Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled bit 10 PKTDONEISE: Receive Error Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled bit 9 BDDONEISE: Transmit Error Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled bit 8 CONTHRISE: Control Buffer Threshold Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled bit 7 CONEMPTYISE: Control Buffer Empty Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled bit 6 CONFULLISE: Control Buffer Full Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled bit 5 RXTHRISE: Receive Buffer Threshold Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled bit 4 RXFULLISE: Receive Buffer Full Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled bit 3 RXEMPTYISE: Receive Buffer Empty Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled bit 2 TXTHRISE: Transmit Buffer Threshold Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled bit 1 TXFULLISE: Transmit Buffer Full Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled bit 0 TXEMPTYISE: Transmit Buffer Empty Interrupt Signal Enable bit 1 = Interrupt signal is enabled 0 = Interrupt signal is disabled  2015-2021 Microchip Technology Inc. DS60001320H-page 361 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-23: SQI1TAPCON: SQI TAP CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — R/W-0 R/W-0 CLKINDLY DATAOUTDLY R/W-0 CLKOUTDLY Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as ‘0’ bit 13-8 CLKINDLY: SQI Clock Input Delay bits These bits are used to add fractional delays to SQI Clock Input while sampling the incoming data. 111111 = 64 taps added on clock input 111110 = 63 taps added on clock input • • • 000001 = 2 taps added on clock input 000000 = 1 tap added on clock input bit 7-4 DATAOUTDLY: SQI Data Output Delay bits These bits are used to add fractional delays to SQI Data Output while writing the data to the Flash. 1111 = 16 taps added on clock output 1110 = 15 taps added on clock output • • • 0001 = 2 taps added on clock output 0000 = 1 tap added on clock output bit 3-0 CLKOUTDLY: SQI Clock Output Delay bits These bits are used to add fractional delays to SQI Clock Output while writing the data to the Flash. 1111 = 16 taps added on clock output 1110 = 15 taps added on clock output • • • 0001 = 2 taps added on clock output 0000 = 1 tap added on clock output DS60001320H-page 362  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-24: SQI1MEMSTAT: SQI MEMORY STATUS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — STATPOS R/W-0 R/W-0 R/W-0 R/W-0 STATTYPE R/W-0 STATBYTES R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STATDATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STATCMD Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-21 Unimplemented: Read as ‘0’ bit 20 STATPOS: Status Bit Position in Flash bit Indicates the BUSY bit position in the Flash Status register. This bit is added to support all Flash types (with BUSY bit at 0 and at 7). 1 = BUSY bit position is bit 7 in status register 0 = BUSY bit position is bit 0 in status register bit 19-18 STATTYPE: Status Command/Read Lane Mode bits 11 = Reserved 10 = Status command and read are executed in Quad Lane mode 01 = Status command and read are executed in Dual Lane mode 00 = Status command and read are executed in Single Lane mode bit 17-16 STATBYTES: Number of Status Bytes bits 11 = Reserved 10 = Status command/read is 2 bytes long 01 = Status command/read is 1 byte long 00 = Reserved bit 15-8 STATDATA: Status Data bits These bits contain the status value of the Flash device bit 7-0 STATCMD: Status Command bits The status check command is written into these bits  2015-2021 Microchip Technology Inc. DS60001320H-page 363 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-25: SQI1XCON3: SQI XIP CONTROL REGISTER 3 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 U-0 R/W-0 — — — INIT1SCHECK R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit Bit 27/19/11/3 26/18/10/2 R/W-0 R/W-0 INIT1COUNT Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 INIT1TYPE R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INIT1CMD3 R/W-0 INIT1CMD2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) INIT1CMD1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28 INIT1SCHECK: Flash Initialization 1 Command Status Check bit 1 = Check the status after executing the INIT1 command 0 = Do not check the status bit 27-26 INIT1COUNT: Flash Initialization 1 Command Count bits 11 = INIT1CMD1, INIT1CMD2, and INIT1CMD3 are sent 10 = INIT1CMD1 and INIT1CMD2 are sent, but INIT1CMD3 is still pending 01 = INIT1CMD1 is sent, but INIT1CMD2 and INIT1CMD3 are still pending 00 = No commands are sent bit 25-24 INIT1TYPE: Flash Initialization 1 Command Type bits 11 = Reserved 10 = INIT1 commands are sent in Quad Lane mode 01 = INIT1 commands are sent in Dual Lane mode 00 = INIT1 commands are sent in Single Lane mode bit 24-16 INIT1CMD3: Flash Initialization Command 3 bits(1) Third command of the Flash initialization. bit 15-8 INIT1CMD2: Flash Initialization Command 2 bits(1) Second command of the Flash initialization. bit 7-0 INIT1CMD1: Flash Initialization Command 1 bits(1) First command of the Flash initialization. Note 1: INIT1CMD1 can be WEN and INIT1CMD2 can be SECTOR UNPROTECT. Note: Some Flash devices require Write Enable and Sector Unprotect commands before read/write operations and this register is useful in working with those Flash types (XIP mode only) DS60001320H-page 364  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 20-26: SQI1XCON4: SQI XIP CONTROL REGISTER 4 Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 U-0 U-0 U-0 R/W-0 — — — INIT2SCHECK R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit Bit 27/19/11/3 26/18/10/2 R/W-0 R/W-0 INIT2COUNT Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 INIT2TYPE R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INIT2CMD3 R/W-0 INIT2CMD2(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 (1) INIT2CMD1 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28 INIT2SCHECK: Flash Initialization 2 Command Status Check bit 1 = Check the status after executing the INIT2 command 0 = Do not check the status bit 27-26 INIT2COUNT: Flash Initialization 2 Command Count bits 11 = INIT2CMD1, INIT2CMD2, and INIT2CMD3 are sent 10 = INIT2CMD1 and INIT2CMD2 are sent, but INIT2CMD3 is still pending 01 = INIT2CMD1 is sent, but INIT2CMD2 and INIT2CMD3 are still pending 00 = No commands are sent bit 25-24 INIT2TYPE: Flash Initialization 2 Command Type bits 11 = Reserved 10 = INIT2 commands are sent in Quad Lane mode 01 = INIT2 commands are sent in Dual Lane mode 00 = INIT2 commands are sent in Single Lane mode bit 24-16 INIT2CMD3: Flash Initialization Command 3 bits(1) Third command of the Flash initialization. bit 15-8 INIT2CMD2: Flash Initialization Command 2 bits(1) Second command of the Flash initialization. bit 7-0 INIT2CMD1: Flash Initialization Command 1 bits(1) First command of the Flash initialization. Note 1: INIT2CMD1 can be WEN and INIT2CMD2 can be SECTOR UNPROTECT. Note: Some Flash devices require Write Enable and Sector Unprotect commands before read/write operations and this register is useful in working with those Flash types (XIP mode only)  2015-2021 Microchip Technology Inc. DS60001320H-page 365 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320H-page 366  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 21.0 Note: INTER-INTEGRATED CIRCUIT (I2C) This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “InterIntegrated Circuit (I2C)” (DS60001116) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/ PIC32). The I2C module provides complete hardware support for both Client and Multi-Host modes of the I2C serial communication standard. Each I2C module offers the following key features: • I2C interface supporting both host and client operation • I2C Client mode supports 7-bit and 10-bit addressing • I2C Host mode supports 7-bit and 10-bit addressing • I2C port allows bidirectional transfers between host and clients • Serial clock synchronization for the I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control) • I2C supports multi-host operation; detects bus collision and arbitrates accordingly • Provides support for address bit masking • SMBus support Figure 21-1 illustrates the I2C module block diagram. Each I2C module has a 2-pin interface: • SCLx pin is clock • SDAx pin is data  2015-2021 Microchip Technology Inc. DS60001320H-page 367 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 21-1: I2C BLOCK DIAGRAM Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2CxBRG Read PBCLK2 DS60001320H-page 368  2015-2021 Microchip Technology Inc. I2C Control Registers Virtual Address (BF82_#) Register Name(1) TABLE 21-1: 0000 I2C1CON 0010 I2C1STAT 0020 I2C1ADD 0030 I2C1MSK 0040 I2C1BRG 0050 I2C1TRN 0060 I2C1RCV I2C2STAT(2) 0220 I2C2ADD(2) 0230 I2C2MSK(2) 0240 I2C2BRG(2) 0250 I2C2TRN(2) 0260 I2C2RCV(2) 31/15 30/14 31:16 — — 15:0 ON — 31:16 — — 15:0 ACKSTAT TRSTAT 31:16 — — 15:0 — — 31:16 — — 15:0 — — 31:16 — — 15:0 31:16 — — 15:0 — — 31:16 — — 15:0 — — 31:16 — — 15:0 ON — 31:16 — — 15:0 ACKSTAT TRSTAT 31:16 — — 15:0 — — 31:16 — — 15:0 — — 31:16 — — 15:0 31:16 — — 15:0 — — 31:16 — — 15:0 — — 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 — SIDL — ACKTIM — — — — — — SCLREL — — — — — — — — STRICT — — — — — — — — A10M — BCL — — — — — — DISSLW — GCSTAT — — SMEN — ADD10 — — GCEN — IWCOL — PCIE STREN — I2COV — — — — — — — — — — — — — — — — — — — — — — — — — Baud Rate Generator Register — — — — — — — — — — — — — — — — — — — SIDL — ACKTIM — — — — — SCLREL — — — — — — — STRICT — — — — — — — A10M — BCL — — — — — DISSLW — GCSTAT — SMEN — ADD10 — GCEN — IWCOL — PCIE STREN — I2COV — — — — — — — — — — — — — — — — — — — — — — — — — Baud Rate Generator Register — — — — — — — — — — — — 21/5 20/4 19/3 SCIE BOEN SDAHT ACKDT ACKEN RCEN — — — D/A P S — — — Address Register — — — Address Mask Register — — — — — — — Transmit Register — — Receive Register SCIE BOEN SDAHT ACKDT ACKEN RCEN — — — D/A P S — — — Address Register — — — Address Mask Register — — — — — — — Transmit Register — — Receive Register 18/2 17/1 16/0 SBCDE PEN — R/W — AHEN RSEN — RBF — DHEN SEN — TBF — — — — — — — — — — — — — SBCDE PEN — R/W — AHEN RSEN — RBF — DHEN SEN — TBF — — — — — — — — — — — — — All Resets Bit Range Bits 0200 I2C2CON(2) 0210 I2C1 THROUGH I2C5 REGISTER MAP 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DS60001320H-page 369 31:16 — — — — — — — — — PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0000 31:16 — — — — — — — — — — — — — — — — 0000 0410 I2C3STAT 15:0 ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 31:16 — — — — — — — — — — — — — — — — 0000 0420 I2C3ADD 15:0 — — — — — — Address Register 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. 2: This register is not available on 64-pin devices. 0400 I2C3CON PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. 21.1 Virtual Address (BF82_#) Register Name(1) 0430 I2C3MSK 0440 0450 0460 I2C1 THROUGH I2C5 REGISTER MAP (CONTINUED) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 31:16 15:0 31:16 I2C3BRG 15:0 31:16 I2C3TRN 15:0 31:16 I2C3RCV 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 31:16 — — 0600 I2C4CON 0610 I2C4STAT 0620 I2C4ADD 0630 I2C4MSK 0640 I2C4BRG 0650 I2C4TRN 0660 I2C4RCV 15:0 ON — 31:16 — — 15:0 ACKSTAT TRSTAT 31:16 — — 15:0 — — 31:16 — — 15:0 — — 31:16 — — 15:0 31:16 — — 15:0 — — 31:16 — — 15:0 — — — — — Baud Rate Generator Register — — — — — — — — — — — — — — — — — — — SIDL — ACKTIM — — — — — SCLREL — — — — — — — STRICT — — — — — — — A10M — BCL — — — — — DISSLW — GCSTAT — SMEN — ADD10 — GCEN — IWCOL — PCIE STREN — I2COV — — — — — — — — — — — — — — — — — — — — — — — — — Baud Rate Generator Register — — — — — — — — — — — — 20/4 — — Address Mask Register — — — — 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — SBCDE PEN — R/W — AHEN RSEN — RBF — DHEN SEN — TBF — — — — — — — — — — — — — — — Transmit Register — — Receive Register SCIE BOEN SDAHT ACKDT ACKEN RCEN — — — D/A P S — — — Address Register — — — Address Mask Register — — — — — — — Transmit Register — — Receive Register 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 — — — — — — — — — PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 0000 15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 0000 31:16 — — — — — — — — — — — — — — — — 0000 0810 I2C5STAT 15:0 ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000 31:16 — — — — — — — — — — — — — — — — 0000 0820 I2C5ADD 15:0 — — — — — — Address Register 0000 31:16 — — — — — — — — — — — — — — — — 0000 0830 I2C5MSK 15:0 — — — — — — Address Mask Register 0000 31:16 — — — — — — — — — — — — — — — — 0000 0840 I2C5BRG 15:0 Baud Rate Generator Register 0000 31:16 — — — — — — — — — — — — — — — — 0000 0850 I2C5TRN 15:0 — — — — — — — — Transmit Register 0000 31:16 — — — — — — — — — — — — — — — — 0000 0860 I2C5RCV 15:0 — — — — — — — — Receive Register 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. 2: This register is not available on 64-pin devices. 0800 I2C5CON 31:16 — 21/5 All Resets Bit Range Bits  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 370 TABLE 21-1: PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 21-1: Bit Range 31:24 23:16 15:8 7:0 I2CXCON: I2C CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN Legend: R = Readable bit -n = Value at POR HC = Cleared in Hardware W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-23 Unimplemented: Read as ‘0’ bit 22 PCIE: Stop Condition Interrupt Enable bit (I2C Client mode only) 1 = Enable interrupt on detection of Stop condition 0 = Stop detection interrupts are disabled bit 21 SCIE: Start Condition Interrupt Enable bit (I2C Client mode only) 1 = Enable interrupt on detection of Start or Restart conditions 0 = Start detection interrupts are disabled bit 20 BOEN: Buffer Overwrite Enable bit (I2C Client mode only) 1 = I2CxRCV is updated and ACK is generated for a received address/data byte, ignoring the state of the I2COV bit (I2CxSTAT)only if the RBF bit (I2CxSTAT) = 0 0 = I2CxRCV is only updated when the I2COV bit (I2CxSTAT) is clear bit 19 SDAHT: SDA Hold Time Selection bit 1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL 0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL bit 18 SBCDE: Client Mode Bus Collision Detect Enable bit (I2C Client mode only) 1 = Enable client bus collision interrupts 0 = Client bus collision interrupts are disabled bit 18 AHEN: Address Hold Enable bit (Client mode only) 1 = Following the 8th falling edge of SCL for a matching received address byte; SCLREL bit will be cleared and the SCL will be held low. 0 = Address holding is disabled bit 16 DHEN: Data Hold Enable bit (I2C Client mode only) 1 = Following the 8th falling edge of SCL for a received data byte; client hardware clears the SCLREL bit and SCL is held low 0 = Data holding is disabled bit 15 ON: I2C Enable bit 1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins 0 = Disables the I2C module; all I2C pins are controlled by PORT functions bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode  2015-2021 Microchip Technology Inc. DS60001320H-page 371 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 21-1: bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 I2CXCON: I2C CONTROL REGISTER (CONTINUED) SCLREL: SCLx Release Control bit (when operating as I2C client) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at beginning of client transmission. Hardware clear at end of client reception. If STREN = 0: Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of client transmission. STRICT: Strict I2C Reserved Address Rule Enable bit 1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate addresses in reserved address space. 0 = Strict I2C Reserved Address Rule is not enabled A10M: 10-bit Client Address bit 1 = I2CxADD is a 10-bit client address 0 = I2CxADD is a 7-bit client address DISSLW: Disable Slew Rate Control bit 1 = Slew rate control is disabled 0 = Slew rate control is enabled SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds GCEN: General Call Enable bit (when operating as I2C client) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address is disabled STREN: SCLx Clock Stretch Enable bit (when operating as I2C client) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching ACKDT: Acknowledge Data bit (when operating as I2C host, applicable during host receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge ACKEN: Acknowledge Sequence Enable bit  (when operating as I2C host, applicable during host receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.  Hardware clear at end of host Acknowledge sequence. 0 = Acknowledge sequence not in progress RCEN: Receive Enable bit (when operating as I2C host) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of host receive data byte. 0 = Receive sequence not in progress PEN: Stop Condition Enable bit (when operating as I2C host) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of host Stop sequence. 0 = Stop condition not in progress RSEN: Repeated Start Condition Enable bit (when operating as I2C host) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of  host Repeated Start sequence. 0 = Repeated Start condition not in progress SEN: Start Condition Enable bit (when operating as I2C host) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of host Start sequence. 0 = Start condition not in progress DS60001320H-page 372  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 21-2: Bit Range 31:24 23:16 15:8 7:0 I2CXSTAT: I2C STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0, HS, HC R-0, HS, HC R/C-0, HS, HC U-0 U-0 R/C-0, HS R-0, HS, HC R-0, HS, HC ACKSTAT TRSTAT ACKTIM — — BCL GCSTAT ADD10 R/C-0, HS, SC R/C-0, HS, SC R-0, HS, HC R/C-0, HS, HC R/C-0, HS, HC R-0, HS, HC R-0, HS, HC R-0, HS, HC IWCOL I2COV D_A P S R_W RBF TBF Legend: HS = Hardware Set HC = Hardware Cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ SC = Software Cleared -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared C = Clearable bit bit 31-16 Unimplemented: Read as ‘0’ bit 15 ACKSTAT: Acknowledge Status bit  (when operating as I2C host, applicable to host transmit operation) 1 = NACK received from client 0 = ACK received from client Hardware set or clear at end of client Acknowledge. bit 14 TRSTAT: Transmit Status bit (when operating as I2C host, applicable to host transmit operation) 1 = Host transmit is in progress (8 bits + ACK) 0 = Host transmit is not in progress Hardware set at beginning of host transmission. Hardware clear at end of client Acknowledge. bit 13 ACKTIM: Acknowledge Time Status bit (Valid in I2C Client mode only) 1 = I2C bus is in an Acknowledge sequence, set on the eight falling edge of SCL clock 0 = Not an Acknowledge sequence, cleared on 9th rising edge of SCL clock bit 12-11 Unimplemented: Read as ‘0’ bit 10 BCL: Host Bus Collision Detect bit 1 = A bus collision has been detected during a host operation 0 = No collision Hardware set at detection of bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. bit 8 ADD10: 10-bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).  2015-2021 Microchip Technology Inc. DS60001320H-page 373 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 21-2: I2CXSTAT: I2C STATUS REGISTER (CONTINUED) bit 5 D_A: Data/Address bit (when operating as I2C client) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of client byte. bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R_W: Read/Write Information bit (when operating as I2C client) 1 = Read – indicates data transfer is output from client 0 = Write – indicates data transfer is input to client Hardware set or clear after reception of I 2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software  reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. DS60001320H-page 374  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 22.0 Note: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The UART module is one of the serial I/O modules available in the PIC32MZ EF family of devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols, such as RS-232, RS-485, LIN, and IrDA®. The module also supports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder. The primary features of the UART module are: • Full-duplex, 8-bit or 9-bit data transmission • Even, Odd or No Parity options (for 8-bit data) • One or two Stop bits • Hardware auto-baud feature • Hardware flow control option • Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler • Baud rates ranging from 76 bps to 25 Mbps at 100 MHz (PBCLK2) • 8-level deep First-In-First-Out (FIFO) transmit data buffer • 8-level deep FIFO receive data buffer • Parity, framing and buffer overrun error detection • Support for interrupt-only on address detect  (9th bit = 1) • Separate transmit and receive interrupts • Loopback mode for diagnostic support • LIN Protocol support • IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support Figure 22-1 illustrates a simplified block diagram of the UART module. FIGURE 22-1: UART SIMPLIFIED BLOCK DIAGRAM PBCLK2 Baud Rate Generator IrDA® Hardware Flow Control UxRTS/BCLKx UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX  2015-2021 Microchip Technology Inc. DS60001320H-page 375 UART Control Registers Virtual Address (BF82_#) TABLE 22-1: U1STA (1) — — — 15:0 ON — SIDL 31:16 — — — 28/12 27/11 26/10 25/9 24/8 — — — — — IREN RTSMD — — — — — ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT UEN — — — — — — — — 15:0 — — — — — — — TX8 31:16 — — — — — — — — 15:0 — — — — — — — RX8 31:16 U1BRG(1) 15:0 — — — — — — — — 31:16 15:0 — — — — — — ON — SIDL IREN RTSMD — 31:16 — — — — — — — ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT 2200 U2MODE (1) U2STA(1) 2220 U2TXREG 2230 U2RXREG 2240 31:16 UTXISEL 29/13 31:16 2030 U1RXREG 2210 30/14 15:0 2020 U1TXREG 2040 31/15 U2BRG(1) 15:0 UTXISEL — — UEN 31:16 — — — — — — — — 15:0 — — — — — — — TX8 31:16 — — — — — — — — 15:0 — — — — — — — RX8 31:16 — — — — — — — — 15:0  2015-2021 Microchip Technology Inc. — — — — — ON — SIDL IREN RTSMD — 31:16 — — — — — — — ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT U3STA UTXISEL — — UEN 31:16 — — — — — — — — 15:0 — — — — — — — TX8 31:16 — — — — — — — — 15:0 — — — — — — — RX8 31:16 U3BRG(1) 15:0 — — — — — — — — 2420 U3TXREG 2430 U3RXREG 2440 15:0 21/5 20/4 19/3 18/2 17/1 — — — — — — — WAKE LPBACK ABAUD RXINV BRGH PDSEL 16/0 — 0000 STSEL 0000 ADDR URXISEL — — ADDEN — 0000 RIDLE PERR FERR OERR URXDA 0110 — — — — — — — — Transmit Register — — — — — Receive Register — — 0000 — — — — — — — — 0000 STSEL 0000 — — — WAKE LPBACK ABAUD RXINV BRGH PDSEL ADDR — ADDEN — 0000 RIDLE PERR FERR OERR URXDA 0110 — — — — — — — — Transmit Register — — — — — — 0000 — — — — — — — — 0000 STSEL 0000 — — — WAKE LPBACK ABAUD RXINV BRGH PDSEL ADDR — ADDEN — 0000 RIDLE PERR FERR OERR URXDA 0110 — — — — — — — — — — — Transmit Register — — — — — — Baud Rate Generator Prescaler — — — 0000 0000 Receive Register — 0000 0000 — — 0000 — — URXISEL 0000 0000 Receive Register — 0000 0000 — — 0000 — — URXISEL 0000 0000 Baud Rate Generator Prescaler — 2410 22/6 Baud Rate Generator Prescaler 31:16 2400 U3MODE(1) 15:0 (1) 23/7 All Resets Register Name Bit Range Bits 2000 U1MODE(1) 2010 UART1 THROUGH UART6 REGISTER MAP 0000 0000 0000 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 376 22.1 Virtual Address (BF82_#) U4STA(1) 2620 U4TXREG 2630 U4RXREG 2640 (1) U4BRG 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 — — 31:16 15:0 — — — — — — ON — SIDL IREN RTSMD — 31:16 — — — — — — — ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT 15:0 UTXISEL UEN 31:16 — — — — — — — — 15:0 — — — — — — — TX8 31:16 — — — — — — — — 15:0 — — — — — — — RX8 31:16 — — — — — — — — 15:0 — — — — — — ON — SIDL IREN RTSMD — 31:16 — — — — — — — ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT 2810 U5STA 15:0 UEN — — — — — — — — — — — — — — — TX8 31:16 — — — — — — — — 15:0 — — — — — — — RX8 31:16 U5BRG(1) 15:0 — — — — — — — — 31:16 15:0 — — — — — — ON — SIDL IREN RTSMD — 31:16 — — — — — — — ADM_EN UTXINV URXEN UTXBRK UTXEN UTXBF TRMT 2A00 U6MODE 2A10 — 15:0 2830 U5RXREG 2840 UTXISEL — 31:16 2820 U5TXREG (1) U6STA(1) 2A20 U6TXREG 2A30 U6RXREG DS60001320H-page 377 (1) 2A40 U6BRG 15:0 21/5 20/4 19/3 18/2 17/1 — — — — — — — WAKE LPBACK ABAUD RXINV BRGH PDSEL 16/0 — 0000 STSEL 0000 ADDR URXISEL — — ADDEN — 0000 RIDLE PERR FERR OERR URXDA 0110 — — — — — — — — Transmit Register — — — — — Receive Register — — 0000 — — — — — — — — 0000 STSEL 0000 — — — WAKE LPBACK ABAUD RXINV BRGH PDSEL ADDR — ADDEN — 0000 RIDLE PERR FERR OERR URXDA 0110 — — — — — — — — Transmit Register — — — — — — UTXISEL — — UEN — — — — — — — — 15:0 — — — — — — — TX8 0000 — — — — — — — — 0000 STSEL 0000 31:16 — — — — — — — — 15:0 — — — — — — — RX8 31:16 — — — — — — — — — — — WAKE LPBACK ABAUD RXINV BRGH PDSEL ADDR — ADDEN — 0000 RIDLE PERR FERR OERR URXDA 0110 — — — — — — — — — — — Transmit Register — — — — — — Baud Rate Generator Prescaler — — — 0000 0000 Receive Register — 0000 0000 — — 0000 — — URXISEL 0000 0000 Receive Register — 0000 0000 — — 0000 — — URXISEL 0000 0000 Baud Rate Generator Prescaler 31:16 15:0 22/6 Baud Rate Generator Prescaler 31:16 2800 U5MODE(1) 15:0 (1) 23/7 All Resets Register Name Bit Range Bits 2600 U4MODE(1) 2610 UART1 THROUGH UART6 REGISTER MAP (CONTINUED) 0000 0000 0000 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family  2015-2021 Microchip Technology Inc. TABLE 22-1: PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 22-1: Bit Range 31:24 23:16 15:8 7:0 UxMODE: UARTx MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ON — SIDL IREN RTSMD — R/W-0 (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH UEN R/W-0 PDSEL R/W-0 STSEL Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: UARTx Enable bit 1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN  control bits 0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx registers; UARTx power consumption is minimal bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation in Idle mode bit 12 IREN: IrDA Encoder and Decoder Enable bit 1 = IrDA is enabled 0 = IrDA is disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode bit 10 Unimplemented: Read as ‘0’ bit 9-8 UEN: UARTx Enable bits(1) 11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit 1 = Wake-up is enabled 0 = Wake-up is disabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Loopback mode is enabled 0 = Loopback mode is disabled Note 1: These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices. For additional information, see Section 12.4 “Peripheral Pin Select (PPS)”. DS60001320H-page 378  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 22-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55); cleared by hardware upon completion 0 = Baud rate measurement is disabled or completed bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ bit 3 BRGH: High Baud Rate Enable bit 1 = High-Speed mode – 4x baud clock enabled 0 = Standard Speed mode – 16x baud clock enabled bit 2-1 PDSEL: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Selection bit 1 = 2 Stop bits 0 = 1 Stop bit Note 1: These bits are present for legacy compatibility, and are superseded by PPS functionality on these devices. For additional information, see Section 12.4 “Peripheral Pin Select (PPS)”.  2015-2021 Microchip Technology Inc. DS60001320H-page 379 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 22-2: Bit Range 31:24 23:16 15:8 7:0 UxSTA: UARTx STATUS AND CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — ADM_EN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR R/W-0 R/W-0 UTXISEL R/W-0 R/W-0 URXISEL R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1 UTXINV URXEN UTXBRK UTXEN UTXBF TRMT R/W-0 R-1 R-0 R-0 R/W-0 R-0 ADDEN RIDLE PERR FERR OERR URXDA Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-25 Unimplemented: Read as ‘0’ bit 24 ADM_EN: Automatic Address Detect Mode Enable bit 1 = Automatic Address Detect mode is enabled 0 = Automatic Address Detect mode is disabled bit 23-16 ADDR: Automatic Address Mask bits When the ADM_EN bit is ‘1’, this value defines the address character to use for automatic address detection. bit 15-14 UTXISEL: TX Interrupt Mode Selection bits 11 = Reserved, do not use 10 = Interrupt is generated and asserted while the transmit buffer is empty 01 = Interrupt is generated and asserted when all characters have been transmitted 00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space bit 13 UTXINV: Transmit Polarity Inversion bit If IrDA mode is disabled (i.e., IREN (UxMODE) is ‘0’): 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IrDA mode is enabled (i.e., IREN (UxMODE) is ‘1’): 1 = IrDA encoded UxTX Idle state is ‘1’ 0 = IrDA encoded UxTX Idle state is ‘0’ bit 12 URXEN: Receiver Enable bit 1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1) 0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module bit 11 UTXBRK: Transmit Break bit 1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Break transmission is disabled or completed bit 10 UTXEN: Transmit Enable bit 1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1) 0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register is Empty bit (read-only) 1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer DS60001320H-page 380  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 22-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL: Receive Interrupt Mode Selection bit 11 = Reserved 10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full 01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full 00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect 0 = Address Detect mode is disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Data is being received bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit. This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit resets the receiver buffer and RSR to empty state. 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty  2015-2021 Microchip Technology Inc. DS60001320H-page 381 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Figure 22-2 and Figure 22-3 illustrate the typical receive and transmit timing for the UART module. FIGURE 22-2: UART RECEPTION Char 1 Char 2-4 Char 5-10 Char 11-13 Read to UxRXREG Start 1 Stop Start 2 Stop 4 Start 5 Stop 10 Start 11 Stop 13 UxRX RIDLE Cleared by Software OERR Cleared by Software UxRXIF URXISEL = 00 Cleared by Software UxRXIF URXISEL = 01 UxRXIF URXISEL = 10 FIGURE 22-3: TRANSMISSION (8-BIT OR 9-BIT DATA) 8 into TxBUF Write to UxTXREG TSR Pull from Buffer BCLK/16 (Shift Clock) UxTX Start Bit 0 Bit 1 Stop Start Bit 1 UxTXIF UTXISEL = 00 UxTXIF UTXISEL = 01 UxTXIF UTXISEL = 10 DS60001320H-page 382  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 23.0 PARALLEL HOST PORT (PMP) Note: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Parallel Master Port (PMP)” (DS60001128) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The PMP is a parallel 8-bit/16-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable. The following are key features of the PMP module: • • • • • • • • • • • • 8-bit,16-bit interface Up to 16 programmable address lines Up to two Chip Select lines Programmable strobe options: - Individual read and write strobes, or - Read/write strobe with enable strobe Address auto-increment/auto-decrement Programmable address/data multiplexing Programmable polarity on control signals Parallel Client Port (PSP) support: - Legacy addressable - Address support - 4-byte deep auto-incrementing buffer Programmable Wait states Operate during Sleep and Idle modes Separate configurable read/write registers or dual buffers for Host mode Fast bit manipulation using CLR, SET, and INV registers Note: FIGURE 23-1: On 64-pin devices, data pins PMD are not available in 16-bit Host modes. PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES PBCLK2 Address Bus Data Bus Parallel Host Port Control Lines PMA0 PMALL PMA1 PMALH Flash EEPROM SRAM Up to 16-bit Address PMA PMA14 PMCS1 PMA15 PMCS2 PMRD PMRD/PMWR PMWR PMENB PMD PMD(1) Note: Microcontroller LCD FIFO Buffer 8-bit/16-bit Data (with or without multiplexed addressing) On 64-pin devices, data pins PMD are not available in 16-bit Host modes.  2015-2021 Microchip Technology Inc. DS60001320H-page 383 PMP Control Registers Virtual Address (BF82_#) Register Name(1) TABLE 23-1: E000 PMCON E010 PMMODE E020 E030 PARALLEL HOST PORT REGISTER MAP PMADDR PMDOUT E040 E050 E060 PMDIN PMAEN PMSTAT E070 PMWADDR 31/15 30/14 31:16 — — — 15:0 ON — SIDL 31:16 — — — 15:0 BUSY 31:16 — — CS2 CS1 ADDR15 ADDR14 — — 15:0 31:16  2015-2021 Microchip Technology Inc. E090 PMRDIN IRQM — 28/12 27/11 — — ADRMUX — — INCM — — 26/10 25/9 24/8 23/7 22/6 — — — RDSTART — PMPTTL PTWREN PTRDEN — MODE16 — — 31:16 — — WAITB — — — — 21/5 20/4 19/3 18/2 17/1 16/0 — — — — DUALBUF — 0000 ALP CS2P CS1P — WRSP RDSP 0000 — — — — — — 0000 WAITE 0000 — 0000 WAITM — — — — — 0000 ADDR — — — — — — — 0000 — — — — — — — — — — — — — — — — — — — — — DATAOUT — — — — — — — 15:0 31:16 — CSF MODE 15:0 — — — — — — — — — 0000 0000 — DATAIN 15:0 0000 0000 — 0000 0000 PTEN 31:16 — — — — — — — — — — — — — — — — 0000 15:0 IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008F 31:16 — — — — — — — — — — — — — — — — 0000 WCS2 WCS1 — — — — — — — — — — — — — — 0000 15:0 31:16 E080 PMRADDR 29/13 All Resets Bit Range Bits 15:0 WADDR15 WADDR14 0000 WADDR — — — — — — — — — — — — — — — — 0000 RCS2 RCS1 — — — — — — — — — — — — — — 0000 — — — — — — RADDR15 RADDR14 31:16 31:16 15:0 15:0 — 0000 RADDR — — — — — — — RDATAIN — 0000 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 384 23.1 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-1: Bit Range 31:24 23:16 15:8 7:0 PMCON: PARALLEL PORT CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0, HC U-0 U-0 U-0 U-0 U-0 R/W-0 RDSTART — — — — — DUALBUF — R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ON — SIDL PMPTTL PTWREN PTRDEN R/W-0 R/W-0 CSF(1) ADRMUX R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ALP(1) CS2P(1) CS1P(1) — WRSP RDSP Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23 RDSTART: Start Read on PMP Bus bit This bit is cleared by hardware at the end of the read cycle. 1 = Start a read cycle on the PMP bus 0 = No effect bit 22-18 Unimplemented: Read as ‘0’ bit 17 DUALBUF: Dual Read/Write Buffers enable bit This bit is valid in Host mode only. 1 = PMP uses separate registers for reads and writes (PMRADDR, PMDATAIN, PMWADDR, PMDATAOUT) 0 = PMP uses legacy registers (PMADDR, PMDATA) bit 16 Unimplemented: Read as ‘0’ bit 15 ON: Parallel Host Port Enable bit 1 = PMP is enabled 0 = PMP is disabled, no off-chip access performed bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 ADRMUX: Address/Data Multiplexing Selection bits 11 = Lower 8 bits of address are multiplexed on PMD pins; upper 8 bits are not used 10 = All 16 bits of address are multiplexed on PMD pins 01 = Lower 8 bits of address are multiplexed on PMD pins, upper bits are on PMA 00 = Address and data appear on separate pins bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffer bit 9 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port is enabled 0 = PMWR/PMENB port is disabled bit 8 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port is enabled 0 = PMRD/PMWR port is disabled Note 1: These bits have no effect when their corresponding pins are used as address lines.  2015-2021 Microchip Technology Inc. DS60001320H-page 385 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 7-6 CSF: Chip Select Function bits(1) 11 = Reserved 10 = PMCS1 and PMCS2 function as Chip Select 01 = PMCS2 functions as Chip Select and PMCS1 functions as address bit 14 00 = PMCS1 and PMCS2 function as address bit 14 and address bit 15 bit 5 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 CS2P: Chip Select 2 Polarity bit(1) 1 = Active-high (PMCS2) 0 = Active-low (PMCS2) bit 3 CS1P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS1) 0 = Active-low (PMCS1) bit 2 Unimplemented: Read as ‘0’ bit 1 WRSP: Write Strobe Polarity bit For Client Modes and Host mode 2 (MODE = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Host mode 1 (MODE = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Client modes and Host mode 2 (MODE = 00,01,10): 1 = Read Strobe active-high (PMRD) 0 = Read Strobe active-low (PMRD) For Host mode 1 (MODE = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. DS60001320H-page 386  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-2: Bit Range 31:24 23:16 15:8 PMMODE: PARALLEL PORT MODE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY R/W-0 7:0 IRQM R/W-0 R/W-0 WAITB(1) INCM R/W-0 R/W-0 MODE16 MODE R/W-0 R/W-0 WAITM(1) R/W-0 WAITE(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 BUSY: Busy bit (Host mode only) 1 = Port is busy 0 = Port is not busy bit 14-13 IRQM: Interrupt Request Mode bits (4) 11 = Reserved, do not use 10 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered Parallel Client Port (PSP) mode) or on a read or write operation when PMA =11 (Addressable Client mode only) 01 = Interrupt is generated at the end of the read/write cycle 00 = No Interrupt is generated bit 12-11 INCM: Increment Mode bits 11 = Client mode read and write buffers auto-increment (MODE = 00 only) 10 = Decrement ADDR and ADDR by 1 every read/write cycle(2) 01 = Increment ADDR and ADDR by 1 every read/write cycle(2) 00 = No increment or decrement of address bit 10 MODE16: 8/16-bit Mode bit 1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer 0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer bit 9-8 MODE: Parallel Port Mode Select bits 11 = Host mode 1 (PMCSx, PMRD/PMWR, PMENB, PMA, and PMD)(3) 10 = Host mode 2 (PMCSx, PMRD, PMWR, PMA, and PMD)(3) 01 = Enhanced Client mode, control signals (PMRD, PMWR, PMCSx, PMD, and PMA) 00 = Legacy Parallel Client Port, control signals (PMRD, PMWR, PMCSx, and PMD) Note 1: Whenever WAITM = 0000, the WAITB and WAITE bits are ignored and forced to 1 TPBCLK2 cycle for a write operation; WAITB = 1 TPBCLK2 cycle, WAITE = 0 TPBCLK2 cycles for a read operation. 2: The Address bits, 14 and 15, are not subject to auto-increment/auto-decrement if configured as Chip Select. 3: The PMD pins are not active unless PMMODE bit = 1. 4: These bits only control the generation of the Parallel Host Port (PMP) interrupt. The Parallel Host Port Error (PMPE) is always generated.  2015-2021 Microchip Technology Inc. DS60001320H-page 387 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) bit 7-6 WAITB: Data Setup to Read/Write Strobe Wait States bits(1) 11 = Data wait of 4 TPBCLK2; multiplexed address phase of 4 TPBCLK2 10 = Data wait of 3 TPBCLK2; multiplexed address phase of 3 TPBCLK2 01 = Data wait of 2 TPBCLK2; multiplexed address phase of 2 TPBCLK2 00 = Data wait of 1 TPBCLK2; multiplexed address phase of 1 TPBCLK2 (default) bit 5-2 WAITM: Data Read/Write Strobe Wait States bits(1) 1111 = Wait of 16 TPBCLK2 • • • 0001 = Wait of 2 TPBCLK2 0000 = Wait of 1 TPBCLK2 (default) bit 1-0 WAITE: Data Hold After Read/Write Strobe Wait States bits(1) 11 = Wait of 4 TPBCLK2 10 = Wait of 3 TPBCLK2 01 = Wait of 2 TPBCLK2 00 = Wait of 1 TPBCLK2 (default) For Read operations: 11 = Wait of 3 TPBCLK2 10 = Wait of 2 TPBCLK2 01 = Wait of 1 TPBCLK2 00 = Wait of 0 TPBCLK2 (default) Note 1: Whenever WAITM = 0000, the WAITB and WAITE bits are ignored and forced to 1 TPBCLK2 cycle for a write operation; WAITB = 1 TPBCLK2 cycle, WAITE = 0 TPBCLK2 cycles for a read operation. 2: The Address bits, 14 and 15, are not subject to auto-increment/auto-decrement if configured as Chip Select. 3: The PMD pins are not active unless PMMODE bit = 1. 4: These bits only control the generation of the Parallel Host Port (PMP) interrupt. The Parallel Host Port Error (PMPE) is always generated. DS60001320H-page 388  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-3: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 (1) R/W-0 (3) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CS2 ADDR15 7:0 PMADDR: PARALLEL PORT ADDRESS REGISTER R/W-0 CS1 (2) ADDR ADDR14(4) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 CS2: Chip Select 2 bit(1) 1 = Chip Select 2 is active 0 = Chip Select 2 is inactive bit 15 ADDR: Target Address bit 15(2) bit 14 CS1: Chip Select 1 bit(3) 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive bit 14 ADDR: Target Address bit 14(4) bit 13-0 ADDR: Address bits Note 1: 2: 3: 4: When the CSF bits (PMCON) = 10 or 01. When the CSF bits (PMCON) = 00. When the CSF bits (PMCON) = 10. When the CSF bits (PMCON) = 00 or 01. Note: If the DUALBUF bit (PMCON) = 0, the bits in this register control both read and write target addressing. If the DUALBUF bit = 1, the bits in this register are not used. In this instance, use the PMRADDR register for Read operations and the PMWADDR register for Write operations.  2015-2021 Microchip Technology Inc. DS60001320H-page 389 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-4: Bit Range 31:24 23:16 15:8 7:0 PMDOUT: PARALLEL PORT OUTPUT DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATAOUT R/W-0 R/W-0 DATAOUT Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 DATAOUT: Port Data Output bits This register is used for Read operations in the Enhanced Parallel Client mode and Write operations for Dual Buffer Host mode. In Dual Buffer Host mode, the DUALBUF bit (PMPCON) = 1, a write to the MSB triggers the transaction on the PMP port. When MODE16 = 1, MSB = DATAOUT. When MODE16 = 0, MSB = DATAOUT. Note: In Host mode, a read will return the last value written to the register. In Client mode, a read will return indeterminate results. REGISTER 23-5: Bit Range 31:24 23:16 15:8 7:0 PMDIN: PARALLEL PORT INPUT DATA REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DATAIN R/W-0 R/W-0 DATAIN Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 DATAIN: Port Data Input bits This register is used for both Parallel Host Port mode and Enhanced Parallel Client mode. In Parallel Host mode, a write to the MSB triggers the write transaction on the PMP port. Similarly, a read to the MSB triggers the read transaction on the PMP port. When MODE16 = 1, MSB = DATAIN. When MODE16 = 0, MSB = DATAIN. Note: This register is not used in Dual Buffer Host mode (i.e., DUALBUF bit (PMPCON) = 1). DS60001320H-page 390  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-6: Bit Range 31:24 23:16 15:8 PMAEN: PARALLEL PORT PIN ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN R/W-0 7:0 PTEN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as ‘0’ bit 15-14 PTEN: PMCS1 Strobe Enable bits 1 = PMA15 and PMA14 function as either PMA or PMCS1 and PMCS2(1) 0 = PMA15 and PMA14 function as port I/O bit 13-2 PTEN: PMP Address Port Enable bits 1 = PMA function as PMP address lines 0 = PMA function as port I/O bit 1-0 PTEN: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL(2) 0 = PMA1 and PMA0 pads function as port I/O Note 1: The use of these pins as PMA15 and PMA14 or CS1 and CS2 is selected by the CSF bits in the PMCON register. 2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode selected by bits ADRMUX in the PMCON register.  2015-2021 Microchip Technology Inc. DS60001320H-page 391 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-7: Bit Range 31:24 23:16 15:8 7:0 PMSTAT: PARALLEL PORT STATUS REGISTER (CLIENT MODES ONLY) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R-0 R/W-0, HS, SC U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV — — IB3F IB2F IB1F IB0F R-1 R/W-0, HS, SC U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF — — OB3E OB2E OB1E OB0E Legend: HS = Hardware Set SC = Software Cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit (1) 1 = A write attempt to a full input byte buffer is occurred (must be cleared in software) 0 = No overflow is occurred bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 IBxF: Input Buffer x Status Full bits 1 = Input Buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input Buffer does not contain any unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bit (1) 1 = A read occurred from an empty output byte buffer (must be cleared in software) 0 = No underflow is occurred bit 5-4 Unimplemented: Read as ‘0’ bit 3-0 OBxE: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted Note 1: This bit will generate a Parallel Host Port Error (PMPE) interrupt. DS60001320H-page 392  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-8: Bit Range 31:24 23:16 15:8 PMWADDR: PARALLEL PORT WRITE ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 (1) R/W-0 (3) WCS2 WADDR15 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCS1 (2) 7:0 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 WADDR WADDR14(4) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WADDR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 WCS2: Chip Select 2 bit(1) 1 = Chip Select 2 is active 0 = Chip Select 2 is inactive bit 15 WADDR: Target Address bit 15(2) bit 14 WCS1: Chip Select 1 bit(3) 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive bit 14 WADDR: Target Address bit 14(4) bit 13-0 WADDR: Address bits Note 1: 2: 3: 4: When the CSF bits (PMCON) = 10 or 01. When the CSF bits (PMCON) = 00. When the CSF bits (PMCON) = 10. When the CSF bits (PMCON) = 00 or 01. Note: This register is only used when the DUALBUF bit (PMCON) is set to ‘1’.  2015-2021 Microchip Technology Inc. DS60001320H-page 393 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-9: Bit Range 31:24 23:16 15:8 PMRADDR: PARALLEL PORT READ ADDRESS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 (1) R/W-0 (3) RCS2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RCS1 (2) RADDR15 7:0 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 RADDR RADDR14(4) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RADDR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 RCS2: Chip Select 2 bit(1) 1 = Chip Select 2 is active 0 = Chip Select 2 is inactive (RADDR15 function is selected) bit 15 RADDR: Target Address bit 15(2) bit 14 RCS1: Chip Select 1 bit(3) 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive (RADDR14 function is selected) bit 14 RADDR: Target Address bit 14(4) bit 13-0 RADDR: Address bits Note 1: 2: 3: 4: When the CSF bits (PMCON) = 10 or 01. When the CSF bits (PMCON) = 00. When the CSF bits (PMCON) = 10. When the CSF bits (PMCON) = 00 or 01. Note: This register is only used when the DUALBUF bit (PMCON) is set to ‘1’. DS60001320H-page 394  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 23-10: PMRDIN: PARALLEL PORT READ INPUT DATA REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RDATAIN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RDATAIN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 Note: RDATAIN: Port Read Input Data bits This register is only used when the DUALBUF bit (PMCON) is set to ‘1’ and exclusively for reads. If the DUALBUF bit is ‘0’, the PMDIN register (Register 23-5) is used for reads instead of PMRDIN.  2015-2021 Microchip Technology Inc. DS60001320H-page 395 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320H-page 396  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 24.0 EXTERNAL BUS INTERFACE (EBI) Note: TABLE 24-1: Feature This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 47. “External Bus Interface (EBI)” (DS60001245) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The External Bus Interface (EBI) module provides a high-speed, convenient way to interface external parallel memory devices to the PIC32MZ EF family device. With the EBI module, it is possible to connect asynchronous SRAM and NOR Flash devices, as well as non-memory devices such as camera sensors and LCDs. 124 144 Async SRAM Y Y Y Async NOR Flash Y Y Y Available address lines 20 20 24 8-bit data bus support Y Y Y 16-bit data bus support Y Y Y Available Chip Selects 1 1 4 Timing mode sets 3 3 3 8-bit R/W from 16-bit bus N N Y Non-memory device Y Y Y LCD Y Y Y Note: The EBI module is not available on 64-pin devices. FIGURE 24-1: Number of Device Pins 100 The features of the EBI module depend on the pin count of the PIC32MZ EF device, as shown in Table 24-1. Note: EBI MODULE FEATURES Once the EBI module is configured, external devices will be memory mapped and can be access from KSEG2 memory space (see Figure 4-1 through Figure 4-4 in Section 4.0 “Memory Organization” for more information). The MMU must be enabled and the TLB must be set up to access this memory (refer to Section 50. “CPU for Devices with MIPS32® microAptiv™ and M-Class Cores” (DS60001192) of the “PIC32 Family Reference Manual” for more information). EBI SYSTEM BLOCK DIAGRAM External Bus Interface Bus Interface Memory Interface EBIA EBID SYSCLK Control Registers Address Decoder EBIBS EBICS System Bus Data FIFO Control Registers EBIOE EBIRP Static Memory Controller Address FIFO  2015-2021 Microchip Technology Inc. EBIWE EBIRDY DS60001320H-page 397 EBI Control Registers Virtual Address (BF8E_#) Register Name TABLE 24-2: 1014 EBICS0 1018 EBICS3 30/14 29/13 28/12 27/11 26/10 25/9 24/8 — — — — — — — — 31:16 15:0 31:16 EBICS1(1) 15:0 (1) 31/15 22/6 21/5 20/4 19/3 18/2 17/1 16/0 — — — — — — — — — — — — — — — — — — — — — CSADDR — 0000 CSADDR — — — — — — — — 31:16 15:0 23/7 — — — — — — — — 31:16 — 0000 0000 CSADDR — All Resets Bit Range Bits 101C EBICS2(1) 1020 EBI REGISTER MAP 0000 0000 CSADDR 0000 0000 15:0 — — — — — — — — — — — — — — — — 0000 31:16 — — — — — — — — — — — — — — — — 0000 15:0 — — — — — 31:16 1058 EBIMSK1(1) 15:0 — — — — — — — — — — — — 31:16 — — — — — — — 15:0 — — — — — 31:16 — — — — — — — 15:0 — — — — — 31:16 — — — — — 1054 EBIMSK0 105C EBIMSK2(1) 1060 EBIMSK3 1094 (1) EBISMT0 1098 EBISMT1 109C EBISMT2  2015-2021 Microchip Technology Inc. 10A0 EBIFTRPD 10A4 EBISMCON Legend: Note 1: 15:0 31:16 — — — — — — — — — — — — — 15:0 — — — — 31:16 — — — — SMDWIDTH2 — — — — — — — — — REGSEL TWR — — 0020 — — — — — — 041C 2D4B TPRC TBTA 041C TRC 2D4B TPRC TBTA 014C TRC — — 2D4B — — — — — TRPD — SMDWIDTH1 — — — 0000 0120 TBTA TRC TAS 0000 0120 MEMSIZE TAS 0000 0020 MEMSIZE TAS — — TPRC RDYMODE PAGESIZE PAGEMODE — — MEMTYPE RDYMODE PAGESIZE PAGEMODE — — MEMSIZE — — RDYMODE PAGESIZE PAGEMODE — — MEMTYPE TWR — — MEMSIZE MEMTYPE TWR — — REGSEL TWP 31:16 — MEMTYPE REGSEL TWP 15:0 15:0 — TWP 15:0 31:16 REGSEL 0000 00C8 — — — — — — — — 0000 SMDWIDTH0 — — — — — — SMRP 0201 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register is available on 144-pin devices only. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 398 24.1 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 24-1: Bit Range 31:24 23:16 15:8 7:0 EBICSx: EXTERNAL BUS INTERFACE CHIP SELECT REGISTER (‘x’ = 0-3) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSADDR U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 CSADDR: Base Address for Device bits Address in physical memory, which will select the external device. Note: Memory base address must be aligned on memory size boundary selected by EBIMSKx:MEMSIZE. For example, 2MB of memory can be assigned at base address 0x2000_0000 and 0x2020_0000 , but not at 0x2010_0000. bit 15-0 Unimplemented: Read as ‘0’  2015-2021 Microchip Technology Inc. DS60001320H-page 399 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 24-2: Bit Range 31:24 23:16 15:8 EBIMSKx: EXTERNAL BUS INTERFACE ADDRESS MASK REGISTER (‘x’ = 0-3) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 7:0 REGSEL R/W-0 R/W-0 R/W-0 MEMSIZE(1) MEMTYPE Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-11 Unimplemented: Read as ‘0’ bit 10-8 REGSEL: Timing Register Set for Chip Select ‘x’ bits 111 = Reserved • • • 011 = Reserved 010 = Use EBISMT2 001 = Use EBISMT1 000 = Use EBISMT0 bit 7-5 MEMTYPE: Select Memory Type for Chip Select ‘x’ bits 111 = Reserved • • • 011 = Reserved 010 = NOR-Flash 001 = SRAM 000 = Reserved bit 4-0 MEMSIZE: Select Memory Size for Chip Select ‘x’ bits(1) 11111 = Reserved • • • 01010 = Reserved 01001 = 16 MB 01000 = 8 MB 00111 = 4 MB 00110 = 2 MB 00101 = 1 MB 00100 = 512 KB 00011 = 256 KB 00010 = 128 KB 00001 = 64 KB (smaller memories alias within this range) 00000 = Chip Select is not used Note 1: The specified value for these bits depends on the number of available address lines. Refer to the specific device pin table (Table 2 through Table 6) for the available address lines. DS60001320H-page 400  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 24-3: Bit Range 31:24 23:16 15:8 7:0 EBISMTx: EXTERNAL BUS INTERFACE STATIC MEMORY TIMING REGISTER  (‘x’ = 0-2) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 U-0 U-0 U-0 U-0 — — — — R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 R/W-1 R/W-0 R/W-0 — RDYMODE R/W-1 R/W-1 R/W-1 TPRC(1) PAGEMODE R/W-0 Bit 26/18/10/2 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 TAS(1) Legend: R = Readable bit -n = Value at POR R/W-0 R/W-0 R/W-0 TBTA(1) R/W-1 R/W-1 TWP(1) R/W-0 PAGESIZE R/W-0 R/W-1 TWR(1) R/W-1 R/W-0 R/W-1 R/W-1 TRC(1) W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-27 Unimplemented: Read as ‘0’ bit 26 RDYMODE: Data Ready Device Select bit The device associated with register set ‘x’ is a data-ready device, and will use the EBIRDYx pin. 1 = EBIRDYx input is used 0 = EBIRDYx input is not used bit 25-24 PAGESIZE: Page Size for Page Mode Device bits 11 = 32-word page 10 = 16-word page 01 = 8-word page 00 = 4-word page bit 23 PAGEMODE: Memory Device Page Mode Support bit 1 = Device supports Page mode 0 = Device does not support Page mode bit 22-19 TPRC: Page Mode Read Cycle Time bits(1) Read cycle time is TPRC + 1 clock cycle. bit 18-16 TBTA: Data Bus Turnaround Time bits(1) Clock cycles (0-7) for static memory between read-to-write, write-to-read, and read-to-read when Chip Select changes. bit 15-10 TWP: Write Pulse Width bits(1) Write pulse width is TWP + 1 clock cycle. bit 9-8 TWR: Write Address/Data Hold Time bits(1) Number of clock cycles to hold address or data on the bus. bit 7-6 TAS: Write Address Setup Time bits(1) Clock cycles for address setup time. A value of ‘0’ is only valid in the case of SSRAM. bit 5-0 TRC: Read Cycle Time bits(1) Read cycle time is TRC + 1 clock cycle. Note 1: Refer to the Section 47. “External Bus Interface (EBI)” in the “PIC32 Family Reference Manual” for the EBI timing diagrams and additional information.  2015-2021 Microchip Technology Inc. DS60001320H-page 401 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 24-4: Bit Range 31:24 23:16 15:8 7:0 EBIFTRPD: EXTERNAL BUS INTERFACE FLASH TIMING REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — R/W-0 R/W-0 R/W-0 R/W-0 TRPD R/W-0 R/W-0 R/W-0 R/W-0 TRPD Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-12 Unimplemented: Read as ‘0’ bit 11-0 TRPD: Flash Timing bits These bits define the number of clock cycles to wait after resetting the external Flash memory before any read/write access. DS60001320H-page 402  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 24-5: Bit Range Bit 31/23/15/7 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 23:16 7:0 Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 U-0 31:24 15:8 EBISMCON: EXTERNAL BUS INTERFACE STATIC MEMORY CONTROL REGISTER SMDWIDTH2 SMDWIDTH1 SMDWIDTH0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1 SMDWIDTH0 — — — — — — SMRP Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-13 SMDWIDTH2: Static Memory Width for Register EBISMT2 bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = 8 bits 011 = Reserved 010 = Reserved 001 = Reserved 000 = 16 bits bit 12-10 SMDWIDTH1: Static Memory Width for Register EBISMT1 bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = 8 bits 011 = Reserved 010 = Reserved 001 = Reserved 000 = 16 bits bit 9-7 SMDWIDTH0: Static Memory Width for Register EBISMT0 bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = 8 bits 011 = Reserved 010 = Reserved 001 = Reserved 000 = 16 bits bit 6-1 Unimplemented: Read as ‘0’ bit 0 SMRP: Flash Reset/Power-down mode Select bit After a Reset, the controller internally performs a power-down for Flash, and then sets this bit to ‘1’. 1 = Flash is taken out of Power-down mode 0 = Flash is forced into Power-down mode  2015-2021 Microchip Technology Inc. DS60001320H-page 403 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family NOTES: DS60001320H-page 404  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 25.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) The following are key features of the RTCC module: • • • • • This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). • • • • • • • • The RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Lowpower optimization provides extended battery lifetime while keeping track of time. • • • • FIGURE 25-1: Time: hours, minutes, and seconds 24-hour format (military time) Visibility of one-half second period Provides calendar: Weekday, date, month and year Alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month, and one year Alarm repeat with decrementing counter Alarm with indefinite repeat: Chime Year range: 2000 to 2099 Leap year correction BCD format for smaller firmware overhead Optimized for long-term battery operation Fractional second synchronization User calibration of the clock crystal frequency with auto-adjust Calibration range: 0.66 seconds error per month Calibrates up to 260 ppm of crystal error Uses external 32.768 kHz crystal or 32 kHz internal oscillator Alarm pulse, seconds clock, or internal clock output on RTCC pin RTCC BLOCK DIAGRAM RTCCLKSEL 32.768 kHz Input from Secondary Oscillator (SOSC) 32 kHz Input from Internal Oscillator (LPRC) TRTC RTCC Prescalers 0.5 seconds YEAR, MTH, DAY RTCVAL RTCC Timer Alarm Event WKDAY HR, MIN, SEC Comparator MTH, DAY Compare Registers with Masks ALRMVAL WKDAY HR, MIN, SEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse Seconds Pulse TRTC RTCC Pin RTCOE RTCOUTSEL  2015-2021 Microchip Technology Inc. DS60001320H-page 405 RTCC Control Registers 0C00 RTCCON 0C10 RTCALRM 0C20 RTCTIME 0C30 RTCDATE 0C40 ALRMTIME 0C50 ALRMDATE Legend: Note 1: RTCC REGISTER MAP 31/15 30/14 31:16 — 15:0 ON 31:16 — 15:0 ALRMEN 29/13 28/12 27/11 — — — — — SIDL — — — — — — CHIME PIV ALRMSYNC 26/10 25/9 — — SEC10 SEC01 31:16 YEAR10 YEAR01 15:0 DAY10 DAY01 31:16 HR10 HR01 15:0 SEC10 SEC01 15:0 DAY10 — — — 20/4 — — — — — — — AMASK 15:0 — 21/5 19/3 18/2 17/1 16/0 CAL HR01 — 22/6 — HR10 — 23/7 RTCCLKSEL RTCOUTSEL RTCCLKON 31:16 31:16 24/8 — DAY01 0000 RTCWREN RTCSYNC HALFSEC RTCOE — — — — ARPT MIN10 — — — — MONTH10 — — — — MIN10 — — — — MONTH10 — — — — — — — 0000 xxxx — xx00 MONTH01 xxxx WDAY01 xx00 MIN01 — 0000 0000 MIN01 — All Resets Bit Range Bits Register Name(1) Virtual Address (BF80_#) TABLE 25-1: — — xxxx — xx00 MONTH01 00xx WDAY01 xx0x x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.3 “CLR, SET, and INV Registers” for more information.  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 406 25.1 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-1: Bit Range Bit 31/23/15/7 31:24 23:16 Bit Bit Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL CAL 15:8 7:0 RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 ON(1) — SIDL — — RTCCLKSEL R/W-0 R-0 U-0 U-0 R/W-0 R-0 R-0 R/W-0 — — RTC WREN(3) RTC SYNC HALFSEC(4) RTCOE RTC RTC OUTSEL(2) CLKON(5) RTC OUTSEL(2) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-26 Unimplemented: Read as ‘0’ bit 25-16 CAL: Real-Time Clock Drift Calibration bits, which contain a signed 10-bit integer value 0111111111 = Maximum positive adjustment, adds 511 real-time clock pulses every one minute • • • 0000000001 = Minimum positive adjustment, adds 1 real-time clock pulse every one minute 0000000000 = No adjustment 1111111111 = Minimum negative adjustment, subtracts 1 real-time clock pulse every one minute • • • 1000000000 = Maximum negative adjustment, subtracts 512 real-time clock pulses every one minute bit 15 ON: RTCC On bit(1) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Disables RTCC operation when CPU enters Idle mode 0 = Continue normal operation when CPU enters Idle mode bit 12-11 Unimplemented: Read as ‘0’ Note 1: 2: 3: 4: 5: Note: The ON bit is only writable when RTCWREN = 1. Requires RTCOE = 1 (RTCCON) for the output to be active. The RTCWREN bit can be set only when the write sequence is enabled. This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME). This bit is undefined when RTCCLKSEL = 00 (LPRC is the clock source). This register is reset only on a Power-on Reset (POR).  2015-2021 Microchip Technology Inc. DS60001320H-page 407 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-1: RTCCON: REAL-TIME CLOCK AND CALENDAR CONTROL REGISTER bit 10-9 RTCCLKSEL: RTCC Clock Select bits When a new value is written to these bits, the Seconds Value register should also be written to properly reset the clock prescalers in the RTCC. 11 = Reserved 10 = Reserved 01 = RTCC uses the external 32.768 kHz Secondary Oscillator (SOSC) 00 = RTCC uses the internal 32 kHz oscillator (LPRC) bit 8-7 RTCOUTSEL: RTCC Output Data Select bits(2) 11 = Reserved 10 = RTCC Clock is presented on the RTCC pin 01 = Seconds Clock is presented on the RTCC pin 00 = Alarm Pulse is presented on the RTCC pin when the alarm interrupt is triggered bit 6 RTCCLKON: RTCC Clock Enable Status bit(5) 1 = RTCC Clock is actively running 0 = RTCC Clock is not running bit 5-4 Unimplemented: Read as ‘0’ bit 3 RTCWREN: Real-Time Clock Value Registers Write Enable bit(3) 1 = Real-Time Clock Value registers can be written to by the user 0 = Real-Time Clock Value registers are locked out from being written to by the user bit 2 RTCSYNC: Real-Time Clock Value Registers Read Synchronization bit 1 = Real-time clock value registers can change while reading (due to a rollover ripple that results in an invalid data read). If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = Real-time clock value registers can be read without concern about a rollover ripple bit 1 HALFSEC: Half-Second Status bit(4) 1 = Second half period of a second 0 = First half period of a second bit 0 RTCOE: RTCC Output Enable bit 1 = RTCC output is enabled 0 = RTCC output is not enabled Note 1: 2: 3: 4: 5: The ON bit is only writable when RTCWREN = 1. Requires RTCOE = 1 (RTCCON) for the output to be active. The RTCWREN bit can be set only when the write sequence is enabled. This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME). This bit is undefined when RTCCLKSEL = 00 (LPRC is the clock source). Note: This register is reset only on a Power-on Reset (POR). DS60001320H-page 408  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-2: Bit Range 31:24 23:16 15:8 7:0 RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — U-0 U-0 U-0 U-0 U-0 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R-0 R/W-0 R/W-0 CHIME(2) R/W-0 (2) R/W-0 ALRMEN(1,2) R/W-0 (2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PIV ALRMSYNC R/W-0 AMASK R/W-0 ARPT(2) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ALRMEN: Alarm Enable bit(1,2) 1 = Alarm is enabled 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit(2) 1 = Chime is enabled – ARPT is allowed to rollover from 0x00 to 0xFF 0 = Chime is disabled – ARPT stops once it reaches 0x00 bit 13 PIV: Alarm Pulse Initial Value bit(2) When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse. When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse. bit 12 ALRMSYNC: Alarm Sync bit 1 = ARPT and ALRMEN may change as a result of a half second rollover during a read.  The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple bits may be changing. 0 = ARPT and ALRMEN can be read without concerns of rollover because the prescaler is more than 32 real-time clocks away from a half-second rollover bit 11-8 AMASK: Alarm Mask Configuration bits(2) 0000 = Every half-second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29, once every four years) 1010 = Reserved 1011 = Reserved 11xx = Reserved Note 1: 2: Note: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and CHIME = 0. This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1. This register is reset only on a Power-on Reset (POR).  2015-2021 Microchip Technology Inc. DS60001320H-page 409 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-2: RTCALRM: REAL-TIME CLOCK ALARM CONTROL REGISTER (CONTINUED) ARPT: Alarm Repeat Counter Value bits(2) 11111111 = Alarm will trigger 256 times bit 7-0 • • • 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1. Note 1: 2: Note: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and CHIME = 0. This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1. This register is reset only on a Power-on Reset (POR). DS60001320H-page 410  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-3: Bit Range 31:24 23:16 15:8 7:0 RTCTIME: REAL-TIME CLOCK TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10 R/W-x R/W-x HR01 R/W-x R/W-x R/W-x R/W-x MIN10 R/W-x R/W-x R/W-x R/W-x R/W-x MIN01 R/W-x R/W-x R/W-x SEC10 R/W-x R/W-x SEC01 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 HR10: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 HR01: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 MIN10: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 MIN01: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 SEC10: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 SEC01: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as ‘0’ Note: This register is only writable when RTCWREN = 1 (RTCCON).  2015-2021 Microchip Technology Inc. DS60001320H-page 411 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-4: Bit Range 31:24 23:16 15:8 7:0 RTCDATE: REAL-TIME CLOCK DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YEAR10 R/W-x R/W-x R/W-x YEAR01 R/W-x R/W-x MONTH10 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x MONTH01 R/W-x R/W-x R/W-x DAY10 R/W-x R/W-x DAY01 U-0 U-0 U-0 U-0 — — — — R/W-x R/W-x R/W-x R/W-x WDAY01 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 YEAR10: Binary-Coded Decimal Value of Years bits, 10 digits bit 27-24 YEAR01: Binary-Coded Decimal Value of Years bits, 1 digit bit 23-20 MONTH10: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1 bit 19-16 MONTH01: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9 bit 15-12 DAY10: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3 bit 11-8 DAY01: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9 bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 WDAY01: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6 Note: This register is only writable when RTCWREN = 1 (RTCCON). DS60001320H-page 412  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-5: Bit Range 31:24 23:16 15:8 7:0 ALRMTIME: ALARM TIME VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x HR10 R/W-x R/W-x HR01 R/W-x R/W-x R/W-x R/W-x MIN10 R/W-x R/W-x R/W-x R/W-x R/W-x MIN01 R/W-x R/W-x R/W-x SEC10 R/W-x R/W-x SEC01 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 HR10: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 HR01: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 MIN10: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 MIN01: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 SEC10: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 SEC01: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9 bit 7-0 Unimplemented: Read as ‘0’  2015-2021 Microchip Technology Inc. DS60001320H-page 413 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 25-6: Bit Range 31:24 23:16 15:8 7:0 ALRMDATE: ALARM DATE VALUE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 U-0 — — — — — R/W-x R/W-x R/W-x R/W-x R/W-x MONTH10 R/W-x R/W-x R/W-x Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 — — — R/W-x R/W-x R/W-x MONTH01 R/W-x R/W-x R/W-x DAY10 R/W-x R/W-x DAY01 U-0 U-0 U-0 U-0 — — — — R/W-x R/W-x R/W-x R/W-x WDAY01 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23-20 MONTH10: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 MONTH01: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9 bit 15-12 DAY10: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3 bit 11-8 DAY01: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9 bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 WDAY01: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6 DS60001320H-page 414  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Note: CRYPTO ENGINE Bulk ciphers that are handled by the Crypto Engine include: This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 49. “Crypto Engine (CE) and Random Number Generator (RNG)” (DS60001246) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The Crypto Engine is intended to accelerate applications that need cryptographic functions. By executing these functions in the hardware module, software overhead is reduced and actions, such as encryption, decryption, and authentication can execute much more quickly. The Crypto Engine uses an internal descriptor-based DMA for efficient programming of the security association data and packet pointers (allowing scatter/ gather data fetching). An intelligent state machine schedules the Crypto Engines based on the protocol selection and packet boundaries. The hardware engines can perform the encryption and authentication in sequence or in parallel. The following are key features of the Crypto Engine: • Bulk ciphers and hash engines • Integrated DMA to off-load processing: - Buffer descriptor-based - Secure association per buffer descriptor • Some functions can execute in parallel FIGURE 26-1: • AES: - 128-bit, 192-bit, and 256-bit key sizes - CBC, ECB, CTR, CFB, and OFB modes • DES/TDES: - CBC, ECB, CFB, and OFB modes Authentication engines that are available through the Crypto Engine include: • • • • • SHA-1 SHA-256 MD-5 AES-GCM HMAC operation (for all authentication engines) The rate of data that can be processed by the Crypto Engine depends on these factors: • Which engine is in use • Whether the engines are used in parallel or in series • The demands on source and destination memories by other parts of the system (i.e., CPU, DMA, etc.) • The speed of PBCLK5, which drives the Crypto Engine Table 26-1 shows typical performance for various engines. TABLE 26-1: CRYPTO ENGINE PERFORMANCE Engine/ Algorithm Performance Factor (Mbps/MHz) Maximum Mbps (PBCLK5 = 100 MHz) DES TDES AES-128 AES-192 AES-256 MD5 SHA-1 SHA-256 14.4 6.6 9.0 7.9 7.2 15.6 13.2 9.3 1440 660 900 790 720 1560 1320 930 CRYPTO ENGINE BLOCK DIAGRAM INB FIFO Packet RD DMA Controller Crypto FSM System Bus SFR System Bus OUTB FIFO Packet WR AES Local Bus 26.0 TDES SHA-1 SHA-256 MD5 PBCLK5  2015-2021 Microchip Technology Inc. DS60001320H-page 415 Crypto Engine Control Registers TABLE 26-2: CRYPTO ENGINE REGISTER MAP CEVER 5004 CECON 5008 CEBDADDR 500C 5010 CEBDPADDR CESTAT 5014 CEINTSRC 5018 CEINTEN 501C CEPOLLCON 5020 5024 Legend: CEHDLEN CETRLLEN 31/15 30/14 29/13 31:16 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 REVISION 20/4 19/3 18/2 17/1 16/0 VERSION 15:0 0000 ID 31:16 — — — — — — — — 15:0 — — — — — — — — 31:16 — 0000 — — SWAPOEN SWRST SWAPEN — — — — — — — 31:16 0000 0000 0000 BASEADDR 15:0 31:16 ERRMODE ERROP ERRPHASE 15:0 — 0000 — BDSTATE START ACTIVE 0000 BDCTRL 0000 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — AREIF PKTIF CBDIF 31:16 — — — — — — — — — — — — — — — 15:0 — — — — — — — — — — — — AREIE PKTIE CBDIE 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — 15:0 — — — — — — — — — 15:0 — — — — — — — — 31:16 — — — — — — — — 15:0 — — — — — — — — x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. — — 0000 PENDIE 0000 0000 0000 HDRLEN — 0000 PENDIF 0000 BDPPLCON 31:16 0000 BDPCHST BDPPLEN DMAEN 0000 BDPADDR 15:0 All Resets Register Name 5000 Bit Range Virtual Address (BF8E_#) Bits — — — — TRLRLEN 0000 0000 0000 0000  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 416 26.1 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-1: Bit Range 31:24 23:16 15:8 7:0 CEVER: CRYPTO ENGINE REVISION, VERSION, AND ID REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-0 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 REVISION R-0 R-0 R-0 R-0 R-0 VERSION R-0 R-0 R-0 R-0 ID R-0 R-0 R-0 R-0 ID Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 REVISION: Crypto Engine Revision bits bit 23-16 VERSION: Crypto Engine Version bits bit 15-0 ID: Crypto Engine Identification bits  2015-2021 Microchip Technology Inc. DS60001320H-page 417 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-2: Bit Range 31:24 23:16 15:8 7:0 CECON: CRYPTO ENGINE CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0, HC R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 SWAPOEN SWRST SWAPEN — — BDPCHST BDPPLEN DMAEN Legend: HC = Hardware Cleared R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 SWAPOEN: Swap Output Data Enable bit 1 = Output data is byte swapped when written by dedicated DMA 0 = Output data is not byte swapped when written by dedicated DMA bit 6 SWRST: Software Reset bit 1 = Initiate a software reset of the Crypto Engine 0 = Normal operation bit 5 SWAPEN: Input Data Swap Enable bit 1 = Input data is byte swapped when read by dedicated DMA 0 = Input data is not byte swapped when read by dedicated DMA bit 4-3 Unimplemented: Read as ‘0’ bit 2 BDPCHST: Buffer Descriptor Processor (BDP) Fetch Enable bit This bit should be enabled only after all DMA descriptor programming is completed. 1 = BDP descriptor fetch is enabled 0 = BDP descriptor fetch is disabled bit 1 BDPPLEN: Buffer Descriptor Processor Poll Enable bit This bit should be enabled only after all DMA descriptor programming is completed. 1 = Poll for descriptor until valid bit is set 0 = Do not poll bit 0 DMAEN: DMA Enable bit 1 = Crypto Engine DMA is enabled 0 = Crypto Engine DMA is disabled DS60001320H-page 418  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-3: Bit Range 31:24 23:16 15:8 7:0 CEBDADDR: CRYPTO ENGINE BUFFER DESCRIPTOR REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-0 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BDPADDR R-0 R-0 R-0 R-0 R-0 BDPADDR R-0 R-0 R-0 R-0 R-0 BDPADDR R-0 R-0 R-0 R-0 R-0 BDPADDR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 BDPADDR: Current Buffer Descriptor Process Address Status bits These bits contain the current descriptor address that is being processed by the Buffer Descriptor Processor (BDP). REGISTER 26-4: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown CEBDPADDR: CRYPTO ENGINE BUFFER DESCRIPTOR PROCESSOR REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BASEADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BASEADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BASEADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BASEADDR Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 x = Bit is unknown BASEADDR: Buffer Descriptor Base Address bits These bits contain the physical address of the first Buffer Descriptor in the Buffer Descriptor chain. When enabled, the Crypto DMA begins fetching Buffer Descriptors from this address.  2015-2021 Microchip Technology Inc. DS60001320H-page 419 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-5: Bit Range 31:24 CESTAT: CRYPTO ENGINE STATUS REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 R-0 R-0 R-0 R-0 ERRMODE 23:16 15:8 U-0 U-0 — — R-0 R-0 Bit 27/19/11/3 Bit 26/18/10/2 R-0 R-0 ERROP R-0 R-0 R-0 R-0 R-0 Bit 24/16/8/0 R-0 R-0 ERRPHASE R-0 R-0 R-0 START ACTIVE R-0 R-0 R-0 R-0 R-0 R-0 BDSTATE R-0 Bit 25/17/9/1 BDCTRL R-0 7:0 R-0 R-0 R-0 R-0 BDCTRL Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 ERRMODE: Internal Error Mode Status bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = Reserved 011 = CEK operation 010 = KEK operation 001 = Preboot authentication 000 = Normal operation bit 28-26 ERROP: Internal Error Operation Status bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = Authentication 011 = Reserved 010 = Decryption 001 = Encryption 000 = Reserved bit 25-24 ERRPHASE: Internal Error Phase of DMA Status bits 11 = Destination data 10 = Source data 01 = Security Association (SA) access 00 = Buffer Descriptor (BD) access bit 23-22 Unimplemented: Read as ‘0’ bit 21-18 BDSTATE: Buffer Descriptor Processor State Status bits The current state of the BDP: 1111 = Reserved • • • bit 17 0111 = Reserved 0110 = SA fetch 0101 = Fetch BDP is disabled 0100 = Descriptor is done 0011 = Data phase 0010 = BDP is loading 0001 = Descriptor fetch request is pending 0000 = BDP is idle START: DMA Start Status bit 1 = DMA start has occurred 0 = DMA start has not occurred DS60001320H-page 420  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-5: bit 16 bit 15-0 CESTAT: CRYPTO ENGINE STATUS REGISTER (CONTINUED) ACTIVE: Buffer Descriptor Processor Status bit 1 = BDP is active 0 = BDP is idle BDCTRL: Descriptor Control Word Status bits These bits contain the Control Word for the current Buffer Descriptor.  2015-2021 Microchip Technology Inc. DS60001320H-page 421 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-6: Bit Range 31:24 23:16 15:8 7:0 CEINTSRC: CRYPTO ENGINE INTERRUPT SOURCE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0 — — — — AREIF PKTIF CBDIF PENDIF Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as ‘0’ bit 3 AREIF: Access Response Error Interrupt bit 1 = Error occurred trying to access memory outside the Crypto Engine 0 = No error has occurred bit 2 PKTIF: DMA Packet Completion Interrupt Status bit 1 = DMA packet was completed 0 = DMA packet was not completed bit 1 CBDIF: BD Transmit Status bit 1 = Last BD transmit was processed 0 = Last BD transmit has not been processed bit 0 PENDIF: Crypto Engine Interrupt Pending Status bit 1 = Crypto Engine interrupt is pending (this value is the result of an OR of all interrupts in the Crypto Engine) 0 = Crypto Engine interrupt is not pending DS60001320H-page 422  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-7: Bit Range 31:24 23:16 15:8 7:0 CEINTEN: CRYPTO ENGINE INTERRUPT ENABLE REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — AREIE PKTIE BDPIE PENDIE(1) Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as ‘0’ bit 3 AREIE: Access Response Error Interrupt Enable bit 1 = Access response error interrupts are enabled 0 = Access response error interrupts are not enabled bit 2 PKTIE: DMA Packet Completion Interrupt Enable bit 1 = DMA packet completion interrupts are enabled 0 = DMA packet completion interrupts are not enabled bit 1 BDPIE: DMA Buffer Descriptor Processor Interrupt Enable bit 1 = BDP interrupts are enabled 0 = BDP interrupts are not enabled bit 0 PENDIE: Host Interrupt Enable bit(1) 1 = Crypto Engine interrupts are enabled 0 = Crypto Engine interrupts are not enabled Note 1: The PENDIE bit is a global enable bit and must be enabled together with the other interrupts desired.  2015-2021 Microchip Technology Inc. DS60001320H-page 423 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-8: Bit Range 31:24 23:16 15:8 7:0 CEPOLLCON: CRYPTO ENGINE POLL CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDPPLCON R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BDPPLCON Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 BDPPLCON: Buffer Descriptor Processor Poll Control bits These bits determine the number of SYSCLK cycles that the Crypto DMA would wait before refetching the descriptor control word if the Buffer Descriptor fetched was disabled. DS60001320H-page 424  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 26-9: Bit Range 31:24 23:16 15:8 7:0 CEHDLEN: CRYPTO ENGINE HEADER LENGTH REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HDRLEN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 HDRLEN: DMA Header Length bits For every packet, skip this length of locations and start filling the data. x = Bit is unknown REGISTER 26-10: CETRLLEN: CRYPTO ENGINE TRAILER LENGTH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TRLRLEN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 TRLRLEN: DMA Trailer Length bits For every packet, skip this length of locations at the end of the current packet and start putting the next packet.  2015-2021 Microchip Technology Inc. DS60001320H-page 425 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 26.2 Crypto Engine Buffer Descriptors Host software creates a linked list of buffer descriptors and the hardware updates them. Table 26-3 provides a list of the Crypto Engine buffer descriptors, followed by format descriptions of each buffer descriptor (see Figure 26-2 through Figure 26-9). TABLE 26-3: Name (see Note 1) BD_CTRL CRYPTO ENGINE BUFFER DESCRIPTORS Bit 31/2315/7 Bit 30/22/14/6 31:24 DESC_EN — 23:16 — SA_FETCH_EN 15:8 7:0 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 LAST_BD LIFM CRY_MODE — — — 23:16 BD_SAADDR 15:8 BD_SAADDR BD_SRCADDR 23:16 BD_SRCADDR 15:8 BD_SRCADDR BD_SRCADDR BD_DSTADDR 31:24 BD_DSTADDR 23:16 BD_DSTADDR 15:8 BD_DSTADDR BD_UPDPTR 7:0 BD_DSTADDR 31:24 BD_NXTADDR 23:16 BD_NXTADDR 15:8 BD_NXTADDR 7:0 BD_NXTADDR 31:24 BD_UPDADDR 23:16 BD_UPDADDR 15:8 BD_UPDADDR 7:0 BD_UPDADDR BD_MSG_LEN 31:24 MSG_LENGTH 23:16 MSG_LENGTH 15:8 MSG_LENGTH 7:0 MSG_LENGTH BD_ENC_OFF 31:24 ENCR_OFFSET 23:16 ENCR_OFFSET 15:8 ENCR_OFFSET 7:0 ENCR_OFFSET Note 1: — BD_SAADR BD_SCRADDR 31:24 BD_NXTPTR — PKT_INT_EN CBD_INT_EN BD_BUFLEN BD_SAADDR 7:0 Bit 24/16/8/0 BD_BUFLEN BD_SA_ADDR 31:24 7:0 Bit 25/17/9/1 The buffer descriptor must be allocated in memory on a 64-bit boundary. DS60001320H-page 426  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 26-2: FORMAT OF BD_CTRL Bit Range Bit 31/23/15/7 Bit 30/22/14/6 31-24 DESC_EN 23-16 — — SA_ FETCH_EN Bit 29/21/13/5 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 CRY_MODE — — LIFM — PKT_ INT_EN — CBD_ INT_EN — Bit 28/20/12/4 Bit 27/19/11/3 LAST_BD 15-8 BD_BUFLEN 7-0 BD_BUFLEN bit 31 DESC_EN: Descriptor Enable 1 = The descriptor is owned by hardware. After processing the BD, hardware resets this bit to ‘0’. 0 = The descriptor is owned by software bit 30 Unimplemented: Must be written as ‘0’ bit 29-27 CRY_MODE: Crypto Mode 111 = Reserved 110 = Reserved 101 = Reserved 100 = Reserved 011 = CEK operation 010 = KEK operation 001 = Preboot authentication 000 = Normal operation bit 22 SA_FETCH_EN: Fetch Security Association From External Memory 1 = Fetch SA from the SA pointer. This bit needs to be set to ‘1’ for every new packet. 0 = Use current fetched SA or the internal SA bit 21-20 Unimplemented: Must be written as ‘0’ bit 19 LAST_BD: Last Buffer Descriptors 1 = Last Buffer Descriptor in the chain 0 = More Buffer Descriptors in the chain After the last BD, the CEBDADDR goes to the base address in CEBDPADDR. bit 18 LIFM: Last In Frame In case of Receive Packets (from H/W-> Host), this field is filled by the Hardware to indicate whether the packet goes across multiple buffer descriptors. In case of transmit packets (from Host -> H/W), this field indicates whether this BD is the last in the frame. bit 17 PKT_INT_EN: Packet Interrupt Enable Generate an interrupt after processing the current buffer descriptor, if it is the end of the packet. bit 16 CBD_INT_EN: CBD Interrupt Enable Generate an interrupt after processing the current buffer descriptor. bit 15-0 BD_BUFLEN: Buffer Descriptor Length This field contains the length of the buffer and is updated with the actual length filled by the receiver. FIGURE 26-3: Bit Range FORMAT OF BD_SADDR Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31-24 BD_SAADDR 23-16 BD_SAADDR 15-8 BD_SAADDR 7-0 BD_SAADDR bit 31-0 Bit 25/17/9/1 Bit 24/16/8/0 BD_SAADDR: Security Association IP Session Address The sessions’ SA pointer has the keys and IV values.  2015-2021 Microchip Technology Inc. DS60001320H-page 427 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 26-4: Bit Range FORMAT OF BD_SRCADDR Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31-24 BD_SCRADDR 23-16 BD_SCRADDR 15-8 BD_SCRADDR 7-0 BD_SCRADDR bit 31-0 BD_SCRADDR: Buffer Source Address The source address of the buffer that needs to be passed through the PE-CRDMA for encryption or authentication. This address must be on a 32-bit boundary. FIGURE 26-5: Bit Range FORMAT OF BD_DSTADDR Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31-24 BD_DSTADDR 23-16 BD_DSTADDR 15-8 BD_DSTADDR 7-0 BD_DSTADDR bit 31-0 BD_DSTADDR: Buffer Destination Address The destination address of the buffer that needs to be passed through the PE-CRDMA for encryption or authentication. This address must be on a 32-bit boundary. FIGURE 26-6: Bit Range FORMAT OF BD_NXTADDR Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31-24 BD_NXTADDR 23-16 BD_NXTADDR 15-8 BD_NXTADDR 7-0 BD_NXTADDR bit 31-0 Bit 25/17/9/1 Bit 24/16/8/0 BD_NXTADDR: Next BD Pointer Address Has Next Buffer Descriptor The next buffer can be a next segment of the previous buffer or a new packet. DS60001320H-page 428  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 26-7: Bit Range FORMAT OF BD_UPDPTR Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31-24 BD_UPDADDR 23-16 BD_UPDADDR 15-8 BD_UPDADDR 7-0 BD_UPDADDR bit 31-0 BD_UPDADDR: UPD Address Location The update address has the location where the CRDMA results are posted. The updated results are the ICV values, key output values as needed. FIGURE 26-8: Bit Range FORMAT OF BD_MSG_LEN Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 31-24 MSG_LENGTH 23-16 MSG_LENGTH 15-8 MSG_LENGTH 7-0 MSG_LENGTH bit 31-0 Bit 24/16/8/0 MSG_LENGTH: Total Message Length Total message length for the hash and HMAC algorithms in bytes. Total number of crypto bytes in case of GCM algorithm (LEN-C). FIGURE 26-9: Bit Range Bit 25/17/9/1 FORMAT OF BD_ENC_OFF Bit 31/23/15/7 Bit 30/22/14/6 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 31-24 ENCR_OFFSET 23-16 ENCR_OFFSET 15-8 ENCR_OFFSET 7-0 ENCR_OFFSET bit 31-0 ENCR_OFFSET: Encryption Offset Encryption offset for the multi-task test cases (both encryption and authentication). The number of AAD bytes in the case of GCM algorithm (LEN-A).  2015-2021 Microchip Technology Inc. DS60001320H-page 429 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 26.3 Security Association Structure Table 26-4 shows the Security Association Structure. The Crypto Engine uses the Security Association to determine the settings for processing a Buffer Descriptor Processor. The Security Association contains: • Which algorithm to use • Whether to use engines in parallel (for both authentication and encryption/decryption) • The size of the key • Authentication key • Encryption/decryption key • Authentication Initialization Vector (IV) • Encryption IV TABLE 26-4: CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE Bit 31/23/15/7 Name SA_CTRL Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 31:24 — — VERIFY — NO_RX OR_EN ICVONLY IRFLAG 23:16 LNC LOADIV FB FLAGS — — — ALGO ENCTYPE KEYSIZE 15:8 7:0 ALGO KEYSIZE MULTITASK CRYPTOALGO SA_AUTHKEY1 31:24 AUTHKEY 23:16 AUTHKEY 15:8 AUTHKEY 7:0 AUTHKEY SA_AUTHKEY2 31:24 AUTHKEY 23:16 AUTHKEY 15:8 AUTHKEY 7:0 AUTHKEY SA_AUTHKEY3 31:24 AUTHKEY 23:16 AUTHKEY 15:8 AUTHKEY 7:0 AUTHKEY SA_AUTHKEY4 31:24 AUTHKEY 23:16 AUTHKEY 15:8 AUTHKEY 7:0 AUTHKEY SA_AUTHKEY5 31:24 AUTHKEY 23:16 AUTHKEY 15:8 AUTHKEY 7:0 AUTHKEY SA_AUTHKEY6 31:24 AUTHKEY 23:16 AUTHKEY 15:8 AUTHKEY 7:0 AUTHKEY SA_AUTHKEY7 31:24 AUTHKEY 23:16 AUTHKEY 15:8 AUTHKEY 7:0 AUTHKEY SA_AUTHKEY8 31:24 AUTHKEY 23:16 AUTHKEY 15:8 AUTHKEY SA_ENCKEY1 SA_ENCKEY2 Bit 24/16/8/0 7:0 AUTHKEY 31:24 ENCKEY 23:16 ENCKEY 15:8 ENCKEY 7:0 ENCKEY 31:24 ENCKEY 23:16 ENCKEY DS60001320H-page 430  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 26-4: CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE (CONTINUED) Bit 31/23/15/7 Name Bit 30/22/14/6 15:8 SA_ENCKEY3 SA_ENCKEY4 SA_ENCKEY5 SA_ENCKEY6 SA_ENCKEY7 SA_ENCKEY8 SA_AUTHIV1 SA_AUTHIV2 SA_AUTHIV3 SA_AUTHIV4 SA_AUTHIV5 SA_AUTHIV6 SA_AUTHIV7 SA_AUTHIV8 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 25/17/9/1 Bit 24/16/8/0 ENCKEY 7:0 ENCKEY 31:24 ENCKEY 23:16 ENCKEY 15:8 ENCKEY 7:0 ENCKEY 31:24 ENCKEY 23:16 ENCKEY 15:8 ENCKEY 7:0 ENCKEY 31:24 ENCKEY 23:16 ENCKEY 15:8 ENCKEY 7:0 ENCKEY 31:24 ENCKEY 23:16 ENCKEY 15:8 ENCKEY 7:0 ENCKEY 31:24 ENCKEY 23:16 ENCKEY 15:8 ENCKEY 7:0 ENCKEY 31:24 ENCKEY 23:16 ENCKEY 15:8 ENCKEY 7:0 ENCKEY 31:24 AUTHIV 23:16 AUTHIV 15:8 AUTHIV 7:0 AUTHIV 31:24 AUTHIV 23:16 AUTHIV 15:8 AUTHIV 7:0 AUTHIV 31:24 AUTHIV 23:16 AUTHIV 15:8 AUTHIV 7:0 AUTHIV 31:24 AUTHIV 23:16 AUTHIV 15:8 AUTHIV 7:0 AUTHIV 31:24 AUTHIV 23:16 AUTHIV 15:8 AUTHIV 7:0 AUTHIV 31:24 AUTHIV 23:16 AUTHIV 15:8 AUTHIV 7:0 AUTHIV 31:24 AUTHIV 23:16 AUTHIV 15:8 AUTHIV 7:0 AUTHIV 31:24 AUTHIV 23:16 AUTHIV 15:8 AUTHIV 7:0 AUTHIV  2015-2021 Microchip Technology Inc. Bit 26/18/10/2 DS60001320H-page 431 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family TABLE 26-4: CRYPTO ENGINE SECURITY ASSOCIATION STRUCTURE (CONTINUED) Bit 31/23/15/7 Name SA_ENCIV1 SA_ENCIV2 SA_ENCIV3 SA_ENCIV4 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 31:24 ENCIV 23:16 ENCIV 15:8 ENCIV 7:0 ENCIV 31:24 ENCIV 23:16 ENCIV 15:8 ENCIV 7:0 ENCIV 31:24 ENCIV 23:16 ENCIV 15:8 ENCIV 7:0 ENCIV 31:24 ENCIV 23:16 ENCIV 15:8 ENCIV 7:0 ENCIV DS60001320H-page 432 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Figure 26-10 shows the Security Association control word structure. The Crypto Engine fetches different structures for different flows and ensures that hardware fetches minimum words from SA required for processing. The structure is ready for hardware optimal data fetches. FIGURE 26-10: FORMAT OF SA_CTRL Bit Range Bit 31/23/15/7 Bit 30/22/14/6 31-24 — — VERIFY — NO_RX 23-16 LNC LOADIV FB FLAGS — 15-8 7-0 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 OR_EN ICVONLY IRFLAG — — ALGO ENC KEY SIZE ALGO KEY SIZE MULTITASK CRYPTOALGO bit 31-30 Reserved: Do not use bit 29 VERIFY: NIST Procedure Verification Setting 1 = NIST procedures are to be used 0 = Do not use NIST procedures bit 28 Reserved: Do not use bit 27 NO_RX: Receive DMA Control Setting 1 = Only calculate ICV for authentication calculations 0 = Normal processing bit 26 OR_EN: OR Register Bits Enable Setting 1 = OR the register bits with the internal value of the CSR register 0 = Normal processing bit 25 ICVONLY: Incomplete Check Value Only Flag This affects the SHA-1 algorithm only. It has no effect on the AES algorithm. 1 = Only three words of the HMAC result are available 0 = All results from the HMAC result are available bit 24 IRFLAG: Immediate Result of Hash Setting This bit is set when the immediate result for hashing is requested. 1 = Save the immediate result for hashing 0 = Do not save the immediate result bit 23 LNC: Load New Keys Setting 1 = Load a new set of keys for encryption and authentication 0 = Do not load new keys bit 22 LOADIV: Load IV Setting 1 = Load the IV from this Security Association 0 = Use the next IV bit 21 FB: First Block Setting This bit indicates that this is the first block of data to feed the IV value. 1 = Indicates this is the first block of data 0 = Indicates this is not the first block of data bit 20 FLAGS: Incoming/Outgoing Flow Setting 1 = Security Association is associated with an outgoing flow 0 = Security Association is associated with an incoming flow bit 19-17 Reserved: Do not use  2015-2021 Microchip Technology Inc. DS60001320H-page 433 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family Figure 26-10: Format of SA_CTRL (Continued) bit 16-10 ALGO: Type of Algorithm to Use 1xxxxxx = HMAC 1 x1xxxxx = SHA-256 xx1xxxx = SHA1 xxx1xxx = MD5 xxxx1xx = AES xxxxx1x = TDES xxxxxx1 = DES bit 9 ENC: Type of Encryption Setting 1 = Encryption 0 = Decryption bit 8-7 KEYSIZE: Size of Keys in SA_AUTHKEYx or SA_ENCKEYx 11 = Reserved; do not use 10 = 256 bits 01 = 192 bits 00 = 128 bits(1) bit 6-4 MULTITASK: How to Combine Parallel Operations in the Crypto Engine 111 = Parallel pass (decrypt and authenticate incoming data in parallel) 101 = Pipe pass (encrypt the incoming data, and then perform authentication on the encrypted data) 011 = Reserved 010 = Reserved 001 = Reserved 000 = Encryption or authentication or decryption (no pass) bit 3-0 CRYPTOALGO: Mode of operation for the Crypto Algorithm 1111 = Reserved 1110 = AES_GCM (for AES processing) 1101 = RCTR (for AES processing) 1100 = RCBC_MAC (for AES processing) 1011 = ROFB (for AES processing) 1010 = RCFB (for AES processing) 1001 = RCBC (for AES processing) 1000 = RECB (for AES processing) 0111 = TOFB (for Triple-DES processing) 0110 = TCFB (for Triple-DES processing) 0101 = TCBC (for Triple-DES processing) 0100 = TECB (for Triple-DES processing) 0011 = OFB (for DES processing) 0010 = CFB (for DES processing) 0001 = CBC (for DES processing) 0000 = ECB (for DES processing) Note 1: This setting does not alter the size of SA_AUTHKEYx or SA_ENCKEYx in the Security Association, only the number of bits of SA_AUTHKEYx and SA_ENCKEYx that are used. DS60001320H-page 434  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 27.0 Note: RANDOM NUMBER GENERATOR (RNG) This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 49. “Crypto Engine (CE) and Random Number Generator (RNG)” (DS60001246) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). TABLE 27-1: RANDOM NUMBER GENERATOR BLOCK DIAGRAM System Bus SFR PRNG PBCLK5 The Random Number Generator (RNG) core implements a thermal noise-based, True Random Number Generator (TRNG) and a cryptographically secure Pseudo-Random Number Generator (PRNG). The TRNG uses multiple ring oscillators and the inherent thermal noise of integrated circuits to generate true random numbers that can initialize the PRNG. TRNG BIAS Corrector The PRNG is a flexible LSFR, which is capable of manifesting a maximal length LFSR of up to 64-bits. The following are some of the key features of the Random Number Generator: • TRNG: - Up to 25 Mbps of random bits - Multi-Ring Oscillator based design - Built-in Bias Corrector • PRNG: - LSFR-based - Up to 64-bit polynomial length - Programmable polynomial - TRNG can be seed value  2015-2021 Microchip Technology Inc. Edge Comparator Ring Oscillator Ring Oscillator DS60001320H-page 435 RNG Control Registers TABLE 27-2: 6008 600C RNGCON RNGPOLY1 RNGPOLY2 6010 RNGNUMGEN1 6014 RNGNUMGEN2 6018 601C 6020 Legend: RNGSEED1 RNGSEED2 RNGCNT 31/15 30/14 29/13 28/12 27/11 26/10 25/9 31:16 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 ID 15:0 xxxx VERSION REVISION 31:16 — — — — — — 15:0 — — — LOAD TRNGMODE CONT — — — — — PRNGEN TRNGEN 31:16 — — xxxx — — — PLEN 31:16 FFFF 0000 FFFF POLY 15:0 31:16 0000 FFFF RNG 15:0 31:16 FFFF FFFF RNG 15:0 31:16 FFFF 0000 SEED 15:0 31:16 0000 0000 SEED 15:0 31:16 — — — — — — — — — 15:0 — — — — — — — — — x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. 0000 0064 POLY 15:0 All Resets Register Name RNGVER Bit Range Virtual Address (BF8E_#) Bits 6000 6004 RANDOM NUMBER GENERATOR (RNG) REGISTER MAP 0000 — — — — RCNT — — — 0000 0000  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family DS60001320H-page 436 27.1 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 27-1: Bit Range 31:24 23:16 15:8 7:0 RNGVER: RANDOM NUMBER GENERATOR VERSION REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 ID R-0 R-0 R-0 R-0 ID R-0 R-0 R-0 R-0 VERSION R-0 R-0 R-0 R-0 R-0 REVISION Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 ID: Block Identification bits bit 15-8 VERSION: Block Version bits bit 7-0 REVISION: Block Revision bits  2015-2021 Microchip Technology Inc. DS60001320H-page 437 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 27-2: Bit Range 31:24 23:16 15:8 7:0 RNGCON: RANDOM NUMBER GENERATOR CONTROL REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — LOAD TRNGMODE CONT PRNGEN TRNGEN R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 PLEN Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-13 Unimplemented: Read as ‘0’ bit 12 LOAD: Device Select bit This bit is self-clearing and is used to load the seed from the TRNG (i.e., the random value) as a seed to the PRNG. bit 11 TRNGMODE: TRNG Mode Selection bit 1 = Use ring oscillators with bias corrector 0 = Use ring oscillators with XOR tree bit 10 CONT: PRNG Number Shift Enable bit 1 = The PRNG random number is shifted every cycle 0 = The PRNG random number is shifted when the previous value is removed bit 9 PRNGEN: PRNG Operation Enable bit 1 = PRNG operation is enabled 0 = PRNG operation is not enabled bit 8 TRNGEN: TRNG Operation Enable bit 1 = TRNG operation is enabled 0 = TRNG operation is not enabled bit 7-0 PLEN: PRNG Polynomial Length bits These bits contain the length of the polynomial used for the PRNG. Note: DS60001320H-page 438 Enabling this bit will generate numbers with a more even distribution of randomness.  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 27-3: Bit Range 31:24 23:16 15:8 7:0 RNGPOLYx: RANDOM NUMBER GENERATOR POLYNOMIAL REGISTER ‘x’  (‘x’ = 1 OR 2) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POLY R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 POLY R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POLY R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 POLY Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 POLY: PRNG LFSR Polynomial MSb/LSb bits (RNGPOLY1 = LSb, RNGPOLY2 = MSb) REGISTER 27-4: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown RNGNUMGENx: RANDOM NUMBER GENERATOR REGISTER ‘x’ (‘x’ = 1 OR 2) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RNG R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RNG R/W-1 RNG R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RNG Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 Note: x = Bit is unknown RNG: Current PRNG MSb/LSb Value bits (RNGNUMGEN1 = LSb, RNGNUMGEN2 = MSb) The RNGNUMGEN2 should be read before the RNGNUMGEN1.  2015-2021 Microchip Technology Inc. DS60001320H-page 439 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family REGISTER 27-5: Bit Range 31:24 23:16 15:8 7:0 RNGSEEDx: TRUE RANDOM NUMBER GENERATOR SEED REGISTER ‘x’  (‘x’ = 1 OR 2) Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 R-0 R-0 R-0 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 SEED R-0 R-0 R-0 R-0 R-0 SEED R-0 R-0 R-0 R-0 R-0 SEED R-0 R-0 R-0 R-0 R-0 SEED Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-0 Note: SEED: TRNG MSb/LSb Value bits (RNGSEED1 = LSb, RNGSEED2 = MSb) The RNGSEED2 should be read before the RNGSEED1. REGISTER 27-6: Bit Range 31:24 23:16 15:8 7:0 x = Bit is unknown RNGCNT: TRUE RANDOM NUMBER GENERATOR COUNT REGISTER Bit 31/23/15/7 Bit 30/22/14/6 Bit 29/21/13/5 Bit 28/20/12/4 Bit 27/19/11/3 Bit 26/18/10/2 Bit 25/17/9/1 Bit 24/16/8/0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — RCNT Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 31-7 Unimplemented: Read as ‘0’ bit 6-0 RCNT: Number of Valid TRNG MSB 32 bits DS60001320H-page 440 x = Bit is unknown  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family 28.0 Note: 12-BIT HIGH-SPEED SUCCESSIVE APPROXIMATION REGISTER (SAR) ANALOG-TODIGITAL CONVERTER (ADC) This data sheet summarizes the features of the PIC32MZ EF family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 22. “12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)” (DS60001344) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). The 12-bit High-Speed Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) includes the following key features: • 12-bit resolution • Six ADC modules with dedicated Sample and Hold (S&H) circuits • Two dedicated ADC modules can be combined in Turbo mode to provide double conversion rate (clock sources for combined ADC modules must be synchronous) • Single-ended and/or differential inputs • Can operate during Sleep mode • Supports touch sense applications • Six digital comparators • Six digital filters supporting two modes: - Oversampling mode - Averaging mode • Early interrupt generation resulting in faster processing of converted data • Designed for motor control, power conversion, and general purpose applications A simplified block diagram of the ADC module is illustrated in Figure 28-1. The 12-bit HS SAR ADC has up to five dedicated ADC modules (ADC0-ADC4) and one shared ADC module (ADC7). The dedicated ADC modules use a single input (or its alternate) and are intended for high-speed and precise sampling of time-sensitive or transient inputs. The the shared ADC module incorporates a multiplexer on the input to facilitate a larger group of inputs, with slower sampling, and provides flexible automated scanning option through the input scan logic. For each ADC module, the analog inputs are connected to the S&H capacitor. The clock, sampling time, and output data resolution for each ADC module can be set independently. The ADC module performs the conversion of the input analog signal  2015-2021 Microchip Technology Inc. based on the configurations set in the registers. When conversion is complete, the final result is stored in the result buffer for the specific analog input and is passed to the digital filter and digital comparator if configured to use data from this particular sample. Input to ADCx mapping is illustrated in Figure 28-2. 28.1 Activation Sequence Step 1: Initialize the ADC calibration values by copying it from the factory programmed DEVADCx Flash locations starting at 0xBFC45000 into the ADCxCFG registers starting at 0xBF887D00. Then, configure the AICPMPEN bit (ADCCON1 and the IOANCPEN bit (CFGCON) = 1 if and only if VDD is less than 2.5V. The default is ‘0’, which assumes VDD is greater than or equal to 2.5V. Step 2: Write all the essential ADC configuration SFRs including the ADC control clock and all ADC core clocks setup as given below: • ADCCON1, keeping the ON bit = 0 • ADCCON2, especially paying attention to ADCDIV and SAMC • ADCANCON, keeping all analog enables ANENx bit = 0, WKUPCLKCNT bits = 0xA • ADCCON3, keeping all DIGENx = 0, especially paying attention to ADCSEL, CONCLKDIV , and VREFSEL • ADCxTIME, ADCDIVx, and SAMCx • ADCTRGMODE, ADCIMCONx, ADCTRGSNS, ADCCSSx, ADCGIRQENx, ADCTRGx, ADCBASE • Comparators, filters, and so on Step 3: Set the ON bit to ‘1’, which enables the ADC control clock. Step 4: Wait for the interrupt or poll the status bit BGVRRDY = 1, which signals that the device analog environment (band gap and VREF) is ready. Step 5: Set the ANENx bit to ‘1’ for each of the ADC SAR cores to be used. Step 6: Wait for the interrupt or polls the warm-up ready bits WKRDYx = 1, which signals that the respective ADC SAR cores are ready to operate. Step 7: Set the DIGENx bit to ‘1’, which enables the digital circuitry to immediately begin processing incoming triggers to perform data conversions. The throughput rate (see Table 37-39 in 37.0 “Electrical Characteristics”) is calculated, as shown in Equation 28-1. DS60001320H-page 441 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family EQUATION 28-1: ADC THROUGHPUT RATE T AD FTP = ------------------------------------------- T SAMP + T CONV  Where, TAD = the frequency of the individual ADC module TABLE 28-1: Note 1: Prior to enabling the ADC module, the user application must copy the ADC calibration data (DEVADC0-DEVADC4, DEVADC7; see Register 34-13) from the Configuration memory into the ADC Configuration registers (ADC0CFGADC4CFG, ADC7CFG). 2: Configure the AICPMPEN (ADCCON1) and IOANCPEN (CFGCON) bits to ‘0’ if VDD >= 2.5V. Set the AICPMPEN and IOANCPEN bits to ‘1’ if VDD < 2.5V. PIC32MZXXEFXX INTERLEAVED ADC THROUGHPUT RATES #No. of Interleaved ADC Possible ADC TAD (min) = 20 ns (50 Mhz max.) 12-bit (max.) msps 10-bit (max.) msps 8-bit (max.) msps 6-bit (max.) msps 1 3.125 msps 3.571 msps 4.167 msps 5.0 msps 2 6.250 msps 7.143 msps 8.333 msps 10.00 msps 3 8.330 msps 10.00 msps 12.50 msps 12.50 msps 4 12.50 msps 12.50 msps 16.667 msps 16.667 msps Note: Interleaved ADCs in this context means connecting the same analog source signal to multiple dedicated Class_1 ADCs (i.e., ADC0-ADC4), and using independent staggered trigger sources accordingly for each interleaved ADC. DS60001320H-page 442  2015-2021 Microchip Technology Inc. PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 28-1: ADC BLOCK DIAGRAM $1 $1 1& 1& 00 01 10 11 $9'' 95() 95() $'&6(/! 00 10 11 &21&/.',9! 95()6(/! 1 0 95()+ ',))! $'&,0&21! 95()/ 7$'7$' $'&',9! $'&[7,0(! 74 $'& 7$' $1 $1 1& 1& 01 7&/. 6+$/7! $'&75*02'(! $1 95()/ $966 $'&',9! $'&&21! 00 01 10 11 6+$/7! $'&75*02'(! $1 95()/ 1 0 $'& ',))! $'&,0&21! $1 $1 ,95()$1 $1 ,97(03$1 $'& $1 95()/ 1 0 &9' &DSDFLWRU ',))[! [ WR $'&,0&21\]! \ WR ] WR2GGQXPEHUV $'&'$7$ « ),)2 'LJLWDO)LOWHU 'LJLWDO&RPSDUDWRU 'DWD ,QWHUUXSW(YHQW 7ULJJHUV 7XUER&KDQQHO 6FDQ&RQWURO/RJLF 7ULJJHU &DSDFLWLYH9ROWDJH 'LYLGHU&9' 6WDWXVDQG&RQWURO 5HJLVWHUV  2015-2021 Microchip Technology Inc. ^z^dDh^ $'&'$7$ ,QWHUUXSW(YHQW ,QWHUUXSW DS60001320H-page 443 PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Family FIGURE 28-2: S&H BLOCK DIAGRAM ADC0 AN0 00 AN3 00 AN45 01 AN48 01 N/C 10 N/C 10 N/C 11 N/C 11 ADC3 SAR SAR SH3ALT (ADCTRGMODE74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 e E E1 N b NOTE 1 1 23 NOTE 2 α c A φ L β A1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV A2 L1 0,//,0(7(56 0,1 1 120 0$;  /HDG3LWFK H 2YHUDOO+HLJKW $ ± %6& ± 0ROGHG3DFNDJH7KLFNQHVV $    6WDQGRII $  ±  )RRW/HQJWK /    )RRWSULQW /  5() )RRW$QJOH  2YHUDOO:LGWK ( ƒ %6& ƒ 2YHUDOO/HQJWK ' %6& 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' %6& ƒ /HDG7KLFNQHVV F  ±  /HDG:LGWK E    0ROG'UDIW$QJOH7RS  ƒ ƒ ƒ 0ROG'UDIW$QJOH%RWWRP  ƒ ƒ ƒ 1RWHV  3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD  &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\  'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH  'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(