SST25WF040B
4 Mbit 1.8V SPI Serial Flash
Features
Product Description
• Single Voltage Read and Write Operations
- 1.65-1.95V
• Serial Interface Architecture
- SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
- 40MHz
• Dual Input/Output Support
- Fast-Read Dual-Output Instruction (3BH)
- Fast-Read Dual I/O Instruction (BBH)
• Superior Reliability
- Endurance: 100,000 Cycles
- Greater than 20 years Data Retention
• Ultra-Low Power Consumption:
- Active Read Current: 4 mA (typical)
- Standby Current: 7 µA (typical)
- Power-down Mode Standby Current: 2 µA (typical)
• Flexible Erase Capability
- Uniform 4 KByte sectors
- Uniform 64 KByte overlay blocks
• Page Program Mode
- 256 Bytes/Page
• Fast Erase and Page-Program:
- Chip-Erase Time: 400 ms (typical)
- Sector-Erase Time: 40 ms (typical)
- Block-Erase Time: 80 ms (typical)
- Page-Program Time: 0.8 ms/ 256 bytes (typical)
• End-of-Write Detection
- Software polling the BUSY bit in Status Register
• Hold Pin (HOLD#)
- Suspend a serial sequence without deselecting the
device
• Write Protection (WP#)
- Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
- Write protection through Block-Protection bits in
status register
• Temperature Range
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
• Packages Available
- 8-lead SOIC (150 mils)
- 8-contact USON (2mm x 3mm)
• All devices are RoHS compliant
SST25WF040B is a member of the Serial Flash 25
Series family and feature a four-wire, SPI-compatible
interface that allows for a low pin-count package which
occupies less board space and ultimately lowers total
system costs. SPI serial flash memory is manufactured
with proprietary, high-performance CMOS SuperFlash
technology. The split-gate cell design and thick-oxide
tunneling injector attain better reliability and manufacturability compared with alternate approaches.
2013-2018 Microchip Technology Inc.
This Serial Flash significantly improve performance
and reliability, while lowering power consumption. The
device writes (Program or Erase) with a single power
supply of 1.65-1.95V. The total energy consumed is a
function of the applied voltage, current, and time of
application. Since for any given voltage range, the
SuperFlash technology uses less current to program
and has a shorter erase time, the total energy consumed during any Erase or Program operation is less
than alternative flash memory technologies.
SST25WF040B is offered in 8-lead SOIC and 8-contact
USON packages. See Figure 2-1 for the pin assignments.
DS20005193E-page 1
SST25WF040B
TO OUR VALUED CUSTOMERS
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http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The
last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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2013-2018 Microchip Technology Inc.
DS20005193E-page 2
SST25WF040B
1.0
FUNCTIONAL BLOCK DIAGRAM
FIGURE 1-1:
FUNCTIONAL BLOCK DIAGRAM
X - Decoder
Address
Buffers
and
Latches
SuperFlash
Memory
Y - Decoder
Control Logic
I/O Buffers
and
Data Latches
Serial Interface
CE#
SCK
SI/ SO/ WP#
SIO0 SIO1
HOLD#
20005193 F01.0
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DS20005193E-page 3
SST25WF040B
2.0
PIN DESCRIPTION
FIGURE 2-1:
PIN ASSIGNMENTS
CE#
1
8
VDD
SO/SIO1
2
7
HOLD#
WP#
3
6
SCK
VSS
4
5
SI/SIO0
8
VDD
7
HOLD#
3
6
SCK
4
5
SI/SIO0
CE#
1
SO/SIO1
2
WP#
VSS
Top View
20005193 08-uson Q3A P1.0
20005193 08-soic-P0.0
8-Lead SOIC
TABLE 2-1:
8-Contact USON
PIN DESCRIPTION
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the input/output timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock
input, while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
SIO[0:1]
Serial Data Input/
To transfer commands, addresses, or data serially into the device, or data out of
Output for Dual I/O the device. Inputs are latched on the rising edge of the serial clock. Data is
Mode
shifted out on the falling edge of the serial clock. These pins are used in Dual
I/O mode
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low
for the duration of any command sequence. The device is deselected and
placed in Standby mode when CE# is high.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD#
Hold
To temporarily stop serial communication with SPI Flash memory while device
is selected.
VDD
Power Supply
To provide power supply voltage: 1.65-1.95V for SST25WF040B
VSS
Ground
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DS20005193E-page 4
SST25WF040B
3.0
MEMORY ORGANIZATION
The SST25WF040B SuperFlash memory arrays are
organized in 128 uniform 4 KByte sectors, with 8
64 KByte overlay erasable blocks.
MEMORY MAP
Top of Memory Block
127
07FFFFH
07F000H
1
...
...
01FFFFH
01F000H
16
...
15
0
070FFFH
070000H
31
...
...
112
1
0
...
7
...
Number of Sectors
01FFFFH
010000H
00FFFFH
00F000H
...
Number of 64 KByte
Blocks
...
FIGURE 3-1:
001FFFH
001000H
000FFFH
000000H
Bottom of Memory Block
20005193 F51.0.eps
4.0
DEVICE OPERATION
The SST25WF040B supports both Mode 0 (0,0) and
Mode 3 (1,1) of SPI bus operations. The difference
between the two modes, as shown in Figure 4-1, is the
state of the SCK signal when the bus master is in
Stand-by mode and no data is being transferred. The
SCK signal is low for Mode 0 and SCK signal is high for
Mode 3. For both modes, the Serial Data In (SI) is sampled at the rising edge of the SCK clock signal and the
Serial Data Output (SO) is driven after the falling edge
of the SCK clock signal.
SST25WF040B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI
bus consist of four control lines; Chip Enable (CE#) is
used to select the device, and data is accessed through
the Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK).
FIGURE 4-1:
SPI PROTOCOL
CE#
SCK
SI
MODE 3
MODE 3
MODE 0
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
SO
HIGH IMPEDANCE
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
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25000193 F03.0
DS20005193E-page 5
SST25WF040B
4.0.1
HOLD
In the hold mode, serial sequences underway with the
SPI Flash memory are paused without resetting the
clocking sequence. To activate the HOLD# mode, CE#
must be in active low state. The HOLD# mode begins
when the SCK active low state coincides with the falling
edge of the HOLD# signal. The Hold mode ends when
the rising edge of the HOLD# signal coincides with the
SCK active low state. HOLD# must not rise or fall when
SCK logic level is high. See Figure 4-2 for Hold Condition waveform.
FIGURE 4-2:
Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH.
If CE# is driven active high during a Hold condition, the
device returns to standby mode. The device can then
be re-initiated with the command sequences listed in
Table 5-1. As long as HOLD# signal is low, the memory
remains in the Hold condition. To resume communication with the device, HOLD# must be driven active high,
and CE# must be driven active low. See Figure 4-2 for
Hold timing.
HOLD CONDITION WAVEFORM
SCK
HOLD#
Active
Hold
Active
20005193 F05.0
4.1
Write Protection
SST25WF040B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lockdown function of the status register. The Block-Protection bits (BP0, BP1, BP2, TB, and BPL) in the status
4.1.1
register provide Write protection to the memory array
and the status register. See Table 4-3 for the Block-Protection description.
WRITE PROTECT PIN (WP#)
The Write Protect (WP#) pin enables the lock-down
function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-
TABLE 4-1:
Status-Register (WRSR) instruction is determined by
the value of the BPL bit (see Table 4-1). When WP# is
high, the lock-down function of the BPL bit is disabled.
CONDITIONS TO EXECUTE WRITE-STATUS-REGISTER (WRSR) INSTRUCTION
WP#
BPL
Execute WRSR Instruction
L
1
Not Allowed
L
0
Allowed
H
X
Allowed
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DS20005193E-page 6
SST25WF040B
4.2
Status Register
The software status register provides status on
whether the flash memory array is available for any
Read or Write operation, whether the device is Write
enabled, and the state of the Memory Write protection.
TABLE 4-2:
During an internal Erase or Program operation, the status register may be read only to determine the completion of an operation in progress. Table 4-2 describes
the function of each bit in the software status register.
SOFTWARE STATUS REGISTER
Default at
Power-up
Read/Write
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
R
2
BP01
Indicate current level of block write protection (See Table 4-3)
0 or 1
R/W
3
BP11
Indicate current level of block write protection (See Table 4-3)
0 or 1
R/W
4
BP21
Indicate current level of block write protection (See Table 4-3)
0 or 1
R/W
5
TB1
1 = 1/8, 1/4, or 1/2 Bottom Memory Blocks are protected (See Table 4-3)
0 = 1/8, 1/4, or 1/2 Top Memory Blocks are protected
0 or 1
R/W
6
RES
0
N/A
7
1
0 or 1
R/W
Bit
Name
Function
0
BUSY
1
BPL
Reserved for future use
1 = BP0, BP1, BP2, TB, and BPL are read-only bits
0 = BP0, BP1, BP2, TB, and BPL are read/writable
1. BP0, BP1, BP2, TB, and BPL bits are non-volatile memory bits.
4.2.1
BUSY (BIT 0)
The Busy bit determines whether there is an internal
Erase or Program operation in progress. A ‘1’ for the
Busy bit indicates the device is busy with an operation
in progress. A ‘0’ indicates the device is ready for the
next valid operation.
4.2.2
BP2, and TB bits as long as WP# is high or the BlockProtect-Lock (BPL) bit is ‘0’. Chip-Erase can only be
executed if Block-Protection bits are all ‘0’. BP0, BP1,
and BP2 select the protected area and TB allocates the
protected area to the higher-order address area (Top
Blocks) or lower-order address area (Bottom Blocks).
WRITE ENABLE LATCH (WEL–BIT 1)
The Write-Enable-Latch bit indicates the status of the
internal Write-Enable-Latch memory. If the WEL bit is
set to ‘1’, it indicates the device is Write enabled. If the
bit is set to ‘0’ (reset), it indicates the device is not Write
enabled and does not accept any Write (Program/
Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
•
•
•
•
•
•
•
Power-up
Write-Disable (WRDI) instruction completion
Page-Program instruction completion
Sector-Erase instruction completion
64 KByte Block-Erase instruction completion
Chip-Erase instruction completion
Write-Status-Register instruction completion
4.2.3
BLOCK-PROTECTION (BP0, BP1,
BP2, AND TB–BITS 2, 3, 4, AND 5)
The Block-Protection (BP0, BP1, BP2, and TB) bits
define the size of the memory area to be software protected against any memory Write (Program or Erase)
operation, see Table 4-3. The Write-Status-Register
(WRSR) instruction is used to program the BP0, BP1,
2013-2018 Microchip Technology Inc.
DS20005193E-page 7
SST25WF040B
4.2.4
BLOCK PROTECTION LOCK-DOWN
(BPL–BIT 7)
BP1, BP2, TB, and BPL bits. When the WP# pin is
driven high (VIH), the BPL bit has no effect and its value
is ‘Don’t Care’.
When the WP# pin is driven low (VIL), it enables the
Block-Protection-Lock-Down (BPL) bit. When BPL is
set to ‘1’, it prevents any further alteration of the BP0,
TABLE 4-3:
SOFTWARE STATUS REGISTER BLOCK PROTECTION
Status Register Bit
Protection Level
TB
BP2
BP1
BP0
0 (Full Memory Array unprotected)
X
0
0
0
None
T1 (1/8 Top Memory Block protected)
0
0
0
1
070000H-07FFFFH
T2 (1/4 Top Memory Block protected)
0
0
1
0
060000H-07FFFFH
T3 (1/2 Top Memory Block protected)
0
0
1
1
040000H-07FFFFH
B1 (1/8 Bottom Memory Block protected)
1
0
0
1
000000H-00FFFFH
B2 (1/4 Bottom Memory Block protected)
1
0
1
0
000000H-01FFFFH
B3 (1/2 Bottom Memory Block protected)
1
0
1
1
000000H-03FFFFH
4 (Full Memory Block protected)
X
1
X
X
000000H-0FFFFFH
2013-2018 Microchip Technology Inc.
Protected Memory Address
DS20005193E-page 8
SST25WF040B
5.0
INSTRUCTIONS
Instructions are used to read, write (Erase and Program), and configure the SST25WF040B devices. The
instruction bus cycles are 8 bits each for commands
(Op Code), data, and addresses. The Write-Enable
(WREN) instruction must be executed prior to SectorErase, Block-Erase, Page-Program, Write-Status-Register, or Chip-Erase instructions. The complete instructions are provided in Table 5-1. All instructions are
synchronized off a high-to-low transition of CE#. Inputs
will be accepted on the rising edge of SCK starting with
TABLE 5-1:
the most significant bit. CE# must be driven low before
an instruction is entered and must be driven high after
the last bit of the instruction has been shifted in (except
for Read, Read-ID, and Read-Status-Register instructions). Any low-to-high transition on CE#, before receiving the last bit of an instruction bus cycle, will terminate
the instruction in progress and return the device to
standby mode. Instruction commands (Op Code),
addresses, and data are all input from the most significant bit (MSB) first.
DEVICE OPERATION INSTRUCTIONS
Address Dummy
Data
Maximum
Cycle(s)2 Cycle(s) Cycle(s) Frequency
Description
Op Code Cycle1
Read
Read Memory
0000 0011b (03H)
3
0
1 to
High-Speed Read
Read Memory at Higher
Speed
0000 1011b (0BH)
3
1
1 to
Fast-Read DualOutput
Read Memory with Dual Output
0011 1011b (3BH)
3
13
1 to 3
1011 1011b (BBH)
33
13
1 to 3
4 KByte SectorErase4
Erase 4 KByte of memory array 0010 0000b (20H)
1101 0111b (D7H)
3
0
0
64 KByte BlockErase5
Erase 64 KByte block
of memory array
1101 1000b (D8H)
3
0
0
Chip-Erase
Erase Full Memory Array
0110 0000b (60H)
or
1100 0111b (C7H)
0
0
0
Instruction
Fast-Read Dual I/O Read Memory with Dual
Address Input and Data Output
40 MHz
Page-Program
To program up to 256 Bytes
0000 0010b (02H)
3
0
1 to 256
RDSR6
Read-Status-Register
0000 0101b (05H)
0
0
1 to
WRSR
Write-Status-Register
0000 0001b (01H)
0
0
1
WREN
Write-Enable
0000 0110b (06H)
0
0
0
WRDI
Write-Disable
0000 0100b (04H)
0
0
0
RDID7, 8
Read-ID
1010 1011b (ABH)
3
0
1 to
JEDEC-ID
JEDEC ID Read
1001 1111b (9FH)
0
0
4 to
DPD
Deep Power-Down Mode
1011 1001b (B9H)
0
0
0
Release from Deep PowerDown or Read ID
1010 1011b (ABH)
0
0
0
8
RDPD
30 MHz
1.
2.
3.
4.
5.
6.
7.
One bus cycle is eight clock periods.
Address bits above the most significant bit of each density can be VIL or VIH.
One bus cycle is four clock periods in Dual Operation
4 KByte Sector-Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
64 KByte Block-Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
Device ID is read after three dummy address bytes. The Device ID output stream is continuous until terminated by a low-tohigh transition on CE#.
8. The instructions Release from Deep Power down and Read-ID are similar instructions (ABH). Executing Read-ID requires
the ABH instruction, followed by 24 dummy address bits to retrieve the Device ID. Release from Deep Power-Down only
requires the instruction ABH.
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DS20005193E-page 9
SST25WF040B
5.1
Read (30 MHz)
The Read instruction, 03H, supports up to 30 MHz
Read. The device outputs a data stream starting from
the specified address location. The data stream is continuous through all addresses until terminated by a lowto-high transition on CE#. The internal address pointer
automatically increments until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer automatically incre-
FIGURE 5-1:
ments to the beginning (wrap-around) of the address
space. For example, for 4 Mbit density, once the data
from the address location 7FFFFH is read, the next output is from address location 000000H. The Read
instruction is initiated by executing an 8-bit command,
03H, followed by address bits A23-A0. CE# must
remain active low for the duration of the Read cycle.
See Figure 5-1 for the Read sequence.
READ SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39 40
47
48
55 56
63 64
70
MODE 0
ADD.
03
SI
ADD.
ADD.
MSB
MSB
N
DOUT
HIGH IMPEDANCE
SO
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
5.2
High-Speed-Read (40 MHz)
The High-Speed-Read instruction supporting up to 40
MHz Read is initiated by executing an 8-bit command,
0BH, followed by address bits [A23-A0] and a dummy
byte. CE# must remain active low for the duration of the
High-Speed-Read cycle. See Figure 5-2 for the HighSpeed-Read sequence.
through all addresses until terminated by a low-to-high
transition on CE#. The internal address pointer will
automatically increment until the highest memory
address is reached. Once the highest memory address
is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address
space. For example, for 4 Mbit density, once the data
from address location 7FFFFH is read, the next output
will be from address location 000000H.
Following a dummy cycle, the High-Speed-Read
instruction outputs the data starting from the specified
address location. The data output stream is continuous
FIGURE 5-2:
HIGH-SPEED-READ SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
71 72
80
MODE 0
0B
SI
ADD.
ADD.
ADD.
X
MSB
SO
N
DOUT
HIGH IMPEDANCE
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
20005193 F07.0
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DS20005193E-page 10
SST25WF040B
5.3
Fast-Read Dual Output (40 MHz)
The Fast-Read Dual-Output (3BH) instruction outputs
data up to 40 MHz from the SIO0 and SIO1 pins. To initiate the instruction, execute an 8-bit command (3BH)
followed by address bits A23-A0 and a dummy byte on
SI/SIO0. Following a dummy cycle, the Fast-Read
Dual-Output instruction outputs the data starting from
the specified address location on the SIO1 and SIO0
lines. SIO1 outputs, per clock sequence, odd data bits
D7, D5, D3, and D1; and SIO0 outputs even data bits
D6, D4, D2, and D0. CE# must remain active low for the
FIGURE 5-3:
duration of the Fast-Read Dual-Output instruction
cycle. See Figure 5-3 for the Fast-Read Dual-Output
sequence.
The data output stream is continuous through all
addresses until terminated by a low-to-high transition
on CE#. The internal address pointer will automatically
increment until the highest memory address is
reached. Once the highest memory address is
reached, the address pointer automatically increments
to the beginning (wraparound) of the address space.
For 4 Mbit density, once the data from address location
7FFFFH has been read the next output will be from
address location 000000H.
FAST-READ DUAL OUTPUT SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
MODE 0
24-Bit Address
SIO0
ADD.
3B
ADD.
Dummy Cycle
ADD.
X
IO, Switches from Input to Output
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0
DOUT
SIO1
HIGH IMPEDANCE
DOUT
DOUT
DOUT
7 5 3 1
7 5 3 1
7 5 3 1
7 5 3 1
MSB
MSB
MSB
MSB
N
N+1
N+2
N+3
20005193 F52.0
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DS20005193E-page 11
SST25WF040B
5.4
Fast-Read Dual I/O (40 MHz)
Following a dummy cycle, the Fast-Read Dual I/O
instruction outputs the data starting from the specified
address location on the SIO1 and SIO0 lines. SIO1 outputs, per clock sequence, odd data bits D7, D5, D3,
and D1; and SIO0 outputs even data bits D6, D4, D2,
and D0 per clock edge. CE# must remain active low for
the duration of the Fast-Read Dual I/O instruction
cycle. The data output stream is continuous through all
addresses until terminated by a low-to-high transition
on CE#.
The Fast-Read Dual I/O (BBH) instruction reduces the
total number of input clock cycles, which results in
faster data access. The device is first selected by driving Chip Enable CE# low. Fast-Read Dual I/O is initiated by executing an 8-bit command (BBH) on SI/SIO0,
thereafter, the device accepts address bits A23-A0 and
a dummy byte on SI/SIO0 and SO/SIO1. It offers the
capability to input address bits A23-A0 at a rate of two
bits per clock. Odd address bits A23 through A1 are
input on SIO1 and even address bits A22 through A0
are input on SIO0, alternately For example, the most
significant bit is input first followed by A23/22, A21/A20,
and so on. Each bit is latched at the same rising edge
of the Serial Clock (SCK). The input data during the
dummy clocks is “don’t care”. However, the SIO0 and
SIO1 pin must be in high-impedance prior to the falling
edge of the first data output clock.
FIGURE 5-4:
The internal address pointer will automatically increment until the highest memory address is reached.
Once the highest memory address is reached, the
address pointer automatically increments to the beginning (wraparound) of the address space. For example,
once the data from address location 7FFFFH is read,
the next output is from address location 000000H. See
Figure 5-4 for the Fast-Read Dual I/O sequence.
FAST-READ DUAL I/O SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
MODE 0
Dummy
Cycle
SIO0
BB
6 4 2 0 6 4 2 0 6 4 2 0
X
IO, Switches from Input to Output
6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6
DOUT
SIO1
7 5 3 1
A23-16
7 5 3 1
A15-8
7 5 3 1
A7-0
X
DOUT
DOUT
DOUT
7 5 3 1
7 5 3 1
7 5 3 1
7 5 3 1 7
MSB
MSB
MSB
MSB
N
N+1
N+2
N+3
20005193 F53.0
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DS20005193E-page 12
SST25WF040B
5.5
Page-Program
The Page-Program instruction programs up to 256
Bytes of data in the memory. The data for the selected
page address must be in the erased state (FFH) before
initiating the Page-Program operation. A Page-Program applied to a protected memory area will be
ignored. Prior to the program operation, execute the
WREN instruction.
the internal, self-timed, Page-Program operation. See
Figure 5-5 for the Page-Program sequence and Figure
6-8 for the Page-Program flow chart.
When executing Page-Program, the memory range for
the SST25WF040B is divided into 256-Byte page
boundaries. The device handles the shifting of more
than 256 Bytes of data by maintaining the last 256
Bytes as the correct data to be programmed. If the target address for the Page-Program instruction is not the
beginning of the page boundary (A[7:0] are not all
zero), and the number of bytes of data input exceeds or
overlaps the end of the address of the page boundary,
the excess data inputs wrap around and will be programmed at the start of that target page.
To execute a Page-Program operation, the host drives
CE# low, then sends the Page-Program command
cycle (02H), three address cycles, followed by the data
to be programmed, and then drives CE# high. The programmed data must be between 1 to 256 Bytes and in
whole byte increments; sending less than a full byte will
cause the partial byte to be ignored. Poll the BUSY bit
in the Status register, or wait TPP, for the completion of
FIGURE 5-5:
PAGE-PROGRAM SEQUENCE
CE#
MODE 3
SCK
23 24
15 16
0 1 2 3 4 5 6 7 8
31 32
39
MODE 0
SI
ADD.
02
MSB
SO
ADD.
ADD.
Data Byte 0
LSB MSB
LSB MSB
LSB
HIGH IMPEDANCE
2079
2078
2077
2076
2075
2074
2073
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
CE#(cont’)
SCK(cont’)
SI(cont’)
Data Byte 1
MSB
SO(cont’)
Data Byte 255
Data Byte 2
LSB MSB
LSB
MSB
LSB
HIGH IMPEDANCE
20005193 F60.1
2013-2018 Microchip Technology Inc.
DS20005193E-page 13
SST25WF040B
5.6
Sector-Erase
(AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits
can be VIL or VIH. CE# must be driven high before the
instruction is executed. Poll the BUSY bit in the Software Status register, or wait TSE, for the completion of
the internal self-timed Sector-Erase cycle. See Figure
5-6 for the Sector-Erase sequence and Figure 6-9 for
the flow chart.
The Sector-Erase instruction clears all bits in the
selected 4 KByte sector to FFH. A Sector-Erase
instruction applied to a protected memory area will be
ignored. Prior to any Write operation, the Write-Enable
(WREN) instruction must be executed. CE# must
remain active low for the duration of any command
sequence. The Sector-Erase instruction is initiated by
executing an 8-bit command, 20H or D7H, followed by
address bits [A23-A0]. Address bits [AMS-A12]
FIGURE 5-6:
SECTOR-ERASE SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31
MODE 0
MSB
ADD.
ADD.
20 or D7
SI
ADD.
MSB
SO
HIGH IMPEDANCE
20005193 F13.0
5.7
64-KByte Block-Erase
The 64-KByte Block-Erase instruction clears all bits in
the selected 64 KByte block to FFH. Applying this
instruction to a protected memory area results in the
instruction being ignored. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of any command sequence.
Initiate the 64-Byte Block-Erase instruction by executing an 8-bit command, D8H, followed by address bits
FIGURE 5-7:
[A23-A0]. Address bits [AMS-A16] (AMS = Most Significant Address) determine the block address (BAX),
remaining address bits can be VIL or VIH. CE# must be
driven high before executing the instruction. Poll the Busy bit
in the software status register or wait TBE for the completion of the internal self-timed Block-Erase cycle. See
Figure 5-7 for the 64-KByte Block-Erase sequences
and Figure 6-9 for the flow chart.
64-KBYTE BLOCK-ERASE SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
D8
SI
MSB
SO
ADDR
ADDR
ADDR
MSB
HIGH IMPEDANCE
20005193 F15.0
2013-2018 Microchip Technology Inc.
DS20005193E-page 14
SST25WF040B
5.8
Chip-Erase
The Chip-Erase instruction clears all bits in the device
to FFH. A Chip-Erase instruction is ignored if any of the
memory area is protected. Prior to any Write operation,
the Write-Enable (WREN) instruction must be executed.
CE# must remain active low for the duration of the
Chip-Erase instruction sequence. Initiate the ChipErase instruction by executing an 8-bit command, 60H
FIGURE 5-8:
or C7H. CE# must be driven high before the instruction is
executed. Poll the BUSY bit in the Software Status register, or wait TSCE, for the completion of the internal
self-timed Chip-Erase cycle. See Figure 5-8 for the
Chip-Erase sequence and Figure 6-10 for the flow
chart.
CHIP-ERASE SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
60 or C7
SI
MSB
SO
HIGH IMPEDANCE
20005193 F16.0
5.9
Read-Status-Register (RDSR)
The Read-Status-Register (RDSR) instruction, 05H,
allows reading of the status register. The status register
may be read at any time even during a Write (Program/
Erase) operation. When a Write operation is in progress, the Busy bit may be checked before sending any
new commands to assure that the new commands are
FIGURE 5-9:
properly received by the device. CE# must be driven
low before the RDSR instruction is entered and remain
low until the status data is read. Read-Status-Register
is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE#. See Figure
5-9 for the RDSR instruction sequence.
READ-STATUS-REGISTER (RDSR) SEQUENCE
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 0
05
SI
MSB
SO
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
Status
Register Out
20005193 F17.0
2013-2018 Microchip Technology Inc.
DS20005193E-page 15
SST25WF040B
5.10
Write-Enable (WREN)
The Write-Enable (WREN) instruction, 06H, sets the
Write-Enable-Latch bit in the Status Register to 1 allowing Write operations to occur. The WREN instruction
must be executed prior to any Write (Program/Erase)
operation. The WREN instruction may also be used to
allow execution of the Write-Status-Register (WRSR)
FIGURE 5-10:
instruction; however, the Write-Enable-Latch bit in the
Status Register will be cleared upon the rising edge
CE# of the WRSR instruction. CE# must be driven low
before entering the WREN instruction, and CE# must
be driven high before executing the WREN instruction.
See Figure 5-10 for the WREN instruction sequence.
WRITE ENABLE (WREN) SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
06
SI
MSB
SO
HIGH IMPEDANCE
20005193 F18.0
5.11
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction, 04H, resets the
Write-Enable-Latch bit to ‘0’, thus preventing any new
Write operations. CE# must be driven low before enter-
FIGURE 5-11:
ing the WRDI instruction, and CE# must be driven high
before executing the WRDI instruction. See Figure 5-11
for the WRDI instruction sequence.
WRITE DISABLE (WRDI) SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
04
SI
MSB
SO
HIGH IMPEDANCE
20005193 F19.0
2013-2018 Microchip Technology Inc.
DS20005193E-page 16
SST25WF040B
5.12
Write-Status-Register (WRSR)
The Write-Status-Register instruction writes new values to the BP0, BP1, BP2, TB, and BPL bits of the status register. CE# must be driven low before the
command sequence of the WRSR instruction is
entered and driven high before the WRSR instruction is
executed. Poll the BUSY bit in the Software Status register, or wait TWRSR, for the completion of the internal
self-timed Write-Status-Register cycle. See Figure 5-12
for WREN and WRSR instruction sequences and Figure 6-11 for the WRSR flow chart.
‘1’ to lock-down the status register, but cannot be reset
from ‘1’ to ‘0’. When WP# is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1,
BP2, and TB bits in the status register can all be
changed. As long as BPL bit is set to ‘0’ or WP# pin is
driven high (VIH) prior to the low-to-high transition of the
CE# pin at the end of the WRSR instruction, the bits in
the status register can all be altered by the WRSR
instruction. In this case, a single WRSR instruction can
set the BPL bit to ‘1’ to lock down the status register as
well as altering the BP0, BP1, BP2, and TB bits at the
same time. See Table 4-1 for a summary description of
WP# and BPL functions.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to ‘1’. When
the WP# is low, the BPL bit can only be set from ‘0’ to
FIGURE 5-12:
WRITE-ENABLE (WREN) AND WRITE-STATUS-REGISTER (WRSR) SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
MODE 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MODE 0
06
SI
MSB
SO
01
MSB
STATUS
REGISTER IN
7 6 5 4 3 2 1 0
MSB
HIGH IMPEDANCE
20005193 F20.0
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DS20005193E-page 17
SST25WF040B
5.13
Power-Down
The Deep Power-Down (DPD) instruction puts the
device in the lowest power consumption mode – the
Deep Power-Down mode. This instruction is ignored if
the device is busy with an internal write operation.
While the device is in DPD mode, all instructions are
ignored except for the Release Deep Power-Down
instruction or Read ID.
before the standby current ISB is reduced to the deep
power-down current IDPD. See Figure 5-13 for the DPD
instruction sequence.
Exit the power-down state using the Release from
Deep Power-Down or Read ID instruction. CE# must
be driven low before sending the Release from Deep
Power-Down command cycle (ABH), and then driving
CE# high. The device will return to Standby mode and
be ready for the next instruction after TSBR. See Figure
5-14. for the Release from Deep Power-Down
sequence.
To initiate deep power-down, input the Deep PowerDown instruction (B9H) while driving CE# low. CE#
must be driven high before executing the DPD instruction. After driving CE# high, it requires a delay of TDPD
FIGURE 5-13:
DEEP POWER-DOWN SEQUENCE
CE#
TDPD
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
B9
SI
MSB
SO
HIGH IMPEDANCE
20005193 F46.1
FIGURE 5-14:
RELEASE FROM DEEP POWER-DOWN SEQUENCE
CE#
TSBR
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
AB
SI
MSB
SO
HIGH IMPEDANCE
20005193 F47.1
2013-2018 Microchip Technology Inc.
DS20005193E-page 18
SST25WF040B
5.14
Read-ID
The Read-ID instruction identifies the device as
SST25WF040B. Use the Read-ID instruction to identify
SST25WF040B when using multiple manufacturers in
the same socket. See Table 5-2.
command, ABH, followed by 24 dummy address bits.
Following the Read-ID instruction, and 24 address
dummy bits, the device ID continues to output with continuous clock input until terminated by a low-to-high
transition on CE#.
The device ID information is read by executing an 8-bit
TABLE 5-2:
PRODUCT IDENTIFICATION
SST25WF040B ID
FIGURE 5-15:
Address
Data
XXXXXXH
3EH
READ-ID SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39 40
47 48
55 56
63
MODE 0
XX
AB
SI
XX
MSB
XX
MSB
HIGH IMPEDANCE
SO
Device ID Device ID Device ID Device ID
HIGH
IMPEDANCE
MSB
20005193 F22.1
Note: The Device ID output stream is continuous until terminated by a low-to-high transition on CE#.
5.15
JEDEC Read-ID
The JEDEC Read-ID instruction identifies the device ID
information of SST25WF040B. The device information
can be read by executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, a 32bit device
ID information is output from the device. The Device ID
information is assigned by the manufacturer and contains the Device ID 1 in the first byte, the type of mem-
FIGURE 5-16:
ory in the second byte, the memory capacity of the
device in the third byte, and a reserved code in the
fourth byte. The 4-Byte code outputs repeatedly with
continuous clock input until a low-to-high transition on
CE#. See Figure 5-16 for the instruction sequence. The
JEDEC Read ID instruction is terminated by a low to
high transition on CE# at any time during data output.
JEDEC READ-ID SEQUENCE
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
MODE 0
SI
SO
9F
HIGH IMPEDANCE
16
62
MSB
13
00
MSB
20005193 F23.2
TABLE 5-3:
JEDEC READ-ID DATA-OUT
Device ID
Product
SST25WF040B
Device ID 1
(Byte 1)
62H
2013-2018 Microchip Technology Inc.
Memory Type (Byte 2)
16H
Memory Capacity (Byte 3)
13H
ReservedCode(Byte
4)
00H
DS20005193E-page 19
SST25WF040B
6.0
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational
sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may
affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (