0
登录后你可以
  • 下载海量资料
  • 学习在线课程
  • 观看技术视频
  • 写文章/发帖/加入社区
会员中心
创作中心
发布
  • 发文章

  • 发资料

  • 发帖

  • 提问

  • 发视频

创作活动
SY88345BLEY

SY88345BLEY

  • 厂商:

    ACTEL(微芯科技)

  • 封装:

    MSOP10_EP

  • 描述:

    IC POST AMP 3.3V 3.2GBPS 10-MSOP

  • 数据手册
  • 价格&库存
SY88345BLEY 数据手册
SY88345BL 3.3V, 3.2Gbps CML Low-Power Limiting Post Amplifier w/ High-Gain TTL Signal Detect General Description Features The SY88345BL high-sensitivity limiting post amplifier is designed for use in fiber-optic receivers. The device connects to typical transimpedance amplifiers (TIAs). The linear signal output from TIAs can contain significant amounts of noise and may vary in amplitude over time. The SY88345BL quantizes these signals and outputs CML-level waveforms. The SY88345BL operates from a single +3.3V +10% power supply, and over temperatures ranging from o o –40 C to +85 C. With its wide bandwidth, high gain, and signals with data rates up to 3.2Gbps and as small as 5mVPP can be amplified to drive devices with CML inputs or AC-coupled CML/PECL inputs. The SY88345BL generates a signal-detect (SD) opencollector TTL output. A programmable signal-detect level-set pin (SDLVL) sets the sensitivity of the input amplitude detection. SD asserts high if the input amplitude rises above the threshold sets by SDLVL and de-asserts low otherwise. The enable input (EN) deasserts the true output signal without removing the input signal. The SD output can be fed back to the EN input to maintain output stability under loss-of-signal condition. Typically, 3.5dB SD hysteresis is provided to prevent chattering. Datasheet and support documentation can be found on Micrel’s web site at: www.micrel.com. • • • • • • • • • Single 3.3V power supply 155Mbps to 3.2Gbps operation Low-noise CML data outputs Chatter-free Open-Collector TTL signal detect (SD) output with internal 4.75kΩ pull-up resistor TTL EN input Internal 50Ω input termination Programmable SD level set (SDLVL) Ideal for multi-rate applications Available in a tiny 10-pin EPAD MSOP and 16-pin QFN package Applications • • • • • APON/BPON, EPON, GPON and GEPON Gigabit Ethernet 1X and 2X Fibre Channel SONET/SDH: OC-3/12/24/48–STMD/4/8/16 High-gain line driver and line receiver Markets • • • • FTTP/FTTH Optical transceivers Datacom/Telecom Low-gain TIA interface Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com February 2007 M9999-021207-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88345BL Typical Application Pin Configuration 10-Pin EPAD-MSOP (K10-2) 16-Pin QFN Ordering Information Part Number SY88345BLEY (1) SY88345BLEYTR (2) SY88345BLMG (1, 2) SY88345BLMGTR Package Type Operating Range Package Marking K10-2 Industrial 345B with Pb-Free bar line indicator Matte-Sn K10-2 Industrial 345B with Pb-Free bar line indicator Matte-Sn QFN-16 Industrial 345B with Pb-Free bar line indicator NiPdAu Pb-Free QFN-16 Industrial 345B with Pb-Free bar line indicator NiPdAu Pb-Free Lead Finish Notes: 1. Tape and Reel. 2. Pb-Free package is recommended for new designs. February 2007 2 M9999-021207-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88345BL Pin Description Pin Number (MSOP) Pin Number (QFN) Pin Name Type 1 15 EN TTL Input: Default is high. 2 1 DIN Data Input True data input w/50Ω termination to VREF. 3 4 /DIN Data Input Complementary data input w/50Ω termination to VREF. 4 6 VREF 5 14 SDLVL Input: Default is maximum sensitivity 6 Exposed Pad 2, 3, 10, 11 Exposed Pad GND Ground Device ground. Exposed pad must be connected to PCB ground plane. 7 7 SD Open Collector TTL Output with Internal 4.75kΩ pull-up Resistor Signal-detect: Asserts high when the data input amplitude rises above the threshold sets by SDLVL. 8 9 /DOUT CML Output Complementary data output. 9 12 DOUT CML Output True data output. 10 5, 8, 13, 16 VCC Power supply February 2007 Pin Function Enable: De-asserts true data output when LOW. Reference Voltage: Placing a capacitor here to VCC helps stabilize SDLVL. 3 Signal-detect Level Set: A resistor from this pin to VCC sets the threshold for the data input amplitude at which the SD output will be asserted. Positive power supply. M9999-021207-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88345BL Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) .................................... 0V to +4.0V Input Voltage (DIN, /DIN) ................................... 0 to VCC Output Current (IOUT) ............................................+25mA EN Voltage ......................................................... 0 to VCC VREF Current……………………………-800uA to +500uA SDLVL Voltage ................................................ VREF to VCC Lead Temperature (soldering, 20sec.) .................. 260°C Storage Temperature (Ts) .....................-65°C to +150°C Supply Voltage (VCC) ................................. +3.0V to +3.6V Ambient Temperature (TA) .......................–40°C to +85°C Junction Temperature (TJ) .....................–40°C to +125°C Junction Thermal Resistance QFN (θJA) Still-air ................................................ 61°C/W (ΨJB)............................................................ 38°C/W EPAD-MSOP (θJA) Still-air ................................................ 38°C/W (ΨJB)............................................................ 22°C/W DC Electrical Characteristics VCC = 3.0V to 3.6V; RLOAD = 50Ω to VCC; TA = –40°C to +85°C. Symbol Parameter Condition ICC Power Supply Current No output load SDLVL SDLVL Voltage VOH CML Output HIGH Voltage Min Typ Max Units 42 65 mA VCC V VCC V VREF VCC-0.020 VCC-0.005 VOL CML Output LOW Voltage VOFFSET Differential Output Offset VCC = 3.3V VCC-0.475 VCC-0.400 VCC-0.350 ZO Single-Ended Output Impedance 40 ZI Single-Ended Input Impedance 40 VREF Reference Voltage V +80 mV 50 60 Ω 50 60 Ω VCC-1.28 V TTL DC Electrical Characteristics VCC = 3.0V to 3.6V; RLOAD = 50Ω to VCC; TA = –40°C to +85°C. Symbol Parameter VIH EN Input HIGH Voltage VIL EN Input LOW Voltage IIH EN Input HIGH Current Condition Min Typ Max 2.0 Units V 0.8 V VIN = 2.7V 20 µA VIN = VCC 100 µA IIL EN Input LOW Current VIN = 0.5V VOH SD Output HIGH Level VCC ≥ 3.3V, IOH (max) < 160µA 2.4 V VCC < 3.3V, IOH (max) < 160µA 2.0 V VOL SD Output LOW Level -300 Sinking 2mA µA 0.5 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential (GND) on the PCB. ΨJB uses 4-layer (θJA) in still-air-number, unless otherwise stated. February 2007 4 M9999-021207-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88345BL AC Electrical Characteristics VCC = 3.0V to 3.6V; RLOAD = 50Ω to VCC; TA = –40°C to +85°C. Symbol Parameter tr , tf Output Rise/Fall Time Typ Max Note 4 60 120 Deterministic Note 5 15 psPP Random Note 6 5 psRMS VID Differential Input Voltage Swing Figure 1 VOD Differential Output Voltage Swing VID > 10mVPP Figure 1 TOFF (20% to 80%) tJITTER Condition Min 5 Units ps 1800 mVPP 800 950 mVPP SD De-assert Time 2 10 µs TON SD Assert Time 2 10 µs SDAL Low SD Assert Level RSDLVL = 15kΩ, Note 8 4.5 mVPP SDDL Low SD De-assert Level RSDLVL = 15kΩ, Note 8 3.0 mVPP HYSL Low SD Hysteresis RSDLVL = 15kΩ, Note 7 3.5 dB SDAM Medium SD Assert Level RSDLVL = 5kΩ, Note 8 SDDM Medium SD De-assert Level RSDLVL = 5kΩ, Note 8 2 5.0 HYSM Medium SD Hysteresis RSDLVL = 5kΩ, Note 7 2 3.5 4.5 dB SDAH High SD Assert Level RSDLVL = 100Ω, Note 8 18 23 mVPP SDDH High SD De-assert Level RSDLVL = 100Ω, Note 8 8 12 HYSH High SD Hysteresis RSDLVL = 100Ω, Note 7 2 3.5 B-3dB 3dB Bandwidth AV(Diff) Differential Voltage Gain S21 Single-ended Small-Signal Gain 700 7.5 11 mVPP mVPP mVPP 4.5 dB 2 GHz 32 38 dB 26 32 dB Notes: 4. Amplifier in limiting mode. Input is a 200MHz square wave. 5. Deterministic jitter measured using 3.2Gbps K28.5 pattern, VID = 10mVPP. 6. Random jitter measured using 3.2Gbps K28.7 pattern, VID = 10mVPP. 7. This specification defines electrical hysteresis as 20log (SD Assert/SD De-assert). The ratio between optical hysteresis and electrical hysteresis is found to vary between 1.5 and 2, depending upon the level of received optical power and ROSA characteristics. Based upon that ratio, the optical hysteresis corresponding to the electrical hysteresis range 2dB-4.5dB, as shown in the AC characteristics table, will be 1dB-3dB. 8. See “Typical Operating Characteristics” for a graph showing how to choose a particular RSDLVL for a particular SD assert and its associated de-assert amplitude. February 2007 5 M9999-021207-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88345BL Typical Characteristics RSDLVL (kΩ) February 2007 RSDLVL (kΩ) 6 M9999-021207-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88345BL Functional Diagram Detailed Description The SY88345BL low-power, high-sensitivity limiting post amplifier operates from a single +3.3V power supply, o o over temperatures from –40 C to +85 C. Signals with data rates up to 3.2Gbps and as small as 5mVPP can be amplified. Figure 1 shows the allowed input voltage swing. The SY88345BL generates an SD output. SDLVL sets the sensitivity of the input amplitude detection. Input Amplifier/Buffer Figure 2 shows a simplified schematic of the SY88345BL’s input stage. The high-sensitivity of the input amplifier allows signals as small as 5mVPP to be detected and amplified. The input amplifier also allows input signals as large as 1800mVPP. Input signals are linearly amplified with a typical 38dB differential voltage gain. Since it is a limiting amplifier, the SY88345BL typically outputs 800mVPP voltage-limited waveforms for input signals that are greater than 12mVPP. Applications requiring the SY88345BL to operate with high-gain should have the upstream TIA placed as close as possible to the SY88345BL’s input pins to ensure the best performance of the device. Output Buffer The SY88345BL’s CML output buffer is designed to drive 50Ω lines. The output buffer requires appropriate termination for proper operation. An external Ω 50 resistor to VCC for each output pin provides this. Figure 3 shows a simplified schematic of the output stage. February 2007 Signal-Detect The SY88345BL generates a chatter-free SD opencollector TTL output with an internal 4.75k Ω pull -up resistor, as shown in Figure 4. SD is used to determine that the input amplitude is large enough to be considered a valid input. SD asserts high if the input amplitude rises above the threshold sets by SDLVL and de-asserts low otherwise. SD can be fed back to the enable (EN) input to maintain output stability under a loss-of-signal condition. EN de-asserts the true output signal without removing the input signals. Typically, 3.5dB SD hysteresis is provided to prevent chattering. Signal-Detect Level Set A programmable SD level-set pin (SDLVL) sets the threshold of the input amplitude detection. Connecting an external resistor between VCC and SDLVL sets the voltage at SDLVL. This voltage ranges from VCC to VREF. The external resistor creates a voltage divider between VCC and VREF, as shown in Figure 5. Hysteresis The SY88345BL typically provides 3.5dB SD electrical hysteresis. By definition, a power ratio measured in dB 2 is 10log (power ratio). Power is calculated as V IN/R for an electrical signal. Hence, the same ratio can be stated as 20log (voltage ratio). While in linear mode, the electrical voltage input changes linearly with the optical power. Therefore, the ratios change linearly. Thus, the optical hysteresis in dB is half the electrical hysteresis in dB given in the data sheet. Since the SY88345BL is an electrical device, this data sheet refers to hysteresis in electrical terms. With 3.5dB SD hysteresis, a voltage factor of 1.5 is required to assert or de-assert SD. 7 M9999-021207-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88345BL Figure 1. VIS and VID Definition February 2007 Figure 2. Input Structure Figure 3. Output Structure Figure 4. SD Output Structure Figure 5. SDLVL Setting Circuit 8 M9999-021207-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88345BL Package Information 10-Pin EPAD-MSOP (K10-2) February 2007 9 M9999-021207-B hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88345BL 16-Pin QFN MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2006 Micrel, Incorporated. February 2007 10 M9999-021207-B hbwhelp@micrel.com or (408) 955-1690
SY88345BLEY 价格&库存

很抱歉,暂时无法提供与“SY88345BLEY”相匹配的价格&库存,您可以联系我们找货

免费人工找货