USB3250-ABZJ

USB3250 Hi-Speed USB Device Transceiver with UTMI Interface Highlights Applications • USB-IF "Hi-Speed" certified to USB 2.0 electrical specification • Interface compliant with the UTMI specification (60MHz 8-bit unidirectional interface or 30MHz 16-bit bidirectional interface) • Supports 480Mbps High Speed (HS) and 12Mbps Full Speed (FS) serial data transmission rates • Integrated 45 and 1.5k termination resistors reduce external component count • Internal short circuit protection of DP and DM lines • On-chip oscillator operates with low cost 12MHz crystal • Robust and low power digital clock and data recovery circuit • SYNC and EOP generation on transmit packets and detection on receive packets • NRZI encoding and decoding • Bit stuffing and unstuffing with error detection • Supports the USB suspend state, HS detection, HS Chirp, Reset and Resume • Support for all test modes defined in the USB 2.0 specification • Draws 72mA (185mW) maximum current consumption in HS mode - ideal for bus powered functions • On-die decoupling capacitance and isolation for immunity to digital switching noise • Available in a 56-pin VQFN package • Full industrial operating temperature range from -40oC to +85oC (ambient) The Universal Serial Bus (USB) is the preferred interface to connect Hi-Speed PC peripherals.  2013 - 2016 Microchip Technology Inc. • • • • • • • • • Digital Still and Video Cameras MP3 Players External Hard Drives Scanners Entertainment Devices Printers Test and Measurement Systems POS Terminals Set Top Boxes DS00002142A-page 1 USB3250 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. 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DS00002142A-page 2  2013 - 2016 Microchip Technology Inc. USB3250 Table of Contents 1.0 General Description ........................................................................................................................................................................ 4 2.0 Functional Block Diagram ............................................................................................................................................................... 5 3.0 Pin Configuration ............................................................................................................................................................................ 6 4.0 Interface Signal Definition ............................................................................................................................................................... 7 5.0 Limiting Values .............................................................................................................................................................................. 10 6.0 Electrical Characteristics ............................................................................................................................................................... 11 7.0 Functional Overview ..................................................................................................................................................................... 19 8.0 Application Notes .......................................................................................................................................................................... 27 9.0 Package Outline ............................................................................................................................................................................ 40 Appendix A: Data Sheet Revision History ........................................................................................................................................... 42 The Microchip Web Site ...................................................................................................................................................................... 43 Customer Change Notification Service ............................................................................................................................................... 43 Customer Support ............................................................................................................................................................................... 43 Product Identification System ............................................................................................................................................................. 44  2013 - 2016 Microchip Technology Inc. DS00002142A-page 3 USB3250 1.0 GENERAL DESCRIPTION The USB3250 provides the Physical Layer (PHY) interface to a USB 2.0 Device Controller. The IC is available in a 56pin VQFN. The USB3250 is a USB 2.0 physical layer transceiver (PHY) integrated circuit. Microchip's proprietary technology results in low power dissipation, which is ideal for building a bus powered USB 2.0 peripheral. The PHY can be configured for either an 8-bit unidirectional or a 16-bit bidirectional parallel interface, which complies with the USB Transceiver Macrocell Interface (UTMI) specification. It supports 480Mbps transfer rate, while remaining backward compatible with USB 1.1 legacy protocol at 12Mbps. All required termination for the USB 2.0 Transceiver is internal. Internal 5.25V short circuit protection of DP and DM lines is provided for USB compliance. While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding. DS00002142A-page 4  2013 - 2016 Microchip Technology Inc. USB3250 2.0 FUNCTIONAL BLOCK DIAGRAM FIGURE 2-1: BLOCK DIAGRAM XO XI VDD1.8 VDD3.3 PWR CONTROL System Clocking PLL and XTAL OSC TX LOGIC TX RPU_EN 1.5k  TX State Machine VPO VMO Parallel to Serial Conversion DATABUS16_8 RESET HS_DATA Bit Stuff SUSPENDN FS TX OEB HS_DRIVE_ENABLE XCVRSELECT HS_CS_ENABLE HS TX NRZ Encode TERMSELECT DP OPMODE[1:0] TXREADY VALIDH RX LOGIC FS SE+ RX State Machine VP VM Serial to Parallel Conversion Clock Recovery Unit Clock and Data Recovery Bit Unstuff RXVALID RXACTIVE FS SE- NRZI Decode RXERROR Elasticity Buffer BIASING Bandgap Voltage Reference FS RX MUX DATA[15:0] * UTMI Interface CLKOUT TXVALID DM RX LINESTATE[1:0] HS RX HS SQ RBIAS Current Reference Note: See Section 7.1, "Modes of Operation," on page 19 for a description of the digital interface.  2013 - 2016 Microchip Technology Inc. DS00002142A-page 5 USB3250 PIN CONFIGURATION CLKOUT VSS VALIDH RXVALID TXVALID DATA[0] VDD3.3 47 46 45 44 43 RXACTIVE 50 48 TXREADY 51 49 VDD1.8 RXERROR 52 DATABUS16_8 36 DATA[6] 35 DATA[7] 9 34 DATA[8] 10 33 VSS 11 32 DATA[9] 12 31 DATA[10] 13 30 DATA[11] 14 29 DATA[12] 19 20 21 22 23 24 25 26 27 OPMODE[1] OPMODE[0] LINESTATE[1] LINESTATE[0] VDD1.8 RESET DATA[15] DATA[14] DATA[13] VDD3.3 18 28 DATA[5] 8 VSS 53 VDD1.8 37 5 VSSA SUSPENDN 54 38 7 VDDA1.8 VSS DATA[4] USB 2.0 USB3250 PHY IC 4 6 XO VSS DATA[3] 39 RBIAS XI 55 3 VDDA3.3 VSSA DS00002142A-page 6 DATA[2] 40 TERMSELECT VSSA 2 17 VDDA3.3 DATA[1] 41 XCVRSELECT DP 42 16 DM 1 VDD1.8 VSSA 56 56-PIN USB3250 PIN CONFIGURATION (TOP VIEW) 15 FIGURE 3-1: VDD3.3 3.0  2013 - 2016 Microchip Technology Inc. USB3250 4.0 INTERFACE SIGNAL DEFINITION TABLE 4-1: Name SYSTEM INTERFACE SIGNALS Direction Active Level Description RESET Input High Reset. Reset all state machines. After coming out of reset, must wait 5 rising edges of clock before asserting TXValid for transmit. Assertion of Reset: May be asynchronous to CLKOUT. De-assertion of Reset: Must be synchronous to CLKOUT unless RESET is asserted longer than two periods of CLKOUT. XCVRSELECT Input N/A Transceiver Select. This signal selects between the FS and HS transceivers: 0: HS transceiver enabled 1: FS transceiver enabled. TERMSELECT Input N/A Termination Select. This signal selects between the FS and HS terminations: 0: HS termination enabled 1: FS termination enabled SUSPENDN Input Low Suspend. Places the transceiver in a mode that draws minimal power from supplies. Shuts down all blocks not necessary for Suspend/Resume operation. While suspended, TERMSELECT must always be in FS mode to ensure that the 1.5k  pull-up on DP remains powered. 0: Transceiver circuitry drawing suspend current 1: Transceiver circuitry drawing normal current CLKOUT OPMODE[1:0] Output Rising Edge System Clock. This output is used for clocking receive and transmit parallel data at 60MHz (8-bit mode) or 30MHz (16-bit mode). When in 8-bit mode, this specification refers to CLKOUT as CLK60. When in 16-bit mode, CLKOUT is referred to as CLK30. Input N/A Operational Mode. These signals select between the various operational modes: [1] [0] Description 0 0 0: Normal Operation 0 1 1: Non-driving (all terminations removed) 1 0 2: Disable bit stuffing and NRZI encoding 1 1 3: Reserved LINESTATE[1:0] Output N/A Line State. These signals reflect the current state of the USB data bus in FS mode, with [0] reflecting the state of DP and [1] reflecting the state of DM. When the device is suspended or resuming from a suspended state, the signals are combinatoria. Otherwise, the signals are synchronized to CLKOUT. [1] [0] Description 0 0 0: SE0 0 1 1: J State 1 0 2: K State 1 1 3: SE1 DATABUS16_8 Input N/A Databus Select. Selects between 8-bit and 16-bit data transfers. 0 8-bit data path enabled. VALIDH is undefined. CLKOUT = 60MHz. 1: 16-bit data path enabled. CLKOUT = 30MHz.  2013 - 2016 Microchip Technology Inc. DS00002142A-page 7 USB3250 TABLE 4-2: DATA INTERFACE SIGNALS Name DATA[15:0] Direction Active Level Description Bidir N/A DATA BUS. 16-BIT BIDIRECTIONAL MODE. TXVALID RXVALID VALIDH 0 0 X Not used DATA[15:0] 0 1 0 DATA[7:0] output is valid for receive VALIDH is an output 0 1 1 DATA[15:0] output is valid for receive VALIDH is an output 1 X 0 DATA[7:0] input is valid for transmit VALIDH is an input 1 X 1 DATA[15:0] input is valid for transmit VALIDH is an input DATA BUS. 8-BIT UNIDIRECTIONAL MODE. TXVALID Input High TXVALID RXVALID DATA[15:0] 0 0 Not used 0 1 DATA[15:8] output is valid for receive 1 X DATA[7:0] input is valid for transmit Transmit Valid. Indicates that the TXDATA bus is valid for transmit. The assertion of TXVALID initiates the transmission of SYNC on the USB bus. The negation of TXVALID initiates EOP on the USB. Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT) must not be changed on the de-assertion or assertion of TXVALID. The PHY must be in a quiescent state when these inputs are changed. TXREADY VALIDH Output High Transmit Data Ready. If TXVALID is asserted, the SIE must always have data available for clocking into the TX Holding Register on the rising edge of CLKOUT. TXREADY is an acknowledgment to the SIE that the transceiver has clocked the data from the bus and is ready for the next transfer on the bus. If TXVALID is negated, TXREADY can be ignored by the SIE. Bidir N/A Transmit/Receive High Data Bit Valid (used in 16-bit mode only). When TXVALID = 1, the 16-bit data bus direction is changed to inputs, and VALIDH is an input. If VALIDH is asserted, DATA[15:0] is valid for transmission. If deasserted, only DATA[7:0] is valid for transmission. The DATA bus is driven by the SIE. When TXVALID = 0 and RXVALID = 1, the 16-bit data bus direction is changed to outputs, and VALIDH is an output. If VALIDH is asserted, the DATA[15:0] outputs are valid for receive. If deasserted, only DATA[7:0] is valid for receive. The DATA bus is read by the SIE. RXVALID Output High Receive Data Valid. Indicates that the RXDATA bus has received valid data. The Receive Data Holding Register is full and ready to be unloaded. The SIE is expected to latch the RXDATA bus on the rising edge of CLKOUT. RXACTIVE Output High Receive Active. Indicates that the receive state machine has detected Start of Packet and is active. RXERROR Output High Receive Error. 0: Indicates no error. 1: Indicates a receive error has been detected. This output is clocked with the same timing as the RXDATA lines and can occur at anytime during a transfer. DS00002142A-page 8  2013 - 2016 Microchip Technology Inc. USB3250 TABLE 4-3: Name USB I/O SIGNALS Direction Active Level DP I/O N/A USB Positive Data Pin. DM I/O N/A USB Negative Data Pin. TABLE 4-4: Name Description BIASING AND CLOCK OSCILLATOR SIGNALS Direction Active Level Description RBIAS Input N/A External 1% bias resistor. Requires a 12K resistor to ground. Used for setting HS transmit current level and on-chip termination impedance. XI/XO Input N/A External crystal. 12MHz crystal connected from XI to XO. TABLE 4-5: Name POWER AND GROUND SIGNALS Direction Active Level Description VDD3.3 N/A N/A 3.3V Digital Supply. Powers digital pads. See Note 4-1 VDD1.8 N/A N/A 1.8V Digital Supply. Powers digital core. VSS N/A N/A Digital Ground. See Note 4-2 VDDA3.3 N/A N/A 3.3V Analog Supply. Powers analog I/O and 3.3V analog circuitry. VDDA1.8 N/A N/A 1.8V Analog Supply. Powers 1.8V analog circuitry. See Note 4-1 VSSA Note 4-1 N/A N/A Analog Ground. See Note 4-2 A Ferrite Bead (with DC resistance