USB3280-AEZG

USB3280 Hi-Speed USB Device PHY with UTMI Interface Highlights Applications • Available in a 36-pin RoHS compliant (6 x 6 x 0.90mm) QFN package • Interface compliant with the UTMI specification (60MHz, 8-bit bidirectional interface) • Only one required power supply (+3.3V) • USB-IF “Hi-Speed” certified to USB 2.0 electrical specification • Supports 480Mbps Hi-Speed (HS) and 12Mbps Full Speed (FS) serial data transmission rates • Integrated 45Ω and 1.5kΩ termination resistors reduce external component count • Internal short circuit protection of DP and DM lines • On-chip oscillator operates with low cost 24MHz crystal • Latch-up performance exceeds 150mA per EIA/ JESD 78, Class II • ESD protection levels of 5kV HBM without external protection devices • SYNC and EOP generation on transmit packets and detection on receive packets • NRZI encoding and decoding • Bit stuffing and unstuffing with error detection • Supports the USB suspend state, HS detection, HS Chirp, Reset and Resume • Support for all test modes defined in the USB 2.0 specification • 55mA Unconfigured Current (typical) - ideal for bus powered applications. • 83uA suspend current (typical) - ideal for battery powered applications. • Industrial Operating Temperature -40oC to +85oC The USB3280 is the ideal companion to any ASIC, SoC or FPGA solution designed with a UTMI Hi-Speed USB device (peripheral) core.  2004 - 2015 Microchip Technology Inc. The USB3280 is well suited for: • • • • • • • • Cell Phones MP3 Players Scanners External Hard Drives Digital Still and Video Cameras Portable Media Players Entertainment Devices Printers DS00001898A-page 1 USB3280 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com. We welcome your feedback. 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DS00001898A-page 2  2004 - 2015 Microchip Technology Inc. USB3280 Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Functional Block Diagram ............................................................................................................................................................... 5 3.0 Pin Layout ....................................................................................................................................................................................... 6 4.0 Interface Signal Definition ............................................................................................................................................................... 7 5.0 Limiting Values .............................................................................................................................................................................. 10 6.0 Electrical Characteristics ............................................................................................................................................................... 11 7.0 Functional Overview ..................................................................................................................................................................... 17 8.0 Application Notes .......................................................................................................................................................................... 24 9.0 Package Outline ............................................................................................................................................................................ 37 Appendix A: Data Sheet Revision History ........................................................................................................................................... 40 The Microchip Web Site ...................................................................................................................................................................... 41 Customer Change Notification Service ............................................................................................................................................... 41 Customer Support ............................................................................................................................................................................... 41 Product Identification System ............................................................................................................................................................. 42  2004 - 2015 Microchip Technology Inc. DS00001898A-page 3 USB3280 1.0 INTRODUCTION The USB3280 provides the Physical Layer (PHY) interface to a USB 2.0 Device Controller. The IC is available in a 36pin RoHS compliant QFN package. 1.1 Product Description The USB3280 is an industrial temperature USB 2.0 physical layer transceiver (PHY) integrated circuit. Microchip’s proprietary technology results in low power dissipation, which is ideal for building a bus powered USB 2.0 peripheral. The PHY uses an 8-bit bidirectional parallel interface, which complies with the USB Transceiver Macrocell Interface (UTMI) specification. It supports 480Mbps transfer rate, while remaining backward compatible with USB 1.1 legacy protocol at 12Mbps. All required termination and 5.25V short circuit protection of the DP/DM lines are internal to the chip. The USB3280 also has an integrated 1.8V regulator so that only a 3.3V supply is required. While transmitting data, the PHY serializes data and generates SYNC and EOP fields. It also performs needed bit stuffing and NRZI encoding. Likewise, while receiving data, the PHY de-serializes incoming data, stripping SYNC and EOP fields and performs bit un-stuffing and NRZI decoding. DS00001898A-page 4  2004 - 2015 Microchip Technology Inc. USB3280 2.0 FUNCTIONAL BLOCK DIAGRAM FIGURE 2-1: USB3280 BLOCK DIAGRAM XO XI VDD3.3 PWR Control PLL and XTAL OSC 1.8V Regulator TX LOGIC TX RPU_EN 1.5kΩ TX State Machine VPO VMO Parallel to Serial Conversion RESET HS_DATA HS_DRIVE_ENABLE NRZI Encode XCVRSELECT FS TX OEB Bit Stuff SUSPENDN System Clocking HS_CS_ENABLE HS TX TERMSELECT DP OPMODE[1:0] R X LINESTATE[1:0] TXVALID TXREADY RX LOGIC FS SE+ VP RX State Machine Serial to Parallel Conversion VM Bit Unstuff RXVALID RXACTIVE FS SE- Clock Recovery Unit NRZI Decode Clock and Data Recovery Elasticity Buffer RXERROR FS RX MUX DATA[7:0] UTMI Interface CLKOUT DM HS RX BIASING HS SQ Bandgap Voltage Reference RBIAS Current Reference  2004 - 2015 Microchip Technology Inc. DS00001898A-page 5 USB3280 PIN LAYOUT FIGURE 3-2: RBIAS REG_EN VDD3.3 VDDA1.8 XI XO VDD1.8 VDD3.3 RXERROR 36 35 34 33 32 31 30 29 28 USB3280 Pin Layout - Top View 27 RXVALID 2 26 DATA[0] 3 25 DATA[1] 24 DATA[2] 23 DATA[3] 22 DATA[4] 21 DATA[5] XCVRSELECT 1 TERMSELECT TXREADY SUSPENDN 4 TXVALID 5 RESET 6 USB2.0 USB3280 PHY IC 14 15 16 17 18 CLKOUT LINESTATE0 VDD1.8 VDD3.3 DATA[7] LINESTATE1 19 13 9 OPMODE0 DATA[6] DM 12 20 11 8 OPMODE1 7 DP RXACTIVE VDD3.3 10 FIGURE 3-1: VDD3.3 3.0 USB3280 PIN LAYOUT - BOTTOM VIEW EXPOSED GND PAD The flag of the QFN package must be connected to ground. DS00001898A-page 6  2004 - 2015 Microchip Technology Inc. USB3280 4.0 INTERFACE SIGNAL DEFINITION TABLE 4-1: SYSTEM INTERFACE SIGNALS Name Direction Active Level RESET (RST) Input High Reset. Reset all state machines. After coming out of reset, must wait 5 rising edges of clock before asserting TXValid for transmit. See Section 7.8.3 XCVRSELECT (XSEL) Input N/A Transceiver Select. This signal selects between the FS and HS transceivers: 0: HS transceiver enabled 1: FS transceiver enabled. TERMSELECT (TSEL) Input N/A Termination Select. This signal selects between the FS and HS terminations: 0: HS termination enabled 1: FS termination enabled SUSPENDN (SPDN) Input Low Suspend. Places the transceiver in a mode that draws minimal power from supplies. Shuts down all blocks not necessary for Suspend/Resume operation. While suspended, TERMSELECT must always be in FS mode to ensure that the 1.5kΩ pull-up on DP remains powered. 0: Transceiver circuitry drawing suspend current 1: Transceiver circuitry drawing normal current CLKOUT (CLK) Output Rising Edge OPMODE[1:0] (OM1) (OM0) Input N/A Operational Mode. These signals select between the various operational modes: [1] [0] Description 0 0 0: Normal Operation 0 1 1: Non-driving (all terminations removed) 1 0 2: Disable bit stuffing and NRZI encoding 1 1 3: Reserved LINESTATE[1:0] (LS1) (LS0) Output N/A Line State. These signals reflect the current state of the USB data bus in FS mode, with [0] reflecting the state of DP and [1] reflecting the state of DM. When the device is suspended or resuming from a suspended state, the signals are combinatorial. Otherwise, the signals are synchronized to CLKOUT. [1] [0] Description 0 0 0: SE0 0 1 1: J State 1 0 2: K State 1 1 3: SE1  2004 - 2015 Microchip Technology Inc. Description System Clock. This output is used for clocking receive and transmit parallel data at 60MHz. DS00001898A-page 7 USB3280 TABLE 4-2: DATA INTERFACE SIGNALS Name Direction Active Level DATA[7:0] (D7) . . . (D0) Bidirectional High TXVALID (TXV) Input Description Data bus. 8-bit Bidirectional mode. TXVALID High DATA[7:0] 0 output 1 input Transmit Valid. Indicates that the DATA bus is valid for transmit. The assertion of TXVALID initiates the transmission of SYNC on the USB bus. The negation of TXVALID initiates EOP on the USB. Control inputs (OPMODE[1:0], TERMSELECT,XCVRSELECT) must not be changed on the de-assertion or assertion of TXVALID. The PHY must be in a quiescent state when these inputs are changed. TXREADY (TXR) Output High Transmit Data Ready. If TXVALID is asserted, the SIE must always have data available for clocking into the TX Holding Register on the rising edge of CLKOUT. TXREADY is an acknowledgement to the SIE that the transceiver has clocked the data from the bus and is ready for the next transfer on the bus. If TXVALID is negated, TXREADY can be ignored by the SIE. RXVALID (RXV) Output High Receive Data Valid. Indicates that the DATA bus has received valid data. The Receive Data Holding Register is full and ready to be unloaded. The SIE is expected to latch the DATA bus on the rising edge of CLKOUT. RXACTIVE (RXA) Output High Receive Active. Indicates that the receive state machine has detected Start of Packet and is active. RXERROR (RXE) Output High Receive Error. 0: Indicates no error. 1: Indicates a receive error has been detected. This output is clocked with the same timing as the receive DATA lines and can occur at anytime during a transfer. TABLE 4-3: USB I/O SIGNALS Name Direction Active Level Description DP I/O N/A USB Positive Data Pin. DM I/O N/A USB Negative Data Pin. TABLE 4-4: BIASING AND CLOCK OSCILLATOR SIGNALS Name Direction Active Level RBIAS (RB) Input N/A External 1% bias resistor. Requires a 12kΩ resistor to ground. Used for setting HS transmit current level and on-chip termination impedance. XI/XO Input N/A External crystal. 24MHz crystal connected from XI to XO. DS00001898A-page 8 Description  2004 - 2015 Microchip Technology Inc. USB3280 TABLE 4-5: POWER AND GROUND SIGNALS Name Direction Active Level VDD3.3 (V33) N/A N/A 3.3V Supply. Provides power for USB 2.0 Transceiver, UTMI+ Digital, Digital I/O, and Regulators. REG_EN (REN) Input High On-Chip 1.8V regulator enable. Connect to ground to disable both of the on chip (VDDA1.8 and VDD1.8) regulators. When regulators are disabled: • External 1.8V must be supplied to VDDA1.8 and VDD1.8 pins. When the regulators are disabled, VDDA1.8 may be connected to VDD1.8 and a bypass capacitor (0.1μF recommended) should be connected to each pin. • The voltage at VDD3.3 must be at least 2.64V (0.8 * 3.3V) before voltage is applied to VDDA1.8 and VDD1.8. VDD1.8 (V18) N/A N/A 1.8V Digital Supply. Supplied by On-Chip Regulator when REG_EN is active. Low ESR 4.7uF minimum capacitor requirement when using internal regulators. Do not connect VDD1.8 to VDDA1.8 when using internal regulators. When the regulators are disabled, VDD1.8 may be connected to VDD1.8A. VSS (GND) N/A N/A Common Ground. VDDA1.8 (V18A) N/A N/A 1.8V Analog Supply. Supplied by On-Chip Regulator when REG_EN is active. Low ESR 4.7uF minimum capacitor requirement when using internal regulators. Do not connect VDD1.8A to VDD1.8 when using internal regulators. When the regulators are disabled, VDD1.8A may be connected to VDD1.8.  2004 - 2015 Microchip Technology Inc. Description DS00001898A-page 9 USB3280 5.0 LIMITING VALUES TABLE 5-1: ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions MIN TYP MAX Units Maximum DP and DM voltage to Ground VMAX_5V -0.3 5.5 V Maximum VDD1.8 and VDDA1.8 voltage to Ground VMAX_1.8V -0.3 2.5 V Maximum 3.3V Supply Voltage to Ground VMAX_3.3V -0.3 4.0 V Maximum I/O Voltage to Ground VI -0.3 4.0 V Storage Temperature TSTG -55 150 o C ESD PERFORMANCE All Pins VHBM Human Body Model ±5 kV ILTCH_UP EIA/JESD 78, Class II 150 mA LATCH-UP PERFORMANCE All Pins Note: In accordance with the Absolute Maximum Rating system (IEC 60134). TABLE 5-2: RECOMMENDED OPERATING CONDITIONS Parameter Symbol Conditions MIN TYP MAX Units 3.3 3.6 V 3.3V Supply Voltage (VDD3.3 and VDDA3.3) VDD3.3 3.0 Input Voltage on Digital Pins VI 0.0 VDD3.3 V Input Voltage on Analog I/O Pins (DP, DM) VI(I/O) 0.0 VDD3.3 V Ambient Temperature TA -40 85 oC TABLE 5-3: RECOMMENDED EXTERNAL CLOCK CONDITIONS Parameter Symbol Conditions System Clock Frequency XO driven by the external clock; and no connection at XI System Clock Duty Cycle XO driven by the external clock; and no connection at XI DS00001898A-page 10 MIN TYP MAX 24 (±100ppm) 45 50 Units MHz 55 %  2004 - 2015 Microchip Technology Inc. USB3280 6.0 ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS: SUPPLY PINS (Note 6-1) TABLE 6-1: Parameter Symbol Conditions MIN TYP MAX Units Unconfigured Current IAVG(UCFG) Device Unconfigured 55 mA FS Idle Current IAVG(FS) FS idle not data transfer 55 mA FS Transmit Current IAVG(FSTX) FS current during data transmit 60.5 mA FS Receive Current IAVG(FSRX) FS current during data receive 57.5 mA HS Idle Current IAVG(HS) HS idle not data transfer 60.6 mA HS Transmit Current IAVG(HSTX) HS current during data transmit 62.4 mA HS Receive Current IAVG(HSRX) HS current during data receive 61.5 mA Low Power Mode IDD(LPM) VBUS 15kΩ pull-down and 1.5kΩ pull-up resistor currents not included. 83 uA VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40oC to 85oC; unless otherwise specified. Note 6-1 DC ELECTRICAL CHARACTERISTICS: LOGIC PINS (Note 6-2) TABLE 6-2: Parameter Symbol Conditions MIN TYP MAX Units Low-Level Input Voltage VIL VSS 0.8 V High-Level Input Voltage VIH 2.0 VDD3.3 V 0.4 V Low-Level Output Voltage VOL IOL = 8mA High-Level Output Voltage VOH IOH = -8mA Input Leakage Current ILI Pin Capacitance Cpin VDD3.3 - 0.5 V ±1 uA 4 pF VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40oC to 85oC; unless otherwise specified. Note 6-2 TABLE 6-3: DC ELECTRICAL CHARACTERISTICS: ANALOG I/O PINS (DP/DM) (Note 6-3) Parameter Symbol Conditions MIN TYP MAX Units FS FUNCTIONALITY Input levels Differential Receiver Input Sensitivity VDIFS Differential Receiver Common-Mode Voltage VCMFS Single-Ended Receiver Low Level Input Voltage VILSE Single-Ended Receiver High Level Input Voltage VIHSE Single-Ended Receiver Hysteresis VHYSSE | V(DP) - V(DM) | 0.2 0.8 V 2.5 V 0.8 V 2.0 0.050 V 0.150 V 0.3 V Output Levels Low Level Output Voltage VFSOL  2004 - 2015 Microchip Technology Inc. Pull-up resistor on DP; RL = 1.5kΩ to VDD3.3 DS00001898A-page 11 USB3280 DC ELECTRICAL CHARACTERISTICS: ANALOG I/O PINS (DP/DM) (Note 6-3) TABLE 6-3: Parameter Symbol High Level Output Voltage Conditions MIN TYP MAX Units 3.6 V 45 49.5 Ω VFSOH Pull-down resistor on DP, DM; RL = 15kΩ to GND 2.8 Driver Output Impedance for HS and FS ZHSDRV Steady state drive (See Figure 6-1) 40.5 Input Impedance ZINP TX, RPU disabled Pull-up Resistor Impedance ZPU Bus Idle 0.900 1.24 1.575 kΩ Pull-up Resistor Impedance ZPURX Device Receiving 1.425 2.26 3.09 kΩ Termination Voltage For Pull-up Resistor On Pin DP VTERM 3.6 V 500 mV 100 mV Termination 10 MΩ 3.0 HS FUNCTIONALITY Input levels HS Differential Input Sensitivity VDIHS HS Data Signaling Common Mode Voltage Range VCMHS HS Squelch Detection Threshold VHSSQ (Differential) | V(DP) - V(DM) | 100 mV -50 Squelch Threshold Unsquelch Threshold 150 mV Output Levels High Speed Low Level Output Voltage (DP/DM referenced to GND) VHSOL 45Ω load -10 10 mV High Speed High Level Output Voltage (DP/DM referenced to GND) VHSOH 45Ω load 360 440 mV High Speed IDLE Level Output Voltage (DP/DM referenced to GND) VOLHS 45Ω load -10 10 mV Chirp-J Output Voltage (Differential) VCHIRPJ HS termination resistor disabled, pull-up resistor connected. 45Ω load. 700 1100 mV Chirp-K Output Voltage (Differential) VCHIRPK HS termination resistor disabled, pull-up resistor connected. 45Ω load. -900 -500 mV ±1 uA 10 pF Leakage Current OFF-State Leakage Current ILZ Port Capacitance Transceiver Input Capacitance Note 6-3 TABLE 6-4: CIN Pin to GND VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40oC 5 to 85oC; unless otherwise specified. DYNAMIC CHARACTERISTICS: ANALOG I/O PINS (DP/DM) (Note 6-4) Parameter Symbol Conditions MIN TYP MAX Units FS Output Driver Timing Rise Time TFSR CL = 50pF; 10 to 90% of |VOH - VOL| 4 20 ns Fall Time TFFF CL = 50pF; 10 to 90% of |VOH - VOL| 4 20 ns Output Signal Crossover Voltage VCRS Excluding the first transition from IDLE state 1.3 2.0 V DS00001898A-page 12  2004 - 2015 Microchip Technology Inc. USB3280 DYNAMIC CHARACTERISTICS: ANALOG I/O PINS (DP/DM) (CONTINUED)(Note 6-4) TABLE 6-4: Parameter Differential Rise/Fall Time Matching Symbol FRFM Conditions MIN Excluding the first transition from IDLE state 90 TYP MAX Units 111.1 % HS Output Driver Timing Differential Rise Time THSR Differential Fall Time THSF Driver Waveform Requirements 500 ps 500 ps Eye pattern of Template 1 in USB 2.0 specification See Figure 6-2 Receiver Waveform Requirements Eye pattern of Template 4 in USB 2.0 specification See Figure 6-2 Data Source Jitter and Receiver Jitter Tolerance Eye pattern of Template 4 in USB 2.0 specification See Figure 6-2 High Speed Mode Timing Note 6-4 VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40oC to 85oC; unless otherwise specified. DYNAMIC CHARACTERISTICS: DIGITAL UTMI PINS (Note 6-5) TABLE 6-5: Parameter Symbol Conditions MIN TYP MAX Units 5 ns UTMI Timing DATA[7:0] TPD Output Delay. Measured from PHY output to the rising edge of CLKOUT 2 TSU Setup Time. Measured from PHY input to the rising edge of CLKOUT. 5 ns TH Hold time. Measured from the rising edge of CLKOUT to the PHY input signal edge. 0 ns RXVALID RXACTIVE RXERROR LINESTATE[1:0] TXREADY DATA[7:0] TXVALID OPMODE[1:0] XCVRSELECT TERMSELECT DATA[7:0] TXVALID OPMODE[1:0] XCVRSELECT TERMSELECT Note 6-5 VDD3.3 = 3.0 to 3.6V; VSS = 0V; TA = -40oC to 85oC; unless otherwise specified.  2004 - 2015 Microchip Technology Inc. DS00001898A-page 13 USB3280 6.1 Driver Characteristics of Full-Speed Drivers in High-Speed Capable Transceivers The USB3280 uses a differential output driver to drive the USB data signal onto the USB cable. FIGURE 6-1: Full-Speed Driver VOH/IOH Characteristics for High-speed Capable Transceiver on page 14 shows the V/I characteristics for a fullspeed driver which is part of a high-speed capable transceiver. The normalized V/I curve for the driver must fall entirely inside the shaded region. The V/I region is bounded by the minimum driver impedance above (40.5 Ohm) and the maximum driver impedance below (49.5 Ohm). The output voltage must be within 10mV of ground when no current is flowing in or out of the pin. FIGURE 6-1: FULL-SPEED DRIVER VOH/IOH CHARACTERISTICS FOR HIGH-SPEED CAPABLE TRANSCEIVER Drive High Iout (mA) Slope = 1/49.5 Ohm -6.1 * |VOH | Test Limit -10.71 * |VOH| Slope = 1/40.5 Ohm 0 0.566*VOH 0 FIGURE 6-2: 0.698*VOH V OH V out (Volts) FULL-SPEED DRIVER VOL/IOL CHARACTERISTICS FOR HIGH-SPEED CAPABLE TRANSCEIVER Drive Low Iout (mA) Slope = 1/40.5 Ohm Test Limit 10.71 * |VOH| 22 Slope = 1/49.5 Ohm 0 1.09V 0 DS00001898A-page 14 0.434*VOH VOH Vout (Volts)  2004 - 2015 Microchip Technology Inc. USB3280 6.2 High-speed Signaling Eye Patterns High-speed USB signals are characterized using eye patterns. For measuring the eye patterns 4 points have been defined (see Figure 6-3). The Universal Serial Bus Specification Rev.2.0 defines the eye patterns in several ‘templates’. The two templates that are relevant to the PHY are shown below. FIGURE 6-3: EYE PATTERN MEASUREMENT PLANES TP1 TP2 TP3 USB Cable Traces Transceiver TP4 Traces A Connector B Connector Hub Circuit Board Transceiver Device Circuit Board The eye pattern in Figure 6-4 defines the transmit waveform requirements for a hub (measured at TP2 of Figure 6-3) or a device without a captive cable (measured at TP3 of Figure 6-3). The corresponding signal levels and timings are given in table below. Time is specified as a percentage of the unit interval (UI), which represents the nominal bit duration for a 480 Mbit/s transmission rate. FIGURE 6-4: EYE PATTERN FOR TRANSMIT WAVEFORM AND EYE PATTERN DEFINITION Level 1 400mV Differential Point 3 Point 4 0 Volts Differential Point 2 Point 1 Point 5 Point 6 -400mV Differential Level 2 0%  2004 - 2015 Microchip Technology Inc. Unit Interval 100% DS00001898A-page 15 USB3280 Voltage Level (D+, D-) Time (% of Unit Interval) Level 1 525mV in UI following a transition, 475mV in all others N/A Level 2 -525mV in UI following a transition, -475mV in all others N/A Point 1 0V 7.5% UI Point 2 0V 92.5% UI Point 3 300mV 37.5% UI Point 4 300mV 62.5% UI Point 5 -300mV 37.5% UI Point 6 -300mV 62.5% UI The eye pattern in Figure 6-5 defines the receiver sensitivity requirements for a hub (signal applied at test point TP2 of Figure 6-3) or a device without a captive cable (signal applied at test point TP3 of Figure 6-3). The corresponding signal levels and timings are given in the table below. Timings are given as a percentage of the unit interval (UI), which represents the nominal bit duration for a 480 Mbit/s transmission rate. FIGURE 6-5: EYE PATTERN FOR RECEIVE WAVEFORM AND EYE PATTERN DEFINITION Level 1 400mV Differential Point 3 Point 1 Point 5 Point 4 0 Voltｓ Differential Point 2 Point 6 -400mV Differential Level 2 0% 100% Voltage Level (D+, D-) Level 1 575mV Time (% of Unit Interval) N/A Level 2 -575mV N/A Point 1 0V 15% UI Point 2 0V 85% UI Point 3 150mV 35% UI Point 4 150mV 65% UI Point 5 -150mV 35% UI Point 6 -150mV 65% UI DS00001898A-page 16  2004 - 2015 Microchip Technology Inc. USB3280 7.0 FUNCTIONAL OVERVIEW FIGURE 2-1: on page 5 shows the functional block diagram of the USB3280. Each of the functions is described in detail below. 7.1 Modes of Operation The USB3280 supports an 8-bit bi-directional parallel interface. • CLKOUT runs at 60MHz • The 8-bit data bus (DATA[7:0]) is used for transmit when TXVALID = 1 • The 8-bit data bus (DATA[7:0]) is used for receive when TXVALID = 0 7.2 System Clocking This block connects to either an external 24MHz crystal or an external clock source and generates a 480MHz multiphase clock. The clock is used in the CRC block to over-sample the incoming received data, resynchronize the transmit data, and is divided down to 60MHz (CLKOUT) which acts as the system byte clock. The PLL block also outputs a clock valid signal to the other parts of the transceiver when the clock signal is stable. All UTMI signals are synchronized to the CLKOUT output. The behavior of the CLKOUT is as follows: • Produce the first CLKOUT transition no later than 5.6ms after negation of SUSPENDN. The CLKOUT signal frequency error is less than 10% at this time. • The CLKOUT signal will fully meet the required accuracy of ±500ppm no later than 1.4ms after the first transition of CLKOUT. In HS mode there is one CLKOUT cycle per byte time. The frequency of CLKOUT does not change when the PHY is switched between HS to FS modes. In FS mode there are 5 CLKOUT cycles per FS bit time, typically 40 CLKOUT cycles per FS byte time. If a received byte contains a stuffed bit then the byte boundary can be stretched to 45 CLKOUT cycles, and two stuffed bits would result in a 50 CLKOUT cycles. Figure 7-1 shows the relationship between CLKOUT and the transmit data transfer signals in FS mode. TXREADY is only asserted for one CLKOUT per byte time to signal the SIE that the data on the DATA lines has been read by the PHY. The SIE may hold the data on the DATA lines for the duration of the byte time. Transitions of TXVALID must meet the defined setup and hold times relative to CLKOUT. FIGURE 7-1: FS CLK RELATIONSHIP TO TRANSMIT DATA AND CONTROL SIGNALS  2004 - 2015 Microchip Technology Inc. DS00001898A-page 17 USB3280 Figure 7-2 shows the relationship between CLKOUT and the receive data control signals in FS mode. RXACTIVE "frames" a packet, transitioning only at the beginning and end of a packet. However transitions of RXVALID may take place any time 8 bits of data are available. Figure 7-1 also shows how RXVALID is only asserted for one CLKOUT cycle per byte time even though the data may be presented for the full byte time. The XCVRSELECT signal determines whether the HS or FS timing relationship is applied to the data and control signals. FIGURE 7-2: 7.3 FS CLK RELATIONSHIP TO RECEIVE DATA AND CONTROL SIGNALS Clock and Data Recovery Circuit This block consists of the Clock and Data Recovery Circuit and the Elasticity Buffer. The Elasticity Buffer is used to compensate for differences between the transmitting and receiving clock domains. The USB 2.0 specification defines a maximum clock error of ±1000ppm of drift. 7.4 TX Logic This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit operations. These operations include parallel to serial conversion, bit stuffing and NRZI encoding. Upon valid assertion of the proper TX control lines by the SIE and TX State Machine, the TX LOGIC block will synchronously shift, at either the FS or HS rate, the data to the FS/HS TX block to be transmitted on the USB cable. Data transmit timing is shown in Figure 7-3. FIGURE 7-3: TRANSMIT TIMING FOR A DATA PACKET The behavior of the Transmit State Machine is described below. • Asserting a RESET forces the transmit state machine into the Reset state which negates TXREADY. When RESET is negated the transmit state machine will enter a wait state. • The SIE asserts TXVALID to begin a transmission. • After the SIE asserts TXVALID it can assume that the transmission has started when it detects TXREADY has been asserted. DS00001898A-page 18  2004 - 2015 Microchip Technology Inc. USB3280 • The SIE must assume that the USB3280 has consumed a data byte if TXREADY and TXVALID are asserted on the rising edge of CLKOUT. • The SIE must have valid packet information (PID) asserted on the DATA bus coincident with the assertion of TXVALID. • TXREADY is sampled by the SIE on the rising edge of CLKOUT. • The SIE negates TXVALID to complete a packet. Once negated, the transmit logic will never reassert TXREADY until after the EOP has been generated. (TXREADY will not re-assert until TXVALD asserts again. • The USB3280 is ready to transmit another packet immediately, however the SIE must conform to the minimum inter-packet delays identified in the USB 2.0 specification. 7.5 RX Logic This block receives serial data from the CRC block and processes it to be transferred to the SIE on the DATA bus. The processing involved includes NRZI decoding, bit unstuffing, and serial to parallel conversion. Upon valid assertion of the proper RX control lines by the RX State Machine, the RX Logic block will provide bytes to the DATA bus as shown in the figures below. The behavior of the Receive State Machine is described below. FIGURE 7-4: RECEIVE TIMING FOR DATA WITH UNSTUFFED BITS The assertion of RESET will force the Receive State Machine into the Reset state. The Reset state deasserts RXACTIVE and RXVALID. When the RESET signal is deasserted the Receive State Machine enters the RX Wait state and starts looking for a SYNC pattern on the USB. When a SYNC pattern is detected the state machine will enter the Strip SYNC state and assert RXACTIVE. The length of the received Hi-Speed SYNC pattern varies and can be up to 32 bits long or as short as 12 bits long when at the end of five hubs. As a result, the state machine may remain in the Strip SYNC state for several byte times before capturing the first byte of data and entering the RX Data state. After valid serial data is received, the state machine enters the RX Data state, where the data is loaded into the RX Holding Register on the rising edge of CLKOUT and RXVALID is asserted. The SIE must clock the data off the DATA bus on the next rising edge of CLKOUT. If OPMODE = Normal, then stuffed bits are stripped from the data stream. Each time 8 stuffed bits are accumulated the state machine will enter the RX Data Wait state, negating RXVALID thus skipping a byte time. When the EOP is detected the state machine will enter the Strip EOP state and negate RXACTIVE and RXVALID. After the EOP has been stripped the Receive State Machine will reenter the RX Wait state and begin looking for the next packet. The behavior of the Receive State Machine is described below: • • • • • • RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT. In the RX Wait state the receiver is always looking for SYNC. The USB3280 asserts RXACTIVE when SYNC is detected (Strip SYNC state). The USB3280 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty (Strip EOP state). When RXACTIVE is asserted, RXVALID will be asserted if the RX Holding Register is full. RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time. This will occur if 8 stuffed bits have been accumulated.  2004 - 2015 Microchip Technology Inc. DS00001898A-page 19 USB3280 • The SIE must be ready to consume a data byte if RXACTIVE and RXVALID are asserted (RX Data state). • Figure 7-5 shows the timing relationship between the received data (DP/DM), RXVALID, RXACTIVE, RXERROR and DATA signals. Note 1: The USB 2.0 Transceiver does NOT decode Packet ID's (PIDs). They are passed to the SIE for decoding. 2: Figure 7-5, Figure 7-6 and Figure 7-7 are timing examples of a HS/FS PHY when it is in HS mode. When a HS/FS PHY is in FS Mode there are approximately 40 CLKOUT cycles every byte time. The Receive State Machine assumes that the SIE captures the data on the DATA bus if RXACTIVE and RXVALID are asserted. In FS mode, RXVALID will only be asserted for one CLKOUT per byte time. 3: In Figure 7-5, Figure 7-6 and Figure 7-7 the SYNC pattern on DP/DM is shown as one byte long. The SYNC pattern received by a device can vary in length. These figures assume that all but the last 12 bits have been consumed by the hubs between the device and the host controller. FIGURE 7-5: RECEIVE TIMING FOR A HANDSHAKE PACKET (NO CRC) FIGURE 7-6: RECEIVE TIMING FOR SETUP PACKET DS00001898A-page 20  2004 - 2015 Microchip Technology Inc. USB3280 FIGURE 7-7: RECEIVE TIMING FOR DATA PACKET (WITH CRC-16) The receivers connect directly to the USB cable. The block contains a separate differential receiver for HS and FS mode. Depending on the mode, the selected receiver provides the serial data stream through the mulitplexer to the RX Logic block. The FS mode section of the FS/HS RX block also consists of a single-ended receiver on each of the data lines to determine the correct FS LINESTATE. For HS mode support, the FS/HS RX block contains a squelch circuit to insure that noise is never interpreted as data. 7.6 USB 2.0 Transceiver The Microchip Hi-Speed USB 2.0 Transceiver consists of the High Speed and Full Speed Transceivers, and the Termination resistors. 7.6.1 HIGH SPEED AND FULL SPEED TRANSCEIVERS The USB3280 transceiver meets all requirements in the USB 2.0 specification. The receivers connect directly to the USB cable. This block contains a separate differential receiver for HS and FS mode. Depending on the mode, the selected receiver provides the serial data stream through the multiplexer to the RX Logic block. The FS mode section of the FS/HS RX block also consists of a single-ended receiver on each of the data lines to determine the correct FS linestate. For HS mode support, the FS/HS RX block contains a squelch circuit to insure that noise is never interpreted as data. The transmitters connect directly to the USB cable. The block contains a separate differential FS and HS transmitter which receive encoded, bit stuffed, serialized data from the TX Logic block and transmit it on the USB cable. 7.6.2 TERMINATION RESISTORS The USB3280 transceiver fully integrates all of the USB termination resistors. The USB3280 includes the 1.5kΩ pull-up resistor on DP. In addition the 45Ω high speed termination resistors are also integrated. These integrated resistors require no tuning or trimming. The state of the resistors is determined by the operating mode of the PHY. The possible valid resistor combinations are shown in Table 7-1. • RPU_DP_EN activates the 1.5kΩ DP pull-up resistor • HSTERM_EN activates the 45Ω DP and DM high speed termination resistors  2004 - 2015 Microchip Technology Inc. DS00001898A-page 21 USB3280 TABLE 7-1: DP/DM TERMINATION VS. SIGNALING MODE TERMSELECT OPMODE[1:0] RPU_DP_EN HSTERM_EN Resistor Settings XCVRSELECT UTMI+ Interface Settings Tri-State Drivers Xb Xb 01b 0b 0b Power-up 1b 0b 00b 0b 0b Signaling Mode Peripheral Chirp 0b 1b 10b 1b 0b Peripheral HS 0b 0b 00b 0b 1b Peripheral FS 1b 1b 00b 1b 0b Peripheral HS/FS Suspend 1b 1b 00b 1b 0b Peripheral HS/FS Resume 1b 1b 10b 1b 0b Peripheral Test J/Test K 0b 0b 10b 0b 1b 7.6.3 BIAS GENERATOR This block consists of an internal bandgap reference circuit used for generating the high speed driver currents and the biasing of the analog circuits. This block requires an external 12kΩ, 1% tolerance, external reference resistor connected from RBIAS to ground. 7.7 Crystal Oscillator and PLL The USB3280 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference clock that is used by the PHY during both transmit and receive. The USB3280 requires a clean 24MHz crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY may not operate correctly. The USB3280 can use either a crystal or an external clock oscillator for the 24MHz reference. The crystal is connected to the XI and XO pins as shown in the application diagram, Figure 8-9. If a clock oscillator is used the clock should be connected to the XI input and the XO pin left floating. When a external clock is used the XI pin is designed to be driven with a 0 to 3.3 volt signal. When using an external clock the user needs to take care to ensure the external clock source is clean enough to not degrade the high speed eye performance. Once, the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz clock. 7.8 Internal Regulators and POR The USB3280 includes an integrated set of built in power management functions. These power management features include a POR generation and allow the USB3280 to be powered from a single 3.3 volt power supply. This reduces the bill of materials and simplifies product design. 7.8.1 INTERNAL REGULATORS The USB3280 has two integrated 3.3 volt to 1.8 volt regulators. These regulators require an external 4.7uF +/-20% low ESR bypass capacitor to ensure stability. X5R or X7R ceramic capacitors are recommended since they exhibit an ESR lower than 0.1 ohm at frequencies greater than 10kHz. The two regulator outputs, which require bypass capacitors, are the pins labeled VDDA1.8 and VDD1.8. Each pin requires a 4.7uF bypass capacitor placed as close to the pin as possible. Note: The USB3280 regulators are designed to generate a 1.8 volt supply for the USB3280 only. Using the regulators to provide current for other circuits is not recommended and Microchip does not guarantee USB performance or regulator stability. DS00001898A-page 22  2004 - 2015 Microchip Technology Inc. USB3280 7.8.2 POWER ON RESET (POR) The USB3280 provides an internal POR circuit that generates a reset pulse once the PHY supplies are stable. 7.8.3 RESET PIN The UTMI+ Digital can be reset at any time with the RESET pin. The RESET pin of the USB3280 may be asynchronously asserted and de-asserted so long as it is held in the asserted state continuously for a duration greater than one CLKOUT cycle. The RESET input may be asserted when the USB3280 CLKOUT signal is not active (i.e. in the suspend state caused by asserting the SUSPENDN input) but reset must only be de-asserted when the USB3280 CLKOUT signal is active and the RESET has been held asserted for a duration greater than one CKOUT clock cycle. No other PHY digital input signals may change state for two CLKOUT clock cycles after the de-assertion of the reset signal.  2004 - 2015 Microchip Technology Inc. DS00001898A-page 23 USB3280 8.0 APPLICATION NOTES The following sections consist of select functional explanations to aid in implementing the USB3280 into a system. For complete description and specifications consult the USB 2.0 Transceiver Macrocell Interface Specification and Universal Serial Bus Specification Revision 2.0. 8.1 Linestate The voltage thresholds that the LINESTATE[1:0] signals use to reflect the state of DP and DM depend on the state of XCVRSELECT. LINESTATE[1:0] uses HS thresholds when the HS transceiver is enabled (XCVRSELECT = 0) and FS thresholds when the FS transceiver is enabled (XCVRSELECT = 1). There is not a concept of variable single-ended thresholds in the USB 2.0 specification for HS mode. The HS receiver is used to detect Chirp J or K, where the output of the HS receiver is always qualified with the Squelch signal. If squelched, the output of the HS receiver is ignored. In the USB3280, as an alternative to using variable thresholds for the single-ended receivers, the following approach is used. TABLE 8-1: LINESTATE STATES State of DP/DM Lines LINESTATE[1:0] Full Speed XCVRSELECT =1 TERMSELECT=1 High Speed XCVRSELECT =0 TERMSELECT=0 Chirp Mode XCVRSELECT =0 TERMSELECT=1 LS[1] LS[0] 0 0 SE0 Squelch Squelch 0 1 J !Squelch !Squelch & HS Differential Receiver Output 1 0 K Invalid !Squelch & !HS Differential Receiver Output 1 1 SE1 Invalid Invalid In HS mode, 3ms of no USB activity (IDLE state) signals a reset. The SIE monitors LINESTATE[1:0] for the IDLE state. To minimize transitions on LINESTATE[1:0] while in HS mode, the presence of !Squelch is used to force LINESTATE[1:0] to a J state. DS00001898A-page 24  2004 - 2015 Microchip Technology Inc. USB3280 8.2 OPMODES The OPMODE[1:0] pins allow control of the operating modes. TABLE 8-2: OPERATIONAL MODES Mode[1:0] State# State Name Description 00 0 Normal Operation Transceiver operates with normal USB data encoding and decoding 01 1 Non-Driving Allows the transceiver logic to support a soft disconnect feature which tri-states both the HS and FS transmitters, and removes any termination from the USB making it appear to an upstream port that the device has been disconnected from the bus 10 2 Disable Bit Stuffing and NRZI encoding Disables bitstuffing and NRZI encoding logic so that 1's loaded from the DATA bus become 'J's on the DP/DM and 0's become 'K's 11 3 Reserved N/A The OPMODE[1:0] signals are normally changed only when the transmitter and the receiver are quiescent, i.e. when entering a test mode or for a device initiated resume. When using OPMODE[1:0] = 10 (state 2), OPMODES are set, and then 5 60MHz clocks later, TXVALID is asserted. In this case, the SYNC and EOP patterns are not transmitted. The only exception to this is when OPMODE[1:0] is set to state 2 while TXVALID has been asserted (the transceiver is transmitting a packet), in order to flag a transmission error. In this case, the USB3280 has already transmitted the SYNC pattern so upon negation of TXVALID the EOP must also be transmitted to properly terminate the packet. Changing the OPMODE[1:0] signals under all other conditions, while the transceiver is transmitting or receiving data will generate undefined results. Under no circumstances should the device controller change OPMODE while the DP/DM lines are still transmitting or unpredictable changes on DP/DM are likely to occur. The same applies for TERMSELECT and XCVRSELECT. 8.3 Test Mode Support TABLE 8-3: USB 2.0 TEST MODES USB3280 Setup USB 2.0 Test Modes 8.4 Operational Mode SIE Transmitted Data XCVRSELECT & TERMSELECT SE0_NAK State 0 No transmit HS J State 2 All '1's HS K State 2 All '0's HS Test_Packet State 0 Test Packet data HS SE0 Handling For FS operation, IDLE is a J state on the bus. SE0 is used as part of the EOP or to indicate reset. When asserted in an EOP, SE0 is never asserted for more than 2 bit times. The assertion of SE0 for more than 2.5us is interpreted as a reset by the device operating in FS mode. For HS operation, IDLE is a SE0 state on the bus. SE0 is also used to reset a HS device. A HS device cannot use the 2.5us assertion of SE0 (as defined for FS operation) to indicate reset since the bus is often in this state between packets. If no bus activity (IDLE) is detected for more than 3ms, a HS device must determine whether the downstream facing port is signaling a suspend or a reset. The following section details how this determination is made. If a reset is signaled, the HS device will then initiate the HS Detection Handshake protocol.  2004 - 2015 Microchip Technology Inc. DS00001898A-page 25 USB3280 8.5 Reset Detection If a device in HS mode detects bus inactivity for more than 3ms (T1), it reverts to FS mode. This enables the FS pull-up on the DP line in an attempt to assert a continuous FS J state on the bus. The SIE must then check LINESTATE for the SE0 condition. If SE0 is asserted at time T2, then the upstream port is forcing the reset state to the device (i.e., a Driven SE0). The device will then initiate the HS detection handshake protocol. FIGURE 8-1: TABLE 8-4: RESET TIMING BEHAVIOR (HS MODE) RESET TIMING VALUES (HS MODE) Timing Parameter Description HS Reset T0 Bus activity ceases, signaling either a reset or a SUSPEND. 0 (reference) T1 Earliest time at which the device may place itself in FS mode after bus activity stops. HS Reset T0 + 3. 0ms < T1 < HS Reset T0 + 3.125ms T2 SIE samples LINESTATE. If LINESTATE = T1 + 100µs < T2 < SE0, then the SE0 on the bus is due to a Reset T1 + 875µs state. The device now enters the HS Detection Handshake protocol. DS00001898A-page 26 Value  2004 - 2015 Microchip Technology Inc. USB3280 8.6 Suspend Detection If a HS device detects SE0 asserted on the bus for more than 3ms (T1), it reverts to FS mode. This enables the FS pullup on the DP line in an attempt to assert a continuous FS J state on the bus. The SIE must then check LINESTATE for the J condition. If J is asserted at time T2, then the upstream port is asserting a soft SE0 and the USB is in a J state indicating a suspend condition. By time T4 the device must be fully suspended. FIGURE 8-2: TABLE 8-5: SUSPEND TIMING BEHAVIOR (HS MODE) SUSPEND TIMING VALUES (HS MODE) Timing Parameter Description HS Reset T0 End of last bus activity, signaling either a reset or a SUSPEND. Value 0 (reference) T1 The time at which the device must place itself in HS Reset T0 + 3. 0ms < T1 < HS Reset T0 FS mode after bus activity stops. + 3.125ms T2 SIE samples LINESTATE. If LINESTATE = 'J', then the initial SE0 on the bus (T0 - T1) had been due to a Suspend state and the SIE remains in HS mode. T1 + 100 µs < T2 < T1 + 875µs T3 The earliest time where a device can issue Resume signaling. HS Reset T0 + 5ms T4 The latest time that a device must actually be suspended, drawing no more than the suspend current from the bus. HS Reset T0 + 10ms  2004 - 2015 Microchip Technology Inc. DS00001898A-page 27 USB3280 8.7 HS Detection Handshake The High Speed Detection Handshake process is entered from one of three states: suspend, active FS or active HS. The downstream facing port asserting an SE0 state on the bus initiates the HS Detection Handshake. Depending on the initial state, an SE0 condition can be asserted from 0 to 4 ms before initiating the HS Detection Handshake. These states are described in the USB 2.0 specification. There are three ways in which a device may enter the HS Handshake Detection process: 1. 2. 3. If the device is suspended and it detects an SE0 state on the bus it may immediately enter the HS handshake detection process. If the device is in FS mode and an SE0 state is detected for more than 2.5µs. it may enter the HS handshake detection process. If the device is in HS mode and an SE0 state is detected for more than 3.0ms. it may enter the HS handshake detection process. In HS mode, a device must first determine whether the SE0 state is signaling a suspend or a reset condition. To do this the device reverts to FS mode by placing XCVRSELECT and TERMSELECT into FS mode. The device must not wait more than 3.125ms before the reversion to FS mode. After reverting to FS mode, no less than 100µs and no more than 875µs later the SIE must check the LINESTATE signals. If a J state is detected the device will enter a suspend state. If an SE0 state is detected, then the device will enter the HS Handshake detection process. In each case, the assertion of the SE0 state on the bus initiates the reset. The minimum reset interval is 10ms. Depending on the previous mode that the bus was in, the delay between the initial assertion of the SE0 state and entering the HS Handshake detection can be from 0 to 4ms. This transceiver design pushes as much of the responsibility for timing events on to the SIE as possible, and the SIE requires a stable CLKOUT signal to perform accurate timing. In case 2 and 3 above, CLKOUT has been running and is stable, however in case 1 the USB3280 is reset from a suspend state, and the internal oscillator and clocks of the transceiver are assumed to be powered down. A device has up to 6ms after the release of SUSPENDN to assert a minimum of a 1ms Chirp K. DS00001898A-page 28  2004 - 2015 Microchip Technology Inc. USB3280 8.8 HS Detection Handshake – FS Downstream Facing Port Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The DP pull-up is asserted and the HS terminations are disabled. The SIE then sets OPMODE to Disable Bit Stuffing and NRZI encoding, XCVRSELECT to HS mode, and begins the transmission of all 0's data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp sequence from the host port. If the downstream facing port is not HS capable, then the HS K asserted by the device is ignored and the alternating sequence of HS Chirp K’s and J’s is not generated. If no chirps are detected (T4) by the device, it will enter FS mode by returning XCVRSELECT to FS mode. FIGURE 8-3: TABLE 8-6: HS DETECTION HANDSHAKE TIMING BEHAVIOR (FS MODE) HS DETECTION HANDSHAKE TIMING VALUES (FS MODE) Timing Parameter Description Value T0 HS Handshake begins. DP pull-up enabled, HS terminations disabled. 0 (reference) T1 Device enables HS Transceiver and asserts Chirp K T0 < T1 < HS Reset T0 + 6.0ms on the bus. T2 Device removes Chirp K from the bus. 1ms minimum width. T1 + 1.0 ms < T2 < HS Reset T0 + 7.0ms T3 Earliest time when downstream facing port may assert Chirp KJ sequence on the bus. T2 < T3 < T2+100µs T4 Chirp not detected by the device. Device reverts to FS default state and waits for end of reset. T2 + 1.0ms < T4 < T2 + 2.5ms T5 Earliest time at which host port may end reset HS Reset T0 + 10ms Note 1: T0 may occur to 4ms after HS Reset T0. 2: The SIE must assert the Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration.  2004 - 2015 Microchip Technology Inc. DS00001898A-page 29 USB3280 8.9 HS Detection Handshake – HS Downstream Facing Port Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The DP pull-up is asserted and the HS terminations are disabled. The SIE then sets OPMODE to Disable Bit Stuffing and NRZI encoding, XCVRSELECT to HS mode, and begins the transmission of all 0's data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp sequence from the downstream facing port. If the downstream facing port is HS capable then it will begin generating an alternating sequence of Chirp K’s and Chirp J’s (T3) after the termination of the chirp from the device (T2). After the device sees the valid chirp sequence Chirp K-J-K-J-K-J (T6), it will enter HS mode by setting TERMSELECT to HS mode (T7). Figure 8-4 provides a state diagram for Chirp K-J-K-J-K-J validation. Prior to the end of reset (T9) the device port must terminate the sequence of Chirp K’s and Chirp J’s (T8) and assert SE0 (T8-T9). Note that the sequence of Chirp K’s and Chirp J’s constitutes bus activity. FIGURE 8-4: CHIRP K-J-K-J-K-J SEQUENCE DETECTION STATE DIAGRAM Start Chirp K-J-K-J-K-J detection !K Chirp Invalid K State Chirp Count =0 Detect K? INC Chirp Count SE0 Chirp Count != 6 & !SE0 !J Chirp Count J State Detect J? INC Chirp Count Chirp Valid Chirp Count != 6 & !SE0 The Chirp K-J-K-J-K-J sequence occurs too slow to propagate through the serial data path, therefore LINESTATE signal transitions must be used by the SIE to step through the Chirp K-J-K-J-K-J state diagram, where "K State" is equivalent to LINESTATE = K State and "J State" is equivalent to LINESTATE = J State. The SIE must employ a counter (Chirp Count) to count the number of Chirp K and Chirp J states. Note that LINESTATE does not filter the bus signals so the requirement that a bus state must be "continuously asserted for 2.5µs" must be verified by the SIE sampling the LINESTATE signals. DS00001898A-page 30  2004 - 2015 Microchip Technology Inc. USB3280 FIGURE 8-5: TABLE 8-7: HS DETECTION HANDSHAKE TIMING BEHAVIOR (HS MODE) RESET TIMING VALUES Timing Parameter T0 Description Value HS Handshake begins. DP pull-up enabled, HS terminations disabled. 0 (reference) T1 Device asserts Chirp K on the bus. T0 < T1 < HS Reset T0 + 6.0ms T2 Device removes Chirp K from the bus. 1 ms minimum T0 + 1.0ms < T2 < width. HS Reset T0 + 7.0ms T3 Downstream facing port asserts Chirp K on the bus. T2 < T3 < T2+100µs T4 Downstream facing port toggles Chirp K to Chirp J on T3 + 40µs < T4 < T3 + 60µs the bus. T5 Downstream facing port toggles Chirp J to Chirp K on T4 + 40µs < T5 < T4 + 60µs the bus. T6 Device detects downstream port chirp. T6 T7 Chirp detected by the device. Device removes DP pull-up and asserts HS terminations, reverts to HS default state and waits for end of reset. T6 < T7 < T6 + 500µs T8 Terminate host port Chirp K-J sequence (Repeating T4 and T5) T9 - 500µs < T8 < T9 - 100µs T9 The earliest time at which host port may end reset. HS Reset T0 + 10ms The latest time, at which the device may remove the DP pull-up and assert the HS terminations, reverts to HS default state. Note 1: T0 may be up to 4ms after HS Reset T0. 2: The SIE must use LINESTATE to detect the downstream port chirp sequence. 3: Due to the assertion of the HS termination on the host port and FS termination on the device port, between T1 and T7 the signaling levels on the bus are higher than HS signaling levels and are less than FS signaling levels.  2004 - 2015 Microchip Technology Inc. DS00001898A-page 31 USB3280 8.10 HS Detection Handshake – Suspend Timing If reset is entered from a suspended state, the internal oscillator and clocks of the transceiver are assumed to be powered down. Figure 8-6 shows how CLKOUT is used to control the duration of the chirp generated by the device. When reset is entered from a suspended state (J to SE0 transition reported by LINESTATE), SUSPENDN is combinatorially negated at time T0 by the SIE. It takes approximately 5 milliseconds for the transceiver's oscillator to stabilize. The device does not generate any transitions of the CLKOUT signal until it is "usable" (where "usable" is defined as stable to within ±10% of the nominal frequency and the duty cycle accuracy 50±5%). The first transition of CLKOUT occurs at T1. The SIE then sets OPMODE to Disable Bit Stuffing and NRZI encoding, XCVRSELECT to HS mode, and must assert a Chirp K for 66000 CLKOUT cycles to ensure a 1ms minimum duration. If CLKOUT is 10% fast (66MHz) then Chirp K will be 1.0ms. If CLKOUT is 10% slow (54 MHz) then Chirp K will be 1.2ms. The 5.6ms requirement for the first CLKOUT transition after SUSPENDN, ensures enough time to assert a 1ms Chirp K and still complete before T3. Once the Chirp K is completed (T3) the SIE can begin looking for host chirps and use CLKOUT to time the process. At this time, the device follows the same protocol as in Section 8.9, "HS Detection Handshake – HS Downstream Facing Port" for completion of the High Speed Handshake. FIGURE 8-6: HS DETECTION HANDSHAKE TIMING BEHAVIOR FROM SUSPEND T0 T1 T2 T3 T4 time OPMODE 0 OPMODE 1 XCVRSELECT TERMSELECT SUSPENDN TXVALID CLK60 DP/DM J SE0 CLK power up time Device Chirp K Look for host chirps To detect the assertion of the downstream Chirp K's and Chirp J's for 2.5us {TFILT}, the SIE must see the appropriate LINESTATE signals asserted continuously for 165 CLKOUT cycles. DS00001898A-page 32  2004 - 2015 Microchip Technology Inc. USB3280 TABLE 8-8: HS DETECTION HANDSHAKE TIMING VALUES FROM SUSPEND Timing Parameter 8.11 Description Value T0 While in suspend state an SE0 is detected on the USB. HS Handshake begins. D+ pull-up enabled, HS terminations disabled, SUSPENDN negated. 0 (HS Reset T0) T1 First transition of CLKOUT. CLKOUT "Usable" (frequency accurate to ±10%, duty cycle accurate to 50±5). T0 < T1 < T0 + 5.6ms T2 Device asserts Chirp K on the bus. T1 < T2 < T0 + 5.8ms T3 Device removes Chirp K from the bus. (1 ms minimum width) and begins looking for host chirps. T2 + 1.0 ms < T3 < T0 + 7.0 ms T4 CLK "Nominal" (CLKOUT is frequency accurate to ±500 ppm, T1 < T3 < T0 + 20.0ms duty cycle accurate to 50±5). Assertion of Resume In this case, an event internal to the device initiates the resume process. A device with remote wake-up capability must wait for at least 5ms after the bus is in the idle state before sending the remote wake-up resume signaling. This allows the hubs to get into their suspend state and prepare for propagating resume signaling. The device has 10ms where it can draw a non-suspend current before it must drive resume signaling. At the beginning of this period the SIE may negate SUSPENDN, allowing the transceiver (and its oscillator) to power up and stabilize. Figure 8-7 illustrates the behavior of a device returning to HS mode after being suspended. At T4, a device that was previously in FS mode would maintain TERMSELECT and XCVRSELECT high. To generate resume signaling (FS 'K') the device is placed in the "Disable Bit Stuffing and NRZI encoding" Operational Mode (OPMODE [1:0] = 10), TERMSELECT and XCVRSELECT must be in FS mode, TXVALID asserted, and all 0's data is presented on the DATA bus for at least 1ms (T1 - T2). FIGURE 8-7: RESUME TIMING BEHAVIOR (HS MODE)  2004 - 2015 Microchip Technology Inc. DS00001898A-page 33 USB3280 TABLE 8-9: RESUME TIMING VALUES (HS MODE) Timing Parameter 8.12 Description Value T0 Internal device event initiating the resume process 0 (reference) T1 Device asserts FS 'K' on the bus to signal resume T0 < T1 < T0 + 10ms. request to downstream port T2 The device releases FS 'K' on the bus. However by this time the 'K' state is held by downstream port. T1 + 1.0ms < T2 < T1 + 15ms T3 Downstream port asserts SE0. T1 + 20ms T4 Latest time at which a device, which was previously in HS mode, must restore HS mode after bus activity stops. T3 + 1.33µs {2 Low-speed bit times} Detection of Resume Resume signaling always takes place in FS mode (TERMSELECT and XCVRSELECT = FS enabled), so the behavior for a HS device is identical to that of a FS device. The SIE uses the LINESTATE signals to determine when the USB transitions from the 'J' to the 'K' state and finally to the terminating FS EOP (SE0 for 1.25us-1.5µs.). The resume signaling (FS 'K') will be asserted for at least 20ms. At the beginning of this period the SIE may negate SUSPENDN, allowing the transceiver (and its oscillator) to power up and stabilize. The FS EOP condition is relatively short. SIEs that simply look for an SE0 condition to exit suspend mode do not necessarily give the transceiver’s clock generator enough time to stabilize. It is recommended that all SIE implementations key off the 'J' to 'K' transition for exiting suspend mode (SUSPENDN = 1). And within 1.25µs after the transition to the SE0 state (low-speed EOP) the SIE must enable normal operation, i.e. enter HS or FS mode depending on the mode the device was in when it was suspended. If the device was in FS mode: then the SIE leaves the FS terminations enabled. After the SE0 expires, the downstream port will assert a J state for one low-speed bit time, and the bus will enter a FS Idle state (maintained by the FS terminations). If the device was in HS mode: then the SIE must switch to the FS terminations before the SE0 expires (< 1.25µs). After the SE0 expires, the bus will then enter a HS IDLE state (maintained by the HS terminations). 8.13 HS Device Attach Figure 8-8 demonstrates the timing of the USB3280 control signals during a device attach event. When a HS device is attached to an upstream port, power is asserted to the device and the device sets XCVRSELECT and TERMSELECT to FS mode (time T1). VBUS is the +5V power available on the USB cable. Device Reset in Figure 8-8 indicates that VBUS is within normal operational range as defined in the USB 2.0 specification. The assertion of Device Reset (T0) by the upstream port will initialize the device. By monitoring LINESTATE, the SIE state machine knows to set the XCVRSELECT and TERMSELECT signals to FS mode (T1). The standard FS technique of using a pull-up resistor on DP to signal the attach of a FS device is employed. The SIE must then check the LINESTATE signals for SE0. If LINESTATE = SE0 is asserted at time T2 then the upstream port is forcing the reset state to the device (i.e. Driven SE0). The device will then reset itself before initiating the HS Detection Handshake protocol. DS00001898A-page 34  2004 - 2015 Microchip Technology Inc. USB3280 FIGURE 8-8: TABLE 8-10: DEVICE ATTACH BEHAVIOR ATTACH AND RESET TIMING VALUES Timing Parameter Description Value T0 Vbus Valid. T1 Maximum time from Vbus valid to when the device must T0 + 100ms < T1 signal attach. T2 (HS Reset T0) Debounce interval. The device now enters the HS Detection Handshake protocol.  2004 - 2015 Microchip Technology Inc. 0 (reference) T1 + 100ms < T2 DS00001898A-page 35 USB3280 8.14 Application Diagram FIGURE 8-9: USB3280 APPLICATION DIAGRAM UTMI TXVALID TXREADY RXACTIVE RXVALID RXERROR 26 25 24 23 22 21 20 19 DATA 0 DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 DATA 6 DATA 7 5 3 11 27 28 1 XCVRSELECT 2 TERMSELECT 4 SUSPENDN 6 RESET 13 OPMODE 0 12 OPMODE 1 16 LINESTATE 0 15 LINESTATE 1 CLKOUT USB C LOAD 24 MHz Crystal 32 XI RBIAS DP 14 36 8 12KΩ 1ΜΩ 31 USB-B XO DM 9 C LOAD POWER 33 VDDA1.8 4.7uF Ceramic 17 VDD1.8 30 VDD1.8 4.7uF Ceramic 7 34 VDD3.3 35 VDD3.3 REG_EN 4.7uF Ceramic 0.1uF and/or 0.01uF ceramic capacitors are also required on power supply pins. DS00001898A-page 36 VSS Exposed Pad 10 VDD3.3 18 VDD3.3 29 VDD3.3 VDD3.3 GND  2004 - 2015 Microchip Technology Inc. USB3280 9.0 PACKAGE OUTLINE USB3280-AEZG 36-PIN QFN PACKAGE OUTLINE AND PARAMETERS, 6 X 6 X 0.90 MM BODY (ROHS COMPLIANT) Note: For the most current package drawings, see the Microchip Packaging Specification at http://www.microchip.com/packaging FIGURE 9-1:  2004 - 2015 Microchip Technology Inc. DS00001898A-page 37 USB3280 FIGURE 9-2: DS00001898A-page 38 QFN, 6X6 TAPE & REEL  2004 - 2015 Microchip Technology Inc. USB3280 EXAMPLE 9-1: Note: REEL DIMENSIONS Standard reel size is 3000 pieces per reel.  2004 - 2015 Microchip Technology Inc. DS00001898A-page 39 USB3280 APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision DS00001898A (03-06-15) DS00001898A-page 40 Section/Figure/Entry Correction Replaces previous SMSC version Rev. 1.5 (11-15-07)  2004 - 2015 Microchip Technology Inc. USB3280 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://www.microchip.com/support  2004 - 2015 Microchip Technology Inc. DS00001898A-page 41 USB3280 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. - Device Device: Package: Tape and Reel Option: XXX Package - [X] Tape and Reel Option USB3280 Examples: • USB3280-AEZG = 36-pin QFN RoHS Compliant Package • USB3280-AEZG-TR = 36-pin QFN RoHS Compliant Package Tape & Reel AEZG = 36-pin QFN Blank TR DS00001898A-page 42 = Tray packaging = Tape and Reel (1) Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Reel size is 3,000 pieces.  2004 - 2015 Microchip Technology Inc. USB3280 Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2004 - 2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 9781632771032 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 ==  2004 - 2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS00001898A-page 43 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2943-5100 Fax: 852-2401-3431 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Germany - Dusseldorf Tel: 49-2129-3766400 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 Austin, TX Tel: 512-257-3370 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Dongguan Tel: 86-769-8702-9880 China - Hangzhou Tel: 86-571-8792-8115 Fax: 86-571-8792-8116 India - Pune Tel: 91-20-3019-1500 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Detroit Novi, MI Tel: 248-848-4000 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Houston, TX Tel: 281-894-5983 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Kaohsiung Tel: 886-7-213-7828 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Canada - Toronto Tel: 905-673-0699 Fax: 905-673-6509 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Pforzheim Tel: 49-7231-424750 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Venice Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Poland - Warsaw Tel: 48-22-3325737 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 01/27/15  2004 - 2015 Microchip Technology Inc. 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