VSC8211XVW

VSC8211 Datasheet Single Port 10/100/1000BASE-T, 1000BASE-X, and 100BASE-FX PHY 1 General Description Ideally suited for Gigabit uplinks on Fast Ethernet switches, Fiber Optics, Media Converter applications, and GBIC/SFP modules, Vitesse's industry-leading low power VSC8211 integrates a high-performance 1.25Gbps SerDes and a triple speed (10/100/1000BASE-T) transceiver, providing unmatched tolerance to noise and cable plant imperfections. Consuming approximately 700mW, the device requires only 3.3V and 1.2V power supplies. To further minimize system complexity and cost, the VSC8211's twisted pair interface features fully integrated line terminations, exceptionally low EMI, and robust Cable Sourced ESD (CESD) performance. The VSC8211 provides systems designers with maximum design flexibility, offering direct connectivity to virtually any parallel or serial MAC, optical module, or triple speed GBIC/ SFP connector. In addition to the familiar parallel MAC side interfaces (GMII, RGMII, MII, TBI, and RTBI), the device features two serial interfaces to minimize signal overhead: a 1000BASE-X compliant SerDes and SGMII. In 1000BASE-X SerDes mode, the VSC8211 may be used to connect a MAC either to copper media (MAC to Cat-5) or to a 1000BASE-X optical module (MAC-to-Optics). In SGMII mode, the VSC8211 provides a fully compliant, 4 or 6-pin interface to MACs. The 1000BASE-X SerDes and SGMII interfaces offer either automatic or user-controlled auto-negotiation priority resolution between the 1000BASE-X and 1000BASE-T autonegotiation processes. A single chip copper to optics Media Converter can be easily implemented by simultaneous use of the SerDes and Cat-5 media interfaces. This device also supports 100BASE-FX over its copper media interface. To minimize power consumption, the VSC8211 offers several programmable power management modes meeting all Wakeon-LAN requirements. The device also supports Vitesse's comprehensive VeriPHY® Cable Diagnostics, offering the system manufacturer and IT administrator with a complete suite of cable plant diagnostics to simplify the manufacture, installation and management of Gigabit-over-copper networks. 2 Features and Benefits Features Benefits • Very low power consumption • Reduces power supply costs • Supports PICMG 2.16 and 3.0 Ethernet backplanes at approximately 500mW • Lowest power mode reduces power supply costs • Patented line driver with integrated line side termination resistors • Allows use of simpler magnetic modules with up to 50% cost savings versus competition • Saves over 12 components per port and reduces PCB area & cost by fifty percent • Serial: • Flexible MAC interfaces: Serial: SGMII & SerDes Parallel: RGMII & RTBI (2.5V & 3.3V) GMII, MII, TBI • Connects to serial MACs or optical modules Supports copper GBIC/SFP modules Parallel: Connects to virtually any MAC controller • User-programmable RGMII timing compensation • Simplifies PCB layout, eliminating PCB trombones • High performance 1.25Gbps SerDes • Supports CAT-5, fiber optic, and backplane interfaces from a single device • Suitable for dual media (copper & fiber optics) switch ports, Gigabit uplinks on Fast Ethernet switches, GBICs/ SFPs, LOM • Single chip solution for flexible media support • Auto-media Sense detects and configures to support fiber or copper VMDS-10105 Revision 4.1 © VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012 Tel: (800) VITESSE • FAX: (805) 987-5896 • E-mail: prodinfo@vitesse.com October 2006 Internet: www.vitesse.com 1 of 165 VSC8211 Datasheet Features Benefits • User-configurable copper or fiber link selection preference with programmable interrupt and signal detect I/O pins • Ensures plug-n-play link configuration when connected to any copper, fiber, or backplane link partner • Compliant with IEEE 802.3 (10BASE-T, 100BASE-TX, 1000BASE-T, 1000BASE-X, 100BASE-FX) and SFP MSA specifications • Ensures seamless deployment throughout copper and optical networks with industry’s highest tolerance to noise and substandard cable plants • Over 150m of Category-5 reach with industry’s highest noise tolerance • Ensures trouble-free deployment in real world Ethernet networks • Several flexible power management modes • Reduces power consumption and system costs; fully compliant with Wake-on-LAN requirements • Small footprint 10mm x 14mm, 117-LBGA package • Suitable for Gigabit switch ports, GBICs/SFPs, media converters 3 Applications • Dual Media Switch Ports • Triple-speed GBIC/SFP modules • iSCSI and TOE LOM • Backplanes • Media Converters 2 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 4 Application Diagrams 10/100/1000 Mbps Ethernet MAC GMIII / MII, RGMII, TBI, RTBI MDC, MDIO 3.3 V 1.2 V Quad Transformer Module VSC8211 RJ-45 Cat-5 UTP 10/100/1000BASE-T Station Manager 1000BASE-LX 1000BASE-SX Optical Module SerDes I/F Single mode Fiber Multi-mode Fiber Backplane Figure 1. Parallel MAC to Cat-5, Fiber Optics, or Backplanes 3.3 V 10/100/1000 Mbps Ethernet MAC 1.2 V Serial I/F MDC, MDIO Quad Transformer Module VSC8211 RJ-45 Cat-5 UTP 10/100/1000BASE-T Station Manager 1000BASE-LX 1000BASE-SX Optical Module SerDes I/F Single mode Fiber Multi-mode Fiber Backplane Figure 2. Serial MAC to Cat-5, Fiber Optics, or Backplanes 3.3 V 1.2 V SGMII or 802.3z SerDes GBIC/SFP Interface SerDes I/F Optional I/F for Configuration Quad Transformer Module VSC8211 RJ-45 Optional EEPROM Figure 3. GBIC/SFP Serial Interface (SGMII or 802.3z SerDes to Cat-5) 3 of 165 VMDS-10105 Revision 4.1 October 2006 Cat-5 UTP 10/100/1000BASE-T VSC8211 Datasheet 3.3 V 1.2 V Single mode Fiber Multi-mode Fiber 1000BASE-LX SerDes I/F 1000BASE-SX Optical Module Optional I/F for Configuration Quad Transformer Module VSC8211 Optional EEPROM Figure 4. Media Converter (1000BASE-X to Cat-5) 4 of 165 VMDS-10105 Revision 4.1 October 2006 RJ-45 Cat-5 UTP 1000BASE-T VSC8211 Datasheet Contents 1 General Description .........................................................................................................................................................1 2 Features and Benefits .....................................................................................................................................................1 3 Applications ......................................................................................................................................................................2 4 Application Diagrams ......................................................................................................................................................3 5 Relevant Specifications & Documentation ............................................................................................................... 14 6 Datasheet Conventions ................................................................................................................................................ 15 7 Document History and Notices ................................................................................................................................... 16 8 Device Block Diagram .................................................................................................................................................. 17 9 Package Pin Assignments & Signal Descriptions .................................................................................................. 18 9.1 VSC8211 117-Ball LBGA Package Ball Diagram ............................................................................... 18 9.2 LBGA Ball to Signal Name Cross Reference ..................................................................................... 19 9.3 Signal Type Description ...................................................................................................................... 20 9.4 Detailed Pin Descriptions ................................................................................................................... 21 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.4.7 9.4.8 9.4.9 9.4.10 9.4.11 9.4.12 9.4.13 9.5 10 Configuration and Control Signals ........................................................................................................21 System Clock Interface Signals (SCI) ..................................................................................................22 Analog Bias Signals ...............................................................................................................................23 JTAG Access Port .................................................................................................................................23 Serial Management Interface Signals ..................................................................................................24 EEPROM Interface Signals ..................................................................................................................25 LED Interface Signals ............................................................................................................................25 Parallel MAC Interface Signals - Transmit Signals ..............................................................................26 Parallel MAC Interface Signals - Receive Signals ...............................................................................28 Serial MAC/Media Interface Signals .....................................................................................................30 Twisted Pair Interface Signals ...............................................................................................................33 Power Supply and Ground Connections .............................................................................................34 No Connects ..........................................................................................................................................34 Power Supply and Associated Functional Signals ............................................................................. 35 System Schematics ...................................................................................................................................................... 36 10.1 Parallel Data MAC to CAT5 Media PHY Operating Mode .................................................................. 36 10.2 Parallel Data MAC to 1000Mbps Fiber Media PHY Operating Mode ................................................. 37 10.3 Parallel Data MAC to Copper/Fiber Auto Media Sense PHY Operating Mode .................................. 38 10.4 SGMII/802.3z SerDes MAC to CAT5 Media PHY Operating Mode ................................................... 39 10.5 SGMII/802.3z SerDes to 1000Mbps Fiber Media PHY Operating Mode ............................................ 40 10.6 100Mbps Fiber Media Implementation ............................................................................................... 41 10.7 Serial MAC to Fiber/CAT5 Media PHY Operating Mode .................................................................... 42 5 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 11 Twisted Pair Interface ................................................................................................................................................... 43 11.1 Twisted Pair Autonegotiation (IEEE802.3 Clause 28) ........................................................................ 43 11.2 Twisted Pair Auto MDI/MDI-X Function .............................................................................................. 44 11.3 Auto MDI/MDI-X in Forced 10/100 Link Speeds ................................................................................. 44 11.4 Twisted Pair Link Speed Downshift .................................................................................................... 45 11.5 100Mbps Fiber Support Over Copper Media Interface ....................................................................... 45 11.5.1 Register Settings ....................................................................................................................................45 12 Transformerless Operation for PICMG 2.16 and 3.0 IP-based Backplanes ........................................................ 45 13 Dual Mode Serial Management Interface (SMI) ........................................................................................................ 45 13.1 PHY Register Access with SMI in MSA mode .................................................................................... 46 13.1.1 13.1.2 13.1.3 13.1.4 Write Operation - Random Write ..........................................................................................................48 Write Operation - Sequential Write .......................................................................................................49 Read Operation - Random Read .........................................................................................................50 Read Operation - Sequential Read ......................................................................................................51 13.2 PHY Register Access with SMI in IEEE Mode ................................................................................... 52 13.3 SMI Interrupt ....................................................................................................................................... 53 14 LED Interface .................................................................................................................................................................. 54 14.1 Serial LED Output ............................................................................................................................... 56 15 Test Mode Interface (JTAG) ......................................................................................................................................... 57 15.1 Supported Instructions and Instruction Codes .................................................................................... 58 15.2 Boundary-Scan Register Cell Order ................................................................................................... 59 16 Enhanced ActiPHY Power Management ................................................................................................................... 60 16.1 Operation in Enhanced ActiPHY Mode .............................................................................................. 60 16.2 Low power state ................................................................................................................................. 61 16.3 LP Wake up state ............................................................................................................................... 61 16.4 Normal operating state ....................................................................................................................... 61 17 Ethernet In-line Powered Device Support ................................................................................................................. 62 17.1 Cisco In-Line Powered Device Detection ........................................................................................... 62 17.2 In-Line Power Ethernet Switch Diagram ............................................................................................. 62 17.3 In-Line Powered Device Detection (Cisco Method) ............................................................................ 62 17.4 IEEE 802.3af (DTE Power via MDI) ................................................................................................... 63 18 Advanced Test Modes .................................................................................................................................................. 64 18.1 1000BASE-T Ethernet Packet Generator (EPG) ................................................................................ 64 18.2 1000BASE-T CRC Counter ................................................................................................................ 64 18.3 Far-end Loopback .............................................................................................................................. 64 18.4 Near-end Loopback ............................................................................................................................ 64 18.5 Connector Loopback .......................................................................................................................... 65 6 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 19 Hardware Configuration Using CMODE Pins ........................................................................................................... 66 19.1 Setting the CMODE Configuration Bits ............................................................................................... 66 19.2 CMODE Bit descriptions ..................................................................................................................... 66 19.3 Procedure For Selecting CMODE Pin Pull-up/Pull-down Resistor Values ......................................... 71 20 EEPROM Interface ........................................................................................................................................................ 72 20.1 Programming Multiple VSC8211s Using the Same EEPROM ........................................................... 73 21 PHY Startup and Initialization ...................................................................................................................................... 75 22 PHY Operating Modes .................................................................................................................................................. 76 22.1 PHY Operating Mode Description ...................................................................................................... 76 22.1.1 22.1.2 Auto Media Sense (AMS) Media Interface PHY Operating Modes ...................................................76 Serial MAC to Serial Media PHY Operating Mode: ............................................................................77 23 IEEE802.3 Clause 28/37 Remote Fault Indication Support .................................................................................... 77 24 PHY Register Set Conventions ................................................................................................................................... 80 24.1 PHY's Register Set Structure ............................................................................................................. 80 24.2 PHY's Register Set Nomenclature ...................................................................................................... 81 24.3 PHY Register Bit Types ...................................................................................................................... 81 25 PHY Register Set ........................................................................................................................................................... 82 25.1 Clause 28/37 Resister View ............................................................................................................... 82 25.2 PHY Register Names and Addresses ................................................................................................ 83 25.3 MII Register Descriptions ................................................................................................................... 85 25.3.1 25.3.2 25.3.3 25.3.4 25.3.5 25.3.6 25.3.7 25.3.8 25.3.9 25.3.10 25.3.11 25.3.12 25.3.13 25.3.14 25.3.15 25.3.16 25.3.17 25.3.18 25.3.19 25.3.20 Register 0 (00h) – Mode Control Register - Clause 28/37 View ........................................................85 Register 1 (01h) – Mode Status Register - Clause 28/37 View ..........................................................86 Register 2 (02h) – PHY Identifier Register #1 - Clause 28/37 View ..................................................88 Register 3 (03h) – PHY Identifier Register #2 - Clause 28/37 View ..................................................88 Register 4 (04h) – Auto-Negotiation Advertisement Register ............................................................89 Register 5 (05h) – Auto-Negotiation Link Partner Ability Register .....................................................91 Register 6 (06h) – Auto-Negotiation Expansion Register ...................................................................93 Register 7 (07h) – Auto-Negotiation Next-Page Transmit Register - Clause 28/37 View ................94 Register 8 (08h)–Auto-Negotiation Link Partner Next-Page Receive Register,Clause 28/37 View 95 Register 9 (09h) – 1000BASE-T Control Register ..............................................................................96 Register 10 (0Ah) – 1000BASE-T Status Register #1 ........................................................................98 Register 11 (0Bh) – Reserved Register .............................................................................................100 Register 12 (0Ch) – Reserved Register .............................................................................................100 Register 13 (0Dh) – Reserved Register .............................................................................................100 Register 14 (0Eh) – Reserved Register .............................................................................................100 Register 15 (0Fh) – 1000BASE-T Status Register #2 ......................................................................101 Register 16 (10h) – Reserved .............................................................................................................102 Register 17 (11h) – Reserved .............................................................................................................102 Register 18 (12h) – Bypass Control Register ....................................................................................103 Register 19 (13h) – Reserved............................................................................................................. 105 7 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 25.3.21 25.3.22 25.3.23 25.3.24 25.3.25 25.3.26 25.3.27 25.3.28 25.3.29 25.3.30 25.3.31 25.3.32 Register 20 (14h) – Reserved .............................................................................................................105 Register 21 (15h) – Reserved .............................................................................................................105 Register 22 (16h) – Control & Status Register ..................................................................................106 Register 23 (17h) – PHY Control Register #1 ...................................................................................108 Register 24 (18h) – PHY Control Register #2 ...................................................................................111 Register 25 (19h) – Interrupt Mask Register ......................................................................................113 Register 26 (1Ah) – Interrupt Status Register ....................................................................................115 Register 27 (1Bh) – LED Control Register .........................................................................................117 Register 28 (1Ch) – Auxiliary Control & Status Register ..................................................................119 Register 29 (1Dh) – Reserved ............................................................................................................120 Register 30 (1Eh) - MAC Interface Clause 37 Autonegotiation Control & Status ...........................120 Register 31 (1Fh) – Extended Page Access .....................................................................................122 25.4 Extended MII Registers .................................................................................................................... 123 25.4.1 25.4.2 25.4.3 25.4.4 25.4.5 25.4.6 25.4.7 25.4.8 25.4.9 25.4.10 25.4.11 25.4.12 25.4.13 25.4.14 25.4.15 26 Register 16E (10h) - Fiber Media Clause 37 Autonegotiation Control & Status .............................123 Register 17E (11h) - Serdes Control Register ...................................................................................124 Register 18E (12h) - Reserved ...........................................................................................................125 Register 19E (13h) - SerDes Control Register # 2 ............................................................................125 Register 20E (14h) - Extended PHY Control Register #3 ................................................................126 Register 21E (15h) - EEPROM Interface Status and Control Register ...........................................128 Register 22E (16h) - EEPROM Data Read/Write Register ..............................................................129 Register 23E (17h) - Extended PHY Control Register #4 ................................................................129 Register 24E (18h) - Reserved ...........................................................................................................130 Register 25E (19h) - Reserved ...........................................................................................................130 Register 26E (1Ah) - Reserved ...........................................................................................................130 Register 27E (1Bh) - Reserved ...........................................................................................................130 Register 28E (1Ch) - Reserved ..........................................................................................................130 Register 29E (1Dh) - 1000BASE-T Ethernet Packet Generator (EPG) Register #1...................... 131 Register 30E (1Eh) - 1000BASE-T Packet Generator Register #2 .................................................132 Electrical Specifications ............................................................................................................................................. 133 26.1 Absolute Maximum Ratings .............................................................................................................. 133 26.2 Recommended Operating Conditions .............................................................................................. 134 26.3 Thermal Application Data ............................................................................................................... 135 26.4 Package Thermal Specifications - 117 LBGA .................................................................................. 135 26.5 Current and Power Consumption ..................................................................................................... 136 27 DC Specifications ........................................................................................................................................................ 141 27.1 Digital Pins (VDDIO = 3.3V) ............................................................................................................. 141 27.2 Digital Pins (VDDIO = 2.5V) ............................................................................................................. 141 27.3 LED Output Pins (LED[4:0]) ............................................................................................................. 142 28 Clocking Specifications ............................................................................................................................................. 142 28.1 Reference Clock Option ................................................................................................................... 142 28.2 Crystal Option ................................................................................................................................... 143 8 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 29 SerDes Specifications ................................................................................................................................................ 144 30 System Timing Specifications .................................................................................................................................. 145 30.1 GMII Mode Transmit Timing (1000BASE-T) ..................................................................................... 145 30.2 GMII Mode Receive Timing (1000BASE-T) ...................................................................................... 146 30.3 MII Transmit Timing (100Mbps) ........................................................................................................ 147 30.4 MII Receive Timing (100Mbps) ......................................................................................................... 147 30.5 TBI Mode Transmit Timing ............................................................................................................... 148 30.6 TBI Mode Receive Timing ................................................................................................................ 149 30.7 RGMII/RTBI Mode Timing ................................................................................................................ 150 30.8 JTAG Timing ..................................................................................................................................... 153 30.9 SMI Timing ....................................................................................................................................... 154 30.10 MDINT Timing .................................................................................................................................. 155 30.11 Serial LED_CLK and LED_DATA Timing ......................................................................................... 155 30.12 REFCLK Timing ................................................................................................................................ 156 30.13 CLKOUTMAC and CLKOUTMICRO Timing ..................................................................................... 157 30.14 Reset Timing .................................................................................................................................... 158 31 Packaging Specifications .......................................................................................................................................... 159 31.1 Package Moisture Sensitivity ............................................................................................................ 159 32 Ordering Information .................................................................................................................................................. 160 32.1 Devices ............................................................................................................................................. 160 33 Design Guidelines ....................................................................................................................................................... 161 33.1 Required PHY Register Write Sequence .......................................................................................... 161 33.2 Interoperability with Intel 82547EI Gigabit Ethernet MAC+PHY IC .................................................. 161 33.3 SerDes Jitter ..................................................................................................................................... 161 33.4 100BASE-FX Initialization Script ...................................................................................................... 162 34 Product Support .......................................................................................................................................................... 165 34.1 Available Documents and Application Notes .................................................................................... 165 9 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Figures Figure 1. Parallel MAC to Cat-5, Fiber Optics, or Backplanes.............................................................................. 3 Figure 2. Serial MAC to Cat-5, Fiber Optics, or Backplanes ................................................................................ 3 Figure 3. GBIC/SFP Serial Interface (SGMII or 802.3z SerDes to Cat-5) ............................................................ 3 Figure 4. Media Converter (1000BASE-X to Cat-5).............................................................................................. 4 Figure 5. VSC8211 Block Diagram ..................................................................................................................... 17 Figure 6. VSC8211 117 Ball LBGA Package Ball Diagram................................................................................. 18 Figure 7. 117-Ball LBGA Signal Map (top view).................................................................................................. 19 Figure 8. System Schematic - ‘Parallel Data MAC to CAT5 Media’ PHY Operating Mode................................. 36 Figure 9. System Schematic - ‘Parallel Data MAC to 1000Mbps Fiber Media’ PHY Operating Mode................ 37 Figure 10. System Schematic - ‘Parallel Data MAC to Copper/Fiber Auto Media Sense’ PHY Operating Mode . 38 Figure 11. System Schematic - ‘SGMII/802.3z SerDes MAC to CAT5 Media’ PHY Operating Mode .................. 39 Figure 12. System Schematic - ‘SGMII/802.3z SerDes to 1000Mbps Fiber Media’ PHY Operating Mode .......... 40 Figure 13. System Schematic – ‘100Mbps Fiber Media’ Implementation ............................................................. 41 Figure 14. System Schematic - ‘Serial MAC to Fiber/CAT5 Media' PHY Operating Mode ................................... 42 Figure 15. VSC8211 Twisted Pair Interface .......................................................................................................... 43 Figure 16. Data Validity......................................................................................................................................... 46 Figure 17. Start [S] and Stop [T] Definition ........................................................................................................... 47 Figure 18. Acknowledge (By Receiver) [A] ........................................................................................................... 47 Figure 19. Acknowledge (By Host) [H].................................................................................................................. 47 Figure 20. No Acknowledge (By Host) [N] ............................................................................................................ 47 Figure 21. Random Write...................................................................................................................................... 48 Figure 22. Sequential Write .................................................................................................................................. 49 Figure 23. Random Read ..................................................................................................................................... 50 Figure 24. Sequential Read .................................................................................................................................. 51 Figure 25. MDIO Read Frame .............................................................................................................................. 53 Figure 26. MDIO Write Frame............................................................................................................................... 53 Figure 27. Logical Representation of MDINT Pin ................................................................................................. 53 Figure 28. Test Access Port and Boundary Scan Architecture ............................................................................. 57 Figure 29. Enhanced ActiPHY State Diagram ...................................................................................................... 60 Figure 30. In-line Powered Ethernet Switch Diagram ........................................................................................... 62 Figure 31. Far-end Loopback Block Diagram ....................................................................................................... 64 Figure 32. Near-end Loopback Block Diagram..................................................................................................... 65 Figure 33. Connector Loopback Block Diagram ................................................................................................... 65 Figure 34. EEPROM Interface Connections ......................................................................................................... 73 Figure 35. PHY Startup and Initialization Sequence ............................................................................................. 75 Figure 36. Extended Page Register Diagram ....................................................................................................... 80 Figure 37. GMII Transmit AC Timing in 1000BASE-T Mode................................................................................ 145 Figure 38. GMII Receive AC Timing in 1000BASE-T Mode ............................................................................... 146 Figure 39. MII Transmit AC Timing (100Mbps) ................................................................................................... 147 Figure 40. MII Receive AC Timing (100Mbps) .................................................................................................... 147 10 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Figure 41. TBI Transmit AC Timing..................................................................................................................... 148 Figure 42. TBI Receive AC Timing ..................................................................................................................... 149 Figure 43. RGMII/RTBI Uncompensated AC Timing and Multiplexing ............................................................... 151 Figure 44. RGMII/RTBI Compensated AC Timing and Multiplexing ................................................................... 152 Figure 45. JTAG Interface AC Timing ................................................................................................................. 153 Figure 46. SMI AC Timing................................................................................................................................... 154 Figure 47. LED_CLK and LED_DATA Output AC Timing ................................................................................... 155 Figure 48. REFCLK AC Timing........................................................................................................................... 156 Figure 49. CLKOUTMAC AC Timing .................................................................................................................. 157 Figure 50. CLKOUTMICRO AC Timing .............................................................................................................. 157 Figure 51. RESET AC Timing ............................................................................................................................. 158 Figure 52. 117-ball 10x14mm LBGA Mechanical Specification .......................................................................... 159 11 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Tables Table 1. Signal Type Description ......................................................................................................................... 20 Table 2. Configuration and Control Signals ......................................................................................................... 21 Table 3. System Clock Interface Signals (SCI) .................................................................................................... 22 Table 4. Analog Bias Signals ............................................................................................................................... 23 Table 5. JTAG Access Port .................................................................................................................................. 23 Table 6. Serial Management Interface Signals .................................................................................................... 24 Table 7. EEPROM Interface Signals ................................................................................................................... 25 Table 8. LED Interface Signals ............................................................................................................................ 25 Table 9. Parallel MAC Interface Signals - Transmit Signals ................................................................................ 26 Table 10. Parallel MAC Interface Signals - Receive Signals ................................................................................. 28 Table 11. Serial MAC/Media Interface Signals ...................................................................................................... 30 Table 12. Twisted Pair Interface Signals ............................................................................................................... 33 Table 13. Power Supply and Ground Connections ................................................................................................ 34 Table 14. No Connects .......................................................................................................................................... 34 Table 15. Power Supply and Associated Functional Signals ................................................................................. 35 Table 16. Accepted MDI Pair Connection Combinations ....................................................................................... 44 Table 17. SMI Pin Descriptions - MSA Mode ........................................................................................................ 46 Table 18. SMI Pin Descriptions - MSA Mode ........................................................................................................ 52 Table 19. SMI Frame Format ................................................................................................................................. 52 Table 20. LED Function Assignments .................................................................................................................... 54 Table 21. Parallel LED Functions .......................................................................................................................... 54 Table 22. LED Output Options ............................................................................................................................... 56 Table 23. JTAG Device Identification Register Description ................................................................................... 58 Table 24. JTAG Interface Instruction Codes .......................................................................................................... 58 Table 25. CMODE Pull-up/Pull-down Resistor Values ........................................................................................... 66 Table 26. CMODE Bit to PHY Operation Condition Parameter Mapping .............................................................. 67 Table 27. PHY Operating Condition Parameter Description .................................................................................. 68 Table 28. Configuration EEPROM Data Format .................................................................................................... 73 Table 29. PHY Operating Modes ........................................................................................................................... 76 Table 30. Clause 28 Register View Remote Fault Transmitted to Link Partner ..................................................... 78 Table 31. Clause 37 Register View Remote Fault Transmitted to Link Partner ..................................................... 78 Table 32. Clause 28 Autonegotiation Link Partner Remote Fault .......................................................................... 78 Table 33. Clause 37 Autonegotiation Link Partner Remote Fault .......................................................................... 79 Table 34. PHY Register Names and Addresses .................................................................................................... 83 Table 35. Bit Sequences for Generating Quinary Symbols ................................................................................... 97 Table 36. PHY Operating Modes ......................................................................................................................... 109 Table 37. Absolute Maximum Ratings ................................................................................................................. 133 Table 38. Recommended Operating Conditions .................................................................................................. 134 Table 39. PCB and Environmental Conditions ..................................................................................................... 135 Table 40. Thermal Resistance Data .................................................................................................................... 135 12 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 41. Thermal Specifications - 117 ball LBGA 10x14mm package ............................................................... 135 Table 42. VDDIO @ 3.3V, RGMII-CAT5, 1000BASE-T, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off ............................................................................................................................................... 136 Table 43. VDDIO @ 3.3V, RGMII-100BASE-FX, FDX, 1518 Byte Random data packet, 100% Utilization, SFP Mode Off ........................................................................................................................................................ 136 Table 44. VDDIO @ 2.5V, RGMII-CAT5, 1000BASE-T, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off ............................................................................................................................................... 136 Table 45. VDDIO @ 3.3 V, RGMII-CAT5, 100BASE-TX, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off ............................................................................................................................................... 137 Table 46. VDDIO @ 2.5 V, RGMII-CAT5, 100BASE-TX, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off ............................................................................................................................................... 137 Table 47. VDDIO @ 3.3 V, RGMII-CAT5, 10BASE-T, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off ............................................................................................................................................... 138 Table 48. VDDIO @ 2.5 V, RGMII-CAT5, 10BASE-T, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off ............................................................................................................................................... 138 Table 49. VDDIO @ 3.3 V, RGMII-Fiber, 1000BASE-X, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off ............................................................................................................................................... 139 Table 50. VDDIO @ 2.5 V, RGMII-Fiber, 1000BASE-X, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off ............................................................................................................................................... 139 Table 51. VDDIO @ 3.3 V, SerDes-CAT5, 1000BASE-T, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off ............................................................................................................................................... 140 Table 52. VDDIO @ 2.5 V, SerDes-CAT5, 1000BASE-T, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode off 140 Table 53. VDDIO @ 3.3 V, SerDes-CAT5, 1000BASE-T, FD, 1518 Byte Random data packet, 100% Utilization, SFP Mode on ............................................................................................................................................... 140 Table 54. Digital Pins Specifications (VDDIO = 3.3 V) ......................................................................................... 141 Table 55. Digital Pins Specifications (VDDIO = 2.5 V) ......................................................................................... 141 Table 56. Current Sinking Capability of LED Pins ............................................................................................... 142 Table 57. Reference Clock Option Specifications ................................................................................................ 142 Table 58. Crystal Option Specifications ............................................................................................................... 143 Table 59. SerDes Specifications .......................................................................................................................... 144 Table 60. GMII Mode Transmit Timing (1000BASE-T) Specifications ................................................................. 145 Table 61. GMII Mode Receive Timing (1000BASE-T) Specifications .................................................................. 146 Table 62. MII Transmit AC Timing Specifications (100 Mbps) ............................................................................. 147 Table 63. MII Receive Timing Specifications (100 Mbps) .................................................................................... 147 Table 64. TBI Mode Transmit Timing ................................................................................................................... 148 Table 65. TBI Mode Receive Timing .................................................................................................................... 149 Table 66. RGMII/RTBI Mode Timing .................................................................................................................... 150 Table 67. JTAG Timing ........................................................................................................................................ 153 Table 68. SMI Timing ........................................................................................................................................... 154 Table 69. MDINT Timing ...................................................................................................................................... 155 Table 70. Serial LED_CLK and LED_DATA Timing ............................................................................................. 155 Table 71. REFCLK Timing ................................................................................................................................... 156 Table 72. CLKOUTMAC and CLKOUTMICRO Timing ........................................................................................ 157 Table 73. RESET AC Timing Specification .......................................................................................................... 158 Table 74. SerDes Jitter ........................................................................................................................................ 161 13 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 5 Relevant Specifications & Documentation The VSC8211 conforms to the following specifications. Please refer to these documents for additional information. Specification - Revision Description IEEE 802.3-2002 Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer Specifications. IEEE 802.3-2002 consolidates and supersedes the following specifications: 802.3ab (1000BASE-T), 802.3z (1000BASE-X), 802.3u (Fast Ethernet), with references to ANSI X3T12 TP-PMD standard (ANSI X3.263 TP-PMD). IEEE 1149.1-1990 Test Access Port and Boundary Scan Architecture1. Includes IEEE Standard 1149.1a-1993 and IEEE Standard 1149.1b-1994. JEDEC EIA/JESD8-5 2.5V±0.2V (Normal Range), and 1.8V to 2.7V (Wide Range) Power Supply Voltage and Interface Standard for Nonterminated Digital Integrated Circuits. JEDEC JESD22-A114-B Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). Revision of JESD22-A114-A. JEDEC JESD22-A115-A Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM). Revision of EIA/JESD22-A115. JEDEC EIA/JESD78 MIL-STD-883E Cisco SGMII v1.7 RGMII Specification - v2.0 PICMG 2.16 Advanced TCA™ Base PICMG 3.0 Cisco InLine Power Detection Algorithm IC Latch-Up Test Standard. Miltary Test Method Standard for Microcircuits. Cisco SGMII specification Reduced Pin-Count Interface for Gigabit Ethernet Physical Layer Devices (per Hewlett Packard). Includes both RGMII and RTBI standards. IP Backplane for CompactPCI. IP Backplane specification for CompactPCI v3.0. Cisco Systems InLine Power Detection: http://www.cisco.com/en/US/products/hw/phones/ps379/ products_tech_note09186a00801189b5.shtml Small Form-factor Pluggable Specification for pluggable fiber optic transceivers. Describes module data access protocol (SFP) Transceiver MultiSource and interface. Agreement 1 Often referred to as the “JTAG” test standard. 14 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 6 Datasheet Conventions Conventions used throughout this datasheet are specified in the following table. 1 2 Convention Syntax Examples Description Register number RegisterNumber.Bit or RegisterNumber.BitRange 23.10 23.12:10 Extended Page Register Number1 RegisterNumberE.Bit or RegisterNumberE.BitRange 23E.10 23E.12:10 Extended Register 23 (address 17h), bit 10. Extended Register 23 (address 17h), bits 12, 11, and 10. Signal name (active high) SIGNALNAME2 PLLMODE Signal name for PLLMODE. Signal name (active low) SIGNALNAME2 RESET Signal bus name BUSNAME[MSB:LSB]2 RXD[4:2] Register 23 (address 17h), bit 10. Register 23 (address 17h), bits 12, 11, and 10. Active low reset signal. Receive Data bus, bits 4, 3, and 2. For more information about MII Extended Page Registers, see Section 24: "PHY Register Set Conventions," page 80. All signal names are in all CAPITAL LETTERS. 15 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 7 Document History and Notices Revision Number Date 0.1.0 Feb. 13 04 First Preliminary Release 0.1.1 May 11 04 Updated pin description with VDD12A and Power supply recommendations. Added Errata Section. Updated ‘specification’ section with VDD12A reference. Updated LED ECO changes. Added GMII,MII,TBI timing sections 2.0 July 08 04 Updated document style to reflect Vitesse corporate standards. Replaced Errata section with Design Guidelines section. 4.0 August 17 05 Comments Added lead-free (Pb-free) package information. Updated register section. Added Reset Timing section. • In the media converter application diagram, the RJ-45 speed was corrected from 10/100/1000BASE-T to 1000BASE-T. • Throughout the datasheet, information was added regarding the 100BASE-FX mode. The following lists the main information: – For information about twisted pair signals in 100BASE-FX mode, see Table 12: “Twisted Pair Interface Signals”. – For information about 100BASE-FX system schematics, see Figure 13: "System Schematic – ‘100Mbps Fiber Media’ Implementation". – For information about 100BASE-FX connections and initialization, see Section 11.5: "100Mbps Fiber Support Over Copper Media Interface" and Section 33.4: "100BASE-FX Initialization Script". – For information about 100BASE-FX current consumption, see Table 43: “VDDIO @ 3.3V, RGMII-100BASE-FX, FDX, 1518 Byte Random data packet, 100% Utilization, SFP Mode Off”. 4.1 October 2006 • In the list of LED function assignments, the function of LED pin 3, value 00, was corrected from Collision to Link/Activity. • In the listing of JTAG interface instruction codes, the register width given for the instructions EXTEST and SAMPLE/PRELOAD was corrected from 196 bits to 78 bits. • The MII transmit timing diagram was redrawn to more accurately reflect the delay from TXCLK to TXD[3:0], TXEN, and TXER. For more information about this specification, see Figure 39: “MII Transmit AC Timing (100Mbps)”. • In the JTAG interface AC timing diagram, missing labels were added that had been left out in the prior revision. • In the reset AC timing diagram, the MDIO signal pulse width was widened to be more accurate relative to the pulse width of the REFCLK signal. For more information about this specification, see Figure 51: "RESET AC Timing". • In the reset AC timing specifications, TREADY signal, a condition was added that if EEPROM is present, an additional 100ms is required. For more information about reset AC timing, see Table 73: “RESET AC Timing Specification”. 16 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 8 Device Block Diagram The diagram below depicts the primary functional blocks and pins for the VSC8211. SDOP SDON SDIP SDIN TDP TDN SerDes SGMII or Serial I/O TXVPA TXVNA TBI PCS PMA (DSP Data Pump) PCS ENCODER RDP RDN TBI SCLKP SCLKN PAM-5 SYMBOL MAPPER, SCRAMBLER MDI (Analog Front End) TX FIR NC1 NC2 NC3 DAC HYBRID EC TXVPC CMODE[7:0] RESET TXVPB TXVNB TXVNC Control TXDIS/SRESET TXD[7:0] TXEN TXER GTXCLK RXD[7:0] GMII MII RGMII TBI RTBI PCS DECODER TRELLIS DECODER PAM-5 SYMBOL DE-MAPPER, DESCRAMBLER + FFE ADC VGA TXVPD TXVND X4 TIMING RECOVERY RXDV RXER RXCLK TXCLK COL PLL, OSCILLATOR CRS TDI TDO TMS TCK TRST MODDEF1/MDC MODDEF2/MDIO RXLOS/SIGDET TEST MANAGER + JTAG ANALOG BIAS BLOCK MII REGISTERS LED INTERFACE PLLMODE/EECLK EEDAT Figure 5. VSC8211 Block Diagram 17 of 165 VMDS-10105 Revision 4.1 October 2006 XTAL2 XTAL1REFCLK AUTO-NEGOTIATION EEPROM and SERIAL MANAGEMENT INTERFACE CLKOUTMICRO/OSCDIS MODDEF0/CLKOUTMAC REFFILT REFREXT LED0 LED1 LED2 LED3 LED4 VSC8211 Datasheet 9 Package Pin Assignments & Signal Descriptions 9.1 VSC8211 117-Ball LBGA Package Ball Diagram 13 12 11 10 9 8 7 6 5 4 3 2 1 The following diagram shows the view from the top of the package with underlying BGA ball positions superimposed. A B C D E F G H J 1.0 mm Ball Pitch (10 mm x 14 mm body) (Top View) Figure 6. VSC8211 117 Ball LBGA Package Ball Diagram 18 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 9.2 LBGA Ball to Signal Name Cross Reference1 1 2 3 4 5 6 7 8 9 10 11 12 13 TDI RESET LED0 A A TXEN GTXCLK TXCLK RXER RXDV RXD1 RXD3 RXD5 RXD7 MODDEF0/ CLKOUTMAC B TXD1 TXDO TXER COL RXCLK RXD0 RXD2 RXD4 RXD6 TMS TDO LED1 LED2 B C TXD3 TXD2 VDDIOMAC CRS VSS VDDIOMAC RXLOS/ SIGDET TRST TCK VDD12 VDD12 LED3 LED4 C D TXD5 TXD4 VDDIOMAC VSS VSS VSS VSS VSS VSS E TXD7 TXD6 NC VSS VSS VSS VSS VSS VSS VSS F SDON SDOP VDD12 VDD12 VSS VSS VSS VSS VSS G SDIN SDIP VDD12 CLKOUTMICRO/ OSCDIS VDDIOMICRO VDD33A H RDN RDP MODDEF1/ MDC MDINT EEDAT REFFILT VDD12A J SCLKP SCLKN TDP TDN EECLK/ PLLMODE REFREXT 1 2 3 4 5 6 MODDEF2/ TXDIS/ MDIO SRESET VDDIOCTRL CMODE7 CMODE6 CMODE5 D CMODE2 CMODE3 CMODE4 E VDD33A CMODE0 TXVND TXVPD F VDD33A VDD33A CMODE1 TXVNC TXVPC G NC VSS XTAL2 VSS TXVNB TXVPB H VSS NC VSS XTAL1/ REFCLK VSS TXVNA TXVPA J 7 8 9 10 11 12 13 Figure 7. 117-Ball LBGA Signal Map (top view) 1 GMII Signal Names are shown for all Parallel MAC Interface Signals, except TXCLK (A3). See Section 9.4.8 on page 26 and Section 9.4.9 on page 28 for Signal Names in other Parallel MAC Interface Modes. 19 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 9.3 Signal Type Description Table 1. Signal Type Description Symbol Signal Type I Digital Input IPU Digital Input with Pull-up Standard digital input. Includes on-chip 100kΩ pull-up to VDDIOMAC, VDDIOMICRO, VDDIOCTRL, or the VDD33A supply. Refer to Section 9.5: “Power Supply and Associated Functional Signals” for details. IPU5V Digital Input with Pull-up Standard digital input. Includes on-chip 100kΩ pull-up to VDDIOMAC, VDDIOMICRO, VDDIOCTRL, or the VDD33A supply. Refer to Section 9.5: “Power Supply and Associated Functional Signals” for details. This input pin is 5V tolerant. IPD Digital Input with Pull-down Standard digital input. Includes on-chip 100kΩ pull-down to GND. IPD5V Digital Input with Pull-down Standard digital input. Includes on-chip 100k Ω pull-down to GND. This input pin is 5V tolerant. IDIFF Differential Input Pair O Digital Output OZC Description Standard digital input signal. No internal pull-up or pull-down. SerDes differential input pair with 100Ω or 150Ω differential terminations. Pins should be AC-coupled with external 0.01μF capacitors. Standard digital output signal. 50Ω integrated (on-chip) source series terminated, digital output signal. Used priImpedance Controlled Output marily for timing-sensitive, high speed MAC I/F and 125MHz clock output pins, in addition to high speed manufacturing test mode pins. SerDes differential output pair, with on-chip 100Ω or 150Ω differential terminations. Pins should be AC-coupled with external 0.01μF capacitors. ODIFF Differential Output Pair I/O Digital Bidirectional Tristate-able, digital input and output signal. IPU/O Digital Bidirectional Tristate-able, digital input and output signal. Includes on-chip 100kΩ pull-up to VDDIOMAC, VDDIOMICRO, VDDIOCTRL, or the VDD33A supply. Refer to Section 9.5: “Power Supply and Associated Functional Signals” for details. IPD/O Digital Bidirectional Tristate-able, digital input and output signal. Includes on-chip 100kΩ pull-down to GND. OD Digital Open Drain Output ADIFF Analog Differential ABIAS Analog Bias Analog bias or reference signal. Must be tied to external resistor and/or capacitor bias network, as shown in Section 10: “System Schematics”. IA Analog Input Analog input for sensing variable voltage levels. OS Open Source Open source digital output signal. Must be pulled to GND through an external pulldown resistor. P Power Supply Power supply connection. Must be connected to specified power supply plane. G GND NC No Connect Open drain digital output signal. Must be pulled to VDDIOMICRO through an external pull-up resistor. Analog differential signal pair for twisted pair interface. Ground Connection. Must be connected to ground. No connect signal. Must be left floating. 20 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 9.4 Detailed Pin Descriptions 9.4.1 Configuration and Control Signals Table 2. Configuration and Control Signals 117 LBGA Ball Signal Name D11 D12 D13 E13 E12 E11 G11 F11 CMODE7 CMODE6 CMODE5 CMODE4 CMODE3 CMODE2 CMODE1 CMODE0 A12 RESET Type Description IA Hardware Chip Mode Select. The CMODE inputs are used for hardware configuration of the various operating modes of the PHY. Each pin has multiple settings, each of which is established by an external 1% resistor tied to GND or VDD33A. See Section 19: “Hardware Configuration Using CMODE Pins” for details on configuring the PHY with the CMODE pins. I Hardware Chip Reset. RESET is an active low input. When asserted, it powers down all of the internal reference voltages and the PLLs. It resets all internal logic, including the DSPs and the MII Management Registers. Hardware reset is distinct from soft reset which only resets the port to accept new configuration based on register settings. Transmit Disable or Software Reset. When asserted, it places the PHY in a low power state, which includes disabling the SerDes interface. Although the device is powered down, non-volatile, Serial Management Interface registers retain their values. G5 TXDIS/ SRESET IPU TXDIS and SRESET are simply two names for the same function. The assertion state (active high or low respectively) of this input pin is determined by the value of Extended MII Register 21E.15 'SFP MODE' set at startup using Hardware Configuration or via the EEPROM interface. Refer to Section 19: “Hardware Configuration Using CMODE Pins” and Section 20: “EEPROM Interface” for details on configuration at startup. 21 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 9.4.2 System Clock Interface Signals (SCI) Table 3. System Clock Interface Signals (SCI) 117 LBGA BALL J10 Signal Name XTAL1/ REFCLK Type Description I XTAL1 - Crystal Oscillator Input. Enabled by pulling OSCDIS (Internal Oscillator Disabled) high, a 25MHz parallel resonant crystal, with a +/- 50ppm frequency tolerance, should be connected across XTAL1 and XTAL2. 33pF capacitors should be connected from XTAL1 and XTAL2 to ground. PLLMODE should be left floating (or pulled low) on reset when a 25MHz crystal is used. REFCLK - PHY Reference Clock Input. The reference input clock can either be a 25MHz (PLLMODE is low) or 125MHz (PLLMODE is high) reference clock, with a +/-50ppm frequency tolerance. See EECLK / PLLMODE pin description for more details. H10 G6 XTAL2 CLKOUTMICRO/ OSCDIS O Crystal Output. 25MHz parallel resonant crystal oscillator output. 33pF capacitors should be connected from both XTAL1 and XTAL2 to ground when using a crystal. PLLMODE should be left floating (or tied low) on reset when using the 25MHz crystal. This output can be left floating if driving XTAL1/REFCLK with a reference clock. CLKOUTMICRO - Clock Output. This is a 4MHz (default) or a 125MHz output clock depending on the value of Extended MII Register 20E.8. The clock output frequency can be set at startup by hardware configuration. Refer to Section 19: “Hardware Configuration Using CMODE Pins” for details. The voltage levels of the clock are based on the VDDIOMICRO power supply. IPU/O OSCDIS - Active Low on-chip Oscillator Disable Input. This input is sampled during the device power-up sequence or on assertion of RESET. When sampled high, the PHY enables the internal on-chip oscillator allowing operation with a 25MHz crystal. When sampled low, the PHY’s oscillator is turned off and the PHY must be supplied with an external 25MHz or 125MHz clock on the REFCLK pin. The functionality of this signal pin depends on the value for Extended MII Register 21E.15 ‘SFP Mode’ which is set at startup. Refer to Section 19: “Hardware Configuration Using CMODE Pins” and Section 20: “EEPROM Interface” for details on configuration at startup. A10 MODDEF0/ CLKOUTMAC O MODDEF0 – Active Low PHY Ready Indicator Output (valid in SFP Mode, when MII Register 21E.15 = 1). This output is driven high immediately on PHY power-up or reset. This signal is asserted low after the PHY startup sequence has completed and the PHY has enabled access to the EEPROM connected to EEPROM Interface through the Serial Management Interface. The minimum time this signal is high before being driven low is 10ms. The maximum time depends on the startup information stored in the EEPROM. Refer to Section 21: “PHY Startup and Initialization” and Section 20: “EEPROM Interface” for details. CLKOUTMAC – 125MHz Clock Output (valid in IEEE Mode, when MII Register 21E.15 = 0). The PHY drive a 125MHz clock output after the PHY startup sequence has completed. This clock can be disabled by clearing MII Register 18.0. 22 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 9.4.3 Analog Bias Signals Table 4. Analog Bias Signals 117 LBGA BALL Signal Name Type J6 REFREXT ABIAS REFREXT - Reference External Resistor. Bias pin connects through external 2kΩ (1%) resistor to analog ground. H6 REFFILT ABIAS REFFILT - Reference Filter. Filter internal reference through external 0.1μF (10%) capacitor to analog ground. Description 9.4.4 JTAG Access Port Table 5. JTAG Access Port 117 LBGA BALL A11 Signal Name TDI Type IPU5V Description JTAG Test Data Serial Input Data. Serial test pattern data is scanned into the device on this input pin, which is sampled with respect to the rising edge of TCK. This pin should be tied high to VDDIOCTRL in designs that do not require JTAG functionality. B11 B10 TDO TMS OZC IPU5V JTAG Test Data Serial Output Data. Serial test data from the PHY is driven out of the device on the falling edge of TCK. This pin should be left floating during normal chip operation. JTAG Test Mode Select. This input pin, sampled on the rising edge of TCK, controls the TAP (Test Access Port) controller’s 16-state, instruction state machine. This pin should be tied high to VDDIOCTRL in designs that do not require JTAG functionality. JTAG Test Clock. This input pin is the master clock source used to control all JTAG test logic in the device. C9 TCK IPU5V This pin should be pulled down with a 2kΩ pull-down resistor in designs that require JTAG functionality. This pin should be tied low in designs that do not require JTAG functionality. C8 TRST IPU5V JTAG Reset. This active low input pin serves as an asynchronous reset to the JTAG TAP controller’s state machine. As required by the JTAG standard, this pin includes an integrated on-chip pull-up (to VDDIOCTRL) resistor. Because of the internal pullup, if the JTAG controller on the printed circuit board does not utilize the TRST signal, then the device will still function correctly when the TRST pin is left unconnected on the board. If the JTAG port of the PHY is not used on the printed circuit board, then this pin should be pulled down with a 2kΩ pull-down resistor or a falling edge must be provided to this pin after PHY power up. 23 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 9.4.5 Serial Management Interface Signals Table 6. Serial Management Interface Signals 117 LBGA BALL Signal Name Type Description The Functionality of this pin is determined by the value of Extended MII Register 21E.15 ‘SFP MODE’ set at startup using CMODE Hardware Configuration or via the EEPROM interface. H3 MODDEF1/ MDC I MODDEF1 - Serial MSA Clock (valid in SFP Mode, when MII Register 21E.15 = 1). MODDEF1 is the clock input of the two-wire serial interface for accessing the PHY’s registers or the EEPROM connected to the EEPROM Interface using the protocol specified in the MSA specification. Although typically operated at 100kHz, MODDEF1 can be operated at a maximum of 1MHz. MDC - Management Data Clock (valid in IEEE Mode, when MII Register 21E.15 = 0). MDC is the clock input of the two wire serial interface for accessing the PHY’s registers or the EEPROM connected to the EEPROM Interface using the Serial Management Interface protocol specified in the IEEE 802.3 specification. This clock is typically between 0 to 12.5MHz and is usually asynchronous with respect to the PHY's transmit or receive clock. The Functionality of this pin is determined by the value of Extended MII Register 21E.15 ‘SFP MODE’ set at startup using CMODE Hardware Configuration or via the EEPROM interface. G4 MODDEF2/ MDIO I/O MODDEF2 - Serial I/O Data (valid in SFP Mode, when MII Register 21E.15 = 1). MODDEF2 is the data line of the two-wire serial interface for accessing the PHY’s registers or the EEPROM connected to the EEPROM Interface using the protocol specified in the MSA specification. This pin normally requires a 1.5kΩ to 4.7kΩ pull-up resistor to VDDIOMICRO at the Station Manager. The value of the pull-up resistor depends on the MODDEF1 frequency and the capacitive load on the MODDEF2 line. MDIO - Serial I/OP Data (valid in IEEE Mode, when MII Register 21E.15 = 0). MDIO is the data line of the two-wire serial interface for accessing the PHY’s registers or the EEPROM connected to the EEPROM Interface using the Serial Management Interface protocol specified in the IEEE 802.3 specification. This pin normally requires a 1.5kΩ to 4.7kΩ pull-up resistor to VDDIOMICRO at the Station Manager. The value of the pull-up resistor depends on the MDC frequency and the capacitive load on the MDIO line. Management Data Interrupt. MDINT is asserted whenever there is a change in operating status of the device. This open drain signal indicates a change in the PHY's link operating conditions for which a Station Manager must interrogate to determine further information. See MII Register 25 and MII Register 26 for more information. H4 MDINT OD The assertion polarity of the MDINT is determined by the presence of a pull-up or pull-down on the MDINT pin. If the MDINT pin is pulled up to VDDIOMICRO using a 4.7kΩ το 10kΩ resistor, is becomes an active low signal. If the MDINT pin is pulled down using a 4.7kΩ το 10kΩ resistor, then it becomes an active high signal. 24 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 9.4.6 EEPROM Interface Signals Table 7. EEPROM Interface Signals 117 LBGA BALL Signal Name Type Description EECLK - EEPROM Clock Output. This output is the clock line of the two-wire, MSA compliant serial EEPROM Interface. This should be connected to the SCL input pin of the AT24 series of Atmel EEPROMs. Refer Section 20: “EEPROM Interface” for details. J5 EECLK/ PLLMODE OZC/IPD PLLMODE - PLL Mode Select Input. PLLMODE is sampled during the device power-up sequence or on reset. When PLLMODE is high, the PHY expects a 125MHz clock input as the PHY's reference clock. When low (default), a reference clock of 25MHz is expected at the REFCLK pin from either an external crystal or a clock reference. This pin is internally pulled down with a 100kΩ resistor. H5 EEDAT OZC/IPD EEPROM Serial I/O Data. This bidirectional signal is the data line of the two wire, MSA compliant, serial EEPROM Interface. This should be connected to the SDA pin of the AT24 series of Atmel EEPROMs. Refer to Section 20: “EEPROM Interface” for details. The PHY determines that an external EEPROM is present by monitoring the EEDAT pin at power-up or when RESET is de-asserted. If EEDAT has a 4.7kΩ 10kΩ external pull-up (to VDDIOMICRO) resistor, it assumes an EEPROM is present. The EEDAT pin can be left floating or grounded to indicate no EEPROM. 9.4.7 LED Interface Signals Table 8. LED Interface Signals 117 LBGA BALL Signal Name C13 C12 B13 B12 A13 LED4 LED3 LED2 LED1 LED0 Type Description OZC LED - Direct-Drive LED Outputs. After reset, these pins serve as the direct drive, low EMI, LED driver output pins. All LEDs are active-low and driven at a 3.3V logic-high through the VDD33A analog power supply. The function of each LED can be set using hardware configuration or via MII Register 27. Refer to Section 19: “Hardware Configuration Using CMODE Pins” and MII Register 27 for details. 25 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 9.4.8 Parallel MAC Interface Signals - Transmit Signals The following signals are used in Parallel MAC Interface PHY Operating modes and connect to the parallel data bus MAC via the industry-standard GMII, RGMII, TBI, RTBI and MII interfaces. If these parallel interfaces are not used, all of the following pins may be left unconnected or tied to ground. Table 9. Parallel MAC Interface Signals - Transmit Signals 117 LBGA BALL Signal Name Parallel MAC Interface Modes TBI RTBI GMII MII Type Description RGMII Transmit Data Inputs (All modes). Transmit code-group data is input on these pins synchronously to the rising edge of GTXCLK in GMII mode and PMATXCLK in TBI mode. C1 C2 B1 B2 TX[3:0] TD[8:5] TD[7:4] and TXD[3:0] TXD[3:0] and TD[3:0] TD[3:0] IPD Transmit code-group data is input on these pins synchronously to the rising edge and falling edge of TXC in RTBI and RGMII modes. Multiplexed Transmit Data Nibbles (RTBI mode). Bits [3:0] are synchronously input on the rising edge of TXC, and bits [8:5] on the falling edge of TXC. Multiplexed Transmit Data Nibbles (RGMII mode). Bits [3:0] are synchronously input on the rising edge of TXC, and bits [7:4] on the falling edge of TXC. E1 E2 D1 D2 TX[7:4] Not used TXD[7:4] Not used Not used Transmit Data Inputs (TBI mode). Transmit code-group data is input on these pins synchronously to the rising edge of PMATXCLK in TBI mode. IPD Transmit Data Inputs (GMII mode). Transmit code-group data is input on these pins synchronously to the rising edge of GTXCLK in GMII mode. Transmit Data Input (TBI mode). Transmit code-group data bit 8 is input on this pin synchronously to the rising edge of PMATXCLK in TBI mode. A1 TX[8] Not used TXEN TXEN Not used IPD Transmit Enable Input (GMII, MII modes). Synchronized to the rising edge of GTXCLK (1000Mb mode) or TXCLK (100Mb mode), this input indicates valid data is present on the TXD bus. 26 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 9. Parallel MAC Interface Signals - Transmit Signals (continued) 117 LBGA BALL Signal Name Parallel MAC Interface Modes TBI RTBI GMII MII Type Description RGMII Transmit Data Input (TBI mode). Transmit code-group data bit 9 is input on this pin synchronously to the rising edge of PMATXCLK in TBI mode. Multiplexed Transmit Data Input (RTBI mode). Bit [4] is synchronously input on the rising edge of TXC, and bit [9] on the falling edge of TXC. B3 TX[9] TD[9] and TD[4] Transmit Error Input (GMII, MII modes). When asserted, this synchronous input causes error symbols to be transmitted from the PHY when operating in 100Mb or 1000Mb modes. TXER TXER TXCTL IPD Transmit Enable, Transmit Error Multiplexed Input (RGMII mode). In RGMII mode, this input is sampled by the PHY on opposite edges of TXC to indicate two transmit conditions of the MAC: 1) on the rising edge of TXC, this input serves as TXEN, indicating valid data is available on the TD input data bus. 2) on the falling edge of TXC, this input signals a transmit error from the MAC, based on a logical derivative of TXEN and TXER, per RGMII specification Version 1.2a, Section 3.4. PMA Transmit Code Group Clock Input (TBI mode). 125 MHz transmit code-group clock. This code-group clock is used to latch data into the PMA (in this case, the PHY) for transmission. A2 PMAT XCLK TXC GTXCLK Not used1 TXC IPD Transmit Clock Input (GMII mode). The transmit clock GTXCLK is a 125MHz, +/-100ppm reference clock used to synchronize the TXD data code group, TXD[7:0], into the PHY. Transmit Clock Input (RGMII/RTBI mode). The transmit clock shall be either a 125MHz or 25MHz (for 1000Mb or 100Mb modes, respectively), with a +/-50ppm tolerance. 1 See TX_CLK pin description in following section. 27 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 9.4.9 Parallel MAC Interface Signals - Receive Signals The following signals are used in Parallel MAC Interface PHY Operating modes and connect to the parallel data bus MAC via the industry-standard GMII, RGMII, TBI, RTBI and MII interfaces. If these parallel interfaces are not used, all of the following pins may be left unconnected or tied to ground. All output pins in the Parallel MAC interface include impedance-calibrated, tristateable output drive capability. Table 10. Parallel MAC Interface Signals - Receive Signals 117 LBGA BALL Signal Name Parallel MAC Interface Modes TBI RTBI GMII MII Type Description RGMII Receive Data Code Group (TBI mode). Bits [3:0] of 10-bit parallel receive code-group data. When code groups are properly aligned, any received code group containing a comma is clocked by the rising edge of PMARXCLK1. A7 B7 A6 B6 RX[3:0] RD[8:5] RD[7:4] and RXD[3:0] RXD[3:0] and RD[3:0] RD[3:0] OZC Multiplexed Receive Data Nibbles (RTBI mode). The MAC synchronously inputs Bits [3:0] on the rising edge of RXC, and bits [8:5] on the falling edge of RXC. Receive Data Code Group (GMII and MII modes). Receive data is driven out of the device synchronously to the rising edge of RXC. RXD[3] is the MSB, RXD[0] is the LSB. Multiplexed Receive Data Nibble (RGMII mode). Bits [3:0] are synchronously output on the rising edge of RXC, and bits [7:4] on the falling edge of RXC. RXD[3] is the MSB, RXD[0] is the LSB. A9 B9 A8 B8 B5 Leave pins RX[7:4] RXD[7:4] unconnected PMARX CLK0 RXC RXCLK Leave pins unconnected RXCLK Leave pins unconnected RXC Receive Data Code Group (TBI mode). Bits [7:4] of 10-bit parallel receive code-group data. When code groups are properly aligned, any received code group containing a comma is clocked by the rising edge of OZC PMARXCLK1. Receive Data Code Group (GMII mode). Receive data is driven out of the device synchronously to the rising edge of RXC. RXD[7] is the MSB. OZC PMA Receiver Clock 0 Output (TBI mode). The protocol device (MAC) uses the rising edge of this 62.5MHz receive clock to latch in odd-numbered code groups on the received PHY bit stream. This clock may be stretched during code-group alignment and is not shortened. Receive Clock Output (GMII, MII, RGMII and RTBI modes). Receive data is sourced from the PHY synchronous to the rising edge of RXCLK in GMII/MII modes or RXC in RGMII/RTBI modes. This clock is recovered from the media. 28 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 10. Parallel MAC Interface Signals - Receive Signals (continued) 117 LBGA BALL Signal Name Parallel MAC Interface Modes TBI A3 A5 RTBI Leave PMARX pins CLK1 unconnected RX[8] Leave pins unconnected GMII Leave pins unconnected RXDV MII TXCLK RXDV Type Description RGMII Leave pins unconnected Leave pins unconnected PMA Receiver Clock 1 Output (TBI mode). The protocol device (MAC) uses the rising edge of this 62.5MHz receive clock to latch even-numbered code groups on the received PHY bit stream. PMARXCLK1 is 180o out of phase with PMARXCLK0. This clock may be stretched during OZC code-group alignment and is not shortened. Transmit Clock (MII mode). 25MHz (100Mb mode) or 2.5MHz (10Mb mode) MII clock output. The MAC uses the rising edge of this clock to synchronize TXD data. OZC Receive Data Code Group, bit [8] (TBI mode). Bit [8] of 10-bit parallel receive code-group data. When code groups are properly aligned, any received code group containing a comma is clocked by the rising edge of PMARXCLK1. Receive Data Valid Output (GMII, MII modes). RXDV is asserted by the PHY to indicate that the PHY is presenting recovered and decoded data on the RXD pins. RXDV is synchronous with respect to RXCLK. Receive Data Code Group, bit [9] (TBI mode). Bit [9] of 10-bit parallel receive code-group data. When code groups are properly aligned, any received code group containing a comma is clocked by the rising edge of PMARXCLK1. Multiplexed Receive Data Nibbles (RTBI mode). The MAC synchronously inputs Bit [4] on the rising edge of RXC, and bit [9] (MSB) on the falling edge of RXC. A4 RX[9] RD[9] and RD[4] RXER RXER Receiver Error Output (GMII, MII modes). This active high output is synchronous to the rising edge of the received data clock (RXCLK or RXC). For 1000Mb mode, this signal is asserted when error symbols or carrier extension symbols are received. In 100Mb mode, it is asserted RXCTL OZC when error symbols are received. Multiplexed Receive Data Valid / Receive Error Output (RGMII mode). In RGMII mode, this output is sampled by the MAC on opposite edges of RXC to indicate two receive conditions from the PHY: 1) on the rising edge of RXC, this output serves as RXDV. When high it signals valid data is available on the RD input data bus. 2) on the falling edge of RXC, this output signals a receive error from the PHY, based on a logical derivative of RXDV and RXER, per RGMII specification Version 1.2a, Section 3.4. 29 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 10. Parallel MAC Interface Signals - Receive Signals (continued) 117 LBGA BALL Signal Name Parallel MAC Interface Modes TBI RTBI COMDET C4 Leave pins unconnected GMII CRS MII CRS Type Description RGMII Leave pins unconnected Comma Detect Output (TBI mode). A high on this signal indicates that the code-group associated with the current PMARXCLK1 contains a valid comma. In TBI mode, the PHY detects and code-group-aligns to the OZC comma+ bit sequence. Carrier Sense Output (GMII, MII modes). Valid only in GMII and MII half duplex modes, CRS is asserted high when a valid carrier is detected on the media. Collision Detect Output (GMII, MII modes). This output is asserted high when a collision is detected on the media. For full-duplex modes, this output is always low. B4 Leave RXCLK pins 125 unconnected COL COL Leave pins unconnected Receiver Clock 125MHz Output (TBI mode). This signal behaves differently, depending on whether TBI loopback mode is enabled: 1) When TBI loopback mode is enabled, RXCLK125 becomes one-half the frequency of the GTXCLK input OZC clock from the protocol device (or MAC). 2) When no carrier is present on the media, this signal is the same as the device’s free running output clock signal, CLKOUTMAC. 3) When a valid carrier is detected on the media, this output signal is the recovered clock from the TBI’s data stream. When switching from one of these three operating modes to another, RXCLK125’s low time will be extended, if necessary, to avoid clock glitching. 9.4.10 Serial MAC/Media Interface Signals Table 11. Serial MAC/Media Interface Signals 117 LBGA BALL J3 J4 H2 H1 Signal Name TDP TDN RDP RDN Type Description IDIFF Transmitter Data Differential Input Pair (used in SerDes/SGMII to CAT5 and Parallel MAC to SerDes/AMS PHY Operating Modes). Differential 1.25Gbaud receiver inputs with register selectable on-chip 100Ω or 150Ω differential termination. The TDP and TDN signals should be AC-coupled with external 0.01μF series capacitors. See Section 10: “System Schematics” for further information. ODIFF Receiver Data Differential Output Pair (used in SerDes/SGMII to CAT5 and Parallel MAC to SerDes/AMS PHY Operating Modes). Differential 1.25Gbaud transmitter outputs. External 0.01μF AC coupling capacitors should be located on the PHY side. The register selectable 100Ω or 150Ω differential termination should be placed near the MAC side. See Section 10: “System Schematics” for further information. For information about adjusting the output swing of these pins, see Register 17E (11h) – SerDes Control Register, page 124. 30 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 11. Serial MAC/Media Interface Signals (continued) 117 LBGA BALL J1 J2 G2 G1 F2 F1 Signal Name SCLKP SCLKN SDIP SDIN SDOP SDON Type Description ODIFF SGMII Clock Differential Output Pair (used in SGMII to CAT5/SerDes/AMS PHY Operating Modes). This signal pair is a differential 625MHz SGMII clock for the SGMII data in accordance with Cisco’s SGMII specification. These pins should be AC-coupled with external 0.01μF series capacitors or left unconnected when not used. See Section 10: “System Schematics” for further information. For information about adjusting the output swing of these pins, see Register 17E (11h) – SerDes Control Register, page 124. IDIFF Fiber Transceiver Differential Input Pair (used in SGMII to SerDes PHY Operating Modes). Differential 1.25Gbaud receiver inputs with register selectable on-chip 100Ω or 150Ω differential termination. The SDIP and SDIN signals should be AC-coupled with external 0.01μF series capacitors. These signals usually connect to the RX signals of the Fiber Optic Transceiver or the RX signals of a SerDes over the Backplane. ODIFF Fiber Transceiver Differential Output Pairs (used in SGMII to SerDes PHY Operating Modes). Differential 1.25Gbaud transmitter outputs. The SDOP and SDON signals should be ACcoupled with external 0.01μF AC series capacitors, placed on the PHY side of these traces. These signals usually connect to the TX signals of the Fiber Optic Transceiver or the TX signals of a SerDes over the Backplane. The register selectable 100Ω or 150Ω differential termination should be placed near the Transceiver/SerDes. For information about adjusting the output swing of these pins, see Register 20E (14h) – Extended PHY Control Register #3, page 126. 31 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 11. Serial MAC/Media Interface Signals (continued) 117 LBGA BALL Signal Name Type Description The functionality of this signal pin depends on the value for Extended MII Register 21E.15 ‘SFP Mode’ which is set at startup. Refer to Section 19: “Hardware Configuration Using CMODE Pins” and Section 20: “EEPROM Interface” for details on configuration at startup. RXLOS - Receiver Loss of Signal Output (valid in SFP Mode, when MII Register 21E.15 = 1). This active high signal is asserted when the CAT5 link goes down. The pulse width of the RXLOS signal is configurable. Refer to MII Register 30.1:0 for details. SIGDET - SerDes Signal Detect (I/O) (valid in IEEE Mode, when MII Register 21E.15 = 0). SIGDET can be configured as an input or output and can be configured to function as active low or active high at startup using hardware configuration or the EEPROM interface. Refer to Section 19: “Hardware Configuration Using CMODE Pins” or Section 20: “EEPROM Interface” for details on configuration at startup. C7 RXLOS/ SIGDET I/O SIGDET as Input: When used as an input, the SIGDET signal is meant to be connected to the signal detect output of the fiber optic transceiver. If SIGDET is high, this indicates receive activity on the fiber optic transceiver. In input mode, SIGDET is relevant only in the following PHY Operating modes: • Parallel MAC to Fiber (MII Register 23.15:12,23.2:1 = 0xx101) • Parallel MAC to Auto Media Sense (MII Register 23.15:12,23.2:1 = 00x0xx) • Serial to CAT5 (MII Register 23.15:12,23.2:1 = 1xxxxx) If SIGDET is not used as an input, the PHY internally generates the signal detect function, from the incoming data on the TDP and TDN signal pins. SIGDET as Output: For Fiber media, the SIGDET behavior depends upon the input signal levels on the TDP/ TDN pins and is defined as: • If the input signal amplitude is > 200mV peak-to-peak, SIGDET is asserted. • If the input signal amplitude is 50mV, SIGDET is undefined. • If the input signal amplitude is < 50mV peak-to-peak, SIGDET is deasserted. For Serial MAC to CAT5 Media PHY Operating modes, SIGDET is asserted if the CAT5 link has been established. In Parallel MAC to CAT5 Media PHY Operating Modes, SIGDET is always deasserted. 32 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 9.4.11 Twisted Pair Interface Signals Table 12. Twisted Pair Interface Signals 117 LBGA BALL J13 J12 H13 H12 G13 G12 F13 F12 Signal Name TXVPA TXVNA TXVPB TXVNB TXVPC TXVNC TXVPD TXVND Type Description ADIFF TX/RX Channel “A” Positive Signal. Positive differential signal connected to the positive primary side of the transformer. This signal forms the positive signal of the “A” data channel. In 10/100/1000Mbps mode, this signal generates the secondary side signal, normally connected to RJ-45 pin 1. In 100BASE-FX mode, it is connected instead to the positive SFP transmit data signal (SFP_TD+). See Section 10: "System Schematics" for details. ADIFF TX/RX Channel “A” Negative Signal. Negative differential signal connected to the negative primary side of the transformer. This signal forms the negative signal of the “A” data channel. In 10/100/1000Mbps mode, this signal generates the secondary side signal, normally connected to RJ-45 pin 1. In 100BASE-FX mode, it is connected instead to the negative SFP transmit data signal (SFP_TD–). See Section 10: "System Schematics" for details. ADIFF TX/RX Channel “B” Positive Signal. Positive differential signal connected to the positive primary side of the transformer. This signal forms the positive signal of the “B” data channel. In 10/100/1000Mbps mode, this signal generates the secondary side signal, normally connected to RJ-45 pin 1. In 100BASE-FX mode, it is connected instead to the positive SFP receive data signal (SFP_RD+). See Section 10: "System Schematics" for details. ADIFF TX/RX Channel “B” Negative Signal. Negative differential signal connected to the negative primary side of the transformer. This signal forms the negative signal of the “B” data channel. In 10/100/1000Mbps mode, this signal generates the secondary side signal, normally connected to RJ-45 pin 1. In 100BASE-FX mode, it is connected instead to the negative SFP receive data signal (SFP_RD–). See Section 10: "System Schematics" for details. ADIFF TX/RX Channel “C” Positive Signal. Positive differential signal connected to the positive primary side of the transformer. This signals forms the positive signal of the “C” data. In 1000Mb mode, this signal generates the secondary side signal, normally connected to RJ-45 pin 4 (not used in 10M/100M modes). See Section 10: "System Schematics" for details. ADIFF TX/RX Channel “C” Negative Signal. Negative differential signal connected to the negative primary side of the transformer. This signal forms the negative signal of the “C” data channel. In 1000Mb mode, this signal generates the secondary side signal, normally connected to RJ-45 pin 5 (not used in 10M/ 100M modes). See Section 10: “System Schematics” for details. ADIFF TX/RX Channel “D” Positive Signal. Positive differential signal connected to the positive primary side of the transformer. This signal forms the positive signal of the “D” data channel. In 1000Mb mode, this signal generates the secondary side signal, normally connected to RJ-45 pin 7 (not used in 10M/ 100M modes). See Section 10: “System Schematics” for details. ADIFF TX/RX Channel “D” Negative Signal. Negative differential signal connected to the negative primary side of the transformer. This signal forms the positive signal of the “D” data channel. In 1000Mb mode, this signal generates the secondary side signal, normally connected to RJ-45 pin 8 (not used in 10M/ 100M modes). See Section 10: “System Schematics” for details. 33 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 9.4.12 Power Supply and Ground Connections Table 13. Power Supply and Ground Connections 117 LBGA BALL Supply Name Recommended PCB Power Plane Type Nominal Supply Voltage (V) Description Digital I/O Power Supply Pins C6, C3, D3 VDDIOMAC1 V+IO P 3.3V or 2.5V Power for the Parallel MAC Interface G7 VDDIOMICRO1 V+IO P 3.3V or 2.5V Power for SMI and EEPROM Interface D10 VDDIOCTRL1 V+IO P 3.3V or 2.5V Power for JTAG I/O V+12 P 1.2V Power for internal digital logic, and SerDes/ SGMII I/O Power Digital Core Power Supply Pins C10, C11, F3, F4, G32 VDD12 Analog Power Pins F10, G10,G9,G8 VDD33A V+33A P 3.3V Power for MDI, CMODE, PLL, and LED blocks. H7 VDD12A V+12A P 1.2V Power of PLL and ADC blocks. VSS GND G 0V Ground Pins C5, D4, D5, D6, D7, D8, D9, E4, E5, E6, E7, E8, E9, E10, F5, F6, F7, F8, F9, J7, H9, J9, H11, J11 1 2 Ground for all blocks The I/O power supplies on the PHY are separated on the chip itself to facilitate support for different VDDIO supply voltages. These VDDIO supplies can be run independently at 2.5v or 3.3v I/O. All these pins must be connected to VDD12 supply. 9.4.13 No Connects Table 14. No Connects 117 LBGA BALL Signal Name Type E3, H8, J8 NC NC Description No Connect - must be left floating 34 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 9.5 Power Supply and Associated Functional Signals Table 15. Power Supply and Associated Functional Signals Power Supply Pins Nominal Voltages VDDIOMAC 3.3V or 2.5V RXLOS/SIGDET, RXD[7:0], RXDV, RXER, RXCLK, COL, CRS, TXCLK, TXER, GTXCLK, TXEN, TXD[7:0], MODDEF0/CLKOUTMAC VDDIOMICRO 3.3V or 2.5V EECLK/PLLMODE, EEDAT, TXDIS/SRESET, MDINT, MODDEF1/MDC, MODDEF2/ MDIO, CLKOUTMICRO/OSCDIS VDDIOCTRL 3.3V or 2.5V RESET, TDO, TDI, TMS, TCK, TRST VDD33A 3.3V LED[4:0], CMODE[7:0], TXVND, TXVPD, TXVNC, TXVPC, TXVNB, TXVPB, TXVNA, TXVPAXTAL2, XTAL1/REFCLK, REFFILT, REFREXT VDD12 1.2V RDP, RDN, TDP, TDN, SCLKP, SCLKN, SDIN, SDIP, SDOP, SDON VDD12A 1.2V Associated Functional Pins 35 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 10 System Schematics 10.1 Parallel Data MAC to CAT5 Media PHY Operating Mode VDD33A VDDIOMAC T1 50 CLKIN Transformer TXVPA MODDEF0/CLKOUTMAC J1 0.1µF RXLOS/SIGDET RXLOS/SIGDET RJ-45 TXVNA 50 CRS 50 50 Receive Data 50 50 50 50 50 50 GMII/MII/RGMII/TBI/RTBI MAC Not used in RGMII/RTBI modes TXVPC Not used in MII/RGMII/RTBI modes TXVNC 0.1µF 9 GND Not used in MII mode TXER TXEN Transmit Data S1 TXVND RXD0 GTXCLK VDD 7 D+ 8 D- TXVPD RXD1 50 4 C+ 5 C- 0.1µF RXD6 RXD5 RXD4 RXD3 RXD2 50 3 B+ 6 B- TXVNB RXER RXDV RXD7 50 U2 0.1µF Not used in GMII/RGMII/RTBI modes RXCLK 50 TXVPB Not used in RGMII/RTBI modes COL TXCLK 50 1 A+ 2 A- 75 Not used in RGMII/RTBI modes 75 TXD7 TXD6 75 Not used in MII/RGMII/RTBI modes TXD5 TXD4 TXD3 TXD2 U1 VSC8211 TXD1 TXD0 REFFILT Use a single GND point for these components 0.1µF 2K (1%) REFREXT GND VDDIOCTRL 33pF XTAL2 VDDIOCTRL U3 TDI 50 TDO JTAG Port Controller TMS TCK TCK VDD33A CMODE7 …. RESET VDDIOMICRO GND R TRST RESET 33pF XTAL1/REFCLK TDO TMS TRST 25MHz TDI (See section on CMODE) R CMODE0 VDDIOMICRO GND VDD33A R 4.7k VDDIOMICRO U4 LED4 EEDAT EECLK/PLLMODE SDA EEPROM SCL VDDIOMICRO R LED3 R VDDIOMICRO or GND LED2 R LED1 VDDIOMICRO 4.7k R 10k LED0 U5 TXDIS/SRESET MDINT MODDEF2/MDIO TXDIS/SRESET Station Manager CPU and/or Control Logic MDINT MDIO MDC CLKIN 50 MODDEF1/MDC CLKOUTMICRO/OSCDIS GND Common analog / digital ground plane Figure 8. System Schematic − ‘Parallel Data MAC to CAT5 Media’ PHY Operating Mode 36 of 165 VMDS-10105 Revision 4.1 October 2006 S2 10 75 1000pF, 2kV VSC8211 Datasheet 10.2 Parallel Data MAC to 1000Mbps Fiber Media PHY Operating Mode V D D IO M A C VD D12 50 C LK IN M O D D E F 0 /C L K O U T M A C R X LO S /S IG D E T R X L O S /S IG D E T 50 CRS 50 COL TXC LK 50 50 Receive Data RXER RXDV RXD7 50 50 50 50 G M II/R G M II/T B I/R T B I M AC .0 1 µ F RDP RXD4 RXD3 RXD2 50 50 TDP 100 or 150 RXD1 RXD0 50 RDN 100 or 150 .0 1 µ F RDN TDN G TXC LK TX ER N ot us ed in R G M II/R T B I m ode s TXEN Transmit Data VDD TX D7 V DD 33A TXD6 TXD5 N ot us ed in R G M II/R T B I m ode s TXD4 TX D3 U1 VSC 8211 TXD2 TX D1 TXD0 R E F F IL T U se a s in g le G N D p o in t fo r th e s e c o m p o n e n ts 0 .1 µ F 2K (1 % ) REFREXT GND V D D IO C T R L 33pF XTAL2 V D D IO C T R L U3 TDI 50 TDO JT A G P o rt C o n tro lle r 25M H z TD I 33pF X T A L 1 /R E F C L K TDO TM S TMS VD D 33A TCK TCK TRST CMODE7 …. RESET V D D IO M IC R O GND R TR ST RESET (S e e s e c tio n o n C M O D E ) R CM ODE0 V D D IO M IC R O GND V DD 33A R 4 .7 k V D D IO M IC R O U4 LED 4 EEDAT SDA EEPROM R E E C L K /P L L M O D E SCL V D D IO M IC R O LED 3 R V D D IO M IC R O o r GND LED 2 R LED 1 V D D IO M IC R O 4 .7 k R 10k LED 0 U5 T X D IS /S R E S E T M D IN T T X D IS /S R E S E T S ta tio n M anager CPU a n d /o r C o n tro l L o g ic M D IN T M O D D E F 2 /M D IO M D IO MDC C L K IN 50 M O D D E F 1 /M D C C L K O U T M IC R O /O S C D IS GND C o m m o n a n a lo g / d ig ita l g ro u n d p la n e Figure 9. System Schematic − ‘Parallel Data MAC to 1000Mbps Fiber Media’ PHY Operating Mode 37 of 165 VMDS-10105 Revision 4.1 October 2006 J1 1 0 0 0 B A S E -L X /S X F ib e r M o d u le N ot us ed in R G M II/R T B I m ode s RXD5 50 U2 .0 1 µ F TD N N ot us ed in R G M II/R T B I m odes RXD6 50 RDP 100 or 150 N ot us ed in R G M II/R T B I m odes R XC LK 50 .0 1 µ F TD P N ot us ed in R G M II/R T B I m odes VSC8211 Datasheet 10.3 Parallel Data MAC to Copper/Fiber Auto Media Sense PHY Operating Mode VDD12 SIGDET RXLOS/SIGDET .01µF TDP RDP 100 or 150 .01µF TDN RDN VDDIOMAC J1 1000BASE-LX/SX Fiber Module .01µF RDP 50 CLKIN TDP 100 or 150 MODDEF0/CLKOUTMAC 100 or 150 .01µF RDN TDN VDD33A 50 CRS 50 TXCLK 50 Receive Data RXER RXDV RXD7 Not used in RGMII/RTBI modes RXD6 RXD5 Not used in MII/RGMII/RTBI modes 50 50 50 50 50 50 50 50 GMII/MII/RGMII/TBI/RTBI MAC TXVNB TXVPC Transmit Data TXVNC 7 D+ 8 D- TXVPD 0.1µF Not used in MII/RGMII/RTBI modes TXD4 S1 TXVND TXD3 TXD2 9 GND REFFILT TXD0 U1 VSC8211 VDDIOCTRL GND 33pF VDD33A GND R CMODE7 …. RESET VDDIOMICRO 75 25MHz XTAL1/REFCLK TDO TRST RESET 1000pF, 2kV 75 33pF XTAL2 TDI TCK TCK 10 75 Use a single GND point for these components TMS TMS TRST S2 75 0.1µF 2K (1%) REFREXT JTAG Port Controller 4 C+ 5 C- 0.1µF Not used in RGMII/RTBI modes TXD5 50 3 B+ 6 B- Not used in MII mode TXD7 TXD6 TDI 1 A+ 2 A0.1µF TXER TXEN TDO RJ-45 TXVNA RXD1 RXD0 TXD1 U3 J1 0.1µF TXVPB GTXCLK VDDIOCTRL Transformer TXVPA RXD4 RXD3 RXD2 50 VDD T1 Not used in GMII/RGMII/RTBI modes RXCLK 50 U2 Not used in RGMII/RTBI modes COL 50 (See section on CMODE) R CMODE0 VDDIOMICRO GND VDD33A R 4.7k VDDIOMICRO U4 LED4 EEDAT SDA EEPROM R EECLK/PLLMODE SCL VDDIOMICRO LED3 R VDDIOMICRO or GND LED2 R LED1 VDDIOMICRO 4.7k R 10k LED0 U5 TXDIS/SRESET MDINT MODDEF2/MDIO TXDIS/SRESET Station Manager CPU and/or Control Logic MDINT MDIO MDC CLKIN 50 MODDEF1/MDC CLKOUTMICRO/OSCDIS GND Common analog / digital ground plane Figure 10. System Schematic − ‘Parallel Data MAC to Copper/Fiber Auto Media Sense’ PHY Operating Mode 38 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 10.4 SGMII/802.3z SerDes MAC to CAT5 Media PHY Operating Mode VDD33A VDDIO M AC T1 50 CLKIN RXLO S/SIG DET M O DDEF0/CLKO UTM AC Transform er TXVPA J1 0.1µF R J-45 RXLO S/SIG DET TXV NA 1 A+ 2 A- TXVPB 0.1µF VDD12 3 B+ 6 B- TXV NB TXV PC TDP TX VNC 100 or 150 .01µF TDN 7 D+ 8 D- TX VPD TDN 0.1µF S GM II/802.3z S erDes M AC Controller S1 TX VND RDP .01µF 9 RDP 100 or 150 VDD 4 C+ 5 C- 0.1µF .01µF TDP U2 GND 75 1000pF, 2kV 75 .01µF RDN 75 .01µF SCLKP SCLKP (O ptional - M ay not be required by the M AC) 100 or 150 SCLKN U1 VSC8211 100 or 150 .01µF SCLKN REFFILT Use a single G ND point for these com ponents 0.1µF 2K (1% ) REFREXT GND VDDIO CTRL 33pF XTA L2 U3 VDDIOCTRL T DI 50 TDO JTAG Port Controller TCK VDD33A CM ODE7 …. RE SET VDDIOM ICRO GND R TRST RESET 33pF XTAL1/RE FCLK TDO TM S TCK TRST 25M Hz TDI TM S (S ee section on CM O DE) R CM ODE0 VDDIOM ICRO G ND VDD33A R 4.7k VDDIOM ICRO U4 LED4 EEDAT SDA EE PROM R EECLK/PLLM O DE SCL VDDIO M ICRO LED3 R VDDIOM ICRO or G ND LED2 R LED1 VDDIOM ICRO 4.7k R 10k LED0 U5 TXDIS/S RESET M DINT TXDIS/SRESET Station M anager CPU and/or Control Logic M DINT M O DDEF2/M DIO M DIO M DC CLKIN 50 M O DDEF1/M DC CLKOUTM ICRO/OSCDIS G ND Com m on analog / digital ground plane Figure 11. System Schematic − ‘SGMII/802.3z SerDes MAC to CAT5 Media’ PHY Operating Mode 39 of 165 VMDS-10105 Revision 4.1 October 2006 10 75 100 or 150 RDN S2 VSC8211 Datasheet 10.5 SGMII/802.3z SerDes to 1000Mbps Fiber Media PHY Operating Mode VDD12 VDDIOMAC 50 CLKIN MODDEF0/CLKOUTMAC .01µF SDIP RXLOS/SIGDET RXLOS/SIG DET RDP 100 or 150 .01µF SDIN RDN VDD12 .01µF SDOP .01µF TDP U2 100 or 150 .01µF TDN TDP 100 or 150 TDP J1 1000BASE-LX/SX Fiber Module OR Back Plane Connector 100 or 150 .01µF SDON TDN TDN SGMII/802.3z SerDes MAC Controller .01µF RDP RDP 100 or 150 VDD 100 or 150 .01µF RDN RDN VDD33A .01µF SCLKP SCLKP (Optional - May not be required by the MAC) 100 or 150 SCLKN U1 VSC8211 100 or 150 .01µF SCLKN REFFILT Use a single GND point for these components 0.1µF 2K (1% ) REFREXT GND VDDIOCTRL 33pF XTAL2 U3 VDDIOCTRL TDI 50 TDO JTAG Port Controller 25MHz TDI XTAL1/REFCLK TDO TMS TMS TCK TCK VDD33A CMODE7 VDDIOMICRO …. RESET RESET GND R TRST TRST 33pF (See section on CMODE) R CMODE0 VDDIOMICRO GND VDD33A R 4.7k VDDIOMICRO U4 LED4 EEDAT SDA EEPROM R EECLK/PLLMODE SCL VDDIOMICRO LED3 R VDDIOMICRO or GND LED2 R LED1 VDDIOM ICRO 4.7k R 10k LED0 U5 TXDIS/SRESET MDINT MODDEF2/M DIO TXDIS/SRESET Station Manager CPU and/or Control Logic M DINT MDIO MDC CLKIN 50 MODDEF1/MDC CLKOUTMICRO/OSCDIS GND Common analog / digital ground plane Figure 12. System Schematic − ‘SGMII/802.3z SerDes to 1000Mbps Fiber Media’ PHY Operating Mode 40 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 10.6 100Mbps Fiber Media Implementation VDD33 VDD33 LEDn LINK100/ACTIVITY TXVNB TXVPB TXVPA TXVNA PHY_TXVNB PHY_TXVPB SFP_RDSFP_RD+ PHY_TXVPA PHY_TXVNA SFP_TD+ SFP_TD- 11 12 13 14 15 16 17 18 19 20 Veet Tfault Tdis MOD_DEF2 MOD_DEF1 MOD_DEF0 Rate Select LOS Veer Veer Veer RDRD+ Veer Vccr Vcct Veet TD+ TDVeet 1 2 3 4 5 6 7 8 9 10 SFP Connector VDD33 1uH 10uF 10uF TXVPC TXVNC TXVPD TXVND 100nF 100nF 1uH 100nF 11 12 13 14 15 16 17 18 19 20 GND11 GND12 GND13 GND14 GND15 GND16 GND17 GND18 GND19 GND20 GND1 GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 1 2 3 4 5 6 7 8 9 10 SFP Cage VSC8211/VSC8221 Figure 13. System Schematic – ‘100Mbps Fiber Media’ Implementation 41 of 165 VMDS-10105 Revision 4.1 October 2006 SFP_TXFAULT SFP_TXDIS SFP_SDA SFP_SCL SFP_PRESENT SFP_RX_LOS VSC8211 Datasheet 10.7 Serial MAC to Fiber/CAT5 Media PHY Operating Mode1 VDD12 Input to station manager U5 SIGDET .01µF SDIP RDP 100 or 150 VDDIOMAC .01µF SDIN 50 CLKIN .01µF SDOP MODDEF0/CLKOUTMAC J2 1000BASE-LX/SX Fiber Module OR Back Plane Connector TDP 100 or 150 100 or 150 RXLOS/SIGDET RXLOS/SIGDET RDN .01µF SDON TDN VDD12 VDD33A .01µF TDP U2 T1 TDP 100 or 150 .01µF TDN Transformer TXVPA J1 0.1µF TDN RJ-45 TXVNA SGMII/802.3z SerDes MAC Controller 1 A+ 2 A- TXVPB 0.1µF .01µF RDP 3 B+ 6 B- RDP TXVNB 100 or 150 100 or 150 VDD .01µF RDN TXVPC 4 C+ 5 C- 0.1µF RDN TXVNC .01µF SCLKP U1 VSC8211 100 or 150 100 or 150 (Optional - May not be required by the MAC) SCLKN .01µF 7 D+ 8 D- TXVPD SCLKP 0.1µF S1 TXVND 9 SCLKN GND S2 10 75 75 VDDIOCTRL 1000pF, 2kV 75 REFFILT VDDIOCTRL U3 TDI 50 TDO JTAG Port Controller TMS TDI GND TCK TCK TRST TRST VDDIOMICRO 25MHz VDD33A GND R CMODE7 EEDAT SDA …. U4 33pF XTAL1/REFCLK VDDIOMICRO 4.7k VDDIOMICRO 33pF XTAL2 RESET RESET EEPROM 75 0.1µF 2K (1%) REFREXT TDO TMS EECLK/PLLMODE SCL (See section on CMODE) R CMODE0 VDDIOMICRO or VDDIOMICRO GND GND VDD33A R U5 LED4 10k 4.7k VDDIOMICRO R LED3 MDIO TXDIS/SRESET MDINT MODDEF2/MDIO MDC MODDEF1/MDC TXDIS/SRESET Station Manager CPU and/or Control Logic MDINT 50 CLKIN SIGDET R LED2 R LED1 R LED0 CLKOUTMICRO/OSCDIS Output from Fiber Module J2 GND Common analog / digital ground plane Figure 14. System Schematic - ‘Serial MAC to Fiber/CAT5 Media' PHY Operating Mode 1 The Transition from 'Serial MAC to CAT5' PHY Operating mode to 'Serial MAC to Fiber' PHY Operating mode and vice versa is managed by the 'Station Manager' by writing to PHY Register 23.15:12,2:1, based on the SIGDET input from the Fiber Optic connector. Note that power supply sequencing is not needed to bring the device out of reset. Once the supplies are stable, the device reset can be deasserted. 42 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 11 Twisted Pair Interface The twisted pair interface on the VSC8211 is fully compliant with the IEEE802.3-2000 specification for CAT-5 media. All passive components necessary to connect the PHY to an external 1:1 transformer have been integrated into the VSC8211. The connection of the twisted pair interface is shown in the following figure: VSC8211 * TXVPA 0.1µF J1 RJ-45 1 A+ 2 A- TXVNA TXVPB 0.1µF 3 B+ 6 B- TXVNB TXVPC 4 C+ 5 C- 0.1µF TXVNC 7 D+ 8 D- TXVPD 0.1µF S1 TXVND S2 75 75 PHY Port 1000pF, 2kV 75 75 * SimpliPHY’d magnetics can be used. For information, refer to the SimpliPHY’d Magnetics application note. Figure 15. VSC8211 Twisted Pair Interface Unlike other Gigabit PHYs, which do not integrate line terminations into the PHY, the VSC8211 device’s twisted pair interface is compatible with a wide variety of standard magnetics and RJ-45 modules from common module vendors. Depending on the application (the number of ports, EMI performance requirements such as FCC Class A or B, the type and quality of the equipment shielding, and other EMI design practices in place, for example), the twisted pair interface may be used with standard (12- or 8-core) magnetics as well as SimpliPHY’d (4-core) magnetics modules available from many module vendors. In addition, this interface is also used to provide support for 100Mbps fiber module connection. For more information on the suitability of using SimpliPHY’d magnetics for a particular design, see the application note SimpliPHY’d Magnetics and EMI Control, available from the Vitesse website. 11.1 Twisted Pair Autonegotiation (IEEE802.3 Clause 28) The VSC8211 supports twisted pair autonegotiation, as defined in IEEE 802.3-2002 clause 28. (However, autonegotiation is not defined by IEEE for the 100BASE-FX mode and is therefore not supported.) This process evaluates the advertised capabilities of the local PHY and its link partner to determine the best possible operating mode. In particular, autonegotiation can determine speed, duplex, and MASTER/SLAVE modes for 1000BASE-T. Autonegotiation also allows the local MAC to communicate with the Link Partner MAC (via optional “Next-Pages”) to set attributes that may not be defined in the standard. If the link partner does not support autonegotiation, the VSC8211 will automatically use parallel-detect to select the appropriate link speed. Clause 28 twisted-pair autonegotiation can be disabled by clearing bit MII Register bit 0.12 – Auto-Negotiation Enable. If autonegotiation is disabled, the operating speed and duplex mode of the VSC8211 is determined by the state of MII Register bits 0.13, 0.6 – Forced Speed Selection and MII Register bit 0.8 – Duplex Mode. For more information, see “Register 0 (00h) – Mode Control Register - Clause 28/37 View” on page 85. 43 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 11.2 Twisted Pair Auto MDI/MDI-X Function For trouble-free configuration and management of Ethernet links, the VSC8211 includes robust Automatic Crossover Detection functionality for all three speeds on the twisted pair interface (10BASE-T, 100BASE-TX, and 1000BASE-T) – fully compliant with the IEEE standard. In addition, the VSC8211 detects and corrects polarity errors on all MDI pairs, beyond what is required by the standard. Both the Automatic MDI/MDI-X and Polarity Correction functions are enabled by default. However, complete user control of these two features is available using bits 5 and 4 of the Bypass Control register. For more information, see “Register 18 (12h) – Bypass Control Register” on page 103. Status bits for each of these functions are located in Register 28 (1Ch) – Auxiliary Control & Status Register. The VSC8211’s Automatic MDI/MDI-X algorithm will successfully detect, correct, and operate with any of the MDI wiring pair combinations listed in the following table: Table 16. Accepted MDI Pair Connection Combinations RJ-45 Connections MDI Pair Connection Combinations Accepted by VSC8211 Comments 1,2 3,6 4,5 7,8 A B C D Normal MDI mode Normal DTE/NIC mode No crossovers B A C D MDI-X mode Normal for switches & repeaters Crossover on A and B pairs only C Normal MDI mode Normal for DTEs (NICs) No crossovers Pair swap on C and D pairs C Normal MDI-X mode Normal switch/repeater mode Crossovers assumed Crossover on A and B pairs Pair swap on C and D pairs A B B A D D 11.3 Auto MDI/MDI-X in Forced 10/100 Link Speeds The VSC8211 includes the ability to perform Auto MDI/MDI-X even when auto-negotiation is disabled (MII Register 0.12 = 0) and the link is forced into 10/100 link speeds. In order to enable this feature, additional MII register write settings are also needed in the following order: To enable Auto MDI/MDI-X in forced 10/100 link speeds: • Write MII Register 31 = 0x2A30 • Write MII Register 8 = 0x0212 • Write MII Register 31 = 0x52B5 • Write MII Register 2 = 0x0012 • Write MII Register 1 = 0x2803 • Write MII Register 0 = 0x87FA • Write MII Register 31 = 0x2A30 • Write MII Register 8 = 0x0012 • Write MII Register 31 = 0x0000 To disable Auto MDI/MDI-X in forced 10/100 link speeds: • Write MII Register 31 = 0x2A30 44 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet • Write MII Register 8 = 0x0212 • Write MII Register 31 = 0x52B5 • Write MII Register 2 = 0x0012 • Write MII Register 1 = 0x3003 • Write MII Register 0 = 0x87FA • Write MII Register 31 = 0x2A30 • Write MII Register 8 = 0x0012 • Write MII Register 31 = 0x0000 11.4 Twisted Pair Link Speed Downshift In addition to automatic crossover detection, the VSC8211 supports an automatic link speed “downshift” option for operation in cabling environments incompatible with 1000BASE-T. When this feature is enabled, the VSC8211 will automatically change its autonegotiation advertisement to 100BASE-TX after a set number of failed attempts at 1000BASE-T. This is especially useful in setting up networks using older cable installations which may include only pairs A and B and not pairs C and D. The link speed downshift feature is configured and monitored using Register 20E (14h) - Extended PHY Control Register #3. 11.5 100Mbps Fiber Support Over Copper Media Interface The VSC8211 supports 100BASE-FX over its copper media interface by using pairs A and B, which provide TX and RX differential connections, respectively. If the fiber module does not have internal AC coupling capacitors, then they are required between the PHY and fiber module. The value should be 0.1µF. The RXLOS/SIGDET signal is not used in this mode. A separate 1000BASE-X fiber module may be connected to the PHY through the 1000BASE-X SerDes pins. 11.5.1 Register Settings The PHY can be brought into the 100BASE-FX operation mode using the following configuring sequence: 1. Initialize the PHY into the specific MAC-to-copper operating mode for the MAC interface type required (register 23). 2. Disable Auto-Negotiation and force the 100BASE-T FDX mode (register 0). 3. Run the 100BASE-FX initialization script; for more information, see Section 33.4: "100BASE-FX Initialization Script". 4. Configure other settings, such as LEDs. 12 Transformerless Operation for PICMG 2.16 and 3.0 IP-based Backplanes The twisted pair interface supports capacitively coupled links, such as those specified by the PICMG 2.16 and 3.0 specifications. With proper AC coupling, the typical category-5 magnetic isolation can be replaced with capacitors. For more information, see “Register 24 (18h) – PHY Control Register #2,” page 111, and the Vitesse application note “Transformerless Ethernet Concept and Applications”. By enabling the PICMG Miser mode, power consumption can be reduced to approximately 500mW. 13 Dual Mode Serial Management Interface (SMI) The Serial Management Interface provides access to the PHY registers for device configuration and Status Information. It also provides access to the EEPROM connected to the EEDAT and EECLK pins (EEPROM Interface) of the PHY. For details on EEPROM access through the SMI interface refer to Section 20: "EEPROM Interface". 45 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet The MODDEF1/MDC, MODDEF2/MDIO, and the MDINT pins comprise the SMI interface. By writing to MII Register 21E.15 at startup (Refer to Section 19: "Hardware Configuration Using CMODE Pins" and Section 20: "EEPROM Interface" for details), the SMI of the PHY can be set to operate in one of the following two modes: 1. MSA 2. IEEE 13.1 PHY Register Access with SMI in MSA mode In this mode, the PHY registers are accessed using the standard MSA compliant protocol. This protocol is generally used for reading and writing to Atmel’s AT24 series compatible EEPROMs. In this mode, the SMI pins function as follows: Table 17. SMI Pin Descriptions - MSA Mode Pin Name Description MODDEF1 Clock Input. Connect to the SCL pin of the AT24 series of EEPROMs. MODDEF2 Bidirectional Data. Connect to the SDA pin of the AT24 series of EEPROMs. This pin should be pulled high on the board using a 4.7kΩ to 10kΩ pull-up resistor. MDINT Interrupt Signal. According to the protocol described in the MSA specification, the following conditions are defined: • Start [S]: A high to low transition on the MODDEF2 pin when MODDEF1 is high. • Data [D]: A transition on the MODDEF2 pin when MODDEF1 is low. A low to high transition is '1' and a high to low transition is '0'. • Stop [T]: A low to high transition on the MODDEF2 pin when MODDEF1 is high. • Acknowledge (By Receiver) [A]: A low driven by the PHY/Receiver after 8 Data states. The transition on MODDEF2 takes place when MODDEF1 is low. The host does not drive the MODDEF2 Data line in this condition. • Acknowledge (By Host) [H]: A low driven by the host after 8 Data states. The transition on MODDEF2 takes place when MODDEF1 is low. The PHY/Receiver does not drive the MODDEF2 Data line in this condition. • No Acknowledge (By Host) [N]: A high driven by the host after 8 Data states. The transition on MODDEF2 takes place when MODDEF1 is low. The PHY/Receiver does not drive the MODDEF2 Data line in this condition. MODDEF2 MODDEF1 Data Stable Data Change Figure 16. Data Validity 46 of 165 VMDS-10105 Revision 4.1 October 2006 Data Stable VSC8211 Datasheet M O D D E F2 M O D D E F1 S TA R T [S ] S TO P [T] Figure 17. Start [S] and Stop [T] Definition 1 MODDEF1 8 9 MODDEF2 (Driven by Receiver) START ACKNOWLEDGE Figure 18. Acknowledge (By Receiver) [A] 1 M O DDEF1 8 9 (Driven by Host) MODDEF2 START ACKNO W LEDG E Figure 19. Acknowledge (By Host) [H] 1 MODDEF1 8 9 (Driven by Host) MODDEF2 START ACKNOW LEDGE Figure 20. No Acknowledge (By Host) [N] 47 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 13.1.1 Write Operation - Random Write S 1 0 1 0 1 1 0 0 A 0 0 0 R4 R3 R2 R1 R0 A M7 M6 M5 M4 M3 M2 M1 M0 A T S 1 0 1 0 1 1 0 0 A 0 0 0 R4 R3 R2 R1 R0 A L7 L6 L5 L3 L2 L1 L0 A T From Host to PHY/Receiver From PHY/Receiver to Host Figure 21. Random Write • R4..R0 are the 5 bits of the Register address R. • M7..M0 are bits of the Upper byte of the 16 bit Register data • L7..L0 are bits of the Upper byte of the 16 bit Register data The PHY register is written only after the host performs the lower data byte write operation. 48 of 165 VMDS-10105 Revision 4.1 October 2006 L4 VSC8211 Datasheet 13.1.2 Write Operation - Sequential Write MSB for Register R S 1 0 1 0 1 1 0 0 A 0 0 0 R4 R3 R2 R1 LSB for Register R L7 L6 L5 L4 L3 L2 L1 L6 L5 L4 L3 L2 L1 A M7 M6 L0 A M7 M6 M5 M4 M3 M2 M1 M0 L6 L5 L4 L3 L2 L1 L0 A L0 A M7 M6 M5 M4 T From Host to PHY/Receiver From PHY/Receiver to Host Figure 22. Sequential Write • R4..R0 are the 5 bits of the Register address R. • M7..M0 are bits of the Upper byte of the 16 bit Register data • L7..L0 are bits of the Upper byte of the 16 bit Register data The PHY register is written only after the host performs the lower data byte write operation. 49 of 165 VMDS-10105 Revision 4.1 October 2006 M3 M2 M1 A MSB for Register R+n LSB for Register R+n L7 M5 M4 MSB for Register R+1 LSB for Register R+1 L7 R0 M3 M2 M1 M0 A M0 A VSC8211 Datasheet 13.1.3 Read Operation - Random Read S 1 0 1 0 1 1 0 0 A 0 0 S 1 0 1 0 1 1 0 1 A M7 M6 M5 M4 M3 M2 M1 M0 N T S 1 0 1 0 1 1 0 0 A 0 S 1 0 1 0 1 1 0 1 A L7 L6 L5 L4 L3 L2 L1 L0 N T 0 0 R4 R3 R2 R1 R0 A 0 R4 R3 R2 R1 R0 A From Host to PHY/Receiver From PHY/Receiver to Host Figure 23. Random Read • R4..R0 are the 5 bits of the Register address • M7..M0 are bits of the Upper byte of the 16 bit Register data • L7..L0 are bits of the Lower byte of the 16 bit Register data 50 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 13.1.4 Read Operation - Sequential Read S 1 0 1 0 1 1 0 0 A 0 0 0 R4 R3 R2 R1 R0 A MSB for Register R S 1 0 1 0 1 1 0 1 A M7 M6 M5 M4 M3 M2 M1 M0 H LSB for Register R L7 L6 L5 L4 L3 L2 MSB for Register R+1 L1 L0 H M7 M6 M5 M4 M3 M2 M1 M0 H LSB for Register R+1 L7 L6 L5 L4 L3 L2 L1 LSB for Register R+n L0 H L0 N M7 M6 M5 M4 M3 M2 M1 M0 H LSB for Register R+n L7 L6 L5 L4 L3 L2 L1 T From Host to PHY/Receiver From PHY/Receiver to Host Figure 24. Sequential Read • R4..R0 are the 5 bits of the Register address • M7..M0 are bits of the Upper byte of the 16 bit Register data • L7..L0 are bits of the Lower byte of the 16 bit Register data 51 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 13.2 PHY Register Access with SMI in IEEE Mode In IEEE mode, the SMI is fully compliant with the IEEE 802.3-2000 MII Interface specifications. In IEEE mode, the SMI pins function as follows: Table 18. SMI Pin Descriptions - MSA Mode Pin Name Description MDC Clock Input, 0 – 12.5 Mhz. MDIO Bidirectional Data. This pin should be pulled high on the board using a 4.7kΩ to 10kΩ resistor. MDINT Active Low or Active High open drain interrupt output. As many as 32 PHYs (32 distinct PHY Addresses) can share a common IEEE SMI signal pair (MDC, MDIO). Data is transferred over the IEEE SMI using 32-bit frames with an optional and arbitrary length preamble. The IEEE SMI frame format is described in the following table. Table 19. SMI Frame Format Direction from VSC8211 # of bits Read Write Start of Frame Preamble PHY Address Op Code Register Address TurnAround Data Idle 1+ 2 2 5 5 2 16 ? Output Z’s ZZ ZZ Z’s Z’s Z0 data Z’s Input 1’s 01 10 addr addr ZZ Z’s Z’s Output Z’s ZZ ZZ Z’s Z’s ZZ Z’s Z’s Input 1’s 01 01 addr addr 10 data Z’s • Idle: During idle, the MDIO node goes to a high-impedance state. This allows an external pull-up resistor to pull the MDIO node up to a logical “1” state. Since idle mode should not contain any transitions on MDIO, the number of bits is undefined during idle. • Preamble: For the VSC8211, the preamble is optional. By default, preambles are not expected or required. The preamble is a string of “1”s. If it exists, the preamble must be at least one bit, but otherwise my be arbitrarily long. See MII Register 1.6 for more information. • Start of frame: A “01” pattern indicates the start of frame. If these bits are anything other than “01”, all following bits are ignored until the next “preamble:0” pattern is detected. • Operation code: A “10” pattern indicates a read. A “01” pattern indicates a write. If these bits are anything other than “01” or “10”, all following bits are ignored until the next “preamble:0” pattern is detected. • PHY address: The next five bits are the PHY address. The PHY responds to a message frame only when the received PHY address matches its physical address. The PHY's address is indicated by the CMODE1[2] and CMODE0[3:0] bits. • Register address: The next five bits are the register address. • Turn-around: The next two bits are “turn-around” (TA) bits. They are used to avoid contention when a read operation is performed on the MDIO. During read operations, the VSC8211 will drive the second TA bit, which is a logical “0”. • Data: The next sixteen bits are data bits. When data is being read from the PHY, data is valid at the output of the PHY from one rising edge of MDC to the next rising edge of MDC. When data is being written to the PHY, data must be valid around the rising edge of MDC. • Idle: The sequence is repeated. 52 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet The following two figures diagram IEEE SMI read and IEEE SMI write operations. S ta tio n M a n a g e r D riv e s M D IO P H Y D riv e s M D IO MDC M D IO Z Id le Z 1 0 1 P re a m b le S F D (o p tio n a l) 1 0 A4 R ead A3 A2 A1 A0 P H Y A d d re s s R4 R3 R2 R1 R0 R e g is te r A d d re s s to P H Y Z 0 D 15 D 14 D 13 D 12 D 11 D 10 D 9 TA D8 D7 D6 D5 D4 D3 D2 D1 D0 R e g is te r D a ta fro m P H Y Z Z Id le Figure 25. MDIO Read Frame S ta tio n M a n a g e r D riv e s M D IO (P H Y tris ta te s M D IO d u rin g e n tire s e q u e n c e ) MDC M D IO Z Id le Z 1 0 1 P re a m b le S F D (o p tio n a l) 0 1 W rite A4 A3 A2 A1 P H Y A d d re s s A0 R4 R3 R2 R1 R0 R e g is te r A d d re s s to P H Y 1 0 D15 D14 D13 D12 D11 D10 D9 TA D8 D7 D6 D5 D4 D3 D2 D1 R e g is te r D a ta fro m P H Y D0 Z Z Id le Figure 26. MDIO Write Frame 13.3 SMI Interrupt The SMI includes an output signal MDINT for signaling the Station Manager when certain events occur in the PHY. The MDINT pin can be configured for active-low or active-high operation by tying the pin to either a pull-up resistor to VDDIOMICRO or to a pull-down resistor to GND. VDDIOMICRO VSC8211 4.7k-10k External Pull-up at Station Manager MDINT Interrupt Enable (Register 25.15) Interrupt Status (Register 26.15) PHY 4.7k-10k External Pull-down at Station Manager Figure 27. Logical Representation of MDINT Pin 53 of 165 VMDS-10105 Revision 4.1 October 2006 MDINT (to Station Manager) VSC8211 Datasheet 14 LED Interface The PHY has five dedicated LED[4:0] pins to drive 5 LEDs directly. For power savings, all LED outputs can be configured to pulse at 5kHz with a 20% duty cycle. All LED outputs are active-low and driven with 3.3V from the VDD33A power supply when deasserted. Due to the fact that the 100BASE-FX mode uses 100BASE-T resources, its indications are those of the 100BASE-T mode. Four different functions have been assigned to each LED pin. Selection is done using either the CMODE hardware configuration (see Section 19: "Hardware Configuration Using CMODE Pins") or the settings in Register 27 (1Bh) – LED Control Register, page 117. The functions are assigned according to the following table: Table 20. LED Function Assignments LED Configuration Bits LED Pin 4 Config [1:0] LED Pin 3 Config [1:0] LED Pin 2 Config [1:0] LED Pin 1 Config [1:0] LED Pin 0 Config [1:0] Value LED Function Selection 11 TX 10 Fault 01 Activity 00 Duplex/Collision 11 RX 10 Fiber 01 Duplex/Collision 00 Link/Activity 11 TX 10 Link/Activity 01 Duplex/Collision 00 Link10/Activity 11 Link100/1000/Activity 10 Link/Activity 01 Link10/100/Activity 00 Link100/Activity 11 RX 10 Fault 01 Link/Act (with serial output on LED pins 1 and 2) 00 Link1000/Activity LED functions are summarized in the following table. Table 21. Parallel LED Functions Function Name Link1000/Activity1 State Description 1 No link in 1000BASE-T or 1000BASE-X 0 Valid 1000BASE-T link or 1000BASE-X link Pulse-stretch/Blink2 (optional) Valid 1000BASE-T link and activity present 54 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 21. Parallel LED Functions (continued) Function Name State Description 1 1 Link100/Activity 0 Pulse-stretch/Blink Link10/Activity1 Link10/100/ Activity1 Link100/1000/ Activity1 Collision Activity Fiber Fault Serial Duplex/Collision3 Rx Tx Valid 100BASE-Tx link 2 (optional) Valid 100BASE-Tx link and activity present 1 No link in 10BASE-T 0 Valid 10BASE-T link Pulse-stretch/Blink2 (optional) Valid 10BASE-T link and activity present 1 No link in 10BASE-T or 100BASE-Tx 0 Valid 10BASE-T link or valid 100BASE-Tx link Pulse-stretch/Blink2 (optional) Valid 10BASE-T link or valid 100BASE-Tx link and activity present 1 No link in 100BASE-Tx or 1000BASE-T 0 Pulse-stretch/Blink Link/Act1 No link in 100BASE-Tx Valid 100BASE-Tx link or valid 1000BASE-T link 2 (optional) Valid 100BASE-Tx link or valid 1000BASE-T link and activity present 1 No link in any speed 0 Valid link in any speed Pulse-stretch/Blink2 Valid link in any speed and activity present 1 No collisions detected Pulse-stretch/blink2 Collisions detected 1 No activity Pulse-stretch/blink2 Activity present 1 No valid 1000BASE-X link established 0 Fiber media detected on SerDes interface and valid 1000BASE-X link established 1 No IEEE Clause 37/28 autonegotiation fault 0 IEEE Clause 37/28 autonegotiation fault ** See serial interface specification 1 Link established in half-duplex mode, or no link established 0 Link established in full-duplex mode Pulse-stretch/Blink2 (optional) Link established in half duplex mode and collisions present 1 No activity on Rx side Pulse-stretch/blink2 Activity present on Rx side 1 No activity on Tx side Pulse-stretch/blink2 Activity present on Tx side 1 By default the ‘Link’ functions are combined with ‘Activity’. To use the LED as a dedicated ‘Link’, LED MII register bit 27.1 must be set. Function can either blink or be pulse-stretched when active. See Table 22 below. 3 By default the ‘Duplex’ function is combined with ‘Collision’. To use the LED as a dedicated ‘Duplex’, LED MII register bit 27.0 must be set. 2 55 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet In addition to function selection, several options are available for the LED outputs through the use of MII register 27.5:0. These are summarized below: Table 22. LED Output Options MII Reg Bits 5:4 3 LED Option Bits LED Blink/Pulse-Stretch Rate LED pulse-stretch/blink 2 LED Pulsing Enable 1 LED combine LINK with ACT 0 LED combine COL with DUP Value LED Function Selection 11 2.5Hz blink rate/ 400 ms pulse-stretch 10 20Hz blink rate/ 50ms pulse-stretch 01 10Hz blink rate/ 100ms pulse-stretch 00 5Hz blink rate/ 200ms pulse-stretch 1 Collision, Activity, Rx and Tx LED outputs will be pulsestretched when active 0 Collision, Activity, Rx and Tx LED outputs will blink when active 1 When active, LED outputs will be pulsed at 5KHz, 20% duty cycle for power savings 0 When active, LED outputs will remain at a static low 1 Link LEDs indicate link status only 0 Link LEDs will blink or flash when activity is present. Blink/flash behavior is selected by Pulse-Stretch Enable bit. 1 Duplex LED indicates duplex status only 0 Duplex LED will blink or flash when collision is present. Blink/ flash behavior is selected by Pulse-Stretch Enable bit. 14.1 Serial LED Output A serial output option is available which allows access to all LED signals through two pins. This option is selected by setting LED Pin 0 configuration bits to 01 on the PHY. In this mode, LED pins 1 and 2 function as serial data and clock. LED function outputs for the PHY are clocked out on the rising edge of data clock. The clock rate is approximately 1MHz, with a 37 clock cycle preamble. The serial bitstream outputs each LED signal as described by the numbered list below.The individual signals shall be clocked out in the following order: 1. Link1000/Act 2. Link/Act 3. Link100/Act 4. Act 5. Link10/Act 6. Dup/Col 7. Tx 8. Col 9. Rx 10. Fault 11. Fiber/Copper 56 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 15 Test Mode Interface (JTAG) The PHY supports the Test Access Port and Boundary Scan Architecture IEEE 1149.1 standards. The device includes an IEEE 1149.1 compliant test interface, often referred to as a “JTAG TAP Interface”. IEEE 1149.1 defined test logic provides the following standardized test methodologies: • Testing the interconnections between integrated circuits once they have been assembled onto a printed circuit board or other substrate. • Testing the integrated circuit itself during IC and systems manufacture. • Observing or modifying circuit activity during the component’s normal operation. The JTAG Test interface logic on the PHY, accessed through a Test Access Port (TAP) interface, consists of a boundary-scan register and other logic control blocks. The TAP controller includes all IEEE-required signals (TMS, TCK, TDI, and TDO), in addition to the optional asynchronous reset signal TRST. The following figure diagrams the TAP and Boundary Scan Architecture. Boundary-Scan Register Device Identification Register Bypass Register Instruction Register, Instruction Decode, Control TDI TMS TRSTz TCK control Mux, DFF control Test Access Port Controller select tdoenable Figure 28. Test Access Port and Boundary Scan Architecture 57 of 165 VMDS-10105 Revision 4.1 October 2006 TDO VSC8211 Datasheet The PHY also includes the optional Device Identification Register, shown in the following table, which allows the manufacturer, part number, and version number of the device to be determined through the TAP Controller. See Chapter 11 of the IEEE 1149.1-1990 specifications for more details. Also, note that some of the information in the identification register is duplicated in the IEEE-specified bit fields in MII Register 3 (PHY Identifier Register #2). Table 23. JTAG Device Identification Register Description Description Device Version Number Part Number (or Revision Code) (or Model Number) Vitesse’s Manufacturer Identity LSB Bit Field 31 - 28 27 - 12 11 - 1 0 1000 0010 0001 0001 001 1001 1000 1 Binary Value 0001 15.1 Supported Instructions and Instruction Codes After a TAP reset, the Device Identification Register is serially connected between TDI and TDO by default. The TAP Instruction Register is loaded either from a shift register (when a new instruction is shifted in), or, if there is no new instruction in the shift register, a hard-wired default value of 0110 (IDCODE) is loaded. Using this method, there is always a valid code in the instruction register, and the problem of toggling instruction bits during a shift is avoided. Unused codes are mapped to the BYPASS instruction. The VSC8211 supports the instruction codes listed in the following table and described below. Table 24. JTAG Interface Instruction Codes Instruction Code Selected Register Register Width Specification EXTEST 0000 Boundary-Scan Register 78 Mandatory IEEE 1149.1 SAMPLE/PRELOAD 0001 Boundary-Scan Register 78 Mandatory IEEE 1149.1 IDCODE 0110 Device Identification Register 32 Optional IEEE 1149.1 CLAMP 0010 Bypass Register 1 Optional IEEE 1149.1 HIGHZ 0011 Bypass Register 1 Optional IEEE 1149.1 BYPASS 0111 Bypass Register 1 Mandatory IEEE 1149.1 Reserved 0100, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111 EXTEST The mandatory EXTEST instruction allows testing of off-chip circuitry and board-level interconnections by sampling input pins and loading data onto output pins. Outputs are driven by the contents of the boundary-scan cells, which have to be updated with valid values (with the PRELOAD instruction) prior to the EXTEST instruction.1 SAMPLE/PRELOAD The mandatory SAMPLE/PRELOAD instruction allows a snapshot of inputs and outputs during normal system operation to be 1 Following the use of this instruction, the on-chip system logic may be in an indeterminate state that will persist until a system reset is applied. Therefore, the on-chip system logic may need to be reset on return to normal (i.e., non-test) operation. 58 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet taken and examined. It also allows data values to be loaded into the boundary-scan cells prior to the selection of other boundary-scan test instructions. IDCODE The optional IDCODE instruction provides the version number (bits 31:28), and Vitesse’s manufacturer identity (bits11:1), which can be serially read from the PHY. See “Register 3 (03h) – PHY Identifier Register #2 - Clause 28/37 View” on page 88 for the PHY-specific values for this instruction. CLAMP The optional CLAMP instruction allows the state of the signals driven from the component pins to be determined from the Boundary-Scan Register while the Bypass Register is selected as the serial path between TDI and TDO. While the CLAMP instruction is selected, the signals driven from the component pins will not change.1 HIGHZ The optional HIGHZ instruction places the component in a state in which all of its system logic outputs are placed in a high impedance state. In this state, an in-circuit test system may drive signals onto the connections normally driven by a component output without incurring a risk of damage to the component. This makes it possible to use a board where not all of the components are compatible with the IEEE 1149.1 standard.1 BYPASS The Bypass Register contains a single shift-register stage and is used to provide a minimum-length serial path (one TCK clock period) between TDI and TDO to bypass the device when no test operation is required. 15.2 Boundary-Scan Register Cell Order All inputs and outputs are observed in the Boundary-Scan Register cells. All outputs are additionally driven by the contents of Boundary-Scan Register cells. Bidirectional pins have all three related Boundary-Scan Register cells: the input, the output, and the control. The full boundary scan cell order is available from Vitesse Semiconductor in *.BSD file format. 1 Following the use of this instruction, the on-chip system logic may be in an indeterminate state that will persist until a system reset is applied. Therefore, the on-chip system logic may need to be reset on return to normal (i.e., non-test) operation. 59 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 16 Enhanced ActiPHY Power Management In addition to the IEEE-specified power-down control bit (MII Register 0.11), the VSC8211 implements an Enhanced ActiPHY™ power management mode. This mode enables support for power-sensitive applications such as laptop computers with Wakeon-LAN™ capability. It utilizes a signal-detect function that monitors the media interface for the presence of a link to determine when to automatically power-down the PHY. The Station Manager is in control of this mode. The PHY then ‘wakes up’ at a programmable interval and attempts to ‘wake-up’ the link partner PHY by sending either a fast link pulse (FLP) over copper media or a Clause 37 restart signal over optical media. The Enhanced ActiPHY™ power management mode can be set at startup (Refer to Section 19: "Hardware Configuration Using CMODE Pins" and Section 20: "EEPROM Interface" for details) or at any time during normal operation by writing to MII Register 28.6. 16.1 Operation in Enhanced ActiPHY Mode There are three PHY operating states when Enhanced ActiPHYTM mode is enabled: • Low power state • LP Wake up state • Normal operating state (link up state) The PHY switches between the low power state and LP wake up state at a programmable rate (sleep timer) until signal energy has been detected on the media interface pins. When signal energy is detected, the PHY enters the normal operating state. When the PHY is in the normal operating state and link is lost, the PHY returns to the low power state after the link status timeout timer has expired. After reset, the PHY enters the low power state. When autonegotiation is enabled in the PHY, the ActiPHYTM state machine will operate as described above. If autonegotiation is disabled and the link forced to 10BT or 100BTX modes while the PHY is in the low power state, the PHY continues to transition between the low power and LP Wake up states until signal energy is detected on the media pins. At that time, the PHY transitions to the normal operating state and stays in that state even when the link is dropped. If autonegotiation is disabled while the PHY is in the normal operation state, the PHY stays in that state when the link is dropped and does not transition back to the low power state. Low Power State Signal Energy Detect on Media (CAT5 or Fiber) FLP or Clause 37 Restart signal sent Sleep timer expires Timeout timer expires and Auto-negotiation enabled LP Wake-up State Normal Operation Figure 29. Enhanced ActiPHY State Diagram 60 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 16.2 Low power state In the low power state, all major digital blocks are powered down. However the following functionality is provided: • SMI interface (MDC/MODDEF1, MDIO/MODDEF2, MDINT) • CLKOUTMAC and CLKOUTMICRO In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low power state and transitions to the Normal operating state when signal energy is detected on the media. This happens when the PHY is connected to one of the following: • Auto-negotiation capable link partner • Auto-negotiation incapable (blind/forced) 100BTX only link partner • Auto-negotiation incapable (blind/forced) 10BT only link partner • Auto-negotiation capable optical link partner over fiber • Auto-negotiation incapable (blind/forced) 1000BASE-X optical link partner over fiber • Another PHY in Enhanced ActiPHY LP Wake Up state In the absence of signal energy on the media pins, the PHY will transition from the low power state to the LP Wake up state periodically based on the programmable sleep timer. Two register bits (MII Register bits 28.1:0) are provided to program the value of the sleep timer. The sleep timer can be programmed to 2'b00 (1sec), 2'b01 (2sec), 2'b10 (3sec) or 2'b11 (4sec). The default value is 2 seconds. The actual sleep time duration is randomized by -80ms to +60ms to avoid two PHYs in Enhanced ActiPHY mode from entering a lock-up state. 16.3 LP Wake up state In this state, the PHY attempts to wake up the link partner. One complete FLP (Fast Link Pulse) is sent on both pairs A and B of the CAT5 media. For the optical Media, a base page of all zeros (Clause 37 restart signal) is sent for 30ms. In this state the following functionality is provided- • SMI interface (MDC/MODDEF1, MDIO/MODDEF2, MDINT) • CLKOUTMAC and CLKOUTMICRO After sending signal energy on the relevant media, the PHY returns to the Low power state. 16.4 Normal operating state In this state, the PHY establishes a link with a link partner. When the media is unplugged or the link partner is powered down, the PHY waits for the duration programmed through a link status time-out timer and then enters the low power state. The Link Status Time-out timer can be programmed to 2'b00 (1sec), 2'b01 (2sec), 2'b10 (3sec), or 2'b11 (4sec). The default value for this timer is 2 seconds. 61 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 17 Ethernet In-line Powered Device Support 17.1 Cisco In-Line Powered Device Detection This feature is used for detecting in-line powered devices in Ethernet network applications. The VSC8211's in-line powered device detection mode can be part of a system that allows for IP-phone and other devices to receive power from an Ethernet cable, similar to office digital phones receiving power from a PBX (Private Branch Exchange) office switch via the phone cable. This can eliminate the need for an IP-Phone to have an external power supply, since the Ethernet cable provides power. It also enables the in-line powered device to remain active during a power outage (assuming the Ethernet switch is connected to an uninterrupted power supply, battery, back-up power generator, etc.). This mode is disabled by default and must be enabled in order to perform in-line powered device detection. Please refer to additional information at http://www.cisco.com/en/US/ products/hw/phones/ps379/products_tech_note09186a00801189b5.shtml for additional information. 17.2 In-Line Power Ethernet Switch Diagram Gigabit Switch/M AC M AC Interface Processor Control SM I VSC8211 10/100/1000BASE-T PHY IN-LINE PO W ER SUPPLY UNIT X-form er R J-45 I/F CAT-5 Figure 30. In-line Powered Ethernet Switch Diagram 17.3 In-Line Powered Device Detection (Cisco Method) This section describes the flow process an Ethernet switch must perform in order to process in-line power requests made by a link partner (LP) capable of receiving in-line power. 1. The in-line powered device detection mode is enabled by setting MII Register bit 23E.10 = 1 and ensuring that the Auto-Negotiation Enable Bit is set (MII Register 0.12 = 1). An interrupt can also be asserted on the MDINT pin when in-line power is needed. This is set by MII Register 25.9 = 1 and ensuring MII Register 25.15 = 1 in order to enable the MDINT pin. 2. The PHY will then start sending a special Fast Link Pulse (FLP) signal to the LP. MII Register 23E.9:8 will equal 00 during the search for devices needing in-line power. 62 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 3. The PHY monitors for the special FLP signal looped back by the LP. An LP device capable of receiving in-line power will loop back the special FLP pulses when it is in a powered-down state. This is reported when MII Register 23E.9:8 = 01. If enabled, an interrupt on the MDINT pin will also be asserted. This can be verified as an in-line power detection interrupt by reading MII Register 26.9 = 1, which will subsequently be cleared and the interrupt de-asserted after the read. If an LP device does not loop back the special FLP after a specific time, then MII Register 23E.9:8 = 10. 4. If the PHY reports that the LP needs in-line power, then the Ethernet switch needs to enable in-line power on this port external of the PHY. 5. The PHY automatically disables in-line powered device detection after Event #3 above and now changes to the normal Auto-negotiation process. A link is then auto-negotiated and established when the link status register is set (MII Register bit 1.2 = 1). 6. In a link down event (MII Register bit 1.2 = 0), the in-line power should be disabled to the in-line powered device external to the PHY. The PHY will disable the normal auto-negotiation process and re-enable in-line powered device detection mode. 17.4 IEEE 802.3af (DTE Power via MDI) The VSC8211 is fully compatible with switch designs which are intended for use in systems that supply power to the DTE (Data Terminal Equipment) via the MDI (Media Dependent Interface, or twisted pair cable), as specified by IEEE 802.3af standard (Clause 33). 63 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 18 Advanced Test Modes 18.1 1000BASE-T Ethernet Packet Generator (EPG) For system-level debugging and in-system production testing, the VSC8211 includes an Ethernet packet generator. This can be used to isolate problems between the MAC and PHY and between a local PHY and remote link partner. It is intended for use with lab testing equipment or in-system test equipment only, and should not be used when the VSC8211 is connected to a live network. To use the EPG, it must be enabled by writing a “1” to Extended MII Register 29E.15. This effectively disables all MAC-interface transmit pins and selects the EPG as the source for all data transmitted onto the VSC8211 media interface. For this reason, packet loss will occur if the EPG is enabled during transmission of packets from MAC to PHY. The MAC receive pins will still be active when the EPG is enabled, however. If it is necessary to disable the MAC receive pins as well, this can be done by writing a “1” to MII Register bit 0.10. When a “1” is written to Extended MII Register Bit 29E.14, the VSC8211 will begin transmitting IEEE802.3 layer-2 compliant packets with a data pattern of repeating 16-bit words as specified in Extended MII Register 30E. The source and destination addresses for each packet, packet size, interpacket gap, FCS state, and transmit duration can all be controlled through Extended MII Register 29E. Note that if Extended MII Register Bit 29E.13 is cleared, Extended MII Register Bit 29E.14 will be cleared automatically after 30,000,000 packets have been transmitted. 18.2 1000BASE-T CRC Counter When the EPG is enabled, a bad-CRC counter is also available for all incoming packets. This counter is available in Extended MII Register Bits 23E.7:0 - CRC Counter and is automatically cleared when read. 18.3 Far-end Loopback Far-end loop back mode, when enabled (MII Register bit 23.3 = 1), forces incoming data from a link partner on the current media interface to be retransmitted back to the link partner on the media interface as shown in the figure below. In addition, the incoming data will also appear on the receive data pins of the MAC interface. Data present on the transmit pins of the MAC interface are ignored in this mode. This loop back mode is available in both Serial and Parallel MAC PHY operating modes. For more information, refer to “Register 23 (17h) – PHY Control Register #1” on page 108. Link Partner RX VSC8211 RXD MAC CAT-5 or Fiber TX TXD Figure 31. Far-end Loopback Block Diagram 18.4 Near-end Loopback When Near-end loop back is set (MII Register bit 0.14 = 1), the Transmit Data (TXD) on the MAC interface is looped back onto the Receive Data (RXD) pins to the MAC as shown in the figure below. In this mode, no signal is transmitted over the network media. This loop back mode in available in both Serial MAC and Parallel MAC PHY Operating modes. 64 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Link Partner RX VSC8211 RXD MAC CAT-5 or Fiber TX TXD Figure 32. Near-end Loopback Block Diagram 18.5 Connector Loopback Connector Loopback allows for the twisted pair interface to be looped back externally. In this mode the PHY must be connected to a loopback connector or a loopback cable. For this loopback, pair A should be connected to pair B and pair C to pair D. This loopback will work in all speeds selected for the interface. A Receive Data VSC8211 B MAC C Transmit Data D Figure 33. Connector Loopback Block Diagram The autonegotiation, speed, and duplex can be configured using MII registers 0,4 and 9. For 1000BT connector loopback only the following additional writes are required in the specific order. 1. Master/Slave configuration forced to Master (MII Register Bits 9.12:11 = 11) 2. Enable 1000BT connector loopback (MII Register 24.0 = 1) 3. Disable pair swap correction (MII Register Bit 18.5=1) 4. Disable autonegotiation and force 1000BT link (MII Register Bit 0.12=0, MII Register Bit 0.6=1, and MII Register Bit 0.12=0) and force either full or half duplex (MII Register Bit 0.8=0 or 1). This loopback is also available in the 100BASE-FX mode. 65 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 19 Hardware Configuration Using CMODE Pins Each of the eight CMODE pins (CMODE[7:0]) are used to latch a four bit value at PHY reset. A total of thirty two CMODE configuration bits are set at reset. Each CMODE bit represents the default value of a particular PHY register and therefore sets a default PHY operating conditions at startup. 19.1 Setting the CMODE Configuration Bits The CMODE bits are set by connecting each CMODE pin to either VDD33A or VSSS (ground) through an external 1% resistor. The four bit value latched by the PHY on each CMODE pin depends upon the value of the resistor used to pull-up or pull-down the CMODE pin. CMODE resistor values and connections are defined in the following table: Table 25. CMODE Pull-up/Pull-down Resistor Values CMODE bit 3 value CMODE bit 2 value CMODE bit 1 value CMODE bit 0 value 0 0 0 0 0 GND 0 0 0 1 2.26k GND 0 0 1 0 4.02k GND 0 0 1 1 5.90k GND 0 1 0 8.25k GND 0 1 0 1 12.1k GND 0 1 1 0 16.9k GND 0 1 1 1 22.6k GND 1 0 0 0 0 VDD33A 1 0 0 1 2.26k VDD33A 1 0 1 0 4.02k VDD33A 1 0 1 1 5.90k VDD33A 1 1 0 0 8.25k VDD33A 1 1 0 1 12.1k VDD33A 1 1 1 0 16.9k VDD33A 1 1 1 1 22.6k VDD33A 0 CMODE Resistor Value Tied to VDD33A or GND 19.2 CMODE Bit descriptions The following table outlines the mapping of each CMODE bit to a PHY operating condition parameter. Each of the PHY operating condition parameters is described in detail in Table 27: “PHY Operating Condition Parameter Description”. 66 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 26. CMODE Bit to PHY Operation Condition Parameter Mapping CMODE Pin Name ‘CMODE Bit’ to ‘PHY Operating Condition Parameter’ Mapping Bit 3 Bit 2 Bit 1 Bit 0 CMODE0 PHY Address[3] PHY Address[2] PHY Address[1] PHY Address[0] CMODE1 SFP Mode Disable PHY Address[4] SIGDET pin direction SerDes Line Impedance CMODE2 PHY Operating Mode[3] PHY Operating Mode[2] PHY Operating Mode[1] PHY Operating Mode[0] CMODE3 LED Control[1] SQE Enable 10BASE-T Echo On CMODE4 LED Control[0] Pulsing Enable Auto-negotiation AdverMII Register View tisement Control[0] CMODE5 RGMII/RTBI Transmit RGMII/RTBI Transmit RGMII/RTBI Receive RGMII/RTBI Receive Path Timing compensa- Path Timing compensa- Path Timing compensa- Path Timing compensation[1] tion[0] tion[1] tion[0] CMODE6 PICMG Miser Mode Enable SIGDET pin Polarity Enhanced ActiPHYTM Enable CLKOUTMICRO Frequency CMODE7 Linkxxxx/Act Behaviour Link Speed Auto-Downshift Enable Flow Control[1] Flow Control[0] 67 of 165 VMDS-10105 Revision 4.1 October 2006 Auto-negotiation Advertisement Control[1] VSC8211 Datasheet Each of the PHY Operating Condition Parameters mentioned in the Table 26 above is described in detail in Table 27. Table 27. PHY Operating Condition Parameter Description PHY Operating CMODE Pin Name and Bit Condition Parameter Value Position Name 31-0 PHY Address[4:0] CMODE1[2],CMODE0[3:0] Description Sets the PHY Address used to access the PHY Registers when the PHY’s SMI is in IEEE mode. The value latched is reflected in Register 23E (17h) - Extended PHY Control Register #4, page 129, bits 23.15:11. These CMODE bits set the default PHY Operating Mode by setting the default values of MII Register 23 bits 15:12 and 2:1. For more information, see Register 23 (17h) – PHY Control Register #1, page 108. 0000 802.3z SerDes to CAT5 Media, Clause 37 auto-negotiation autosense enabled. 0001 RGMII with Copper/Fiber Auto Media Sense (Fiber Preference). 0010 GMII to Fiber. 0011 GMII/MII with Copper/Fiber Auto Media Sense (Fiber Preference). 0100 802.3z SerDes to CAT5 Media, Clause 37 disabled. 0101 SGMII to CAT5 Media, SCLK enabled. PHY Operating Mode[3:0] CMODE2[3:0] 0110 RGMII to CAT5 Media. 0111 RGMII to Fiber Media. 1000 GMII/MII to CAT5 Media. 1001 TBI to CAT5 Media, Clause 37 auto-negotiation auto-sense enabled. 1010 802.3z SerDes to CAT5 Media, Media Converter Mode. 1011 TBI to Fiber Media. 1100 RTBI to CAT5 Media, Clause 37 auto-negotiation auto-sense enabled. 1101 Serial MAC to Fiber Media, SCLK enabled. 1110 802.3z SerDes to CAT5 Media, Clause 37 enabled. 1111 SGMII to CAT5 Media, SCLK disabled. This sets the default behavior of the LED pins LED[4:0] by setting the startup values of MII “Register 27 (1Bh) – LED Control Register” on page 117. LED Control[1:0] Pulsing Enable CMODE3[3],CMODE4[3] CMODE4[2] 00 LED[4:0] = {Duplex/Collision, Link/Activity, Link10/Activity, Link100/ Activity, Link1000/Activity}(MII Reg 27 = 0000h) 01 LED[4:0] - {Activity, Duplex/Collision, Duplex/Collision, Link10/100/ Activity, Link/Activity} (MII Reg 27 = 5540h) 10 LED[4:0] - {Link Fault, Fiber Media Selected, Link/Activity, Link/ Activity, Fault} (MII Reg 27 = AA80h) 11 LED[4:0] - {Tx, Rx, Tx, Link100/1000/Activity, Rx} (MII Reg 27 = FFC0h) This sets the default power saving mode of the LED pins LED[4:0] by setting the startup value of MII Register bit 27.4 Enable 5Khz, 20% duty cycle LED pulsing for power savings 1 0 LED pulsing disabled 68 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 27. PHY Operating Condition Parameter Description (continued) PHY Operating CMODE Pin Name and Bit Condition Parameter Value Position Name Link/Activity and Linkxxxx/Activity behaviour RGMII/RTBI Transmit Path Timing Compensation[1:0] RGMII/RTBI Receive Path Timing Compensation[1:0] CMODE7[3] Description This sets the LED behaviour by setting the default values of MII Register 27.2:1 . Link function indicated link status only. 1 0 All link function blinks or flashes when activity is present. Blink or flash behavior is selected by the Blink/Pulse-stretch Enable and Blink/Pulse-stretch rate bits. Sets the RGMII/RTBI Transmit Path Timing compensation. This timing compensation adds a configurable delay to the signal on the TXC pin. These CMODE bits set the default value of MII Register 23.11:10. CMODE5[3:2] 00 2.0ns 01 2.5ns 10 No skew 11 1.5ns Sets the RGMII/RTBI Receive Path Timing compensation. This timing compensation adds a configurable delay to the RXC signal internal to the chip. These CMODE bits set the default value of MII Register 23.9:8. CMODE5[1:0] 00 2.0ns 01 2.5ns 10 No skew 11 1.5ns These CMODE bits set the default auto-negotiation advertisement by setting the initial values of MII Registers 4 and 9. Auto-negotiation Advertisement Control[1:0] Flow Control[1:0] CMODE3[0],CMODE4[1] CMODE7[1:0] 00 10/100/1000BASE-T HDX, 10/100/1000BASE-T FDX 01 10/100BASE-T HDX, 10/100/1000BASE-T FDX 10 10/100BASE-T HDX, 10/100BASE-T FDX 11 1000BASE-T FDX 00-11 Sets the default value of the Flow Control bits of MII Register 4. The value on these CMODE pins is the default value of MII Register 4.11:10 in Clause 28 Register View Mode and the default value of MII Register 4.8:7 in Clause 37 Register View Mode. The MII Register View is set by CMODE bit CMODE4[0] (page 70). 69 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 27. PHY Operating Condition Parameter Description (continued) PHY Operating CMODE Pin Name and Bit Condition Parameter Value Position Name Description This CMODE bit sets the default value of MII Register 21E.15. SFP Mode Disable SIGDET pin direction SerDes Line Impedance 0 This sets MII Register 21E.15 = 1. Sets the following PHY defaults: • TXDIS/SRESET is active high i.e. behaves like TXDIS. • MODDEF0/CLKOUTMAC pin functions like MODDEF0 i.e this pin is asserted low by the PHY once the EEPROM interface is released for access through the SMI interface. • RXLOS/SIGDET pins functions like the RXLOS. • The SMI interface is set in MSA mode. 1 This sets MII Register 21E.15 = 0. Sets the following PHY defaults: • TXDIS/SRESET is active low i.e. behaves like SRESET. • MODDEF0/CLKOUTMAC pin functions like CLKOUTMAC i.e this pin drives out a 125Mhz clock. • RXLOS/SIGDET pin functions like SIGDET. • The SMI interface is set in IEEE mode. CMODE1[3] CMODE1[1] CMODE1[0] The value of this bit is valid in non-SFP mode when CMODE bit CMODE1[3] is 1. This CMODE bit sets the direction of the SIGDET pin by setting the default value of Extended MII Register 19E.1 0 Input 1 Output Sets the internal end termination resistance value of the Serial MAC/ Media Interface Input pins. 0 50 Ω 1 75Ω Sets the default value of MII Register 22.12. SQE Enable CMODE3[2] 0 SQE Disabled (MII Register 22.12 = 1) 1 SQE Enabled (MII Register 22.12 = 0) Sets the default value of MII Register 22.13. 10BASE-T Echo On MII Register View PICMG Miser Mode Enable CMODE3[1] CMODE4[0] 0 10BASE-T Echo disabled (MII Register 22.13 = 1) 1 10BASE-T Echo Enabled (MII Register 22.13 = 0) Sets the default Register View of the standard IEEE specified Registers (MII Register 0 through MII Register 15). 0 Clause 28 view (specified for 1000BASE-T devices) 1 Clause 37 view (specified for 1000BASE-X devices) Sets the default value of MII Register 24.12. Putting the PHY in this mode reduces power consumption. This mode is suitable for applications where the signal to noise ratio on the CAT-5 media is high, such as ethernet over the backplane. CMODE6[3] See Section 12: "Transformerless Operation for PICMG 2.16 and 3.0 IPbased Backplanes" on page 45 for more information. 0 PICMG Miser Mode Disabled 1 PICMG Miser Mode Enabled 70 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 27. PHY Operating Condition Parameter Description (continued) PHY Operating CMODE Pin Name and Bit Condition Parameter Value Position Name SIGDET pin Polarity Enhanced ActiPHYTM Enable CMODE6[2] The value of this bit is valid in non-SFP mode i.e. when CMODE bit CMODE1[3] is 1. This CMODE bit sets the polarity (active high or active low) of the SIGDET pin by setting the default value of Extended MII Register 19E.0. 0 Active High 1 Active Low This CMODE bit sets the default value of MII Register 28.6. CMODE6[1] 0 Enhanced ActiPHYTM Mode Disabled 1 CLKOUTMICRO FreCMODE6[0] quency Link Speed AutoDownshift Enable Description Enhanced ActiPHYTM Mode Enabled This bit sets the default value of Extended MII Register 20E.8. 0 4Mhz 1 125 MHz Sets the default value of Extended MII Register 20E.4. CMODE7[2] 0 Link Speed Auto-Downshift Disabled 1 Link Speed Auto-Downshift Enabled 19.3 Procedure For Selecting CMODE Pin Pull-up/Pull-down Resistor Values 1. Using the descriptions in Table 27 column D (“Description”), choose the desired PHY operating condition parameter values from Column C (“Value”). 2. Using Table 27 Column B (“CMODE Pin Name and Bit Position”) and the chosen PHY operating condition parameter values, enter the value of each CMODE pin in Table 26: “CMODE Bit to PHY Operation Condition Parameter Mapping”. 3. Choose the value of each CMODE pull-up or pull-down resistor from Table 25: “CMODE Pull-up/Pull-down Resistor Values” based on the CMODE Bit values in Table 26. 71 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 20 EEPROM Interface The EEPROM Interface consists of the EEDAT and EECLK pins of the PHY. If this interface is used, these pins should connect to the SDA and SCL pins respectively of a serial EEPROM that is compatible with the AT24xxx series of ATMEL EEPROMs. The EEPROM interface on the VSC8211 serves the following purposes: • It provides the PHY with the ability to self configure its internal registers. • The system manager can access the EEPROM to obtain information pertaining to the system/module configuration. • A single EEPROM can be shared among multiple PHYs for their custom configuration. The PHY detects the EEPROM based on the presence of a pull-up on the EEDAT pin. It is initialized using the configuration EEPROM (if present) under the following conditions: • RESET deassertion. • TXDIS/SRESET deassertion and Extended MII Register 21E.14 is set. • S/W reset (MII Register 0.15) is asserted and Extended MII Register 21E.14 is set. If an EEPROM is present, the start-up control block looks for a “Vitesse Header” (value:16’hBDBD’) at addresses 0 and 1 of the EEPROM. The address is incremented by 256 until the Vitesse Header is found. If the Vitesse Header is not found, or no EEPROM is connected, the VSC8211 bypasses the EEPROM read step. Once the Vitesse header is located, the EEPROM Interface block of the PHY searches for its PHY address in bit position 7:3 in the subsequent EEPROM locations. Once the PHY address is located, the 11 bit EEPROM address location for the start of the configuration script is read. At this point, the PHY begins reading from this 11 bit EEPROM address and initializes its Register values based on the EEPROM configuration script contents. For more information see Table 28, “Configuration EEPROM Data Format,” on page 73. The total number of EEPROM bytes needed for a configuration script is equal to: ((Number of Register writes) * 3 + 2 (BDBD) + 2 (PHY address and Configuration Script Address) + 2 (Length of configuration script)). Data is read from the EEPROM sequentially (at 50 Khz, or 50 kbits/s) until all PHY Register are set. Once all of the PHY registers are set, the PHY enters the ‘NORMAL STATE’ (Section 21: "PHY Startup and Initialization"). If the PHY is in ‘NORMAL STATE’ state, the user can access the EEPROM connected to the EEPROM interface through the SMI. If the SMI is in IEEE mode, the EEPROM can be accessed via the SMI using Extended MII Registers 21E and 22E. If the SMI is in MSA mode, the EEPROM can be accessed directly via the SMI i.e. the PHY behaves as if the MODDEF2 and MODDEEF1 pins of the SMI are directly connected to the EEDAT and EECLK pins of the PHY.1 One exception is the memory portion with device/page address ‘110’. This is reserved for the PHY Register access when the PHY’s SMI is set in MSA mode. If an EEPROM is present, but the EEPROM does not acknowledge (according to the ATMEL EEPROM protocol), the VSC8211 waits for an acknowledge for approximately 3 seconds. If there is no acknowledge within 3 seconds, the VSC8211 will abort and continue into normal operation. 1EEPROM memory with device address ‘110’ cannot be accessed directly when the SMI is in MSA mode. This device address is reserved for PHY Register access in MSA mode. To access EEPROM with device address ‘110’ in MSA mode Extended MII Registers 21E and 22E should be used. 72 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 20.1 Programming Multiple VSC8211s Using the Same EEPROM To prevent contention on the 2 wire bus when multiple PHYs use the same EEPROM for initialization, the EEPROM start-up block of each VSC8211 monitors the bus for (PHY Address[4:0] + 1) * 9 + 92 clock cycles for no bus activity and only then attempts to access the EEPROM bus. PhyAddress[4:0] is chosen because these are the PHY Address bits that are unique to each VSC8211. (i.e VSC8211 with lowest PHY Address gets priority on this bus.) R E F C L K S o u rc e R E S E T S o u rc e S C L EECLK EEDAT V S C 8 2 1 1 (2 ) EECLK EEDAT V S C 8 2 1 1 (1 ) E E P R O M S D A Figure 34. EEPROM Interface Connections NOTE: The same clock must be used for each VSC8211’s REFCLK input. In addition, the RESET pin for each VSC8211 must be driven from the same source to ensure that the reference clock modes within each device are correctly set. This prevents using the CLKOUTMAC or CLKOUTMICRO output from one VSC8211 to drive the clock input of another VSC8211, if the devices are sharing the same EEPROM. Table 28. Configuration EEPROM Data Format Address Contents ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- O+7 Data to be written (LSB) O+6 Data to be written (MSB) O+5 RegAddress b O+4 Data to be written (LSB) O+3 Data to be written (MSB) O+2 RegAddress a O+1 Number of PHY Register writes *3[7:0] {bpage_addr3,s_ Number of PHY Register writes *3[15:8] addr3} = O 73 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 28. Configuration EEPROM Data Format (continued) Address Contents ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- ------------- ---------------------------------------------------- M+7 Data to be written (LSB) M+6 Data to be written (MSB) M+5 RegAddress b M+4 Data to be written (LSB) M+3 Data to be written (MSB) M+2 RegAddress a M+1 Number of PHY Register writes *3[7:0] {bpage_addr2,s_ Number of PHY Register writes *3[15:8] addr2} = M ------------- ---------------------------------------------------- N+7 Data to be written (LSB) N+6 Data to be written (MSB) N+5 RegAddress b N+4 Data to be written (LSB) N+3 Data to be written (MSB) N+2 RegAddress a N+1 Number of PHY Register writes *3[7:0] {bpage_addr1,s_ Number of PHY Register writes *3[15:8] addr1} = N ------------- ---------------------------------------------------- 7,263,519,.. Starting address for initializing PHY3 s_addr3 6,262,518,.. {PHY Address 1[4:0], 3’bpage_addr3} 5,261,517,.. Starting address for initializing PHY2 s_addr2 4,260,516,.. {PHY Address 2[4:0], 3’bpage_addr2} 3,259,515,.. Starting address for initializing PHY1 s_addr1 2,258,514,.. {PHY Address 1[4:0], 3’bpage_addr1} 1,257,513.. 8’hBD 0,256,512... 8’hBD Using the EEPROM data format shown in Table 28 enables multiple PHYs to be initialized in a similar way by reading the same locations from the EEPROM. If the PHYs have to be initialized differently, then the 'Address pointers' will differ for each PHY, along with different PHY configuration data values. 74 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 21 PHY Startup and Initialization The PHY Startup and Initialization sequence is detailed in the flowchart below. P H Y S ta r tu p a n d In itia liz a tio n A S ta r t - 3 .3 v s u p p ly is u p B N C If R E S E T z = 1 D riv e o u t C L K O U T M A C a n d C L K O U T M IC R O if e n a b le d d u rin g In itia lz a tio n . N Y N Is e x te r n a l 1 .2 v s u p p ly u p Y Is T X D IS /S R E S E T z d e a s s e rte d ( T h e a s s e rtio n p o la r ity is b a s e d o n s e ttin g o f E x te n d e d M II re g is te r 2 1 E .1 5 , w h ic h c a n b e in itia liz e d u s in g H a rd w a re o r E E P R O M In itia liz a tio n ) N Is R E F C L K in p u t p r e s e n t Y L a tc h E E D A T ,P L L M O D E ,O S C D IS z a n d M D IN T z p o la r ity u s in g in te r n a lly g e n e r a te d ris in g e d g e Y 1 .P e rfo m H a rd w a re In itia liz a tio n - i.e . o v e rw r ite d e fa u lt P H Y R e g is te r v a lu e s b a s e d o n r e s is to r v a lu e s o n C M O D E [7 :0 ] 2 .S to re s ta rtu p C M O D E in itia liz a tio n v a lu e s 3 . S e t In te rn a l v a ria b le S R = 0 . If S R = 1 Y If E E D A T = 1 If M II R e g is te r 2 2 .9 ‘S tic k y R e s e t E n a b le ’= 0 (O n R E S E T z d e a s s e rtio n th is b it w ill b e s e t to 1 ) Y P e rfo r m E E P R O M In itia liz a tio n - i.e . o v e rw r ite d e fa u lt P H Y R e g is te r v a lu e s u s in g c o n fig u ra tio n E E P R O M d a ta Y N 1 .P e r fo m In itia liz a tio n - i.e . o v e rw r ite d e fa u lt P H Y R e g is te r v a lu e s b a s e d o n s to re d C M O D E v a lu e s . N A N If E x te n d e d M II R e g is te r 2 1 E .1 4 ‘R e r e a d E E P R O M o n s /w re s e t’= 1 (O n R E S E T z d e a s s e rtio n th is b it w ill b e s e t to 0 ) Y NORM AL STATE S ta rt - 3 .3 v s u p p ly is u p If E E D A T = 1 N N Y Is T X D IS / SRESETz a s s e r te d Y SR =1 If R E S E T z = 0 N Y P e rfo r m E E P R O M In itia liz a tio n - i.e . o v e r w r ite d e fa u lt P H Y R e g is te r v a lu e s u s in g c o n fig u ra tio n E E P R O M d a ta B NORMAL STATE C 1 . E n t e r N o r m a l O p e r a t in g M o d e 2 . R e le a s e S M I f o r u s e r a c c e s s . Figure 35. PHY Startup and Initialization Sequence 75 of 165 VMDS-10105 Revision 4.1 October 2006 N VSC8211 Datasheet 22 PHY Operating Modes The PHY Operating Mode is set according to the value of MII Register 23.15:12,23.2:1. Refer to Section 19: "Hardware Configuration Using CMODE Pins" and Section 20: "EEPROM Interface" for details on PHY Operating Mode configuration at startup. The following table summarizes the PHY operating modes. Table 29. PHY Operating Modes Operating Mode Category MII Register CMODE2 23.15:12,2 [3:0] 3.2:1 MAC Interface Media Interface Other Settings 0011, 10 1000 GMII/MII CAT5 0011, 01 0010 GMII Fiber 0010, 01 0011 GMII/MII Auto Media Sense Fiber Preference 0010, 10 - GMII/MII Auto Media Sense CAT5 Preference1 0001, 10 Parallel MAC 0001, 01 PHY Operat0000, 01 ing Modes 0000, 10 0110 RGMII CAT5 0111 RGMII Fiber 0001 RGMII Auto Media Sense Fiber Preference - RGMII Auto Media Sense CAT5 Preference1 0110, 00 1001 TBI CAT5 With Clause 37 Auto-Negotiation Detection TBI Fiber2 0111, 01 1011 0100, 00 1100 RTBI CAT5 0101, 01 - RTBI Fiber2 With Clause 37 Auto-Negotiation Detection 1111, 00 0100 802.3z SerDes CAT5 Clause 37 disabled 1110, 01 1110 802.3z SerDes CAT5 Clause 37 enabled 1110, 10 1010 802.3z SerDes CAT5 Clause 37 enabled, Media Convertor Mode 1110, 00 0000 802.3z SerDes CAT5 With Clause 37 Auto-Negotiation Detection Serial MAC 1010, 01 PHY Operat- 1000, 01 ing Modes 1001, 01 1111 SGMII CAT5 625Mhz SCLK Clock Disabled 0101 SGMII CAT5 625MHz SCLK Clock Enabled 1101 Serial Serial Buffered Mode – With Clock Recovery3 1001, 00 SGMII CAT5 Modified Clause 37 auto-negotiation disabled, 625MHz SCLK Clock Enabled 1011, 00 SGMII CAT5 Modified Clause 37 auto-negotiation disabled, 625MHz SCLK Clock Disabled 1 In this mode the PHY does not drop the Fiber Media link if the CAT5 link comes up after the Fiber link has been established and therefore it is not a suitable mode for unmanaged applications. For more information on how to use this mode in managed applications, contact you Vitesse Semiconductor representative. PHY Registers are not supported in this mode. 3 In this mode, the PHY’s MAC and media interfaces are the same. Both interfaces can be either SGMII or 802.3z SerDes. 2 22.1 PHY Operating Mode Description Most of the PHY Operating Modes listed in Table 29: “PHY Operating Modes” are standard operating modes. Some of the nonstandard modes are described below: 22.1.1 Auto Media Sense (AMS) Media Interface PHY Operating Modes The VSC8211 can be configured for GMII/MII to AMS or RGMII to AMS Media Interface PHY Operating Modes. In these modes, the PHY continuously tries to establish a link on both the CAT5 and Fiber medias. When a link is established on the preferred media, the PHY turns off the non-preferred media interface. 76 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 22.1.2 Serial MAC to Serial Media PHY Operating Mode: In this mode, the high-speed serial data on the SDIP/SPIN input pins is routed to the RDP/RDN output pins and data from the TDP/TPN input pins is routed to the SDOP/SDON output pins. A 625MHz clock, recovered from the data on the SDIP/SDIN input pins, is driven out on the SCLKP/SCLKN outputs. See Section 9.4.10: "Serial MAC/Media Interface Signals" for more information. 23 IEEE802.3 Clause 28/37 Remote Fault Indication Support The VSC8211 is capable of both Clause-28 and Clause-37 autonegotiation. In addition, the VSC8211 can be configured for a register view corresponding to Clause-28 or Clause-37. However, in IEEE802.3, Clause-37 provides for two remote fault bits, while Clause-28 provides only a single remote fault bit. A third remote fault status bit is also located in MII Register Bit 1.4, which is independent of the register view. In instances where the register view is configured for a different IEEE Clause than the current autonegotiation advertisement, Extended MII Register -bits 16E.2:0 handle the mapping between autonegotiation and register view. These bits also control the result of MII Register bit 1.4 if a remote fault is detected in the link partner. There are four possible combinations of register view and autonegotiation. In each case, remote fault conditions are both transmitted by the local PHY and received from the link partner. Remote fault conditions in each of these are described below: Clause-28 autonegotiation with Clause-28 register view- One remote fault bit is received from the link partner and one bit is transmitted from the local PHY to the link partner. No special handling of registers 4/5, or MII Register bit 1.4 is necessary, as the two modes are identical. Clause-28 autonegotiation with Clause-37 register view- One remote fault bit is received from the link partner and must be mapped to two MII Register bits 5.13:12, as well as MII Register bit 1.4. Two remote fault MII Register bits 4.13:12 must be mapped to a single bit to transmit from the local PHY to the link partner. Clause-37 autonegotiation with Clause-28 register view- Two remote fault bits are received from the link partner and must be mapped to one MII Register bit 5.13, as well as MII Register bit 1.4. One remote fault MII Register bit 4.13 must be mapped to two bits to transmit from the local PHY to the link partner. Clause-37 autonegotiation with Clause-37 register view- Two remote fault bits are received from the link partner and two remote fault bits are transmitted from the local PHY to the link partner. No special handling of registers 4/5 is necessary. MII Register bits 5:13:12 must be mapped to MII Register bit 1.4. 77 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Extended MII Register 16E bits 2:1, the Remote Fault Mapping Mask, and bit 0, the Remote Fault Mapping OR, handle remote fault mapping. For more information, see Register 16E (10h) – Fiber Media Clause 37 Autonegotiation Control & Status, page 123. The functionality of these bits is summarized in the following tables: Table 30. Clause 28 Register View Remote Fault Transmitted to Link Partner Bit 4.13, Bit 16E.0, Bits 16E.2:1, Local Remote Remote Remote Fault Fault OR Fault Mask Value Transmitted to LP during Clause-28 Autonegotiation (combination 1, above) Value Transmitted to LP during Clause-37 Autonegotiation (combination 3, above) 0 x xx 0 00 1 x xx 1 Equal to bits 16E.2:1 Table 31. Clause 37 Register View Remote Fault Transmitted to Link Partner Bits 4.13:12, Bit 16E.0, Bits 16E.2:1, Local Remote Remote Remote Fault Fault OR Fault Mask 00 0 00 01, 10 or 11 0 01, 10 or 11 01, 10 or 11 1 xx Value Transmitted during Clause-28 Autonegotiation (combination 2, above) Value Transmitted during Clause-37 Autonegotiation (combination 4, above) 0 00 1, if bits 4.13:12 equal bits 16E.2:1 0, if bits 4.13:12 do not equal bits 16E.2:1 Equal to bits 4.13:12 1 Equal to bits 4.13:12 Table 32. Clause 28 Autonegotiation Link Partner Remote Fault Value Displayed LP Remote Bit 16E.0, Bits 16E.2:1, Value Displayed Remote Remote in Clause-28 View in Clause-37 View Fault Bit1 Fault OR Fault Mask Register Bit 1.4 Register Bit 1.4 1 Value Displayed Value Displayed in Clause-28 View in Clause-37 View Register Bit 5.13 Register Bits 5.13:12 (combination 1, above) (combination 2, above) 0 x xx 0 0 0 00 1 x 00 1 0 1 00 1 x 01, 10 or 11 1 1 1 Equal to bits 16E.2:1 This is the remote fault bit sent by the link partner during Clause-28 autonegotiation 78 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 33. Clause 37 Autonegotiation Link Partner Remote Fault 1 LP Remote Fault Bits1 Bit 16E.0, Remote Fault OR Bits 16E.2:1, Remote Fault Mask 00 x xx 0 0 1, if LP remote fault bits equal bits 16E.2:1 Equal to LP remote 0, if LP remote fault bits do fault bits not equal bits 16E.2:1 1 01, 10 or 11 0 xx 1, if LP remote fault bits equal bits 16E.2:1 0, if LP remote fault bits do not equal bits 16E.2:1 01, 10 or 11 1 xx 1 These are the remote fault bits sent by the link partner during Clause-37 autonegotiation 79 of 165 VMDS-10105 Revision 4.1 October 2006 Value Displayed in Clause-28 View Register Bit 5.13 (combination 3, above) Value Displayed in Register Bit 1.4 Value Displayed in Clause-37 View Register Bits 5.13:12 (combination 4, above) 00 Equal to LP remote fault bits VSC8211 Datasheet 24 PHY Register Set Conventions The user can control the PHY's features, operating modes, etc. by setting the PHY Registers to the desired values. The PHY provides access to its Registers via the Serial Management Interface. For details on PHY Register access, see Section 13 “Dual Mode Serial Management Interface (SMI),” page 45. 24.1 PHY's Register Set Structure The register access protocol, as defined by the IEEE 802.3 specification, reserves five bits for register addressing. This limits the register space to 32, 16 bit wide registers. Of these, registers addressed 0 through 15 are defined by the IEEE 802.3 specification and registers addressed 16 through 31 are vendor specific. To provide extensive feature control of the PHY, the vendor specific registers addressed 16 through 31 have been divided into two Page views, called PAGE0 and PAGE1, enabling access to 32 vendor specific registers instead of 16. PAGE0 is the default page view. To switch to PAGE1, write 0001h to PHY Register 31. To switch to PAGE0 write 0000h to PHY Register 31. Normal Page Registers 0 1 2 3 . . . . . . . 15 31 Extended Page Registers 16 17 18 19 . . . . . . . 30 16E 17E 18E 19E . . . . . . . 30E 0000 0001 Figure 36. Extended Page Register Diagram 80 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 24.2 PHY's Register Set Nomenclature Register Address Page View Naming Convention 0-15 - NA- MII Register 16-31 PAGE0 MII Register 16-31 PAGE1 Extended Page MII Register (Referred to with an ‘E’ after the register number e.g. 20E.15 is Page 1 Register 20 bit 15) 24.3 PHY Register Bit Types PHY Register bit types are defined in the table below: Register Bit Type Description R/W Read and Write, effective immediately RO Read Only (must be written ‘0’, unless specified otherwise) RO SC Read Only, Self Clears after Read LH Latched High, Clears after Read LL Latched Low, Clears after Read SC Self-Cleared RWSW Read and Write, effective after s/w reset. This register will read the new value only after s/w reset. “Sticky” refers to the behavior of the register bit(s) after a software reset. If an “S” appears in the sticky column, the corresponding bit(s) will retain their values after a software reset, as long as the correct MII register bit is set. For more information, see Section 25.3.23 “Register 22 (16h) – Control & Status Register,” page 106. If an “SS” appears in the sticky column, the corresponding bit(s) will retain their values after a software reset, regardless of the state of the register bit. 81 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 25 PHY Register Set 25.1 Clause 28/37 Resister View PHY registers 0 through 15 are implemented according to the IEEE 802.3 specification. According to this standard, the contents of MII Registers 4, 5, 6, 9 and 10 are different for 1000BASE-X PHYs and 1000BASE-T PHYs. Since the VSC8211 supports both Fiber (1000BASE-X) and CAT5 (1000BASE-T) media, it supports both register sets. In registers 0 through 15, the 1000BASE-T register set is referred to as the “Clause 28 View” and the 1000BASE-X register set is referred to as the “Clause 37 View”. The default register view is “Clause 28 View” for all PHY Operating Modes. To switch the Register View to “Clause 37 View”, set the “Register View” bit (MII Register 23.4). Refer to section 19, “Hardware Configuration Using CMODE Pins,” page 66, and section 20, “EEPROM Interface,” page 72 for details on Register View configuration at startup. • Please note that “Clause 37" Register View is allowed only in 'GMII/RGMII to CAT5/Fiber/AMS' category of PHY operating modes i.e. where MII Register 23.15:12,23.2:1 = 6'b00xxxx. 82 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 25.2 PHY Register Names and Addresses Table 34. PHY Register Names and Addresses Register Number Register Address (hex) Mode Control 0 00 Mode Status 1 01 PHY Identifier Register # 1 2 02 PHY Identifier Register # 2 3 03 Auto-Negotiation Advertisement 4 04 Auto-Negotiation Link Partner Ability 5 05 Register Name Auto-Negotiation Expansion 6 06 Auto-Negotiation Next-Page Transmit 7 07 Auto-Negotiation Link Partner Next Page Receive 8 08 1000BASE-T Control 9 09 1000BASE-T Status Register # 1 10 0A Reserved 11 0B Reserved 12 0C Reserved 13 0D Reserved 14 0E 1000BASE-T Status Register #2 15 0F Reserved 16 10 Reserved 17 11 Bypass Control 18 12 Reserved 19 13 Reserved 20 14 Reserved 21 15 Control & Status 22 16 PHY Control # 1 23 17 PHY Control # 2 24 18 Interrupt Mask 25 19 Interrupt Status 26 1A LED Control 27 1B Auxiliary Control & Status 28 1C Reserved 29 1D MAC Interface Clause 37 Autonegotiation Control & Status 30 1E Extended Page Access 31 1F Fiber Media Clause 37 Autonegotiation Control & Status 16E 10 SerDes Control 17E 11 Reserved 18E 12 SerDes Control Register # 2 19E 13 Extended PHY Control # 3 20E 14 EEPROM Interface Status and Control 21E 15 EEPROM Data Read/Write 22E 16 Extended PHY Control # 4 23E 17 Reserved 24E 18 Reserved 25E 19 83 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet Table 34. PHY Register Names and Addresses (continued) Register Number Register Address (hex) Reserved 26E 1A Reserved 27E 1B Reserved 28E 1C 1000BASE-T Ethernet Packet Generator (EPG) # 1 29E 1D 1000BASE-T Ethernet Packet Generator (EPG) # 2 30E 1E Register Name 84 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 25.3 MII Register Descriptions 25.3.1 Register 0 (00h) – Mode Control Register - Clause 28/37 View Register 0 (00h) – Mode Control Register - Clause 28/37 View Bit Name 15 Software Reset1 14 Near End Loopback 6, 13 Forced Speed Selection 12 Auto-Negotiation Enable 11 Power-Down 10 Isolate2 9 Restart Auto-Negotiation 8 Duplex Mode 7 Collision Test Enable 6 5:0 MSB for Speed Selection (see bit 13 above) Reserved Access States 1 = Reset asserted R/W SC 0 = Reset de-asserted 1 = Near End Loopback on R/W 0 = Near End Loopback off 00 = 10Mbps 01 = 100Mbps R/W 10 = 1000Mbps 11 = Reserved 1 = Auto-Negotiation enabled R/W 0 = Auto-Negotiation disabled 1 = Power-down R/W 0 = Power-up 1 = Disable Parallel MAC outputs R/W 0 = Normal Operation 1 = Restart MII R/W SC 0 = Normal operation 1 = Full duplex R/W 0 = Half duplex 1 = Collision test enabled R/W 0 = Collision test disabled Reset Value R/W 1 See “Forced Speed Selection” Above RO Sticky 0 0 10 1 0 0 0 0 0 000000 1 In MSA mode, when this bit is set, the PHY does not return the correct values for the subsequent register read operations. In order to read the correct PHY register values, the station manager must provide 70 clock cycles on the MODDEF1/MDC pin or perform two byte read operations on any eeprom address other than in page ‘110’ immediately following s/w reset. 2 When this bit is set, while the PHY is operating in one of the ‘Serial MAC/TBI/RTBI to CAT5 Media’ category of PHY operating modes. The PHY will drop the CAT5 Media link. Also, setting of this bit will not disable the clock output on SCLKP and SCLKN pins. 0.15 – Software Reset Writing a “1” to bit 0.15 initiates a software reset. Once Software Reset is asserted, the PHY is returned to normal operating mode and is ready for the next SMI transaction, so Software Reset always reads back “0”. Software Reset restores all SMI registers to their default states, except for registers marked with an “S” or “SS” in the sticky column. 0.14 – Near End Loopback When the Near End Loopback bit is set, the Transmit Data (TXD) on the MAC interface is looped back onto the Receive Data (RXD) pins to the MAC. In this mode, no signal is transmitted over the network media. The loopback mechanism works in all (10/100/1000) modes of operation. The operating mode is determined by bits 0.13 and 0.6 (forced speed selection). See section 18.4, “Near-end Loopback,” page 64 for more information. 0.13, 0.6 – Forced Speed Selection These bits determine the 10/100/1000 speed when Auto-Negotiation is disabled by clearing control bit 0.12. These bits are ignored if control bit 0.12 is set. These bits also determine the operating mode when Near End Loopback (bit 0.14) is set. 85 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 0.12 – Auto-Negotiation Enable After a power-up, or reset, the PHY automatically activates the Auto-Negotiation state machine, setting bit 0.12 to a “1”. If a “0” is written to bit 0.12, the Auto-Negotiation process is disabled and the present contents of the PHY’s SMI register bits determine the operating characteristics. Note that Auto-Negotiation is always required in 1000BASE-T mode. 0.11 – Power-Down Power-Down functions the same as Software Reset, except that it is not self-clearing, and that R/W SMI bits are not restored to their default states by Power-Down. The RGMII pins (except for SMI pins MDC, MDIO, and MDINT#) are electrically isolated during power-down. After Power-Down is released (i.e., set to “0”), the PHY will be ready for normal operation before the next SMI transaction. If Auto-Negotiation is enabled, the PHY will begin Auto-Negotiation immediately upon exiting Power-Down. 0.10 – Isolate When Isolate is asserted (i.e., set to “1”), all MAC outputs (except for MDIO) will be high impedance. Operation of the PHY is otherwise unaffected. For example, if Isolate is asserted while Auto-Negotiation is under way, Auto-Negotiation will continue unaffected. 0.9 – Restart Auto-Negotiation When Restart Auto-Negotiation is asserted (i.e., set to “1”), the Auto-Negotiation state machine will restart the Auto-Negotiation process, even if it is in the midst of an Auto-Negotiation process. This control bit is self-clearing, meaning that it will always return a “0” when read. 0.8 – Duplex Mode Bit 0.8 determines the duplex mode of the VSC8211 when Auto-Negotiation is disabled. Changes to the state of Duplex Mode while Auto-Negotiation is enabled are ignored. 0.7 – Collision Test Enable Collision Test allows the COL pin (pin B4 in GMII/MII Mode) to be tested during Near End Loopback. When Collision Test is enabled (by setting this bit), asserting TXEN will cause the COL output to go high within 512 bit times. De-asserting TXEN will cause the COL output go low within 4 bit times. The Collision Test should only be enabled when Near End Loopback is enabled. 0.5:0 – Reserved 25.3.2 Register 1 (01h) – Mode Status Register - Clause 28/37 View Register 1 (01h) – Mode Status Register - Clause 28/37 View Bit 15 14 13 12 11 10 9 8 7 Name 100BASE-T4 Capability 100BASE-X FDX Capability 100BASE-X HDX Capability 10BASE-T FDX Capability 10BASE-T HDX Capability 100BASE-T2 FDX Capability 100BASE-T2 HDX Capability Extended Status Enable Reserved Access RO RO RO RO RO RO RO RO RO 6 Preamble Suppression Capability RO 5 Auto-Negotiation Complete RO 4 Remote Fault RO LH States 1 = 100BASE-T4 capable 1 = 100BASE-X FDX capable 1 = 100BASE-X HDX capable 1 = 10BASE-T FDX capable 1 = 10BASE-T HDX capable 1 = 100BASE-T2 FDX capable 1 = 100BASE-T2 HDX capable 1 = Extended status information present in R15 1 = MF preamble may be suppressed 0 = MF preamble always required 1 = Auto-Negotiation complete 0 = Auto-Negotiation not complete 1 = Far-end fault detected 0 = No fault detected 86 of 165 VMDS-10105 Revision 4.1 October 2006 Reset Value 0 1 1 1 1 0 0 1 0 1 0 0 Sticky VSC8211 Datasheet Register 1 (01h) – Mode Status Register - Clause 28/37 View Bit 3 Name Auto-Negotiation Capability Access RO 2 Link Status RO LL 1 Jabber Detect RO LH 0 Extended Capability RO States 1 = Auto-Negotiation capable 1 = Link is up 0 = Link is down 1 = Jabber condition detected 0 = No jabber condition detected 1 = Extended register capable Reset Value 1 Sticky 0 0 1 1.15 – 100BASE-T4 Capability The VSC8211 is not 100BASE-T4 capable, so this bit is hard-wired to “0”. 1.14 – 100BASE-X FDX Capability The VSC8211 is 100BASE-X FDX capable, so this bit is hard-wired to “1”. 1.13 – 100BASE-X HDX Capability The VSC8211 is 100BASE-X HDX capable, so this bit is hard-wired to “1”. 1.12 – 10BASE-T FDX Capability The VSC8211 is 10BASE-T FDX capable, so this bit is hard-wired to “1”. 1.11 – 10BASE-T HDX Capability The VSC8211 is 10BASE-T HDX capable, so this bit is hard-wired to “1”. 1.10 – 100BASE-T2 FDX Capability The VSC8211 is not 100BASE-T2 FDX capable, so this bit is hard-wired to “0”. 1.9 – 100BASE-T2 HDX Capability The VSC8211 is not 100BASE-T2 HDX capable, so this bit is hard-wired to “0”. 1.8 – Extended Status Enable The VSC8211 is extended status capable, so this bit is hard-wired to “1”. 1.7 – Reserved 1.6 – Preamble Suppression Capability The VSC8211 accepts management frames on the SMI without preambles, so preamble suppression capability is hard-wired to “1”. The management frame preamble may be as short as 1 bit. 1.5 – Auto-Negotiation Complete When this bit is a “1”, the contents of Registers 4, 5, 6, 10 and 28 are valid. 1.4 – Remote Fault Bit 1.4 will be set to “1” if the Link Partner signals a far-end fault. The bit is cleared automatically upon a read if the far-end fault condition has been removed. 87 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 1.3 – Auto-Negotiation Capability The VSC8211 is Auto-Negotiation capable, so this bit is hard-wired to “1”. Note that this bit will read a “1” even if AutoNegotiation is disabled via bit 0.12. 1.2 – Link Status This bit will return a “1” when the VSC8211 link state machine has reached the “link pass” state, meaning that a valid link has been established. If the link is subsequently lost, the Link Status will revert to a “0” state. It will remain a “0” until Link Status is read while the link state machine is in the “link pass” state. 1.1 – Jabber Detect Note that Jabber Detect is required for 10BASE-T mode only. Jabber Detect will be set to “1” when the jabber condition is detected. Jabber Detect will be cleared automatically when this register is read. 1.0 – Extended Capability The VSC8211 has extended register capability, so this bit is hard-wired to “1”. 25.3.3 Register 2 (02h) – PHY Identifier Register #1 - Clause 28/37 View Register 2 (02h) – PHY Identifier Register #1 - Clause 28/37 View Bit Name Access 15:0 Organizationally Unique Identifier RO States OUI most significant bits (Vitesse OUI bits 3:18) Reset Value 0000000000001111 or (000Fh) Sticky 2.15:0 – PHY Identifier Register #1 Vitesse has been assigned an OUI from the IEEE of 0003F1h. Per IEEE requirements, only OUI bits 3 to 18 are used in this register. 25.3.4 Register 3 (03h) – PHY Identifier Register #2 - Clause 28/37 View Register 3 (03h) – PHY Identifier Register #2 - Clause 28/37 View Bit Name Access 15:10 Organizationally Unique Identifier RO 9:4 3:0 Vendor Model Number Vendor Revision Number RO RO States OUI least significant bits (Vitesse OUI bits 19:24) Vendor’s model number (IC) Vendor’s revision number (IC) Reset Value Sticky 110001 001011 = VSC8211 0001 = Silicon Revision C 3.15:10 – OUI Vitesse has been assigned an OUI from the IEEE of 0003F1h. Per IEEE requirements, only OUI bits 19 to 24 are used in this register. 3.9:4 - Vendor Model Number The Model no. of this IC is ‘001011’. 88 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 3.3:0 - Vendor Revision Number The current Revision Number of this IC is ‘0001’. 25.3.5 Register 4 (04h) – Auto-Negotiation Advertisement Register 25.3.5.1 Clause 28 View Register 4 (04h) – Auto-Negotiation Advertisement Register - Clause 28 View Bit 15 14 13 12 11 10 9 8 7 6 5 4:0 Name Next-Page Transmission Request Reserved Transmit Remote Fault Reserved Advertise Asymmetric Pause Advertise Symmetric Pause Advertise 100BASE-T4 Capability Advertise 100BASE-TX FDX Advertise 100BASE-TX HDX Advertise 10BASE-T FDX Advertise 10BASE-T HDX Advertise Selector Field Access R/W RO R/W RO R/W R/W R/W R/W R/W R/W R/W R/W States 1 = Next-Page transmission request 1 = Transmit remote fault 1 = Advertise Asymmetric Pause capable 1 = Advertise Symmetric Pause capable 1 = 100BASE-T4 capable 1 = 100BASE-TX FDX capable 1 = 100BASE-TX HDX capable 1 = 10BASE-T FDX capable 1 = 10BASE-T HDX capable Reset Value 0 0 0 0 CMODE CMODE 0 CMODE CMODE CMODE CMODE 00001 Sticky This register controls the advertised abilities of the local (not remote) PHY. The state of this register is latched when the AutoNegotiation state machine enters the ABILITY_DETECT state. Thus, any writes to this register prior to completion of AutoNegotiation as indicated by MII Register bit 1.5 should be followed by a re-negotiation for the new values to be properly used for Auto-Negotiation. Once Auto-Negotiation has completed, this register value may be read via the SMI to determine the highest common denominator technology. 4.15 – Auto-Negotiation Additional Next-Page Transmission Request The VSC8211 supports additional Next-Page transmission through MII Register bit 4.15. See description of MII Register bit 18.1 for more details on Next-Page exchanges. This bit is only supported on copper media. 4.14, 4.12 – Reserved 4.13 – Transmit Remote Fault This bit is used by the local MAC to communicate a fault condition to the link partner during auto-negotiation. This bit does not have any effect on the local PHY operation. This bit is automatically cleared following a successful negotiation with the Link Partner. Note that IEEE Clause-37 provides for two remote fault bits, while Clause-28 provides only a single remote fault bit. This discrepancy is handled in MII Extended Register bits 16E.2:1 - Remote Fault Mapping Mask and 16E.0 - Remote Fault Mapping OR. 4.11 – Advertise Asymmetric Pause Capability This bit is used by the local MAC to communicate Asymmetric Pause Capability to the link partner during auto-negotiation. This has no effect on PHY operation. Changing this bit in Clause-28 view will also change bit 4.8 in Clause-37 view. 4.10 – Advertise Symmetric Pause Capability This bit is used by the local MAC to communicate Symmetric Pause Capability to the link partner during autonegotiation. This has no effect on PHY operation. Changing this bit in Clause-28 view will also change bit 4.9 in Clause-37 view. 89 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 4.9:5 – Advertise Capability Bits 4.9:5 allow the user to customize the ability information transmitted to the Link Partner during auto-negotiation. By writing a “1” to any of these bits, the corresponding ability will be advertised to the Link Partner. Writing a “0” to any bit causes the corresponding ability to be suppressed from transmission. The state of these bits has no other effect on the operation of the local PHY. Resetting the chip restores the default bit values. Note that the default values of these bits indicate the true ability of the VSC8211. These bits are not available for read or write in Clause-37 view, but remain valid for CAT-5 copper media. 4.4:0 – Advertise Selector Field Since the VSC8211 is a member of the 802.3 class of PHYs, the Advertise Selector Field defaults to “00001”. These bits are R/W because the Ethernet standard requires them to be R/W. Changing the value of these bits has no effect on PHY operation. 25.3.5.2 Clause 37 View Register 4 (04h) – Auto-Negotiation Advertisement Register - Clause 37 View Bit 15 14 13:12 11:9 8 7 6 5 4:0 Name Next-Page Transmission Request Reserved Transmit Remote Fault Reserved Advertise Asymmetric Pause Advertise Symmetric Pause Advertise 1000BASE-X HDX Advertise 1000BASE-X FDX Reserved Access R/W RO R/W RO R/W R/W R/W R/W RO States 1 = Next-Page transmission request Reset Value 0 0 Remote fault transmission to link partner 00 000 1 = Advertise Asymmetric Pause capable CMODE 1 = Advertise Symmetric Pause capable CMODE 1 = 1000BASE-X FDX capable 1 1 = 1000BASE-X HDX capable 1 00000 Sticky 4.15 – Auto-Negotiation Additional Next-Page Transmission Request With copper media, this bit functions identically to Clause-28 view. Note, however, that the VSC8211 does not support nextpage transmission over fiber 1000BASE-X media. 4.14 - Reserved 4.13:12 - Transmit Remote Fault These bits are used by the local MAC to communicate a fault condition to the link partner during auto-negotiation. These bits do not have any effect on the local PHY operation. These bits are automatically cleared following a successful negotiation with the link partner. Note that IEEE Clause-37 provides for two remote fault bits, while Clause-28 provides only a single remote fault bit. This discrepancy is handled in MII Extended Register bits 16E.2:1 - Remote Fault Mapping Mask and 16E.0 - Remote Fault Mapping OR 4.11:9 - Reserved 4.8 – Advertise Asymmetric Pause Capability This bit is used by the local MAC to communicate Asymmetric Pause Capability to the link partner during auto-negotiation. This has no effect on PHY operation. Changing this bit in Clause-37 view will also change bit 4.11 in Clause-28 view. 4.7 – Advertise Symmetric Pause Capability This bit is used by the local MAC to communicate Symmetric Pause Capability to the link partner during autonegotiation. This has no effect on PHY operation. Changing this bit in Clause-37 view will also change bit 4.10 in Clause-28 view. 90 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 4.6:5 - Advertise 1000BASE-X Capability Bits 4.6:5 control the 1000BASE-X capability advertisement transmitted to the link partner for both fiber and copper media. Changing these bits in Clause-37 view will also change MII Register bits 9.9:8 in Clause-28 view. 4.4:0 - Reserved 25.3.6 Register 5 (05h) – Auto-Negotiation Link Partner Ability Register 25.3.6.3 Clause 28 View Register 5 (05h) – Auto-Negotiation Link Partner Ability Register - Clause 28 View Bit 15 14 13 12 11 10 9 8 7 6 5 4:0 Name LP Next-Page Transmit Request LP Acknowledge LP Remote Fault Reserved LP Asymmetric Pause Capability LP Symmetric Pause Capability LP Advertise 100BASE-T4 Capability LP Advertise 100BASE-TX FDX LP Advertise 100BASE-TX HDX LP Advertise 10BASE-T FDX LP Advertise 10BASE-T HDX LP Advertise Selector Field Access RO RO RO RO RO RO RO RO RO RO RO RO States 1 = LP NP transmit request 1 = LP acknowledge 1 = LP remote fault Reset Value 0 0 0 0 1 = LP Advertise Asymmetric Pause capable 0 1 = LP Advertise Symmetric Pause capable 0 1 = LP Advertise 100BASE-T4 capable 0 1 = LP 100BASE-TX FDX capable 0 1 = LP 100BASE-TX HDX capable 0 1 = LP 10BASE-T FDX capable 0 1 = LP 10BASE-T HDX capable 0 LP Advertise Selector Field 00000 Sticky 5.15 – LP Next-Page Transmit Request Bit 5.15 returns a “1” when the Link Partner implements the Next-Page function and has Next-Page information it wants to transmit. The state of this bit is valid when the Auto-Negotiation Complete bit (1.5) or the Page Received bit (6.1) is set, and the current media type is CAT-5 copper. 5.14 – LP Acknowledge Bit 5.14 returns a “1” when the Link Partner signals that it has successfully received the Link Code Word from the local PHY. The local PHY uses this bit for proper Link Code Word exchange, as defined in Clause 28 of IEEE 802.3. 5.13 – LP Remote Fault Bit 5.13 returns a “1” when the Link Partner signals that a remote fault (from its perspective) has occurred. The local PHY does not otherwise use this bit. Note that IEEE Clause-37 provides for two remote fault bits, while Clause-28 provides only a single remote fault bit. This difference is handled in Extended MII Register bits 16E.2:1 - Remote Fault Mapping Mask and 16E.0 Remote Fault Mapping OR. The state of this bit is valid when the Auto-Negotiation Complete bit (1.5) is set. 5.12 – Reserved 5.11 – LP Asymmetric Pause Capability The LP Asymmetric Pause Capability bit indicates whether the Link Partner has asymmetric pause capability. The state of this bit is valid when the Auto-Negotiation Complete bit (1.5) is set. 5.10 – LP Symmetric Pause Capability The LP Symmetric Pause Capability bit indicates whether the Link Partner supports symmetric pause frame capability. This bit is used by the Link Partner’s MAC to communicate symmetric pause capability to the local MAC. It has no effect on PHY operation. The state of this bit is valid when the Auto-Negotiation Complete bit (1.5) is set. 91 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 5.9:5 – LP Advertise Capability Bits 5.9:5 reflect the abilities of the Link Partner. A “1” on any of these bits indicates that the Link Partner advertises capability of performing the corresponding mode of operation. These bits are not available for read in Clause-37 view, but remain valid for CAT-5 copper media and can be viewed by switching to Clause-28 view. 5.4:0 – LP Advertise Selector Field Bits 5.4:0 indicate the state of the Link Partner’s Selector Field. The local PHY does not otherwise use these bits. 25.3.6.4 Clause 37 View Register 5(05h) – Auto-Negotiation Link Partner Ability Register - Clause 37 View Bit 15 14 13:12 11:9 8 7 6 5 4:0 Name LP Next-Page Transmit Request LP Acknowledge LP Remote Fault Reserved LP Advertise Asymmetric Pause LP Advertise Symmetric Pause LP Advertise 1000BASE-X HDX LP Advertise 1000BASE-X FDX Reserved Access RO RO RO RO RO RO RO RO RO States 1 = LP next-page transmission request 1 = LP acknowledge LP remote fault 1 = LP Advertise Asymmetric Pause 1 = LP Advertise Symmetric Pause 1 = 1000BASE-X HDX capable 1 = 1000BASE-X FDX capable Reset Value 0 0 00 000 0 0 0 0 00000 Sticky 5.15 – LP Next-Page Transmit Request In Clause-37 view, bit 5.15 functions identically to bit 5.15 in Clause-28 view. 5.14 - LP Acknowledge In Clause-37 view, bit 5.14 functions identically to bit 5.14 in Clause-28 view. 5.13:12 – LP Remote Fault Bits 5.13:12 return a “1” when the Link Partner signals that a remote fault (from its perspective) has occurred. The local PHY does not otherwise use these bits. Note that IEEE Clause-37 provides for two remote fault bits, while Clause-28 provides only a single remote fault bit. This discrepancy is handled in Extended MII Register bits 16E.2:1 - Remote Fault Mapping Mask and 16E.0 - Remote Fault Mapping OR . The state of this bit is valid when the Auto-Negotiation Complete bit (1.5) is set. 5.11:9 - Reserved 5.8 - LP Advertise Asymmetric Pause In Clause-37 view, bit 5.8 functions identically to bit 5.11 in Clause-28 view. The state of this bit is valid when the AutoNegotiation Complete bit (1.5) is set. 5.7 - LP Advertise Symmetric Pause In Clause-37 view, bit 5.7 functions identically to bit 5.10 in Clause-28 view.The state of this bit is valid when the AutoNegotiation Complete bit (1.5) is set. 5.6:5 - LP Advertise 1000BASE-X Bits 5.6:5 reflect the 1000Mbit capability advertisement received from the link partner for both fiber and copper media. Therefore, these bits are set either if bits 5.6:5 are set during Clause-37 autonegotiation, or if MII Register bits 10.11:10 are set during Clause-28 autonegotiation. 92 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 5.4:0 - Reserved 25.3.7 Register 6 (06h) – Auto-Negotiation Expansion Register 25.3.7.5 Clause 28 View Register 6 (06h) – Auto-Negotiation Expansion Register - Clause 28 View Bit 15:5 4 3 2 1 0 Name Reserved Parallel Detection Fault LP Next-Page Able Local PHY Next-Page Able Page Received LP Auto-Negotiation Able Access RO RO LH RO RO RO LH RO States Reset Value 00000000000 0 0 1 0 0 1 = Parallel detection fault 1 = LP Next-Page capable 1 = Next-Page capable 1 = New page has been received 1 = LP Auto-Negotiation capable Sticky 6.15:5 – Reserved 6.4 – Parallel Detection Fault Parallel Detection Fault returns a “1” when a parallel detection fault occurs in the local Auto-Negotiation state machine. Once set, this bit is automatically cleared when (and only when) Register 6 is read. 6.3 – LP Next-Page Able1 LP Next-Page Able returns a “1” when the Link Partner has Next-Page capabilities. This bit is used in the Auto-Negotiation state machines, as defined in Clause 28 of IEEE 802.3. The state of this bit is valid when either the Auto-Negotiation Complete bit (1.5) or the Page Received bit (6.1) is set. 6.2 – Local PHY Next-Page Able Since the VSC8211 is next-page capable during Clause-28 autonegotiation, this bit is hard-wired to “1”. 6.1 – Page Received Page Received is set to “1” when a new Link Code Word is received from the Link Partner, validated, and acknowledged. Page Received is automatically cleared when (and only when) Register 6 is read via the SMI. 6.0 – LP Auto-Negotiation Able2 LP Auto-Negotiation Capable is set to “1” if the Link Partner advertises Auto-Negotiation capability. The state of this bit is valid when the Auto-Negotiation Complete bit (1.5) or the Page Received bit (6.1) is set. 25.3.7.6 Clause 37 View Register 6 (06h) – Auto-Negotiation Expansion Register - Clause 37 View Bit 15:3 2 1 0 Name Reserved Local PHY Next-Page Able Page Received Reserved Access RO RO RO LH RO States 1 = Next-Page capable 1 = New page has been received 1 The state of this bit is valid only when the CAT5 media link is up. 2 The state of this bit is vaild only when the CAT5 media link is up. 93 of 165 VMDS-10105 Revision 4.1 October 2006 Reset Value 0000000000000 0 0 0 Sticky VSC8211 Datasheet 6.15:3 – Reserved 6.2 – Local PHY Next-Page Able The VSC8211 is not next-page capable in Clause-37 auto-negotiation, therefore this bit is hard-wired to “0”. Note that this does not apply to bit 6.2 in Clause-28 auto-negotiation. 6.1 - Page Received In Clause-37 view, bit 6.1 functions identically to bit 6.1 in Clause-28 view. Note, however, that next-pages can only be received by the VSC8211 during Clause-28 autonegotiation. 6.0 - Reserved 25.3.8 Register 7 (07h) – Auto-Negotiation Next-Page Transmit Register - Clause 28/37 View1 Register 7 (07h) – Auto-Negotiation Next-Page Transmit Register - Clause 28/37 View Bit Name Access 15 Next Page R/W 14 Reserved RO 13 Message Page R/W 12 Acknowledge2 R/W 11 Toggle RO 10:0 Message/Unformatted Code R/W States 1 = More pages follow 0 = Last page Reset Value Sticky 0 0 1 = Message page 0 = Unformatted page 1 = Will comply with request 0 = Cannot comply with request 1 = Previous transmitted LCW == 0 0 = Previous transmitted LCW == 1 1 0 0 00000000001 7.15 – Next Page The Next Page bit indicates whether this is the last Next-Page to be transmitted. By default, this bit is set to “0”, indicating that this is the last page. 7.14 – Reserved 7.13 – Message Page The Message Page bit indicates whether this page is a message page or an unformatted page. This bit does not otherwise affect the operation of the local PHY. By default, this bit is set to “1”, indicating that this is a message page. 7.12 – Acknowledge2 The Acknowledge2 bit indicates if the local MAC reports that it is able to act on the information (or perform the task) indicated in the previous message. The local PHY does not interpret or act on changes in the state of this bit. 7.11 – Toggle The Toggle bit is used by the arbitration function in the local PHY to ensure synchronization with the Link Partner during NextPage exchanges. The Toggle bit is automatically set to the opposite state of the Toggle bit in the previously exchanged Link Code Word. 7.10:0 – Message/Unformatted Code 1 This register is only valid for CAT-5 copper media 94 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet The Message/Unformatted Code bits indicate the message code being transmitted to the Link Partner. The local PHY passes the message code to the Link Partner without interpreting or reacting to it. By default, this code is set to “000 0000 0001”, indicating a null message. 25.3.9 Register 8 (08h)–Auto-Negotiation Link Partner Next-Page Receive Register,Clause 28/37 View1 Register 8 (08h) – Auto-Negotiation Link Partner Next-Page Receive Register - Clause 28/37 View Bit Name Access 15 LP Next Page RO 14 LP Acknowledge RO 13 LP Message Page RO 12 LP Acknowledge2 RO 11 LP Toggle RO 10:0 LP Message/Unformatted Code RO States 1 = More pages follow 0 = Last page 1 = LP acknowledge 1 = Message page 0 = Unformatted page 1 = LP will comply with request 1 = Previous transmitted LCW == 0 0 = Previous transmitted LCW == 1 Reset Value Sticky 0 0 0 0 0 00000000000 SMI Register 8 contains the Link Partner’s Next-Page register contents. The contents of this register are only valid when the Page Received bit (6.1) is set. 8.15 – LP Next Page This bit indicates if more pages follow from the Link Partner. 8.14 – LP Acknowledge This bit returns a “1” when the Link Partner signals that it has received the Link Code Word from the local PHY. The local PHY uses this bit for proper Link Code Word exchange, as defined in Clause 28 of IEEE 802.3. 8.13 – LP Message Page The Message Page bit indicates if the page received from the Link Partner is a message page or an unformatted page. 8.12 – LP Acknowledge2 The Acknowledge2 bit indicates whether the Link Partner MAC reports that it is able to act on the information (or perform the task) indicated in the message. The local PHY does not interpret or act on changes in the state of this bit. 8.11 – LP Toggle The Toggle bit is used by the arbitration function in the local PHY to ensure synchronization with the Link Partner during NextPage exchanges. In the Link Partner, the Toggle bit is automatically set to the opposite state of the Toggle bit in the previously exchanged Link Code Word from the Link Partner. 8.10:0 – LP Message/Unformatted Code The Message/Unformatted Code bits indicate the message code being transmitted by the Link Partner. 1 This register is only valid for CAT-5 copper media 95 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 25.3.10 Register 9 (09h) – 1000BASE-T Control Register 25.3.10.7 Clause 28 View1 Register 9 (09h) – 1000BASE-T Control Register - Clause 28 View Bit Name 15:13 Transmitter Test Mode 12 MASTER/SLAVE Manual Configuration Enable 11 MASTER/SLAVE Manual Configuration Value 10 Port Type 9 8 7:0 1000BASE-T FDX Capability 1000BASE-T HDX Capability Reserved Access States R/W Described below, per IEEE 802.3, 40.6.1.1.2 1 = Enable MASTER/SLAVE Manual Configuration value R/W 0 = Disable MASTER/SLAVE Manual Configuration value 1 = Configure PHY as MASTER during MASTER/SLAVE negotiation, only when bit 9.12 is set to logical one. R/W 0 = Configure PHY as SLAVE during MASTER/ SLAVE negotiation, only when bit 9.12 is set to logical one. 1 = Multi-port device R/W 0 = Single-port device R/W 1 = PHY is 1000BASE-T FDX capable R/W 1 = PHY is 1000BASE-T HDX capable R/W Reset Value 000 Sticky 0 0 0 CMODE CMODE 00000000 9.15:13 Transmitter/Receiver Test Mode1 This test is valid only in 1000BASE-T mode. Refer to IEEE 802.3-2002, section 40.6.1.1.2 for more information. Bit 1 (9.15) Bit 2 (9.14) Bit 3 (9.13) 0 0 0 Normal operation 0 0 1 Test Mode 1 – Transmit waveform test 0 1 0 Test Mode 2 – Transmit jitter test in MASTER mode 0 1 1 Test Mode 3 – Transmit jitter test in SLAVE mode 1 0 0 Test Mode 4 – Transmitter distortion test 1 0 1 Reserved; operation not defined 1 1 0 Reserved; operation not defined 1 1 1 Reserved; operation not defined Test Mode • Test Mode 1: The PHY repeatedly transmits the following sequence of data symbols from all four transmitters: {{"+2" followed by 127 "0" symbols}, {"-2" followed by 127 "0" symbols}, {"+1" followed by 127 "0" symbols}, {"-1" followed by 127 "0" symbols}, {128 "+2" symbols, 128 "-2" symbols, 128 "+2" symbols, 128 "-2" symbols}, {1024 "0" symbols}}. The transmitter should use a 125.00 MHz ± 0.01% clock and should operate in MASTER timing mode. • Test Mode 2: The PHY transmits the data symbol sequence {+2, -2} repeatedly on all channels. The transmitter should use a 125.00 MHz ± 0.01% clock in the MASTER timing mode. 1 The state of this register is internally latched when the Auto-Negotiation state machine enters the ABILITY_DETECT state. Changes to the states of these bits are recognized only at that time. This register is valid only in 1000BASE-T mode. 96 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet • Test Mode 3: The PHY transmits the data symbol sequence {+2, -2} repeatedly on all channels. The transmitter should use a 125.00 MHz ± 0.01% clock and should operate in SLAVE timing mode. • Test Mode 4: The PHY transmits the sequence of symbols generated by the following scrambler generator polynomial, bit generation, and level mappings: The maximum-length shift register used to generate the sequences defined by this polynomial is updated once per symbol interval (8ns). The bits stored in the shift register delay line at a particular time n are denoted by Scrn[10:0]. At each symbol period, the shift register is advanced by one bit, and one new bit represented by Scrn[0] is generated. Bits Scrn[8] and Scrn[10] are exclusive-OR'd together to generate the next Scrn[0] bit. The bit sequences, x0n, x1n, and x2n, generated from combinations of the scrambler bits as shown in the following equations, shall be used to generate the quinary symbols, sn, as shown in the following table. The transmitter should use a 125.00 MHz ± 0.01% clock and should operate in MASTER timing mode. Table 35. Bit Sequences for Generating Quinary Symbols x2n x1n x0n Quinary Symbol, sn 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 -1 1 0 0 0 1 0 1 1 1 1 0 -2 1 1 1 -1 9.12 – MASTER/SLAVE Manual Configuration Enable1 When this bit is set to “0” (default), the MASTER/SLAVE designation of the local PHY is determined using the arbitration protocol established in the IEEE Ethernet standard. When this bit is set to “1”, the MASTER/SLAVE designation of the local PHY is set by bit 9.11. Note that MASTER/SLAVE configuration is valid only in 1000BASE-T mode. 9.11 – MASTER/SLAVE Configuration Value1 This bit is ignored when bit 9.12 is set to “0”. However, if bit 9.12 is set to “1”, bit 9.11 determines the MASTER/SLAVE designation of the local PHY. If bit 9.12 is set to “1” and bit 9.11 set to “0”, the local PHY is forced to be a SLAVE. If bit 9.12 is set to “1” and bit 9.11 set to “1”, the local PHY is forced to be a MASTER. Note that MASTER/SLAVE configuration is valid only in 1000BASE-T mode. 9.10 – Port Type1 Since the VSC8211 is a single port physical layer transceiver, bit 9.10 is set to “0” by default. When set to “0”, this bit indicates a preference for operation as a SLAVE. If the Link Partner does not indicate the same preference, the local PHY will operate as a SLAVE, and the Link Partner will be a MASTER. Otherwise, the normal MASTER/SLAVE assignment protocol is used. 9.9 – 1000BASE-T FDX1 Since the VSC8211 is 1000BASE-T FDX capable, this bit is “1” by default. If bit 9.9 is written to be “0”, the Auto-Negotiation state machine for the local PHY will be blocked from advertising 1000BASE-T FDX. Note that the Link Partner will be notified of 1 The state of this register is internally latched when the Auto-Negotiation state machine enters the ABILITY_DETECT state. Changes to the states of these bits are recognized only at that time. This register is valid only in 1000BASE-T mode. 97 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet the state of 9.9 during Auto-Negotiation. After Auto-Negotiation is complete, changing the state of this bit has no effect unless Auto-Negotiation is manually restarted. 9.8 – 1000BASE-T HDX1 Since the VSC8211 is 1000BASE-T HDX capable, this bit is “1” by default. If bit 9.8 is written to be “0”, the Auto-Negotiation state machine for the local PHY will be blocked from advertising 1000BASE-T HDX. Note that the Link Partner will be notified of the state of bit 9.8 during Auto-Negotiation. After Auto-Negotiation is complete, changing the state of this bit has no effect unless Auto-Negotiation is manually restarted. 9.7:0 – Reserved 25.3.10.8 Clause 37 View Register 9 (09h) - 1000BASE-T Control Register - Clause 37 View Bit 15:0 Name Reserved Access RO States Reset Value 00000000 00000000 Sticky 9.15:0 - Reserved In Clause-37 register view, MII register 9 is reserved. Note that MII register 9 bits in Clause-28 view remain valid, but cannot be read or written to if the current register view is Clause-37. 25.3.11 Register 10 (0Ah) – 1000BASE-T Status Register #1 25.3.11.9 Clause 28 View2 Register 10 (0Ah) – 1000BASE-T Status Register #1 - Clause 28 View Bit 15 14 13 12 11 10 9:8 7:0 Name Access States 1 = MASTER/SLAVE configuration fault MASTER/SLAVE Configuration detected RO LH SC Fault 0 = No MASTER/SLAVE configuration fault detected 1 = Local PHY configuration resolved to MASMASTER/SLAVE Configuration RO TER Resolution 0 = Local PHY configuration resolved to SLAVE 1 = Local receiver OK (loc_rcvr_status == OK) Local Receiver Status RO 0 = Local receiver not OK (loc_rcvr_status == NOT_OK) 1 = Remote receiver OK (rem_rcvr_status == OK) Remote Receiver Status RO 0 = Remote receiver not OK (rem_rcvr_status == NOT_OK) 1 = LP 1000BASE-T FDX capable LP 1000BASE-T FDX Capability RO 0 = LP not 1000BASE-T FDX capable 1 = LP is 1000BASE-T HDX capable LP 1000BASE-T HDX Capability RO 0 = LP is not 1000BASE-T HDX capable Reserved RO Idle Error Count RO SC 1 Reset Value Sticky 0 1 0 0 0 0 00 00000000 The state of this register is internally latched when the Auto-Negotiation state machine enters the ABILITY_DETECT state. Changes to the states of these bits are recognized only at that time. This register is valid only in 1000BASE-T mode. 98 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 10.15 – MASTER/SLAVE Configuration Fault1 This bit indicates whether a MASTER/SLAVE configuration fault has been detected by the local PHY. A configuration fault occurs if both the local and remote PHYs are forced to the same MASTER/SLAVE state, or if no resolution is reached after seven retries. When such a fault has been detected, this bit is set to “1”, but the PHY continues to renegotiate until the MASTER/SLAVE configuration is resolved. Once set, this bit is automatically cleared when (and only when) Register 10 is read via the SMI. 10.14 – MASTER/SLAVE Configuration Resolution1 By default, the MASTER/SLAVE configuration is determined as part of the Auto-Negotiation process. However, the MASTER/ SLAVE status can optionally be manually forced via bits in MII Register 9. Bit 10.14 indicates the final MASTER/SLAVE configuration status for the local PHY. This bit can change state only as a result of the reset or subsequent restart of the AutoNegotiation process. This bit is only valid when the Auto-Negotiation Complete bit (1.5) is set. 10.13 – Local Receiver Status1 Bit 10.13 indicates the state of the loc_rcvr_status flag within the PMA receive function within the local PHY. 10.12 – Remote Receiver Status1 Bit 10.12 indicates the state of the rem_rcvr_status flag within the PMA receive function within the local PHY. 10.11 – LP 1000BASE-T FDX Capability1, 3 Bit 10.11 is set to “1” if the Link Partner PHY advertises 1000BASE-T FDX capability. Otherwise, this bit is set to “0”. This bit is valid on when MII Register 1.5 is set. 10.10 – LP 1000BASE-T HDX Capability2, 3 Bit 10.10 is set to “1” if the Link Partner PHY advertises 1000BASE-T HDX capability. Otherwise, this bit is set to “0”. This bit is valid on when MII Register 1.5 is set. 10.9:8 – Reserved 10.7:0 – Idle Error Count3 Bits 10.7:0 indicate the Idle Error count, where 10.7 is the most significant bit. These bits contain a cumulative count of the errors detected when the receiver is receiving idles and PMA_TXMODE.indicate is equal to SEND_N (indicating that both the local and remote receiver status have been detected to be OK). The counter is incremented every symbol period that rx_error_status in the PMA receive function is equal to ERROR. Bits 10.7:0 are reset to all “0”s when the error count is read by the management function, or upon execution of the PCS reset function, and they are saturated to all “1”s in case of overflow. 2 The bits in this register apply only in 1000BASE-T mode. 1This bit is valid only when the Page Received bit (6.1) is set to a “1”. 2 This bit applies only in 1000BASE-T mode. 3 The state of this bit is valid only if MII Register 9.9 or 9.8 is set. 99 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 25.3.11.10 Clause 37 View Register 10 (0Ah) - 1000BASE-T Status Register #1 - Clause 37 View Bit 15:0 Name Reserved Access RO States Reset Value 00000000 00000000 Sticky 9.15:0 - Reserved In Clause-37 register view, MII register 10 is reserved. Note that MII register 10 bits in Clause-28 view remain valid, but cannot be read if the current register view is Clause-37. 25.3.12 Register 11 (0Bh) – Reserved Register Register 11 (0Bh) – Reserved Register Bit 15:0 Name Reserved Access RO States Reset Value 00000000 00000000 Sticky States Reset Value 00000000 00000000 Sticky Reset Value 00000000 00000000 Sticky 11.15:0 – Reserved 25.3.13 Register 12 (0Ch) – Reserved Register Register 12 (0Ch) – Reserved Register Bit 15:0 Name Reserved Access RO 12.15:0 – Reserved 25.3.14 Register 13 (0Dh) – Reserved Register Register 13 (0Dh) – Reserved Register Bit 15:0 Name Reserved Access RO States 13.15:0 – Reserved 25.3.15 Register 14 (0Eh) – Reserved Register Register 14 (0Eh) – Reserved Register Bit 15:0 Name Reserved Access RO States 100 of 165 VMDS-10105 Revision 4.1 October 2006 Reset Value 00000000 00000000 Sticky VSC8211 Datasheet 14.15:0 – Reserved 25.3.16 Register 15 (0Fh) – 1000BASE-T Status Register #2 25.3.16.11 Clause 28 View Register 15 (0Fh) – 1000BASE-T Status Register #2 - Clause 28 View Bit Name Access 15 1000BASE-X FDX Capability RO 14 1000BASE-X HDX Capability RO 13 1000BASE-T FDX Capability RO 12 1000BASE-T HDX Capability RO 11:0 Reserved RO States 1 = PHY is 1000BASE-X FDX capable 0 = PHY is not 1000BASE-X FDX capable 1 = PHY is 1000BASE-X HDX capable 0 = PHY is not 1000BASE-X HDX capable 1 = PHY is 1000BASE-T FDX capable 0 = PHY is not 1000BASE-T FDX capable 1 = PHY is 1000BASE-T HDX capable 0 = PHY is not 1000BASE-T HDX capable Reset Value Sticky 0 0 1 1 000000000000 15.15 – 1000BASE-X FDX Capability The VSC8211 is not 1000BASE-X capable, so this bit is hard-wired to “0”. 15.14 – 1000BASE-X HDX Capability The VSC8211 is not 1000BASE-X capable, so this bit is hard-wired to “0”. 15.13 – 1000BASE-T FDX Capability The VSC8211 is 1000BASE-T FDX capable, so this bit is hard-wired to “1”. 15.12 – 1000BASE-T HDX Capability The VSC8211 is 1000BASE-T HDX capable, so this bit is hard-wired to “1”. 15.11:0 – Reserved 25.3.16.12 Clause 37 View Register 15 (0Fh) – 1000BASE-T Status Register #2 - Clause 37 View Bit Name Access 15 1000BASE-X FDX Capability RO 14 1000BASE-X HDX Capability RO 13 1000BASE-T FDX Capability RO 12 1000BASE-T HDX Capability RO 11:0 Reserved RO States 1 = PHY is 1000BASE-X FDX capable 0 = PHY is not 1000BASE-X FDX capable 1 = PHY is 1000BASE-X HDX capable 0 = PHY is not 1000BASE-X HDX capable 1 = PHY is 1000BASE-T FDX capable 0 = PHY is not 1000BASE-T FDX capable 1 = PHY is 1000BASE-T HDX capable 0 = PHY is not 1000BASE-T HDX capable October 2006 1 1 0 0 000000000000 101 of 165 VMDS-10105 Revision 4.1 Reset Value Sticky VSC8211 Datasheet 15.15:12 – 1000BASE-X Capability In Clause-37 view, bits 15.15:12 differ from bits 15.15:12 in Clause-28 view by their reset values only. In Clause 37 view MII Register 15.15:12 = ‘0011’. 15:11:0 - Reserved 25.3.17 Register 16 (10h) – Reserved Register 16 (10h) – Reserved Register Bit 15:0 Name Reserved Access RO States Reset Value 00000000 00000000 Sticky Reset Value 00000000 00000000 Sticky 16.15:0 – Reserved 25.3.18 Register 17 (11h) – Reserved Register 17 (11h) – Reserved Register Bit 15:0 Name Reserved Access RO States 17.15:0 – Reserved 102 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 25.3.19 Register 18 (12h) – Bypass Control Register Register 18 (12h) – Bypass Control Register Bit 15 Name Reserved 14 Bypass 4B5B Encoder/Decoder R/W 13 Bypass Scrambler R/W 12 Bypass Descrambler R/W 11:9 Reserved RO 8 Transmitter Test Clock Enable R/W 7:6 Reserved Disable Automatic Pair Swap Correction RO 4 Disable Polarity Inversion R/W 3 Parallel-Detect Control R/W 2 Reserved RO 1 Disable Automatic 1000BASE-T R/W Next-Page Exchange 0 CLKOUTMAC Output Enable 5 Access RO R/W R/W States 1 = Bypass 4B5B encoder/decoder 0 = Enable 4B5B encoder/decoder 1 = Bypass scrambler 0 = Enable scrambler 1 = Bypass descrambler 0 = Enable descrambler Reset Value 0 Sticky 0 0 0 000 1 = Enable TXCLK test output on CLKOUTMICRO pin 0 0 = Disable TXCLK test output on CLKOUTMICRO pin 00 1 = Disable 0 0 = Enable 1 = Disable 0 0 = Enable 1 = Do not ignore advertised ability 1 0 = Ignore advertised ability 0 1 = Disable automatic 1000BASE-T Next-Page exchanges 0 0 = Enable automatic 1000BASE-T Next-Page exchanges 1 = Enable output clock pins CLKOUTMAC 1 0 = Disable output clock pins CLKOUTMAC S S S 18.15 – Reserved 18.14 – Bypass 4B5B Encoder/Decoder 1 When bit 18.14 is set to “1”, the 5B codes (TXER and TXD[3:0]) will be passed from the MII interface directly to the scrambler, bypassing the 4B5B encoder. Note that in this mode, J/K and T/R code insertion will not be performed. The receiver will pass descrambled/aligned 5B codes directly to the MII interface (RXER and RXD[3:0]), bypassing the 4B5B decoder. Carrier sense (CRS) is still asserted when a valid frame is detected. 18.13 – Bypass Scrambler2 When bit 18.13 is set to “1”, the scrambler is disabled. 18.12 – Bypass Descrambler2 When bit 18.12 is set to “1”, the descrambler is disabled. 1 This bit applies only in 100BASE-TX mode. 2 This bit applies only in 100BASE-TX and 1000BASE-T modes. 103 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 18.11:9 – Reserved 18.8 – Transmitter Test Clock Enable When a “1” is written to bit 18.8, the CLKOUTMICRO output pin becomes a test pin for the transmit clock “TXCLK”. This capability is intended to enable measurement of transmitter timing jitter, as specified in IEEE Standard 802.3-2002, section 40.6.1.2.5. When in IEEE-specified transmitter test modes 2 or 3 (see IEEE 802.3-2002, section 40.6.1.1.2 and MII Register bits 9.15:13), the peak-to-peak jitter of the zero-crossings of the differential signal output at the MDI, relative to the corresponding edge of TXCLK, is measured. The corresponding edge of TXCLK is the edge of the transmit test clock, in polarity and time, that generates the zero-crossing transition being measured. While transmitter test mode clock TXCLK is intended only for characterization test purposes, CLKOUTMICRO is intended to serve as a general purpose system or MAC reference clock. 18.7:6 – Reserved 18.5 - Disable Automatic Pair Swap Correction When set to “1”, the automatic pair swap correction feature of the PHY is disabled. 18.4 - Disable Polarity Inversion When set to “1”, the automatic polarity inversion feature of the PHY is disabled. 18.3 – Parallel-Detect Control When bit 18.3 is “1”, MII Register 4, bits [8:5], are taken into account when attempting to parallel-detect. This is the default behavior expected by the standard. Setting 18.3 to a “0” will result in Auto-Negotiation ignoring the advertised abilities, as specified in MII Register 4, during parallel detection of a non-auto-negotiating 10BASE-T or 100BASE-TX PHY. 18.2 – Reserved 18.1 – Disable Automatic 1000BASE-T Next-Page Exchanges Bit 18.1 is used to control the automatic exchange of 1000BASE-T Next-Pages defined in IEEE 802.3-2002 (Annex 40C). When this bit is set, the automatic exchange of these pages is disabled, and the control is returned to the user through the SMI after the base page has been exchanged. The user then has complete responsibility to: • send the correct sequence of Next-Pages to the Link Partner, and • determine common capabilities and force the device into the correct configuration following successful exchange of pages. When bit 18.1 is reset to “0”, the 1000BASE-T related Next-Pages are automatically exchanged without user intervention. If the Next Page bit 4.15 was set by the user in the Auto-Negotiation Advertisement register at the time the Auto-Negotiation was restarted, control is returned to the user for additional Next-Pages following the 1000BASE-T Next-Page exchange. If both bit 18.1 and MII Register bit 4.15 are reset when an Auto-Negotiation sequence is initiated, all Next-Page exchange is automatic, including sourcing of null pages. No user notification is provided until either Auto-Negotiation completes or fails. See the description of MII Register bit 4.15 for more details on standard Next-Page exchanges. 18.0 – CLKOUTMAC Output Enable When bit 18.0 is set to “1”, the VSC8211 provides a 125MHz clock on the CLKOUTMAC output pin. The electrical specification for this clock corresponds to the current settings for VDDIOMAC. This clock is for use by the MAC, system manager CPU, or control logic. By default, this pin is enabled, which enables the clock output independent of the status of any link, unless the hardware reset is active (which also powers down the PLL). When disabled, the clock pins are normally driven low. 104 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 25.3.20 Register 19 (13h) – Reserved Register 19 (13h) – Reserved Bit 15:0 Name Reserved Access RO States Reset Value 00000000 00000000 Sticky States Reset Value 00000000 00000000 Sticky States Reset Value 00000000 00000000 Sticky 19.15:0 - Reserved 25.3.21 Register 20 (14h) – Reserved Register 20 (14h) – Reserved Bit 15:0 Name Reserved Access RO 20.15:0 – Reserved 25.3.22 Register 21 (15h) – Reserved Register 21 (15h) – Reserved Bit 15:0 Name Reserved Access RO 21.15:0 – Reserved 105 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 25.3.23 Register 22 (16h) – Control & Status Register Register 22 (16h) – Control & Status Register Bit Name Access 15 Disable Link Integrity State Machine R/W 14 Disable jabber Detect R/W 13 Disable 10BASE-T Echo R/W 12 SQE Disable Mode R/W 11:10 10BASE-T Squelch Control R/W 9 Sticky Reset Enable R/W 8 EOF Error RO SC 7 10BASE-T Disconnect State RO SC 6 10BASE-T Link Status RO 5:3 2:1 0 Reserved CRS Control Reserved RO R/W RO States 1 = Disable link integrity test 0 = Enable link integrity test 1 = Disable jabber detect 0 = Enable jabber detect 1 = Disable 10BASE-T Echo 0 = Enable 10BASE-T Echo 1 = Disable SQE Transmit 0 = Enable SQQ Transmit 00 = Normal squelch 01 = Low squelch 10 = High squelch 11 = Reserved 1 = All bits marked as sticky will retain their values during software reset 0 = All bits marked as sticky will be changed to default values during software reset 1 = EOF error detected since last read 0 = EOF error not detected since last read 1 = 10BASE-T link disconnected 0 = 10BASE-T link connected 1 = 10BASE-T link active 0 = 10BASE-T link inactive See table in register description below Reset Value Sticky 0 S 0 S CMODE S CMODE S 00 S 1 SS 0 0 0 00 00 0 S 22.15 – Disable Link-Integrity State Machine1 When bit 22.15 is set to “0”, the VSC8211 link integrity state machine runs automatically. When bit 22.15 is set to “1”, the link integrity state machine is bypassed, and the PHY is forced into link pass status. 22.14 – Disable Jabber Detect1 When bit 22.14 is set to “0”, the VSC8211 automatically shuts off the transmitter when a transmission request exceeds the IEEE-specified time limit. When bit 22.14 is set to “1”, transmission requests are allowed to be arbitrarily long without shutting down the transmitter. 22.13 – Disable 10BASE-T Echo Mode1 When this bit is set, TXEN and TXD will not be echoed on the RXDV abd RXD pins respectively in 10BASE-T half duplex mode. 22.12 – SQE Disable Mode2 When bit 22.12 is set to “1”, SQE (Signal Quality Error) pulses are not sent. Note that this control bit applies in 10BASE-T HDX mode only. 1 This bit applies only in 10BASE-T mode. 2 This bits applies only in 10BASE-T HDX mode. 106 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 22.11:10 – 10BASE-T Squelch Control1 When bits 22.11:10 are set to “00”, the VSC8211 uses the squelch threshold levels prescribed by the IEEE’s 10BASE-T specification. When bits 22.11:10 are set to “01”, the squelch level is decreased, which may improve the bit error rate performance on long loops. When bits 22.11:10 are set to “10”, the squelch level is increased, which may improve the bit error rate in high-noise environments. 22.9 - Sticky Reset Enable When bit 22.9 is set, all MII register bits that are marked with an “S” in the “sticky” column will retain their values during a software reset. When cleared, all MII register bits that are marked with an “S” in the “sticky” column will be changed to their default values during a software reset. Note that bits marked with an “SS” retain their values across software reset regardless of the setting of bit 22.9. 22.8 – EOF Error1 When bit 22.8 returns a “1”, a defective EOF (End-of-Frame) sequence has been received since the last time this bit was read. This bit is automatically set to “0” when it is read. 22.7 – 10BASE-T Disconnect State Bit 22.7 is set to “1” if the 10BASE-T connection has been broken by the carrier integrity monitor since the last read of this bit; otherwise, this bit is set to “0”. 22.6 – 10BASE-T Link Status Bit 22.6 is set to “1” if the 10BASE-T link is active. Otherwise, this bit is set to “0”. 22.5:3 – Reserved 22.2:1 - CRS Control Bits 22.2:1 determine the behavior of the CRS indication provided by the VSC8211 according to the following table: Link State CRS Control Bits - bits 2:1 1000BASE-T Full-Duplex 1000BASE-T Half-Duplex 100BASE-TX Full-Duplex 100BASE-TX Half-Duplex 10BASE-T Full-Duplex 10BASE-T Half-Duplex 00 (default) 01 10 CRS = RXDV CRS = 0 CRS = RXDV CRS = 0 CRS = Logical OR of RXDV and TXEN CRS = Logical OR of RXDV and TXEN CRS = RXDV CRS = RXDV CRS = RXDV CRS = 0 CRS = RXDV CRS = 0 CRS = RXDV CRS = 0 CRS = Logical OR of RXDV and TXEN CRS = Logical OR of RXDV and TXEN CRS = RXDV CRS = RXDV 1 This bit applies only in 10BASE-T mode. 107 of 165 October 2006 CRS = RXDV CRS = 0 CRS = Logical OR of RXDV and TXEN CRS = Logical OR of RXDV and TXEN CRS = RXDV CRS = RXDV 22.0 – Reserved VMDS-10105 Revision 4.1 11 VSC8211 Datasheet 25.3.24 Register 23 (17h) – PHY Control Register #1 Register 23 (17h) – PHY Control Register #1 Bit Name Access 15:12 MAC/Media Interface Mode Select RWSW 11:10 RGMII/RTBI TXC Skew Selection R/W 9:8 RGMII/RTBI RXC Skew Selection R/W 7 EWRAP Enable R/W 6 TBI Bit Order Reversal Enable R/W 5 RX Idle Clock Enable R/W 4 Register View RWSW 2:1 Far End (Media-Side) Loopback R/W Enable MAC/Media Interface Mode Select RWSW 0 EEPROM Status 3 RO States See Table 36 below 00 = No skew on TXC 01 = 1.5ns skew on TXC 10 = 2.0ns skew on TXC 11 = 2.5ns skew on TXC 00 = No skew on RXC 01 = 1.5ns skew on RXC 10 = 2.0ns skew on RXC 11 = 2.5ns skew on RXC 1 = Enable EWRAP in TBI mode 0 = Disable EWRAP in TBI mode 1 = Enable TBI bit order reversal 0 = Disable TBI bit order reversal 1 = 25MHz clock on RXCLK pin enabled in Enhanced ActiPHY mode 0 = 25MHz clock on RXCLK pin disabled in Enhanced ActiPHY mode 0 = MII registers 0:15 correspond to the definition in IEEE802.3 clause 28.2.4 (copper media) 1 = MII registers 0:15 correspond to the definition in IEEE802.3 clause 37.2.5 (fiber media) 1 = Far End (Media side) Loopback is enabled 0 = Far End (Media side) Loopback is disabled SeeTable 36 below 1 = EEPROM is detected on EEPROM interface 0 = EEPROM is not detected on EEPROM interface 108 of 165 VMDS-10105 Revision 4.1 October 2006 Reset Value CMODE Sticky CMODE S CMODE S 0 0 S 1 SS CMODE SS 0 CMODE 0 VSC8211 Datasheet 23.15:12, 2:1– MAC/Media Interface Mode Select Bits 23.15:12 and 23.2:1 are used to select the MAC interface modes and media interface modes. The reset value for these bits is dependent upon the state of the MAC Interface bits in the CMODE hardware configuration. All combinations of these bits not indicated below are reserved: Table 36. PHY Operating Modes Operating Mode Category MII Register 23.15:12, 23.2:1 CMODE2 [3:0] MAC Interface Media Interface Other Settings 0011,10 1000 GMII/MII 0011,01 0010 GMII Fiber 0010,01 0011 GMII/MII Auto Media Sense Fiber Preference 0010,10 - GMII/MII Auto Media Sense CAT5 Preference1 0001,10 Parallel MAC 0001,01 PHY Operat0000,01 ing Modes 0000,10 0110,00 CAT5 0110 RGMII CAT5 0111 RGMII Fiber 0001 RGMII Auto Media Sense Fiber Preference - RGMII Auto Media Sense CAT5 Preference1 1001 TBI CAT5 With Clause 37 Auto-Negotiation Detection 0111,01 1011 TBI Fiber2 0100,00 1100 RTBI CAT5 With Clause 37 Auto-Negotiation Detection 0101,01 - RTBI Fiber2 1111,00 0100 802.3z SerDes CAT5 Clause 37 disabled 1110, 01 1110 802.3z SerDes CAT5 Clause 37 enabled 1110,10 1010 802.3z SerDes CAT5 Clause 37 enabled, Media Convertor Mode 1110,00 0000 802.3z SerDes CAT5 With Clause 37 Auto-Negotiation Detection 1010,01 1111 SGMII CAT5 625Mhz SCLK Clock Disabled 0101 SGMII CAT5 625MHz SCLK Clock Enabled 1101 Serial Serial Buffered Mode – With Clock Recovery3 1001,00 SGMII CAT5 Modified Clause 37 auto-negotiation disabled, 625MHz SCLK Clock Enabled 1011,00 SGMII CAT5 Modified Clause 37 auto-negotiation disabled, 625MHz SCLK Clock Disabled Serial MAC PHY Operat- 1000,01 ing Modes 1001,01 1 In this mode, the PHY does not drop the Fiber Media link if the CAT5 link comes up after the Fiber Link has been established. It is therefore not a suitable mode for unmanaged applications. For more information on how to use this mode in managed applications, contact your Vitesse representative. 2 PHY registers are not supported in this mode. 3 In this mode, the PHY’s MAC and media interfaces are the same. Both interfaces can be either SGMII or 802.3z SerDes. 23.11:10 – RGMII/RTBI TXC Skew Selection Bits 23.11:10 specify the amount of clock delay added to the TX_CLK line inside the VSC8211 when using an RGMII or RTBI interface. By enabling this internal delay, a PCB “trombone” delay is not required as specified by the RGMII standard. Multiple values are provided to compensate for PCB trace skews. The default values of these bits are specified by the RGMII Skew bits in the CMODE hardware configuration. See Table 27, “PHY Operating Condition Parameter Description,” on page 68 for more information. 23.9:8 – RGMII/RTBI RXC Skew Selection Bits 23.9:8 specify the amount of clock delay added to the RX_CLK line inside the VSC8211 when using an RGMII or RTBI interface. By enabling this internal delay, a PCB “trombone” delay is not required as specified by the RGMII standard. Multiple 109 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet values are provided to compensate for PCB trace skews. The default values of these bits are specified by the RGMII Skew bits in the CMODE hardware configuration. See Table 27, “PHY Operating Condition Parameter Description,” on page 68 for more information. 23.7 – EWRAP Enable When bit 23.7 is set to “1” and the MAC interface is set to TBI, data loopback is enabled on the MAC interface. 23.6 – TBI Bit Order Reversal Enable Bit 23.6 allows the user to specify the bit order for the PCS when TBI mode is selected. By default, TBI bit order reversal, as defined in the IEEE standard, is disabled. 23.5 – RX Idle Clock Enable When bit 23.5 is set to “1”, a 25MHz clock is enabled on the RXCLK pin when the VSC8211 is in Enhanced ActiPHY mode. When bit 23.5 is cleared, the RXCLK pin remains low during Enhanced ActiPHY mode. This clock is enabled by default. 23.4 – Register View When bit 23.4 is set to “1”, MII registers 0:15 correspond to the definition in IEEE802.3 clause 28.2.4 (copper media). When bit 23.4 is cleared, MII registers 0:15 correspond to the definition in IEEE802.3 clause 37.2.5 (fiber media). Bit 23.4 is set to “1” by default. Refer to Section 25.1: "Clause 28/37 Resister View" on page 82 for more information. 23.3 – Far End (Media-Side) Loopback Enable1 When bit 23.3 is set to “1”, all incoming data from the link partner on the current media interface is retransmitted back to the link partner on the media interface. In addition, the incoming data will also appear on the RX pins of the MAC interface. Any data present on the TX pins of the MAC interface is ignored by the VSC8211 when bit 23.3 is set. In order to avoid loss of data, bit 23.3 should not be set while the VSC8211 is receiving data on the media interface. Bit 23.3 applies to all operating modes of the VSC8211. When bit 23.3 is cleared, the VSC8211 resumes normal operation. This bit is cleared by default. Refer to section 18.3, “Far-end Loopback,” page 64. 23.0 – EEPROM Status When bit 23.0 is set to “1”, an EEPROM has been detected on the external EEPROM interface. When cleared, bit 23.0 indicates that no EEPROM has been detected. 1 This feature is not available in ‘TBI to CAT5 Media’ PHY operating mode. 110 of 165 VMDS-10105 Revision 4.1 October 2006 VSC8211 Datasheet 25.3.25 Register 24 (18h) – PHY Control Register #2 Register 24 (18h) – PHY Control Register #2 Bit Name 15:13 Reserved1 12 Enable PICMG Miser Mode2 11:10 Reserved Access RO R/W TX FIFO Depth Control for RGMII, SGMII and Serial MAC 6:4 RX FIFO Depth Control (RTBI only) R/W 3:1 Reserved 1 2 Connector Loopback 1 = PICMG Miser Mode Enabled 0 = PICMG Miser Mode Disabled RO 9:7 0 States R/W Sticky S 0 S 00 000 to 010 = Reserved 011 = Jumbo packet mode 100 = IEEE mode 101 to 111 = Reserved 000 to 010 = Reserved 011 = Jumbo packet mode 100 = IEEE mode 101 to 111 = Reserved RO R/W Reset Value 111 100 S 100 S 000 1 = Active (See Section 18.5: "Connector Loopback" for details) 0 = Disable 0 These bits must always be written to as ‘111’. See section 12, “Transformerless Operation for PICMG 2.16 and 3.0 IP-based Backplanes,” page 45 for more information. 24.15:13 – Reserved These bits must always be written to as ‘111’. 24.12 - Enable PICMG Miser Mode1 Setting bit 24.12 turns off some portions of the PHY's DSP block and reduces the PHY's Operating power. This bit can be set in order to reduce power consumption in applications where the signal to noise ratio on the CAT-5 media is high, such as ethernet over the backplane or where the cable length is short (