VSC8562-11 Datasheet
Dual-Port 10/100/1000BASE-T PHY with Synchronous
Ethernet, Intellisec™, and QSGMII/SGMII MAC
Microsemi Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
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Outside the USA: +1 (949) 380-6100
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www.microsemi.com
©2019 Microsemi, a wholly owned
subsidiary of Microchip Technology Inc. All
rights reserved. Microsemi and the
Microsemi logo are registered trademarks of
Microsemi Corporation. All other trademarks
and service marks are the property of their
respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of
its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the
application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have
been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any
performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all
performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to
independently determine suitability of any products and to test and verify the same. The information provided by Microsemi
hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely
with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP
rights, whether with regard to such information itself or anything described by such information. Information provided in this
document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
About Microsemi
Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of
semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets.
Products include high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and
ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's
standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication
solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and
midspans; as well as custom design capabilities and services. Learn more at www.microsemi.com.
VMDS-10475. 4.2 5/19
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
Revision 4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Revision 4.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1
2.2
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1
Low Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2
Advanced Carrier Ethernet Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3
Wide Range of Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4
Flexibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.5
MACsec Encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
3
3
3
3
3
4
3 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1
3.2
3.3
3.4
3.5
3.6
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.1
QSGMII/SGMII MAC to 1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1.2
QSGMII/SGMII MAC to 100BASE-FX Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1.3
QSGMII/SGMII MAC to AMS and 1000BASE-X Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.4
QSGMII/SGMII MAC to AMS and 100BASE-FX Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1.5
QSGMII/SGMII MAC-to-AMS and Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1.6
QSGMII/SGMII MAC to Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.7
QSGMII/SGMII MAC-to-Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1.8
1000BASE-X MAC to Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.1
1000BASE-X MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.2
SGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.3
QSGMII MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.1
QSGMII/SGMII to 1000BASE-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.2
QSGMII/SGMII to 100BASE-FX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.3
QSGMII to SGMII Protocol Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.4
Unidirectional Transport for Fiber Media . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
PHY Addressing and Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.1
PHY Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.4.2
SerDes Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Cat5 Twisted Pair Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.1
Voltage Mode Line Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.5.2
Cat5 Autonegotiation and Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.3
Automatic Crossover and Polarity Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.5.4
Manual MDI/MDIX Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.5
Link Speed Downshift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.6
Energy Efficient Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5.7
Ring Resiliency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MACsec Block Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.1
MACsec Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6.2
MACsec Target Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6.3
Formats, Transforms, and Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6.4
MACsec Integration in PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6.5
MACsec Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.6.6
Debug Fault Code in FCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
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3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
3.21
3.6.7
Capture FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.8
Flow Control Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6.9
Media Access Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automatic Media Sense Interface Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.1
Configuring the Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.2
Single-Ended REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8.3
Differential REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ethernet Inline Powered Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 802.3af PoE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ActiPHY Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11.1 Low Power State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11.2 Link Partner Wake-Up State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11.3 Normal Operating State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI I/O Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Media Recovered Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13.1 Clock Selection Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13.2 Clock Output Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14.1 SMI Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.14.2 SMI Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.1 LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.2 Extended LED Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.3 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.4 Basic Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.5 Enhanced Serial LED Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.15.6 LED Port Swapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fast Link Failure Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integrated Two-Wire Serial Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.17.1 Read/Write Access Using the Two-Wire Serial MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Testing Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.1 Ethernet Packet Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.2 CRC Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.3 Loopbacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.4 VeriPHY Cable Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.5 JTAG Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.6 JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.19.7 Boundary Scan Register Cell Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100BASE-FX Far-End Fault Indication (FEFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.20.1 100BASE-FX Halt Code Transmission and Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.21.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
47
50
53
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58
58
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59
59
60
60
60
61
62
62
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64
65
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66
66
66
67
68
69
69
69
70
74
75
75
77
77
77
77
78
4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.1
4.2
Register and Bit Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IEEE 802.3 and Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.1
Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.2
Mode Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.3
Device Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.4
Autonegotiation Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.5
Link Partner Autonegotiation Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.6
Autonegotiation Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2.7
Transmit Autonegotiation Next Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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4.3
4.4
4.5
4.6
4.7
4.2.8
Autonegotiation Link Partner Next Page Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.2.9
1000BASE-T Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
4.2.10 1000BASE-T Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
4.2.11 MMD Access Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.2.12 MMD Address or Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.2.13 1000BASE-T Status Extension 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.2.14 100BASE-TX/FX Status Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.2.15 1000BASE-T Status Extension 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.2.16 Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
4.2.17 Error Counter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.2.18 Error Counter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.2.19 Error Counter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.2.20 Extended Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.2.21 Extended PHY Control Set 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.2.22 Extended PHY Control Set 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.2.23 Interrupt Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
4.2.24 Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.2.25 Device Auxiliary Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.2.26 LED Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.2.27 LED Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
4.2.28 Extended Page Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Extended Page 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.3.1
SerDes Media Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.3.2
Cu Media CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.3.3
Extended Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
4.3.4
ActiPHY Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
4.3.5
PoE and Miscellaneous Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.3.6
Ethernet Packet Generator Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
4.3.7
Ethernet Packet Generator Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Extended Page 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
4.4.1
Cu PMD Transmit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
4.4.2
EEE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
4.4.3
Extended Chip ID, Address 18E2 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.4.4
Entropy Data, Address 19E2 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.4.5
Extended Interrupt Mask, Address 28E2 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
4.4.6
Extended Interrupt Status, Address 29E2 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
4.4.7
Ring Resiliency Control (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Extended Page 3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
4.5.1
MAC SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4.5.2
MAC SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
4.5.3
MAC SerDes Clause 37 Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.5.4
MAC SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.5.5
MAC SerDes Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.5.6
Media/MAC SerDes Transmit Good Packet Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
4.5.7
Media/MAC SerDes Transmit CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.5.8
Media SerDes PCS Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
4.5.9
Media SerDes PCS Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
4.5.10 Media SerDes Clause 37 Advertised Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.5.11 Media SerDes Clause 37 Link Partner Ability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.5.12 Media SerDes Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
4.5.13 Media/MAC SerDes Receive CRC Good Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
4.5.14 Media/MAC SerDes Receive CRC Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Extended Page 4 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.6.1
CSR Access Controls and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
General Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
4.7.1
Reserved General Purpose Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.7.2
LED/SIGDET/GPIO Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.7.3
GPIO Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
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4.7.4
GPIO Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.7.5
GPIO Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.7.6
GPIO Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.7.7
Microprocessor Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
4.7.8
MAC Configuration and Fast Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.7.9
Two-Wire Serial MUX Control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
4.7.10 Two-Wire Serial MUX Control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.7.11 Two-Wire Serial MUX Data Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.7.12 Recovered Clock 1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
4.7.13 Recovered Clock 2 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
4.7.14 Enhanced LED Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
4.7.15 Global Interrupt Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Clause 45 Registers to Support Energy Efficient Ethernet and 802.3bf . . . . . . . . . . . . . . . . . . . . . . . 125
4.8.1
PMA/PMD Status 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.8.2
PCS Status 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4.8.3
EEE Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.8.4
EEE Wake Error Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.8.5
EEE Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.8.6
EEE Link Partner Advertisement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
5 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1
5.2
5.3
5.4
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1.1
VDD25 and VDDMDIO (2.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1.2
VDDMDIO (1.2 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
5.1.3
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.1.4
LED and GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.1.5
Internal Pull-Up or Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
5.1.6
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.1.7
SerDes Interface (SGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.1.8
Enhanced SerDes Interface (QSGMII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.1.9
Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.1.10 Thermal Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
5.2.1
Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.2.2
Recovered Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.2.3
SerDes Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
5.2.4
SerDes Driver Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.2.5
SerDes Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.2.6
SerDes Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
5.2.7
Enhanced SerDes Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.2.8
Basic Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.2.9
Enhanced Serial LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.2.10 Serial CPU Interface (SI) for Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
5.2.11 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.2.12 Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5.2.13 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
6 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
6.1
6.2
6.3
Pin Identifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pins by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2
GPIO and Two-Wire Serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.3
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.4
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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150
152
152
153
153
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6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
Power Supply and Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SerDes Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Serial Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SIGDET/GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Twisted Pair Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
155
156
156
157
157
157
158
7 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
7.1
7.2
7.3
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Moisture Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
8 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.16
8.17
8.18
8.19
8.20
8.21
8.22
Clause 45 register address post-increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Clause 45, register 7.60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
10BASE-T signal amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
10BASE-T Half-Duplex linkup after initial reset from power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Link performance in 100BASE-TX and 1000BASE-T modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Clause 36 PCS incompatibilities in 1000BASE-X media mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
1000BASE-X parallel detect mode with Clause 37 auto-negotiation enabled . . . . . . . . . . . . . . . . . . . 163
Near-end loopback non-functional in protocol transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Far-end loopback requires disabling Tx preamble fix for 1000M traffic . . . . . . . . . . . . . . . . . . . . . . . . 163
VTSS_MACSEC_uncontrolled_counters_get show incorrect counter values . . . . . . . . . . . . . . . . . . . 163
Controlled port counter if_in_octets does not get set correctly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
LED Duplex/Collision function not working when in protocol transfer mode 10/100 Mbps . . . . . . . . . 163
Fast Link Failover indication delay when using interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Anomalous Fast Link Failure indication in 1000BT Energy Efficient Ethernet mode . . . . . . . . . . . . . . 164
Anomalous PCS error indications in Energy Efficient Ethernet mode . . . . . . . . . . . . . . . . . . . . . . . . . 164
Auto-Negotiation Management Register Test failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Changing speed from 1 Gbps to 100 Mbps hangs MACsec engine . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Non-standard preamble frames discarded by MACsec engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Pause control frames pause_timer may be exceeded by MACsec engine . . . . . . . . . . . . . . . . . . . . . 164
MACsec engine may shrink the minimum 100M IPG during wire-speed transmission . . . . . . . . . . . . 165
Operate MACsec with flow control to handle bandwidth expansion . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Frames with nibbles after the FCS may be discarded by MACsec engine . . . . . . . . . . . . . . . . . . . . . 165
9 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
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Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Dual Media Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Copper Transceiver Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Fiber Media Transceiver Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SGMII MAC to 1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
QSGMII MAC to 1000BASE-X Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
QSGMII/SGMII MAC to 100BASE-FX Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
QSGMII/SGMII MAC to AMS and 1000BASE-X Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
QSGMII/SGMII MAC to AMS and 100BASE-FX Media SerDes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
QSGMII/SGMII MAC-to-AMS and Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
QSGMII/SGMII MAC to Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
QSGMII/SGMII MAC to Protocol Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1000BASE-X MAC to Cat5 Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SerDes MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
QSGMII MAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Cat5 Media Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Low Power Idle Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MACsec Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Secure Enterprise Infrastructure and WAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Secure Carrier Ethernet Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Untagged Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Standard MACsec Transform of Untagged Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Single-Tagged Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Standard MACsec Transform of Single-Tagged Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Dual-Tagged Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Standard MACsec Transform of Dual-Tagged Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Single-Tagged Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MACsec Transform to Single Tag Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Dual-Tagged Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MACsec Transform to Single and Dual Tag Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
EoMPLS with One Label . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Standard and Advanced MACsec Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
EoMPLS with Two Labels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Standard and Advanced MACsec Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MACsec in PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
MACsec Egress Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MACsec Ingress Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VLAN Tag Bypass Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
EoMPLS Header Bypass Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Capture FIFO Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Line Back-Pressure by Remote Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Host Back-Pressure by Remote Link Partner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Advanced Flow Control Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
MAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Automatic Media Sense Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.5 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.3 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5 V CMOS Single-Ended REFCLK Input Resistor Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
AC Coupling for REFCLK Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Inline Powered Ethernet Switch Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
ActiPHY State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
SPI Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
SPI Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
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Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
Figure 76
Figure 77
Figure 78
Figure 79
Figure 80
Figure 81
Figure 82
Figure 83
SMI Read Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
SMI Write Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
MDINT Configured as an Open-Drain (Active-Low) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Two-Wire Serial MUX with SFP Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Two-Wire Serial MUX Read and Write Register Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Far-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Near-End Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Connector Loopback Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Data Loops of the SerDes Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Test Access Port and Boundary Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Register Space Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
SGMII DC Transmit Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SGMII DC Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SGMII DC Driver Output Impedance Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
SGMII DC Input Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Thermal Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Test Circuit for Recovered Clock Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
QSGMII Transient Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Basic Serial LED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Enhanced Serial LED Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SI Input Data Timing Diagram for Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
SI Output Data Timing Diagram for Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Test Circuit for SI_DO Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
JTAG Interface Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Test Circuit for TDO Disable Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Serial Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Top-Left Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Top-Right Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
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Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Table 54
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
MAC Interface Mode Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Supported MDI Pair Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Standard MACsec Frame Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Advanced MACsec Frame Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MACsec Tag Parsing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Match Criteria and Maskable Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Egress SA Flow Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Ingress SA Flow Actions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Transform Record Format (Non-XPN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Context Control Word Fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Transform Record Format (XPN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Egress SA Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Egress Global Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Ingress SA Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Ingress Global Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Egress Per-User Global Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
802.1AE Correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Ingress Per-User Global Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
FCS Fault Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Ingress Global Stat Event Vector Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Ingress SA Stat Event Vector Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Egress Global Stat Event Vector Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Egress SA Stat Event Vector Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
AMS Media Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
REFCLK Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
SI_ADDR Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
LED Drive State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
LED Mode and Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Extended LED Mode and Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
LED Serial Bitstream Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Register Bits for GPIO Control and Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
SerDes Macro Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
JTAG Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
IDCODE JTAG Device Identification Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
USERCODE JTAG Device Identification Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
JTAG Instruction Code IEEE Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
IEEE 802.3 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Main Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Mode Control, Address 0 (0x00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Mode Status, Address 1 (0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Identifier 1, Address 2 (0x02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Identifier 2, Address 3 (0x03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Device Autonegotiation Advertisement, Address 4 (0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Autonegotiation Link Partner Ability, Address 5 (0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Autonegotiation Expansion, Address 6 (0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Autonegotiation Next Page Transmit, Address 7 (0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Autonegotiation LP Next Page Receive, Address 8 (0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
1000BASE-T Control, Address 9 (0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
1000BASE-T Status, Address 10 (0x0A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
MMD EEE Access, Address 13 (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
MMD Address or Data Register, Address 14 (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
1000BASE-T Status Extension 1, Address 15 (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
100BASE-TX/FX Status Extension, Address 16 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
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Table 62
Table 63
Table 64
Table 65
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
Table 83
Table 84
Table 85
Table 86
Table 87
Table 88
Table 89
Table 90
Table 91
Table 92
Table 93
Table 94
Table 95
Table 96
Table 97
Table 98
Table 99
Table 100
Table 101
Table 102
Table 103
Table 104
Table 105
Table 106
Table 107
Table 108
Table 109
Table 110
Table 111
Table 112
Table 113
1000BASE-T Status Extension 2, Address 17 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Bypass Control, Address 18 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Extended Control and Status, Address 19 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Extended Control and Status, Address 20 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Extended Control and Status, Address 21 (0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Extended Control and Status, Address 22 (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Extended PHY Control 1, Address 23 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Extended PHY Control 2, Address 24 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Interrupt Mask, Address 25 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Interrupt Status, Address 26 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Auxiliary Control and Status, Address 28 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
LED Mode Select, Address 29 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
LED Behavior, Address 30 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Extended/GPIO Register Page Access, Address 31 (0x1F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Extended Registers Page 1 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SerDes Media Control, Address 16E1 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Cu Media CRC Good Counter, Address 18E1 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Extended Mode Control, Address 19E1 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Extended PHY Control 3, Address 20E1 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Extended PHY Control 4, Address 23E1 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
EPG Control Register 1, Address 29E1 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
EPG Control Register 2, Address 30E1 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Extended Registers Page 2 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Cu PMD Transmit Control, Address 16E2 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
EEE Control, Address 17E2 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Extended Chip ID, Address 18E2 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Entropy Data, Address 19E2 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Extended Interrupt Mask, Address 28E2 (0x1C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Extended Interrupt Status, Address 29E2 (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Ring Resiliency, Address 30E2 (0x1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Extended Registers Page 3 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
MAC SerDes PCS Control, Address 16E3 (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
MAC SerDes PCS Status, Address 17E3 (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
MAC SerDes Cl37 Advertised Ability, Address 18E3 (0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
MAC SerDes Cl37 LP Ability, Address 19E3 (0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
MAC SerDes Status, Address 20E3 (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Media/MAC SerDes Tx Good Packet Counter, Address 21E3 (0x15) . . . . . . . . . . . . . . . . . . . . . 111
Media/MAC SerDes Tx CRC Error Counter, Address 22E3 (0x16) . . . . . . . . . . . . . . . . . . . . . . . 112
Media SerDes PCS Control, Address 23E3 (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Media SerDes PCS Status, Address 24E3 (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Media SerDes Cl37 Advertised Ability, Address 25E3 (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
MAC SerDes Cl37 LP Ability, Address 26E3 (0x1A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Media SerDes Status, Address 27E3 (0x1B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Media/MAC SerDes Receive CRC Good Counter, Address 28E3 (0x1C) . . . . . . . . . . . . . . . . . . 115
Media/MAC SerDes Receive CRC Error Counter, Address 29E3 (0x1D) . . . . . . . . . . . . . . . . . . 115
Extended Registers Page 4 Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
CSR Buffer, Address 17E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
CSR Buffer, Address 18E4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
General Purpose Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
LED/SIGDET/GPIO Control, Address 13G (0x0D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
GPIO Control 2, Address 14G (0x0E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
GPIO Input, Address 15G (0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
GPIO Output, Address 16G (0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
GPIO Input/Output Configuration, Address 17G (0x11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Microprocessor Command Register, Address 18G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
MAC Configuration and Fast Link Register, Address 19G (0x13) . . . . . . . . . . . . . . . . . . . . . . . . 121
Two-Wire Serial MUX Control 1, Address 20G (0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Two-Wire Serial MUX Interface Status and Control, Address 21G (0x15) . . . . . . . . . . . . . . . . . . 122
Two-Wire Serial MUX Data Read/Write, Address 22G (0x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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Table 141
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Table 149
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Table 157
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Table 169
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Table 171
Table 172
Recovered Clock 1 Control, Address 23G (0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Recovered Clock 2 Control, Address 24G (0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Enhanced LED Control, Address 25G (0x19) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Global Interrupt Status, Address 29G (0x1D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Clause 45 Registers Page Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
PMA/PMD Status 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
PCS Status 1, Address 3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
EEE Capability, Address 3.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
EEE Wake Error Counter, Address 3.22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
EEE Advertisement, Address 7.60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
EEE Advertisement, Address 7.61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
802.3bf Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
VDD25 and VDDMDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
VDDMDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Supply Voltage Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
LED and GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Internal Pull-Up or Pull-Down Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Reference Clock DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SerDes Driver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
SerDes Receiver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Enhanced SerDes Driver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Enhanced SerDes Receiver DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Current Consumption (MACsec Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
MACsec Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Thermal Diode Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Reference Clock AC Characteristics for QSGMII 125 MHz Differential Clock . . . . . . . . . . . . . . . 137
Recovered Clock AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SerDes Outputs AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
SerDes Driver Jitter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SerDes Input AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
SerDes Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Enhanced SerDes Outputs AC Specifications, SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Enhanced SerDes Outputs AC Specifications, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Enhanced SerDes Input AC Specifications, SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Enhanced SerDes Inputs AC Specifications, QSGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Enhanced SerDes Receiver Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Basic Serial LEDs AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Enhanced Serial LEDs AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
SI Timing Specifications for Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
JTAG Interface AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Serial Management Interface AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
PHY Latency in SGMII Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Stress Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Pin Type Symbol Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
GPIO and Two-Wire Serial Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Miscellaneous Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Power Supply and Ground Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
SerDes MAC Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SerDes Media Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SMI Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SIGDET/GPIO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
SPI Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Twisted Pair Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Thermal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
xii
Revision History
1
Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1
Revision 4.2
Revision 4.2 was published in May 2019. The following is a summary of the changes in this document.
•
•
•
•
1.2
The VeriPHY information was updated in the Flexibility section. For more information, see Flexibility,
page 3.
VeriPHY™ Cable Diagnostics section was updated. For more information, see VeriPHY Cable
Diagnostics, page 74.
The VeriPHY Control 1/2/3 sections were removed.
The references to the VeriPHY were removed from the Extended Registers Page 1 Space table. For
more information, see Table 69, page 98.
Revision 4.1
Revision 4.1 was published in August 2017. The following was a summary of the changes in this
document.
•
•
•
•
•
•
•
•
•
•
1.3
All references to LVDS were clarified to reflect LVDS compatibility.
All references to serial parallel interface were corrected to serial peripheral interface.
Operating modes were updated to correctly reflect available functionality. For more information, see
Operating Modes, page 5.
A note was added about the use of recovered clock outputs and fast link failure indication in EEE
mode. For more information, see Media Recovered Clock Outputs, page 59 and Fast Link Failure
Indication, page 66.
The equipment loop description was updated to correctly reflect available functionality. For more
information, see Equipment Loop, page 73.
EEE Control register descriptions were updated to indicate sticky bits. For more information, see
Table 79, page 105.
Media/MAC SerDes transmit CRC error counter register descriptions were updated. For more
information, see Table 92, page 112.
Some GPIO register names were updated to correctly reflect available functionality. For more
information, see General Purpose Registers, page 116.
Design considerations were updated. For more information, see Design Considerations, page 162.
Temperature specifications were added to the part ordering information. For more information, see
Table 172, page 166.
Revision 4.0
Revision 4.0 was published in November 2015. It was the first publication of this document
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
1
Product Overview
2
Product Overview
VSC8562-11 is a low-power, dual-port Gigabit Ethernet transceiver with two SerDes interfaces for dualport dual media capability. It also includes an integrated dual-port two-wire serial multiplexer (MUX) to
control SFPs or PoE modules. It has a low electromagnetic interference (EMI) line driver, and integrated
line side termination resistors that conserve both power and printed circuit board (PCB) space.
The VSC8562-11 device includes Intellisec™, Microsemi’s implementation of IEEE 802.1AE 128/256-bit
MACsec protocols to meet the security requirements for protecting data traversing Ethernet LANs. It
does input classification, frame encryption/decryption, performance, and latency monitoring.
The VSC8562-11 also supports a ring resiliency feature that allows a 1000BASE-T connected PHY port
to switch between master and slave timing without having to interrupt the 1000BASE-T link.
Using Microsemi’s EcoEthernet v2.0 PHY technology, the VSC8562-11 supports energy efficiency
features such as Energy Efficient Ethernet (EEE), ActiPHY link down power savings, and PerfectReach
that can adjust power based on the cable length. It also supports fully optimized power consumption in all
link speeds.
Microsemi's mixed signal and digital signal processing (DSP) architecture is a key operational feature of
the VSC8562-11, assuring robust performance even under less-than-favorable environmental conditions.
It supports both half-duplex and full-duplex 10BASE-T, 100BASE-TX, and 1000BASE-T communication
speeds over Category 5 (Cat5) unshielded twisted pair (UTP) cable at distances greater than 100 m,
displaying excellent tolerance to NEXT, FEXT, echo, and other types of ambient environmental and
system electronic noise. The device also supports two dual media ports that can support up to two
100BASE-FX, 1000BASE-X fiber, and/or triple-speed copper SFPs.
The following illustrations show a high-level, general view of typical VSC8562-11 applications.
Figure 1 •
Dual Media Application Diagram
½ QSGMII,
2x SGMII, or
2x 1000BASE-X MAC
½ QSGMII,
2x SGMII MAC, or
2x 1000BASE-X MAC
Figure 2 •
1.0 V
1.2 V
(optional)
2.5 V
2× RJ-45
and Magnetics
VSC8562
2 ports dual media
(fiber or copper)
SGMII or half QSGMII
MAC interface
SerDes
SCL/SDA
2× SFPs
(fiber or copper)
Copper Transceiver Application Diagram
½ QSGMII,
2x SGMII, or
2x 1000BASE-X MAC
½ QSGMII,
2x SGMII MAC, or
2x 1000BASE-X MAC
1.0 V
1.2 V
(optional)
2.5 V
VSC8562
2 ports copper media
SGMII or half QSGMII
MAC interface
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
2x RJ-45
and Magnetics
2
Product Overview
Figure 3 •
Fiber Media Transceiver Application Diagram
½ QSGMII,
2x SGMII, or
2x 1000BASE -X MAC
1.0 V
½ QSGMII,
2x SGMII MAC , or
2x 1000BASE-X MAC
2.1
1.2 V
(optional)
2.5 V
VSC 8562
2 ports fiber media
SGMII or half QSGMII
MAC interface
2× 1000 BASE -X SFP
or
2x 100BASE -FX SFP
Or
2x Copper SFP
Key Features
This section lists the main features and benefits of the VSC8562-11 device.
2.1.1
Low Power
•
•
•
•
2.1.2
Advanced Carrier Ethernet Support
•
•
•
•
•
2.1.3
Recovered clock outputs with programmable clock squelch control and fast link failure indication
(typical 0, then frames have been captured, read CAPT_DEBUG_TRIGGER_SA1/SA2 to
confirm if the packet for that SA has been captured. Bits will fall back to 0b automatically when a
packet is captured for the SA.
Stop the capture by programming CAPT_DEBUG_TRIGGER.ENABLE = 0 to enable software to
access the FIFO.
Read CAPT_DEBUG_DATA (0 to 127) to read the packet from the capture FIFO.
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
46
Functional Descriptions
3.6.8
Flow Control Buffer
The following list provides an overview of the flow control buffer functionality in the VSC8562-11 device.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
3.6.8.1
Frame buffering in egress to handle frame expansion by MACsec and flow control back-pressure to
host/switch ASIC.
Frame buffering in ingress to handle pause frame insertion (from host MAC) and rate adaptation.
Cut-through mode of operation.
Configurable pause reaction (including pause timer handling) for line received pause frames.
Pause generation triggers to host MAC based on configurable XOFF/XON thresholds.
Control queue and data queue with strict priority scheduling in egress with highest priority given to
control queue.
Transmit MAC control frames irrespective of pause state.
Rate adaptation between line and host clocks for PPM compensation.
Rate difference between line and host clocks based on LAN/WAN modes.
Flow control (back-pressure) feedback from MACsec block by compensating gap between frames.
Pass link fault/LF/RF/LPI in both directions using special control word in-band with frames.
EEE controller state machine for activating LPI and wake-up.
4X MTU buffering in egress.
Ingress buffer for pause frame insertion by host MAC.
ECC support in RAM's.
Frame drops recorded for statistics.
Sticky bits and interrupt.
Flow Control Handling
This section describes the basic flow control mode of operation. Buffering provided handles frame
expansion and its own latency. Buffering required for long interconnects that depend upon cable/fiber
length need to be provided separately. The following illustration shows the sequence of events when a
pause frame is received from line.
Figure 42 • Line Back-Pressure by Remote Link Partner
PHY with MACSec
xM II
FC Buffer
(Egress )
Host
MAC Rx
(Egress)
4
2
H
Host/
Switch/
MAC
MACSec
(Egress)
Line
MAC Tx
(Egress)
xM II
L
OR
AND
Tx-XO FF
3
xM II
Tx-XO N
Host
MAC Tx
(Ingress)
MACSec
(Ingress)
FC Buffer
(Ingress )
Line
MAC Rx
(Ingress)
xM II
1
The following steps describe the sequence of events depicted in the illustration.
1.
2.
Pause frame (XOFF) is received by PHY at line MAC Rx. This frame is internally consumed by MAC.
The MAC Rx signals the Tx FC buffer with pause received indication and pause quanta.
The Tx FC buffer goes to pause state at the next frame boundary. Pause timer will be maintained by
Tx FC buffer and is started only after it goes to pause state, which may be immediate in some cases.
The Tx FC buffer drain rate is 0 and fill rate can be max port speed. The Tx FC buffer signals XOFF
to host MAC Tx to schedule a pause transmission upstream. This signaling is shown via the optional
OR gate. Without back-pressured from the remote link partner the Tx FC buffer uses XOFF/XON
thresholds to signal XOFF/XON to host MAC Tx to manage frame expansion due to MACsec.
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
47
Functional Descriptions
3.
4.
The host MAC Tx can schedule a pause frame for transmission at the next frame boundary. The Tx
FC buffer needs to be able to hold at least one jumbo frame until XOFF pause is scheduled so that it
can continue to receive data downstream. The XOFF frame is then received by host/switch.
The host device can only stop transmission at next frame boundary because it may have started
transmitting a second jumbo frame.
The following configuration signals control the basic flow control mode.
•
•
•
PAUSE_REACT_ENA. Enables pause reaction and pause timer maintenance in egress flow control
buffer. Set to 1.
PAUSE_GEN_ENA. Enables XON and XOFF pause frame signaling to host MAC based on XON
and XOFF thresholds. Set to 1.
INCLUDE_PAUSE_RCVD_IN_PAUSE_GEN. Enables the optional OR and AND gate. Set to 1. If
not enabled the pause gen signaling to host MAC is purely based on XOFF/XON thresholds.
The following illustration shows the sequence of events when a pause frame is received from host.
Figure 43 • Host Back-Pressure by Remote Link Partner
PHY with MACSec
3
CRTL Queue
2
xMII
1
Host/
Switch/
MAC
xMII
Host
MAC Rx
(Egress)
5
FC Buffer
(Egress)
4
Host
MAC Tx
(Ingress )
MACSec
(Egress)
Line
MAC Tx
(Egress)
MACSec
(Ingress)
Line
MAC Rx
(Ingress)
FC Buffer
(Ingress)
xMII
xMII
The following steps describe the sequence of events depicted in the illustration.
1.
2.
3.
4.
5.
Host experiences congestion in ingress and sends pause (XOFF) to line.
Host MAC Rx receives pause frame. It is not enabled to react on received pause frames so it passes
the pause frame to Tx FC buffer.
Tx FC buffer maintains two logical queues, one for data and one for MAC control frames. If a data
frame is already scheduled and in progress, it passes on MAC control frames at the next boundary
to quickly relay MAC control frames to line, despite the presence of other data frames in the data
queue.
Tx FC buffer transmits any or all control frames in the control queue.
Pause frame passes through the MACsec block. The MACsec egress block detects frame as a
control frame and does not encrypt it. Frame eventually passes through the line MAC Tx block and
the rest of the PHY blocks.
TX_CTRL_QUEUE_ENA determines if the control queue is enabled in the egress flow control buffer.
This should be set to 1 in basic flow control mode. The physical memory of egress FC buffer can be
partitioned between data and control queues using TX_CTRL_QUEUE_START/END and
TX_DATA_QUEUE_START/END configuration fields.
3.6.8.2
Advanced Flow Control Handling
The following illustration shows the sequence of events when the PHY is configured to the advanced flow
control mode of operation. PAUSE_GEN_ENA needs to be set to 1 and other configuration bits of FC
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
48
Functional Descriptions
buffer, such as PAUSE_REAhT_ENA, INCLUDE_PAUSE_RCVD_IN_PAUSE_GEN, and
TX_CTRL_QUEUE_ENA, need to be set to 0. All other configurations for this mode are part of line MAC
and host MAC.
Figure 44 • Advanced Flow Control Handling
Tx-X O FF/
XO N
xM II
4
Host
MAC Rx
(Egress )
PHY with MACSec
FC Buffer
(Egress)
Line
MAC Tx
(Egress )
MACSec
(Egress )
H
xM II
L
2
Host/
Switch/
MAC
Tx -XO FF
3
xM II
Tx-X O FF
Host
MAC Tx
(Ingress )
MACSec
(Ingress )
FC Buffer
(Ingress )
Tx -XO N
Line
MAC Rx
(Ingress )
xM II
1
The following steps describe the sequence of events depicted in the illustration.
3.6.8.2.1
PHY Back-Pressured by Remote Link partner
1.
2.
3.6.8.2.2
Host Back-Pressuring Remote Link Partner
3.
4.
3.6.8.3
Pause frame (XOFF) is received by PHY at line MAC Rx. This frame is internally consumed by MAC.
Line MAC Rx signals line MAC Tx with pause received indication and pause quanta.
Line MAC Tx goes to pause state at the next frame boundary. Line MAC Tx stalls to pause the
pipeline. Pause timer maintained by line MAC Tx is started only after it goes to pause state. The Tx
FC buffer signals XOFF/XON to host MAC Tx based on XOFF/XON threshold.
System pause is consumed by host MAC Rx. Pause timer maintained in host MAC Rx (instead of
Tx) for egress direction to generate XOFF/XON pause gen signal for line MAC Tx.
Line MAC Tx stalls to send pause frame (either XOFF or XON). This path will work irrespective of
whether line MAC is in pause state.
Frame Drop Statistics
The following 32-bit counters provide frame drop statistics. These counters roll over to 0 when the
maximum value is reached.
3.6.8.3.1
TX_CTRL_QUEUE_OVERFLOW_DROP_CNT
Number of control frame drops due to overflow in the control queue of the egress flow control buffer.
3.6.8.3.2
TX_CTRL_QUEUE_UNDERFLOW_DROP_CNT
Number of control frame drops due to underflow in the control queue of the egress flow control buffer.
3.6.8.3.3
TX_CTRL_UNCORRECTED_FRM_DROP_CNT
Number of control frames aborted due to ECC check fail during reading from RAM in egress flow control
buffer.
3.6.8.3.4
TX_DATA_QUEUE_OVERFLOW_DROP_CNT
Number of data frame drops due to overflow in the data queue of the egress flow control buffer.
3.6.8.3.5
TX_DATA_QUEUE_UNDERFLOW_DROP_CNT
Number of data frame drops due to underflow in the data queue of the egress flow control buffer.
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
49
Functional Descriptions
3.6.8.3.6
TX_DATA_UNCORRECTED_FRM_DROP_CNT
Number of data frames aborted due to ECC check fail during reading from RAM in egress flow control
buffer.
3.6.8.3.7
RX_OVERFLOW_DROP_CNT
Number of frame drops due to overflow in the ingress flow control buffer.
3.6.8.3.8
RX_UNDERFLOW_DROP_CNT.
Number of frame drops due to underflow in the ingress flow control buffer.
3.6.8.3.9
RX_UNCORRECTED_FRM_DROP_CNT.
Number of frames aborted due to ECC check fail during reading from RAM in ingress flow control buffer.
3.6.9
Media Access Control
This section describes the media access control sub layer (MAC) block. There are two instances of MAC
block in each channel. One instance, which interfaces with MACsec and PCS/PMA, is called Line MAC
and other instance which interfaces with FC Buffer and PHY XS is called Host MAC.
The MAC is defined in IEEE 802.3, clauses 3 and 4. The purpose of the MAC is to control the MACsec
block access to the physical layer. In other words, it takes frames from the MACsec and converts those
to a continuous byte stream on the xMII interface. In doing so, it is responsible for frame CRC generation
and checking, preamble insertion and extraction, and pause frame generation and detection. The MAC
block also contains the counters for an SNMP management information base (MIB) statistics module.
The MAC block supports frame sizes up to 10240 bytes in both receive and transmit directions. The
maximum frame size is controlled by the host. The maximum frame size can also be set to the standard
1518 bytes or 1522 bytes, if desired. Maximum frame length restrictions are not enforced in the transmit
direction. The following illustration shows the block diagram of MAC.
Figure 45 • MAC Block Diagram
MAC
Rx Clock Domain
mac_pause_frm
Early Pause
Detector
WRAPPER
KERNEL
xMII Rx I /F
RX-MAC
Host I/ F to
Packet I/F
Converter
Pause
Frame
Detector
LF/ RF Status
LPI Detect
Packet Rx I /F
Pause frame Indication
CW
Generator
Pause State
Early Pause Detect
Packet /I F to
Host I/F
Converter
xMII Tx I /F
TX- MAC
Packet Tx I/F
Pause gen Signalling
MAC ready Indication
Pause
Frame
Generator
Force
LF/ RF/ LPI
CW Detect
Tx Clock Domain
Configuration, Status, Counters( CSR)
Interface
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
50
Functional Descriptions
3.6.9.1
MAC Transmit
The transmit section of the MAC contains three blocks, packet interface wrapper, pause frame generator,
and MAC Tx kernel. All three blocks operate off the same clock, TX_MAC_CLK.
The MAC Tx kernel block handles the reconciliation sublayer functions as per IEEE 802.3.
•
•
•
•
•
Calculates the CRC for pause frames generated by the pause frame generator.
Converts MAC frames to the xMII format and adds control characters for framing as required by
IEEE 802.3.
Generates the interframe gap (IFG) on the xMII using the deficit idle count algorithm to achieve an
average IPG of 12 bytes.
Shapes all the traffic to go out with an average IPG of 12 bytes after MACsec frame expansion.
Analyzes each packet and increments statistical counters used for RMON support.
The Pause Frame Generator (PFG) block performs the following two major functions.
•
•
Requests packets from the upstream blocks, when packets are present and the Tx direction is not in
the pause state (because a pause frame has been received in the Rx direction). They are forwarded
to the MAC Tx kernel block for further processing.
Generates flow control packets. Pause frames are generated based upon seeing the
MAC_PAUSE_FRM_GEN signal. For the Host MAC this signal is generated by the FC buffer based
upon programmable XOFF/XON threshold values in the FC buffer. In advance flow control mode of
operation the line MAC can also generate pause frames based on MAC_PAUSE_FRM_GEN signal
from Host MAC to relay pause frames that are deleted in Host MAC in this mode.
When the pause frame generator sees the MAC_PAUSE_FRM_GEN signal asserted, it generates pause
frames using settings in configuration registers. Part of the pause frame is the pause value, which
specifies how long the link partner (the network entity that the pause frame is destined for) stops sending
traffic. The pause value specifies the requested delay in bit times and uses the equation 512 ×
PAUSE_VALUE.
After the PFG starts generating pause frames, it continues to generate pause frames at specified
intervals until the de-assertion of the MAC_PAUSE_FRM_GEN signal. When this signal is deasserted,
the PFG does one of two things, depending upon the configuration in MAC_TX_PAUSE_MODE. In
normal mode, the PFG stops sending pause frames. This causes the link partner to start sending frames
again after its pause frame timer has expired. In XON mode, the PFG generates a single pause frame
with a pause value of 0 and sends it to the link partner. This causes the link partner to start sending
frames again right away.
The PFG contains a configurable pause frame interval register, MAC_TX_PAUSE_INTERVAL. This
register controls the time between generated pause frames when the FC buffer continues to request that
pause frames be generated.
The packet interface wrapper handles the following functions:
•
•
•
•
•
3.6.9.2
Provides the packet interfacing support to MACsec and FC buffer blocks. On this packet interface,
frames are transported without preamble and FCS.
Supports LF/RF/LPI generation on xMII interface through special control word received on packet
interface. This special control word is received on packet interface if relaying of LF/RF/LPI is desired
in MACsec subsystem.
Padding of frames whose length is less than 64 bytes. This is required for padding of MACsec short
length frames whose length is less than 64 bytes. This padding is enabled by configuring
ENABLE_TX_PADDING in host MAC.
Standard preamble insertion.
FCS insertion.
MAC Receive
The receive section of the MAC contains three blocks, MAC Rx kernel, pause frame detector, and packet
interface wrapper. All three blocks operate off the same clock, RX_MAC_CLK.
The MAC Rx kernel receives the byte stream from the xMII interface and handles the reconciliation sub
layer processing to convert them to frames sent over the host interface. It checks the CRC of each frame
for validity and abort marks any frame with an invalid CRC. A variety of length checks are performed,
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
51
Functional Descriptions
including looking for short frames (less than 64 bytes), oversized, and jabber frames (longer than the
configured maximum). VLAN tagging is supported up to three VLAN tags. Length checks are adjusted
accordingly when VLAN tags are encountered. The Rx kernel supports counters in support of RMON
statistics.
The pause frame detector (PFD) detects and reacts to valid pause frames received by the MAC from the
xMII interface. The PFD reacts to PAUSE frames with a DMAC equal to either the multicast address (0180-c2-00-00-01) or the address of the MAC (MAC_ADDRESS_LSB/MSB register value) in accordance
with IEEE 802.3-2008, Annex 31B. Pause frames that are too short, or have invalid CRC, are abort
marked and ignored by the PFD. Pause frames carry a pause value that indicates the desired pause time
in units of pause quanta, where 1 pause-quantum equals 512 bit times. Because the data path in the
MAC is 8 bytes (or 64 bits) wide, the extracted pause value is multiplied by 8 and stored in the pause
counter. A signal from the PFG indicates if a packet is currently being transmitted.
After the current packet has completed or if there is no packet, the PFD tells the PFG to stop requesting
packets (XOFF) and the pause counter is decremented by one for each MAC Rx clock cycle. When the
counter reaches 0, the PFG is instructed that it may resume requesting packets from the upstream
blocks. Pause frames must have a destination address equal to either the multicast address (01-80-c200-00-01) or the address of the MAC (MAC_ADDRESS_LSB/MSB register value). If there is no match,
then the pause frame is ignored. If a pause frame is received while the Tx direction is already being
paused (because a valid pause frame was already received and the pause counter had not yet counted
down to 0), the pause counter is simply updated with the new value. If the received pause value is 0, then
the state machine transitions immediately to END_PAUSE and frames are again requested from the
upstream blocks.
The packet interface wrapper handles the following functions:
•
•
•
•
3.6.9.3
Provides the packet interfacing support to MACsec and FC buffer blocks. On this packet interface,
frames are transported without preamble and FCS.
Supports LF/RF/LPI indication on packet interface through special control word. This special control
word is relayed to other MAC if relaying of LF/RF/LPI is desired.
Preamble strip on packet interface.
FCS check and strip.
RMON Statistical Counters
The following counters count the number of bytes or frames received or transmitted. The counters count
continuously and are only cleared if the device is reset or the counter is written with 0 through the CPU
interface. These counters roll-over to 0 when the maximum value is reached. Unless specified otherwise,
each counter is 32 bits.
•
•
•
•
•
RX_IN_BYTES_CNT (40 bits) counts the total bytes received including preamble
RX_OK_BYTES_CNT (40 bits) counts the number of bytes received in valid frames
RX_BAD_BYTES_CNT counts the number of bytes received in invalid frames
TX_OUT_BYTES_CNT (40 bits) counts the total number of bytes transmitted including preamble
TX_OK_BYTES_CNT (40 bits) counts the number of bytes in successfully transmitted frames
The following counters are based on the type of frame received or transmitted.
•
•
•
•
•
•
•
•
•
RX_PAUSE_CNT counts the number of pause frames received
RX_UNSUP_OPCODE_CNT counts the number of control frames received with unsupported
opcodes
RX_UC_CNT counts the number of unicast frames received
RX_MC_CNT counts the number of multicast frames received
RX_BC_CNT counts the number of broadcast frames received
TX_PAUSE_CNT counts the number of pause frames transmitted
TX_UC_CNT counts the number of unicast frames transmitted
TX_MC_CNT counts the number of multicast frames transmitted
TX_BC_CNT counts the number of broadcast frames transmitted
The following error counters are provided.
•
•
RX_SYMBOL_ERR_CNT counts the number of symbol errors received
RX_CRC_ERR_CNT counts the number of frames received with CRC errors
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Functional Descriptions
•
•
•
•
•
•
•
RX_UNDERSIZE_CNT counts the number of undersized frames received with valid CRC
RX_FRAGMENTS_CNT counts the number of undersized frames received with invalid CRC
RX_IN_RANGE_LENGTH_ERR_CNT counts the number of frames where the length field does not
match the frame length
RX_OUT_OF_RANGE_LENGTH_ERR_CNT counts the number of frames with an illegal length
field
RX_OVERSIZE_CNT counts the number of oversize frames with valid CRC
RX_JABBERS_CNT counts the number of oversize frames with an invalid CRC
RX_XGMII_PROT_ERR_CNT counts the number of XGMII protocol errors detected.
The following size histogram counters are provided for both transmit and receive directions.
•
•
•
•
•
•
•
Frames with 64-byte payloads
Frames with 65-byte to 127-byte payloads
Frames with 128-byte to 255-byte payloads
Frames with 256-byte to 511-byte payloads
Frames with 512-byte to 1023-byte payloads
Frames with 1024-byte to 1518-byte payloads
Frames with 1519-byte to maximum size payloads
Frame size counters also count invalid frames, as long as they are not short frames, fragments, long
frames, or jabber frames. Long frames are defined as those greater than MAX_LEN bytes.
3.7
Automatic Media Sense Interface Mode
Automatic media sense (AMS) mode automatically sets the media interface to Cat5 mode or SerDes
mode. The active media mode chosen is based on the automatic media sense preferences set in the
device register 23, bit 11. The following illustration shows a block diagram of AMS functionality on ports 0
through 3 of the VSC8562-11 device.
Figure 46 • Automatic Media Sense Block Diagram
PHY port_n
Cat5
MAC
TD
RD
SGMII/
QSGMII
Serial MAC
Auto Sense
Logic
SerDes
SIGDET
Fiber Optic
Module
When both the SerDes and Cat5 media interfaces attempt to establish a link, the preferred media
interface overrides a linkup of the nonpreferred media interface. For example, if the preference is set for
SerDes mode and Cat5 media establishes a link, Cat5 becomes the active media interface. However,
after the SerDes media interface establishes a link, the Cat5 interface drops its link because the
preference was set for SerDes mode. In this scenario, the SerDes preference determines the active
media source until the SerDes link is lost. Also, Cat5 media cannot link up unless there is no SerDes
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
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Functional Descriptions
media link established. The following table shows the possible link conditions based on preference
settings.
AMS Media Preferences
Table 25 •
Preference
Setting
Cat5 Linked,
Fiber Not Linked
SerDes Linked,
Cat5 Not Linked
Cat5 Linked,
SerDes Attempts
to Link
SerDes Linked,
Cat5 Attempts
to Link
Both Cat5 and
SerDes Attempt
to Link
SerDes
Cat5
SerDes
SerDes
SerDes
SerDes
Cat5
Cat5
SerDes
Cat5
Cat5
Cat5
The status of the media mode selected by the AMS can be read from device register 20E1, bits 7:6. It
indicates whether copper media, SerDes media, or no media is selected. Each PHY has four automatic
media sense modes. The difference between the modes is based on the SerDes media modes:
•
•
•
SGMII or QSGMII MAC to AMS and 1000BASE-X SerDes
SGMII or QSGMII MAC to AMS and 100BASE-FX SerDes
SGMII or QSGMII MAC to AMS and SGMII (protocol transfer)
For more information about SerDes media mode functionality with AMS enabled, see SerDes Media
Interface, page 12.
3.8
Reference Clock
The device reference clock supports both 25 MHz and 125 MHz clock signals. It can be either differential
or single-ended. If differential, it must be capacitively coupled and LVDS compatible.
3.8.1
Configuring the Reference Clock
The REFCLK_SEL2 pin configures the reference clock speed. The following table shows the functionality
and associated reference clock frequency.
Table 26 •
REFCLK Frequency Selection
REFCLK_SEL2 Frequency
3.8.2
0
25 MHz
1
125 MHz
Single-Ended REFCLK Input
To use a single-ended reference clock, an external resistor network is required. The purpose of the
network is to limit the amplitude and to adjust the center of the swing. The configurations for a singleended REFCLK, with the clock centered at 1 V and a 500 mV peak-to-peak swing, are shown in the
following illustrations.
Figure 47 • 2.5 V CMOS Single-Ended REFCLK Input Resistor Network
VDD1A
2.5 V
CMOS
220 Ω
910 Ω
REFCLK_P
REFCLK_N
VDD1A
VSSA
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Functional Descriptions
Figure 48 • 3.3 V CMOS Single-Ended REFCLK Input Resistor Network
VDD1A
3.3 V
CMOS
270 Ω
430 Ω
REFCLK_P
REFCLK_N
VDD1A
VSSA
Figure 49 • 5 V CMOS Single-Ended REFCLK Input Resistor Network
VDD1A
5V
CMOS
430 Ω
300 Ω
REFCLK_P
REFCLK_N
VDD1A
VSSA
3.8.3
Differential REFCLK Input
AC coupling is required when using a differential REFCLK. Differential clocks must be capacitively
coupled and LVDS-compatible. The following illustration shows the configuration.
Figure 50 • AC Coupling for REFCLK Input
REFCLK_P
PHY Equivalent
Termination Circuit
0.1 µF
50 Ω
VTT (Internal Voltage)
50 Ω
REFCLK_N
0.1 µF
3.9
Ethernet Inline Powered Devices
The VSC8562-11 can detect legacy inline powered devices in Ethernet network applications. Inline
powered detection capability is useful in systems that enable IP phones and other devices (such as
wireless access points) to receive power directly from their Ethernet cable, similar to office digital phones
receiving power from a private branch exchange (PBX) office switch over telephone cabling. This type of
setup eliminates the need for an external power supply and enables the inline powered device to remain
active during a power outage, assuming that the Ethernet switch is connected to an uninterrupted power
supply, battery, back-up power generator, or other uninterruptable power source.
For more information about legacy inline powered device detection, visit the Cisco Web site at
www.cisco.com. The following illustration shows an example of an inline powered Ethernet switch
application.
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
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Functional Descriptions
Figure 51 • Inline Powered Ethernet Switch Diagram
Gigabit Switch
SGMII/
QSGMII
Interface
Processor
Control
SMI
PHY_port0
PHY_port1
PHY_portn
Transformer
Transformer
Transformer
RJ-45
I/F
RJ-45
I/F
RJ-45
I/F
Link
Partner
Link
Partner
Inline,
Power-Over-Ethernet
(PoE)
Power Supply
Cat5
Link
Partner
The following procedure describes the process that an Ethernet switch must perform to process inline
power requests made by a link partner (LP) that is, in turn, capable of receiving inline power:
1.
2.
3.
4.
5.
6.
Enable the inline powered device detection mode on each VSC8562-11 PHY using its serial
management interface. Set register bit 23E1.10 to 1.
Ensure that the VSC8562-11 autonegotiation enable bit (register 0.12) is also set to 1. In the
application, the device sends a special fast link pulse (FLP) signal to the LP. Reading register
bit 23E1.9:8 returns 00 during the search for devices that require power over Ethernet (PoE).
The VSC8562-11 PHY monitors its inputs for the FLP signal looped back by the LP. An LP capable
of receiving PoE loops back the FLP pulses when the LP is in a powered down state. This is
reported when VSC8562-11 register bit 23E1.9:8 reads back 01. It can also be verified as an inline
power detection interrupt by reading VSC8562-11 register bit 26.9, which should be a 1, and which
is subsequently cleared and the interrupt de-asserted after the read. When an LP device does not
loop back the FLP after a specific time, VSC8562-11 register bit 23E1.9:8 automatically resets to 10.
If the VSC8562-11 PHY reports that the LP requires PoE, the Ethernet switch must enable inline
power on this port, externally of the PHY.
The PHY automatically disables inline powered device detection when the VSC8562-11 register bits
23E1.9:8 automatically reset to 10, and then automatically changes to its normal autonegotiation
process. A link is then autonegotiated and established when the link status bit is set (register bit 1.2
is set to 1).
In the event of a link failure (indicated when VSC8562-11 register bit 1.2 reads 0), it is recommended
that the inline power be disabled to the inline powered device external to the PHY. The VSC8562-11
PHY disables its normal autonegotiation process and re-enables its inline powered device detection
mode.
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Functional Descriptions
3.10
IEEE 802.3af PoE Support
The VSC8562-11 device is compatible with designs that are intended for use in systems that supply
power to data terminal equipment (DTE) by means of the MDI or twisted pair cable, as described in IEEE
802.3af Clause 33.
3.11
ActiPHY Power Management
In addition to the IEEE-specified power-down control bit (device register bit 0.11), the device also
includes an ActiPHY power management mode for each PHY. This mode enables support for powersensitive applications. It utilizes a signal-detect function that monitors the media interface for the
presence of a link to determine when to automatically power-down the PHY. The PHY wakes up at a
programmable interval and attempts to wake up the link partner PHY by sending a burst of FLP over
copper media.
The ActiPHY power management mode in the VSC8562-11 is enabled on a per-port basis during normal
operation at any time by setting register bit 28.6 to 1.
The following operating states are possible when ActiPHY mode is enabled:
•
•
•
Low power state
Link partner wake-up state
Normal operating state (link-up state)
The VSC8562-11 switches between the low power state and LP wake-up state at a programmable rate
(the default is two seconds) until signal energy has been detected on the media interface pins. When
signal energy is detected, the PHY enters the normal operating state. If the PHY is in its normal operating
state and the link fails, the PHY returns to the low power state after the expiration of the link status timeout timer. After reset, the PHY enters the low power state.
When autonegotiation is enabled in the PHY, the ActiPHY state machine operates as described. When
autonegotiation is disabled and the link is forced to use 10BASE-T or 100BASE-TX modes while the
PHY is in its low power state, the PHY continues to transition between the low power and LP wake-up
states until signal energy is detected on the media pins. At that time, the PHY transitions to the normal
operating state and stays in that state even when the link is dropped. When autonegotiation is disabled
while the PHY is in the normal operation state, the PHY stays in that state when the link is dropped and
does not transition back to the low power state.
The following illustration shows the relationship between ActiPHY states and timers.
Figure 52 • ActiPHY State Diagram
Low Power State
Signal Energy Detected on
Media
FLP Burst or
Clause 37 Restart
Signal Sent
Sleep Timer Expires
Timeout Timer Expires and
Auto-negotiation Enabled
LP Wake-up
State
Normal
Operation State
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Functional Descriptions
3.11.1
Low Power State
In the low power state, all major digital blocks are powered down. However, the SMI interface (MDC,
MDIO, and MDINT) functionality is provided.
In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low
power state and transitions to the normal operating state when signal energy is detected on the media.
This happens when the PHY is connected to one of the following:
•
•
Autonegotiation-capable link partner
Another PHY in enhanced ActiPHY LP wake-up state
In the absence of signal energy on the media pins, the PHY periodically transitions from low-power state
to LP wake-up state, based on the programmable sleep timer (register bits 20E1.14:13). The actual sleep
time duration is randomized from –80 ms to 60 ms to avoid two linked PHYs in ActiPHY mode entering a
lock-up state during operation.
3.11.2
Link Partner Wake-Up State
In the link partner wake-up state, the PHY attempts to wake up the link partner. Up to three complete FLP
bursts are sent on alternating pairs A and B of the Cat5 media for a duration based on the wake-up timer,
which is set using register bits 20E1.12:11.
In this state, SMI interface (MDC, MDIO, and MDINT) functionality is provided.
After sending signal energy on the relevant media, the PHY returns to the low power state.
3.11.3
Normal Operating State
In the normal operating state, the PHY establishes a link with a link partner. When the media is
unplugged or the link partner is powered down, the PHY waits for the duration of the programmable link
status time-out timer, which is set using register bit 28.7 and bit 28.2. It then enters the low power state.
3.12
SPI I/O Register Access
The VSC8562-11 device provides a bidirectional SPI I/O interface for register access to handle MACsec
communication to the device. The device uses one slave select (SS) per slave for a simple slave design,
and to share the SCLK, MOSI, and MISO signals. The SPI I/O port is fully independent of either the SPI
time stamp input or output ports.
The following illustrations show the write and read cycle format supported by the VSC8562-11 device,
with LSB_FIRST=0, BIG_ENDIAN=1, and PADDING _BYTES=3. No other formats are supported.
Figure 53 • SPI Write Cycles
SPI_CS
SPI_Clk
Bigendian mode, Most significant bit first
SPI_DI
2 2 1 1 1 1 1 1 1 1 1 1
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
Serial Address (SI_ADDR)
Serial Data
SPI_DO
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Functional Descriptions
Figure 54 • SPI Read Cycle
SPI_CS
...
SPI_Clk
...
Big endian mode, Most significant bit first, three-byte padding
2 2 1 1 1 1
1 0 9 8 7 6
SPI_DI
1 1 1 1 1 1
5 4 3 2 1 0
9 8 7 6 5
4 3 2 1 0
Serial Address (SI_ADDR)
3 3 2
1 0 9
SPI_DO
2 2 2 2 2 2
8 7 6 5 4 3
2 2 2 1 1
2 1 0 9 8
padding (3-bytes)
1 1 1 1 1 1
7 6 5 4 3 2
1 1
9 8 7 6
1 0
5 4 3 2 1
0
Serial Data
A 25 MHz SPI operating rate is used to access the CSR address space.
The 22-bit address (indicated as SI_ADDR), is composed of a 2-bit ring select, an 8-bit Target ID, and a
12-bit register address. This register address represents a word address where a word is 32 bits. The
SPI data is 32 bits and is consistent with this mapping.
Table 27 •
SI_ADDR Mapping
Bit
Description
21:20
CSR ring select
00: Ring 0
01: Reserved
10: Reserved
11: Reserved
19:14
Target ID[7:2]
13:12
Target ID [1:0] for most targets
CSR register address[13:12] for MACsec INGR/EGR Targets
11:0
CSR register address[11:0]
The 2-bit ring select (SI_ADDR[21:20]) selects the CSR ring. A coding of 00 selects ring 0. Coding of 01,
10, and 11 are reserved.
SI_ADDR[19:14] maps to Target ID[7:2] and SI_ADDR[11:0] maps to CSR register address bits 11:0. The
Target ID[1:0] and CSR register address bits 13:12 depends on Target ID[5:3].
Target ID[5:3] bits set to 111 access the MACsec INGR or MACsec EGR registers. In this case, Target
ID[1:0] is hard-coded to 00 and the CSR address bits 13:12 is supplied by SI_ADDR[13:12]. In all other
cases, Target ID[1:0] is supplied by SI_ADDR[13:12] and the CSR address bits 13:12 is hard-coded to
00.
The Chip ID, Extended Chip ID, and Revision Code can be read at Target ID 0x40, address 0xFFF.
3.13
Media Recovered Clock Outputs
For Synchronous Ethernet applications, the VSC8562-11 includes two recovered clock output pins,
RCVRDCLK1 and RCVRDCLK2, controlled by registers 23G and 24G, respectively. The recovered clock
pins are synchronized to the clock of the active media link.
To enable recovered clock output, set register 23G or 24G, bit 15, to 1. By default, the recovered clock
output pins are disabled and held low, including when NRESET is asserted. Registers 23G and 24G also
control the PHY port for clock output, the clock source, the clock frequency (either 25 MHz or 31.25 MHz
or 125 MHz), and squelch conditions.
Note: When EEE is enabled on a link, the use of the recovered clock output is not recommended due to long
holdovers occurring during EEE quiet/refresh cycles.
3.13.1
Clock Selection Settings
On each pin, the recovered clock supports the following sources, as set by registers 23G or 24G, bits 2:0:
VMDS-10475 VSC8562-11 Datasheet Revision 4.2
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Functional Descriptions
•
Fiber SerDes media
•
Copper media
•
Copper transmitter TCLK output (RCVRDCLK1 only)
Note: When using the automatic media sense feature, the recovered clock output cannot automatically change
between each active media. Changing the media source must be managed through the recovered clock
register settings.
Adjust the squelch level to enable 1000BASE-T master mode recovered clock for SyncE operation. This
is accomplished by changing the 23G and 24G register bits 5:4 to 01. This setting also provides clock out
for 10BASE-T operation. For 1000BASE-T master mode, the clock is based on the VSC8562-11
REFCLK input, which is a local clock.
3.13.2
Clock Output Squelch
Under certain conditions, the PHY outputs a clock based on the REFCLK_P and REFCLK_N pins, such
as when there is no link present or during autonegotiation. To prevent an undesirable clock from
appearing on the recovered clock pins, the VSC8562-11 squelches, or inhibits, the clock output based on
any of the following criteria:
•
•
•
•
No link is detected (the link status register 1, bit 2 = 0).
The link is found to be unstable using the fast link failure detection feature. The
GPIO9/FASTLINK-FAIL pin is asserted high when enabled.
The active link is in 10BASE-T or in 1000BASE-T master mode. These modes produce unreliable
recovered clock sources.
CLK_SQUELCH_IN is enabled to squelch the clock.
Use registers 23G or 24G, bits 5:4 to configure the clock squelch criteria. These registers can also
disable the squelch feature. The CLK_SQUELCH_IN pin controls the squelching of the clock. Both
RCVRDCLK1 and RCVRDCLK2 are squelched when the CLK_SQUELCH_IN pin is high.
3.14
Serial Management Interface
The VSC8562-11 device includes an IEEE 802.3-compliant serial management interface (SMI) that is
affected by use of its MDC and MDIO pins. The SMI provides access to device control and status
registers. The register set that controls the SMI consists of 32 16-bit registers, including all required
IEEE-specified registers. Also, there are additional pages of registers accessible using device register
31.
Energy efficient Ethernet control registers are available through the SMI using Clause 45 registers and
Clause 22 register access in registers 13 through 14. For more information, see Table 51, page 87 and
Table 118, page 125.
The SMI is a synchronous serial interface with input data to the VSC8562-11 on the MDIO pin that is
clocked on the rising edge of the MDC pin. It is a multiple-target bus that incorporates open-collector
drivers along with an external pull-up to share the MDIO data line between multiple PHY chips. The
output data is sent on the MDIO pin on the rising edge of the MDC signal. The interface can be clocked
at a rate from 0 MHz to 12.5 MHz, depending on the total load on MDIO. An external 2-kΩ pull-up resistor
is required on the MDIO pin.
3.14.1
SMI Frames
Data is transferred over the SMI using 32-bit frames with an optional, arbitrary-length preamble. Before
the first frame can be sent, at least two clock pulses on MDC must be provided with the MDIO signal at
logic one to initialize the SMI state machine. The following illustrations show the SMI frame format for
read and write operations.
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Functional Descriptions
Figure 55 • SMI Read Frame
Station manager drives MDIO
PHY drives MDIO
MDC
MDIO
Z
Z
1
0
1
Idle Preamble SFD
(optional)
1
0
Read
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0 Z
PHY Address
Register Address
to PHY
0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Z
TA
Register Data
from PHY
Z
Idle
Figure 56 • SMI Write Frame
Station manager drives MDIO (PHY tri-states MDIO during the entire sequence)
MDC
MDIO
Z
Z
1
0
1
0
1
Idle Preamble SFD Write
(optional)
A4 A3 A2 A1 A0 R4 R3 R2 R1 R0
PHY Address
Register Address
to PHY
1
0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Z
TA
Register Data
to PHY
Z
Idle
The following list provides additional information about the terms used in the SMI read and write timing
diagrams.
•
•
•
•
•
•
•
•
•
3.14.2
Idle During idle, the MDIO node goes to a high-impedance state. This allows an external pull-up
resistor to pull the MDIO node up to a logical 1 state. Because the idle mode does not contain any
transitions on MDIO, the number of bits is undefined during idle.
Preamble By default, preambles are not expected or required. The preamble is a string of ones. If
it exists, the preamble must be at least 1 bit; otherwise, it can be of an arbitrary length.
Start of Frame (SFD) A pattern of 01 indicates the start of frame. If the pattern is not 01, all
following bits are ignored until the next preamble pattern is detected.
Read or Write Opcode A pattern of 10 indicates a read. A 01 pattern indicates a write. If the bits
are not either 01 or 10, all following bits are ignored until the next preamble pattern is detected.
PHY Address The particular VSC8562-11 responds to a message frame only when the received
PHY address matches its physical address. The physical address is 5 bits long (4:0).
Register Address The next five bits are the register address.
Turnaround The two bits used to avoid signal contention when a read operation is performed on
the MDIO are called the turnaround (TA) bits. During read operations, the VSC8562-11 drives the
second TA bit, a logical 0.
Data The 16-bits read from or written to the device are considered the data or data stream. When
data is read from a PHY, it is valid at the output from one rising edge of MDC to the next rising edge
of MDC. When data is written to the PHY, it must be valid around the rising edge of MDC.
Idle The sequence is repeated.
SMI Interrupt
The SMI includes an output interrupt signal, MDINT, for signaling the station manager when certain
events occur in the VSC8562-11.
The MDINT pin is configured for open-drain (active-low). Tie the pin to a pull-up resistor to VDDIO. The
following illustration shows the configuration.
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Functional Descriptions
Figure 57 • MDINT Configured as an Open-Drain (Active-Low) Pin
VDDIO
PHY_n
Interrupt Pin Enable
(Register 25.15)
External Pull-up
Resistor at the
Station Manager
MDINT
(to the Station
Manager)
MDINT
Interrupt Pin Status
(Register 26.15)
When a PHY generates an interrupt, the MDINT pin is asserted by driving low if the interrupt pin enable
bit (MII register 25.15) is set.
3.15
LED Interface
The LED interface supports the following configurations: direct drive, basic serial LED mode, and
enhanced serial LED mode. The polarity of the LED outputs is programmable and can be changed
through register 17E2, bits 13:10. The default polarity is active low.
Direct drive mode provides four LED signals per port, LED0_[0:3] through LED3_[0:3]. The mode and
function of each LED signal can be configured independently. When serial LED mode is enabled, the
direct drive pins not used by the serial LED interface remain available.
In basic serial LED mode, all signals that can be displayed on LEDs are sent as LED_Data and
LED_CLK for external processing. In enhanced serial LED mode, up to four LED signals per port can be
sent as LED_Data, LED_CLK, LED_LD, and LED_Pulse. The following sections provide detailed
information about the various LED modes.
Note: LED number is listed using the convention, LED_.
The following table shows the bit 9 settings for register 14G that are used to control the LED behavior for
all the LEDs in VSC8562-11.
Table 28 •
3.15.1
LED Drive State
Setting
Active
Not Active
14G.9 = 1 (default)
Ground
Tristate
14G.9 = 0 (alternate setting)
Ground
VDD
LED Modes
Each LED pin can be configured to display different status information that can be selected by setting the
LED mode in register 29. The modes listed in the following table are equivalent to the setting used in
register 29 to configure each LED pin. The default LED state is active low and can be changed by
modifying the value in register 17E2, bits 13:10. The blink/pulse-stretch is dependent on the LED
behavior setting in register 30.
The following table provides a summary of the LED modes and functions.
Table 29 •
LED Mode and Function Summary
Mode Function Name
LED State and Description
0
1: No link in any speed on any media interface.
0: Valid link at any speed on any media interface.
Blink or pulse-stretch = Valid link at any speed on any media
interface with activity present.
Link/Activity
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Functional Descriptions
Table 29 •
LED Mode and Function Summary (continued)
Mode Function Name
LED State and Description
1
Link1000/Activity
1: No link in 1000BASE-T or 1000BASE-X.
0: Valid 1000BASE-T or 1000BASE-X.
Blink or pulse-stretch = Valid 1000BASE-T or 1000BASE-X
link with activity present.
2
Link100/Activity
1: No link in 100BASE-TX or 100BASE-FX.
0: Valid 100BASE-TX or 100BASE-FX.
Blink or pulse-stretch = Valid 100BASE-TX or 100BASE-FX
link with activity present.
3
Link10/Activity
1: No link in 10BASE-T.
0: Valid 10BASE-T link.
Blink or pulse-stretch = Valid 10BASE-T link with activity
present.
4
Link100/1000/Activity
1: No link in 100BASE-TX, 100BASE-FX, 1000BASE-X, or
1000BASE-T.
0: Valid 100BASE-TX, 100BASE-FX, 1000BASE-X, or
1000BASE-T link. Blink or pulse-stretch = Valid 100BASE-TX,
100BASE-FX, 1000BASE-X, or 1000BASE-T link with activity
present.
5
Link10/1000/Activity
1: No link in 10BASE-T, 1000BASE-X, or 1000BASE-T.
0: Valid 10BASE-T, 1000BASE-X, or 1000BASE-T link.
Blink or pulse-stretch = Valid 10BASE-T, 1000BASE-X, or
1000BASE-T link with activity present.
6
Link10/100/Activity
1: No link in 10BASE-T, 100BASE-FX, or 100BASE-TX.
0: Valid 10BASE-T, 100BASE-FX, or 100BASE-TX link.
Blink or pulse-stretch = Valid 10BASE-T, 100BASE-FX, or
100BASE-TX link with activity present.
7
Link100BASE-FX/1000BASE-X/ 1: No link in 100BASE-FX or 1000BASE-X.
Activity
0: Valid 100BASE-FX or 1000BASE-X link.
Blink or pulse-stretch = Valid 100BASE-FX or 1000BASE-X
link with activity present.
8
Duplex/Collision
1: Link established in half-duplex mode, or no link established.
0: Link established in full-duplex mode.
Blink or pulse-stretch = Link established in half-duplex mode
but collisions are present.
9
Collision
1: No collision detected.
Blink or pulse-stretch = Collision detected.
10
Activity
1: No activity present.
Blink or pulse-stretch = Activity present (becomes TX activity
present when register bit 30.14 is set to 1).
11
100BASE-FX/1000BASE-X Fiber 1: No 100BASE-FX or 1000BASE-X activity present.
Activity
Blink or pulse-stretch = 100BASE-FX or 1000BASE-X activity
present (becomes Rx activity present when register bit 30.14
is set to 1).
12
Autonegotiation Fault
1: No autonegotiation fault present.
0: Autonegotiation fault occurred.
13
Serial Mode
Serial stream. See Basic Serial LED Mode, page 65. Only
relevant on PHY port 0 and reserved in others.
14
Force LED Off
1: De-asserts the LED1.
15
Force LED On
0: Asserts the LED1.
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Functional Descriptions
1.
3.15.2
Setting this mode suppresses LED blinking after reset.
Extended LED Modes
In addition to the LED modes in register 29, there are also additional LED modes that are enabled on the
LED0_[1:0] pins whenever the corresponding register 19E1, bits 15 to 12 are set to 1. Each of these bits
enables extended modes on a specific LED pin and these extended modes are shown in the following
table. For example, LED0 = mode 17 means that register 19E1 bit 12 = 1 and register 29 bits 3 to
0 = 0001.
The following table provides a summary of the extended LED modes and functions.
Table 30 •
Extended LED Mode and Function Summary
Mode Function Name
3.15.3
LED State and Description
16
Link1000BASE-X Activity 1: No link in 1000BASE-X.
0: Valid 1000BASE-X link.
17
Link100BASE-FX Activity 1: No link in 100BASE-FX.
0: Valid 100BASE-FX link.
18
1000BASE-X Activity
1: No 1000BASE-X activity present.
Blink or pulse-stretch = 1000BASE-X activity present.
19
100BASE-FX Activity
1: No 100BASE-FX activity present.
Blink or pulse-stretch = 100BASE-FX activity present.
20
Force LED Off
1: De-asserts the LED.
21
Force LED On
0: Asserts the LED. LED pulsing is disabled in this mode.
22
Fast Link Fail
1: Enable fast link fail on the LED pin
0: Disable
LED Behavior
Several LED behaviors can be programmed into the VSC8562-11. Use the settings in register 30 and
19E1 to program LED behavior, which includes the following.
3.15.3.1
LED Combine
Enables an LED to display the status for a combination of primary and secondary modes. This can be
enabled or disabled for each LED pin. For example, a copper link running in 1000BASE-T mode and
activity present can be displayed with one LED by configuring an LED pin to Link1000/Activity mode. The
LED asserts when linked to a 1000BASE-T partner and also blinks or performs pulse-stretch when
activity is either transmitted by the PHY or received by the Link Partner. When disabled, the combine
feature only provides status of the selected primary function. In this example, only Link1000 asserts the
LED, and the secondary mode, activity, does not display when the combine feature is disabled.
3.15.3.2
LED Blink or Pulse-Stretch
This behavior is used for activity and collision indication. This can be uniquely configured for each LED
pin. Activity and collision events can occur randomly and intermittently throughout the link-up period.
Blink is a 50% duty cycle oscillation of asserting and de-asserting an LED pin. Pulse-stretch guarantees
that an LED is asserted and de-asserted for a specific period of time when activity is either present or not
present. These rates can also be configured using a register setting.
3.15.3.3
Rate of LED Blink or Pulse-Stretch
This behavior controls the LED blink rate or pulse-stretch length when blink/pulse-stretch is enabled on
an LED pin. The blink rate, which alternates between a high and low voltage level at a 50% duty cycle,
can be set to 2.5 Hz, 5 Hz, 10 Hz, or 20 Hz. For pulse-stretch, the rate can be set to 50 ms, 100 ms,
200 ms, or 400 ms. The blink rate selection for PHY0 globally sets the rate used for all LED pins on all
PHY ports.
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Functional Descriptions
3.15.3.4
LED Pulsing Enable
To provide additional power savings, the LEDs (when asserted) can be pulsed at 5 kHz, 20% duty cycle.
3.15.3.5
LED Blink After Reset
The LEDs will blink for one second after power-up and after any time all resets have been de-asserted.
This can be disabled through register 19E1, bit 11 = 0.
3.15.3.6
Fiber LED Disable
This bit controls whether the LEDs indicate the fiber and copper status (default) or the copper status only.
3.15.3.7
Pulse Programmable Control
These bits add the ability to width and frequency of LED pulses. This feature facilitates power reduction
options.
3.15.3.8
Fast Link Failure
For more information about this feature, see Fast Link Failure Indication, page 66.
3.15.4
Basic Serial LED Mode
Optionally, the VSC8562-11 can be configured so that access to all its LED signals is available through
two pins. This option is enabled by setting LED0 on PHY0 to serial LED mode in register 29, bits 3:0 to
0xD. When serial LED mode is enabled, the LED0_0 pin becomes the serial data pin, and the LED1_0
pin becomes the serial clock pin. All other LED pins can still be configured normally. The serial LED
mode clocks the 48 LED status bits on the rising edge of the serial clock where bits 25:48 are ignored.
The LED behavior settings can also be used in serial LED mode. The controls are used on a per-PHY
basis, where the LED combine and LED blink or pulse-stretch setting of LED0_n for each PHY is used to
control the behavior of each bit of the serial LED stream for each corresponding PHY. To configure LED
behavior, set device register 30.
The following table shows the 48-bit serial output bitstream of each LED signal where bits 25:48 are
ignored. The individual signals can be clocked in the following order.
Table 31 •
LED Serial Bitstream Order
Output
3.15.5
PHY0
PHY1
Link/activity
1
13
Link1000/activity
2
14
Link100/activity
3
15
Link10/activity
4
16
Fiber link/activity
5
17
Duplex/collision
6
18
Collision
7
19
Activity
8
20
Fiber activity
9
21
Tx activity
10
22
Rx activity
11
23
Autonegotiation fault
12
24
Enhanced Serial LED Mode
VSC8562-11 can be configured to output up to four LED signals per port on a serial stream that can be
de-serialized externally to drive LEDs on the system board. In enhanced serial LED mode, the port 0 and
port 1 LED output pins serve the following functions:
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Functional Descriptions
•
•
•
•
LED0_0/LED0_1: LED_DATA
LED1_0/LED1_1: LED_CLK
LED2_0/LED2_1: LED_LD
LED3_0/LED3_1: LED_PULSE
The serial LED_DATA is shifted out on the falling edge of LED_CLK and is latched in the external
serial-to-parallel converter on the rising edge of LED_CLK. The falling edge of LED_LD signal can be
used to shift the data from the shift register in the converter to the parallel output drive register. When a
separate parallel output drive register is not used in the external serial-to-parallel converter, the LEDs will
blink at a high frequency as the data bits are being shifted through, which may be undesirable. LED pin
functionality is controlled by setting register 25G, bits 7:1.
The LED_PULSE signal provides a 5 kHz pulse stream whose duty cycle can be modulated to turn on/off
LEDs at a high rate. This signal can be tied to the output enable signal of the serial-to-parallel converter
to provide the LED dimming functionality to save energy. The LED_PULSE duty cycle is controlled by
setting register 25G, bits 15:8.
3.15.6
LED Port Swapping
For additional hardware configurations, the VSC8562-11 can have its LED port order swapped. This is a
useful feature to help simplify PCB layout design. Register 25G bit 0 controls the LED port swapping
mode. LED port swapping only applies to the direct-drive LEDs and not to any serial LED output modes.
3.16
Fast Link Failure Indication
To aid Synchronous Ethernet applications, the VSC8562-11 can indicate the onset of a link failure in less
than 1 ms (worst-case
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