a
Dual, 12-Bit, 40 MSPS MCM A/D Converter
with Analog Input Signal Conditioning
AD10242
The AD10242 operates with ± 5.0 V for the analog signal conditioning with a separate 5.0 V supply for the analog-to-digital
conversion. Each channel is completely independent, allowing
operation with independent encode or analog inputs. The AD10242
also offers the user a choice of analog input signal ranges to minimize additional signal conditioning required for multiple functions
within a single system. The heart of the AD10242 is the AD9042,
which is designed specifically for applications requiring wide
dynamic range.
FEATURES
2 Matched ADCs with Input Signal Conditioning
Selectable Bipolar Input Voltage Range
(ⴞ0.5 V, ⴞ1.0 V, ⴞ2.0 V)
Full MIL-STD-883B Compliant
80 dB Spurious-Free Dynamic Range
Trimmed Channel-Channel Matching
APPLICATIONS
Radar Processing
Communications Receivers
FLIR Processing
Secure Communications
Any I/Q Signal Processing Application
The AD10242 is manufactured on Analog Devices’
MIL-PRF-38534 MCM line and is completely qualified. Units
are packaged in a custom, cofired, ceramic 68-lead gull wing
package and specified for operation from –55°C to +125°C.
Contact the factory for additional custom options including those
that allow the user to ac couple the ADC directly, bypassing the
front end amplifier section. Also see the AD9042 data sheet for
additional details on ADC performance.
GENERAL DESCRIPTION
The AD10242 is a complete dual signal chain solution including
on-board amplifiers, references, ADCs, and output buffering
providing unsurpassed total system performance. Each channel is
laser trimmed for gain and offset matching and provides channelto-channel crosstalk performance better than 80 dB. The AD10242
utilizes two each of the AD9632, OP279, and AD9042 in a custom MCM to gain space, performance, and cost advantages over
solutions previously available.
PRODUCT HIGHLIGHTS
1. Guaranteed sample rate of 40 MSPS.
2. Dynamic performance specified over entire Nyquist band;
spurious signals @ 80 dBc for –1 dBFS input signals.
3. Low power dissipation: 4 clock cycles. Output recovers in band in specified time with Encode = 40 MSPS. No foldover guaranteed.
13
Outputs are sourcing 10 µA.
14
Outputs are sinking 10 µA.
All specifications guaranteed within 100 ms of initial power-up regardless of sequencing.
Specifications subject to change without notice.
REV. D
–3–
AD10242
ABSOLUTE MAXIMUM RATINGS 1
Parameter
ELECTRICAL
VCC Voltage
VEE Voltage
Analog Input Voltage
Analog Input Current
Digital Input Voltage (ENCODE)
ENCODE, ENCODE Differential Voltage
Digital Output Current
Table I. Output Coding
Min
Max
Unit
0
–7
VEE
–10
0
7
0
VCC
+10
VCC
4
+40
V
V
V
mA
V
V
mA
+125
175
300
+150
°C
°C
°C
°C
–40
MSB
0111111111111
0000000000001
0000000000000
1111111111111
1000000000000
Base 10
Input
2047
+1
0
–1, 4095
–2047, 2048
+FS
0.0 V
–FS
EXPLANATION OF TEST LEVELS
Test Level
2
ENVIRONMENTAL
Operating Temperature (Case)
Maximum Junction Temperature
Lead Temperature (Soldering, 10 sec)
Storage Temperature Range (Ambient)
LSB
–55
–65
I
– 100% Production Tested.
II – 100% production tested at 25°C, and sample tested at
specified temperatures. AC testing done on sample basis.
III – Sample Tested Only.
NOTES
1
Absolute maximum ratings are limiting values to be applied individually, and beyond
which the serviceability of the circuit may be impaired. Functional operability is not
necessarily implied. Exposure to absolute maximum rating conditions for an
extended period of time may affect device reliability.
2
Typical thermal impedances for ES-68-1 package: θJC = 11°C/W; θJA = 30°C/W.
IV – Parameter is guaranteed by design and characterization
testing.
V – Parameter is a typical value only.
VI – All devices are 100% production tested at 25°C; sample
tested at temperature extremes.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD10242 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. D
AD10242
5
4
3
2
GNDB
GNDA
UCOMA
UNEGA
GNDA
SHIELD
GNDB
AVEE
6
AINB2
AINB1
AINA1
7
8
GNDB
AINB3
AINA2
9
AVCC
GNDA
AINA3
PIN CONFIGURATION
68-Lead Ceramic Leaded Chip Carrier
1 68 67 66 65 64 63 62 61
GNDA 10
PIN 1
IDENTIFIER
GNDA 11
UPOSA 12
60
GNDB
GNDB
GNDB
57 UPOSB
56 UNEGB
59
58
AVEE 13
AVCC 14
NC 15
55
UCOMB
NC 16
54
GNDB
AD10242
53
GNDB
TOP VIEW
(Not to Scale)
52
ENCODEB
ENCODEB
(LSB) D0A 17
D1A 18
D2A 19
51
D3A 20
50
D4A 21
49
D5A 22
48
D6A 23
47
D7A 24
46
D8A 25
45
D8B
D7B
GNDA 26
44
GNDB
DVCC
D11B (MSB)
D10B
D9B
D6B
GNDB
D5B
D3B
D4B
D1B
D2B
(LSB) D0B
(MSB) D11A
NC
NC
D10A
GNDA
NC = NO CONNECT
ENCODEA
ENCODEA
DVCC
D9A
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Function
1
2, 5, 9–11, 26–27
3
4
6
7
8
12
13
14
15, 16, 34, 35
17–25, 31–33
28
29
30, 50
36–42, 45–49
43–44, 53–54,
58–61, 65, 68
51
52
55
56
57
62
63
64
66
67
SHIELD
GNDA
UNEGA
UCOMA
AINA1
AINA2
AINA3
UPOSA
AVEE
AVCC
NC
D0A–D11A
ENCODEA
ENCODEA
DVCC
D0B–D11B
GNDB
Internal Ground Shield between Channels.
A Channel Ground. A and B grounds should be connected as close to the device as possible.
Unipolar Negative.
Unipolar Common.
Analog Input for A Side ADC (Nominally ± 0.5 V).
Analog Input for A Side ADC (Nominally ± 1.0 V).
Analog Input for A Side ADC (Nominally ± 2.0 V).
Unipolar Positive.
Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V).
Analog Positive Supply Voltage (Nominally 5.0 V).
No Connect.
Digital Outputs for ADC A. (D0 LSB.)
ENCODE is the complement of ENCODE.
Data conversion is initiated on the rising edge of the ENCODE input.
Digital Positive Supply Voltage (Nominally 5.0 V).
Digital Outputs for ADC B. (D0 LSB.)
B Channel Ground. A and B grounds should be connected as close to the device
as possible.
Data conversion is initiated on the rising edge of the ENCODE input.
ENCODE is the complement of ENCODE.
Unipolar Common.
Unipolar Negative.
Unipolar Positive.
Analog Input for B Side ADC (Nominally ± 0.5 V).
Analog Input for B Side ADC (Nominally ± 1.0 V).
Analog Input for B Side ADC (Nominally ± 2.0 V).
Analog Positive Supply Voltage (Nominally 5.0 V).
Analog Negative Supply Voltage (Nominally –5.0 V or –5.2 V).
REV. D
ENCODEB
ENCODEB
UCOMB
UNEGB
UPOSB
AINB1
AINB2
AINB3
AVCC
AVEE
–5–
AD10242
Overvoltage Recovery Time
DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The amount of time required for the converter to recover to
0.02% accuracy after an analog input signal of the specified
percentage of full scale is reduced to midscale.
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in power
supply voltage.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Signal-to-Noise and Distortion (SINAD)
The sample-to-sample variation in aperture delay.
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Differential Nonlinearity
Signal-to-Noise Ratio (SNR, without Harmonics)
The deviation of any code from an ideal 1 LSB step.
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Aperture Uncertainty (Jitter)
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic “1” state to achieve rated
performance; pulsewidth low is the minimum time that the
ENCODE pulse should be left in low state. At a given clock
rate, these specifications define an acceptable encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude to the rms value of the
worst harmonic component.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious component may or may not be a harmonic. SFDR may be reported in
dBc (i.e., degrades as signal levels are lowered) or in dBFS
(always related back to converter full scale).
Transient Response
The time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the
analog input.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line” determined by a least square curve fit.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms value of
the worst third order intermodulation product; reported in dBc.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
Two-Tone SFDR
The ratio of the rms value of either input tone to the rms value of
the peak spurious component. The peak spurious component
may or may not be an IMD product. Two-tone SFDR may be
reported in dBc (i.e., degrades as signal levels are lowered) or
in dBFS (always related back to converter full scale).
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between the 50% point of the rising edge of the ENCODE
command and the time when all output data bits are within valid
logic levels.
–6–
REV. D
AD10242
N+1
N
N+2
N+3
N+4
N+5
ENC
TTL CLOCK
f 10MHz
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
ENC
AIN
AIN3
tA = 1.0ns TYP
1/2
AD10242
SHOWN
AIN2
ENCODE
AIN1
tOD = 12ns TYP
DIGITAL
OUTPUTS
N–2
N–1
N
N+1
N+2
ALL 5V SUPPLY PINS BYPASSED
TO GND WITH A 0.1F CAPACITOR
Figure 2. Equivalent Burn-In Circuit
Figure 1. Timing Diagram
EQUIVALENT CIRCUITS
DVCC
AIN3
AIN2
R4
200⍀
CURRENT
MIRROR
R3
100⍀
AIN1
R2
21⍀
TO AD9632
R1
79⍀
DVCC
VREF
Figure 3. Analog Input Stage
D0–D11
AVCC
AVCC
R1
17k⍀
R1
17k⍀
AVCC
CURRENT
MIRROR
ENCODE
ENCODE
R2
8k⍀
TIMING
CIRCUITS
R2
8k⍀
Figure 5. Digital Output Stage
Figure 4. Encode Inputs
REV. D
–7–
AD10242–Typical Performance Characteristics
0
ENCODE = 40MSPS
AIN = 4.85MHz
AIN = –1dBFS
SNR = 66.4dB
SFDR = 72.8dBc
–10
–20
POWER RELATIVE TO FULL SCALE – dB
POWER RELATIVE TO FULL SCALE – dB
0
–30
–40
–50
–60
–70
–80
–90
–100
2
4
6
8
10
12
14
FREQUENCY – MHz
16
18
AIN2 = 10.1MHz
AIN2 = –7dBFS
SFDR = 76.0dBc
–30
–40
–50
–60
–70
–80
–90
0
20
TPC 1. Single Tone @ 4.85 MHz
2
4
6
0
–20
POWER RELATIVE TO FULL SCALE – dB
ENCODE = 40MSPS
AIN = 9.9MHz
AIN = –1dBFS
SNR = 66.0dB
SFDR = 65.7dBc
–10
–30
–40
–50
–60
–70
–80
–90
2
4
6
8
10
12
14
FREQUENCY – MHz
16
18
–20
–30
–50
–60
–70
–80
–90
0
2
4
6
8
10
12
14
FREQUENCY – MHz
16
18
20
76
ENCODE = 40MSPS
AIN = 19.5MHz
AIN = –1dBFS
SNR = 64.3dB
SFDR = 63.3dBc
ENCODE = 40MSPS
AIN = –1dBFS
74
WORST-CASE HARMONIC – dB
–30
20
TPC 5. Two-Tone FFT @ 19.5 MHz/19.7 MHz
0
–20
18
–40
20
TPC 2. Single Tone @ 9.9 MHz
–10
16
ENCODE = 40MSPS
AIN1 = 19.5MHz
AIN1 = –7dBFS
AIN2 = 19.7MHz
AIN2 = –7dBFS
SFDR = 70.6dBc
–10
–100
–100
0
8
10
12
14
FREQUENCY – MHz
TPC 4. Two-Tone FFT @ 9.8 MHz/10.1 MHz
0
POWER RELATIVE TO FULL SCALE – dB
–20
–100
0
POWER RELATIVE TO FULL SCALE – dB
ENCODE = 40MSPS
AIN1 = 9.8MHz
AIN1 = –7dBFS
–10
–40
–50
–60
–70
–80
72
70
T = +125 C
68
T = +25 C
66
T = –55 C
64
62
60
–90
–100
0
2
4
6
8
10
12
14
FREQUENCY – MHz
16
18
58
20
5
10
ANALOG INPUT FREQUENCY – MHz
20
TPC 6. Harmonics vs. AIN
TPC 3. Single Tone @ 19.5 MHz
–8–
REV. D
AD10242
67.0
–90
IN A1
66.5
IN B1
–80
T = –55 C
66.0
–70
65.5
IN B3
ISOLATION – dB
T = +25 C
SNR – dB
65.0
64.5
T = +125 C
64.0
63.5
ENCODE = 40MSPS
AIN = –1dBFS
63.0
–60
–50
–40
–30
–10
62.0
0
10
61.5
10
ANALOG INPUT FREQUENCY – MHz
5
20
68
WORST-CASE SPURIOUS – dBc, dBFS
AIN = 9.9MHz
AIN = –1dBFS
SNR, WORST SPUR – dB, dBc
20
25
30
35
ANALOG INPUT FREQUENCY – MHz
40
90
70
SFDR
66
SNR
64
62
60
5
10
15
20
25
30
35
SAMPLE RATE – MSPS
40
45
50
SFDR (dBFS)
70
60
50
SFDR (dBc)
40
SFDR = 75dB
30
20
ENCODE = 40MSPS
AIN = 9.98MHz
10
–60
–50
–40
–30
–20
–10
ANALOG INPUT POWER LEVEL – dBFS
0
TPC 11. Single Tone SFDR (AIN @ 9.98) vs. Power Level
TPC 8. SNR and Harmonics vs. Encode Rate
2.0
WORST-CASE SPURIOUS – dBc, dBFS
100
1.5
1.0
GAIN
0.5
0
–0.5
OFFSET
–1.0
–1.5
–2.0
–55
80
0
–70
58
ERROR – % FS
15
TPC 10. Isolation vs. Frequency
TPC 7. SNR vs. AIN
90
80
SFDR (dBFS)
70
60
SFDR (dBc)
50
40
SFDR = 75dB
30
20
ENCODE = 40MSPS
AIN = 19.9MHz
10
–35
–15
5
25
45
65
85
105
0
–70
125
TEMPERATURE – C
–60
–50
–40
–30
–20
–10
ANALOG INPUT POWER LEVEL – dBFS
0
TPC 12. Single Tone SFDR (AIN @ 19.9) vs. Power Level
TPC 9. Offset and Gain Error vs. Temperature
REV. D
ENCODE = 40MSPS
AIN = –1dBFS
–20
62.5
IN A3
–9–
AD10242
80
–0.5
70
0
ENCODE = 40MSPS
FUNDAMENTAL LEVELS – dBFS
SNR, WORST SPUR – dB, dBc
SNR (dB)
60
50
SFDR (dBFS)
40
30
20
ENCODE = 40MSPS
AIN = 1dBFS
10
0.5
1.0
1.5
2.0
2.5
3.0
0
5
10
20
29.2
34.5
52.5
ANALOG INPUT FREQUENCY – MHz
0
60.95
TPC 13. SNR/Harmonics to AIN > Nyquist MSPS
5
10
15
20
25
30
35
40
INPUT FREQUENCY – MHz
45
50
55
TPC 14. Gain Flatness vs. Input Frequency
THEORY OF OPERATION
Refer to the functional block diagram. The AD10242 employs
three monolithic ADI components per channel (AD9632, OP279,
and AD9042), along with multiple passive resistor networks
and decoupling capacitors to fully integrate a complete 12-bit
analog-to-digital converter.
APPLYING THE AD10242
Encoding the AD10242
The AD10242 is designed to interface with TTL and CMOS
logic families. The source used to drive the ENCODE pin(s)
must be clean and free from jitter. Sources with excessive jitter
will limit SNR and overall performance.
The input signal is first passed through a precision laser trimmed
resistor divider, allowing the user to externally select operation
with a full-scale signal of ± 0.5 V, ± 1.0 V, or ± 2.0 V by choosing
the proper input terminal for the application. The result of
the resistor divider is to apply a full-scale input of approximately
0.4 V to the noninverting input of the internal AD9632 amplifier.
The AD9632 provides the dc-coupled level shift circuit required
for operation with the AD9042 ADC. Configuring the amplifier
in a noninverting mode, the ac signal gain can be trimmed to
provide a constant input to the ADC centered around the internal reference voltage of the AD9042. This allows the converter
to be used in multiple system applications without the need for
external gain and level shift circuitry normally requiring trim.
The AD9632 was chosen for its superior ac performance and
input drive capabilities. These two specifications have limited
the ability of many amplifiers to drive high performance ADCs.
As new amplifiers are developed, pin compatible improvements are planned to incorporate the latest operational amplifier technology.
The OP279 provides the buffer and inversion of the internal
reference of the AD9042 in order to supply the summing node
of the AD9632 input amplifier. This dc voltage is then summed
with the input voltage and applied to the input of the AD9042
ADC. The reference voltage of the AD9042 is designed to track
internal offsets and drifts of the ADC and is used to ensure
matching over an extended temperature range of operation.
AD10242
TTL OR CMOS
SOURCE
ENCODE
ENCODE
0.01F
Figure 6. Single-Ended TTL/CMOS Encode
The AD10242 encode inputs are connected to a differential
input stage (see Figure 4). With no input connected to either
the ENCODE or ENCODE input, the voltage dividers bias the
inputs to 1.6 V. For TTL or CMOS usage, the encode source
should be connected to ENCODE (Pins 29 and/or 51). ENCODE
(Pins 28 and/or 52) should be decoupled using a low inductance
or microwave chip capacitor to ground. Devices such as AVX
05085C103MA15, a 0.01 µF capacitor, work well.
Performance Improvements
It is possible to improve the performance of the AD10242
slightly by taking advantage of the internal characteristics of the
amplifier and converter combination. By increasing the 5 V
supply slightly, the user may be able to gain up to a 5 dB improvement in SFDR over the entire frequency range of the converter.
It is not recommended to exceed 5.5 V on the analog supplies
since there are no performance benefits beyond that range and
care should be taken to avoid the absolute maximum ratings.
–10–
REV. D
AD10242
If a logic threshold other than the nominal 1.6 V is required,
the following equations show how to use an external resistor,
Rx, to raise or lower the trip point (see Figure 4, R1 = 17 kΩ,
R2 = 8 kΩ).
V1 =
5R2Rx
to lower logic threshold.
R1R2 + R1Rx + R2Rx
ENCODE
SOURCE
ENCODE
Vl
0.01F
If no TTL source is available, a clean sine wave may be substituted. In the case of the sine source, the matching network is
shown below. Since the matching transformer specified is a 1:1
impedance ratio, the load resistor R should be selected to match
the source impedance. The input impedance of the AD9042
is negligible in most cases.
ENCODE
R1
ENCODE
AD10242
R
ENCODE
Rx
R2
AD10242
Figure 10. Sine Source—Differential Encode
Figure 7. Lower Threshold for Encode
V1 =
T1–1T
SINE
SOURCE
5V
5R 2
to raise logic threshold.
R1Rx
R2 +
R1 + Rx
If a low jitter ECL clock is available, another option is to ac-couple
a differential ECL signal to the encode input pins, as shown
in Figure 11. The capacitors shown here should be chip capacitors but do not need to be of the low inductance variety.
0.1F
AVCC
ENCODE
ECL
GATE
AD10242
0.1F
ENCODE
Rx
ENCODE
SOURCE
ENCODE
Vl
0.01F
ENCODE
5V
Figure 11. Differential ECL for Encode
While the single-ended encode will work well for many applications, driving the encode differentially will provide increased
performance. Depending on circuit layout and system noise, a
1 dB to 3 dB improvement in SNR can be realized. It is recommended that the encode signal be ac-coupled into the ENCODE
and ENCODE pins.
The simplest option is shown below. The low jitter TTL signal
is coupled with a limiting resistor, typically 100 Ω, to the primary
side of an RF transformer (these transformers are inexpensive
and readily available; part number in Figures 9 and 10 is from
Mini-Circuits). The secondary side is connected to the ENCODE
and ENCODE pins of the converter. Since both encode inputs
are self-biased, no additional components are required.
100⍀
T1–1T
As a final alternative, the ECL gate may be replaced by an ECL
comparator. The input to the comparator could then be a logic
signal or a sine signal.
AD96687 (1/2)
0.1F
ENCODE
AD10242
0.1F
50⍀
ENCODE
510⍀
510⍀
–VS
Figure 12. ECL Comparator for Encode
Care should be taken not to overdrive the encode input pin when
ac-coupled. Although the input circuitry is electrically protected
from overvoltage or undervoltage conditions, improper circuit
operations may result from overdriving the encode input pin.
ENCODE
AD10242
ENCODE
Figure 9. TTL Source—Differential Encode
REV. D
510⍀
–VS
R2
AD10242
Figure 8. Raise Logic Threshold for Encode
TTL
510⍀
R1
–11–
AD10242
USING THE FLEXIBLE INPUT
The AD10242 has been designed with the user’s ease of operation in mind. Multiple input configurations have been included on
board to allow the user a choice of input signal levels and input
impedance. While the standard inputs are ± 0.5 V, ± 1.0 V, and
± 2.0 V, the user can select the input impedance of the AD10242
on any input by using the other inputs as alternate locations for
GND or an external resistor. The following chart summarizes the
impedance options available at each input location:
AIN1 = 100 Ω when AIN2 and AIN3 are open.
AIN1 = 75 Ω when AIN3 is shorted to GND.
AIN1 = 50 Ω when AIN2 is shorted to GND.
AIN2 = 200 Ω when AIN3 is open.
AIN2 = 100 Ω when AIN3 is shorted to GND.
AIN2 = 75 Ω when AIN2 to AIN3 has an external resistor of
AIN2 = 300 Ω, with AIN3 shorted to GND.
AIN2 = 50 Ω when AIN2 to AIN3 has an external resistor of AIN2
=
100 Ω, with AIN3 shorted to GND.
AIN3 = 400 Ω.
AIN3 = 100 Ω when AIN3 has an external resistor of 133 Ω to GND.
AIN3 = 75 Ω when AIN3 has an external resistor of 92 Ω to GND.
AIN3 = 50 Ω when AIN3 has an external resistor of 57 Ω to GND.
While the analog inputs of the AD10242 are designed for
dc- coupled bipolar inputs, the AD10242 has the ability to
use unipolar inputs in a user selectable mode through the addition of an external resistor. This allows for 1 V, 2 V, and 4 V
full-scale unipolar signals to be applied to the various inputs
(AIN1, AIN2, and AIN3, respectively). Placing a 2.43 kΩ resistor (typical, offset calibration required) between UPOS and
UCOM shifts the reference voltage setpoint to allow a unipolar
positive voltage to be applied at the inputs of the device. To calibrate offset, apply a midscale dc voltage to the converter while
adjusting the unipolar resistor for a midscale output transition.
A IN 1
A IN 2
A IN 3
UPOS
A IN 1
A IN 2
A IN 3
UNEG
AD10242
2.67k⍀
UCOM
Figure 14. Unipolar Negative
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in
performance.
It is important to design a layout that prevents noise from coupling to the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. The AD10242 does not distinguish between
analog and digital ground pins as the AD10242 should always
be treated like an analog component. All ground pins should be
connected together directly under the AD10242. The PCB
should have a ground plane covering all unused portions of the
component side of the board to provide a low impedance path
and manage the power and ground currents. The ground plane
should be removed from the area near the input pins to reduce
stray capacitance.
AD10242
LAYOUT INFORMATION
2.43k⍀
UCOM
Figure 13. Unipolar Positive
To operate with –1 V, –2 V, or –4 V full-scale unipolar signals,
place a 2.67 kΩ resistor (typical, offset calibration required)
between UNEG and UCOM. This again shifts the reference voltage setpoint to allow a unipolar negative voltage to be applied at
the inputs of the device. To calibrate offset, apply a midscale dc
voltage to the converter while adjusting the unipolar resistor for
a midscale output transition.
The schematic of the evaluation board (Figure 15) represents a
typical implementation of the AD10242. The pinout of the
AD10242 is very straightforward and facilitates ease of use
and the implementation of high frequency/high resolution
design practices. It is recommended that high quality ceramic
chip capacitors be used to decouple each supply pin to ground
directly at the device. All capacitors except the one placed on
ENCODE can be standard high quality ceramic chip capacitors.
The capacitor used on the ENCODE pin must be a low inductance chip capacitor as referenced previously.
–12–
REV. D
AD10242
5VA
C1
0.1F
U1
K1115
SMA SMA
J1
JA
14
VCC
VEE
U5
AD9696KN
8
2
R9
470⍀
3
R10
470⍀
U2
K1115
1
7
5VA
C14
0.1F
5VA
51⍀
H2DM
E5
J17
1
2
T1
T1–1T
4
3
SMA
J11
PULSE B
IN
PULSE A
OUT
6
SMA
J13
SMA
J12
1
VEE
U5
AD9696KN
8
2
51⍀
H2DM
J18
1
2
E5
3
C5
0.1F
5
6
GND
R8
49.9⍀
5
PULSE B
OUT
B JACKS
SMA
J14
E1
+5VA
+5VA
–5.2V
E4
E3
GND
GND
VLOW
VLOW
–5.2V VHIGH
VHIGH
E2
VLOW
R5
470⍀
R6
470⍀
R4
470⍀
VHIGH
U4
C22
0.1F
U3
C21
0.1F
U3
C19
0.1F
U4
C20
0.1µF
+5V
U4
C17
0.1F
U3
C18
0.1F
DUT
C9
0.1F
C23
10F
U5
C12
0.1F
U6
C3
0.1F
DUT
C8
0.1F
U3
C15
0.1F
U4
C16
0.1F
C24
10F
DUT
C10
0.1F
U5
C13
0.1F
U6
C4
0.1F
DUT
C11
0.1F
DUT
C7
0.1F
C25
10F
DUT
C6
0.1F
D3A
D2A
D1A
(LSB) D0A
GND
GND
GND
GND
GND
+5VD
SMA
J2
SMA
J3
AINA2
SMA
J5
AINA3
SMA
J6
AINB1
SMA
J7
AINB2
AINB3
GND
A IN A3
A IN A2
A IN A1
GND
TP5
TP6
GND
GND
GND
–5.2V
+5VA
GND
A IN B3
A IN B2
A IN B1
GND
AINA1
SMA
J4
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
5
4
3
2
1 68 67 66 65 64 63 62 61
GNDA
GNDA
UNIPOSA
–5.2VAA
+5VAA
NCA
NCA
D0A (LSBA)
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
GNDA
DUT
AD10242
GNDB
GNDB
GNDB
UNIPOSB
UNINEGB
UNICOMB
GNDB
GNDB
ENCB
ENCB
+5VDB
(MSBB) D11B
D10B
D9B
D8B
D7B
GNDB
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Figure 15. Evaluation Board Schematic
REV. D
GNDB
6
ENCA
ENCA
+5VDA
D9A
D10A
D11A (MSBA)
NCB
NCB
D0B (LSBB)
D1B
D2B
D3B
D4B
D5B
D6B
GNDB
11
7
GND
ENCA
ENCA
+5VD
D9A
D10A
D11A
GND
GND
D0B
D1B
D2B
D3B
D4B
D5B
D6B
GND
4) POWER (5VD) FOR DIGITAL OUTPUTS OF THE
AD10242 IS SUPPLIED VIA PIN 1 OF EITHER J9 OR J10
(THE DIGITAL INTERFACES). TO POWER THE EVAL.
BOARD WITH ONE 5V SUPPLY, JUMPER A WIRE
FROM E1 TO E4 (CONNECTED AT FACTORY).
10
GNDA
GND
GND
TP1
–5.2V
2) ABOVE UNIPOLAR RESISTOR VALUES ARE
+5VA
NOMINAL AND MAY HAVE TO BE ADJUSTED
GND
DEPENDING ON OFFSET OF DUT.
GND
D0A
3) ENCODE SOURCES
D1A
A) FOR NORMAL OPERATION, A 40MHz TTL CLOCK
OSCILLATOR IS INSTALLED IN U1 AND U2. THERE D2A
D3A
IS A 51⍀ RESISTOR BETWEEN J15 AND J16.
J17 AND J18 ARE OPEN.
D4A
B) FOR EXTERNAL SQUARE WAVE ENCODE, INPUT
D5A
SIGNAL AT J1 AND J8, REMOVE U1, U2, JUMPERS D6A
J15 AND J16. CONNECT JUMPERS J17 AND J18.
D7A
C) FOR EXTERNAL SINE WAVE ENCODE, INPUT
D8A
SIGNAL AT J1 AND J8, REMOVE U1, U2, R9, R11,
GND
JUMPERS J15 AND J16.
CONNECT JUMPERS J17 AND J18.
8
GNDA
A IN A3
A IN A2
A IN A1
GNDA
UNICOMA
UNINEGA
GNDA
SHIELD
GNDB
–5.2VAB
+5VAB
GNDB
A IN B3
A IN B2
A IN B1
9
NOTES;
1) UNIPOLAR OPERATION
A SIDE + CONNECT 2.43k⍀ RES. FROM TP1 TO TP5.
A SIDE – CONNECT 2.67k⍀ RES. FROM TP5 TO TP6.
B SIDE + CONNECT 2.43k⍀ RES. FROM TP2 TO TP4.
B SIDE – CONNECT 2.67k⍀ RES. FROM TP4 TO TP3.
5VD
(MSB) D11A
D10A
D9A
D8A
D7A
D6A
D5A
D4A
BUFLATA
–5.2V
VLOW
6
1:1
5
VLOW
1
ENCA
6
T2
T1–1T
4
3
–13–
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
GND
GND
GND
TP2
TP3
TP4
GND
GND
ENCB
ENCB
+5VD
D11B
D10B
D9B
D8B
D7B
GND
ENCBB
2
R2
100⍀
2
R7
49.9⍀
BUFLATB
7
ENCAB
U4
AD8036Q VHIGH
3
8
2
R3
470⍀
H2DM
J16
2
1
7
R12
470⍀
SMA
JD
B SECTION
1:1
U3
AD8036Q VHIGH
3
8
SMA
JB
8
2
R1
100⍀
A SECTION
OUT
BUFLATA
7
5
SMA
J8
14
VCC
R11
470⍀
GND
PULSE A
IN
C2
0.1F
H2DM
J15
2
8
OUT
5VA
SMA
JC
+5VD
(MSB) D11B
D10B
D9B
D8B
D7B
D6B
D5B
D4B
BUFLATB
D3B
D2B
D1B
(LSB) D0B
GND
GND
GND
GND
GND
ENCB
H40DM
J9
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
1
13
14
15
16
17
18
19
20
H40DM
J10
40
39
38
37
36
35
34
33
32
31
30
29
28
13
27
14
15
26
16
25
17
24
18
23
19
22
20
21
1
2
3
4
5
6
7
8
9
10
11
12
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
TEST POINTS
TP1
TP1
TP6
TP6
TP2
TP2
TP7
ENCAB
TP3
TP3
TP8
ENCA
TP4
TP4
TP9
TP5
TP5 TP10
ENCBB
ENCB
AD10242
Care should be taken when placing the digital output runs.
Because the digital outputs have such a high slew rate, the
capacitive loading on the digital outputs should be minimized.
Circuit traces for the digital outputs should be kept short and
connect directly to the receiving gate. Internal circuitry buffers
the outputs of the AD9042 ADC through a resistor network to
eliminate the need to externally isolate the device from the
receiving gate.
EVALUATION BOARD
The AD10242 evaluation board (see Figure 16) is designed to
provide optimal performance for evaluation of the AD10242
analog-to-digital converter. The board encompasses everything
needed to ensure the highest level of performance for evaluating
the AD10242.
Power to the analog supply pins is connected via banana jacks.
The analog supply powers the crystal oscillator, the associated
components and amplifiers, and the analog section of the
AD10242. The digital outputs of the AD10242 are powered via
Pin 1 of either J9 or J10 found on the digital interface connector. To power the evaluation board with one 5 V supply, a
jumper wire is required from test point E1 to E4. Contact the
factory if additional layout or applications assistance is required.
Figure 16. Evaluation Board Mechanical Layout
–14–
REV. D
AD10242
OUTLINE DIMENSIONS
0.010 (0.25)
0.008 (0.20)
0.007 (0.18)
0.235 (5.97)
MAX
0.960 (24.38)
0.950 (24.13) SQ
0.940 (23.88)
9
61
10
60
PIN 1
TOE DOWN
ANGLE
0–8 DEGREES
1.070
(27.18)
MIN
TOP VIEW
0.800
(20.32)
BSC
1.190 (30.23)
1.180 (29.97) SQ
1.170 (29.72)
(PINS DOWN)
0.010 (0.254)
26
30°
44
43
27
0.060 (1.52)
0.050 (1.27)
0.040 (1.02)
0.020 (0.508)
DETAIL A
ROTATED 90° CCW
DETAIL A
0.175 (4.45)
MAX
0.055 (1.40)
0.050 (1.27)
0.045 (1.14)
0.020 (0.508)
0.017 (0.432)
0.014 (0.356)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
012908-A
0.050 (1.27)
Figure 17. 68-Lead Ceramic Leaded Chip Carrier [CLCC]
(ES-68-1)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model
AD10242BZ
AD10242TZ
AD10242TZ/883B
5962-9581501HXA
Temperature Range
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–55°C to +125°C
Package Description
68-Lead Ceramic Leaded Chip Carrier [CLCC]
68-Lead Ceramic Leaded Chip Carrier [CLCC]
68-Lead Ceramic Leaded Chip Carrier [CLCC]
68-Lead Ceramic Leaded Chip Carrier [CLCC]
REVISION HISTORY
6/15—Rev. C to Rev. D
Change to Note 2 ............................................................................... 4
Updated Outline Dimensions ........................................................15
Changes to Ordering Guide ...........................................................15
1/03—Rev. B to Rev. C
Changes to Functional Block Diagram .......................................... 1
Changes to Table I . ........................................................................... 4
Changes to Pin Function Descriptions........................................... 5
Change to Encoding the AD10242 Section .................................10
Updated Outline Dimensions ........................................................15
6/01—Rev. A to Rev. B
AD9631 References Changed to AD9632 ....................... Universal
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00665-0-6/15(D)
Rev. D | Page 15
Package Option
ES-68-1
ES-68-1
ES-68-1
ES-68-1
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