2 ADC/8 DAC with PLL,
192 kHz, 24-Bit Codec
AD1928
GENERAL DESCRIPTION
PLL-generated or direct master clock
Low EMI design
108 dB DAC/107 dB ADC dynamic range and SNR
−94 dB THD + N
3.3 V single supply
Tolerance for 5 V logic inputs
Supports 24 bits and 8 kHz to 192 kHz sample rates
Differential ADC input
Single-ended DAC output
Log volume control with autoramp function
SPI® controllable for flexibility
Software-controllable clickless mute
Software power-down
Right-justified, left-justified, I2S-justified, and TDM modes
Master and slave modes up to 16-channel input/output
48-lead LQFP
The AD1928 is a high performance, single-chip codec that
provides two analog-to-digital converters (ADCs) with differential input and eight digital-to-analog converters (DACs) with
single-ended output using the Analog Devices, Inc., patented
multibit sigma-delta (Σ-Δ) architecture. An SPI port is included,
allowing a microcontroller to adjust volume and many other
parameters. The AD1928 operates from 3.3 V digital and analog
supplies. The AD1928 is available in a 48-lead (single-ended
output) LQFP package. Other members of this family include a
differential DAC output version.
TE
FEATURES
LE
The AD1928 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the master clock from the
LR clock or from an external crystal, the AD1928 eliminates the
need for a separate high frequency master clock and can be
used with a suppressed bit clock. The digital-to-analog and
analog-to-digital converters are designed using the latest
Analog Devices continuous time architectures to further
minimize EMI. By using 3.3 V supplies, power consumption is
minimized, further reducing emissions.
APPLICATIONS
B
SO
Automotive audio systems
Home theater systems
Set-top boxes
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT/OUTPUT
AD1928
O
SERIAL DATA PORT
ANALOG
AUDIO
INPUTS
ADC
ADC
QUAD
DEC
FILTER
48kHz/
96kHz/
192kHz
SDATA
OUT
DAC
DAC
SDATA
IN
CLOCKS
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
DAC
ANALOG
AUDIO
OUTPUTS
DAC
DAC
DAC
CONTROL DATA
INPUT/OUTPUT
06623-001
PRECISION
VOLTAGE
REFERENCE
CONTROL PORT
SPI
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007-2011 Analog Devices, Inc. All rights reserved.
AD1928
TABLE OF CONTENTS
Analog-to-Digital Converters (ADCs).................................... 13
Applications....................................................................................... 1
Digital-to-Analog Converters (DACs) .................................... 13
General Description ......................................................................... 1
Clock Signals............................................................................... 13
Functional Block Diagram .............................................................. 1
Reset and Power-Down ............................................................. 14
Revision History ............................................................................... 2
Serial Control Port ..................................................................... 14
Specifications..................................................................................... 3
Power Supply and Voltage Reference....................................... 15
Test Conditions............................................................................. 3
Serial Data Ports—Data Format............................................... 15
Analog Performance Specifications ........................................... 3
Time-Division Multiplexed (TDM) Modes............................ 15
Crystal Oscillator Specifications................................................. 5
Daisy-Chain Mode ..................................................................... 19
Digital Input/Output Specifications........................................... 5
Control Registers ............................................................................ 24
Power Supply Specifications........................................................ 5
Definitions................................................................................... 24
Digital Filters................................................................................. 6
PLL and Clock Control Registers............................................. 24
Timing Specifications .................................................................. 6
DAC Control Registers .............................................................. 25
Absolute Maximum Ratings............................................................ 8
ADC Control Registers.............................................................. 27
LE
TE
Features .............................................................................................. 1
Thermal Resistance ...................................................................... 8
Additional Modes....................................................................... 29
ESD Caution.................................................................................. 8
Application Circuits ....................................................................... 30
Pin Configuration and Function Descriptions............................. 9
Outline Dimensions ....................................................................... 31
Typical Performance Characteristics ........................................... 11
Ordering Guide .......................................................................... 31
B
SO
Theory of Operation ...................................................................... 13
REVISION HISTORY
7/11—Rev. A to Rev. B
Deleted References to I2C ............................................. Throughout
Changes to Table 10, DSDATAx/ASDATAx Pin Descriptions... 9
O
2/11—Rev. 0 to Rev. A
Change to Table 2, Introductory Text ............................................ 4
Change to Table 4, Introductory Text ............................................ 5
Change to Table 7, Introductory Text ............................................ 6
Changes to Figure 29, Figure 31, and Figure 32 ......................... 30
Changes to Ordering Guide .......................................................... 31
4/07—Revision 0: Initial Version
Rev. B | Page 2 of 32
AD1928
SPECIFICATIONS
TEST CONDITIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
1
3.3 V
As specified in Table 1 and Table 2
12.288 MHz (48 kHz fS, 256 × fS mode)
48 kHz
20 Hz to 20 kHz
24 bits
20 pF
±1 mA or 1.5 kΩ to ½ DVDD supply
2.0 V
0.8 V
TE
Supply voltages (AVDD, DVDD)
Temperature range 1
Master clock
Input sample rate
Measurement bandwidth
Word width
Load capacitance (digital output)
Load current (digital output)
High level input voltage
Low level input voltage
Functionally guaranteed at −40°C to +125°C case temperature.
LE
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at an ambient temperature of 25°C.
Table 1.
Conditions
Min
All ADCs
20 Hz to 20 kHz, −60 dB input
B
SO
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Input Voltage (Differential)
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
Interchannel Isolation
CMRR
O
Input Resistance
Input Capacitance
Input Common-Mode Bias Voltage
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
With A-Weighted Filter (Average)
Total Harmonic Distortion + Noise
Single-Ended Version
98
100
−1 dBFS
−10
−0.25
−10
100 mV rms, 1 kHz
100 mV rms, 20 kHz
Typ
Max
Unit
24
Bits
102
105
−96
1.9
dB
dB
dB
V rms
%
dB
mV
ppm/°C
dB
dB
dB
kΩ
pF
V
0
100
−110
55
55
14
10
1.5
−87
+10
+0.25
+10
20 Hz to 20 kHz, −60 dB input
98
100
0 dBFS
Two channels running
Eight channels running
Full-Scale Output Voltage
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
−92
−86
0.88 (2.48)
−10
−0.2
−25
−30
Rev. B | Page 3 of 32
104
106
108
−4
dB
dB
dB
−75
+10
+0.2
+25
+30
dB
dB
V rms (V p-p)
%
dB
mV
ppm/°C
AD1928
Conditions
Min
±0.6
FILTR pin
FILTR pin
CM pin
1.32
Table 2.
Conditions
Min
All ADCs
20 Hz to 20 kHz, −60 dB input
−1 dBFS
1.50
1.50
1.50
Typ
1.68
Unit
dB
Degrees
dB
dB
dB
Ω
V
V
V
−10
−0.25
−10
Max
Unit
24
Bits
102
105
−96
1.9
dB
dB
dB
V rms
%
dB
mV
LE
95
97
B
SO
O
Full-Scale Output Voltage
Gain Error
Interchannel Gain Mismatch
Offset Error
Gain Drift
REFERENCE
Internal Reference Voltage
External Reference Voltage
Common-Mode Reference Output
Max
100
Specifications measured at a case temperature of 125°C.
Parameter
ANALOG-TO-DIGITAL CONVERTERS
ADC Resolution
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Input Voltage (Differential)
Gain Error
Interchannel Gain Mismatch
Offset Error
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
With A-Weighted Filter (Average)
Total Harmonic Distortion + Noise
Single-Ended Version
Typ
100
0
0.375
95
TE
Parameter
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
Internal Reference Voltage
External Reference Voltage
Common-Mode Reference Output
0
−87
+10
+0.25
+10
20 Hz to 20 kHz, −60 dB input
98
100
0 dBFS
Two channels running
Eight channels running
FILTR pin
FILTR pin
CM pin
−92
−86
0.8775 (2.482)
−10
−0.2
−25
−30
1.32
Rev. B | Page 4 of 32
104
106
108
−4
1.50
1.50
1.50
dB
dB
dB
−70
+10
+0.2
+25
+30
1.68
dB
dB
V rms (V p-p)
%
dB
mV
ppm/°C
V
V
V
AD1928
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 3.
Parameter
Transconductance
Min
Typ
3.5
Max
Unit
mmhos
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TC < 125°C, DVDD = 3.3 V ± 10%.
Table 4.
Parameter
High Level Input Voltage (VIH)
Conditions/Comments
POWER SUPPLY SPECIFICATIONS
Parameter
SUPPLIES
Voltage
Digital Current
Normal Operation
0.4
5
Unit
V
V
V
μA
μA
V
V
pF
0.8
10
10
DVDD − 0.60
Min
Typ
Max
Unit
DVDD
AVDD
Master clock = 256 fS
fS = 48 kHz
fS = 96 kHz
fS = 192 kHz
fS = 48 kHz to 192 kHz
3.0
3.0
3.3
3.3
3.6
3.6
V
V
56
65
95
2.0
mA
mA
mA
mA
74
23
mA
mA
429
185
244
83
mW
mW
mW
mW
50
50
dB
dB
Master clock = 256 fS, 48 kHz
O
Power-Down
Analog Current
Normal Operation
Power-Down
DISSIPATION
Normal Operation
All Supplies
Digital Supply
Analog Supply
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
Max
Conditions/Comments
B
SO
Table 5.
IIH @ VIH = 2.4 V
IIL @ VIL = 0.8 V
IOH = 1 mA
IOL = 1 mA
LE
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Input Capacitance
Typ
TE
MCLKI/XI pin
Low Level Input Voltage (VIL)
Input Leakage
Min
2.0
2.2
1 kHz, 200 mV p-p
20 kHz, 200 mV p-p
Rev. B | Page 5 of 32
AD1928
DIGITAL FILTERS
Table 6.
Transition Band
Stop Band
Group Delay
Min
0.4375 fS
Typ
Max
21
±0.015
24
27
0.5 fS
0.5625 fS
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
48 kHz mode, typ @ 48 kHz
96 kHz mode, typ @ 96 kHz
192 kHz mode, typ @ 192 kHz
0.4535 fS
0.3646 fS
0.3646 fS
479
22
35
70
±0.01
±0.05
±0.1
0.5 fS
0.5 fS
0.5 fS
0.5465 fS
0.6354 fS
0.6354 fS
24
48
96
26
61
122
70
70
70
25/fS
11/fS
8/fS
Unit
kHz
dB
kHz
kHz
dB
μs
79
22.9844/fS
B
SO
Stop-Band Attenuation
Factor
TE
Pass-Band Ripple
Mode
All modes, typ @ 48 kHz
LE
Parameter
ADC DECIMATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Group Delay
DAC INTERPOLATION FILTER
Pass Band
521
115
42
kHz
kHz
kHz
dB
dB
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
μs
μs
μs
TIMING SPECIFICATIONS
−40°C < TC < 125°C, DVDD = 3.3 V ± 10%.
Table 7.
O
Parameter
INPUT MASTER CLOCK (MCLK) AND
RESET
tMH
Condition
Comments
Min
Max
Unit
MCLK duty cycle
DAC/ADC clock source = PLL clock @ 256 fS,
384 fS, 512 fS, and 768 fS
DAC/ADC clock source = direct MCLK @ 512 fS
(bypass on-chip PLL)
PLL mode, 256 fS reference
Direct 512 fS mode
40
60
%
40
60
%
6.9
13.8
27.6
MHz
MHz
ns
tMCLK
10
ms
60
%
fMCLK
MCLK frequency
tPDR
tPDRR
RST low
RST recovery
PLL
Lock Time
256 fS VCO Clock Output Duty Cycle
Reset to active output
MCLK and LR
clock input
MCLKO/XO pin
15
4096
40
Rev. B | Page 6 of 32
AD1928
CCLK high
CCLK low
CCLK frequency
CIN setup
CIN hold
CLATCH setup
CLATCH hold
CLATCH high
COUT enable
COUT delay
COUT hold
COUT tristate
ABCLK high
ABCLK low
ALRCLK setup
ALRCLK hold
ALRCLK skew
ASDATA delay
fCCLK = 1/tCCP, only tCCP shown in Figure 11
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK falling
Not shown in Figure 11
From CCLK falling
From CCLK falling
From CCLK falling, not shown in Figure 11
From CCLK falling
See Figure 24
Slave mode
Slave mode
To DBCLK rising, slave mode
From DBCLK rising, slave mode
From DBCLK falling, master mode
To DBCLK rising
From DBCLK rising
See Figure 25
Slave mode
Slave mode
To ABCLK rising, slave mode
From ABCLK rising, slave mode
From ABCLK falling, master mode
From ABCLK falling
To AUXBCLK rising
From AUXBCLK rising
From AUXBCLK falling
To AUXBCLK rising
From AUXBCLK rising
O
AAUXDATA setup
AAUXDATA hold
DAUXDATA delay
AUXBCLK high
AUXBCLK low
AUXLRCLK setup
AUXLRCLK hold
Min
Max
35
35
LE
DBCLK high
DBCLK low
DLRCLK setup
DLRCLK hold
DLRCLK skew
DSDATA setup
DSDATA hold
Comments
See Figure 11, except where otherwise noted
10
10
10
10
10
10
30
30
30
TE
Condition
B
SO
Parameter
SPI PORT
tCCH
tCCL
fCCLK
tCDS
tCDH
tCLS
tCLH
tCLHIGH
tCOE
tCOD
tCOH
tCOTS
DAC SERIAL PORT
tDBH
tDBL
tDLS
tDLH
tDLSKEW
tDDS
tDDH
ADC SERIAL PORT
tABH
tABL
tALS
tALH
tALSKEW
tABDD
AUXILIARY INTERFACE
tAXDS
tAXDH
tDXDD
tXBH
tXBL
tDLS
tDLH
Rev. B | Page 7 of 32
10
10
10
5
−8
10
5
10
10
10
5
−8
30
+8
+8
18
10
5
18
10
10
10
5
Unit
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AD1928
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
Parameter
Analog (AVDD)
Digital (DVDD)
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Case)
Storage Temperature Range
Rating
−0.3 V to +3.6 V
−0.3 V to +3.6 V
±20 mA
–0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
θJA represents thermal resistance, junction-to-ambient;
θJC represents the thermal resistance, junction-to-case. All
characteristics are for a 4-layer board.
Table 9. Thermal Resistance
Package Type
48-Lead LQFP
θJA
50.1
θJC
17
O
B
SO
LE
TE
ESD CAUTION
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 8 of 32
Unit
°C/W
AD1928
AVDD
LF
ADC1RN
ADC1RP
ADC1LN
ADC1LP
NC
NC
NC
NC
CM
AVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48
47
46
45
44
43
42
41
40
39
38
37
AGND
1
36
AGND
2
35
FILTR
3
34
AGND
AGND
4
33
AVDD
AVDD
5
AD1928
32
AGND
OL3
6
31
OR2
OR3
7
TOP VIEW
(Not to Scale)
30
OL2
OL4
8
29
OR1
OR4
9
28
OL1
27
CLATCH
26
CCLK
25
DGND
17
18
19
20
DVDD
DSDATA2
DSDATA1
DBCLK
DLRCLK
ASDATA1
ADCTDMOUT
21
22
23
24
06623-002
16
COUT
15
CIN
14
LE
NC = NO CONNECT
13
DSDATA3
DGND 12
ALRCLK
PD/RST 10
DSDATA4 11
ABCLK
SINGLE-ENDED
OUTPUT
TE
MCLKI/XI
MCLKO/XO
Figure 2. Pin Configuration, 48-Lead LQFP
Table 10. Pin Function Descriptions
Input/Output
I
I
O
I
I
O
O
O
O
I
I/O
Mnemonic
AGND
MCLKI/XI
MCLKO/XO
AGND
AVDD
OL3
OR3
OL4
OR4
PD/RST
DSDATA4
12
13
14
I
I
I/O
DGND
DVDD
DSDATA3
15
I/O
DSDATA2
16
17
18
19
20
21
22
23
24
I
I/O
I/O
I/O
O
I/O
I/O
I
I/O
DSDATA1
DBCLK
DLRCLK
ASDATA1
ADCTDMOUT
ABCLK
ALRCLK
CIN
COUT
Description
Analog Ground.
Master Clock Input/Crystal Oscillator Input.
Master Clock Output/Crystal Oscillator Output.
Analog Ground.
Analog Power Supply. Connect to analog 3.3 V supply.
DAC Left 3 Output.
DAC Right 3Output.
DAC Left 4 Output.
DAC Right 4 Output.
Power-Down Reset (Active Low).
DAC Serial Data Input 4. Data input to DAC4 data in/TDM DAC2 data out (dual-line
mode)/AUX DAC2 data out (to external DAC2).
Digital Ground.
Digital Power Supply. Connect to digital 3.3 V supply.
DAC Serial Data Input 3. Data input to DAC3 data in/TDM DAC2 data in (dual-line
mode)/AUX ADC2 data in (from external ADC2).
DAC Serial Data Input 2. Data input to DAC2 data in/TDM DAC data out/AUX ADC1 data in
(from external ADC1).
DAC Serial Data Input 1. Data input to DAC1 data in/TDM DAC data in/TDM data in.
Bit Clock for DACs.
LR Clock for DACs.
ADC Serial Data Output 1. Data output from ADC1/TDM ADC data out/TDM data out.
ADC TDM Data Output.
Bit Clock for ADCs.
LR Clock for ADCs.
Control Data Input (SPI).
Control Data Output (SPI).
O
B
SO
Pin No.
1
2
3
4
5
6
7
8
9
10
11
Rev. B | Page 9 of 32
AD1928
Description
Digital Ground.
Control Clock Input (SPI).
Latch Input for Control Data (SPI).
DAC Left 1 Output.
DAC Right 1 Output.
DAC Left 2 Output.
DAC Right 2 Output.
Analog Ground.
Analog Power Supply. Connect to analog 3.3 V supply.
Analog Ground.
Voltage Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.
Analog Ground.
Analog Power Supply. Connect to analog 3.3 V supply.
Common-Mode Reference Filter Capacitor Connection. Bypass with 47 μF||100 nF to AGND.
Must be tied to common mode, Pin 38; alternatively, ac-coupled to ground.
ADC Left 1 Positive Input.
ADC Left 1 Negative Input.
ADC Right 1 Positive Input.
ADC Right 1 Negative Input.
PLL Loop Filter. Return to AVDD.
Analog Power Supply. Connect to analog 3.3 V supply.
TE
Mnemonic
DGND
CCLK
CLATCH
OL1
OR1
OL2
OR2
AGND
AVDD
AGND
FILTR
AGND
AVDD
CM
Unused
ADC1LP
ADC1LN
ADC1RP
ADC1RN
LF
AVDD
LE
Input/Output
I
I
I
O
O
O
O
I
I
I
O
I
I
O
I
I
I
I
I
O
I
O
B
SO
Pin No.
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39 to 42
43
44
45
46
47
48
Rev. B | Page 10 of 32
AD1928
TYPICAL PERFORMANCE CHARACTERISTICS
0.10
0
0.08
0.06
MAGNITUDE (dB)
MAGNITUDE (dB)
0.04
0.02
0
–0.02
–0.04
–50
–100
–0.10
0
–150
2000 4000 6000 8000 10000 12000 14000 16000 18000
0
12
24
06623-006
–0.08
TE
06623-003
–0.06
36
48
FREQUENCY (kHz)
FREQUENCY (Hz)
Figure 3. ADC Pass-Band Filter Response, 48 kHz
Figure 6. DAC Stop-Band Filter Response, 48 kHz
0
0.10
LE
–10
–20
0.05
MAGNITUDE (dB)
–40
–50
–60
–90
–100
–0.05
06623-004
–80
B
SO
–70
0
0
–0.10
5000 10000 15000 20000 25000 30000 35000 40000
06623-007
MAGNITUDE (dB)
–30
0
24
FREQUENCY (Hz)
Figure 4. ADC Stop-Band Filter Response, 48 kHz
0.02
O
0
–0.02
0
–50
–100
06623-005
–0.04
–0.06
0
8
16
96
–150
24
06623-008
MAGNITUDE (dB)
0.04
72
Figure 7. DAC Pass-Band Filter Response, 96 kHz
MAGNITUDE (dB)
0.06
48
FREQUENCY (kHz)
0
24
48
72
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 8. DAC Stop-Band Filter Response, 96 kHz
Figure 5. DAC Pass-Band Filter Response, 48 kHz
Rev. B | Page 11 of 32
96
AD1928
0.5
0
0.4
0.3
–2
MAGNITUDE (dB)
0.1
0
–0.1
–4
–6
–0.2
–8
06623-009
–0.3
–0.4
0
8
16
32
–10
48
64
64
80
FREQUENCY (kHz)
TE
–0.5
06623-010
MAGNITUDE (dB)
0.2
FREQUENCY (kHz)
Figure 10. DAC Stop-Band Filter Response, 192 kHz
O
B
SO
LE
Figure 9. DAC Pass-Band Filter Response, 192 kHz
Rev. B | Page 12 of 32
96
AD1928
THEORY OF OPERATION
There are two analog-to-digital converter (ADC) channels in
the AD1928, configured as a stereo pair with differential inputs.
The ADCs can operate at a nominal sample rate of 48 kHz,
96 kHz, or 192 kHz. The ADCs include on-board digital
antialiasing filters with 79 dB stop-band attenuation and linear
phase response, operating at an oversampling ratio of 128
(48 kHz, 96 kHz, and 192 kHz modes). Digital outputs are
supplied through two serial data output pins (one for each
stereo pair) and a common frame clock (ALRCLK) and bit
clock (ABCLK). Alternatively, one of the TDM modes can be
used to access up to 14 channels on a single TDM data line.
CLOCK SIGNALS
The on-chip phase-locked loop (PLL) can be selected to
reference the input sample rate from either of the LRCLK pins
or 256, 384, 512, or 768 times the sample rate, referenced to the
48 kHz mode from the MCLKI/XI pin. The default at power-up
is 256 × fS from MCLKI/XI. In 96 kHz mode, the master clock
frequency stays at the same absolute frequency; therefore, the
actual multiplication rate is divided by 2. In 192 kHz mode,
the actual multiplication rate is divided by 4. For example, if the
AD1928 is programmed in 256 × fS mode, the frequency of the
master clock input is 256 × 48 kHz = 12.288 MHz. If the AD1928
is then switched to 96 kHz operation (by writing to the SPI
port), the frequency of the master clock should remain at
12.288 MHz, which, under these conditions, is 128 × fS. In 192 kHz
mode, this becomes 64 × fS.
LE
The ADCs must be driven from a differential signal source for
best performance. The input pins of the ADCs connect to internal
switched capacitors. To isolate the external driving op amp from
the glitches caused by the internal switched capacitors, each
input pin should be isolated by using a series-connected, external, 100 Ω resistor together with a 1 nF capacitor connected
from each input to ground. This capacitor must be of high quality,
for example, ceramic NP0 or polypropylene film.
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
TE
ANALOG-TO-DIGITAL CONVERTERS (ADCS)
B
SO
The differential inputs have a nominal common-mode voltage
of 1.5 V. The voltage at the common-mode reference pin (CM)
can be used to bias external op amps to buffer the input signals
(see the Power Supply and Voltage Reference section). The
inputs can also be ac-coupled and do not need an external dc
bias to CM.
A digital high-pass filter can be switched in line with the ADCs
under serial control to remove residual dc offsets. It has a
1.4 Hz, 6 dB per octave cutoff at a 48 kHz sample rate. The
cutoff frequency scales directly with sample frequency.
DIGITAL-TO-ANALOG CONVERTERS (DACS)
Note that it is not possible to use a direct clock for the ADCs set
to the 192 kHz mode. It is required that the on-chip PLL be
used in this mode.
The PLL can be powered down in the PLL and Clock Control 0
register. To ensure reliable locking when changing PLL modes,
or if the reference clock is unstable at power-on, power down
the PLL and then power it back up when the reference clock has
stabilized.
O
The AD1928 digital-to-analog converter (DAC) channels are
arranged as four single-ended stereo pairs, providing eight
analog outputs for minimum external components. The DACs
include on-board digital reconstruction filters with 70 dB stopband attenuation and linear phase response, operating at an
oversampling ratio of 4 (48 kHz or 96 kHz modes) or 2 (192 kHz
mode). Each channel has its own independently programmable
attenuator, adjustable in 255 steps in 0.375 dB increments. Digital
inputs are supplied through four serial data input pins (one for
each stereo pair) and a common frame clock (DLRCLK) and bit
clock (DBCLK). Alternatively, one of the TDM modes can be
used to access up to 16 channels on a single TDM data line.
The internal clock for the ADCs is 256 × fS for all clock modes.
The internal clock for the DACs varies by mode: 512 × fS (48 kHz
mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz mode). By
default, the on-board PLL generates this internal master clock
from an external clock. A direct 512 × fS (referenced to 48 kHz
mode) master clock can be used for either the ADCs or DACs if
selected in the PLL and Clock Control 1 register.
The internal master clock (MCLK) can be disabled in the PLL
and Clock Control 0 register to reduce power dissipation when
the AD1928 is idle. The clock should be stable before it is
enabled. Unless a standalone mode is selected (see the Serial
Control Port section), the clock is disabled by reset and must be
enabled by writing to the SPI port for normal operation.
Each output pin has a nominal common-mode dc level of 1.5 V
and swings ±1.27 V for a 0 dBFS digital input signal. A single op
amp, third-order, external, low-pass filter is recommended to
remove high frequency noise present on the output pins. The
use of op amps with low slew rate or low bandwidth can cause
high frequency noise and tones to fold down into the audio
band; therefore, exercise care in selecting these components.
To maintain the highest performance possible, it is recommended
that the clock jitter of the internal master clock signal be limited
to less than 300 ps rms TIE (time interval error). Even at these
levels, extra noise or tones can appear in the DAC outputs if the
jitter spectrum contains large spectral peaks. If the internal PLL
is not being used, it is best to use an independent crystal oscillator to generate the master clock. In addition, it is especially
important that the clock signal should not be passed through an
FPGA, CPLD, or other large digital chip (such as a DSP) before
being applied to the AD1928. In most cases, this induces clock
jitter due to the sharing of common power and
Rev. B | Page 13 of 32
AD1928
RESET AND POWER-DOWN
The function of the RST pin sets all the control registers to
their default settings. To avoid pops, reset does not power
down the analog outputs. After RST is deasserted and the PLL
acquires lock condition, an initialization routine runs inside the
AD1928. This initialization lasts for approximately 256 master
clock cycles.
The power-down bits in the PLL and Clock Control 0, DAC
Control 1, and ADC Control 1 registers power down the
respective sections. All other register settings are retained. The
reset pin, PD/RST, should be pulled low by an external resistor
to guarantee proper startup.
SERIAL CONTROL PORT
Table 11. Standalone Mode Selection
ADC Clocks
Slave
Master
CIN
0
0
COUT
0
1
CCLK
CCLK
0
0
B
SO
tCLS
CLATCH
The SPI control port of the AD1928 is a 4-wire serial control
port. The format is similar to the Motorola® SPI format, except
the input data-word is 24 bits wide. The serial bit clock and
latch can be completely asynchronous to the sample rate of the
ADCs and DACs. Figure 11 shows the format of the SPI signal.
The first byte is a global address with a read/write bit. For the
AD1928, the address is 0x04, shifted left 1 bit due to the R/W
bit. The second byte is the AD1928 register address and the
third byte is the data.
LE
The AD1928 has an SPI control port that permits programming
and reading back of the internal control registers for the ADCs,
DACs, and clock system. There is also a standalone mode
available for operation without serial control that is configured
at reset using the serial control pins. All registers are set to
default, except the internal master clock enable is set to 1
and ADC BCLK and LRCLK master/slave is set by the COUT
pin. Standalone mode only supports stereo mode with an I2S
data format and 256 fS master clock rate. Refer to Table 11 for
details. It is recommended to use a weak pull-up resistor on
CLATCH in applications that have a microcontroller. This pullup resistor ensures that the AD1928 recognizes the presence of
a microcontroller.
TE
ground connections with other unrelated digital output signals.
When the PLL is used, jitter in the reference clock is attenuated
above a certain frequency depending on the loop filter.
tCCH tCCL
tCCP
CLATCH
0
0
tCLH
tCOTS
CIN
COUT
D23
D22
D9
tCOE
D9
D8
D0
D8
D0
O
tCOD
Figure 11. Format of SPI Signal
Rev. B | Page 14 of 32
06623-011
tCDS tCDH
AD1928
POWER SUPPLY AND VOLTAGE REFERENCE
TIME-DIVISION MULTIPLEXED (TDM) MODES
The AD1928 is designed for 3.3 V supplies. Separate power
supply pins are provided for the analog and digital sections.
These pins should be bypassed with 100 nF ceramic chip
capacitors, as close to the pins as possible, to minimize noise
pickup. A bulk aluminum electrolytic capacitor of at least 22 μF
should also be provided on the same PC board as the codec. For
critical applications, improved performance is obtained with
separate supplies for the analog and digital sections. If this is
not possible, it is recommended that the analog and digital
supplies be isolated by means of a ferrite bead in series with
each supply. It is important that the analog supply be as clean
as possible.
The AD1928 serial ports also have several different TDM serial
data modes. The first and most commonly used configurations
are shown in Figure 12 and Figure 13. In Figure 12, the ADC
serial port outputs one data stream consisting of two on-chip
ADCs and unused slots. In Figure 13, the eight on-chip DAC
data slots are packed into one TDM stream. In this mode, both
DBCLK and ABCLK are 256 fS.
LE
The ADC and DAC internal voltage reference (VREF) is brought
out on FILTR and should be bypassed as close as possible to the
chip, with a parallel combination of 10 μF and 100 nF. Any
external current drawn should be limited to less than 50 μA.
The AD1928 allows systems with more than eight DAC channels
to be easily configured by the use of an auxiliary serial data port.
The DAC TDM-AUX mode is shown in Figure 14. In this mode,
the AUX channels are the last four slots of the TDM data stream.
These slots are extracted and output to the AUX serial port.
Note that due to the high DBCLK frequency, this mode is available
only in the 48 kHz/44.1 kHz/32 kHz sample rate.
TE
All digital inputs are compatible with TTL and CMOS levels.
All outputs are driven from the 3.3 V DVDD supply and are
compatible with TTL and 3.3 V CMOS levels.
The input/output pins of the serial ports are defined according
to the serial mode selected. For a detailed description of the
function of each pin in TDM and auxilliary modes, see
Table 12.
SERIAL DATA PORTS—DATA FORMAT
Combining the AUX ADC and DAC modes results in a system
configuration of 6 ADCs and 12 DACs. The system, then, consists of two external stereo ADCs, two external stereo DACs,
and one AD1928. This mode is shown in Figure 17 (combined
AUX DAC and ADC modes).
LRCLK
256 BCLKs
BCLK
DATA
32 BCLKs
SLOT 1
O
The eight DAC channels use a common serial bit clock (DBCLK)
and a common left-right framing clock (DLRCLK) in the serial
data port. The two ADC channels use a common serial bit clock
(ABCLK) and left-right framing clock (ALRCLK) in the serial
data port. The clock signals are all synchronous with the sample
rate. The normal stereo serial modes are shown in Figure 23.
The ADC and DAC serial data modes default to I2S. The ports
can also be programmed for left-justified, right-justified, and
TDM modes. The word width is 24 bits by default and can be
programmed for 16 or 20 bits. The DAC serial formats are
programmable according to DAC Control 0 register. The
polarity of the DBCLK and DLRCLK is programmable according
to the DAC Control 1 register. The ADC serial formats and
serial clock polarity are programmable according to ADC
Control 1 register. Both DAC and ADC serial ports are
programmable to become the bus masters according to the
DAC Control 1 register and the ADC Control 2 register. By
default, both ADC and DAC serial ports are in slave mode.
SLOT 2
SLOT 3
LEFT 1
SLOT 4
RIGHT 1
SLOT 5
SLOT 6
SLOT 7
SLOT 8
LRCLK
BCLK
MSB
MSB – 1
MSB – 2
06623-012
The CM pin is the internal common-mode reference. It should
be bypassed as close as possible to the chip, with a parallel
combination of 47 μF and 100 nF. This voltage can be used to
bias external op amps to the common-mode voltage of the input
and output signal pins. The output current should be limited to
less than 0.5 mA source and 2 mA sink.
The AD1928 also allows system configurations with more than
two ADC channels, as shown in Figure 15 and Figure 16, which
show configurations using 6 ADCs and 14 ADCs, respectively.
Again, due to the high ABCLK frequency, this mode is available
only in the 48 kHz/44.1 kHz/32 kHz sample rate.
DATA
Figure 12. ADC TDM (6-Channel I2S Mode)
LRCLK
256 BCLKs
BCLK
DATA
Rev. B | Page 15 of 32
32 BCLKs
SLOT 1
LEFT 1
SLOT 2
RIGHT 1
SLOT 3
LEFT 2
SLOT 4
RIGHT 2
SLOT 5
LEFT 3
SLOT 6
RIGHT 3
SLOT 7
LEFT 4
SLOT 8
RIGHT 4
LRCLK
BCLK
MSB
MSB – 1
MSB – 2
DATA
Figure 13. DAC TDM (8-Channel I2S Mode)
06623-013
B
SO
The internal reference can be disabled in the PLL and Clock
Control 1 register, and FILTR can be driven from an external
source. This can be used to scale the DAC output to the clipping
level of a power amplifier based on its power supply voltage.
The ADC input gain varies by the inverse ratio. The total gain
from ADC input to DAC output remains constant.
AD1928
Table 12. Pin Function Changes in TDM-AUX Mode
Stereo Modes
NC
ADC1 Data Output
DAC1 Data Input
DAC2 Data Input
DAC3 Data Input
DAC4 Data Input
ADC LRCLK Input/Output
ADC BCLK Input/Output
DAC LRCLK Input/Output
DAC BCLK Input/Output
TDM Modes
ADC TDM Data Output
ADC TDM Data Input
DAC TDM Data Input
DAC TDM Data Output
DAC TDM Data Input 2 (Dual-Line Mode)
DAC TDM Data Output 2 (Dual-Line Mode)
ADC TDM Frame Sync Input/Output
ADC TDM BCLK Input/Output
DAC TDM Frame Sync Input/Output
DAC TDM BCLK Input/Output
ABCLK
UNUSED SLOTS
EMPTY
EMPTY
EMPTY
32 BITS
DLRCLK
(AUX PORT)
DBCLK
(AUX PORT)
ASDATA1
(AUX1_OUT)
DSDATA4
(AUX2_OUT)
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
B
SO
MSB
DAC L1
LE
EMPTY
AUXILIARY DAC CHANNELS
WILL APPEAR AT
AUX DAC PORTS
8 ON-CHIP DAC CHANNELS
DAC L4
DAC R4
LEFT
MSB
MSB
MSB
Figure 14. 16-Channel DAC TDM-AUX Mode
O
AUX R1
AUX L2
AUX R2
RIGHT
MSB
Rev. B | Page 16 of 32
AUX L1
06623-014
ALRCLK
DSDATA1
(TDM_IN)
AUX Modes
TDM Data Output
AUX Data Output 1 (to External DAC 1)
TDM Data Input
AUX Data Input 1 (from External ADC 1)
AUX Data Input 2 (from External ADC 2)
AUX Data Output 2 (to External DAC 2)
TDM Frame Sync Input/Output
TDM BCLK Input/Output
AUX LRCLK Input/Output
AUX BCLK Input/Output
TE
Mnemonic
ADCTDMOUT
ASDATA1
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ALRCLK
ABCLK
DLRCLK
DBCLK
AD1928
ALRCLK
ABCLK
8 ON-CHIP DAC CHANNELS
DSDATA1
(TDM_IN)
DAC L1
ADCTDMOUT
(TDM_OUT)
UNUSED
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
ADC R1
AUX L1
AUX R1
2 ON-CHIP ADC CHANNELS
UNUSED
ADC L1
DAC L4
DAC R4
4-AUX ADC CHANNELS
AUX L2
AUX R2
TE
32 BITS
MSB
LEFT
RIGHT
DBCLK
(AUX PORT)
MSB
DSDATA3
(AUX2_IN)
MSB
MSB
LE
DSDATA2
(AUX1_IN)
MSB
06623-015
DLRCLK
(AUX PORT)
Figure 15. 6-Channel AUX ADC Mode
B
SO
ALRCLK
ABCLK
ADCTDMOUT
(TDM_OUT)
2 ON-CHIP ADC CHANNELS
UNUSED UNUSED ADC L1
ADC R1
AUXILIARY ADC CHANNELS
AUX L1
AUX R1
AUX L2
UNUSED SLOTS
AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
32 BITS
O
MSB
DLRCLK
(AUX PORT)
LEFT
RIGHT
DSDATA2
(AUX1_IN)
MSB
MSB
DSDATA3
(AUX2_IN)
MSB
MSB
Figure 16. 14-Channel AUX ADC Mode
Rev. B | Page 17 of 32
06623-016
DBCLK
(AUX PORT)
AD1928
ALRCLK
ABCLK
DSDATA1
(TDM_IN)
ADCTDMOUT
(TDM_OUT)
UNUSED SLOTS
EMPTY
EMPTY
EMPTY
EMPTY
2 ON-CHIP ADC CHANNELS
UNUSED UNUSED ADC L1
DLRCLK
(AUX PORT)
AUXILIARY DAC CHANNELS
WILL APPEAR AT
AUX DAC PORTS
8 ON-CHIP DAC CHANNELS
ADC R1
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
AUXILIARY ADC CHANNELS
AUX L1
AUX R1
AUX L2
DAC L4
DAC R4
AUX L1
AUX R1
AUX L2
AUX R2
UNUSED SLOTS
AUX R2 UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED
LEFT
RIGHT
DSDATA3
(AUX2_IN)
MSB
ASDATA1
(AUX1_OUT)
MSB
DSDATA4
(AUX2_OUT)
MSB
MSB
MSB
MSB
MSB
O
B
SO
Figure 17. Combined AUX DAC and ADC Mode
Rev. B | Page 18 of 32
06623-017
MSB
LE
DSDATA2
(AUX1_IN)
TE
DBCLK
(AUX PORT)
AD1928
There are two configurations for the ADC port to work in
daisy-chain mode. The first one is with an ABCLK at 256 fS,
shown in Figure 21. The second configuration is shown in
Figure 22. Note that in the 512 fS ABCLK mode, the ADC
channels occupy the first eight slots; the second eight slots are
empty. The TDM_IN of the first AD1928 must be grounded in
all modes of operation.
DAISY-CHAIN MODE
The AD1928 also allows a daisy-chain configuration to expand
the system to 4 ADCs and 16 DACs (see Figure 18). In this mode,
the DBCLK frequency is 512 fS. The first eight slots of the DAC
TDM data stream belong to the first AD1928 in the chain and
the last eight slots belong to the second AD1928. The second
AD1928 is the device attached to the DSP TDM port.
The input/output pins of the serial ports are defined according
to the serial mode selected. See Table 13 for a detailed
description of the function of each pin. See Figure 26 for a
typical AD1928 configuration with two external stereo DACs
and two external stereo ADCs.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1928 can be configured into a dual-line TDM mode, as
shown in Figure 19. This mode allows a slower DBCLK than
normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first AD1928 in the chain and the last four channels belong to
the second AD1928.
TE
Figure 23 through Figure 25 show the serial mode formats. For
maximum flexibility, the polarity of LRCLK and BCLK are
programmable. In these figures, all of the clocks are shown with
their normal polarity. The default mode is I2S.
The dual-line TDM mode can also be used to send data at a
192 kHz sample rate into the AD1928, as shown in Figure 20.
DBCLK
LE
DLRCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DAC L1
DAC R1
DAC L2
DAC L3
DAC R3
DAC L4
DAC R4
B
SO
DSDATA2 (TDM_OUT)
OF THE SECOND AD1928
THIS IS THE TDM
TO THE FIRST AD1928
DAC R2
FIRST
AD1928
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
8 UNUSED SLOTS
SECOND
AD1928
DSP
32 BITS
MSB
O
Figure 18. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two-AD1928 Daisy Chain)
Rev. B | Page 19 of 32
06623-018
DSDATA1 (TDM_IN)
OF THE SECOND AD1928
AD1928
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
DSDATA1
(IN)
DAC L1
DAC R1
DAC L2
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
DAC R2
DSDATA2
(OUT)
DSDATA3
(IN)
DAC L3
DAC R3
DAC L4
DAC R4
DSDATA4
(OUT)
DAC L1
DAC R1
DAC L2
DAC R2
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
DAC L3
DAC R3
DAC L4
DAC R4
MSB
SECOND
AD1928
DSP
LE
FIRST
AD1928
06623-019
TE
32 BITS
Figure 19. Dual-Line DAC TDM Mode (Applicable to 96 kHz Sample Rate, 16-Channel, Two-AD1928 Daisy Chain, DSDATA3 and DSDATA4 are the Daisy Chain)
DLRCLK
DSDATA1
DSDATA2
B
SO
DBCLK
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
06623-020
32 BITS
MSB
O
Figure 20. Dual-Line DAC TDM Mode (Applicable to 192 kHz Sample Rate, 8-Channel Mode)
ALRCLK
ABCLK
2 ADC CHANNELS OF SECOND IC IN THE CHAIN
ADCTDMOUT (TDM_OUT
OF THE SECOND AD1928
IN THE CHAIN)
UNUSED
UNUSED
ADC L1
ADC R1
ASDATA1 (TDM_IN
OF THE SECOND AD1928
IN THE CHAIN)
UNUSED
UNUSED
ADC L1
ADC R1
2 ADC CHANNELS OF FIRST IC IN THE CHAIN
UNUSED
UNUSED
ADC L1
ADC R1
32 BITS
SECOND
AD1928
DSP
MSB
Figure 21. ADC TDM Daisy-Chain Mode (256 fS BCLK, Two-AD1928 Daisy Chain)
Rev. B | Page 20 of 32
06623-021
FIRST
AD1928
AD1928
ALRCLK
ABCLK
2 ADC CHANNELS OF
SECOND IC IN THE CHAIN
2 ADC CHANNELS OF
FIRST IC IN THE CHAIN
ADCTDMOUT (TDM_OUT
OF THE SECOND AD1928
IN THE CHAIN)
UNUSED UNUSED ADC L1
ADC R1 UNUSED UNUSED ADC L1
ASDATA1 (TDM_IN
OF THE SECOND AD1928
IN THE CHAIN)
UNUSED UNUSED ADC L1
ADC R1
ADC R1
32 BITS
DSP
06623-022
SECOND
AD1928
TE
FIRST
AD1928
MSB
Figure 22. ADC TDM Daisy-Chain Mode (512 fS BCLK, Two-AD1928 Daisy Chain)
BCLK
SDATA
MSB
RIGHT CHANNEL
LE
LEFT CHANNEL
LRCLK
MSB
LSB
LSB
LEFT-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
LRCLK
B
SO
BCLK
SDATA
RIGHT CHANNEL
MSB
LSB
MSB
LSB
I2S-JUSTIFIED MODE—16 BITS TO 24 BITS PER CHANNEL
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB
RIGHT CHANNEL
LSB
MSB
LSB
RIGHT-JUSTIFIED MODE—SELECT NUMBER OF BITS PER CHANNEL
MSB
O
BCLK
SDATA
LSB
MSB
LSB
DSP MODE—16 BITS TO 24 BITS PER CHANNEL
1/fS
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL.
2. LRCLK NORMALLY OPERATES AT fS EXCEPT FOR DSP MODE WHICH, IS 2 × fS.
3. BCLK FREQUENCY IS NORMALLY 64 × LRCLK BUT MAY BE OPERATED IN BURST MODE.
Figure 23. Stereo Serial Modes
Rev. B | Page 21 of 32
06623-023
LRCLK
AD1928
tDBH
tDBP
DBCLK
tDBL
tDLS
tDLH
DLRCLK
tDLSKEW
tDDS
DSDATA
LEFT-JUSTIFIED
MODE
MSB – 1
MSB
tDDH
tDDS
DSDATAx
I2S-JUSTIFIED
MODE
MSB
TE
tDDH
tDDS
MSB
LSB
tDDH
tDDH
06623-024
tDDS
DSDATAx
RIGHT-JUSTIFIED
MODE
LE
Figure 24. DAC Serial Timing
tABH
ABCLK
tABL
tALS
ALRCLK
ASDATA
LEFT-JUSTIFIED
MODE
B
SO
tALSKEW
tALH
tABDD
MSB
MSB – 1
tABDD
ASDATA
I2S-JUSTIFIED
MODE
MSB
ASDATA
RIGHT-JUSTIFIED
MODE
O
Figure 25. ADC Serial Timing
Rev. B | Page 22 of 32
MSB
LSB
06623-025
tABDD
AD1928
Table 13. Pin Function Changes in TDM-AUX Mode (Replication of Table 12)
BCLK
DATA
TFS (NC)
RxDATA
ADCTDMOUT ALRCLK ABCLK DSDATA1
B
SO
MCLK
SHARC IS RUNNING IN SLAVE MODE
(INTERRUPT-DRIVEN)
LE
LRCLK
AUX
ADC 1
SHARC
RxCLK
12.288MHz
FSYNC-TDM (RFS)
30MHz
AUX Modes
TDM Data Output
AUX Data Output 1 (to External DAC 1)
TDM Data Input
AUX Data Input 1 (from External ADC 1)
AUX Data Input 2 (from External ADC 2)
AUX Data Output 2 (to External. DAC 2)
TDM Frame Sync Input/Output
TDM BCLK Input/Output
AUX LRCLK Input/Output
AUX BCLK Input/Output
TE
TDM Modes
ADC TDM Data Output
ADC TDM Data Input
DAC TDM Data Input
DAC TDM Data Output
DAC TDM Data Input 2 (Dual-Line Mode)
DAC TDM Data Output 2 (Dual-Line Mode)
ADC TDM Frame Sync Input/Output
ADC TDM BCLK Input/Output
DAC TDM Frame Sync Input/Output
DAC TDM BCLK Input/Output
TxDATA
Stereo Modes
NC
ADC1 Data Output
DAC1 Data Input
DAC2 Data Input
DAC3 Data Input
DAC4 Data Input
ADC LRCLK Input/Output
ADC BCLK Input/Output
DAC LRCLK Input/Output
DAC BCLK Input/Output
TxCLK
Mnemonic
ADCTDMOUT
ASDATA1
DSDATA1
DSDATA2
DSDATA3
DSDATA4
ALRCLK
ABCLK
DLRCLK
DBCLK
LRCLK
BCLK
AUX
DATA DAC 1
MCLK
DBCLK
AD1928
BCLK
DSDATA2
DATA
DSDATA3
TDM MASTER
AUX MASTER
AUX
ADC 2
MCLK
MCLKI/XI
LRCLK
ASDATA1
DSDATA4
BCLK
AUX
DATA DAC 2
MCLK
O
Figure 26. Example of AUX Mode Connection to SHARC® (AD1928 as TDM Master/AUX Master Shown)
Rev. B | Page 23 of 32
06623-026
DLRCLK
LRCLK
AD1928
CONTROL REGISTERS
DEFINITIONS
The global address for the AD1928 is 0x04, shifted left one bit due to the R/W bit. All registers are reset to 0, except for the DAC volume
registers that are set to full volume. Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Bit
Global Address
R/W
Register Address
Data
23:17
16
15:8
7:0
LE
Function
PLL and Clock Control 0
PLL and Clock Control 1
DAC Control 0
DAC Control 1
DAC Control 2
DAC individual channel mutes
DAC 1L volume control
DAC 1R volume control
DAC 2L volume control
DAC 2R volume control
DAC 3L volume control
DAC 3R volume control
DAC 4L volume control
DAC 4R volume control
ADC Control 0
ADC Control 1
ADC Control 2
B
SO
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TE
Table 15. Register Addresses and Functions
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0 Register
2:1
4:3
6:5
7
Value
0
1
00
01
10
11
00
01
10
11
00
01
10
11
0
1
Function
Normal operation
Power-down
Input 256 (×44.1 kHz or 48 kHz)
Input 384 (×44.1 kHz or 48 kHz)
Input 512 (×44.1 kHz or 48 kHz)
Input 768 (×44.1 kHz or 48 kHz)
XTAL oscillator enabled
256 × fS VCO output
512 × fS VCO output
Off
MCLKI/XI
DLRCLK
ALRCLK
Reserved
Disable: ADC and DAC idle
Enable: ADC and DAC active
O
Bit
0
Description
PLL power-down
MCLKI/XI pin functionality (PLL active), master clock rate setting
MCLKO/XO pin, master clock rate setting
PLL input
Internal master clock enable
Rev. B | Page 24 of 32
AD1928
Table 17. PLL and Clock Control 1 Register
1
2
3
7:4
Value
0
1
0
1
0
1
0
1
0000
Function
PLL clock
MCLK
PLL clock
MCLK
Enabled
Disabled
Not locked
Locked
Reserved
Description
DAC clock source select
ADC clock source select
On-chip voltage reference
PLL lock indicator (read only)
TE
Bit
0
DAC CONTROL REGISTERS
Table 18. DAC Control 0 Register
5:3
7:6
Function
Normal operation
Power-down
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
1
0
8
12
16
Reserved
Reserved
Reserved
Stereo (normal)
TDM (daisy chain)
DAC AUX mode (ADC-, DAC-, TDM-coupled)
Dual-line TDM
Description
Power-down
Sample rates
LE
2:1
Value
0
1
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
SDATA delay (BCLK periods)
B
SO
Bit
0
Serial format
Table 19. DAC Control 1 Register
Value
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
Function
Latch in midcycle (normal)
Latch in at end of cycle (pipeline)
64 (2 channels)
128 (4 channels)
256 (8 channels)
512 (16 channels)
Left low
Left high
Slave
Master
Slave
Master
DBCLK pin
Internally generated
Normal
Inverted
O
Bit
0
2:1
3
4
5
6
7
Description
BCLK active edge (TDM in)
BCLKs per frame
LRCLK polarity
LRCLK master/slave
BCLK master/slave
BCLK source
BCLK polarity
Rev. B | Page 25 of 32
AD1928
Table 20. DAC Control 2 Register
2:1
4:3
5
7:6
Value
0
1
00
01
10
11
00
01
10
11
0
1
00
Function
Unmute
Mute
Flat
48 kHz curve
44.1 kHz curve
32 kHz curve
24
20
Reserved
16
Noninverted
Inverted
Reserved
Description
Master mute
De-emphasis (32 kHz/44.1 kHz/48 kHz mode only)
Word width
DAC output polarity
TE
Bit
0
Table 21. DAC Individual Channel Mutes
2
3
4
5
6
7
Function
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Unmute
Mute
Description
DAC 1L mute
LE
1
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DAC 1R mute
DAC 2L mute
DAC 2R mute
B
SO
Bit
0
DAC 3L mute
DAC 3R mute
DAC 4L mute
DAC 4R mute
Table 22. DAC Volume Controls
Value
0
1 to 254
255
Function
No attenuation
−3/8 dB per step
Full attenuation
O
Bit
7:0
Description
DAC volume control
Rev. B | Page 26 of 32
AD1928
ADC CONTROL REGISTERS
Table 23. ADC Control 0 Register
2
3
4
5
7:6
Function
Normal operation
Power down
Off
On
Reserved
Reserved
Unmute
Mute
Unmute
Mute
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
Table 24. ADC Control 1 Register
4:2
6:5
ADC 1L mute
ADC 1R mute
Output sample rate
Function
24
20
Reserved
16
1
0
8
12
16
Reserved
Reserved
Reserved
Stereo
TDM (daisy chain)
ADC AUX mode (ADC-, DAC-, TDM-coupled)
Reserved
Latch in midcycle (normal)
Latch in at end of cycle (pipeline)
O
7
Value
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
0
1
High-pass filter
B
SO
Bit
1:0
Description
Power-down
TE
1
Value
0
1
0
1
0
0
0
1
0
1
00
01
10
11
LE
Bit
0
Rev. B | Page 27 of 32
Description
Word width
SDATA delay (BCLK periods)
Serial format
BCLK active edge (TDM in)
AD1928
Table 25. ADC Control 2 Register
5:4
6
7
BCLK polarity
LRCLK polarity
LRCLK master/slave
BCLKs per frame
TE
3
Description
LRCLK format
BCLK master/slave
BCLK source
LE
2
1
0
1
0
1
0
1
00
01
10
11
0
1
0
1
Function
50/50 (allows 32, 24, 20, 16 bit clocks (BCLKs) per
channel
Pulse (32 BCLKs per channel)
Drive out on falling edge (DEF)
Drive out on rising edge
Left low
Left high
Slave
Master
64
128
256
512
Slave
Master
ABCLK pin
Internally generated
B
SO
1
Value
0
O
Bit
0
Rev. B | Page 28 of 32
AD1928
ADDITIONAL MODES
The AD1928 offers several additional modes for board-level
design enhancements. To reduce the EMI in board-level design,
serial data can be transmitted without an explicit BCLK. See
Figure 27 for an example of a DAC TDM data transmission
mode that does not require high speed DBCLK. This configuration is applicable when the AD1928 master clock is generated
by the PLL with the DLRCLK as the PLL reference frequency.
To relax the requirement for the setup time of the AD1928 in
cases of high speed TDM data transmission, the AD1928 can
latch in the data using the falling edge of DBCLK. This
effectively dedicates the entire BCLK period to the setup time.
This mode is useful in cases where the source has a large delay
time in the serial data driver. Figure 28 shows this pipeline
mode of data transmission.
Both the BCLK-less and pipeline modes are available on the
ADC serial data port.
DLRCLK
TE
32 BITS
INTERNAL
DBCLK
DLRCLK
INTERNAL
DBCLK
TDM-DSDATAx
06623-027
LE
DSDATAx
B
SO
Figure 27. Serial DAC Data Transmission in TDM Format without DBCLK
(Applicable only if PLL locks to DLRCLK. This mode is also available in the ADC serial data port.)
DLRCLK
DBCLK
DSDATAx
MSB
O
Figure 28. I2S Pipeline Mode in DAC Serial Data Transmission
(Applicable in stereo and TDM, useful for high frequency TDM transmission. This mode is also available in the ADC serial data port.)
Rev. B | Page 29 of 32
06623-028
DATA MUST BE VALID
AT THIS BCLK EDGE
AD1928
APPLICATION CIRCUITS
Typical applications circuits are shown in Figure 29 through
Figure 32. Figure 29 shows a typical ADC input filter circuit.
Recommended loop filters for LR clock and master clock as the
PLL reference are shown in Figure 30. Output filters for the
DAC outputs are shown in Figure 31 and Figure 32 for the
noninverting and inverting cases.
120pF
5.76kΩ
5.76kΩ
2
100pF
3
–
240pF
NP0
1
OP275
+
4.7µF 237Ω
5.76kΩ
+
120pF
ADCxN
1nF
NP0
7
1nF
NP0
ADCxP
+
+
LRCLK
39nF
11kΩ
5.6nF
2.2nF
DAC
OUT
390pF
562Ω
AVDD2
06623-030
3.32kΩ
AVDD2
MCLK
B
SO
+
LF
1
604Ω 4.7µF
–
+
3.3nF
NP0
4.99kΩ
AUDIO
OUTPUT
49.9kΩ
4.99kΩ
Figure 31. Typical DAC Output Filter Circuit (Single-Ended, Noninverting)
Figure 29. Typical ADC Input Filter Circuit
LF
+
OP275
LE
OP275
4.7µF 237Ω
06623-029
5
5.76kΩ
–
2
270pF
NP0
100pF
6
3
4.75kΩ 4.75kΩ
TE
DAC OUT
06623-031
600Z
2
11kΩ
3.01kΩ
CM
270pF
NP0
0.1µF
3
–
OP275
+
1
604Ω 4.7µF
+
2.2nF
NP0
AUDIO
OUTPUT
49.9kΩ
Figure 32. Typical DAC Output Filter Circuit (Single-Ended, Inverting)
O
Figure 30. Recommended Loop Filters for LRCLK and MCLK PLL Reference
68pF
NP0
Rev. B | Page 30 of 32
06623-032
AUDIO
INPUT
AD1928
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
0.15
0.05
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
VIEW A
0.27
0.22
0.17
TE
ROTATED 90° CCW
24
051706-A
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 33. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature Range
−40°C to +105°C
−40°C to +105°C
1
Package Description
48-Lead LQFP
48-Lead LQFP, 13” Tape and Reel
Evaluation Board
LE
Model 1, 2, 3
AD1928YSTZ
AD1928YSTZ-RL
EVAL-AD1938AZ
Package Option
ST-48
ST-48
Z = RoHS Compliant Part.
For the AD1928YSTZ and AD1928YSTZ-RL: single-ended output; SPI control port.
3
The EVAL-AD1938AZ should be used as the evaluation board for the AD1928. The AD1938 is a functional equivalent to the AD1928, featuring two additional ADC
channels.
O
B
SO
2
Rev. B | Page 31 of 32
AD1928
O
B
SO
LE
TE
NOTES
©2007-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09656-0-7/11(B)
Rev. B | Page 32 of 32
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