AD2S90AP

a FEATURES Complete Monolithic Resolver-to-Digital Converter Incremental Encoder Emulation (1024-Line) Absolute Serial Data (12-Bit) Differential Inputs 12-Bit Resolution Industrial Temperature Range 20-Lead PLCC Low Power (50 mW) APPLICATIONS Industrial Motor Control Servo Motor Control Industrial Gauging Encoder Emulation Automotive Motion Sensing and Control Factory Automation Limit Switching GENERAL DESCRIPTION The AD2S90 is a complete 12-bit resolution tracking resolverto-digital converter. No external components are required to operate the device. The converter accepts 2 V rms ± 10% input signals in the range 3 kHz–20 kHz on the SIN, COS and REF inputs. A Type II servo loop is employed to track the inputs and convert the input SIN and COS information into a digital representation of the input angle. The bandwidth of the converter is set internally at 1 kHz within the tolerances of the device. The guaranteed maximum tracking rate is 500 rps. Angular position output information is available in two forms, absolute serial binary and incremental A quad B. The absolute serial binary output is 12-bit (1 in 4096). The data output pin is high impedance when Chip Select CS is logic HI. This allows the connection of multiple converters onto a common bus. Absolute angular information in serial pure binary form is accessed by CS followed by the application of an external clock (SCLK) with a maximum rate of 2 MHz. Low Cost, Complete 12-Bit Resolver-to-Digital Converter AD2S90 FUNCTIONAL BLOCK DIAGRAM REF SIN (u – f) SIN SIN LO COS ANGLE u COS LO NMC A B NM CS SCLK DATA DECODE LOGIC HIGH ACCURACY SIN COS MULTIPLIER P.S.D. AND VEL FREQUENCY SHAPING ERROR AMPLIFIER DIGITAL ANGLE f U/D UP-DOWN COUNTER CLK CLKOUT HIGH DYNAMIC RANGE V.C.O. DIR LATCH SERIAL INTERFACE The AD2S90 operates on ± 5 V dc ± 5% power supplies and is fabricated on Analog Devices’ Linear Compatible CMOS process (LC2MOS). LC2MOS is a mixed technology process that combines precision bipolar circuits with low power CMOS logic circuits. PRODUCT HIGHLIGHTS Complete Resolver-Digital Interface. The AD2S90 provides the complete solution for digitizing resolver signals (12-bit resolution) without the need for external components. Dual Format Position Data. Incremental encoder emulation in standard A QUAD B format with selectable North Marker width. Absolute serial 12-bit angular binary position data accessed via simple 3-wire interface. Single High Accuracy Grade in Low Cost Package. ±10.6 arc minutes of angular accuracy available in a 20-lead PLCC. Low Power. Typically 50 mW power consumption. The encoder emulation outputs A, B and NM continuously produce signals equivalent to a 1024 line encoder. When decoded this corresponds to 12 bits of resolution. Three common north marker pulsewidths are selected via a single pin (NMC). An analog velocity output signal provides a representation of velocity from a rotating resolver shaft traveling in either a clockwise or counterclockwise direction. REV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 = +5 V ⴞ 5%, V AD2S90–SPECIFICATIONS (Votherwise noted) DD SS = –5 V ⴞ 5%, AGND = DGND = 0 V, TA = –40ⴗC to +85ⴗC unless Parameter Min Typ Max Units Test Condition SIGNAL INPUTS Voltage Amplitude 1.8 2.0 2.2 V rms Sinusoidal Waveforms, Differential SIN to SINLO, COS to COSLO 20 100 kHz nA MΩ mV peak dB Frequency Input Bias Current Input Impedance Common-Mode Volts1 CMRR REFERENCE INPUT Voltage Amplitude Frequency Input Bias Current Input Impedance Permissible Phase Shift CONVERTER DYNAMICS Bandwidth Maximum Tracking Rate Maximum VCO Rate (CLKOUT) Settling Time 1° Step 179° Step 3 1.0 100 60 1.8 3 2.0 100 –10 700 500 2.048 +10 LOGIC INPUTS SCLK, CS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance LOGIC OUTPUTS DATA, A, B,4 NM, CLKOUT, DIR Output High Voltage Output Low Voltage 120 ± 2.78 1000 Hz rps MHz 2 7 20 ms ms ± 10.6 + 1 LSB 1 arc min LSB 180 ± 4.17 ± 250 rps/V dc V dc µA 1.5 10 10 V dc V dc µA pF 1.0 0.4 V dc V dc V dc 2 MHz 150 ± 3.33 3.5 4.0 SERIAL CLOCK (SCLK) SCLK Input Rate NORTH MARKER CONTROL (NMC) 90° 180° 360° POWER SUPPLIES VDD VSS IDD ISS V rms kHz nA kΩ Degrees 840 ACCURACY Angular Accuracy2 Repeatability3 VELOCITY OUTPUT Scaling Output Voltage at 500 rps Load Drive Capability 3.35 20 100 +4.75 –0.75 –4.75 +5.0 DGND –5.0 +5.25 +0.75 –5.25 V dc V dc V dc +4.75 –4.75 +5.00 –5.00 +5.25 –5.25 10 10 V dc V dc mA mA VIN = 2 ± 10% V rms VIN = 2 ± 10% V rms CMV @ SINLO, COSLO w.r.t. AGND @ 10 kHz Sinusoidal Waveform Relative to SIN, COS Inputs VOUT = ±2.5 V dc (typ), RL ≥ 10 kΩ VDD = +5 V dc, VSS = –5 V dc VDD = +5 V dc, VSS = –5 V dc VDD = +5 V dc, VSS = –5 V dc IOH = 1 mA IOL = 1 mA IOL = 400 µA North Marker Width Relative to “A” Cycle NOTES 1 If the tolerance on signal inputs = ± 5%, then CMV = 200 mV. 2 1 LSB = 5.3 arc minute. 3 Specified at constant temperature. 4 Output load drive capability. Specifications subject to change without notice. –2– REV. D AD2S90 TIMING CHARACTERISTICS1, 2 (VDD = +5 V ⴞ 5%, VSS = –5 V ⴞ 5%, AGND = DGND = 0 V, TA = –40ⴗC to +85ⴗC unless otherwise noted) t2 t6 CSB t3 SCLK t4 t* MSB DATA t1 LSB t7 t5 *THE MINIMUM ACCESS TIME: USER DEPENDENT Figure 1. Serial Interface NOTES 1 Timing data are not 100% production tested. Sample tested at +25°C only to ensure conformance to data sheet limits. Logic output timing tests carried out using 10 pF, 100 kΩ load. 2 Capacitance of data pin in high impedance state = 15 pF. Parameter AD2S90 Units Test Conditions/Notes t1 t2 1 t3 t4 t5 t6 t7 150 600 250 250 100 600 150 ns max ns min ns min ns min ns max ns min ns max CS to DATA Enable CS to 1st SCLK Negative Edge SCLK Low Pulse SCLK High Pulse SCLK Negative Edge to DATA Valid CS High Pulsewidth CS High to DATA High Z (Bus Relinquish) NOTE 1 SCLK can only be applied after t2 has elapsed. COUNTER IS CLOCKED ON THIS EDGE A tCLK CLKOUT B tABN 908 A, B, NM NM 1808 tDIR DIR 3608 NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE Figure 2. Incremental Encoder Figure 3. DIR/CLKOUT/A, B and NM Timing AD2S90 Parameter Min Max Units Test Conditions/Notes tDIR tCLK tABN 250 200 400 250 ns ns ns DIR to CLKOUT Positive Edge CLKOUT Pulsewidth CLKOUT Negative Edge to A, B and NM Transition REV. D –3– AD2S90 RECOMMENDED OPERATING CONDITIONS PIN DESCRIPTIONS Power Supply Voltage (VDD – VSS) . . . . . . . . . . ± 5 V dc ± 5% Analog Input Voltage (SIN, COS & REF) . . . . . 2 V rms ± 10% Signal and Reference Harmonic Distortion . . . . . . . . . . . . 10% Phase Shift between Signal and Reference . . . . . . . . . . . . . ± 10° Ambient Operating Temperature Range Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Pin No. Mnemonic Function 1 AGND Analog ground, reference ground. 2 SIN SIN channel noninverting input connect to resolver SIN HI output. SIN to SIN LO = 2 V rms ± 10%. 3 SIN LO SIN channel inverting input connect to resolver SIN LO. 4 DATA Serial interface data output. High impedance with CS = HI. Enabled by CS = 0. 5 SCLK Serial interface clock. Data is clocked out on “first” negative edge of SCLK after a LO transition on CS. 12 SCLK pulses to clock data out. 6 CS Chip select. Active LO. Logic LO transition enables DATA output. 7 A Encoder A output. 8 B Encoder B output. 9 NM Encoder North Marker emulation output. Pulse triggered as code passes through zero. Three common pulsewidths available. 10 DIR Indicates direction of rotation of input. Logic HI = increasing angular rotation. Logic LO = decreasing angular rotation. 11 ABSOLUTE MAXIMUM RATINGS* VDD to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V dc to +7.0 V dc VSS to AGND . . . . . . . . . . . . . . . . . . . . +0.3 V dc to –7.0 V dc AGND to DGND . . . . . . . . . . . . –0.3 V dc to VDD + 0.3 V dc Analog Inputs to AGND REF . . . . . . . . . . . . . . . . . . VSS – 0.3 V dc to VDD + 0.3 V dc SIN, SIN LO . . . . . . . . . . . VSS – 0.3 V dc to VDD + 0.3 V dc COS, COS LO . . . . . . . . . . VSS – 0.3 V dc to VDD + 0.3 V dc Analog Output to AGND VEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD Digital Inputs to DGND, CSB, SCLK, RES . . . . . . . . . . . . . . . –0.3 V dc to VDD + 0.3 V dc Digital Outputs to DGND, NM, A, B, DIR, CLKOUT DATA . . . . . . –0.3 V dc to VDD + 0.3 V dc Operating Temperature Range Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C Power Dissipation to +75°C . . . . . . . . . . . . . . . . . . . . 300 mW Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DGND Digital power ground return. 12 VSS Negative power supply, –5 V dc ± 5%. 13 VDD Positive power supply, +5 V dc ± 5%. ORDERING GUIDE 14 VDD Positive power supply, +5 V dc ± 5%. Must be connected to Pin 13. 15 NMC North marker width control. Internally pulled HI via 50 kΩ nominal. 16 CLKOUT Internal VCO clock output. Indicates angular velocity of input signals. Max nominal rate = 1.536 MHz. CLKOUT is a 300 ns positive pulse. 17 VEL Indicates angular velocity of input signals. Positive voltage w.r.t. AGND indicates increasing angle. FSD = 375 rps. 18 REF Converter reference input. Normally derived from resolver primary excitation. REF = 2 V rms nominal. Phase shift w.r.t. COS and SIN = ± 10° max 19 COS LO COS channel inverting input. Connect to resolver COS LO. 20 COS COS channel noninverting input. Connect to resolver COS HI output. COS = 2 V rms ± 10%. Model Temperature Range Accuracy AD2S90AP –40°C to +85°C Package Option 10.6 arc min P-20A SIN LO SIN AGND COS COS LO PIN CONFIGURATION 3 2 1 20 19 PIN 1 18 IDENTIFIER 17 DATA 4 SCLK 5 AD2S90 CS 6 TOP VIEW (Not to Scale) A 7 B 8 VEL 16 CLKOUT 15 NMC 14 VDD 13 VDD 12 VSS 11 DGND NM 10 DIR 9 REF CAUTION The AD2S90 features an input protection circuit consisting of large “distributed” diodes and polysilicon series resistors to dissipate both high energy discharges (Human Body Model) and fast, low energy pulses (Charges Device Model). Proper ESD precautions are strongly recommended to avoid functional damage or performance degradation. For further information on ESD precautions, refer to Analog Devices ESD Prevention Manual. –4– WARNING! ESD SENSITIVE DEVICE REV. D AD2S90 For more information on the operation of the converter, see Circuit Dynamics section. RESOLVER FORMAT SIGNALS A resolver is a rotating transformer which has two stator windings and one rotor winding. The stator windings are displaced mechanically by 90° (see Figure 4). The rotor is excited with an ac reference. The amplitude of subsequent coupling onto the stator windings is a function of the position of the rotor (shaft) relative to the stator. The resolver, therefore, produces two output voltages (S3–S1, S2–S4) modulated by the SINE and COSINE of shaft angle. Resolver format signals refer to the signals derived from the output of a resolver. Equation 1 illustrates the output form. S3–S1 = EO SIN ωt • SINθ S2–S4 = EO SIN ωt • COSθ where: S2 TO S4 (COS) S3 TO S1 (SIN) (1) R2 TO R4 (REF) θ = shaft angle SIN ωt = rotor excitation frequency EO = rotor excitation amplitude 08 908 1808 2708 3608 u Principle of Operation The AD2S90 operates on a Type 2 tracking closed-loop principle. The output continually tracks the position of the resolver without the need for external convert and wait states. As the transducer moves through a position equivalent to the least significant bit weighting, the output is updated by one LSB. Figure 4. Electrical and Physical Resolver Representation Connecting The Converter Refer to Figure 4. Positive power supply VDD = +5 V dc ± 5% should be connected to Pin 13 & Pin 14 and negative power supply VSS = –5 V dc ± 5% to Pin 12. Reversal of these power supplies will destroy the device. S3 (SIN) and S2 (COS) from the resolver should be connected to the SIN and COS pins of the converter. S1 (SIN) and S4 (COS) from the resolver should be connected to the SINLO and COSLO pins of the converter. The maximum signal level of either the SIN or COS resolver outputs should be 2 V rms ± 10%. The AD2S90 AGND pin is the point at which all analog signal grounds should be star connected. The SIN LO and COS LO pins on the AD2S90 should be connected to AGND. Separate screened twisted cable pairs are recommended for all analog inputs SIN, COS, and REF. The screens should terminate at the converter AGND pin. On the AD2S90, CLKOUT updates corresponding to one LSB increment. If we assume that the current word state of the up-down counter is φ, S3–S1 is multiplied by COS φ and S2–S4 is multiplied by SIN φ to give: EO SIN ωt • SIN θ COSφ EO SIN ωt • COS θ SINφ (2) An error amplifier subtracts these signals giving: EO SIN θ • (SIN θ COS φ – COS θ SIN φ) or EO SIN ωt • SIN (θ – φ) (3) where (θ – φ) = angular error North marker width selection is controlled by Pin 15, NMC. Application of VDD, 0 V, or VSS to NMC will select standard 90°, 180° and 360° pulsewidths. If unconnected, the NM pulse defaults to 90°. For a more detailed description of the output formats available see the Position Output section. A phase sensitive detector, integrator and voltage controlled oscillator (VCO) form a closed loop system which seeks to null sin (θ – φ). When this is accomplished the word state of the up/down counter, φ, equals within the rated accuracy of the converter, the resolver shaft angle θ. +5V OSCILLATOR 10nF 47mF 10nF 47mF 0V (POWER GROUND) 18 17 16 15 REF TWISTED PAIR SCREENED CABLE S2 R1 R2 S4 S2 S4 S3 S3 S1 S1 14 –5V VDD 19 COS LO VDD 13 20 COS VSS 12 1 AGND 2 SIN 3 SIN LO 4 DGND 11 10 AD2S90AP 5 6 7 9 8 RESOLVER POWER RETURN Figure 5. Connecting the AD2S90 to a Resolver REV. D –5– AD2S90 ABSOLUTE POSITION OUTPUT The north marker pulse is generated as the absolute angular position passes through zero. The AD2S90 supports the three industry standard widths controlled using the NMC pin. Figure 7 details the relationship between A, B and NM. The width of NM is defined relative to the A cycle. SERIAL INTERFACE Absolute angular position is represented by serial binary data and is extracted via a three-wire interface, DATA, CS and SCLK. The DATA output is held in a high impedance state when CS is HI. INCREASING ANGLE Upon the application of a Logic LO to the CS pin, the DATA output is enabled and the current angular information is transferred from the counters to the serial interface. Data is retrieved by applying an external clock to the SCLK pin. The maximum data rate of the SCLK is 2 MHz. To ensure secure data retrieval it is important to note that SCLK should not be applied until a minimum period of 600 ns after the application of a Logic LO to CS. Data is then clocked out, MSB first, on successive negative edges of the SCLK; 12 clock edges are required to extract the full 12 bits of data. Subsequent negative edges greater than the defined resolution of the converter will clock zeros from the data output if CS remains in a low state. A B 908 *NM If a resolution of less than 12 bits is required, the data access can be terminated by releasing CS after the required number of bits have been read. t2 1808 3608 NUMBER OF DEGREES REFERS TO WIDTH RELATIVE TO "A" CYCLE t6 *SELECTABLE WITH THREE - LEVEL CONTROL PIN "MARKER" DEFAULT TO 908 USING INTERNAL PULL - UP. CSB t3 908 1808 3608 Figure 7. A, B and NM Timing t4 t* MSB t1 WIDTH +VDD 0 –VSS Unlike incremental encoders, the AD2S90 encoder output is not subject to error specifications such as cycle error, eccentricity, pulse and state width errors, count density and phase φ. SCLK DATA LEVEL t5 The maximum speed rating, n, of an encoder is calculated from its maximum switching frequency, fMAX, and its ppr (pulses per revolution). LSB t7 *THE MINIMUM ACCESS TIME: USER DEPENDENT n= Figure 6. Serial Read Cycle CS can be released a minimum of 100 ns after the last negative edge. If the user is reading data continuously, CS can be reapplied a minimum of 250 ns after it is released (see Figure 6). 60 × f MAX PPR The AD2S90 A, B pulses are initiated from CLKOUT which has a maximum frequency of 2.048 MHz. The equivalent encoder switching frequency is: 1/4 × 2.048 MHz = 512 kHz (4 updates = 1 pulse) The maximum read time is given by: (12-bits read @ 2 MHz) Max RD Time = [600 + (12 × 500) + 600 + 100] = 7.30 µs. At 12 bits the ppr = 1024, therefore the maximum speed, n, of the AD2S90 is: INCREMENTAL ENCODER OUTPUTS The incremental encoder emulation outputs A, B and NM are free running and are always valid, providing that valid resolver format input signals are applied to the converter. n= 60 × 512000 = 30000 rpm 1024 This compares favorably with encoder specifications where fMAX is specified from 20 kHz (photo diodes) to 125 kHz (laser based) depending on the light system used. A 1024 line laser-based encoder will have a maximum speed of 7300 rpm. The AD2S90 emulates a 1024-line encoder. Relating this to converter resolution means one revolution produces 1024 A, B pulses. B leads A for increasing angular rotation (i.e., clockwise direction). The addition of the DIR output negates the need for external A and B direction decode logic. DIR is HI for increasing angular rotation. The inclusion of A, B outputs allows the AD2S90 + resolver solution to replace optical encoders directly without the need to change or upgrade existing application software. –6– REV. D AD2S90 VELOCITY OUTPUT The analog velocity output VEL is scaled to produce 150 rps/V dc ± 15%. The sense is positive V dc for increasing angular rotation. VEL can drive a maximum load combination of 10 kΩ and 30 pF. The internal velocity scaling is fixed. unless all parts of the system are backed up, a reset to a known datum point needs to take place. This can be extremely hazardous in many applications. The AD2S90 gets round this problem by supplying an absolute position serial data stream upon request, thus removing the need to reset to a known datum. POSITION CONTROL HOST I/O PORT TO HOST PROCESSOR The rotor movement of dc or ac motors used for servo control is monitored at all times. Feedback transducers used for this purpose detect either relative position in the case of an incremental encoder or absolute position and velocity using a resolver. An incremental encoder only measures change in position not actual position. COMMAND POSITION SEQUENCER (32-BIT) – ACTUAL POSITION SERVO AMP SERVO MOTOR AD2S90 RESOLVER Figure 8. Position Loop MOTION CONTROL PROCESSES Advanced VLSI designs mean that silicon system blocks are now available to achieve high performance motion control in servo systems. A digital position control system using the AD2S90 is shown in Figure 9. In this system the task of determining the acceleration and velocity characteristics is fulfilled by programming a trapezoidal velocity profile via the I/O port. IN, A, B 8 – 12 DAC DC MOTOR OPTIONAL VELOCITY FEEDBACK INCREMENTAL POSITION AD2S90 ABSOLUTE POSITION RESOLVER Figure 9. Practical Implementation of the AD2S90 DSP Interfacing The AD2S90 serial output is ideally suited for interfacing to DSP configured microprocessors. Figures 10 to 13 illustrate how to configure the AD2S90 for serial interfacing to the DSP. Figure 10 shows the AD2S90 interfaced to an ADSP-2105. The on-chip serial port of the ADSP-2105 is used in alternate framing receive mode with internal framing (internally inverted) and internal serial clock generation (externally inverted) options selected. In this mode the ADSP-2105 provides a CS and a serial clock to the AD2S90. The serial clock is inverted to prevent timing errors as a result of both the AD2S90 and ADSP2105 clock data on the negative edge of SCLK. The first data bit is void; 12 bits of significant data then follow on each consecutive negative edge of the clock. Data is clocked from the AD2S90 into the data receive register of the ADSP-2105. This is internally set to 13 bit (12 bits and one “dummy” bit) when 13 bits are received. The serial port automatically generates an internal processor interrupt. This allows the ADSP-2105 to read 12 significant bits at once and continue processing. The ADSP-2101, ADSP-2102, ADSP-2111 and 21msp50 can all interface to the AD2S90 with similar interface circuitry. As can be seen from Figure 9 encoder position feedback information is used. This is a popular format and one which the AD2S90 emulates thereby facilitating the replacement of encoders with an AD2S90 and a resolver. However, major benefits can be realized by adopting the resolver principle as opposed to the incremental technique. Incremental feedback based systems normally carry out a periodic check between the position demanded by the controller and the increment position count. This requires software and hardware comparisons and battery backup in the case of power failure. If there is a supply failure and the drive system moves, REV. D DIGITAL PID DAC FILTER PORT (16-BIT) ADSP-2105 Interfacing POSITION CONTROLLER POSITION DEMAND S POSITION FEEDBACK PROCESSOR (32-BIT) The primary demand for a change in position must take into account the magnitude of that change and the associated acceleration and velocity characteristics of the servo system. This is necessary to avoid “hunting” due to over- or underdamping of the control employed. A simplified position loop is shown in Figure 8. POWER AMP + Closed Loop Control Systems A position loop needs both actual and demand position information. Algorithms consisting of proportional, integral and derivative control (PID) may be implemented to control the velocity profile. HOST INTERFACE SCLK ADSP-2105 RFS SCLK DR DATA AD2S90 CS NOTE: ADDITIONAL PINS OMITTED FOR CLARITY Figure 10. ADSP-2105/AD2S90 Serial Interface –7– AD2S90 Select the AD2S90 and frame the data. The S1 register is fixed at 16 bits, therefore, to obtain the 12-significant bits the processor needs to execute four right shifts. Once the NEC7720 has read 16 bits, an internal interrupt is generated to read the internal contents of the S1 register. TMS32020 Interfacing Figure 11 shows the serial interface between the AD2S90 and the TMS32020. The interface is configured in alternate internal framing, external clock (externally inverted) mode. Sixteen bits of data are clocked from the AD2S90 into the data receive register (DRR) of the TMS32020. The DRR is fixed at 16 bits. To obtain the 12-significant bits, the processor needs to execute three right shifts. (First bit read is void, the last three will be zeros). When 16 bits have been received by the TMS32020, it generates an internal interrupt to read the data from the DRR. SCLK AD2S90 SIEN S1 SCLK AD2S90 FSR CS DRR DATA CS DATA NOTE: ADDITIONAL PINS OMITTED FOR CLARITY SCLK TMS32020 SCLK mPD7720 Figure 13. µ PD7720/AD2S90 Serial Interface EDGE TRIGGERED 4ⴛ DECODING LOGIC In most data acquisition or control systems the A, B incremental outputs must be decoded into absolute information, normally a parallel word, before they can be utilized effectively. NOTE: ADDITIONAL PINS OMITTED FOR CLARITY Figure 11. TMS32020/AD2S90 Serial Interface To decode the A, B outputs on the AD2S90 the user must implement a 4× decoding architecture. The principle states that one A, B cycle represents 4 LSB weighted increments of the converter (see Equation 4). DSP56000 Interface Figure 12 shows a serial interface between the AD2S90 and the DSP56000. The DSP in configured for normal mode synchronous operation with gated clock with SCLK and SC1 as outputs. SC1 is applied to CS. Up = (↑A) • B + (↓B) • A + (↓A) • B + (↑Β) • A Down = (↑A) • B + (↑B) • A + (↓A) • B + (↓B) • A SCLK (4) SCLK DSP56000 AD2S90 SC1 CS SRD DATA CLOCKWISE ROTATION COUNTER CLOCKWISE ROTATION UP DOWN CH A CH B NOTE: ADDITIONAL PINS OMITTED FOR CLARITY Figure 12. DSP56000/AD2S90 Serial Interface The DSP56000 assumes valid data on the first falling edge of SCLK. SCLK is inverted to ensure that the valid data is clocked in after one leading bit. The receive data shift register (SRD) is set for a 13-bit word. Figure 14. Principles of 4× Decoding The algorithms in Equation 4 can be implemented using the architecture shown in Figure 15. Traditionally the direction of the shaft is decoded by determining whether A leads B. The AD2S90 removes the need to derive direction by supplying a direction output state which can be fed straight into the updown counter. When this register has received 13 bits of data, it generates an internal interrupt on the DSP56000 to read the 12 bits of significant data from the register. NEC7720 Interface Figure 13 shows the serial interface between the NEC7720 and the AD2S90. The NEC7720 expects data on the rising edge of its SCLK output, and therefore unlike the previous interfaces no inverter is required to clock data into the S1 register. There is no need to ignore the first data bit read. SIEN is used to Chip CHA EDGE GENERATOR CHB For further information on this topic please refer to the application note “Circuit Applications of the AD2S90 Resolver-toDigital Converters.” A A B B CLOCK DIRECTION U/D UP/DOWN COUNTER PARALLEL DIGITAL OUTPUT RESET Figure 15. 4× Decoding Incremental to Parallel Conversion –8– REV. D AD2S90 REMOTE MULTIPLE SENSOR INTERFACING The AD2S90 acceleration constant is given by: The DATA output of the AD2S90 is held in a high impedance state until CS is taken LO. This allows a user to operate the AD2S90 in an application with more than one converter connected on the same line. Figure 16 shows four resolvers interfaced to four AD2S90s. Excitation for the resolvers is provided locally by an oscillator. K a = K1 × K 2 ≅ 3.0 × 106 sec −2 The AD2S90’s design has been optimized with a critically damped response. The closed-loop transfer function is given by: θOUT = θ IN SCLK, DATA and two address lines are fed down low loss cables suitable for communication links. The two address lines are decoded locally into CS for the individual converters. Data is received and transmitted using transmitters and receivers. A0 2-4 DECODING (74HC139) 4 RES1 4 RES2 1+ st1 s2 s 3t2 1+ st1 + + K1K 2 K1K 2 (9) The normalized gain and phase diagrams are given in Figures 18 and 19. 5 A1 CS1 CS2 CS3 CS4 AD2S90 1 (8) 0 –5 AD2S90 2 SCLK –10 4 RES3 4 RES4 DATA AD2S90 3 –15 –20 AD2S90 4 VDD 2 2 –25 VSS OSC –30 0V BUFFER –35 Figure 16. Remote Sensor Interfacing –40 –45 CIRCUIT DYNAMICS/ERROR SOURCES Transfer Function The AD2S90 operates as a Type 2 tracking servo loop. An integrator and VCO/counter perform the two integrations inherent in a Type 2 loop. 100 FREQUENCY – Hz 1k 10k 0 –20 –40 –60 –80 VEL OUT A1 (S) 10 Figure 18. AD2S90 Gain Plot The overall system response of the AD2S90 is that of a unity gain second order low-pass filter, with the angle of the resolver as the input and the digital position data as the output. Figure 17 illustrates the AD2S90 system diagram. u IN 1 A2 (S) u OUT –100 –120 –140 Figure 17. AD2S90 Transfer Function –160 The open-loop transfer function is given by: –180 K K (1 + st1 ) θOUT = 12 2 1 + st2 θ IN s 1 (5) A2(s) = REV. D K2 s K1 1+ st1 s 1+ st2 t1 = 1.0 ms t2 = 90 µs K1 = 4.875V /(LSB × sec) K 2 = 614, 400 LSB /(V × sec) 100 FREQUENCY – Hz 1k Figure 19. AD2S90 Phase Plot where: A1(s) = 10 (6) (7) –9– 10k AD2S90 The small step response is given in Figure 20, and is the time taken for the converter to settle to within 1 LSB. ts = 7.00 ms (maximum) The large step response (steps >20°) applies when the error voltage will exceed the linear range of the converter. Typically it will take three times longer to reach the first peak for a 179° step. In response to a velocity step [VELOUT/(dθ/dt)] the velocity output will exhibit the same response characteristics as outlined above. SOURCES OF ERROR Acceleration Error A tracking converter employing a Type 2 servo loop does not suffer any velocity lag, however, there is an additional error due to acceleration. This additional error can be defined using the acceleration constant Ka of the converter. Ka = Input Acceleration Error in Output Angle (10) The numerator and denominator’s units must be consistent. Ka does not define maximum input acceleration, only the error due to its acceleration. The maximum acceleration allowable before the converter loses track is dependent on the angular accuracy requirements of the system. Angular Error × Ka = degrees/sec2 108 (11) DEGREES Ka can be used to predict the output position error for a given input acceleration. The AD2S90 has a fixed Ka = 3.0 × 106 sec–2 if we apply an input accelerating at 100 revs/sec2, the error can be calculated as follows: Error in LSBs = 08 [ K [sec ] Input Acceleration LSB / sec 2 a 0 4 8 12 16 20 = Figure 20. Small Step Response –10– [ ] [ 100 rev / sec2 × 212 LSB / rev [ 3.0 × 10 sec 6 –2 ] −2 ] = 0.14 LSBs ] (12) REV. D AD2S90 AD2S90/AD2S99 TYPICAL CONFIGURATION Figure 21 shows a typical circuit configuration for the AD2S99 Oscillator and the AD2S90 Resolver-to-Digital Converter. The maximum level of the SIN and COS input signals to the AD2S90 should be 2 V rms ± 10%. All the analog ground signals should be star connected to the AD2S90 AGND pin. If shielded twisted pair cables are used for the resolver signals, the shields should also be terminated at the AD2S90 AGND pin. The SYNREF output of the AD2S99 should be connected to the REF input pin of the AD2S90 via a 0.1 µF capacitor with a 100 kΩ resistor to GND. This is to block out any dc offset in the SYNREF signal. For more detailed information please refer to the AD2S99 data sheet. VSS 0.1mF 1 VSS VSS FBIAS NC 4 SIN 5 DGND 6 COS 7 SEL2 2 3 NC = NO CONNECT 20 19 18 AD2S99 17 TOP VIEW (Not to Scale) 16 EXC EXC AGND 15 NC NC 8 14 NC NC VDD 10 11 12 13 LOS 9 NC SYNREF SEL2 = GND SEL1 = VSS FOUT = 5kHz SEL1 4.7mF 50kV VDD 4.7mF 0.1mF 0.1mF 100kV S2 R2 COS S4 S3 REF 19 18 17 16 15 14 REF VDD 13 COS LO 20 COS 1 AGND 2 SIN 3 SIN LO SIN 4 R4 VSS 12 RESOLVER 5 DGND 11 AD2S90 10 TOP VIEW (Not to Scale) 9 6 7 8 S1 Figure 21. AD2S90 and AD2S99 Example Configuration REV. D –11– VDD 4.7mF 0.1mF 4.7mF 0.1mF VSS AD2S90 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). P-20A 20-Lead Plastic Leaded Chip Carrier (PLCC) 0.048 (1.21) 0.042 (1.07) 0.056 (1.42) 0.042 (1.07) 19 18 PIN 1 IDENTIFIER TOP VIEW (PINS DOWN) 8 9 0.020 (0.50) R 0.025 (0.63) 0.015 (0.38) 3 4 C1653b–2–1/99 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 0.050 (1.27) BSC 14 13 0.040 (1.01) 0.025 (0.64) 0.356 (9.04) SQ 0.350 (8.89) 0.395 (10.02) SQ 0.385 (9.78) 0.110 (2.79) 0.085 (2.16) 0.020 (0.50) R PIN 1 IDENTIFIER BOTTOM VIEW PRINTED IN U.S.A. (PINS UP) –12– REV. D