Single Supply, 24-Bit, Sigma-Delta ADC with ±10 V
and 0 mA to 20 mA Inputs, Open Wire Detection
AD4111
Data Sheet
FEATURES
GENERAL DESCRIPTION
Tested for robustness per: IEC6100-4-2, IEC6100-4-3,
IEC6100-4-4, IEC6100-4-5, IEC6100-4-6, CISPR 11
24-bit ADC with integrated analog front end
Fast and flexible output rate: 1.25 SPS to 31.25 kSPS
Channel scan data rate of 6.21 kSPS per channel
(161 µs settling)
16 noise free bits at 1 kSPS per channel
85 dB rejection of 50 Hz and 60 Hz at 20 SPS per channel
±10 V inputs, 4 differential or 8 single-ended
Pin absolute maximum rating ±50 V
Absolute input pin voltage up to ±20 V
≥1 MΩ impedance
±0.06% accuracy at 25°C
Open wire detection
0 mA to 20 mA inputs, 4 single-ended
Pin absolute maximum rating ±50 mA
Input range from −0.5 mA to +24 mA
60 Ω impedance
±0.08% accuracy at 25°C
On-chip 2.5 V reference
±0.12% accuracy at 25°C, ±5 ppm/°C (typical) drift
Internal or external clock
Power supplies
AVDD = 3.0 V to 5.5 V
IOVDD = 2 V to 5.5 V
Total IDD = 3.9 mA
Temperature range: −40°C to +105°C
3-wire or 4-wire serial digital interface (Schmitt trigger on SCLK)
SPI, QSPI, MICROWIRE, and DSP compatible
The AD41111 is a low power, low noise, 24-bit, sigma-delta (Σ-Δ)
analog-to-digital converter (ADC) that integrates an analog
front end (AFE) for fully differential or single-ended, high
impedance (≥1 MΩ) bipolar, ±10 V voltage inputs, and 0 mA
to 20 mA current inputs.
APPLICATIONS
Process control
PLC and DCS modules
Instrumentation and measurement
The AD4111 also integrates key analog and digital signal
conditioning blocks to configure eight individual setups for
each analog input channel in use. The AD4111 features a
maximum channel scan rate of 6.21 kSPS (161 µs) for fully
settled data.
The embedded 2.5 V, low drift (5 ppm/°C), band gap internal
reference (with output reference buffer) reduces the external
component count.
The digital filter allows flexible settings, including simultaneous
50 Hz and 60 Hz rejection at a 27.27 SPS output data rate. The
user can select between the different filter settings depending on
the demands of each channel in the application. The automatic
channel sequencer enables the ADC to switch through each
enabled channel.
The precision performance of the AD4111 is achieved by
integrating the proprietary iPassives™ technology from Analog
Devices, Inc. The AD4111 is factory calibrated to achieve a high
degree of specified accuracy.
The AD4111 also has the unique feature of open wire detection on
the voltage inputs for system level diagnostics using a single 5 V or
3.3 V power supply.
The AD4111 operates with a single power supply, making it easy
to use in galvanically isolated applications. The specified
operating temperature range is −40°C to +105°C. The AD4111
is housed in a 40-lead, 6 mm × 6 mm LFCSP package.
Protected by U.S. Patent 10,852,360.
1
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2018–2021 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD4111
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
CRC Calculation......................................................................... 40
Applications ...................................................................................... 1
Integrated Functions ...................................................................... 42
General Description ......................................................................... 1
General-Purpose Outputs ......................................................... 42
Revision History ............................................................................... 3
Delay ............................................................................................ 42
Functional Block Diagram .............................................................. 4
16-Bit/24-Bit Conversions ........................................................ 42
Specifications .................................................................................... 5
DOUT_RESET ........................................................................... 42
Timing Characteristics ................................................................ 8
Synchronization ......................................................................... 42
Absolute Maximum Ratings ......................................................... 10
Error Flags ................................................................................... 43
Thermal Resistance .................................................................... 10
DATA_STAT .............................................................................. 43
ESD Caution................................................................................ 10
IOSTRENGTH ........................................................................... 43
Pin Configuration and Function Descriptions .......................... 11
Internal Temperature Sensor ................................................... 43
Typical Performance Characteristics ........................................... 13
Applications Information ............................................................. 44
Noise Performance and Resolution ............................................. 18
IEC61000-4-x and CISPR 11 Robustness ............................... 44
Theory of Operation ...................................................................... 20
Grounding and Layout .............................................................. 44
Power Supplies ............................................................................ 21
Register Summary .......................................................................... 45
Digital Communication ............................................................ 21
Register Details ............................................................................... 47
AD4111 Reset.............................................................................. 22
Communications Register ........................................................ 47
Configuration Overview............................................................ 23
Status Register............................................................................. 48
Circuit Description......................................................................... 26
ADC Mode Register ................................................................... 49
Multiplexer .................................................................................. 26
Interface Mode Register ............................................................ 50
Current Inputs ............................................................................ 27
Register Check ............................................................................ 51
Voltage Inputs............................................................................. 27
Data Register ............................................................................... 51
Data Output Coding .................................................................. 29
GPIO Configuration Register ................................................... 52
AD4111 Reference...................................................................... 29
ID Register .................................................................................. 53
Buffered Reference Input .......................................................... 30
Channel Register 0 ..................................................................... 53
Clock Source ............................................................................... 30
Channel Register 1 to Channel Register 15 ............................ 54
Digital Filter .................................................................................... 31
Setup Configuration Register 0 ................................................ 55
Sinc5 + Sinc1 Filter .................................................................... 31
Sinc3 Filter................................................................................... 31
Setup Configuration Register 1 to Setup Configuration
Register 7 ..................................................................................... 55
Single Cycle Settling ................................................................... 32
Filter Configuration Register 0 ................................................ 56
Enhanced 50 Hz and 60 Hz Rejection Filters ......................... 32
Filter Configuration Register 1 to Filter Configuration
Register 7 ..................................................................................... 57
Operating Modes ............................................................................ 35
Continuous Conversion Mode ................................................. 35
Continuous Read Mode ............................................................ 36
Single Conversion Mode ........................................................... 37
Standby and Power-Down Modes ........................................... 38
Calibration................................................................................... 38
Digital Interface .............................................................................. 39
Offset Register 0 ......................................................................... 57
Offset Register 1 to Offset Register 7 ....................................... 57
Gain Register 0 ........................................................................... 58
Gain Register 1 to Gain Register 7 ........................................... 58
Outline Dimensions ....................................................................... 59
Ordering Guide .......................................................................... 59
Checksum Protection ................................................................ 39
Rev. B | Page 2 of 59
Data Sheet
AD4111
REVISION HISTORY
3/2021—Rev. A to Rev. B
Changes to Features Section ............................................................ 1
Added Patent Note, Note 1 .............................................................. 1
Changes to Table 6 and Table 7 ....................................................18
Changes to Table 8 and Table 9 ....................................................19
Changes to Table 36 ........................................................................56
2/2019—Rev. 0 to Rev. A
Change to Product Title ................................................................... 1
Changes to Features Section and Applications Section ............... 1
Changes to Table 1 ............................................................................ 5
Changes to Figure 10 .....................................................................13
Changed 180 pF to 680 pF .............................................................28
Added IEC61000-4-x and CISPR 11 Robustness Section .........44
8/2018—Revision 0: Initial Version
Rev. B | Page 3 of 59
AD4111
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
AVDD
COMPA
COMPB
REGCAPA
REF–
REF+
IOVDD
BUFFERED
PRECISION
REFERENCE
OPEN WIRE
DETECTION
1.8V
LDO
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VINCOM
REFOUT
REGCAPD
1.8V
LDO
INT
REF
PRECISION
VOLTAGE
DIVIDER
RAIL TO RAIL
REFERENCE
INPUT BUFFERS
CS
SCLK
Σ-Δ ADC
MUX
VBIAS–
DIGITAL
FILTER
SERIAL
INTERFACE
DIN
DOUT/RDY
IIN3+
IIN2+
IIN1+
IIN0+
SYNC
ERROR
50Ω
AD4111
GPO CONTROL
TEMPERATURE
SENSOR
AVSS
GPO0
Figure 1.
Rev. B | Page 4 of 59
GPO1
XTAL AND INTERNAL
CLOCK OSCILLATOR
CIRCUITRY
XTAL1
XTAL2/CLKIO
16640-001
IIN0–
IIN1–
IIN2–
IIN3–
Data Sheet
AD4111
SPECIFICATIONS
AVDD = 3.0 V to 5.5 V, IOVDD = 2 V to 5.5 V, AVSS = 0 V, DGND = 0 V, VBIAS− = 0 V, REF+ = 2.5 V, REF− = AVSS, internal master
clock (MCLK) = 2 MHz, TA = TMIN to TMAX (−40°C to +105°C), unless otherwise noted.
Table 1.
Parameter
VOLTAGE INPUTS
Differential Input Voltage Range 1
Absolute (Pin) Input Voltage
Input Impedance
Offset Error 2
Offset Drift
Gain Error
Gain Drift
Integral Nonlinearity (INL)
Total Unadjusted Error (TUE) 4
Power Supply Rejection
Common-Mode Rejection
At DC
At 50 Hz, 60 Hz
Normal Mode Rejection4
Resolution
Noise
CURRENT INPUTS
Input Current Range
Absolute (Pin) Input Voltage
Input Impedance 6
Offset Error2
Offset Drift
Gain Error
Gain Drift
INL
TUE4
Power Supply Rejection
Normal Mode Rejection4
Resolution
Noise
ADC SPEED AND PERFORMANCE
ADC Output Data Rate (ODR)
No Missing Codes4
Test Conditions/Comments
Min
Specified performance
Functional
AVDD ≥ 4.75 V
AVDD = 3.0 V
−10
−VREF × 10
−20
−12
1
25°C
Internal full-scale calibration
25°C, internal VREF
−40°C to +105°C, internal VREF
25°C, external VREF
−40°C to +105°C, external VREF
AVDD for VIN = 1 V
VIN = 1 V
71
85
−0.5
AVSS − 0.05
54
Factory calibrated gain, 25°C
25°C, internal VREF
−40°C to +105°C, internal VREF
25°C, external VREF
−40°C to +105°C, external VREF
AVDD for IIN = 10 mA
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
Internal clock, 20 SPS ODR (postfilter)
External clock, 20 SPS ODR (postfilter)
See Table 7 and Table 9
See Table 7 and Table 9
One channel, see Table 6
Excluding sinc3 filter ≥ 15 kHz notch
Rev. B | Page 5 of 59
Max
Unit
+10
+VREF × 10
+20
+12
V
V
V
V
MΩ
mV
µV/°C
% of FS
ppm/°C
% of FSR
±0.06
±0.1
±0.06
±0.08
70
% of FSR
% of FSR
% of FSR
% of FSR
dB
85
120
dB
dB
90
90
dB
dB
±1.5
±7
±0.05
±1
±0.01
Internal full-scale calibration 3, 25°C
20 Hz output data rate (postfilter), 50 Hz ±
1 Hz and 60 Hz ± 1 Hz
50 Hz ± 1 Hz and 60 Hz ± 1 Hz
Internal clock, 20 SPS ODR (postfilter)
External clock, 20 SPS ODR (postfilter)
See Table 6 and Table 8
See Table 6 and Table 8
Typ
0.5
mA
V
Ω
µA
nA/°C
% of FS
ppm/°C
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
µA/V
90
90
dB
dB
60
±2
±3
±0.02
±10
±0.01
+24
AVDD + 0.05 5
75
±0.08
±0.2
±0.08
±0.2
71
85
1.25
24
31,250
SPS
Bits
AD4111
Parameter
INTERNAL REFERENCE
Output Voltage
Initial Accuracy4, 7
Temperature Coefficient
Reference Load Current, ILOAD
Power Supply Rejection
Load Regulation
Voltage Noise
Voltage Noise Density
Turn On Settling Time
Short-Circuit Current, ISC
EXTERNAL REFERENCE INPUTS
Differential Input Range
Absolute Voltage Limits
Buffers Disabled
Buffers Enabled
REF± Input Current
Buffers Disabled
Input Current
Input Current Drift
Buffers Enabled
Input Current
Input Current Drift
Normal Mode Rejection
Common-Mode Rejection
TEMPERATURE SENSOR
Accuracy
Sensitivity
GENERAL-PURPOSE OUTPUTS
(GPO0, GPO1)
Floating State Output Capacitance
Output Voltage4
High, VOH
Low, VOL
CLOCK
Internal Clock
Frequency
Accuracy
Duty Cycle
Output Voltage
Low, VOL
High, VOH
Crystal
Frequency
Start-Up Time
External Clock (CLKIO)
Duty Cycle
Data Sheet
Test Conditions/Comments
100 nF external capacitor to AVSS
REFOUT with respect to AVSS
REFOUT, TA = 25°C
Min
Typ
2.5
−0.12
±5
−10
AVDD (line regulation)
∆VOUT/∆ILOAD
eN, 0.1 Hz to 10 Hz, 2.5 V reference
eN, 1 kHz, 2.5 V reference
100 nF REFOUT capacitor
VREF = (REF+) − (REF−)
Max
+0.12
+12
+10
95
32
4.5
215
200
25
1
2.5
AVSS −0.05
AVSS
External clock
Internal clock
Unit
V
% of V
ppm/°C
mA
dB
ppm/mA
µV rms
nV/√Hz
µs
mA
AVDD
V
AVDD +0.05
AVDD
V
V
±9
±0.75
±2
µA/V
nA/V/°C
nA/V/°C
±100
0.25
nA
nA/°C
95
dB
±2
477
°C
µV/K
5
pF
See the rejection parameter
After user calibration at 25°C
With respect to AVSS
Source current (ISOURCE) = 200 µA
Sink current (ISINK) = 800 µA
AVDD − 1
AVSS + 0.4
2
−2.5%
+2.5%
50
30
Rev. B | Page 6 of 59
16
10
2
50
MHz
%
%
0.4
V
V
16.384
MHz
µs
MHz
%
0.8 × IOVDD
14
V
V
2.048
70
Data Sheet
Parameter
LOGIC INPUTS
Input Voltage4
High, VINH
Low, VINL
Hysteresis4
Leakage Current
LOGIC OUTPUT (DOUT/RDY)
Output Voltage
High, VOH
Low, VOL
Leakage Current
Output Capacitance
POWER REQUIREMENTS
Power Supply Voltage
AVDD to AVSS
AVSS to DGND
IOVDD to DGND
IOVDD to AVSS
POWER SUPPLY CURRENTS 8
Full Operating Mode
AVDD Current
IOVDD Current
Standby Mode
Power-Down Mode
POWER DISSIPATION
Full Operating Mode
Standby Mode
Power-Down Mode
AD4111
Test Conditions/Comments
Min
2 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
2 V ≤ IOVDD < 2.3 V
2.3 V ≤ IOVDD ≤ 5.5 V
IOVDD ≥ 2.7 V
IOVDD < 2.7 V
0.65 × IOVDD
0.7 × IOVDD
IOVDD ≥ 4.5 V, ISOURCE = 1 mA
2.7 V ≤ IOVDD < 4.5 V, ISOURCE = 500 µA
IOVDD < 2.7 V, ISOURCE = 200 µA
IOVDD ≥ 4.5 V, ISINK = 2 mA
2.7 V ≤ IOVDD < 4.5 V, ISINK = 1 mA
IOVDD < 2.7 V, ISINK = 400 µA
Floating state
Floating state
0.8 × IOVDD
0.8 × IOVDD
0.8 × IOVDD
Typ
0.08
0.04
−10
Unit
0.35 × IOVDD
0.7
0.25
0.2
+10
V
V
V
V
V
V
µA
0.4
0.4
0.4
+10
−10
10
3.0
−2.75
2
For AVSS < DGND
All outputs unloaded, digital inputs
connected to IOVDD or DGND
Including internal reference
Internal clock
All VIN = 0 V
All VIN = 0 V
Max
3.3
0.6
120
90
19.5
600
450
V
V
V
V
V
V
µA
pF
5.5
0
5.5
6.35
V
V
V
V
3.7
0.8
mA
mA
µA
µA
mW
µW
µW
The full specification is guaranteed for a differential input signal of ±10 V. The device is functional up to a differential input signal of ±VREF × 10. However, the specified
absolute (pin) voltage must not be exceeded for the proper function.
2
Following a system zero-scale calibration, the offset error is in the order of the noise for the programmed output data rate selected.
3
The gain calibration register is overwritten by performing an internal full-scale calibration. Alternatively, a system full-scale calibration reduces the gain error to the
order of the noise for the programmed output data rate for the channel that is calibrated.
4
Specification is not production tested but is supported by characterization data at the initial product release.
5
This maximum specification is only possible if IINx− is biased so that the current through the resistor is less than 24 mA. It is not possible with IINx− connected to 0 V.
6
This specification shows the impedance seen between current input pins. The current is measured across a 50 Ω sense resistor.
7
This specification includes moisture sensitivity level (MSL) preconditioning effects.
8
This specification is with no load on the REFOUT pin and the digital output pins.
1
Rev. B | Page 7 of 59
AD4111
Data Sheet
TIMING CHARACTERISTICS
IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, capacitive load (CLOAD) = 20 pF, unless otherwise noted.
Table 2.
Parameter
SCLK
t3
t4
READ OPERATION
t1
t2 3
t5 5
t6
t7
WRITE OPERATION
t8
t9
t10
t11
Limit at TMIN, TMAX
Unit
Description 1, 2
25
25
ns min
ns min
SCLK high pulse width
SCLK low pulse width
0
15
40
0
12.5
25
2.5
20
0
10
ns min
ns max
ns max
ns min
ns max
ns max
ns min
ns max
ns min
ns min
CS falling edge to DOUT/RDY active time
IOVDD = 4.75 V to 5.5 V
IOVDD = 2 V to 3.6 V
SCLK active edge to data valid delay 4
IOVDD = 4.75 V to 5.5 V
IOVDD = 2 V to 3.6 V
Bus relinquish time after CS inactive edge
0
8
8
5
ns min
ns min
ns min
ns min
CS falling edge to SCLK active edge setup time4
Data valid to SCLK edge setup time
Data valid to SCLK edge hold time
CS rising edge to SCLK edge hold time
SCLK inactive edge to CS inactive edge
SCLK inactive edge to DOUT/RDY high/low
Sample tested during initial release to ensure compliance.
See Figure 2 and Figure 3.
3
This parameter is defined as the time required for the output to cross the VOL or VOH limits.
4
The SCLK active edge is the falling edge of SCLK.
5
DOUT/RDY returns high after a read of the data register. In single-conversion mode and continuous conversion mode, the same data can be read again, if required,
while DOUT/RDY is high. However, care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is
enabled, the digital word can be read only once.
1
2
Rev. B | Page 8 of 59
Data Sheet
AD4111
Timing Diagrams
CS (I)
t6
t1
t5
MSB
DOUT/RDY (O)
LSB
t7
t2
t3
16640-002
SCLK (I)
t4
I = INPUT, O = OUTPUT
Figure 2. Read Cycle Timing Diagram
CS (I)
t11
t8
SCLK (I)
t9
t10
MSB
LSB
I = INPUT, O = OUTPUT
Figure 3. Write Cycle Timing Diagram
Rev. B | Page 9 of 59
16640-003
DIN (I)
AD4111
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 3.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
AVDD to AVSS
AVDD to DGND
IOVDD to DGND
IOVDD to AVSS
AVSS to DGND
VINx to AVSS
IINx+ to AVSS
IINx− to AVSS
Current Input Current1
Reference Input Voltage to AVSS
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Digital Input Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Lead Soldering, Reflow Temperature
1
Rating
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−0.3 V to +7.5 V
−3.25 V to +0.3 V
−50 V to +50 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−50 mA to +50 mA
−0.3 V to AVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
10 mA
−40°C to +105°C
−65°C to +150°C
150°C
260°C
θJA is specified for a device soldered on a JEDEC test board for
surface-mount packages.
Table 4. Thermal Resistance
Package Type
CP-40-151
4-Layer JEDEC Board
1
θJA
Unit
34
°C/W
Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with 16 thermal vias. See JEDEC JESD51.
ESD CAUTION
The absolute maximum current input current, current input voltage, and
IINx− voltage must all be within the specified limits.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Rev. B | Page 10 of 59
Data Sheet
AD4111
40
39
38
37
36
35
34
33
32
31
REF+
REF–
GPO1
IIN3+
IIN2+
IIN1+
IIN0+
IIN0–
IIN1–
IIN2–
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
AD4111
TOP VIEW
(Not to Scale)
30
29
28
27
26
25
24
23
22
21
IIN3–
VIN7
VIN6
VIN5
VIN4
GPO0
COMPB
COMPA
REGCAPD
DGND
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT ANYTHING TO THIS PIN.
2. SOLDER THE EXPOSED PAD TO A SIMILAR PAD ON THE PCB UNDER THE
EXPOSED PAD TO CONFER MECHANICAL STRENGTH AND FOR HEAT
DISSIPATION. THE EXPOSED PAD MUST BE CONNECTED TO AVSS
THROUGH THIS PAD ON THE PCB.
16640-004
VBIAS–
XTAL1
XTAL2/CLKIO
DOUT/RDY
DIN
SCLK
CS
ERROR
SYNC
IOVDD
11
12
13
14
15
16
17
18
19
20
VINCOM
VIN0
VIN1
VIN2
VIN3
REFOUT
REGCAPA
AVSS
AVDD
DNC
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic 1
VINCOM
Type 2
AI
2
VIN0
AI
3
VIN1
AI
4
VIN2
AI
5
VIN3
AI
6
REFOUT
AO
7
REGCAPA
AO
8
9
10
11
AVSS
AVDD
DNC
VBIAS−
P
P
N/A
AI
12
13
XTAL1
XTAL2/CLKIO
AI
AI/DI
14
DOUT/RDY
DO
15
DIN
DI
Description
Voltage Input Common. Voltage inputs are referenced to this pin when configured as single-ended.
Connect this pin to analog ground.
Voltage Input 0. Input referenced to VINCOM in single-ended configuration, or a positive input of an
input pair with VIN1 in differential configuration.
Voltage Input 1. Input referenced to VINCOM in single-ended configuration, or a negative input of an
input pair with VIN0 in differential configuration.
Voltage Input 2. Input referenced to VINCOM in single-ended configuration, or a positive input of an
input pair with VIN3 in differential configuration.
Voltage Input 3. Input referenced to VINCOM in single-ended configuration, or a negative input of an
input pair with VIN2 in differential configuration.
Buffered Output of Internal Reference. The output is 2.5 V with respect to AVSS. Decouple this pin to
AVSS using a 0.1 µF capacitor.
Analog Low Dropout (LDO) Regulator Output. Decouple this pin to AVSS using a 1 µF capacitor and a
0.1 µF capacitor.
Negative Analog Supply. This supply ranges from −2.75 V to 0 V and is nominally set to 0 V.
Analog Supply Voltage. This voltage ranges from 3.0 V to 5.5 V with respect to AVSS.
Do Not Connect. Do not connect anything to this pin.
Voltage Bias Negative. The pin is setting bias voltage for the voltage input analog front-end. Connect
this pin to AVSS.
Input 1 for Crystal.
Input 2 for Crystal/Clock Input or Output. See the CLOCKSEL bit settings in the ADCMODE register for
more information.
Serial Data Output/Data Ready Output. This pin serves a dual purpose. It functions as a serial data
output pin to access the output shift register of the ADC. The output shift register can contain data
from any of the on-chip data or control registers. The data-word/control word information is placed on
the DOUT/RDY pin on the SCLK falling edge and is valid on the SCLK rising edge. When CS is high, the
DOUT/RDY output is tristated. When CS is low, and a register is not being read, DOUT/RDY operates as
a data ready pin, going low to indicate the completion of a conversion. If the data is not read after the
conversion, the pin goes high before the next update occurs. The DOUT/RDY falling edge can be used
as an interrupt to a processor, indicating that valid data is available.
Serial Data Input to the Input Shift Register on the ADC. Data in this shift register is transferred to the
control registers in the ADC, with the register address (RA) bits of the communications register
identifying the appropriate register. Data is clocked in on the rising edge of SCLK.
Rev. B | Page 11 of 59
AD4111
Data Sheet
Pin No.
16
Mnemonic 1
SCLK
Type 2
DI
17
CS
DI
18
ERROR
DI/O
19
SYNC
DI
20
IOVDD
P
21
22
DGND
REGCAPD
P
AO
23
COMPA
AO
24
COMPB
AO
25
26
GPO0
VIN4
DO
AI
27
VIN5
AI
28
VIN6
AI
29
VIN7
AI
30
31
32
33
34
35
36
37
38
39
IIN3−
IIN2−
IIN1−
IIN0−
IIN0+
IIN1+
IIN2+
IIN3+
GPO1
REF−
AI
AI
AI
AI
AI
AI
AI
AI
DO
AI
40
REF+
AI
EP
P
1
2
Description
Serial Clock Input. This serial clock input is for data transfers to and from the ADC. SCLK has a Schmitt
triggered input.
Chip Select Input. This pin is an active low logic input used to select the ADC. Use CS to select the ADC
in systems with more than one device on the serial bus. CS can be hardwired low, allowing the ADC to
operate in 3-wire mode with SCLK, DIN, and DOUT/RDY used to interface with the device. When CS is
high, the DOUT/RDY output is tristated.
Error Input/Output or General-Purpose Output. This pin can be used in one of the following three modes:
Active low error input mode. This mode sets the ADC_ERROR bit in the status register.
Active low, open-drain error output mode. The status register error bits are mapped to the ERROR pin.
The ERROR pins of multiple devices can be wired together to a common pull-up resistor so that an error
on any device can be observed.
General-purpose output mode. The status of the pin is controlled by the ERR_DAT bit in the GPIOCON
register. The pin is referenced between IOVDD and DGND.
Synchronization Input. Allows synchronization of the digital filters and analog modulators when using
multiple AD4111 devices.
Digital I/O Supply Voltage. The IOVDD voltage ranges from 2 V to 5.5 V (nominal). IOVDD is
independent of AVDD. For example, IOVDD can be operated at 3.3 V when AVDD equals 5 V, or vice
versa. If AVSS is set to −2.5 V, the voltage on IOVDD must not exceed 3.6 V.
Digital Ground.
Digital LDO Regulator Output. This pin is for decoupling purposes only. Decouple this pin to DGND
using a 1 µF capacitor.
Compensation Pin for VIN0, VIN2, VIN4, and VIN6. Connect this pin to the corresponding voltage input
pins through a 1 kΩ resistor and 680 pF capacitor when using open wire detection (see the Open Wire
Detection section).
Compensation Pin for VIN1, VIN3, VIN5, and VIN7. Connect this pin to the corresponding voltage input
pins through a 1 kΩ resistor and 680 pF capacitor when using open wire detection (see the Open Wire
Detection section).
General-Purpose Output. Logic output on this this pin is referred to the AVDD and AVSS supplies.
Voltage Input 4. Input referenced to VINCOM in single-ended configuration, or a positive input of an
input pair with VIN5 in differential configuration.
Voltage Input 5. Input referenced to VINCOM in single-ended configuration, or a negative input of an
input pair with VIN4 in differential configuration.
Voltage Input 6. Input referenced to VINCOM in single-ended configuration, or a positive input of an
input pair with VIN7 in differential configuration.
Voltage Input 7. Input referenced to VINCOM in single-ended configuration, or a negative input of an
input pair with VIN6 in differential configuration.
Current Input Return 3. Connect this pin to analog ground.
Current Input Return 2. Connect this pin to analog ground.
Current Input Return 1. Connect this pin to analog ground.
Current Input Return 0. Connect this pin to analog ground.
Current Input 0.
Current Input 1.
Current Input 2.
Current Input 3.
General-Purpose Output. Logic output on this pin is referred to the AVDD and AVSS supplies.
Reference Input Negative Terminal. REF− can span from AVSS to AVDD − 1 V. Reference can be selected
through the REF_SELx bits in the setup configuration registers.
Reference Input Positive Terminal. An external reference can be applied between REF+ and REF−. REF+
can span from AVDD to AVSS + 1 V. Reference can be selected through the REF_SELx bits in the setup
configuration registers.
Exposed Pad. Solder the exposed pad to a similar pad on the PCB under the exposed pad to confer
mechanical strength to the package and for heat dissipation. The exposed pad must be connected to
AVSS through this pad on the PCB.
Note that, throughout this data sheet, the dual function pin mnemonics are referenced by the relevant function only.
AI means analog input, AO means analog output, P means power supply, N/A means not applicable, DI means digital input, DO means digital output, and DI/O means
bidirectional digital input/output.
Rev. B | Page 12 of 59
Data Sheet
AD4111
TYPICAL PERFORMANCE CHARACTERISTICS
8388628
300
8388627
250
8388626
OCCURRENCE
ADC CODE
8388625
8388624
8388623
8388622
200
150
100
8388621
16640-105
700
800
900
0
1000
SAMPLE NUMBER
8388627
600
8388626
500
8388625
400
8388624
300
8388623
200
8388622
100
8388621
0
8388620
8388619
16640-108
50
8388620
ADC CODE
Figure 5. Noise (Voltage Input, Output Data Rate = 1.25 SPS)
Figure 8. Histogram (Voltage Input, Output Data Rate = 1.25 SPS)
8388680
35
8388660
30
8388620
8388600
20
15
8388580
10
8388560
5
0
100
200
300
400
500
600
700
800
900
0
1000
8388559
8388563
8388567
8388571
8388575
8388579
8388583
8388587
8388591
8388595
8388599
8388603
8388607
8388611
8388615
8388619
8388623
8388627
8388631
8388635
8388639
8388643
8388647
8388651
8388655
8388659
8388663
8388540
16640-109
OCCURRENCE
25
16640-106
ADC CODE
8388640
SAMPLE NUMBER
ADC CODE
Figure 9. Histogram (Voltage Input, Output Data Rate = 2.5 kSPS)
Figure 6. Noise (Voltage Input, Output Data Rate = 2.5 kSPS)
20
8388750
18
8388700
16
14
OCCURRENCE
8388600
8388550
12
10
8
6
4
8388500
0
100
200
300
400
500
600
700
800
900
0
8388511
8388520
8388529
8388538
8388547
8388556
8388565
8388574
8388583
8388592
8388601
8388610
8388619
8388628
8388637
8388646
8388655
8388664
8388673
8388682
8388691
8388700
8388709
8388718
8388727
8388450
16640-110
2
16640-107
ADC CODE
8388650
1000
SAMPLE NUMBER
ADC CODE
Figure 7. Noise (Voltage Input, Output Data Rate = 31.25 kSPS)
Figure 10. Histogram (Voltage Input, Output Data Rate = 31.25 kSPS)
Rev. B | Page 13 of 59
AD4111
Data Sheet
1000
8388382.5
900
8388382.0
800
700
OCCURRENCE
ADC CODE
8388381.5
8388381.0
8388380.5
600
500
400
300
16640-111
8388379.5
0
100
200
300
400
500
600
700
800
900
100
0
1000
8388380
SAMPLE NUMBER
8388381
8388382
ADC CODE
Figure 11. Noise (Current Input, Output Data Rate = 1.25 SPS)
Figure 14. Histogram (Current Input, Output Data Rate = 1.25 SPS)
8388440
60
8388420
50
8388400
40
OCCURRENCE
8388380
8388360
8388340
30
20
16640-112
10
0
100
200
300
400
500
600
700
800
900
0
1000
8388330
8388334
8388338
8388342
8388346
8388350
8388354
8388358
8388362
8388366
8388370
8388374
8388378
8388382
8388386
8388390
8388394
8388398
8388402
8388406
8388410
8388414
8388418
8388422
8388426
8388320
16640-115
ADC CODE
16640-114
200
8388380.0
SAMPLE NUMBER
ADC CODE
Figure 12. Noise (Current Input, Output Data Rate = 2.5 kSPS)
Figure 15. Histogram (Current Input, Output Data Rate = 31.25 SPS)
8388750
25
8388700
20
OCCURRENCE
8388600
8388550
15
10
0
100
200
300
400
500
600
700
800
900
0
1000
8388297
8388304
8388311
8388318
8388325
8388332
8388339
8388346
8388353
8388360
8388367
8388374
8388381
8388388
8388395
8388402
8388409
8388416
8388423
8388430
8388437
8388444
8388451
8388458
8388465
8388450
16640-116
5
8388500
16640-113
ADC CODE
8388650
SAMPLE NUMBER
ADC CODE
Figure 13. Noise (Current Input, Output Data Rate = 31.25 kSPS)
Figure 16. Histogram (Current Input, Output Data Rate = 31.25 kSPS)
Rev. B | Page 14 of 59
Data Sheet
AD4111
10
–70
8
–80
6
–90
4
INL (ppm OF FSR)
–60
–110
–120
2
0
–2
–4
–140
–6
16640-117
–130
–150
–160
20
10
30
–8
–10
–10
60
50
40
16640-120
CMRR (dB)
–100
–8
–6
–4
VIN FREQUENCY (Hz)
0
2
4
6
8
10
VIN (V)
Figure 17. Common-Mode Rejection Ratio (CMRR) vs. VIN Frequency
(VIN = 0.1 V, 10 Hz to 70 Hz, Output)
Figure 20. Integral Nonlinearity (INL) vs. Input Range (Voltage Input)
–50
35
–60
30
–70
25
OCCURRENCE
–80
–90
–100
20
15
10
16640-118
–110
–120
1
100
10
1k
10k
100k
1M
10M
5
16640-121
PSRR (dB)
–2
0
100M
1.996
VIN FREQUENCY (Hz)
1.997
1.998
1.999
2.000
2.001
2.002
2.003
FREQUENCY (MHz)
Figure 18. Power Supply Rejection Ratio (PSRR) vs. VIN Frequency
Figure 21. Internal Oscillator Frequency/Accuracy Distribution Histogram
10
2.01
8
2.00
6
FREQUENCY (MHz)
2
0
–2
–4
1.99
1.98
1.97
–6
4.5
14.5
9.5
19.5
1.95
–40 –30 –20 –10
24.5
IIN (mA)
16640-122
–8
–10
–0.5
1.96
16640-119
INL (ppm OF FSR)
4
0
10 20 30 40 50 60
TEMPERATURE (°C)
70 80 90 100
Figure 22. Internal Oscillator Frequency vs. Temperature
Figure 19. Integral Nonlinearity (INL) vs. Input (Current Input)
Rev. B | Page 15 of 59
AD4111
Data Sheet
35
900
800
30
700
OCCURRENCE
OCCURRENCE
25
600
500
400
20
15
300
10
200
0
–5
–4
–3
–2
–1
0
1
2
3
OFFSET ERROR (mV)
4
5
6
16640-126
5
16640-123
100
0
7
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
GAIN ERROR DRIFT (ppm/°C)
Figure 23. Offset Error Distribution Histogram (Voltage Input)
Figure 26. Gain Error Drift Distribution Histogram (Voltage Input)
30
25
25
20
OCCURRENCE
15
10
15
10
5
16640-124
5
0
4
5
6
7
8
9
10
16640-127
OCCURRENCE
20
0
11
–0.3
–0.2
–0.1
OFFSET ERROR DRIFT (µV/°C)
0
0.1
0.2
0.3
0.4
0.5
0.6
OFFSET ERROR (µA)
Figure 24. Offset Error Drift Distribution Histogram (Voltage Input)
Figure 27. Offset Error Distribution Histogram (Current Input)
35
20
18
30
16
OCCURRENCE
14
20
15
12
10
8
6
10
0
–0.055
–0.050
–0.045
–0.040
–0.035
–0.030
16640-128
4
5
16640-125
OCCURRENCE
25
2
0
–0.025
1.0 1.5
GAIN ERROR (% of Full-Scale)
2.0
2.5
3.0 3.5 4.0 4.5 5.0
OFFSET DRIFT (nA/°C)
5.5
6.0
6.5
Figure 28. Offset Error Drift Distribution Histogram (Current Input)
Figure 25. Gain Error Distribution Histogram (Voltage Input)
Rev. B | Page 16 of 59
Data Sheet
AD4111
20
30
18
25
16
OCCURRENCE
20
12
10
8
15
10
6
4
0
6
0.0250
0.0225
0.0200
0.0175
0.0150
0.0125
0.0100
0.0075
0
16640-130
16640-129
5
2
0.0050
OCCURRENCE
14
7
8
9
10
11
12
13
GAIN ERROR DRIFT (ppm/°C)
GAIN ERROR (% of Full-Scale)
Figure 30. Gain Error Drift Distribution Histogram (Current Input)
Figure 29. Gain Error Distribution Histogram (Current Input)
Rev. B | Page 17 of 59
AD4111
Data Sheet
NOISE PERFORMANCE AND RESOLUTION
Table 6 to Table 9 show the rms noise, peak-to-peak noise,
effective resolution, and the noise free (peak-to-peak)
resolution of the AD4111 for various ODRs. These values are
typical and are measured with an external 2.5 V reference and
with the ADC continuously converting on multiple channels.
The values in Table 6 and Table 8 are generated for the ±10 V
voltage input range, with a differential input voltage of 0 V.
The values in Table 7 and Table 9 are generated for the 0 mA
to 20 mA input range, with an input current of 0 mA. It is
important to note that the peak-to-peak resolution is calculated
based on the peak-to-peak noise. The peak-to-peak resolution
represents the resolution for which there is no code flicker.
Table 6. ±10 V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc5 + Sinc1 Filter
Default Output Data Rate
(SPS); SING_CYC = 0 and
Single Channel Enabled
31,250
15,625
10,417
5208
2597.4
1007
504
381
200.3
100.2
59.52
49.68
20.01
16.63
10
5
2.5
1.25
1
2
Output Data Rate (SPS per
Channel); SING_CYC = 1 or
Multiple Channels Enabled
6211.18
5181.65
4444
3115
2597.4
1007.1
504
381
200.3
100.2
59.52
49.68
20.01
16.63
10
5
2.5
1.25
Settling
Time 1
161 µs
193 µs
225 µs
321 µs
385 µs
993 µs
1.99 ms
2.63 ms
4.99 ms
9.99 ms
16.8 ms
20.13 ms
49.98 ms
60.13 ms
100 ms
200 ms
400 ms
800 ms
Notch
Frequency
(Hz)
31,250
15,625
10,417
5208
3906
1157
539
401
206
102
59.98
50
20.06
16.67
10
5
2.5
1.25
Noise
(µV rms) 2
106
94
82
62
47
27
21
17
13
8
7
7
4
4
3.7
3.4
2.4
2.3
Effective
Resolution
(Bits)
17.5
17.7
17.9
18.3
18.7
19.5
19.9
20.2
20.6
21.3
21.4
21.4
22.3
22.3
22.4
22.5
23
23.1
Noise
(µV p-p)
750
580
512
372
312
190
140
92
62
45
33
33
22
21
18
17
12
11
Peak-to-Peak
Resolution
(Bits)
14.7
15.1
15.3
15.7
16.0
16.7
17.1
17.7
18.3
18.8
19.2
19.2
19.8
19.9
20.1
20.2
20.7
20.8
The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
Based on 1000 samples for data rates ≥ 381 SPS per channel, based on 100 samples for data rates ≤ 200.3 SPS per channel.
Table 7. 0 mA to 20 mA Current Input Noise and Resolution vs. Output Data Rate Using a Sinc5 + Sinc1 Filter
Default Output Data Rate
(SPS); SING_CYC = 0 and
Single Channel Enabled
31,250
15,625
10,417
5208
2597.4
1007
504
381
200.3
100.2
59.52
49.68
20.01
16.63
10
5
2.5
1.25
1
2
Output Data Rate (SPS per
Channel); SING_CYC = 1 or
Multiple Channels Enabled
6211.18
5181.65
4444
3115
2597.4
1007.1
503.8
381
200.3
100.2
59.52
49.68
20.01
16.63
10
5
2.5
1.25
Settling
Time 1
161 µs
193 µs
225 µs
321 µs
385 µs
993 µs
1.99 ms
2.63 ms
4.99 ms
9.99 ms
16.8 ms
20.13 ms
49.98 ms
60.13 ms
100 ms
200 ms
400 ms
800 ms
Notch
Frequency
(Hz)
31,250
15,625
10,417
5208
3906
1157
539
401
206
102
59.98
50
20.06
16.67
10
5
2.5
1.25
Noise
(nA rms) 2
155
136
113
84
75
43
29
21
18
13
10
9
6
5.3
4.6
3
2.8
2.7
Effective
Resolution
(Bits)
17.0
17.2
17.4
17.9
18.0
18.8
19.4
19.9
20.1
20.6
20.9
21.1
21.7
21.8
22.1
22.7
22.8
22.8
Noise
(nA p-p)
1100
920
720
580
480
220
150
125
95
71
48
41
30
23
18
12
12
6
Peak-to-Peak
Resolution
(Bits)
14.2
14.4
14.8
15.1
15.3
16.5
17.0
17.3
17.7
18.1
18.7
18.9
19.3
19.7
20.1
20.7
20.7
21.7
The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
Based on 1000 samples for data rates ≥ 381 SPS per channel, based on 100 samples for data rates ≤ 200.3 SPS per channel.
Rev. B | Page 18 of 59
Data Sheet
AD4111
Table 8. ±10 V Voltage Input RMS Noise Resolution vs. ODR Using a Sinc3 Filter
Default Output Data Rate
(SPS); SING_CYC = 0 and
Single Channel Enabled
31,250
15,625
10,417
5208
2604.2
1008.1
504
401
200.3
100.16
59.98
50
20
16.67
10
5
2.5
1.25
1
2
Output Data Rate (SPS per
Channel); SING_CYC = 1 or
Multiple Channels Enabled
10309.28
5181.35
3460.21
1733
867.3
335.9
167.98
133.5
66.67
33.39
19.99
16.67
6.67
5.56
3.33
1.67
0.83
0.42
Settling
Time 1
97 µs
193 µs
289 µs
577 µs
1.15 ms
2.98 ms
5.95 ms
7.49 ms
14.99 ms
30.00 ms
50.02 ms
60 ms
149.95 ms
180.0 ms
300 ms
600 ms
1.2 sec
2.4 sec
Notch
Frequency
(Hz)
31,250
15,625
10,417
5208
2604.2
1008.1
504
401
200.3
100.2
59.98
50
20
16.67
10
5
2.5
1.25
Noise
(µV rms) 2
1035
158
77
50
34
22
15
13
10
7.3
6.2
5.3
4.9
4.2
3.7
3.5
3
2.9
Effective
Resolution
(Bits)
14.2
16.9
18
18.6
19.2
19.8
20.3
20.5
20.9
21.4
21.6
21.8
22
22.1
22.4
22.4
22.7
22.7
Noise
(µV p-p)
6037
954
536
334
205
137
108
82
65
39
35
36
33
29.8
20.9
17.8
17.8
14.9
Peak-to-Peak
Resolution
(Bits)
11.7
14.4
15.2
15.9
16.6
17.2
17.5
17.9
18.2
18.9
19.1
19.1
19.2
19.35
19.9
20.1
20.1
20.4
The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
Based on 1000 samples for data rates ≥ 381 SPS per channel, based on 100 samples for data rates ≤ 200.3 SPS per channel.
Table 9. 0 mA to 20 mA Current Input Noise and Resolution vs. Output Data Rate Using a Sinc3 Filter
Default Output Data Rate
(SPS); SING_CYC = 0 and
Single Channel Enabled
31,250
15,625
10,417
5208
2604.2
1008.1
504
401
200.3
100.16
59.98
50
20
16.67
10
5
2.5
1.25
1
2
Output Data Rate (SPS per
Channel); SING_CYC = 1 or
Multiple Channels Enabled
10309.28
5181.35
3460.21
1733
867.3
335.9
167.98
133.5
66.67
33.39
19.99
16.67
6.67
5.56
3.33
1.67
0.83
0.42
Settling
Time 1
97 µs
193 µs
289 µs
577 µs
1.15 ms
2.98 ms
5.95 ms
7.49 ms
14.99 ms
30.00 ms
50.02 ms
60 ms
149.95 ms
180.0 ms
300 ms
600 ms
1.2 sec
2.4 sec
Notch
Frequency
(Hz)
31,250
15,625
10,417
5208
2604.2
1008.1
504
401
200.3
100.2
59.98
50
20
16.67
10
5
2.5
1.25
Noise
(nA rms) 2
2177
309
121
72
49
30
22
19
14
10
7.6
7.2
4.8
4.4
3.8
3.1
2.6
2.4
Effective
Resolution
(Bits)
15.5
18.3
19.7
20.4
20.9
21.6
22.1
2.3
22.8
23.2
23.6
23.7
24
24
24
24
24
24
Noise
(nA p-p)
13315
1830
781
452
339
214
149
125
77
71
53
41
29.8
29.8
23.8
17.9
11.9
11.9
Peak-to-Peak
Resolution
(Bits)
12.9
15.8
17
17.8
18.2
18.8
19.4
19.6
20.3
20.4
20.8
21.2
21.7
21.7
22
22.4
23
23
The settling time is rounded to the nearest microsecond, which is reflected in the output data rate and channel switching rate. Channel switching rate = 1 ÷ settling time.
Based on 1000 samples for data rates ≥ 381 SPS per channel, based on 100 samples for data rates ≤ 200.3 SPS per channel.
Rev. B | Page 19 of 59
AD4111
Data Sheet
THEORY OF OPERATION
The AD4111 offers the user a fast settling, high resolution,
multiplexed ADC with high levels of configurability, including
the following features:
The AD4111 includes two separate linear regulator blocks for
both the analog and digital circuitry. The analog LDO regulator
regulates the AVDD supply to 1.8 V.
•
•
The linear regulator for the digital IOVDD supply performs a
similar function, regulating the input voltage applied at the
IOVDD pin to 1.8 V. The serial interface signals always operate
from the IOVDD supply seen at the pin; meaning that, if 3.3 V
is applied to the IOVDD pin, the interface logic inputs and
outputs operate at this level.
•
The AD4111 includes a precision, 2.5 V, low drift (5 ppm/°C),
band gap internal reference. This reference can be selected for
use in ADC conversions, reducing the external component
count. When enabled, the internal reference is output to the
REFOUT pin. It can be used as a low noise biasing voltage for
the external circuitry and must be connected to a 0.1 μF
decoupling capacitor.
The AD4111 is designed for a multitude of factory automation
and process control applications, such as programmable logic
controller (PLC) and distributed control system (DCS)
modules. The AD4111 reduces overall system cost and design
burden while maintaining a very high level of accuracy. The
AD4111 offers the following system benefits:
•
•
•
•
A single 5 V or 3.3 V power supply.
Guaranteed minimum 1 MΩ input impedance.
Overrange voltage greater than ±10 V.
Integrated sense resistors for direct current input
measurement.
Reduced calibration costs.
Voltage input open wire detection.
•
•
16MHz
CX2
CX1
23
COMPA
OPTIONAL EXTERNAL
CRYSTAL CIRCUITRY
CAPACITORS
XTAL1 12
XTAL2/CLKIO 13
2
VIN0
3
VIN1
DOUT/RDY
DOUT/RDY 14
DIN
DIN 15
SCLK
24
SCLK
16
COMPB
CS
CS 17
1
CLKIN
OPTIONAL
EXTERNAL
CLOCK
INPUT
VINCOM
IOVDD
IOVDD 20
AD4111
34
IIN0+
33
IIN0–
0.1µF
DGND 21
REGCAPD 22
0.1µF
1µF
AVDD
AVDD 9
0.1µF
REFOUT 6
11
0.1µF
VBIAS–
REGCAPA 7
AVSS
8
Figure 31. Typical Connection Diagram
Rev. B | Page 20 of 59
0.1µF
1µF
16640-010
•
•
Four fully differential or eight single-ended voltage inputs.
High impedance voltage divider with integrated precision
matched resistors
Four current inputs with integrated current sense resistors.
Embedded proprietary iPassives™ technology within a very
small device footprint.
Per channel configurability—up to eight different setups
can be defined. A separate setup can be mapped to each of
the channels. Each setup allows the user to configure whether
the buffers are enabled or disabled, gain and offset correction,
filter type, ODR, and reference source selection.
Data Sheet
AD4111
POWER SUPPLIES
The AD4111 has two independent power supply pins: AVDD,
and IOVDD. The AD4111 has no specific requirements for a
power supply sequence. However, when all power supplies are
stable, a device reset is required. See the AD4111 Reset section
for details on how to reset the device.
AVDD powers the internal 1.8 V analog LDO regulator, which
powers the ADC core. AVDD also powers the crosspoint multiplexer and integrated input buffers. AVDD is referenced to
AVSS, and AVDD − AVSS = 3.3 V or 5 V. AVDD and AVSS can
be a single 3.3 V or 5 V supply, or a ±1.65 V or ±2.5 V split
supply. When using split supplies, consider the absolute maximum
ratings (see the Absolute Maximum Ratings section).
IOVDD powers the internal 1.8 V digital LDO regulator. This
regulator powers the digital logic of the ADC. IOVDD sets the
voltage levels for the serial peripheral interface (SPI) of the
ADC. IOVDD is referenced to DGND, and IOVDD to DGND
can vary from 2 V (minimum) to 5.5 V (maximum).
Single-Supply Operation (AVSS = DGND)
When the AD4111 is powered from a single supply connected
to AVDD, the supply can be either 3.3 V or 5 V. In this configuration, AVSS and DGND can be shorted together on one
single ground plane.
determine the specific register to which the read or write
operation applies.
When the read or write operation to the selected register is
complete, the interface returns to its default state, where it
expects a write operation to the communications register.
In situations where interface synchronization is lost, a write
operation of at least 64 serial clock cycles with DIN high
returns the ADC to its default state by resetting the entire
device, including the register contents. Alternatively, if CS is
being used with the digital interface, returning CS high resets
the digital interface to its default state and aborts any current
operation.
Figure 33 and Figure 34 show writing to and reading from a
register by first writing the 8-bit command to the communications
register followed by the data for the addressed register.
Reading the ID register is the recommended method for verifying
correct communication with the device. The ID register is a read
only register and contains the value 0x30DX for the AD4111.
The communication register and ID register details are described
in Table 10 and Table 11.
8 BITS, 16 BITS,
OR 24 BITS OF DATA
CMD
DATA
CS
IOVDD can range from 2 V to 5.5 V in this unipolar input
configuration.
DIN
DIGITAL COMMUNICATION
SCLK
16640-012
The AD4111 has a 3-wire or 4-wire SPI interface that is
compatible with QSPI™, MICROWIRE®, and DSPs. The
interface operates in SPI Mode 3 and can be operated with CS
tied low. In SPI Mode 3, SCLK idles high, the falling edge of
SCLK is the drive edge, and the rising edge of SCLK is the
sample edge. Data is clocked out on the falling/drive edge and
data is clocked in on the rising/sample edge.
8-BIT COMMAND
Figure 33. Writing to a Register (8-Bit Command with Register Address
Followed by Data of 8 Bits, 16 Bits, or 24 Bits; Data Length Is Dependent on
the Register Selected)
8-BIT COMMAND
8 BITS, 16 BITS,
24 BITS, OR
32 BITS OUTPUT
CS
SAMPLE EDGE
Figure 32. SPI Mode 3 SCLK Edges
DIN
DOUT/RDY
Accessing the ADC Register Map
The communications register controls access to the full register
map of the ADC. This register is an 8-bit write only register. On
power-up or after a reset, the digital interface defaults to a state
where it is expecting a write to the communications register.
Therefore, all communication begins by writing to the
communications register.
SCLK
CMD
DATA
16640-013
16640-011
DRIVE EDGE
Figure 34. Reading from a Register (8-Bit Command with Register Address
Followed by Data of 8 Bits, 16 Bits, 24, or 32 Bits; Data Length on DOUT Is
Dependent on the Register Selected)
The data written to the communications register determines
which register is being accessed and if the next operation is a
read or write. The RA bits (Bits[5:0] in Register 0x00)
Rev. B | Page 21 of 59
AD4111
Data Sheet
the default state by resetting the entire device, including the
register contents. Alternatively, if CS is being used with the digital
interface, returning CS high sets the digital interface to the
default state and halts any serial interface operation.
AD4111 RESET
After a power-up cycle and when the power supplies are stable,
a device reset is required. In situations where interface synchronization is lost, a device reset is also required. A write operation
of at least 64 serial clock cycles with DIN high returns the ADC to
Table 10. Communications Register Bit Map
Reg.
0x00
Name
COMMS
Bits
[7:0]
Bit 7
WEN
Bit 6
R/W
Bit 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0x00
RW
W
Bit 2
Bit 1
Bit 0
Reset
0x30DX 1
RW
R
RA
Table 11. ID Register Bit Map
Reg.
0x07
1
Name
ID
Bits
[15:8]
[7:0]
Bit 4
Bit 3
ID[15:8]
ID[7:0]
X means don’t care.
Rev. B | Page 22 of 59
Data Sheet
AD4111
CONFIGURATION OVERVIEW
Channel Configuration
After power-on or reset, the AD4111 default configuration is as
follows:
The AD4111 has 16 independent channels and 8 independent
setups. When open wire detection is not enabled, the user can
select any of the input pairs on any channel, as well as any of
the eight setups for any channel, giving the user full flexibility in
the channel configuration. This flexibility also allows per channel
configuration when using differential inputs and single-ended
inputs because each channel can have its own dedicated setup.
When open wire detection is enabled, the input selection per
channel must follow the guidelines documented in the Open
Wire Detection section. Open wire detection is enabled in the
GPIO configuration register.
•
•
•
•
•
Channel configuration: Channel 0 is enabled, the VIN0
and VIN1 pair is selected as the input. Setup 0 is selected.
Setup configuration: the analog input buffers are disabled and
the reference input buffers are also disabled. The REF± pins
are selected as the reference source. Note that for this
setup, the default channel does not operate correctly
because the input buffers need to be enabled for a VIN
input.
Filter configuration: the sinc5 + sinc1 filter is selected and
the maximum output data rate of 31.25 kSPS is selected.
ADC mode: continuous conversion mode and the internal
oscillator are enabled. The internal reference is disabled.
Interface mode: CRC and the data and status output are
disabled.
GPIO configuration: open wire detection is disabled.
Note that only a few of the register setting options are shown.
This list is only an example. For full register information, see
the Register Details section.
Figure 35 shows an overview of the suggested flow for changing
the ADC configuration, divided into the following three blocks:
•
•
•
Channel Registers
The channel registers select which of the voltage or current
inputs is used for that channel. This register also contains a
channel enable/disable bit and the setup selection bits, which are
used to select which of the eight available setups to use for this
channel.
When the AD4111 is operating with more than one channel
enabled, the channel sequencer cycles through the enabled
channels in sequential order, from Channel 0 to Channel 15. If
a channel is disabled, it is skipped by the sequencer. Details of
the channel register for Channel 0 are shown in Table 12.
Channel configuration (see Box A in Figure 35)
Setup configuration (see Box B in Figure 35)
ADC mode and interface mode configuration (see Box C
in Figure 35)
A
CHANNEL CONFIGURATION
SELECT INPUT AND SETUP FOR EACH ADC CHANNEL
ENABLE OPEN WIRE DECTION IN GPIO CONFIGURATION
B
SETUP CONFIGURATION
8 POSSIBLE ADC SETUPS
SELECT FILTER ORDER, OUTPUT DATA RATE, AND MORE
C
ADC MODE AND INTERFACE MODE CONFIGURATION
SELECT ADC OPERATING MODE, CLOCK SOURCE,
ENABLE CRC, DATA AND STATUS, AND MORE
16640-137
•
Figure 35. Suggested ADC Configuration Flow
Table 12. Channel Register 0
Reg.
0x10
Name
CH0
Bits
[15:8]
[7:0]
Bit 7
CH_EN0
Bit 6
Bit 5
Bit 4
SETUP_SEL0
Bit 3
INPUT[7:0]
Rev. B | Page 23 of 59
Bit 2
Reserved
Bit 1
Bit 0
INPUT[9:8]
Reset
0x8001
RW
RW
AD4111
Data Sheet
ADC Setups
Setup Configuration Registers
The AD4111 has eight independent setups. Each setup consists
of the following four registers:
The setup configuration registers allow the user to select the output
coding of the ADC by selecting between bipolar mode and
unipolar mode. The user can select the reference source using
these registers. Three options are available: a reference connected
between the REF+ and REF− pins, the internal reference, or using
AVDD − AVSS. The input and reference buffers can also be
enabled or disabled using these registers.
•
•
•
•
Setup configuration register
Filter configuration register
Gain register
Offset register
For example, Setup 0 consists of Setup Configuration
Register 0, Filter Configuration Register 0, Gain Register 0, and
Offset Register 0. Figure 36 shows the grouping of these
registers. The setup is selectable from the channel registers (see
the Channel Configuration section), which allows each channel
to be assigned to one of eight separate setups. Table 13 through
Table 16 show the four registers that are associated with Setup 0.
This structure is repeated for Setup 1 to Setup 7.
SETUP CONFIG
REGISTERS
Filter Configuration Registers
The filter configuration registers select which digital filter is
used at the output of the ADC modulator. The order of the
filter and the output data rate are selected by setting the bits in
these registers. For more information, see the Digital Filter
section.
FILTER CONFIG
REGISTERS
GAIN REGISTERS*
OFFSET REGISTERS
SETUPCON0 0x20
FILTCON0 0x28
GAIN0
0x38
OFFSET0 0x30
SETUPCON1 0x21
FILTCON1 0x29
GAIN1
0x39
OFFSET1
SETUPCON2 0x22
FILTCON2 0x2A
GAIN2
0x3A
OFFSET2 0x32
SETUPCON3 0x23
FILTCON3 0x2B
GAIN3
0x3B
OFFSET3 0x33
SETUPCON4 0x24
FILTCON4 0x2C
GAIN4
0x3C
OFFSET4 0x34
SETUPCON5 0x25
FILTCON5 0x2D
GAIN5
0x3D
OFFSET5 0x35
SETUPCON6 0x26
FILTCON6 0x2E
GAIN6
0x3E
OFFSET6 0x36
SETUPCON7 0x27
FILTCON7 0x2F
GAIN7
0x3F
INPUT BUFFERS
REFERENCE INPUT BUFFERS
REFERENCE SOURCE
SELECT DIGITAL
FILTER TYPE
AND OUTPUT DATA RATE
31.25kSPS TO 1.25SPS
SINC5 + SINC1
SINC3
SINC3 MAP
ENHANCED 50Hz/60Hz
GAIN CORRECTION
OPTIONALLY
PROGRAMMED
PER SETUP AS REQUIRED
(FACTORY CALIBRATED
FOR CURRENT INPUT)
OFFSET7 0x37
OFFSET CORRECTION
OPTIONALLY PROGRAMMED
PER SETUP AS REQUIRED
16640-138
SELECT PERIPHERAL
FUNCTIONS FOR
ADC CHANNEL
0x31
Figure 36. ADC Setup Register Grouping
Table 13. Setup Configuration Register 0
Reg.
0x20
Name
Bits
Bit 7
SETUPCON0 [15:8]
[7:0] Reserved
Bit 6
Reserved
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
BI_UNIPOLAR0 REFBUF0+ REFBUF0−
REF_SEL0
Reserved
Bit 0
INBUF0
Reset
0x1000
RW
RW
Reset
0x0500
RW
RW
Table 14. Filter Configuration Register 0
Reg.
0x28
Name
FILTCON0
Bits
Bit 7
[15:8] SINC3_MAP0
[7:0] Reserved
Bit 6
Bit 5
Bit 4
Reserved
ORDER0
Bit 3
Bit 2
ENHFILTEN0
ODR0
Bit 1
Bit 0
ENHFILT0
Table 15. Gain Register 0
Reg.
0x38
Name
GAIN0
Bits
[23:0]
Bits[23:0]
GAIN0[23:0]
Reset
RW
0x5XXXX0 RW
Bits[23:0]
OFFSET0[23:0]
Reset
RW
0x800000 RW
Table 16. Offset Register 0
Reg.
0x30
Name
OFFSET0
Bits
[23:0]
Rev. B | Page 24 of 59
Data Sheet
AD4111
Gain Registers
ADC Mode Register
The gain registers are 24-bit registers that hold the gain calibration
coefficient for the ADC. The gain registers are read/write registers.
At power-on, these registers are configured for current inputs
with factory calibrated coefficients. Therefore, every device has
different default coefficients. When enabling a voltage input on
a channel register (see the Channel Registers section), the user
must also update the gain register for the corresponding setup.
For more information, see the Adjusting Voltage Input Gain
section.
The ADC mode register primarily sets the conversion mode of
the ADC to either continuous or single conversion. The user
can also select the standby and power-down modes, as well as
any of the calibration modes. In addition, this register contains
the clock source select bits and internal reference enable bit. The
reference select bits are contained in the setup configuration
registers (see the ADC Setups section for more information).
The details of this register are shown in Table 17.
Offset Registers
The interface mode register configures the digital interface
operation. This register allows the user to control data-word
length, CRC enable, data plus status read, and continuous read
mode. The details of this register are shown in Table 18. For more
information, see the Digital Interface section.
Interface Mode Register
The offset registers hold the offset calibration coefficient for the
ADC. The power-on reset value of the offset registers is 0x800000.
The offset registers are 24-bit read and write registers.
ADC Mode and Interface Mode Configuration
The ADC mode register and the interface mode register configure
the core peripherals for use by the AD4111 and the mode for the
digital interface.
Table 17. ADC Mode Register
Reg.
0x01
Name
ADCMODE
Bits
[15:8]
[7:0]
Bit 7
REF_EN
Reserved
Bit 6
Reserved
Bit 5
SING_CYC
Mode
Bit 4
Bit 3
Reserved
Bit 2
CLOCKSEL
Bit 1
Bit 0
Delay
Reserved
Reset
0x2000
RW
RW
Reset
0x0000
RW
RW
Table 18. Interface Mode Register
Reg.
0x02
Name
IFMODE
Bits
[15:8]
[7:0]
Bit 7
CONTREAD
Bit 6
Reserved
DATA_STAT
Bit 5
REG_CHECK
Bit 4
ALT_SYNC
Reserved
Bit 3
Bit 2
Bit 1
IOSTRENGTH
Reserved
CRC_EN
Reserved
Rev. B | Page 25 of 59
Bit 0
DOUT_RESET
WL16
AD4111
Data Sheet
CIRCUIT DESCRIPTION
The simplified input circuits are shown in Figure 37 and Figure
38.
MULTIPLEXER
There are nine voltage pins and eight current inputs: VIN0− to
VIN7, VINCOM, IIN0+ to IIN3+, and IIN0− to IIN3−. Each of
these pins connects to the internal multiplexer. The multiplexer
enables these inputs to be configured as input pairs (see the
Voltage Inputs section and the Current Inputs section for more
information on how to set up these inputs). The AD4111 can
have up to 16 active channels. When more than one channel is
enabled, the channels are automatically sequenced in order
from the lowest enabled channel number to the highest enabled
channel number. The output of the multiplexer is connected to
the input of the integrated true rail-to-rail buffers. These
buffers can be bypassed and the multiplexer output can be
directly connected to the switched capacitor input of the ADC.
AVDD MULTIPLEXER
IIN0+
5Ω
+IN
AVSS
RSENSE
50Ω
AVDD
–IN
5Ω
16640-014
IIN0–
AVSS
Figure 37. Simplified Current Input Circuit
AVDD
COMPA
10MΩ
VIN0
222kΩ
222kΩ
MULTIPLEXER
1MΩ
+IN
AVSS
COMPB
AVDD
10MΩ
VIN1
AVDD
222kΩ
1MΩ
AVSS
AVDD
222kΩ
VBIAS–
–IN
222kΩ
222kΩ
AVSS
Figure 38. Simplified Voltage Input Circuit
Rev. B | Page 26 of 59
16640-015
VINCOM
1MΩ
Data Sheet
AD4111
Open wire detection is enabled by setting Bit 12 (OW_EN) and
Bit 13 (OP_EN0_1) in the GPIO configuration register to 1 (see
Table 30). Bit 6 (DATA_STAT) in the interface mode register,
must also be set (see Table 27).
CURRENT INPUTS
There are four current input pins (IIN0+ to IIN3+) and four
current return pins (IIN0− to IIN3−). Connect these pins in
numbered pairs (for example, IIN0+ and IIN0−).
Disable the input buffers for the current inputs.
To achieve specified accuracy, the current channels are factory
calibrated. This calibration value is stored in on-chip nonvolatile
memory and is copied to all gain registers after a power-up or reset.
VOLTAGE INPUTS
The AD41111 can be set up to have eight single-ended inputs
or four fully differential inputs. The voltage divider on the
analog front end has a division ratio of 10 and consists of
precision matched resistors that enable an input range of ±20 V
from a single 5 V power supply.
Enable the input buffers in the setup register for voltage input
channels.
Fully Differential Inputs
Due to the matching resistors on the analog front end, the
differential inputs must be paired together in the following
pairs: VIN0 and VIN1, VIN2 and VIN3, VIN4 and VIN5, and
VIN6 and VIN7. If any two voltage inputs are paired in a
configuration other than what is described in this data sheet,
the accuracy of the device cannot be guaranteed.
Single-Ended Inputs
Voltage inputs must be assigned two channels per
measurement when using open wire detection. Voltage inputs
must also be assigned to specific channel pairs to ensure that
open wire detection measurements work correctly. For singleended input, open wire detection measurements, the channel
pairings that must be used are as follows:
•
•
•
•
•
•
•
•
Channel 15 and Channel 0
Channel 1 and Channel 2
Channel 3 and Channel 4
Channel 5 and Channel 6
Channel 7 and Channel 8
Channel 9 and Channel 10
Channel 11 and Channel 12
Channel 13 and Channel 14
For differential input, open wire detection measurements, the
channel pairings that must be used are as follows:
•
•
•
•
Channel 1 and Channel 2
Channel 5 and Channel 6
Channel 9 and Channel 10
Channel 13 and Channel 14
Additionally, for differential inputs, the inputs must be set up
in the following differential pairs to ensure correct operation:
The user can also choose to measure up to eight different
single-ended voltage inputs. In this case, each of the voltage
inputs must be paired with VINCOM. Connect VINCOM
externally to AVSS.
Adjusting Voltage Input Gain
After a power-up or reset, all gain registers are loaded with factory
calibration coefficients for current inputs. When using a
voltage input, the corresponding gain register must be modified
after powering up or resetting the device. Perform this
modification by running an internal full-scale calibration (see
the Calibration section for more information). Alternatively,
the gain register can be overwritten with a nominal value of
0x55567C. However, a calibration is recommended because the
ideal value varies from device to device.
Open Wire Detection
Open wire detection is a system level diagnostic that detects
when an external sensor or source signal is disconnected from
the system input. The AD4111 incorporates a unique feature
that enables open wire detection on ±10 V voltage inputs while
operating on a 5 V or 3.3 V single power supply, which in
existing designs requires a supply greater than ±10 V. Open
wire detection must be supported in user software. This section
describes how to set up the AD4111 for open wire detection
together with the associated calculations required.
•
•
•
•
VIN0 and VIN1
VIN2 and VIN3
VIN4 and VIN5
VIN6 and VIN7
See Table 30 for more information on the channel registers.
After the AD4111 is configured correctly, the output data must
be processed in user software to implement open wire
detection. An open wire on an input is detected by comparing
the absolute difference between the two channels associated
with an input to a threshold. The suggested threshold is
300 mV input referred. This threshold is approximately 100,000
(0x0186A0) in decimal output code from the ADC when
operating in bipolar configuration with a 2.5 V voltage
reference and AVDD = 5 V. This threshold is approximately
200,000 (0x030D40) codes when operating in unipolar
configuration. See the Data Output Coding section for more
information on converting ADC output codes to volts. If the
difference is greater than this threshold, an open wire must be
flagged by the user software. Open wire detection operation is
shown in the Example 1—Open Wire Detection (Single-Ended
Input) section and the Example 2—Open Wire Detection
(Differential Input) section.
Rev. B | Page 27 of 59
AD4111
Data Sheet
Note that the following registers and settings are used in the
examples shown in the Example 1—Open Wire Detection
(Single-Ended Input) section and the Example 2—Open Wire
Detection (Differential Input) section:
•
•
•
•
•
IFMODE = 0x0040 enables data and status.
GPIOCON = 0x3800 enables open wire detection.
SETUPCON0 = 0x1300 enables input buffers and the
external reference (2.5 V), and selects bipolar mode.
Set GAIN0 as described in the Adjusting Voltage Input
Gain section.
All other registers are set to default values.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
In this example,
•
In this example,
•
Example 1—Open Wire Detection (Single-Ended Input)
•
Example 2—Open Wire Detection (Differential Input)
Channel 0 and Channel 15 = 0x8010 enables the singleended input (VIN0, VINCOM) and Setup 0.
The VIN0 and VINCOM pins are left floating. Nothing is
connected to the pins.
Channel 0 = 9,129,327 (2.2075 V).
Channel 15 = 9,360,856 (2.8975 V).
|9,129,327 − 9,360,856| = 231,529 (690 mV) > 100,000
(300 mV).
Open wire is flagged.
A 1 V input is connected to the VIN0 and VINCOM input
pins.
Channel 0 = 8,725,210 (1.00315 V).
Channel 15 = 8,725,200 (1.00312 V).
|8,725,210 – 8,725,200| = 10 (0.03 mV) < 100,000 (300 mV).
Open wire is not flagged.
•
•
•
•
•
•
Channel 1 and Channel 2 = 0x8001 enables the differential
input (VIN0, VIN1) and Setup 0.
Channel 0 cannot be used for the differential input.
Disable Channel 0 by setting it to 0x0000.
The VIN0 and VIN1 pins are left floating. Nothing is
connected to the pins.
Channel 1 = 8,619,210 (687 mV).
Channel 2 = 8,157,971 (−687 mV).
|8,619,210 − 8,157,971| = 461,239 (1.374 V) > 100,000
(300 mV).
Open wire is flagged.
A 1 V differential input is connected the VIN0 and VIN1
input pins.
Channel 1 = 8,724,611 (1.0014 V).
Channel 2 = 8,724,577 (1.0013 V).
|8,724,611 − 8,724,577| = 34 (0.1 mV) < 100,000 (300 mV).
Open wire is not flagged.
Open Wire Detection Compensation Pins
For the correct function of open wire detection, connect a
capacitor and resistor in series between each compensation and
voltage input pin. The recommended values are a 1 kΩ resistor
and a 680 pF capacitor. There are two compensation pins,
COMPA and COMPB. COMPA must be connected through
the resistor and capacitor to VIN0, VIN2, VIN4, and VIN6.
COMPB must be connected to VIN1, VIN3, VIN5, and VIN7
(see Table 5 and Figure 31).
Rev. B | Page 28 of 59
Data Sheet
AD4111
Bits[5:4], in the setup configuration registers appropriately. The
structure of the Setup Configuration 0 register is shown in Table
19. By default, the AD4111 uses an external reference on powerup.
DATA OUTPUT CODING
When the ADC is configured for unipolar operation, the
output code is natural (straight) binary with a zero differential
input voltage resulting in a code of 00 … 00, a midscale voltage
resulting in a code of 100 … 000, and a full-scale input voltage
resulting in a code of 111 … 111. The output code for any input
voltage is represented as
Internal Reference
The AD4111 includes a low noise, low drift voltage reference.
The internal reference has a 2.5 V output. The internal
reference is output on the REFOUT pin after the REF_EN bit in
the ADC mode register is set and is decoupled to AVSS with a
0.1 μF capacitor. The AD4111 internal reference is disabled by
default on power-up.
Code = (2N × VIN × 0.1)/VREF
The output code for any input current is represented as
Code = (2N × IIN × 50 Ω)/VREF
When the ADC is configured for bipolar operation, the output
code is offset binary with a negative full-scale voltage resulting
in a code of 000 … 000, a zero differential input voltage resulting in
a code of 100 … 000, and a positive full-scale input voltage
resulting in a code of 111 … 111. The output code for any
analog input voltage can be represented as
External Reference
The AD4111 has a fully differential reference input applied
through the REF+ and REF− pins. Standard low noise, low drift
voltage references, such as the ADR4525, are recommended for
use. Apply the external reference to the AD4111 reference pins
as shown in Figure 39. Decouple the output of any external
reference to AVSS. As shown in Figure 39, the ADR4525
output is decoupled with a 0.1 μF capacitor at the output for
stability purposes. The output is then connected to a 4.7 μF
capacitor, which acts as a reservoir for any dynamic charge
required by the ADC, and is followed by a 0.1 μF decoupling
capacitor at the REF+ input. This capacitor is placed as close as
possible to the REF+ and REF− pins.
Code = 2N – 1 × ((VIN × 0.1/VREF) + 1)
The output code for any input current is represented as
Code = 2N − 1 × ((IIN × 50 Ω/VREF) + 1)
where:
N = 24.
VIN is the input voltage.
IIN is the input current.
VREF is the reference voltage.
The REF− pin is connected directly to the AVSS potential. When
an external reference is used instead of the internal reference
to supply the AD4111, attention must be paid to the output of
the REFOUT pin. The internal reference is controlled by the
REF_EN bit (Bit 15) in the ADC mode register, which is shown
in Table 20. If the internal reference is not being used elsewhere
in the application, ensure that the REF_EN bit is disabled.
AD4111 REFERENCE
The AD4111 offers the user the option of either supplying an
external reference to the REF+ and REF− pins of the device,
using AVDD – AVSS, or by allowing the use of the internal
2.5 V, low noise, low drift reference. Select the reference source
to be used by the analog input by setting the REF_SELx bits,
AD4111
3V TO 18V
ADR45252
0.1µF
2.5V VREF
1
40
REF+
39
REF–
0.1µF
0.1µF
1
1
4.7µF
1
1
16640-016
1 ALL DECOUPLING IS TO AVSS.
2ANY OF THE ADR4525 FAMILY REFERENCES CAN BE USED.
ADR4525 ENABLES REUSE OF THE 3.3V ANALOG SUPPLY
NEEDED FOR AVDD TO POWER THE REFERENCE VIN.
Figure 39. ADR4525 Connected to AD4111 REF± Pins
Table 19. Setup Configuration 0 Register
Reg.
0x20
Name
SETUPCON0
Bits
[15:8]
[7:0]
Bit 7
Reserved
Bit 6
Reserved
Reserved
Bit 5
Bit 4
BI_UNIPOLAR0
REF_SEL0
Bit 3
REFBUF0+
Bit 2
Bit 1
REFBUF0−
Reserved
Bit 0
INBUF0
Reset
0x1000
RW
RW
Table 20. ADC Mode Register
Reg.
0x01
Name
ADCMODE
Bits
[15:8]
[7:0]
Bit 7
REF_EN
Reserved
Bit 6
Reserved
Bit 5
SING_CYC
Mode
Bit 4
Bit 3
Reserved
Rev. B | Page 29 of 59
Bit 2
CLOCKSEL
Bit 1
Bit 0
Delay
Reserved
Reset
0x2000
RW
RW
AD4111
Data Sheet
BUFFERED REFERENCE INPUT
External Crystal
The AD4111 has true rail-to-rail, integrated, precision unity
gain buffers on both ADC reference inputs. The buffers provide
the benefit of providing high input impedance and allowing
high impedance external sources to be directly connected to the
reference inputs. The integrated reference buffers can fully
drive the internal reference switch capacitor sampling network,
simplifying the reference circuit requirements. Each reference
input buffer amplifier is fully chopped, meaning that it
minimizes the offset error drift and 1/f noise of the buffer. When
using a reference such as the ADR4525, these buffers are not
required because these references, with proper decoupling, can
drive the reference inputs directly.
If higher precision, lower jitter clock sources are required, the
AD4111 can use an external crystal to generate the master
clock. The crystal is connected to the XTAL1 and XTAL2/
CLKIO pins. A recommended crystal for use is the FA-20H, a
16 MHz, 10 ppm, 9 pF crystal from Epson-Toyocom that is
available in a surface-mount package. As shown in Figure 40,
insert two capacitors (CX1 and CX2) from the traces
connecting the crystal to the XTAL1 and XTAL2/CLKIO pins.
These capacitors allow circuit tuning. Connect these capacitors
to the DGND pin. The value for these capacitors depends on
the length and capacitance of the trace connections between the
crystal and the XTAL1 and XTAL2/CLKIO pins. Therefore, the
values of these capacitors differ depending on the PCB layout
and the crystal used.
CLOCK SOURCE
The AD4111 uses a nominal master clock of 2 MHz. The AD4111
can source its sampling clock from one of three sources:
CX1
1
XTAL1 12
An internal oscillator.
An external crystal (use a 16 MHz crystal automatically
divided internally to set the 2 MHz clock).
An external clock source.
XTAL2/CLKIO 13
CX2
1
All output data rates listed in the data sheet relate to a master
clock rate of 2 MHz. Using a lower clock frequency from, for
instance, an external source scales any listed data rate proportionally. To achieve the specified data rates, particularly rates
for rejection of 50 Hz and 60 Hz, use a 2 MHz clock. The source
of the master clock is selected by setting the CLOCKSEL bits
(Bits[3:2]) in the ADC mode register, as shown in Table 20. The
default operation on power-up and reset of the AD4111 is to
operate with the internal oscillator. It is possible to fine tune the
output data rate and filter notch at low output data rates using
the SINC3_MAPx bits.
Internal Oscillator
The internal oscillator runs at 16 MHz and is internally divided
down to 2 MHz for the modulator and can be used as the ADC
master clock. The internal oscillator is the default clock source for
the AD4111 and is specified with an accuracy of −2.5% to +2.5%.
There is an option to allow the internal clock oscillator to be output
on the XTAL2/CLKIO pin. The clock output is driven to the
IOVDD logic level. This option can affect the dc performance of
the AD4111 due to the disturbance introduced by the output
driver. The extent to which the performance is affected depends
on the IOVDD voltage supply. Higher IOVDD voltages create a
wider logic output swing from the driver and affect performance
to a greater extent. This effect is further exaggerated if the
IOSTRENGTH bit is set at higher IOVDD levels (see Table 27
for more information).
1DECOUPLE TO DGND
16640-017
AD4111
Figure 40. External Crystal Connections
The external crystal circuitry can be sensitive to the SCLK
edges, depending on the SCLK frequency, IOVDD voltage,
crystal circuitry layout, and the crystal used. During crystal startup,
any disturbances caused by the SLCK edges may cause double
edges on the crystal input, resulting in invalid conversions until
the crystal voltage has reached a high enough level such that
any interference from the SCLK edges is insufficient to cause
double clocking. This double clocking can be avoided by
ensuring that the crystal circuitry has reached a sufficient
voltage level after startup before applying any SCLK.
Because of the nature of the crystal circuitry, it is recommended
that empirical testing of the circuit be performed under the
required conditions, with the final PCB layout and crystal, to
ensure correct operation.
External Clock
The AD4111 can also use an externally supplied clock. In
systems where an externally supplied clock is used, the external
clock is routed to the XTAL2/CLKIO pin. In this configuration,
the XTAL2/ CLKIO pin accepts the externally sourced clock
and routes it to the modulator. The logic level of this clock
input is defined by the voltage applied to the IOVDD pin.
Rev. B | Page 30 of 59
Data Sheet
AD4111
DIGITAL FILTER
SINC3 FILTER
The AD4111 has three flexible filter options to allow
optimization of noise, settling time, and rejection:
•
•
•
The sinc3 filter achieves the best single-channel noise performance
at lower rates and is, therefore, most suitable for single-channel
applications. The sinc3 filter always has a settling time equal to
The sinc5 + sinc1 filter.
The sinc3 filter.
Enhanced 50 Hz and 60 Hz rejection filters.
SINC5
SINC1
tSETTLE = 3/Output Data Rate
Figure 43 shows the frequency domain filter response for the
sinc3 filter. The sinc3 filter has good roll-off over frequency and
has wide notches for good notch frequency rejection.
50Hz AND 60Hz
POSTFILTER
16640-018
0
SINC3
–10
–20
Figure 41. Digital Filter Block Diagram
The filter and output data rate are configured by setting the
appropriate bits in the filter configuration register for the selected
setup. Each channel can use a different setup and therefore, a
different filter and output data rate. See the Register Details
section for more information.
FILTER GAIN (dB)
–30
–60
–70
–80
–90
SINC5 + SINC1 FILTER
–100
0
–20
–40
–110
–120
0
50
100
FREQUENCY (Hz)
150
16640-020
The sinc5 + sinc1 filter is targeted at multiplexed applications
and achieves single cycle settling at output data rates of 2.6 kSPS
and less. The sinc5 block output is fixed at the maximum rate of
31.25 kSPS, and the sinc1 block output data rate can be varied to
control the final ADC output data rate. Figure 42 shows the
frequency domain response of the sinc5 + sinc1 filter at a 50 SPS
output data rate. The sinc5 + sinc1 filter has a slow roll-off over
frequency and narrow notches.
FILTER GAIN (dB)
–40
–50
Figure 43. Sinc3 Filter Response
The output data rates with the accompanying settling time and
rms noise for the sinc3 filter are shown in Table 8 and Table 9.
It is possible to fine tune the output data rate for the sinc3 filter by
setting the SINC3_MAPx bit in the filter configuration registers.
If this bit is set, the mapping of the filter register changes to directly
program the decimation rate of the sinc3 filter. All other options
are eliminated. The data rate when on a single channel can be
calculated using the following equation:
Output Data Rate = fMOD/(32 × FILTCONx[14:0])
where:
fMOD is the modulator rate (MCLK/2) and is equal to 1 MHz.
FILTCONx[14:0] are the contents on the filter configuration
registers, excluding the MSB.
–60
–80
–120
0
50
100
150
FREQUENCY (Hz)
16640-019
–100
For example, an output data rate of 50 SPS can be achieved with
SINC3_MAPx enabled by setting the FILTCONx[14:0] bits to a
value of 625.
Figure 42. Sinc5 + Sinc1 Filter Response at 50 SPS ODR
The output data rates with the accompanying settling time and
rms noise for the sinc5 + sinc1 filter are shown in in Table 6
and Table 7.
Rev. B | Page 31 of 59
AD4111
Data Sheet
The AD4111 can be configured by setting the SING_CYC bit in
the ADC mode register so that only fully settled data is output, thus
effectively putting the ADC into a single cycle settling mode. This
mode achieves single cycle settling by reducing the output data rate
to be equal to the settling time of the ADC for the selected output
data rate. This bit has no effect with the sinc5 + sinc1 filter at
output data rates of 2.6 kSPS and less or when multiple
channels are enabled.
Figure 44 shows a step on the analog input with single cycle
settling mode disabled and the sinc3 filter selected. The analog
input requires at least three cycles after the step change for the
output to reach the final settled value.
ANALOG
INPUT
FULLY
SETTLED
16640-021
ADC
OUTPUT
1/ODR
Figure 44. Step Input Without Single Cycle Settling
Figure 45 shows the same step on the analog input but with
single cycle settling enabled. The analog input requires at least a
single cycle for the output to be fully settled. The output data
rate, as indicated by the RDY signal, is now reduced to equal
the settling time of the filter at the selected output data rate.
ANALOG
INPUT
FULLY
SETTLED
ADC
OUTPUT
16640-033
SINGLE CYCLE SETTLING
tSETTLE
Figure 45. Step Input with Single Cycle Settling
ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS
The enhanced filters provide rejection of 50 Hz and 60 Hz
simultaneously and allow the user to trade off settling time and
rejection. These filters can operate at up to 27.27 SPS or can reject
up to 90 dB of 50 Hz ± 1 Hz and 60 Hz ± 1 Hz interference.
These filters are operated by postfiltering the output of the
sinc5 + sinc1 filter. For this reason, the sinc5 + sinc1 filter must
be selected when using the enhanced filters to achieve the
specified settling time and noise performance. Table 21 and
Table 22 show the output data rates with the accompanying
settling time, rejection, and rms noise. Figure 46 to Figure 53
show the frequency domain plots of the responses from the
enhanced filters.
Table 21. Enhanced Filters Output Data Rate, Voltage Input Noise, Settling Time, and Rejection Using the Enhanced Filters
Output Data Rate (SPS)
27.27
25
20
16.667
1
Settling
Time (ms)
36.67
40.0
50.0
60.0
Simultaneous Rejection of
50 Hz ± 1 Hz and 60 Hz ± 1 Hz (dB) 1
47
62
85
90
Noise
(µV rms)
6.44
6.09
5.54
5.38
Peak-to-Peak
Resolution (Bits)
19.1
19.2
19.35
19.51
Comments
See Figure 46 and Figure 49
See Figure 47 and Figure 50
See Figure 48 and Figure 51
See Figure 52 and Figure 53
Master clock = 2.00 MHz.
Table 22. Enhanced Filters Output Data Rate, Current Input Noise, Settling Time, and Rejection Using the Enhanced Filters
Output Data Rate (SPS)
27.27
25
20
16.667
1
Settling
Time (ms)
36.67
40.0
50.0
60.0
Simultaneous Rejection of
50 Hz ± 1 Hz and 60 Hz ± 1 Hz (dB) 1
47
62
85
90
Noise
(nA rms)
7.69
7.68
7.26
7.25
Master clock = 2.00 MHz.
Rev. B | Page 32 of 59
Peak-to-Peak
Resolution (Bits)
21.4
21.2
21.7
21.7
Comments
See Figure 46 and Figure 49
See Figure 47 and Figure 50
See Figure 48 and Figure 51
See Figure 52 and Figure 53
AD4111
0
–10
–10
–20
–20
–30
–30
–40
–50
–60
–60
–70
–80
–80
–90
–90
200
300
400
500
600
FREQUENCY (Hz)
–100
40
–10
–10
–20
–20
–30
–30
FILTER GAIN (dB)
0
–40
–50
–60
–80
–90
–90
600
FREQUENCY (Hz)
–100
40
16640-023
–100
500
–10
–10
–20
–20
–30
–30
FILTER GAIN (dB)
0
–40
–50
–60
–90
–90
–100
FREQUENCY (Hz)
600
16640-024
–80
500
65
70
–50
–80
400
60
–60
–70
300
55
–40
–70
200
50
Figure 50. 25 SPS ODR, 40 ms Settling Time (40 Hz to 70 Hz)
0
100
45
FREQUENCY (Hz)
Figure 47. 25 SPS ODR, 40 ms Settling Time
0
70
–60
–80
400
65
–50
–70
300
60
–40
–70
200
55
Figure 49. 27.27 SPS ODR, 36.67 ms Settling Time (40 Hz to 70 Hz)
0
100
50
FREQUENCY (Hz)
Figure 46. 27.27 SPS ODR, 36.67 ms Settling Time
0
45
16640-026
100
–100
40
45
50
55
60
65
FREQUENCY (Hz)
Figure 51. 20 SPS ODR, 50 ms Settling Time (40 Hz to 70 Hz)
Figure 48. 20 SPS ODR, 50 ms Settling Time
Rev. B | Page 33 of 59
70
16640-027
0
FILTER GAIN (dB)
–50
–70
–100
FILTER GAIN (dB)
–40
16640-025
FILTER GAIN (dB)
0
16640-022
FILTER GAIN (dB)
Data Sheet
Data Sheet
0
–10
–10
–20
–20
–30
–30
–40
–50
–60
–40
–50
–60
–70
–70
–80
–80
–90
–90
–100
0
100
200
300
400
500
FREQUENCY (Hz)
600
Figure 52. 16.667 SPS ODR, 60 ms Settling Time
–100
40
45
50
55
60
65
70
FREQUENCY (Hz)
Figure 53. 16.667 SPS ODR, 60 ms Settling Time (40 Hz to 70 Hz)
Rev. B | Page 34 of 59
16640-029
FILTER GAIN (dB)
0
16640-028
FILTER GAIN (dB)
AD4111
Data Sheet
AD4111
OPERATING MODES
The AD4111 has a number of operating modes that can be set
from the ADC mode register and interface mode register (see
Table 26 and Table 27). These modes are as follows:
•
•
•
•
•
•
Continuous conversion mode
Continuous read mode
Single conversion mode
Standby mode
Power-down mode
Calibration modes (four)
CONTINUOUS CONVERSION MODE
Continuous conversion mode is the default power-up mode.
The AD4111 converts continuously, and the RDY bit in the
status register goes low each time a conversion is complete. If CS
is low, the RDY output also goes low when a conversion is
complete. To read a conversion, write to the communications
register to indicate that the next operation is a read of the data
register. When the data-word has been read from the data register,
the DOUT/RDY pin goes high. The user can read this register
additional times, if required. However, ensure that the data
register is not being accessed at the completion of the next
conversion. Otherwise, the new conversion word is lost.
When several channels are enabled, the ADC automatically
sequences through the enabled channels, performing one
conversion on each channel. When all the channels are
converted, the sequence starts again with the first channel. The
channels are converted in order from the lowest enabled channel
to the highest enabled channel. The data register is updated as
soon as each conversion is available. The RDY output pulses
low each time a conversion is available. The user can then read
the conversion while the ADC converts the next enabled channel.
If the DATA_STAT bit in the interface mode register is set to 1,
the contents of the status register, along with the conversion data,
are output each time the data register is read. The four LSBs of
the status register indicates the channel to which the conversion
corresponds.
CS
0x44
0x44
DIN
DATA
DATA
16640-030
DOUT/RDY
SCLK
Figure 54. Continuous Conversion Mode
Rev. B | Page 35 of 59
AD4111
Data Sheet
mode register. When this bit is set, the only serial interface
operations possible are reads from the data register. To exit continuous read mode, issue a dummy read of the ADC data register
command (0x44) while the RDY output is low. Alternatively, apply
a software reset (that is, 64 SCLKs with CS = 0 and DIN = 1) to
reset the ADC and all register contents. The dummy read and
the software reset are the only commands that the interface
recognizes after it is placed in continuous read mode. Hold
DIN low in continuous read mode until an instruction is to be
written to the device.
CONTINUOUS READ MODE
In continuous read mode, it is not required to write to the
communications register before reading ADC data. Apply only
the required number of SCLKs after the RDY output goes low
to indicate the end of a conversion. When the conversion is
read, the RDY output returns high until the next conversion is
available. In this mode, the data can be read only once. Ensure
that the data-word is read before the next conversion is
complete. If the user has not read the conversion before the
completion of the next conversion or if insufficient serial clocks
are applied to the AD4111 to read the data-word, the serial
output register is reset shortly before the next conversion is
complete, and the new conversion is placed in the output serial
register. The ADC must be configured for continuous
conversion mode to use continuous read mode. To enable
continuous read mode, set the CONTREAD bit in the interface
If multiple ADC channels are enabled, each channel is output
in turn, with the status bits being appended to the data if the
DATA_STAT bit is set in the interface mode register. The four
LSBs of the status register indicates the channel to which the
conversion corresponds.
CS
0x02
0x0080
DIN
DATA
DATA
DATA
16640-031
DOUT/RDY
SCLK
Figure 55. Continuous Read Mode
Rev. B | Page 36 of 59
Data Sheet
AD4111
SINGLE CONVERSION MODE
In single conversion mode, the AD4111 performs a single
conversion and is placed in standby mode after the conversion
is complete. The RDY output goes low to indicate the completion
of a conversion. When the data-word has been read from the
data register, the RDY output goes high. The data register can
be read several times, if required, even when the RDY output goes
high.
If several channels are enabled, the ADC automatically sequences
through the enabled channels and performs a conversion on
each channel. When the first conversion is started, the RDY
output goes high and remains high until a valid conversion is
available and CS is low. When the conversion is available, the
RDY output goes low. The ADC then selects the next channel and
begins a conversion. The user can read the present conversion
while the next conversion is being performed. When the next
conversion is complete, the data register is updated; therefore,
the user has a limited period in which to read the conversion.
When the ADC has performed a single conversion on each of
the selected channels, it returns to standby mode.
If the DATA_STAT bit in the interface mode register is set to 1, the
contents of the status register, along with the conversion, are
output each time the data register is read. The four LSBs of the
status register indicate the channel to which the conversion
corresponds.
CS
0x01
0x8010
0x44
DIN
DATA
16640-032
DOUT/RDY
SCLK
Figure 56. Single Conversion Mode
Rev. B | Page 37 of 59
AD4111
Data Sheet
STANDBY AND POWER-DOWN MODES
In standby mode, most blocks are powered down. The LDO
regulators remain active so that the registers maintain their
contents. The crystal oscillator remains active if selected. To
power down the clock in standby mode, set the CLOCKSEL bits
in the ADC mode register to 00 (internal oscillator mode).
In power-down mode, all blocks are powered down, including
the LDO regulators. All registers lose their contents, and the GPIO
outputs are placed in three-state. To prevent accidental entry to
power-down mode, the ADC must first be placed in standby
mode. Exiting power-down mode requires 64 SCLKs with CS = 0
and DIN = 1, that is, a serial interface reset. A delay of 500 µs is
recommended before issuing a subsequent serial interface
command to allow the LDO regulator to power up.
CALIBRATION
The AD4111 allows a two-point calibration to be performed to
eliminate any offset and gain errors. Four calibration modes are
used to eliminate these offset and gain errors on a per setup basis:
•
•
•
•
Internal zero-scale calibration mode
Internal full-scale calibration mode
System zero-scale calibration mode
System full-scale calibration mode
Only one channel can be active during calibration. After each
conversion, the ADC conversion result is scaled using the ADC
calibration registers before being written to the data register.
The default value of the offset register is 0x800000, and the
nominal value of the gain register is factory calibrated for the
current channels; therefore, this value can vary from 0x500000
to 0x5FFFFF. When enabling a voltage channel, run an internal
full-scale calibration. The following equations show the
calculations that are used. In unipolar mode, the ideal
relationship (that is, not taking into account the ADC gain
error and offset error) is as follows:
Data = ((0.075 × VIN/VREF) × 223 – (Offset − 0x800000)) ×
(Gain/0x400000) × 2
For a current input, the ideal relationship is as follows:
Data = ((0.75 × (IIN × 50)/VREF) × 2123 – (Offset −
0x800000)) × (Gain/0x400000) × 2
In bipolar mode, the ideal relationship (that is, not taking into
account the ADC gain error and offset error) is as follows:
Data = ((0.075 × VIN/VREF) × 223 – (Offset − 0x800000)) ×
(Gain/0x400000) + 0x800000
For a current input, the ideal relationship is as follows:
Data = ((0.75 × (IIN × 50)/VREF) × 223 – (Offset − 0x800000))
× (Gain/0x400000) + 0x800000
To start a calibration, write the relevant value to the mode bits
in the ADC mode register. The DOUT/RDY pin and the RDY bit
in the status register go high when the calibration initiates. When
the calibration is complete, the contents of the corresponding
offset or gain register are updated, the RDY bit in the status
register is reset and the RDY output pin returns low (if CS is
low), and the AD4111 reverts to standby mode.
During an internal offset calibration both modulator inputs are
connected internally to the selected negative analog input pin.
Therefore, it is necessary to ensure that the voltage on the selected
negative analog input pin does not exceed the allowed limits and is
free from excessive noise and interference. To perform
an internal full-scale calibration, a full-scale input voltage is
automatically connected to the ADC input for this calibration.
Internal full-scale calibrations must only be performed on
voltage inputs. Do not perform internal full-scale calibrations
on the current inputs.
However, for system calibrations, the system zero-scale (offset)
and system full-scale (gain) voltages must be applied to the
input pins before initiating the calibration modes. As a result,
errors external to the AD4111 are removed. The calibration
range of the ADC gain for a system full-scale calibration on a
voltage input is from 3.75 × VREF to 10.5 × VREF. However, if
10.5 × VREF is greater than the absolute input voltage specification
for the applied AVDD, use the specification as the upper limit
instead of 10.5 × VREF (see the Specifications section).
Current inputs are factory calibrated. Therefore, it is not necessary
to perform a system calibration. However if a system
calibration is required, apply a full-scale value of 24 mA for a
VREF = 2.5 V.
An internal zero-scale calibration only removes the offset error
of the ADC core. It does not remove error from the resistive
front end. A system zero-scale calibration reduces the offset
error to the order of the noise on that channel.
From an operational point of view, treat a calibration like
another ADC conversion. An offset calibration, if required,
must always be performed before a full-scale calibration. Set the
system software to monitor the RDY bit in the status register or
the RDY output to determine the end of a calibration via a
polling sequence or an interrupt driven routine. All calibrations
require a time equal to the settling time of the selected filter and
output data rate to be completed.
Any calibration can be performed at any output data rate.
Using lower output data rates results in better calibration
accuracy and is accurate for all output data rates. A new offset
calibration is required for a given channel if the reference
source for that channel is changed.
The AD4111 provides the user with access to the on-chip
calibration registers, allowing the microprocessor to read the
calibration coefficients of the device and to write its own
calibration coefficients. A read or write of the offset and gain
registers can be performed at any time except during an internal or
self calibration.
Rev. B | Page 38 of 59
Data Sheet
AD4111
DIGITAL INTERFACE
The DOUT/RDY pin also functions as a data ready signal, with
the line going low if CS is low when a new data-word is available
in the data register. The pin is reset high when a read operation
from the data register is complete. The RDY output also goes high
before updating the data register to indicate when not to read
from the device to ensure that a data read is not attempted
while the register is being updated. Take care to avoid reading
from the data register when RDY is about to go low. The best
method to ensure that no data read occurs is to always monitor the
RDY output. Start reading the data register as soon as RDY
goes low, and ensure a sufficient SCLK rate, such that the read is
completed before the next conversion result. CS is used to select a
device. CS can be used to decode the AD4111 in systems where
several components are connected to the serial bus.
Figure 2 and Figure 3 show timing diagrams for interfacing to
the AD4111 using CS to decode the device. Figure 2 shows the
timing for a read operation from the AD4111, and Figure 3
shows the timing for a write operation to the AD4111. It is
possible to read from the data register several times, even though
the RDY output returns high after the first read operation.
However, take care to ensure that the read operations are
completed before the next output update occurs. In continuous
read mode, the data register can be read only once.
The serial interface can operate in 3-wire mode by tying CS
low. In this case, the SCLK, DIN, and DOUT/RDY lines are
used to communicate with the AD4111. The end of the
conversion can also be monitored using the RDY bit in the
status register.
CRC_ERROR bit is set in the status register. However, to
ensure that the register write was completed. It is important to
read back the register and verify the checksum.
For CRC checksum calculations during a write operation, the
following polynomial is always used:
x8 + x2 + x + 1
During read operations, the user can select between this
polynomial and a similar exclusive OR (XOR) function. The
XOR function requires less time to process on the host
microcontroller than the polynomial-based checksum. The
CRC_EN bits in the interface mode register enable and disable
the checksum and allow the user to select between the
polynomial check and the simple XOR check.
The checksum is appended to the end of each read and write
transaction. The checksum calculation for the write transaction
is calculated using the 8-bit command word and the 8-bit to 24bit data. For a read transaction, the checksum is calculated
using the command word and the 8-bit to 32-bit data output.
Figure 57 and Figure 58 show SPI write and read transactions,
respectively.
8-BIT COMMAND
UP TO 24-BIT INPUT
CMD
DATA
8-BIT CRC
CS
DIN
CRC
16640-157
The programmable functions of the AD4111 are accessible via
the SPI serial interface. The serial interface of the AD4111
consists of four signals: CS, DIN, SCLK, and DOUT/RDY. The
DIN line transfers data into the on-chip registers. The DOUT
output accesses data from the on-chip registers. SCLK is the serial
clock input for the device. All data transfers (either on DIN or on
DOUT) occur with respect to the SCLK signal.
SCLK
Figure 57. SPI Write Transaction with CRC
8-BIT COMMAND
UP TO 32-BIT OUTPUT
8-BIT CRC
CS
DIN
CHECKSUM PROTECTION
The AD4111 has a checksum mode that can be used to improve
interface robustness. Using the checksum ensures that only valid
data is written to a register and allows data read from a register
to be validated. If an error occurs during a register write, the
DOUT/
RDY
DATA
CRC
SCLK
16640-158
The serial interface can be reset by writing 64 SCLKs with CS =
0 and DIN = 1. A reset returns the interface to the state in which it
expects a write to the communications register. This operation
resets the contents of all registers to their power-on values.
Following a reset, allow a period of 500 µs before addressing the
serial interface.
CMD
Figure 58. SPI Read Transaction with CRC
If checksum protection is enabled when continuous read mode
is active, there is an implied read data command of 0x44 before
every data transmission that must be accounted for when
calculating the checksum value. The checksum protection ensures
a nonzero checksum value even if the ADC data equals
0x000000.
Rev. B | Page 39 of 59
AD4111
Data Sheet
CRC CALCULATION
Polynomial
The checksum, which is eight bits wide, is generated using the
following polynomial:
x8 + x2 + x + 1
To generate the checksum, the data is left shifted by eight bits
to create a number ending in eight Logic 0s. The polynomial is
aligned so that its MSB is adjacent to the leftmost Logic 1 of the
data. An exclusive OR (XOR) function is applied to the data to
produce a new, shorter number. The polynomial is again aligned
Initial value
so that its MSB is adjacent to the leftmost Logic 1 of the new
result, and the procedure is repeated. This process is repeated
until the original data is reduced to a value less than the
polynomial. This value is the 8-bit checksum.
Example of a Polynomial CRC Calculation—24-Bit Word:
0x654321 (Eight Command Bits and 16-Bit Data)
An example of generating the 8-bit checksum using the
polynomial-based checksum is as follows.
011001010100001100100001
x8 + x2 + x + 1 =
01100101010000110010000100000000
left shifted eight bits
100000111
polynomial
100100100000110010000100000000
XOR result
100000111
polynomial
100011000110010000100000000
XOR result
100000111
polynomial
11111110010000100000000
XOR result
100000111
polynomial value
1111101110000100000000
XOR result
100000111
polynomial value
111100000000100000000
XOR result
100000111
polynomial value
11100111000100000000
XOR result
100000111
polynomial value
1100100100100000000
XOR result
100000111
polynomial value
100101010100000000
XOR result
100000111
polynomial value
101101100000000
XOR result
100000111
polynomial value
1101011000000
XOR result
100000111
polynomial value
101010110000
XOR result
100000111
polynomial value
1010001000
XOR result
100000111
polynomial value
10000110
Rev. B | Page 40 of 59
checksum = 0x86.
Data Sheet
AD4111
XOR Calculation
The XOR calculation is then as follows:
The checksum, which is eight bits wide, is generated by
splitting the data into bytes and then performing an XOR of the
bytes.
01100101
0x65
01000011
0x43
00100110
XOR result
00100001
0x21
00000111
CRC
Example of an XOR Calculation—24-Bit Word: 0x654321
(Eight Command Bits and 16-Bit Data)
Using the example shown in the Polynomial section, divide the
checksum into three bytes: 0x65, 0x43, and 0x21.
Rev. B | Page 41 of 59
AD4111
Data Sheet
INTEGRATED FUNCTIONS
The AD4111 has a number of integrated functions.
clock cycle to ensure that synchronization occurs. If multiple
channels are enabled, the sequencer is reset to the first enabled
channel.
GENERAL-PURPOSE OUTPUTS
The AD4111 has two general-purpose digital output pins
(GPO0, GPO1). The GPO pins are enabled using the
OP_EN0_1 bit in the GPIOCON register.
The GP_DATA0 and GP_DATA1 bits determines the logic level
output at the pin, respectively. The logic levels for these pins are
referenced to AVDD and AVSS. Therefore, outputs have an
amplitude of either 5 V or 3.3 V depending on the AVDD −
AVSS voltage.
The ERROR pin can also be used as a general-purpose output
if the ERR_EN bits in the GPIOCON register are set to 11. In
this configuration, the ERR_DAT bit in the GPIOCON register
determines the logic level output at the ERROR pin. The logic
level for the pin is referenced to IOVDD and DGND, and the
ERROR pin has an active pull-up resistor.
DELAY
It is possible to insert a programmable delay before the AD4111
begins to take samples. This delay allows an external amplifier
or multiplexer to settle and can also alleviate the specification
requirements for the external amplifier or multiplexer. Eight
programmable settings, ranging from 0 μs to 8 ms, can be set using
the delay bits in the ADC mode register (Register 0x01, Bits[10:8]).
16-BIT/24-BIT CONVERSIONS
By default, the AD4111 generates 24-bit conversions. However,
the width of the conversions can be reduced to 16 bits. Setting
Bit WL16 in the interface mode register to 1 rounds all data
conversions to 16 bits. Clearing this bit sets the width of the
data conversions to 24 bits.
DOUT_RESET
The serial interface uses a shared DOUT/RDY pin. By default,
this pin outputs the RDY signal. During a data read, this pin
outputs the data from the register being read. After the read is
complete, the pin reverts to outputting the RDY signal after a short
fixed period of time (t7). However, this time may be too short for
some microcontrollers and can be extended until the CS pin is
brought high by setting the DOUT_RESET bit in the interface
mode register to 1. This setting means that CS must frame each
read operation and complete the serial interface transaction.
SYNCHRONIZATION
Normal Synchronization
When the SYNC_EN bit in the GPIOCON register is set to 1,
the SYNC pin functions as a synchronization pin. The SYNC
input allows the user to reset the modulator and the digital
filter without affecting any of the setup conditions on the
device. This reset allows the user to start gathering samples of
the analog input from a known point in time, that is, the rising
edge of SYNC. This pin must be low for at least one master
If multiple AD4111 devices are operated from a common
master clock, they can be synchronized so that their data
registers are updated simultaneously. Synchronization is
normally done after each AD4111 has performed its own
calibration or has calibration coefficients loaded into its
calibration registers. A falling edge on the SYNC pin resets the
digital filter and the analog modulator and places the AD4111
into a consistent known state. While the SYNC pin is low, the
AD4111 is maintained in this state. On the SYNC rising edge,
the modulator and filter are taken out of this reset state, and on
the next master clock edge, the device starts to gather input
samples again.
The device is taken out of reset on the master clock falling edge
following the SYNC low to high transition. Therefore, when
multiple devices are being synchronized, take the SYNC pin
high on the master clock rising edge to ensure that all devices
begin sampling on the master clock falling edge. If the SYNC
pin is not taken high in sufficient time, it is possible to have a
difference of one master clock cycle between the devices, that is,
the instant at which conversions are available differs from
device to device by a maximum of one master clock cycle.
The SYNC input can also be used as a start conversion command
for a single channel when in normal synchronization mode. In
this mode, the rising edge of the SYNC input starts a conversion,
and the falling edge of the RDY output indicates when the
conversion is complete. The settling time of the filter is required
for each data register update. After the conversion is complete,
bring the SYNC input low in preparation for the next conversion
start signal.
Alternate Synchronization
In alternate synchronization mode, the SYNC input operates as a
start conversion command when several channels of the AD4111
are enabled. Setting the ALT_SYNC bit in the interface mode
register to 1 enables an alternate synchronization scheme. When
the SYNC input is taken low, the ADC completes the conversion
on the enabled channel, selects the next channel in the sequence,
and then waits until the SYNC input is taken high to start the
conversion. The RDY output goes low when the conversion is
complete on the current channel, and the data register is updated
with the corresponding conversion. Therefore, the SYNC input
does not interfere with the sampling on the currently selected
channel but allows the user to control the instant at which the
conversion begins on the next channel in the sequence.
Alternate synchronization mode can be used only when several
channels are enabled. It is not recommended to use this mode
when a single channel is enabled.
Rev. B | Page 42 of 59
Data Sheet
AD4111
ERROR FLAGS
component. The value on the ERROR input is inverted and OR’ed
with the errors from the ADC conversion, and the result is
indicated via the ADC_ERROR bit in the status register. The value
of the ERROR input is reflected in the ERR_DAT bit in the
GPIO configuration register.
The status register contains three error bits (ADC_ERROR,
CRC_ERROR, and REG_ERROR) that flag errors with the
ADC conversion, errors with the CRC check, and errors caused
by changes in the registers, respectively. In addition, the
ERROR output can indicate that an error has occurred.
ADC_ERROR
The ADC_ERROR bit in the status register flags any errors that
occur during the conversion process. The flag is set when an overrange or underrange result is output from the ADC. The ADC
also outputs all 0s or all 1s when an undervoltage or overvoltage
occurs. This flag is reset only when the overvoltage or undervoltage
is removed. This flag is not reset by a read of the data register.
CRC_ERROR
If the CRC value that accompanies a write operation does not
correspond with the information sent, the CRC_ERROR flag is
set. The flag is reset as soon as the status register is explicitly read.
REG_ERROR
The REG_ERROR flag is used in conjunction with the
REG_CHECK bit in the interface mode register. When the
REG_CHECK bit is set, the AD4111 monitors the values in
the on-chip registers. If a bit changes, the REG_ERROR bit is
set to 1. Therefore, for writes to the on-chip registers, set the
REG_CHECK bit to 0. When the registers have been updated,
the REG_CHECK bit can be set to 1. The AD4111 calculates a
checksum of the on-chip registers. If one of the register values
has changed, the REG_ERROR bit is set to 1. If an error is
flagged, the REG_CHECK bit must be set to 0 to clear the
REG_ERROR bit in the status register. The register check
function does not monitor the data register, status register, or
interface mode register.
ERROR Input/Output
The ERROR pin functions as an error input/output pin or as a
general-purpose output pin. The ERR_EN bits in the GPIOCON
register determine the function of the pin.
When ERR_EN is set to 10, the ERROR pin functions as an
open-drain error output. The three error bits in the status
register (ADC_ERROR, CRC_ERROR, and REG_ERROR) are
OR’ed, inverted, and mapped to the ERROR output. Therefore, the
ERROR output indicates that an error has occurred. The status
register must be read to identify the error source.
When ERR_EN is set to 01, the ERROR pin functions as an
error input. The error output of another component can be
connected to the AD4111 ERROR input so that the AD4111
indicates when an error occurs on either itself or the external
The ERROR input/output is disabled when ERR_EN is set to 00.
When the ERR_EN bits are set to 11, the ERROR pin operates as
a general-purpose output where the ERR_DAT bit is used to
determine the logic level of the pin.
DATA_STAT
The contents of the status register can be appended to each
conversion on the AD4111 using the DATA_STAT bit in the
IFMODE register. This function is useful if several channels are
enabled. Each time a conversion is output, the contents of the
status register are appended. The four LSBs of the status
register indicate to which channel the conversion corresponds.
In addition, the user can determine if any errors are being
flagged by the error bits.
IOSTRENGTH
The serial interface can operate with a power supply as low as
2 V. However, at this low voltage, the DOUT/RDY pin may not
have sufficient drive strength if there is moderate parasitic
capacitance on the board or if the SCLK frequency is high. The
IOSTRENGTH bit in the interface mode register increases the
drive strength of the DOUT/RDY pin.
INTERNAL TEMPERATURE SENSOR
The AD4111 has an integrated temperature sensor. The
temperature sensor can be used as a guide for the ambient
temperature at which the device is operating. The ambient
temperature can be used for diagnostic purposes or as an
indicator of when the application circuit must rerun a
calibration routine to take into account a shift in operating
temperature. The temperature sensor is selected using the
multiplexer and is selected in the same way as an input channel.
The temperature sensor requires that the input buffers be enabled
on both inputs and the internal reference be enabled.
To use the temperature sensor, the first step is to calibrate the
device in a known temperature (25°C) and take a conversion as a
reference point. The temperature sensor has a nominal sensitivity
of 477 μV/K. The difference in this ideal slope and the slope
measured can calibrate the temperature sensor. The temperature
sensor is specified with a ±2°C typical accuracy after calibration
at 25°C. Calculate the temperature as follows:
Temperature (°C) = (Conversion Result ÷ 477 µV) − 273.15
Rev. B | Page 43 of 59
AD4111
Data Sheet
APPLICATIONS INFORMATION
IEC61000-4-x AND CISPR 11 ROBUSTNESS
PLC and DCS modules often operate in harsh industrial
environments and must survive electromagnetic interference
(EMI) conditions. To aid the design of electromagnetic
compatibility (EMC) capable solutions, the AN-1572
Applications Note is available. AN-1572 details all necessary
information on the test procedures used, as well as the layout
and board design schematics necessary to design an EMC
proven input module for the AD4111. The board ensures that
the circuit performance is not permanently affected by radiated
radio frequency (RF) or conducted RF disturbances and has
sufficient immunity against electrostatic discharge (ESD),
electrical fast transients (EFT), and surge as per the IEC610004-x standards. The AD4111 was also evaluated for CISPR 11,
where the radiated emissions for the board are less than the
Class A limits.
GROUNDING AND LAYOUT
The inputs and reference inputs are differential and, therefore,
most of the voltages in the analog modulator are common-mode
voltages. The high common-mode rejection of the device removes
common-mode noise on these inputs. The analog and digital
supplies to the AD4111 are independent and separately pinned
out to minimize coupling between the analog and digital sections
of the device. The digital filter provides rejection of broadband
noise on the power supplies, except at integer multiples of the
master clock frequency.
The digital filter also removes noise from the analog inputs and
reference inputs, provided that these noise sources do not
saturate the analog modulator. As a result, the AD4111 is more
immune to noise interference than a conventional high
resolution converter. However, because the resolution of the
AD4111 is high and the noise levels from the converter are so
low, take care with regard to grounding and layout.
The PCB that houses the ADC must be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. A minimum etch technique is
generally best for ground planes because it results in the best
shielding.
In any layout, the user must keep in mind the flow of currents
in the system, ensuring that the paths for all return currents are as
close as possible to the paths the currents took to reach their
destinations.
Avoid running digital lines under the device because this
couples noise onto the die and allows the analog ground plane
to run under the AD4111 to prevent noise coupling. The power
supply lines to the AD4111 must use as wide a trace as possible
to provide low impedance paths and reduce glitches on the
power supply line. Shield fast switching signals like clocks with
digital ground to prevent radiating noise to other sections of
the board and never run clock signals near the inputs. Avoid
crossover of digital and analog signals. Run traces on opposite
sides of the board at right angles to each other. This layout
reduces the effects of feedthrough on the board. A microstrip
technique is by far the best but is not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground planes, whereas signals are
placed on the solder side.
Proper decoupling is important when using high resolution ADCs.
The AD4111 has two power supply pins: AVDD and IOVDD.
The AVDD pin is referenced to AVSS, and the IOVDD pin is
referenced to DGND. Decouple AVDD with a 10 µF tantalum
capacitor in parallel with a 0.1 µF capacitor to AVSS on each
pin. Place the 0.1 µF capacitor as near as possible to the device
on each supply, ideally right up against the device. Decouple
IOVDD with a 10 µF tantalum capacitor, in parallel with a 0.1 µF
capacitor to DGND. Decouple all inputs to AVSS. If an external
reference is used, decouple the REF+ and REF− pins to AVSS.
The AD4111 also has two on-board LDO regulators: one that
regulates the AVDD supply, and one that regulates the IOVDD
supply. For the REGCAPA pin, it is recommended that 1 µF
and 0.1 µF capacitors to AVSS be used. Similarly, for the
REGCAPD pin, it is recommended that 1 µF and 0.1 µF
capacitors to DGND be used.
Rev. B | Page 44 of 59
Data Sheet
AD4111
REGISTER SUMMARY
Table 23. Register Summary
Reg. Name
0x00 COMMS
Bits
[7:0]
Bit 7
WEN
Bit 6
R/W
0x00 Status
[7:0]
RDY
ADC_ERROR CRC_ERROR REG_ERROR
Channel
REF_EN
Reserved
Reserved
Delay
0x2000 RW
Reserved
Reserved
DOUT_RESET 0x0000 RW
Reserved
WL16
0x000000 R
0x01 ADCMODE [15:8]
[7:0]
0x02 IFMODE
[15:8]
[7:0]
0x03 REGCHECK [23:16]
[15:8]
[7:0]
0x04 Data
[23:16]
[15:8]
[7:0]
0x06 GPIOCON [15:8]
[7:0]
0x07 ID
[15:8]
[7:0]
0x10 CH0
[15:8]
[7:0]
0x11 CH1
[15:8]
[7:0]
0x12 CH2
[15:8]
[7:0]
0x13 CH3
[15:8]
[7:0]
0x14 CH4
[15:8]
[7:0]
0x15 CH5
[15:8]
[7:0]
0x16 CH6
[15:8]
[7:0]
0x17 CH7
[15:8]
[7:0]
0x18 CH8
[15:8]
[7:0]
0x19 CH9
[15:8]
[7:0]
0x1A CH10
[15:8]
[7:0]
0x1B CH11
[15:8]
[7:0]
0x1C CH12
[15:8]
[7:0]
0x1D CH13
[15:8]
[7:0]
0x1E CH14
[15:8]
[7:0]
0x1F CH15
[15:8]
[7:0]
0x20 SETUPCON0 [15:8]
[7:0]
0x21 SETUPCON1 [15:8]
[7:0]
CONTREAD
Reserved
GP_DATA1
Reserved
DATA_STAT
Reserved
GP_DATA0
CH_EN0
CH_EN1
CH_EN2
CH_EN3
CH_EN4
CH_EN5
CH_EN6
CH_EN7
CH_EN8
CH_EN9
CH_EN10
CH_EN11
CH_EN12
CH_EN13
CH_EN14
CH_EN15
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RA
SING_CYC
Mode
Reserved
CLOCKSEL
ALT_SYNC
IOSTRENGTH
REG_CHECK Reserved
CRC_EN
REGISTER_CHECK[23:16]
REGISTER_CHECK[15:8]
REGISTER_CHECK[7:0]
Data [23:16]
Data [15:8]
Data [7:0]
OP_EN0_1 OW_EN
SYNC_EN
ERR_EN
Reserved
ID[15:8]
ID[7:0]
SETUP_SEL0
Reserved
INPUT0[7:0]
SETUP_SEL1
Reserved
INPUT1[7:0]
SETUP_SEL2
Reserved
INPUT2[7:0]
SETUP_SEL3
Reserved
INPUT3[7:0]
SETUP_SEL4
Reserved
INPUT4[7:0]
SETUP_SEL5
Reserved
INPUT5[7:0]
SETUP_SEL6
Reserved
INPUT6[7:0]
SETUP_SEL7
Reserved
INPUT7[7:0]
SETUP_SEL8
Reserved
INPUT8[7:0]
SETUP_SEL9
Reserved
INPUT9[7:0]
SETUP_SEL10
Reserved
Input10[7:0]
SETUP_SEL11
Reserved
INPUT11[7:0]
SETUP_SEL12
Reserved
INPUT12[7:0]
SETUP_SEL13
Reserved
INPUT13[7:0]
SETUP_SEL14
Reserved
INPUT14[7:0]
SETUP_SEL15
Reserved
INPUT15[7:0]
BI_UNIPOLAR0 REFBUF0+
REFBUF0−
REF_SEL0
Reserved
BI_UNIPOLAR1 REFBUF1+
REFBUF1−
REF_SEL1
Reserved
Rev. B | Page 45 of 59
Reset
0x00
RW
W
0x80
R
0x000000 R
ERR_DAT
0x0800
RW
0x30Dx
R
INPUT0[9:8]
0x8001
RW
INPUT1[9:8]
0x0001
RW
INPUT2[9:8]
0x0001
RW
INPUT3[9:8]
0x0001
RW
INPUT4[9:8]
0x0001
RW
INPUT5[9:8]
0x0001
RW
INPUT6[9:8]
0x0001
RW
INPUT7[9:8]
0x0001
RW
INPUT8[9:8]
0x0001
RW
INPUT9[9:8]
0x0001
RW
INPUT10[9:8]
0x0001
RW
INPUT11[9:8]
0x0001
RW
INPUT12[9:8]
0x0001
RW
INPUT13[9:8]
0x0001
RW
INPUT14[9:8]
0x0001
RW
INPUT15[9:8]
0x0001
RW
INBUF0
0x1000
RW
INBUF1
0x1000
RW
AD4111
Reg. Name
Bits
0x22 SETUPCON2 [15:8]
[7:0]
0x23 SETUPCON3 [15:8]
[7:0]
0x24 SETUPCON4 [15:8]
[7:0]
0x25 SETUPCON5 [15:8]
[7:0]
0x26 SETUPCON6 [15:8]
[7:0]
0x27 SETUPCON7 [15:8]
[7:0]
0x28 FILTCON0 [15:8]
[7:0]
0x29 FILTCON1 [15:8]
[7:0]
0x2A FILTCON2 [15:8]
[7:0]
0x2B FILTCON3 [15:8]
[7:0]
0x2C FILTCON4 [15:8]
[7:0]
0x2D FILTCON5 [15:8]
[7:0]
0x2E FILTCON6 [15:8]
[7:0]
0x2F FILTCON7 [15:8]
[7:0]
0x30 OFFSET0
[23:0]
0x31 OFFSET1
[23:0]
0x32 OFFSET2
[23:0]
0x33 OFFSET3
[23:0]
0x34 OFFSET4
[23:0]
0x35 OFFSET5
[23:0]
0x36 OFFSET6
[23:0]
0x37 OFFSET7
[23:0]
0x38 GAIN0
[23:0]
0x39 GAIN1
[23:0]
0x3A GAIN2
[23:0]
0x3B GAIN3
[23:0]
0x3C GAIN4
[23:0]
0x3D GAIN5
[23:0]
0x3E GAIN6
[23:0]
0x3F GAIN7
[23:0]
Data Sheet
Bit 7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SINC3_MAP0
Reserved
SINC3_MAP1
Reserved
SINC3_MAP2
Reserved
SINC3_MAP3
Reserved
SINC3_MAP4
Reserved
SINC3_MAP5
Reserved
SINC3_MAP6
Reserved
SINC3_MAP7
Reserved
Bit 6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 5
Bit 4
Bit 3
BI_UNIPOLAR2 REFBUF2+
REF_SEL2
BI_UNIPOLAR3 REFBUF3+
REF_SEL3
BI_UNIPOLAR4 REFBUF4+
REF_SEL4
BI_UNIPOLAR5 REFBUF5+
REF_SEL5
BI_UNIPOLAR6 REFBUF6+
REF_SEL6
BI_UNIPOLAR7 REFBUF7+
REF_SEL7
Reserved
ENHFILTEN0
ORDER0
Reserved
ENHFILTEN1
ORDER1
Reserved
ENHFILTEN2
ORDER2
Reserved
ENHFILTEN3
ORDER3
Reserved
ENHFILTEN4
ORDER4
Reserved
ENHFILTEN5
ORDER5
Reserved
ENHFILTEN6
ORDER6
Reserved
ENHFILTEN7
ORDER7
OFFSET0[23:0]
OFFSET1[23:0]
OFFSET2[23:0]
OFFSET3[23:0]
OFFSET4[23:0]
OFFSET5[23:0]
OFFSET6[23:0]
OFFSET7[23:0]
GAIN0[23:0]
GAIN1[23:0]
GAIN2[23:0]
GAIN3[23:0]
GAIN4[23:0]
GAIN5[23:0]
GAIN6[23:0]
GAIN7[23:0]
Rev. B | Page 46 of 59
Bit 2
Bit 1
Bit 0
REFBUF2−
INBUF2
Reserved
REFBUF3−
INBUF3
Reserved
REFBUF4−
INBUF4
Reserved
REFBUF5−
INBUF5
Reserved
REFBUF6−
INBUF6
Reserved
REFBUF7−
INBUF7
Reserved
ENHFILT0
ODR0
ENHFILT1
ODR1
ENHFILT2
ODR2
ENHFILT3
ODR3
ENHFILT4
ODR4
ENHFILT5
ODR5
ENHFILT6
ODR6
ENHFILT7
ODR7
Reset
0x1000
RW
RW
0x1000
RW
0x1000
RW
0x1000
RW
0x1000
RW
0x1000
RW
0x0500
RW
0x0500
RW
0x0500
RW
0x0500
RW
0x0500
RW
0x0500
RW
0x0500
RW
0x0500
RW
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Data Sheet
AD4111
REGISTER DETAILS
COMMUNICATIONS REGISTER
Address: 0x00, Reset: 0x00, Name: COMMS
All access to the on-chip registers must start with a write to the communications register. This write determines which register is
accessed next and whether that operation is a write or a read.
Table 24. Bit Descriptions for COMMS
Bits
7
Bit Name
WEN
6
R/W
Settings
0
1
[5:0]
RA
000000
000001
000010
000011
000100
000110
000111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
Description
This bit must be low to begin communications with the ADC
Reset
0x0
Access
W
This bit determines if the command is a read or write operation
Write command
Read command
The register address bits determine the register to be read from or
written to as part of the current communication
Status register
ADC mode register
Interface mode register
Register checksum register
Data register
GPIO configuration register
ID register
Channel 0 register
Channel 1 register
Channel 2 register
Channel 3 register
Channel 4 register
Channel 5 register
Channel 6 register
Channel 7 register
Channel 8 register
Channel 9 register
Channel 10 register
Channel 11 register
Channel 12 register
Channel 13 register
Channel 14 register
Channel 15 register
Setup Configuration 0 register
Setup Configuration 1 register
Setup Configuration 2 register
Setup Configuration 3 register
Setup Configuration 4 register
Setup Configuration 5 register
Setup Configuration 6 register
Setup Configuration 7 register
Filter Configuration 0 register
Filter Configuration 1 register
Filter Configuration 2 register
Filter Configuration 3 register
Filter Configuration 4 register
Filter Configuration 5 register
Filter Configuration 6 register
Filter Configuration 7 register
0x0
W
0x00
W
Rev. B | Page 47 of 59
AD4111
Bits
Bit Name
Data Sheet
Settings
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Description
Offset 0 register
Offset 1 register
Offset 2 register
Offset 3 register
Offset 4 register
Offset 5 register
Offset 6 register
Offset 7 register
Gain 0 register
Gain 1 register
Gain 2 register
Gain 3 register
Gain 4 register
Gain 5 register
Gain 6 register
Gain 7 register
Reset
Access
STATUS REGISTER
Address: 0x00, Reset: 0x80, Name: Status
The status register is an 8-bit register that contains ADC and serial interface status information. The register can optionally be appended
to the data register by setting the DATA_STAT bit in the interface mode register.
Table 25. Bit Descriptions for STATUS
Bits
7
Bit Name
RDY
Settings
0
1
6
ADC_ERROR
0
1
5
CRC_ERROR
0
1
4
REG_ERROR
0
1
Description
The status of RDY is output to the DOUT/RDY pin when CS is low and a
register is not being read. This bit goes low when the ADC writes a new
result to the data register. In ADC calibration modes, this bit goes low
when the ADC writes the calibration result. RDY is brought high
automatically by a read of the data register.
New data result available.
Awaiting new data result.
By default, this bit indicates if an ADC overrange or underrange occurred.
The ADC result is clamped to 0xFFFFFF for overrange errors and 0x000000
for underrange errors. This bit is updated when the ADC result is written
and is cleared at the next update after removing the overrange or
underrange condition.
No error.
Error.
This bit indicates if a CRC error occurred during a register write. For
register reads, the host microcontroller determines if a CRC error
occurred. This bit is cleared by a read of this register.
No error.
CRC error.
This bit indicates if the content of one of the internal registers changes
from the value calculated when the register integrity check is activated.
The check is activated by setting the REG_CHECK bit in the interface
mode register. This bit is cleared by clearing the REG_CHECK bit.
No error.
Error.
Rev. B | Page 48 of 59
Reset
0x1
Access
R
0x0
R
0x0
R
0x0
R
Data Sheet
Bits
[3:0]
Bit Name
Channel
AD4111
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
These bits indicate which channel was active for the ADC conversion
whose result is currently in the data register. This may be different from
the channel currently being converted. The mapping is a direct map from
the channel register. Therefore, Channel 0 results in 0x0 and Channel 15
results in 0xF.
Channel 0.
Channel 1.
Channel 2.
Channel 3.
Channel 4.
Channel 5.
Channel 6.
Channel 7.
Channel 8.
Channel 9.
Channel 10.
Channel 11.
Channel 12.
Channel 13.
Channel 14.
Channel 15.
Reset
0x0
Access
R
ADC MODE REGISTER
Address: 0x01, Reset: 0x2000, Name: ADCMODE
The ADC mode register controls the operating mode of the ADC and the master clock selection. A write to the ADC mode register resets
the filter and the RDY bits and starts a new conversion or calibration.
Table 26. Bit Descriptions for ADCMODE
Bits
15
Bit Name
REF_EN
Settings
0
1
14
13
Reserved
SING_CYC
0
1
[12:11]
[10:8]
Reserved
Delay
000
001
010
011
100
101
110
111
7
Reserved
Description
Enables internal reference and outputs a buffered 2.5 V to the REFOUT
pin.
Disabled.
Enabled.
This bit is reserved. Set this bit to 0.
This bit can be used when only a single channel is active to set the ADC to
only output at the settled filter data rate.
Disabled.
Enabled.
These bits are reserved. Set these bits to 0.
These bits allow a programmable delay to be added after a channel
switch to allow the settling of external circuitry before the ADC starts
processing its input.
0 µs.
32 µs.
128 µs.
320 µs.
800 µs.
1.6 ms.
4 ms.
8 ms.
This bit is reserved. Set this bit to 0.
Rev. B | Page 49 of 59
Reset
0x0
Access
RW
0x0
0x1
RW
RW
0x0
0x0
R
RW
0x0
R
AD4111
Bits
[6:4]
Bit Name
Mode
Data Sheet
Settings
000
001
010
011
100
101
110
111
[3:2]
CLOCKSEL
00
01
10
11
[1:0]
Reserved
Description
These bits control the operating mode of the ADC. See the Operating
Modes section for more information.
Continuous conversion mode.
Single conversion mode.
Standby mode.
Power-down mode.
Internal offset calibration.
Internal gain calibration
System offset calibration.
System gain calibration.
These bits select the ADC clock source. Selecting the internal oscillator
also enables the internal oscillator.
Internal oscillator.
Internal oscillator output on the XTAL2/CLKIO pin.
External clock input on the XTAL2/CLKIO pin.
External crystal on the XTAL1 pin and the XTAL2/CLKIO pin.
These bits are reserved; set these bits to 0.
Reset
0x0
Access
RW
0x0
RW
0x0
R
Reset
0x0
0x0
Access
R
RW
0x0
RW
0x0
0x0
R
RW
0x0
RW
0x0
RW
INTERFACE MODE REGISTER
Address: 0x02, Reset: 0x0000, Name: IFMODE
The interface mode register configures various serial interface options.
Table 27. Bit Descriptions for IFMODE
Bits
[15:13]
12
Bit Name
Reserved
ALT_SYNC
Settings
0
1
11
IOSTRENGTH
0
1
[10:9]
8
Reserved
DOUT_RESET
0
1
7
CONTREAD
0
1
6
DATA_STAT
0
1
Description
These bits are reserved; set these bits to 0.
This bit enables a different behavior of the SYNC pin to allow the use of
SYNC as a control for conversions when cycling channels
Disabled.
Enabled.
This bit controls the drive strength of the DOUT/RDY pin. Set this bit when
reading from the serial interface at high speed with a low IOVDD supply
and moderate capacitance.
Disabled (default).
Enabled.
These bits are reserved; set these bits to 0.
See the DOUT_RESET section
Disabled.
Enabled.
This bit enables the continuous read mode of the ADC data register. The ADC
must be configured in continuous conversion mode to use continuous
read mode. For more details, see the Operating Modes section.
Disabled.
Enabled.
This bit enables the status register to be appended to the data register
when read so that channel and status information are transmitted with
the data. This is the only way to be sure that the channel bits read from
the status register correspond to the data in the data register.
Disabled.
Enabled.
Rev. B | Page 50 of 59
Data Sheet
Bits
5
Bit Name
REG_CHECK
AD4111
Settings
0
1
4
[3:2]
Reserved
CRC_EN
00
01
10
1
0
Reserved
WL16
0
1
Description
This bit enables a register integrity checker, which can be used to monitor
any change in the value of the user registers. To use this feature,
configure all other registers as desired with this bit cleared. Then, write to this
register to set the REG_CHECK bit to 1. If the contents of any of the
registers change, the REG_ERROR bit is set in the status register. To clear the
error, set the REG_CHECK bit to 0. Neither the interface mode register nor
the ADC data or status registers are included in the registers that are checked.
If a register must have a new value written, this bit must first be cleared;
otherwise, an error is flagged when the new register contents are written.
Disabled.
Enabled.
This bit is reserved. Set this bit to 0.
These bits enable CRC protection of register reads/writes. CRC increases
the number of bytes in a serial interface transfer by one.
Disabled
XOR checksum enabled for register read transactions; register writes still
use CRC with these bits set.
CRC checksum enabled for read and write transactions.
This bit is reserved. Set this bit to 0.
This bit changes the ADC data register to 16 bits. The ADC is not reset by a
write to the interface mode register; therefore, the ADC result is not
rounded to the correct word length immediately after writing to these
bits. The first new ADC result is correct.
24-bit data.
16-bit data.
Reset
0x0
Access
RW
0x0
0x00
R
RW
0x0
0x0
R
RW
REGISTER CHECK
Address: 0x03, Reset: 0x000000, Name: REGCHECK
The register check register is a 24-bit checksum calculated by exclusively OR'ing the contents of the user registers. The REG_CHECK bit
in the interface mode register must be set for this checksum to operate; otherwise, the register reads 0.
Table 28. Bit Descriptions for REGCHECK
Bits
[23:0]
Bit Name
REGISTER_CHECK
Settings
Description
This register contains the 24-bit checksum of user registers when the
REG_CHECK bit is set in the interface mode register.
Reset
0x000000
Access
R
DATA REGISTER
Address: 0x04, Reset: 0x000000, Name: Data
The data register contains the ADC conversion result. The encoding is offset binary, or it can be changed to unipolar by the BI_UNIPOLARx
bits in the setup configuration registers. Reading the data register brings the RDY bit and the RDY output high if it is low. The ADC
result can be read multiple times. However, because the RDY output is brought high, it is not possible to determine if another ADC result is
imminent. After the command to read the ADC register is received, the ADC does not write a new result into the data register.
Table 29. Bit Descriptions for Data
Bits
[23:0]
Bit Name
Data
Settings
Description
This register contains the ADC conversion result. If DATA_STAT is set in
the interface mode register, the status register is appended to this
register when read, making this a 32-bit register. If WL16 is set in the
interface mode register, this register is reduced to 16 bits.
Rev. B | Page 51 of 59
Reset
0x000000
Access
R
AD4111
Data Sheet
GPIO CONFIGURATION REGISTER
Address: 0x06, Reset: 0x0800, Name: GPIOCON
The GPIO configuration register controls the general-purpose I/O pins of the ADC.
Table 30. Bit Descriptions for GPIOCON
Bits
[15:14]
13
Bit Name
Reserved
OP_EN0_1
Settings
0
1
12
OW_EN
0
1
11
SYNC_EN
0
1
[10:9]
ERR_EN
00
01
10
11
8
ERR_DAT
0
1
7
GP_DATA1
0
1
6
GP_DATA0
0
1
[5:0]
Reserved
Description
Reserved.
GPO0/GPO1 output enable. This bit enables the GPO0 and GPO1 pins. The outputs
are referenced between AVDD and AVSS.
Disabled.
Enabled.
This bit enables the use of open wire detection of voltage channels.
Disabled.
Enabled.
SYNC input enable. This bit enables the SYNC pin as a sync input. When set low, the
SYNC pin holds the ADC and filter in reset until SYNC goes high. An alternative
operation of the SYNC pin is available when the ALT_SYNC bit in the interface mode
register is set. This mode works only when multiple channels are enabled. In such cases, a
low on the SYNC pin does not immediately reset the filter/modulator. Instead, if the
SYNC pin is low when the channel is due to be switched, the modulator and filter
are prevented from starting a new conversion. Bringing SYNC high begins the next
conversion. This alternative sync mode allows SYNC to be used while cycling
through channels.
Disabled.
Enabled.
Error pin mode. These bits enable the ERROR pin as an error input/output.
Disabled.
Enable error input (active low). ERROR is an error input. The (inverted) readback
state is OR'ed with other error sources and is available in the ADC_ERROR bit in the
status register. The ERROR pin state can also be read from the ERR_DAT bit in this
register.
Enable open-drain error output (active low). ERROR is an open-drain error output.
The status register error bits are OR'ed, inverted, and mapped to the ERROR pin.
ERROR pins of multiple devices can be wired together to a common pull-up resistor
so that an error on any device can be observed.
General-purpose output (active low). ERROR is a general-purpose output. The status
of the pin is controlled by the ERR_DAT bit in this register. This output is referenced
between IOVDD and DGND, as opposed to the AVDD1 and AVSS levels used by the
GPIOx pins. The output has an active pull-up resistor in this case.
Error pin data. This bit determines the logic level at the ERROR pin if the pin is
enabled as a general-purpose output. This bit reflects the readback status of the pin
if the pin is enabled as an input.
Logic 0.
Logic 1.
GPO1 data. This bit is the write data for GPO1.
GPO1 = 0.
GPO1 = 1.
GPO0 data. This bit is the write data for GPO0.
GPO0 = 0.
GPO0 = 1.
Reserved.
Rev. B | Page 52 of 59
Reset
0x0
0x0
Access
R
R/W
0x0
R/W
0x1
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R
Data Sheet
AD4111
ID REGISTER
Address: 0x07, Reset: 0x30DX, Name: ID
The ID register returns a 16-bit ID. For the AD4111, this value is 0x30DX.
Table 31. Bit Descriptions for ID
Bits
[15:0]
Bit Name
ID
Settings
Description
Product ID. The ID register returns a 16-bit ID code that is specific to the ADC.
Reset
0x30DX
Access
R
CHANNEL REGISTER 0
Address: 0x10, Reset: 0x8001, Name: CH0
The channel registers are 16-bit registers that select the currently active channels, the selected inputs for each channel, and the setup to
be used to configure the ADC for that channel.
Table 32. Bit Descriptions for CH0
Bits
15
Bit Name
CH_EN0
Settings
0
1
[14:12]
SETUP_SEL0
000
001
010
011
100
101
110
111
[11:10]
[9:0]
Reserved
INPUT0
0000000001
0000010000
0000100000
0000110000
0001000011
0001010000
0001100010
0001110000
0010000101
0010010000
0010100100
0010110000
0011000111
0011010000
0011100110
0011110000
0110001011
0110101010
0111001001
Description
This bit enables Channel 0. If more than one channel is enabled, the ADC
automatically sequences between them.
Disabled.
Enabled.
These bits identify which of the eight setups is used to configure the ADC for
this channel. A setup comprises a set of four registers: a setup configuration register,
a filter configuration register, an offset register, and a gain register. All channels can
use the same setup, in which case the same 3-bit value must be written to these
bits on all active channels, or up to eight channels can be configured differently.
Setup 0.
Setup 1.
Setup 2.
Setup 3.
Setup 4.
Setup 5.
Setup 6.
Setup 7.
Reserved.
These bits select which input pair is connected to the input of the ADC for this
channel.
VIN0, VIN1.
VIN0, VINCOM.
VIN1, VIN0.
VIN1, VINCOM.
VIN2, VIN3.
VIN2, VINCOM.
VIN3, VIN2.
VIN3, VINCOM.
VIN4, VIN5.
VIN4, VINCOM.
VIN5, VIN4.
VIN5, VINCOM.
VIN6, VIN7.
VIN6, VINCOM.
VIN7, VIN6.
VIN7, VINCOM.
IIN3+, IIN3−.
IIN2+, IIN2−.
IIN1+, IIN1−.
Rev. B | Page 53 of 59
Reset
0x1
Access
R/W
0x0
R/W
0x0
0x1
R
R/W
AD4111
Bits
Bit Name
Data Sheet
Settings
0111101000
1000110010
1010110110
Description
IIN0+, IIN0−.
Temperature sensor.
Reference.
Reset
Access
CHANNEL REGISTER 1 TO CHANNEL REGISTER 15
Address: 0x11 to Address 0x1F, Reset: 0x0001, Name: CH1 to CH7
The remaining 15 channel registers share the same layout as Channel Register 0.
Table 33. CH1 to CH15 Register Map
Reg.
0x11
Name
CH1
0x12
CH2
0x13
CH3
0x14
CH4
0x15
CH5
0x16
CH6
0x17
CH7
0x18
CH8
0x19
CH9
0x1A
CH10
0x1B
CH11
0x1C
CH12
0x1D
CH13
0x1E
CH14
0x1F
CH15
Bits
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
Bit 7
CH_EN1
CH_EN2
CH_EN3
CH_EN4
CH_EN5
CH_EN6
CH_EN7
CH_EN8
CH_EN9
CH_EN10
CH_EN11
CH_EN12
CH_EN13
CH_EN14
CH_EN15
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
SETUP_SEL1
Reserved
INPUT1[7:0]
SETUP_SEL2
Reserved
INPUT2[7:0]
SETUP_SEL3
Reserved
INPUT3[7:0]
SETUP_SEL4
Reserved
INPUT4[7:0]
SETUP_SEL5
Reserved
INPUT5[7:0]
SETUP_SEL6
Reserved
INPUT6[7:0]
SETUP_SEL7
Reserved
INPUT7[7:0]
SETUP_SEL8
Reserved
INPUT8[7:0]
SETUP_SEL9
Reserved
INPUT9[7:0]
SETUP_SEL10
Reserved
INPUT10[7:0]
SETUP_SEL11
Reserved
INPUT11[7:0]
SETUP_SEL12
Reserved
INPUT12[7:0]
SETUP_SEL13
Reserved
INPUT13[7:0]
SETUP_SEL14
Reserved
INPUT14[7:0]
SETUP_SEL15
Reserved
INPUT15[7:0]
Rev. B | Page 54 of 59
Bit 1
Bit 0
INPUT1[9:8]
Reset
0x0001
RW
RW
INPUT2[9:8]
0x0001
RW
INPUT3[9:8]
0x0001
RW
INPUT4[9:8]
0x0001
RW
INPUT5[9:8]
0x0001
RW
INPUT6[9:8]
0x0001
RW
INPUT7[9:8]
0x0001
RW
INPUT8[9:8]
0x0001
RW
INPUT9[9:8]
0x0001
RW
INPUT10[9:8]
0x0001
RW
INPUT11[9:8]
0x0001
RW
INPUT12[9:8]
0x0001
RW
INPUT13[9:8]
0x0001
RW
INPUT14[9:8]
0x0001
RW
INPUT15[9:8]
0x0001
RW
Data Sheet
AD4111
SETUP CONFIGURATION REGISTER 0
Address: 0x20, Reset: 0x1000 Name: SETUPCON0
The setup configuration registers are 16-bit registers that configure the reference selection, input buffers, and output coding of the ADC.
Table 34. Bit Descriptions for SETUPCON0
Bits
[15:13]
12
Bit Name
Reserved
BI_UNIPOLAR0
Settings
0
1
11
REFBUF0+
0
1
10
REFBUF0−
0
1
[9:8]
INBUF0
00
01
10
11
7
6
[5:4]
Reserved
Reserved
REF_SEL0
00
10
11
[3:0]
Reserved
Description
These bits are reserved; set these bits to 0.
Bipolar/unipolar. This bit sets the output coding of the ADC for Setup 0.
Unipolar coded output.
Bipolar coded output.
REF+ buffer. This bit enables or disables the REF+ input buffer.
Disabled.
Enabled.
REF− buffer. This bit enables or disables the REF− input buffer.
Disabled.
Enabled.
Input buffer. This bit enables or disables input buffers.
Disabled.
Reserved.
Reserved.
Enabled.
This bit is reserved. Set this bit to 0.
This bit is reserved. Set this bit to 0.
These bits allow the user to select the reference source for ADC conversion on
Setup 0.
External reference − REF±.
Internal 2.5 V reference, must be enabled via ADCMODE (see Table 26).
AVDD − AVSS.
These bits are reserved. Set these bits to 0.
Reset
0x0
0x1
Access
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
0x0
R
R
R/W
0x0
R
SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7
Address: 0x21 to Address 0x27, Reset: 0x1000, Name: SETUPCON1 to SETUPCON7
The remaining seven setup configuration registers share the same layout as Setup Configuration Register 0.
Table 35. SETUPCON1 to SETUPCON7 Register Map
Reg.
0x21
Name
SETUPCON1
0x22
SETUPCON2
0x23
0x24
0x25
0x26
0x27
SETUPCON3
SETUPCON4
SETUPCON5
SETUPCON6
SETUPCON7
Bits
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
Bit 7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 6
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 5 Bit 4
BI_UNIPOLAR1
REF_SEL1
BI_UNIPOLAR2
REF_SEL2
BI_UNIPOLAR3
REF_SEL3
BI_UNIPOLAR4
REF_SEL4
BI_UNIPOLAR5
REF_SEL5
BI_UNIPOLAR6
REF_SEL6
BI_UNIPOLAR7
REF_SEL7
Rev. B | Page 55 of 59
Bit 3
REFBUF1+
REFBUF2+
REFBUF3+
REFBUF4+
REFBUF5+
REFBUF6+
REFBUF7+
Bit 2
REFBUF1−
Reserved
REFBUF2−
Reserved
REFBUF3−
Reserved
REFBUF4−
Reserved
REFBUF5−
Reserved
REFBUF6−
Reserved
REFBUF7−
Reserved
Bit 1 Bit 0 Reset
INBUF1
0x1000
RW
RW
INBUF2
0x1000
RW
INBUF3
0x1000
RW
INBUF4
0x1000
RW
INBUF5
0x1000
RW
INBUF6
0x1000
RW
INBUF7
0x1000
RW
AD4111
Data Sheet
FILTER CONFIGURATION REGISTER 0
Address: 0x28, Reset: 0x0500, Name: FILTCON0
The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers
resets any active ADC conversion and restarts converting at the first channel in the sequence.
Table 36. Bit Descriptions for FILTCON0
Bits
15
Bit Name
SINC3_MAP0
[14:12]
11
Reserved
ENHFILTEN0
Settings
0
1
[10:8]
ENHFILT0
010
011
101
110
7
[6:5]
Reserved
ORDER0
00
11
[4:0]
ODR0
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
Description
If this bit is set, the mapping of the filter register changes to directly
program the decimation rate of the sinc3 filter for Setup 0. All other
options are eliminated. This bit allows fine tuning of the output data
rate and filter notch for rejection of specific frequencies. The data
rate when on a single channel equals fMOD/(32 × FILTCON0[14:0]).
These bits are reserved; set these bits to 0.
This bit enables various postfilters for enhanced 50 Hz/60 Hz
rejection for Setup 0. The ORDER0 bits must be set to 00 to select the
sinc5 + sinc1 filter for this function to work.
Disabled.
Enabled.
These bits select between various postfilters for enhanced 50 Hz/
60 Hz rejection for Setup 0.
27 SPS, 47 dB rejection, 36.7 ms settling
25 SPS, 62 dB rejection, 40 ms settling
20 SPS, 86 dB rejection, 50 ms settling
16.67 SPS, 92 dB rejection, 60 ms settling
This bit is reserved. Set this bit to 0.
These bits control the order of the digital filter that processes the
modulator data for Setup 0.
Sinc5 + sinc1 (default).
Sinc3.
These bits control the output data rate of the ADC and, therefore, the
settling time and noise for Setup 0. Rates shown are for single channel
enabled sinc5 + sinc 1 filter. See Table 6 to Table 9 for multiple
channels enabled.
31,250 SPS.
31,250 SPS.
31,250 SPS.
31,250 SPS.
31,250 SPS.
31,250 SPS.
15,625 SPS.
10,417 SPS.
5208.30 SPS.
2597.4 SPS (2604.2 SPS for sinc3).
1007 SPS (1008.1 SPS for sinc3).
503.8 SPS.
381 SPS (401 SPS for sinc3).
200.3 SPS.
100.2 SPS.
59.52 SPS (59.98 SPS for sinc3).
49.68 SPS (50 SPS for sinc3).
20.01 SPS.
16.63 SPS (16.67 SPS for sinc3).
10 SPS.
5 SPS.
2.5 SPS.
1.25 SPS.
Rev. B | Page 56 of 59
Reset
0x0
Access
RW
0x0
0x0
R
RW
0x5
RW
0x0
0x0
R
RW
0x0
RW
Data Sheet
AD4111
FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7
Address: 0x29 to Address 0x2F, Reset: 0x0500, Name: FILTCON1 to FILTCON7
The remaining seven filter configuration registers share the same layout as Filter Configuration Register 0.
Table 37. FILTCON1 to FILTCON7 Register Map
Reg.
0x29
Name
FILTCON1
0x2A
FILTCON2
0x2B
FILTCON3
0x2C
FILTCON4
0x2D
FILTCON5
0x2E
FILTCON6
0x2F
FILTCON7
Bits
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
[15:8]
[7:0]
Bit 7
SINC3_MAP1
Reserved
SINC3_MAP2
Reserved
SINC3_MAP3
Reserved
SINC3_MAP4
Reserved
SINC3_MAP5
Reserved
SINC3_MAP6
Reserved
SINC3_MAP7
Reserved
Bit 6
Bit 5
Bit 4
Reserved
ORDER1
Reserved
ORDER2
Reserved
ORDER3
Reserved
ORDER4
Reserved
ORDER5
Reserved
ORDER6
Reserved
ORDER7
Bit 3
ENHFILTEN1
Bit 2
Bit 1
Bit 0
ENHFILT1
Reset
0x0500
RW
RW
ENHFILT2
0x0500
RW
ENHFILT3
0x0500
RW
ENHFILT4
0x0500
RW
ENHFILT5
0x0500
RW
ENHFILT6
0x0500
RW
ENHFILT7
0x0500
RW
ODR1
ENHFILTEN2
ODR2
ENHFILTEN3
ODR3
ENHFILTEN4
ODR4
ENHFILTEN5
ODR5
ENHFILTEN6
ODR6
ENHFILTEN7
ODR7
OFFSET REGISTER 0
Address: 0x30, Reset: 0x800000, Name: OFFSET0
The offset (zero-scale) registers are 24-bit registers that can be used to compensate for any offset error in the ADC or in the system.
Table 38. Bit Descriptions for OFFSET0
Bits
[23:0]
Bit Name
OFFSET0
Settings
Description
Offset calibration coefficient for Setup 0.
Reset
0x800000
Access
RW
OFFSET REGISTER 1 TO OFFSET REGISTER 7
Address: 0x31 to Address 0x37, Reset: 0x800000, Name: OFFSET1 to OFFSET7
The remaining seven offset registers share the same layout as Offset Register 0.
Table 39. OFFSET1 to OFFSET7 Register Map
Reg.
0x31
0x32
0x33
0x34
0x35
0x36
0x37
Name
OFFSET1
OFFSET2
OFFSET3
OFFSET4
OFFSET5
OFFSET6
OFFSET7
Bits
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
Bits[23:0]
OFFSET1[23:0]
OFFSET2[23:0]
OFFSET3[23:0]
OFFSET4[23:0]
OFFSET5[23:0]
OFFSET6[23:0]
OFFSET7[23:0]
Reset
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
0x800000
Rev. B | Page 57 of 59
RW
RW
RW
RW
RW
RW
RW
RW
AD4111
Data Sheet
GAIN REGISTER 0
Address: 0x38, Reset: 0x5XXXX0, Name: GAIN0
The gain (full-scale) registers are 24-bit registers that can be used to compensate for any gain error in the ADC or in the system.
Table 40. Bit Descriptions for GAIN0
Bits
[23:0]
1
Bit Name
GAIN0
Settings
Description
Gain calibration coefficient for Setup 0.
Reset 1
0x5XXXX0
Access
RW
Reset 1
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
0x5XXXX0
RW
RW
RW
RW
RW
RW
RW
RW
X means don’t care.
GAIN REGISTER 1 TO GAIN REGISTER 7
Address: 0x39 to 0x3F, Reset: 0x5XXXX0, Name: GAIN1 to GAIN7
The remaining seven gain registers share the same layout as Gain Register 0.
Table 41. GAIN1 to GAIN7 Register Map
Reg.
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
1
Name
GAIN1
GAIN2
GAIN3
GAIN4
GAIN5
GAIN6
GAIN7
Bits
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
[23:0]
Bits[23:0]
GAIN1[23:0]
GAIN2[23:0]
GAIN3[23:0]
GAIN4[23:0]
GAIN5[23:0]
GAIN6[23:0]
GAIN7[23:0]
X means don’t care.
Rev. B | Page 58 of 59
Data Sheet
AD4111
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
AREA
0.30
0.25
0.18
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
31
40
1
30
0.50
BSC
4.70
4.60 SQ
4.50
EXPOSED
PAD
TOP VIEW
1.00
0.95
0.85
SIDE VIEW
PKG-003653/5050
SEATING
PLANE
0.45
0.40
0.35
21
11
20
10
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-5
02-05-2019-C
6.10
6.00 SQ
5.90
Figure 59. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm Body and 0.95 mm Package Height
(CP-40-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD4111BCPZ
AD4111BCPZ-RL7
EVAL-AD4111SDZ
EVAL-SDP-CB1Z
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
40-Lead Lead Frame Chip Scale Package [LFCSP]
40-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Evaluation Controller Board
Z = RoHS Compliant Part.
©2018–2021 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16640-3/21(B)
Rev. B | Page 59 of 59
Package Option
CP-40-15
CP-40-15
工商网监
湘ICP备2023018690号
