AD5124BRUZ100-RL7

Quad Channel, 128-/256-Position, I2C/SPI, Nonvolatile Digital Potentiometer AD5124/AD5144/AD5144A Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VDD VLOGIC 10 kΩ and 100 kΩ resistance options Resistor tolerance: 8% maximum Wiper current: ±6 mA Low temperature coefficient: 35 ppm/°C Wide bandwidth: 3 MHz Fast start-up time < 75 µs Linear gain setting mode Single- and dual-supply operation Independent logic supply: 1.8 V to 5.5 V Wide operating temperature: −40°C to +125°C 4 mm × 4 mm package option LRDAC AD5124/AD5144 POWER-ON RESET RDAC1 A1 INPUT REGISTER 1 W1 B1 RESET RDAC2 DIS A2 INPUT REGISTER 2 W2 SCLK/SCL SDI/SDA B2 SERIAL INTERFACE RDAC3 7/8 A3 INPUT REGISTER 3 W3 SYNC/ADDR0 APPLICATIONS B3 RDAC4 SDO/ADDR1 A4 INPUT REGISTER 4 Portable electronics level adjustment LCD panel brightness and contrast controls Programmable filters, delays, and time constants Programmable power supplies W4 B4 GND VSS WP 10877-001 EEPROM MEMORY Figure 1. AD5124/AD5144 24-Lead LFCSP GENERAL DESCRIPTION The AD5124/AD5144/AD5144A potentiometers provide a nonvolatile solution for 128-/256-position adjustment applications, offering guaranteed low resistor tolerance errors of ±8% and up to ±6 mA current density in the Ax, Bx, and Wx pins. The low resistor tolerance and low nominal temperature coefficient simplify open-loop applications as well as applications requiring tolerance matching. The linear gain setting mode allows independent programming of the resistance between the digital potentiometer terminals, through the RAW and RWB string resistors, allowing very accurate resistor matching. The high bandwidth and low total harmonic distortion (THD) ensure optimal performance for ac signals, making these devices suitable for filter design. The low wiper resistance of only 40 Ω at the ends of the resistor array allow for pin-to-pin connection. The wiper values can be set through an SPI-/I2C-compatible digital interface that is also used to read back the wiper register and EEPROM contents. Rev. C The AD5124/AD5144/AD5144A are available in a compact, 24-lead, 4 mm × 4 mm LFCSP and a 20-lead TSSOP. The parts are guaranteed to operate over the extended industrial temperature range of −40°C to +125°C. Table 1. Family Models Model AD5123 1 AD5124 AD5124 AD51431 AD5144 AD5144 AD5144A AD5122 AD5122A AD5142 AD5142A AD5121 AD5141 1 Channel Quad Quad Quad Quad Quad Quad Quad Dual Dual Dual Dual Single Single Position 128 128 128 256 256 256 256 128 128 256 256 128 256 Interface I2 C SPI/I2C SPI I2 C SPI/I2C SPI I2 C SPI I2 C SPI I2 C SPI/I2C SPI/I2C Package LFCSP LFCSP TSSOP LFCSP LFCSP TSSOP TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP/TSSOP LFCSP LFCSP Two potentiometers and two rheostats. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5124/AD5144/AD5144A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 RDAC Register and EEPROM .................................................. 23 Applications ....................................................................................... 1 Input Shift Register .................................................................... 23 Functional Block Diagram .............................................................. 1 Serial Data Digital Interface Selection, DIS ............................ 23 General Description ......................................................................... 1 SPI Serial Data Interface ............................................................ 23 Revision History ............................................................................... 2 I2C Serial Data Interface ............................................................ 25 Functional Block Diagrams—TSSOP ............................................ 3 I2C Address.................................................................................. 25 Specifications..................................................................................... 4 Advanced Control Modes ......................................................... 27 Electrical Characteristics—AD5124 .......................................... 4 EEPROM or RDAC Register Protection ................................. 28 Electrical Characteristics—AD5144 and AD5144A ................ 7 Load RDAC Input Register (LRDAC) ..................................... 28 Interface Timing Specifications ................................................ 10 RDAC Architecture .................................................................... 31 Shift Register and Timing Diagrams ....................................... 11 Programming the Variable Resistor ......................................... 31 Absolute Maximum Ratings .......................................................... 13 Programming the Potentiometer Divider ............................... 32 Thermal Resistance .................................................................... 13 Terminal Voltage Operating Range ......................................... 32 ESD Caution ................................................................................ 13 Power-Up Sequence ................................................................... 32 Pin Configurations and Function Descriptions ......................... 14 Layout and Power Supply Biasing ............................................ 32 Typical Performance Characteristics ........................................... 17 Outline Dimensions ....................................................................... 33 Test Circuits ..................................................................................... 22 Ordering Guide .......................................................................... 34 Theory of Operation ...................................................................... 23 REVISION HISTORY 7/2019—Rev. B to Rev. C Added Endnote 2, Table 14 ........................................................... 26 Added Endnote 2, Table 20 ........................................................... 29 Updated Outline Dimensions ....................................................... 33 7/2017—Rev. A to Rev. B Changed LFCSP_WQ to LFCSP .................................. Throughout Changes to Features Section............................................................ 1 Changes to Logic Supply Current Parameter, Table 2 ................. 5 Added Note 12 to Data Retention Parameter, Table 2; Renumbered Sequentially................................................................ 6 Changes to Logic Supply Current Parameter, Table 3 ................. 8 Added Note 12 to Data Retention Parameter, Table 3; Renumbered Sequentially................................................................ 9 Changes to Table 7.......................................................................... 13 Changes to Figure 11 and Table 11 .............................................. 16 Changes to Figure 20...................................................................... 18 Added Figure 21; Renumbered Sequentially .............................. 18 Changes to Figure 24...................................................................... 19 Change to Linear Gain Setting Mode Section ............................ 27 Change to RDAC Architecture Section ....................................... 31 Updated Outline Dimensions ....................................................... 33 12/2012—Rev. 0 to Rev. A Changes to Table 12 and Table 13 ................................................ 25 10/2012—Revision 0: Initial Version Rev. C | Page 2 of 36 Data Sheet AD5124/AD5144/AD5144A FUNCTIONAL BLOCK DIAGRAMS—TSSOP VDD VLOGIC VDD AD5144A AD5124/AD5144 POWER-ON RESET RDAC 1 A1 INPUT REGISTER 1 W1 POWER-ON RESET RDAC 1 A1 INPUT REGISTER 1 W1 B1 B1 SYNC RDAC 2 SCLK INPUT REGISTER 2 SPI SERIAL INTERFACE SDO W2 B2 RDAC 3 7/8 INPUT REGISTER 3 INPUT REGISTER 2 SCL SDA A3 I2C SERIAL INTERFACE W3 ADDR 8 INPUT REGISTER 3 B3 A4 INPUT REGISTER 4 W4 VSS W4 B4 B4 EEPROM MEMORY EEPROM MEMORY GND A3 W3 RDAC 4 A4 INPUT REGISTER 4 A2 W2 B2 RDAC 3 B3 RDAC 4 10877-002 SDI RDAC 2 RESET A2 GND Figure 2. AD5124/AD5144 20-Lead TSSOP VSS Figure 3. AD5144A 20-Lead TSSOP Rev. C | Page 3 of 36 10877-003 VLOGIC AD5124/AD5144/AD5144A Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5124 VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution Resistor Integral Nonlinearity 2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance3 Bottom Scale or Top Scale Nominal Resistance Match DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity 4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 Symbol Test Conditions/Comments N R-INL Min Typ 1 Max 7 RAB = 10 kΩ VDD ≥ 2.7 V VDD < 2.7 V RAB = 100 kΩ VDD ≥ 2.7 V VDD < 2.7 V R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW Unit Bits −1 −2.5 ±0.1 ±1 +1 +2.5 LSB LSB −0.5 −1 −0.5 −8 +0.5 +1 +0.5 +8 Code = full scale Code = zero scale RAB = 10 kΩ RAB = 100 kΩ ±0.1 ±0.25 ±0.1 ±1 35 LSB LSB LSB % ppm/°C 55 130 125 400 Ω Ω RAB = 10 kΩ RAB = 100 kΩ Code = 0xFF −1 40 60 ±0.2 80 230 +1 Ω Ω % RAB = 10 kΩ RAB = 100 kΩ −0.5 −0.25 −0.25 ±0.1 ±0.1 ±0.1 +0.5 +0.25 +0.25 LSB LSB LSB RAB = 10 kΩ RAB = 100 kΩ −1.5 −0.5 −0.1 ±0.1 +0.5 LSB LSB RBS or RTS RAB1/RAB2 INL DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 RAB = 10 kΩ RAB = 100 kΩ Code = half scale Rev. C | Page 4 of 36 1 0.25 ±5 1.5 0.5 LSB LSB ppm/°C Data Sheet Parameter RESISTOR TERMINALS Maximum Continuous Current Terminal Voltage Range 5 Capacitance A, Capacitance B3 Capacitance W3 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUTS Output High Voltage3 Output Low Voltage3 AD5124/AD5144/AD5144A Symbol Negative Supply Current EEPROM Store Current3, 6 EEPROM Read Current3, 7 Logic Supply Current Power Dissipation 8 Power Supply Rejection Ratio Min RAB = 10 kΩ RAB = 100 kΩ −6 −1.5 VSS Typ 1 Max Unit +6 +1.5 VDD mA mA V IA, IB, and IW CA, CB CW VINH f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ VA = VW = VB −500 VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 × VLOGIC 0.7 × VLOGIC VINL VHYST IIN CIN VOH VOL Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Logic Supply Range Positive Supply Current Test Conditions/Comments 25 12 pF pF 12 5 ±15 pF pF nA +500 0.2 × VLOGIC 0.1 × VLOGIC ±1 5 RPULL-UP = 2.2 kΩ to VLOGIC ISINK = 3 mA ISINK = 6 mA, VLOGIC > 2.3 V VLOGIC −1 0.4 0.6 +1 V V V µA pF 5.5 ±2.75 VDD VDD V V V V 5.5 µA nA µA mA µA µA µW dB 2 VSS = GND IDD ISS IDD_EEPROM_STORE IDD_EEPROM_READ ILOGIC PDISS PSRR Single supply, VSS = GND Dual supply, VSS < GND VIH = VLOGIC or VIL = GND VDD = 5.5 V VDD = 2.3 V VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND ∆VDD/∆VSS = VDD ± 10%, code = full scale Rev. C | Page 5 of 36 2.3 ±2.25 1.8 2.25 −5.5 0.7 400 −0.7 2 320 0.05 3.5 −66 V V V V µA pF 1.4 −60 AD5124/AD5144/AD5144A Parameter DYNAMIC CHARACTERISTICS 9 Bandwidth Total Harmonic Distortion Resistor Noise Density VW Settling Time Data Sheet Symbol Test Conditions/Comments BW −3 dB RAB = 10 kΩ RAB = 100 kΩ VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ RAB = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ RAB = 100 kΩ VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band RAB = 10 kΩ RAB = 100 kΩ RAB = 10 kΩ RAB = 100 kΩ THD eN_WB tS Crosstalk (CW1/CW2) CT Analog Crosstalk Endurance 10 CTA Min TA = 25°C Typ 1 Unit 3 0.43 MHz MHz −80 −90 dB dB 7 20 nV/√Hz nV/√Hz 2 12 10 25 −90 1 µs µs nV-sec nV-sec dB Mcycles kcycles Years 100 Data Retention 11, 12 Max 50 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. Resistor integral nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 12 50 years apply to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years. 1 2 Rev. C | Page 6 of 36 Data Sheet AD5124/AD5144/AD5144A ELECTRICAL CHARACTERISTICS—AD5144 AND AD5144A VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; VLOGIC = 1.8 V to 5.5 V, −40°C < TA < +125°C, unless otherwise noted. Table 3. Parameter DC CHARACTERISTICS—RHEOSTAT MODE (ALL RDACs) Resolution Resistor Integral Nonlinearity 2 Resistor Differential Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient3 Wiper Resistance3 Bottom Scale or Top Scale Nominal Resistance Match DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (ALL RDACs) Integral Nonlinearity 4 Differential Nonlinearity4 Full-Scale Error Zero-Scale Error Voltage Divider Temperature Coefficient3 Symbol Test Conditions/Comments N R-INL Min Typ 1 Max 8 RAB = 10 kΩ VDD ≥ 2.7 V VDD < 2.7 V RAB = 100 kΩ VDD ≥ 2.7 V VDD < 2.7 V R-DNL ΔRAB/RAB (ΔRAB/RAB)/ΔT × 106 RW Unit Bits −2 −5 ±0.2 ±1.5 +2 +5 LSB LSB −1 −2 −0.5 −8 ±0.1 ±0.5 ±0.2 ±1 35 +1 +2 +0.5 +8 LSB LSB LSB % ppm/°C 55 130 125 400 Ω Ω −1 40 60 ±0.2 80 230 +1 Ω Ω % RAB = 10 kΩ RAB = 100 kΩ −1 −0.5 −0.5 ±0.2 ±0.1 ±0.2 +1 +0.5 +0.5 LSB LSB LSB RAB = 10 kΩ RAB = 100 kΩ −2.5 −1 −0.1 ±0.2 +1 LSB LSB Code = full scale Code = zero scale RAB = 10 kΩ RAB = 100 kΩ RBS or RTS RAB = 10 kΩ RAB = 100 kΩ Code = 0xFF RAB1/RAB2 INL DNL VWFSE VWZSE (ΔVW/VW)/ΔT × 106 RAB = 10 kΩ RAB = 100 kΩ Code = half scale Rev. C | Page 7 of 36 1.2 0.5 ±5 3 1 LSB LSB ppm/°C AD5124/AD5144/AD5144A Parameter RESISTOR TERMINALS Maximum Continuous Current Terminal Voltage Range 5 Capacitance A, Capacitance B3 Capacitance W3 Common-Mode Leakage Current3 DIGITAL INPUTS Input Logic3 High Low Input Hysteresis3 Input Current3 Input Capacitance3 DIGITAL OUTPUTS Output High Voltage3 Output Low Voltage3 Data Sheet Symbol Negative Supply Current EEPROM Store Current3, 6 EEPROM Read Current3, 7 Logic Supply Current Power Dissipation 8 Power Supply Rejection Ratio Min RAB = 10 kΩ RAB = 100 kΩ −6 −1.5 VSS Typ 1 Max Unit +6 +1.5 VDD mA mA V IA, IB, and IW CA, CB CW VINH f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ f = 1 MHz, measured to GND, code = half scale RAB = 10 kΩ RAB = 100 kΩ VA = V W = V B −500 VLOGIC = 1.8 V to 2.3 V VLOGIC = 2.3 V to 5.5 V 0.8 × VLOGIC 0.7 × VLOGIC VINL VHYST IIN CIN VOH VOL Three-State Leakage Current Three-State Output Capacitance POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Logic Supply Range Positive Supply Current Test Conditions/Comments 25 12 pF pF 12 5 ±15 pF pF nA +500 0.2 × VLOGIC 0.1 × VLOGIC ±1 5 RPULL-UP = 2.2 kΩ to VLOGIC ISINK = 3 mA ISINK = 6 mA, VLOGIC > 2.3 V VLOGIC −1 0.4 0.6 +1 V V V µA pF 5.5 ±2.75 VDD VDD V V V V 5.5 µA nA µA mA µA µA µW dB 2 VSS = GND IDD ISS IDD_EEPROM_STORE IDD_EEPROM_READ ILOGIC PDISS PSRR Single supply, VSS = GND Dual supply, VSS < GND VIH = VLOGIC or VIL = GND VDD = 5.5 V VDD = 2.3 V VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND VIH = VLOGIC or VIL = GND ∆VDD/∆VSS = VDD ± 10%, code = full scale Rev. C | Page 8 of 36 2.3 ±2.25 1.8 2.25 −5.5 0.7 400 −0.7 2 320 0.05 3.5 −66 V V V V µA pF 1.4 −60 Data Sheet Parameter DYNAMIC CHARACTERISTICS 9 Bandwidth Total Harmonic Distortion Resistor Noise Density VW Settling Time AD5124/AD5144/AD5144A Symbol Test Conditions/Comments BW −3 dB RAB = 10 kΩ RAB = 100 kΩ VDD/VSS = ±2.5 V, VA = 1 V rms, VB = 0 V, f = 1 kHz RAB = 10 kΩ RAB = 100 kΩ Code = half scale, TA = 25°C, f = 10 kHz RAB = 10 kΩ RAB = 100 kΩ VA = 5 V, VB = 0 V, from zero scale to full scale, ±0.5 LSB error band RAB = 10 kΩ RAB = 100 kΩ RAB = 10 kΩ RAB = 100 kΩ THD eN_WB tS Crosstalk (CW1/CW2) CT Analog Crosstalk Endurance 10 CTA Min TA = 25°C Typ 1 Unit 3 0.43 MHz MHz −80 −90 dB dB 7 20 nV/√Hz nV/√Hz 2 12 10 25 −90 1 µs µs nV-sec nV-sec dB Mcycles kcycles Years 100 Data Retention 11, 12 Max 50 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. Resistor integral nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground referenced bipolar signal adjustment. 6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms. 7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs. 8 PDISS is calculated from (IDD × VDD) + (ILOGIC × VLOGIC). 9 All dynamic characteristics use VDD/VSS = ±2.5 V, and VLOGIC = 2.5 V. 10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV, derates with junction temperature in the Flash/EE memory. 12 50 years apply to an endurance of 1000 cycles. An endurance of 100,000 cycles has an equivalent retention lifetime of 5 years. 1 2 Rev. C | Page 9 of 36 AD5124/AD5144/AD5144A Data Sheet INTERFACE TIMING SPECIFICATIONS VLOGIC = 1.8 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. Table 4. SPI Interface Parameter 1 t1 t2 t3 Test Conditions/Comments VLOGIC > 1.8 V VLOGIC = 1.8 V VLOGIC > 1.8 V VLOGIC = 1.8 V VLOGIC > 1.8 V VLOGIC = 1.8 V Min 20 30 10 15 10 15 10 5 5 10 20 t4 t5 t6 t7 t8 2 t9 3 t10 Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns ns 50 500 Description SCLK cycle time SCLK high time SCLK low time SYNC-to-SCLK falling edge setup time Data setup time Data hold time SYNC rising edge to next SCLK fall ignored Minimum SYNC high time SCLK rising edge to SDO valid SYNC rising edge to SDO pin disable All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Refer to tEEPROM_PROGRAM and tEEPROM_READBACK for memory commands operations (see Table 6). 3 RPULL_UP = 2.2 kΩ to VDD with a capacitance load of 168 pF. 1 2 Table 5. I2C Interface Parameter 1 fSCL 2 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t11A Test Conditions/Comments Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Fast mode Standard mode Min Fast mode 20 + 0.1 CL 4.0 0.6 4.7 1.3 250 100 0 0 4.7 0.6 4 0.6 4.7 1.3 4 0.6 20 + 0.1 CL 20 + 0.1 CL 20 + 0.1 CL Typ Max 100 400 1000 300 300 300 1000 300 1000 Unit kHz kHz µs µs µs µs ns ns µs µs µs µs µs µs µs µs µs µs ns ns ns ns ns ns ns 300 ns 3.45 0.9 Rev. C | Page 10 of 36 Description Serial clock frequency SCL high time, tHIGH SCL low time, tLOW Data setup time, tSU; DAT Data hold time, tHD; DAT Setup time for a repeated start condition, tSU; STA Hold time (repeated) for a start condition, tHD; STA Bus free time between a stop and a start condition, tBUF Setup time for a stop condition, tSU; STO Rise time of SDA signal, tRDA Fall time of SDA signal, tFDA Rise time of SCL signal, tRCL Rise time of SCL signal after a repeated start condition and after an acknowledge bit, tRCL1 (not shown in Figure 5) Data Sheet Parameter 1 t12 tSP 3 AD5124/AD5144/AD5144A Test Conditions/Comments Standard mode Fast mode Fast mode Min Typ 20 + 0.1 CL 0 Max 300 300 50 Unit ns ns ns Description Fall time of SCL signal, tFCL Pulse width of suppressed spike Maximum bus capacitance is limited to 400 pF. The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the EMC behavior of the part. 3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode. 1 2 Table 6. Control Pins Parameter t1 t2 t3 tEEPROM_PROGRAM 1 tEEPROM_READBACK tPOWER_UP 2 tRESET 1 2 Min 1 50 0.1 Typ Max 15 7 10 50 30 75 Unit µs ns µs ms µs µs µs 30 Description End command to LRDAC falling edge Minimum LRDAC low time RESET low time Memory program time (not shown in Figure 8) Memory readback time (not shown in Figure 8) Start-up time (not shown in Figure 8) Reset EEPROM restore time (not shown in Figure 8) EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles. Maximum time after VDD − VSS is equal to 2.3 V. SHIFT REGISTER AND TIMING DIAGRAMS C3 C2 C1 C0 A3 A2 A1 DB8 DB7 A0 D7 DB0 (LSB) D6 D5 D4 D3 D2 D1 D0 10877-004 DB15 (MSB) DATA BITS ADDRESS BITS CONTROL BITS Figure 4. Input Shift Register Contents t12 t11 t6 t8 t2 SCL t5 t1 t6 t4 t10 t3 t9 t7 P S S Figure 5. I 2C Serial Interface Timing Diagram (Typical Write Sequence) Rev. C | Page 11 of 36 P 10877-005 SDA AD5124/AD5144/AD5144A t4 Data Sheet t1 t2 t7 SCLK t3 t8 SYNC t5 t6 SDI C3 C2 C1 C0 D7 D6 D5 SDO C3* C2* C1* C0* D7* D6* D5* D2 D1 D0 D2* D1* D0* t9 10877-006 t10 *PREVIOUS COMMAND RECEIVED. Figure 6. SPI Serial Interface Timing Diagram, CPOL = 0, CPHA = 1 t1 t2 t4 t7 SCLK t3 t8 SYNC t5 t6 C3 C2 C1 C0 D7 D6 D5 SDO C3* C2* C1* C0* D7* D6* D5* D2 D1 D0 D2* D1* D0* t9 t10 10877-007 SDI *PREVIOUS COMMAND RECEIVED. Figure 7. SPI Serial Interface Timing Diagram, CPOL = 1, CPHA = 0 SCLK SPI INTERFACE SYNC SCL I2C INTERFACE SDA P t1 t2 t3 RESET Figure 8. Control Pins Timing Diagram Rev. C | Page 12 of 36 10877-008 LRDAC Data Sheet AD5124/AD5144/AD5144A ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to GND VSS to GND VDD to VSS VLOGIC to GND Rating −0.3 V to +7.0 V +0.3 V to −7.0 V 7V −0.3 V to VDD + 0.3 V or +7.0 V (whichever is less) VSS − 0.3 V, VDD + 0.3 V VA, VW, VB to GND IA, IW, IB Pulsed 1 Frequency > 10 kHz RAW = 10 kΩ RAW = 100 kΩ Frequency ≤ 10 kHz RAW = 10 kΩ RAW = 100 kΩ Digital Inputs Operating Temperature Range, TA Maximum Junction Temperature, TJ Maximum Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation FICDM Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is defined by the JEDEC JESD51 standard, and the value is dependent on the test board and test environment. Table 8. Thermal Resistance Package Type 24-Lead LFCSP 20-Lead TSSOP ±6 mA/d ±1.5 mA/d2 2 3 ±6 mA/√d2 ±1.5 mA/√d2 −0.3 V to VLOGIC + 0.3 V or +7 V (whichever is less) −40°C to +125°C 150°C 1 θJA 351 1431 JEDEC 2S2P test board, still air (0 m/sec airflow). ESD CAUTION −65°C to +150°C 260°C 20 sec to 40 sec (TJ max − TA)/θJA 1.5 kV Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 d = pulse duty factor. 3 Includes programming of EEPROM memory. 1 Rev. C | Page 13 of 36 θJC 3 45 Unit °C/W °C/W AD5124/AD5144/AD5144A Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS SYNC 1 20 SDO GND 2 19 SDI A1 3 18 SCLK W1 4 17 VLOGIC B1 5 A3 6 AD5124/ AD5144 VDD TOP VIEW 15 B4 (Not to Scale) W3 7 14 W4 B3 8 13 A4 VSS 9 12 B2 A2 10 11 W2 10877-010 16 Figure 9. 20-Lead TSSOP, SPI Interface Pin Configuration (AD5124/AD5144) Table 9. 20-Lead TSSOP, SPI Interface Pin Function Descriptions (AD5124/AD5144) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Mnemonic SYNC GND A1 W1 B1 A3 W3 B3 VSS A2 W2 B2 A4 W4 B4 VDD VLOGIC SCLK SDI SDO Description Synchronization Data Input, Active Low. When SYNC returns high, data is loaded into the input shift register. Ground Pin, Logic Ground Reference. Terminal A of RDAC1. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD. Terminal B of RDAC1. VSS ≤ VB ≤ VDD. Terminal A of RDAC3. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD. Terminal B of RDAC3. VSS ≤ VB ≤ VDD. Negative Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. Terminal A of RDAC2. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD. Terminal B of RDAC2. VSS ≤ VB ≤ VDD. Terminal A of RDAC4. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD. Terminal B of RDAC4. VSS ≤ VB ≤ VDD. Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. Serial Clock Line. Data is clocked in at the logic low transition. Serial Data Input. Serial Data Output. This is an open-drain output pin, and it needs an external pull-up resistor. Rev. C | Page 14 of 36 Data Sheet AD5124/AD5144/AD5144A RESET 1 20 ADDR GND 2 19 SDA A1 3 18 SCL W1 4 17 VLOGIC B1 5 A3 6 AD5144A W3 7 14 W4 B3 8 13 A4 VSS 9 12 B2 A2 10 11 W2 10877-011 16 VDD TOP VIEW (Not to Scale) 15 B4 Figure 10. 20-Lead TSSOP, I2C Interface Pin Configuration (AD5144A) Table 10. 20-Lead TSSOP, I2C Interface Pin Function Descriptions (AD5144A) Pin No. 1 Mnemonic RESET 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 GND A1 W1 B1 A3 W3 B3 VSS A2 W2 B2 A4 W4 B4 VDD VLOGIC SCL SDA ADDR Description Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is not used, tie RESET to VLOGIC. Ground Pin, Logic Ground Reference. Terminal A of RDAC1. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD. Terminal B of RDAC1. VSS ≤ VB ≤ VDD. Terminal A of RDAC3. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD. Terminal B of RDAC3. VSS ≤ VB ≤ VDD. Negative Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. Terminal A of RDAC2. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD. Terminal B of RDAC2. VSS ≤ VB ≤ VDD. Terminal A of RDAC4. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD. Terminal B of RDAC4. VSS ≤ VB ≤ VDD. Positive Power Supply. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 μF ceramic capacitors and 10 μF capacitors. Serial Clock Line. Data is clocked in at the logic low transition. Serial Data Input/Output. Programmable Address for Multiple Package Decoding. Rev. C | Page 15 of 36 20 WP 19 SDA/SDI 22 ADDR0/SYNC 21 ADDR1/SDO 24 RESET Data Sheet 23 LRDAC AD5124/AD5144/AD5144A 18 DIS GND 1 A1 2 W1 3 AD5124/ AD5144 B1 4 TOP VIEW (Not to Scale) A3 5 17 SCL/SCLK 16 VLOGIC 15 VDD 14 B4 W3 6 NOTES 1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO THE POTENTIAL OF THE VSS PIN, OR, ALTERNATIVELY, LEAVE IT ELECTRICALLY UNCONNECTED. IT IS RECOMMENDED THAT THE PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR ENHANCED THERMAL PERFORMANCE. 10877-009 B2 11 A4 12 A2 9 W2 10 B3 7 VSS 8 13 W4 Figure 11. 24-Lead LFCSP Pin Configuration (AD5124/AD5144) Table 11. 24-Lead LFCSP Pin Function Descriptions (AD5124/AD5144) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Mnemonic GND A1 W1 B1 A3 W3 B3 VSS A2 W2 B2 A4 W4 B4 VDD VLOGIC SCL/SCLK 18 DIS 19 SDA/SDI 20 WP 21 ADDR1/SDO 22 ADDR0/SYNC 23 LRDAC 24 RESET EPAD Description Ground Pin, Logic Ground Reference. Terminal A of RDAC1. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD. Terminal B of RDAC1. VSS ≤ VB ≤ VDD. Terminal A of RDAC3. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD. Terminal B of RDAC3. VSS ≤ VB ≤ VDD. Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Terminal A of RDAC2. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD. Terminal B of RDAC2. VSS ≤ VB ≤ VDD. Terminal A of RDAC4. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD. Terminal B of RDAC4. VSS ≤ VB ≤ VDD. Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors. I2C Serial Clock Line (SCL). Data is clocked in at the logic low transition. SPI Serial Clock Line (SCLK). Data is clocked in at the logic low transition. Digital Interface Select (SPI/I2C Select). SPI when DIS = 0 (GND), and I2C when DIS = 1 (VLOGIC). This pin cannot be left floating. Serial Data Input/Output (SDA), When DIS = 1. Serial Data Input (SDI), When DIS = 0. Optional Write Protect. This pin prevents any changes to the present RDAC and EEPROM content, except when reloading the content of the EEPROM into the RDAC register. WP is activated at logic low. If this pin is not used, tie WP to VLOGIC. Programmable Address (ADDR1) for Multiple Package Decoding, When DIS = 1. Serial Data Output (SDO). Open-drain output, needs an external pull-up resistor, when DIS = 0. Programmable Address (ADDR0) for Multiple Package Decoding, When DIS = 1. Synchronization Data Input, When DIS = 0. This pin is active low. When SYNC returns high, data is loaded into the input shift register. Load RDAC. Transfers the contents of the input registers to their respective RDAC registers when their associated input registers were previously loaded using Command 2 (see Table 20). This allows simultaneous update of all RDAC registers. LRDAC is activated at the high-to-low transition. If not used, tie LRDAC to VLOGIC. Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If not used, tie RESET to VLOGIC. Exposed Pad. Connect the exposed pad to the potential of the VSS pin, or, alternatively, leave it electrically unconnected. It is recommended that the pad be thermally connected to a copper plane for enhanced thermal performance. Rev. C | Page 16 of 36 Data Sheet AD5124/AD5144/AD5144A TYPICAL PERFORMANCE CHARACTERISTICS 0.5 0.4 0.3 0.1 0 R-DNL (LSB) 0.2 R-INL (LSB) 0.2 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C 0.1 0 –0.1 –0.1 –0.2 –0.3 –0.2 –0.4 –0.5 –0.4 0 100 200 CODE (Decimal) –0.6 10877-012 –0.5 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 0 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C 100 200 10877-015 –0.3 CODE (Decimal) Figure 12. R-INL vs. Code (AD5144/AD5144A) Figure 15. R-DNL vs. Code (AD5144/AD5144A) 0.20 0.10 0.15 0.05 0.10 0 R-DNL (LSB) 0 –0.05 –0.10 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C –0.20 –0.25 0 –0.10 –0.15 –0.20 –0.25 50 100 CODE (Decimal) –0.30 10877-013 –0.15 –0.05 10kΩ, +125°C 10kΩ, +25°C 10kΩ, –40°C 0 100 Figure 16. R-DNL vs. Code (AD5124) 0.10 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C 0.2 50 CODE (Decimal) Figure 13. R-INL vs. Code (AD5124) 0.3 100kΩ, +125°C 100kΩ, +25°C 100kΩ, –40°C 10877-016 R-INL (LSB) 0.05 0.05 0 DNL (LSB) 0 –0.1 –0.05 –0.10 –0.15 –0.20 –0.2 –0.3 0 100 200 CODE (Decimal) Figure 14. INL vs. Code (AD5144/AD5144A) –0.30 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 0 100 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C 200 CODE (Decimal) Figure 17. DNL vs. Code (AD5144/AD5144A) Rev. C | Page 17 of 36 10877-017 –0.25 10877-014 INL (LSB) 0.1 AD5124/AD5144/AD5144A Data Sheet 0.15 1000 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C 0.10 VLOGIC = 2.3V VLOGIC = 3.3V VLOGIC = 5.5V 800 700 0.05 600 ILOGIC (nA) INL (LSB) VDD = VLOGIC VSS = GND 900 0 500 400 –0.05 300 200 –0.10 100 0 –40 CODE (Decimal) –20 0 250 –0.02 200 150 50 –0.10 0 –0.12 –50 0 50 100 150 200 255 0 25 50 75 CODE (Decimal) 100 127 AD5144/ AD5144A AD5124 –0.14 0 50 450 RHEOSTAT MODE TEMPERATURE COEFFICIENT (ppm/°C) 400 300 200 VDD = 2.3V VDD = 3.3V VDD = 5.5V 20 40 60 80 100 TEMPERATURE (°C) Figure 20. Supply Current vs. Temperature 120 350 300 250 200 150 100 50 0 10877-020 0 10kΩ 100kΩ 400 500 IDD (nA) 100 Figure 22. DNL vs. Code (AD5124) VDD = VLOGIC VSS = GND 600 100kΩ, –40°C 100kΩ, +25°C 100kΩ, +125°C CODE (Decimal) Figure 19. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106) vs. Code –20 120 –0.06 –0.08 100 100 –0.04 100 0 –40 80 10877-021 DNL (LSB) 0.02 300 700 60 10kΩ, –40°C 10kΩ, +25°C 10kΩ, +125°C 0.04 10877-019 POTENTIOMETER MODE TEMPERATURE COEFFICIENT (ppm/°C) 0.06 350 800 40 Figure 21. ILOGIC vs. Temperature 100kΩ 10kΩ 400 20 TEMPERATURE (°C) Figure 18. INL vs. Code (AD5124) 450 0 –50 0 50 100 150 200 255 AD5144/ AD5144A 0 25 50 75 CODE (Decimal) 100 127 AD5124 Figure 23. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106) vs. Code Rev. C | Page 18 of 36 10877-122 50 0 10877-018 –0.15 10877-160 100 Data Sheet AD5124/AD5144/AD5144A 1.2 0.8 VDD/VSS = ±2.5V RAB = 10kΩ 0 –20 PHASE (Degrees) 1.0 0.6 0.4 –40 –60 –80 0.2 0 3 2 1 5 4 –100 10 10877-023 0 DIGITAL INPUT VOLATGE (V) 0 0x80 (0x40) 0x20 (0x10) 100k 1M 10M 0x80 (0x40) 0x8 (0x04) –30 0x10 (0x08) GAIN (dB) GAIN (dB) 10k –10 0x40 (0x20) 0x20 (0x10) –20 0x10 (0x08) –10 0x40 (0x20) 0x8 (0x04) 0x4 (0x02) 0x2 (0x01) –40 1k Figure 27. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ 0 –30 100 FREQUENCY (Hz) Figure 24. ILOGIC Current vs. Digital Input Voltage –20 QUARTER SCALE MIDSCALE FULL-SCALE 10877-026 ILOGIC CURRENT (µA) 20 I2C, VLOGIC = 1.8V I2C, VLOGIC = 2.3V I2C, VLOGIC = 3.3V I2C, VLOGIC = 5V I2C, VLOGIC = 5.5V SPI, VLOGIC = 1.8V SPI, VLOGIC = 2.3V SPI, VLOGIC = 3.3V SPI, VLOGIC = 5V SPI, VLOGIC = 5.5V 0x1 (0x00) –40 –50 0x4 (0x02) 0x2 (0x01) 0x1 (0x00) 0x00 –60 0x00 –70 –50 –80 AD5144/AD5144A (AD5124) AD5144/AD5144A (AD5124) 10k 1k 1M 100k 10M FREQUENCY (Hz) –90 10 100 –50 0 10M 10kΩ 100kΩ –10 –20 –60 –30 THD + N (dB) THD + N (dB) 1M Figure 28. 100 kΩ Gain vs. Frequency vs. Code 10kΩ 100kΩ VDD/VSS = ±2.5V VA = 1V rms VB = GND CODE = HALF SCALE NOISE FILTER = 22kHz 100k FREQUENCY (Hz) Figure 25. 10 kΩ Gain vs. Frequency vs. Code –40 10k 1k 10877-123 100 10877-022 –60 10 –70 –80 –40 –50 –60 –70 VDD/VSS = ±2.5V –80 200 2k FREQUENCY (Hz) 20k 200k Figure 26. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency CODE = HALF SCALE NOISE FILTER = 22kHz –90 0.001 10877-025 –100 20 fIN = 1kHz 0.01 0.1 VOLTAGE (V rms) 1 10877-028 –90 Figure 29. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude Rev. C | Page 19 of 36 AD5124/AD5144/AD5144A Data Sheet 10 0.8 0 –10 RELATIVE VOLTAGE (V) –30 –40 –50 –60 0.5 0.4 0.3 0.2 0.1 –70 100k 1M –0.1 0 0.0025 300 1.2 1.0 0.0020 PROBABILITY DENSITY WIPER ON RESISTANCE (Ω) 400 200 0.8 0.0015 0.6 0.0010 0.4 0.0005 100 1 2 3 4 5 0.2 0 10877-030 0 VOLTAGE (V) –600 –500 –400 –300 –200 –100 10 8 7 0 –10 PSRR (dB) 4 2 –70 1 –80 20 60 80 100 30 40 CODE (Decimal) 50 AD5144/ 120 AD5144A 60 AD5124 10877-031 40 10 500 0 600 10kΩ 100kΩ VDD = 5V ±10% AC VSS = GND, VA = 4V, VB = GND CODE = MIDSCALE –50 –60 20 400 –40 3 0 300 –30 5 0 200 –20 6 0 100 Figure 34. Resistor Lifetime Drift 10kΩ + 0pF 10kΩ + 75pF 10kΩ + 150pF 10kΩ + 250pF 100kΩ + 0pF 100kΩ + 75pF 100kΩ + 150pF 100kΩ + 250pF 9 0 RESISTOR DRIFT (ppm) Figure 31. Incremental Wiper On Resistance vs. Positive Power Supply (VDD) BANDWIDTH (MHz) 15 Figure 33. Maximum Transition Glitch 100kΩ, V DD = 2.3V 100kΩ, V DD = 2.7V 100kΩ, V DD = 3V 100kΩ, V DD = 3.6V 100kΩ, V DD = 5V 100kΩ, V DD = 5.5V 10kΩ, VDD = 2.3V 10kΩ, VDD = 2.7V 10kΩ, VDD = 3V 10kΩ, VDD = 3.6V 10kΩ, VDD = 5V 10kΩ, VDD = 5.5V 500 10 TIME (µs) Figure 30. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ 600 5 10877-032 10k CUMULATIVE PROBABILITY 1k FREQUENCY (Hz) 10877-033 100 0 VDD/VSS = ±2.5V RAB = 100kΩ –90 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 35. Power Supply Rejection Ratio (PSRR) vs. Frequency Figure 32. Maximum Bandwidth vs. Code vs. Net Capacitance Rev. C | Page 20 of 36 10877-034 –90 10 QUARTER SCALE MIDSCALE FULL-SCALE 10877-029 –80 0 VDD/VSS = ±2.5V VA = VDD VB = VSS 0.6 –20 PHASE (Degrees) 0x80 TO 0x7F, 100kΩ 0x80 TO 0x7F, 10kΩ 0.7 AD5124/AD5144/AD5144A 0.020 7 0.015 6 THEORETICAL IMAX (mA) 0.010 0.005 0 –0.005 –0.010 0 500 1500 2000 SHUTDOWN MODE ENABLED –20 –60 –80 –100 1k 10k 100k 1M FREQUENCY (Hz) 10M 10877-036 GAIN (dB) –40 100 0 0 50 100 0 25 50 75 CODE (Decimal) 150 200 100 Figure 37. Shutdown Isolation vs. Frequency Rev. C | Page 21 of 36 AD5144/ 250 AD5144A 125 AD5124 Figure 38. Theoretical Maximum Current vs. Code Figure 36. Digital Feedthrough –120 10 2 100kΩ 1000 10kΩ 100kΩ 3 1 TIME (ns) 0 4 10877-037 –0.020 5 10kΩ VDD/VSS = ±2.5V VA = VDD VB = VSS CODE = HALF SCALE –0.015 10877-035 RELATIVE VOLTAGE (V) Data Sheet AD5124/AD5144/AD5144A Data Sheet TEST CIRCUITS Figure 39 to Figure 43 define the test conditions used in the Specifications section. NC VA IW V+ = VDD ±10% VDD B V+ VMS Figure 39. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) PSRR (dB) = 20 LOG W ~ B 10877-038 NC = NO CONNECT A VMS PSS (%/%) = RSW = ΔVDD% 0.1V ISW CODE = 0x00 VMS A = NC Figure 40. Potentiometer Divider Nonlinearity Error (INL, DNL) IW = VDD/RNOMINAL DUT W VW B RW = VMS1/IW NC = NO CONNECT 10877-040 VMS1 – VSS TO VDD Figure 43. Incremental On Resistance NC A 0.1V ISW 10877-045 B B 10877-039 W V+ + V+ = VDD 1LSB = V+/2N Figure 41. Wiper Resistance Rev. C | Page 22 of 36 ΔVDD ) ΔVMS% W DUT ΔVMS Figure 42. Power Supply Sensitivity and Power Supply Rejection Ratio (PSS and PSRR) DUT A ( 10877-041 DUT A W Data Sheet AD5124/AD5144/AD5144A THEORY OF OPERATION The AD5124/AD5144/AD5144A digital programmable potentiometers are designed to operate as true variable resistors for analog signals within the terminal voltage range of VSS < VTERM < VDD. The resistor wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register that allows unlimited changes of resistance settings. A secondary register (the input register) can be used to preload the RDAC register data. The RDAC register can be programmed with any position setting using the I2C or SPI interface (depending on the model). When a desirable wiper position is found, this value can be stored in the EEPROM memory. Thereafter, the wiper position is always restored to that position for subsequent power-ups. The storing of the EEPROM data takes approximately 15 ms; during this time, the device is locked and does not acknowledge any new command, preventing any changes from taking place. RDAC REGISTER AND EEPROM The RDAC register directly controls the position of the digital potentiometer wiper. For example, when the RDAC register is loaded with 0x80 (AD5144/AD5144A, 256 taps), the wiper is connected to half scale of the variable resistor. The RDAC register is a standard logic register; there is no restriction on the number of changes allowed. It is possible to both write to and read from the RDAC register using the digital interface (see Table 14). The contents of the RDAC register can be stored to the EEPROM using Command 9 (see Table 14). Thereafter, the RDAC register always sets at that position for any future on-off-on power supply sequence. It is possible to read back data saved into the EEPROM with Command 3 (see Table 14). Alternatively, the EEPROM can be written to independently using Command 11 (see Table 20). INPUT SHIFT REGISTER SERIAL DATA DIGITAL INTERFACE SELECTION, DIS The AD5124/AD5144 LFSCP provides the flexibility of a selectable interface. When the digital interface select (DIS) pin is tied low, the SPI mode is engaged. When the DIS pin is tied high, the I2C mode is engaged. SPI SERIAL DATA INTERFACE The AD5124/AD5144 contain a 4-wire, SPI-compatible digital interface (SDI, SYNC, SDO, and SCLK). The write sequence begins by bringing the SYNC line low. The SYNC pin must be held low until the complete data-word is loaded from the SDI pin. Data is loaded in at the SCLK falling edge transition, as shown in Figure 6. When SYNC returns high, the serial dataword is decoded according to the instructions in Table 20. To minimize power consumption in the digital input buffers when the part is enabled, operate all serial interface pins close to the VLOGIC supply rails. SYNC Interruption In a standalone write sequence for the AD5124/AD5144, the SYNC line is kept low for 16 falling edges of SCLK, and the instruction is decoded when SYNC is pulled high. However, if the SYNC line is kept low for less than 16 falling edges of SCLK, the input shift register content is ignored, and the write sequence is considered invalid. SDO Pin The serial data output pin (SDO) serves two purposes: to read back the contents of the control, EEPROM, RDAC, and input registers using Command 3 (see Table 14 and Table 20), and to connect the AD5124/AD5144 in daisy-chain mode. The SDO pin contains an internal open-drain output that needs an external pull-up resistor. The SDO pin is enabled when SYNC is pulled low, and the data is clocked out of SDO on the rising edge of SCLK, as shown in Figure 6 and Figure 7. For the AD5124/AD5144/AD5144A, the input shift register is 16 bits wide, as shown in Figure 4. The 16-bit word consists of four control bits, followed by four address bits and by eight data bits. If the AD5124 RDAC or EEPROM registers are read from or written to, the lowest data bit (Bit 0) is ignored. Data is loaded MSB first (Bit 15). The four control bits determine the function of the software command, as listed in Table 14 and Table 20. Rev. C | Page 23 of 36 AD5124/AD5144/AD5144A Data Sheet Daisy-Chain Connection To prevent data from mislocking (for example, due to noise) the part includes an internal counter, if the SCLK falling edges count is not a multiple of 8, the part ignores the command. A valid clock count is 16, 24, 32, 40, and so on. The counter resets when SYNC returns high. Daisy chaining minimizes the number of port pins required from the controlling IC. As shown in Figure 44, the SDO pin of one package must be tied to the SDI pin of the next package. The clock period may need to be increased because of the propagation delay of the line between subsequent devices. When two AD5124/ AD5144 devices are daisy chained, 32 bits of data are required. The first 16 bits are assigned to U2, and the second 16 bits are assigned to U1, as shown in Figure 45. Keep the SYNC pin low until all 32 bits are clocked into their respective serial registers. The SYNC pin is then pulled high to complete the operation. VLOGIC VLOGIC AD5124/ AD5144 SDI MOSI AD5124/ AD5144 RP 2.2kΩ SDI SDO U1 RP 2.2kΩ U2 SDO SCLK SYNC SCLK DAISY-CHAIN SYNC 10877-046 MICROCONTROLLER MISO SCLK SS Figure 44. Daisy-Chain Configuration SCLK 1 2 16 17 18 32 SYNC DB15 DB0 INPUT WORD FOR U1 INPUT WORD FOR U2 SDO_U1 DB0 DB15 DB0 DB15 DB15 UNDEFINED DB0 INPUT WORD FOR U2 Figure 45. Daisy-Chain Diagram Rev. C | Page 24 of 36 10877-047 MOSI Data Sheet AD5124/AD5144/AD5144A I2C SERIAL DATA INTERFACE I2C ADDRESS The AD5144/AD5144A have 2-wire, I2C-compatible serial interfaces. These devices can be connected to an I2C bus as a slave device, under the control of a master device. See Figure 5 for a timing diagram of a typical write sequence. The AD5144/AD5144A each have two different device address options available (see Table 12 and Table 13). Table 12. 20-Lead TSSOP Device Address Selection The AD5144/AD5144A support standard (100 kHz) and fast (400 kHz) data transfer modes. Support is not provided for 10-bit addressing and general call addressing. The 2-wire serial bus protocol operates as follows: 1. 2. 3. ADDR VLOGIC No connect1 GND 1 The master initiates a data transfer by establishing a start condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address and an R/W bit. The slave device corresponding to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is called the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its shift register. If the R/W bit is set high, the master reads from the slave device. However, if the R/W bit is set low, the master writes to the slave device. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. When all data bits have been read from or written to, a stop condition is established. In write mode, the master pulls the SDA line high during the tenth clock pulse to establish a stop condition. In read mode, the master issues a no acknowledge for the ninth clock pulse (that is, the SDA line remains high). The master then brings the SDA line low before the tenth clock pulse, and then high again during the tenth clock pulse to establish a stop condition. 7-Bit I2C Device Address 0101000 0101010 0101011 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8 V). Table 13. 24-Lead LFCSP Device Address Selection ADDR0 Pin VLOGIC No connect1 GND VLOGIC No connect1 GND VLOGIC No connect1 GND 1 ADDR1 Pin VLOGIC VLOGIC VLOGIC No connect1 No connect1 No connect1 GND GND GND 7-Bit I2C Device Address 0100000 0100010 0100011 0101000 0101010 0101011 0101100 0101110 0101111 Not available in bipolar mode (VSS < 0 V) or in low voltage mode (VLOGIC = 1.8 V). Rev. C | Page 25 of 36 AD5124/AD5144/AD5144A Data Sheet Table 14. Reduced Commands Operation Truth Table Command Number 0 1 Control Bits[DB15:DB12] C3 C2 C1 C0 0 0 0 0 0 0 0 1 Address Bits[DB11:DB8] 1 A3 A2 A1 A0 X X X X 0 0 A1 A0 D7 X D7 D6 X D6 Data Bits[DB7:DB0]1 D5 D4 D3 D2 D1 X X X X X D5 D4 D3 D2 D1 D0 X D0 2 2 0 0 1 0 0 0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D02 3 0 0 1 1 X 0 A1 A0 X X X X X X D1 D0 9 10 14 15 0 0 1 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 X A3 0 0 X 0 A1 A1 X A1 A0 A0 X A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 X D0 1 2 Operation NOP: do nothing. Write contents of serial register data to RDAC Write contents of serial register data to input register Read back contents D1 D0 Data 0 1 EEPROM 1 1 RDAC Copy RDAC register to EEPROM Copy EEPROM into RDAC Software reset Software shutdown D0 Condition 0 Normal mode 1 Shutdown mode X = don’t care. D0 = don’t care for AD5124. Table 15. Reduced Address Bits Table A3 1 0 0 0 0 1 A2 0 0 0 0 0 A1 X1 0 0 1 1 A0 X1 0 1 0 1 Channel All channels RDAC1 RDAC2 RDAC3 RDAC4 X = don’t care. Rev. C | Page 26 of 36 Stored Channel Memory Not applicable RDAC1 RDAC2 RDAC3 RDAC4 Data Sheet AD5124/AD5144/AD5144A ADVANCED CONTROL MODES Low Wiper Resistance Feature The AD5124/AD5144/AD5144A digital potentiometers include a set of user programming features to address the wide number of applications for these universal adjustment devices (see Table 20 and Table 22). The AD5124/AD5144/AD5144A include two commands to reduce the wiper resistance between the terminals when the devices achieve full scale or zero scale. These extra positions are called bottom scale, BS, and top scale, TS. The resistance between Terminal A and Terminal W at top scale is specified as RTS. Similarly, the bottom scale resistance between Terminal B and Terminal W is specified as RBS. Key programming features include the following: • • • • • • • • Input register Linear gain setting mode Low wiper resistance feature Linear increment and decrement instructions ±6 dB increment and decrement instructions Burst mode (I2C only) Reset Shutdown mode The contents of the RDAC registers are unchanged by entering into these positions. There are three ways to exit from top scale and bottom scale: by using Command 12 or Command 13 (see Table 20); by loading new data in an RDAC register, which includes increment/decrement operations; or by entering shutdown mode, Command 15 (see Table 20). Input Register Table 16 and Table 17 show the truth tables for the top scale position and the bottom scale position, respectively, when the potentiometer or linear gain setting mode is enabled. The AD5124/AD5144/AD5144A include one input register per RDAC register. These registers allow preloading of the value for the associated RDAC register. These registers can be written to using Command 2 and read back from using Command 3 (see Table 20). Linear Gain Setting Mode RAW RWB RAB RAB This feature allows a synchronous and asynchronous update of one or all of the RDAC registers at the same time. Table 17. Bottom Scale Truth Table The transfer from the input register to the RDAC register is done asynchronously by the LRDAC pin or synchronously by Command 8 (see Table 20). If new data is loaded into an RDAC register, this RDAC register automatically overwrites the associated input register. Linear Gain Setting Mode The proprietary architecture of the AD5124/AD5144/AD5144A allows the independent control of each string resistor, RAW, and RWB. To enable this feature, use Command 16 (see Table 20) to set Bit D2 of the control register (see Table 22). This mode of operation can control the potentiometer as two independent rheostats connected at a single point, the W terminal. This feature enables a second input and an RDAC register per channel, as shown in Table 21, but the actual RDAC contents remain unchanged. The same operations are valid for potentiometer and linear gain setting modes. The EEPROM commands affect the RWB resistance only. The parts restores in potentiometer mode after a reset or power-up. Table 16. Top Scale Truth Table Linear Gain Setting Mode RAW RWB RTS RBS RAW RTS RAW RAB Potentiometer Mode RWB RAB Potentiometer Mode RWB RBS Linear Increment and Decrement Instructions The increment and decrement commands (Command 4 and Command 5 in Table 20) are useful for linear step adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send an increment or decrement command to the device. The adjustment can be individual or in a ganged potentiometer arrangement, where all wiper positions are changed at the same time. For an increment command, executing Command 4 automatically moves the wiper to the next RDAC position. This command can be executed in a single channel or multiple channels. Rev. C | Page 27 of 36 AD5124/AD5144/AD5144A Data Sheet ±6 dB Increment and Decrement Instructions Shutdown Mode Two programming instructions produce logarithmic taper increment or decrement of the wiper position control by an individual potentiometer or by a ganged potentiometer arrangement where all RDAC register positions are changed simultaneously. The +6 dB increment is activated by Command 6, and the −6 dB decrement is activated by Command 7 (see Table 20). For example, starting with the zero-scale position and executing Command 6 ten times moves the wiper in 6 dB steps to the fullscale position. When the wiper position is near the maximum setting, the last 6 dB increment instruction causes the wiper to go to the full-scale position (see Table 18). The AD5124/AD5144/AD5144A can be placed in shutdown mode by executing the software shutdown command, Command 15 (see Table 20), and setting the LSB (D0) to 1. This feature places the RDAC in a zero power consumption state where the device operates in potentiometer mode, Terminal A is open circuited, and the wiper, Terminal W, is connected to Terminal B; however, a finite wiper resistance of 40 Ω is present. When the device is configured in linear gain setting mode, the resistor addressed, RAW or RWB, is internally place at high impedance. Table 19 shows a truth table depending on the device operating mode. The contents of the RDAC register are unchanged by entering shutdown mode. However, all commands listed in Table 20 are supported while in shutdown mode. Execute Command 15 (see Table 20) and set the LSB (D0) to 0 to exit shutdown mode. Incrementing the wiper position by +6 dB essentially doubles the RDAC register value, whereas decrementing the wiper position by −6 dB halves the register value. Internally, the AD5124/ AD5144/AD5144A use shift registers to shift the bits left and right to achieve a ±6 dB increment or decrement. These functions are useful for various audio/video level adjustments, especially for white LED brightness settings in which human visual responses are more sensitive to large adjustments than to small adjustments. Table 18. Detailed Left Shift and Right Shift Functions for the ±6 dB Step Increment and Decrement Left Shift (+6 dB/Step) 0000 0000 0000 0001 0000 0010 0000 0100 0000 1000 0001 0000 0010 0000 0100 0000 1000 0000 1111 1111 Right Shift (−6 dB/Step) 1111 1111 0111 1111 0011 1111 0001 1111 0000 1111 0000 0111 0000 0011 0000 0001 0000 0000 0000 0000 Table 19. Shutdown Mode Truth Table Linear Gain Setting Mode RAW RWB High impedance High impedance Potentiometer Mode RAW RWB High impedance RBS EEPROM OR RDAC REGISTER PROTECTION The EEPROM and RDAC registers can be protected by disabling any update to these registers. This can be done by using software or by using hardware. If these registers are protected by software, set Bit D0 and/or Bit D1 (see Table 22), which protects the RDAC and EEPROM registers independently. If the registers are protected by hardware, pull the WP pin low (only available in the LFCSP package). If the WP pin is pulled low when the part is executing a command, the protection is not enabled until the command is completed (only available in the LFCSP package). When RDAC is protected, the only operation allowed is to copy the EEPROM into the RDAC register. Burst Mode (I2C Only) By enabling the burst mode, multiple data bytes can be sent to the part consecutively. After the command byte, the part interprets the following consecutive bytes as data bytes for the command. A new command can be sent by generating a repeat start or by a stop and start condition. The burst mode is activated by setting Bit D3 of the control register (see Table 22). LOAD RDAC INPUT REGISTER (LRDAC) LRDAC software or hardware transfers data from the input register to the RDAC register (and therefore updates the wiper position). By default, the input register has the same value as the RDAC register; therefore, only the input register that has been updated using Command 2 is updated. Software LRDAC, Command 8, allows updating of a single RDAC register or all of the channels at once (see Table 20). This is a synchronous update. Reset The AD5124/AD5144/AD5144A can be reset through software by executing Command 14 (see Table 20) or through hardware on the low pulse of the RESET pin. The reset command loads the RDAC register with the contents of the EEPROM and takes approximately 30 µs. The EEPROM is preloaded to midscale at the factory, and initial power-up is, accordingly, at midscale. Tie RESET to VDD if the RESET pin is not used. The hardware LRDAC is completely asynchronous and copies the content of all the input registers into the associated RDAC registers. If a command is being executed, any transition in the LRDAC pin is ignored by the part to avoid data corruption. Rev. C | Page 28 of 36 Data Sheet AD5124/AD5144/AD5144A Table 20. Advance Commands Operation Truth Table Command Number 0 1 Control Bits[DB15:DB12] C3 C2 C1 C0 0 0 0 0 0 0 0 1 Address Bits[DB11:DB8] 1 A3 A2 A1 A0 X X X X A3 A2 A1 A0 D7 X D7 D6 X D6 Data Bits[DB7:DB0]1 D5 D4 D3 D2 D1 X X X X X D5 D4 D3 D2 D1 D0 X D0 2 2 0 0 1 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D02 3 0 0 1 1 X A2 A1 A0 X X X X X X D1 D0 4 5 6 7 8 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 A3 A3 A3 A3 A3 A2 A2 A2 A2 A2 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 1 0 X 9 0 1 1 1 0 0 A1 A0 X X X X X X X 1 10 11 0 1 1 0 1 0 1 0 0 0 0 0 A1 A1 A0 A0 X D7 X D6 X D5 X D4 X D3 X D2 X D1 0 D02 12 1 0 0 1 A3 A2 A1 A0 1 X X X X X X D0 13 1 0 0 1 A3 A2 A1 A0 0 X X X X X X D0 14 15 1 1 0 1 1 0 1 0 X A3 X A2 X A1 X A0 X X X X X X X X X X X X X X X D0 16 1 1 0 1 X X X X X X X X D3 D2 D1 D0 1 2 X = don’t care. D0 = don’t care for AD5124. Rev. C | Page 29 of 36 Operation NOP: do nothing Write contents of serial register data to RDAC Write contents of serial register data to input register Read back contents D1 D0 Data 0 0 Input register 0 1 EEPROM 1 0 Control register 1 1 RDAC Linear RDAC increment Linear RDAC decrement +6 dB RDAC increment −6 dB RDAC decrement Copy input register to RDAC (software LRDAC) Copy RDAC register to EEPROM Copy EEPROM into RDAC Write contents of serial register data to EEPROM Top scale D0 = 1; enter D0 = 0; exit Bottom scale D0 = 1; enter D0 = 0; exit Software reset Software shutdown D0 = 0; normal mode D0 = 1; device placed in shutdown mode Copy serial register data to control register AD5124/AD5144/AD5144A Data Sheet Table 21. Address Bits A3 1 0 0 0 0 0 0 0 0 1 A2 X1 0 1 0 1 0 1 0 1 A1 X1 0 0 0 0 1 1 1 1 A0 X1 0 0 1 1 0 0 1 1 Potentiometer Mode Input Register RDAC Register All channels All channels RDAC1 RDAC1 Not applicable Not applicable RDAC2 RDAC2 Not applicable Not applicable RDAC3 RDAC3 Not applicable Not applicable RDAC4 RDAC4 Not applicable Not applicable Linear Gain Setting Mode Input Register RDAC Register All channels All channels RWB1 RWB1 RAW1 RAW1 RWB2 RWB2 RAW2 RAW2 RWB3 RWB3 RAW3 RAW3 RWB4 RWB4 RAW4 RAW4 X = don’t care. Table 22. Control Register Bit Descriptions Bit Name D0 D1 D2 D3 Description RDAC register write protect 0 = wiper position frozen to value in EEPROM memory 1 = allows update of wiper position through digital interface (default) EEPROM program enable 0 = EEPROM program disabled 1 = enables device for EEPROM program (default) Linear setting mode/potentiometer mode 0 = potentiometer mode (default) 1 = linear gain setting mode Burst mode (I2C only) 0 = disabled (default) 1 = enabled (no disable after stop or repeat start condition) Rev. C | Page 30 of 36 Stored RDAC Memory Not applicable RDAC1 Not applicable RDAC2 Not applicable RDAC3 Not applicable RDAC4 Not applicable Data Sheet AD5124/AD5144/AD5144A RDAC ARCHITECTURE PROGRAMMING THE VARIABLE RESISTOR To achieve optimum performance, Analog Devices, Inc., has proprietary RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5124/AD5144 employ a three-stage segmentation approach, as shown in Figure 46. The AD5124/AD5144/AD5144A wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from VDD and VSS. Rheostat Operation—±8% Resistor Tolerance A A W STS B RH A W B W B 10877-049 A The AD5124/AD5144/AD5144A operate in rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be floating, or it can be tied to Terminal W, as shown in Figure 47. Figure 47. Rheostat Mode Configuration RH The nominal resistance between Terminal A and Terminal B, RAB, is 10 kΩ or 100 kΩ, and has 128/256 tap points accessed by the wiper terminal. The 7-bit/8-bit data in the RDAC latch is decoded to select one of the 128/256 possible wiper settings. The general equations for determining the digitally programmed output resistance between Terminal W and Terminal B are RM RM RL W RL 7-BIT/8-BIT ADDRESS DECODER AD5124: RM RWB ( D )  RH RM RH D  R AB  RW 128 From 0x00 to 0x7F (1) From 0x00 to 0xFF (2) AD5144/AD5144A: SBS RWB ( D )  10877-048 B Figure 46. AD5124/AD5144/AD5144A Simplified RDAC Circuit Top Scale/Bottom Scale Architecture In addition, the AD5124/AD5144/AD5144A include new positions to reduce the resistance between terminals. These positions are called bottom scale and top scale. At bottom scale, the typical wiper resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ). At top scale, the resistance between Terminal A and Terminal W is decreased by 1 LSB, and the total resistance is reduced to 60 Ω (RAB = 100 kΩ). D  R AB  RW 256 where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. In potentiometer mode, similar to the mechanical potentiometer, the resistance between Terminal W and Terminal A also produces a digitally controlled complementary resistance, RWA. RWA also gives a maximum of 8% absolute resistance error. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equations for this operation are AD5124: R AW ( D )  128  D  R AB  RW 128 From 0x00 to 0x7F (3) AD5144/AD5144A: R AW ( D )  256  D  R AB  RW 256 From 0x00 to 0xFF (4) where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. Rev. C | Page 31 of 36 AD5124/AD5144/AD5144A Data Sheet If the part is configured in linear gain setting mode, the resistance between Terminal W and Terminal A is directly proportional to the code loaded in the associate RDAC register. The general equations for this operation are AD5124: D  R AB  RW 128 From 0x00 to 0x7F (5) AD5144/AD5144A: The AD5124/AD5144/AD5144A are designed with internal ESD diodes for protection. These diodes also set the voltage boundary of the terminal operating voltages. Positive signals present on Terminal A, Terminal B, or Terminal W that exceed VDD are clamped by the forward-biased diode. There is no polarity constraint between VA, VW, and VB, but they cannot be higher than VDD or lower than VSS. VDD D RWB ( D )   R AB  RW 256 From 0x00 to 0xFF (6) A where: D is the decimal equivalent of the binary code in the 7-bit/8-bit RDAC register. RAB is the end-to-end resistance. RW is the wiper resistance. In the bottom scale condition or top scale condition, a finite total wiper resistance of 40 Ω is present. Regardless of which setting the part is operating in, limit the current between Terminal A to Terminal B, Terminal W to Terminal A, and Terminal W to Terminal B to the maximum continuous current of ±6 mA or to the pulse current specified in Table 7. Otherwise, degradation or possible destruction of the internal switch contact can occur. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A that is proportional to the input voltage at A to B, as shown in Figure 48. A VB Figure 48. Potentiometer Mode Configuration Connecting Terminal A to 5 V and Terminal B to ground produces an output voltage at the Wiper W to Terminal B ranging from 0 V to 5 V. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B is VW (D )  VSS Figure 49. Maximum Terminal Voltages Set by VDD and VSS POWER-UP SEQUENCE Because there are diodes to limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 49), it is important to power up VDD first before applying any voltage to Terminal A, Terminal B, and Terminal W. Otherwise, the diode is forward-biased such that VDD is powered unintentionally. The ideal power-up sequence is VSS, VDD, VLOGIC, digital inputs, and VA, VB, and VW. The order of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VSS, VDD, and VLOGIC. Regardless of the power-up sequence and the ramp rates of the power supplies, once VDD is powered, the power-on preset activates, which restores EEPROM values to the RDAC registers. LAYOUT AND POWER SUPPLY BIASING VOUT B B R (D) RWB (D )  VA  AW  VB RAB RAB (7) It is always a good practice to use a compact, minimum lead length layout design. Ensure that the leads to the input are as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance. It is also good practice to bypass the power supplies with quality capacitors. Apply low equivalent series resistance (ESR) 1 μF to 10 μF tantalum or electrolytic capacitors at the supplies to minimize any transient disturbance and to filter low frequency ripple. Figure 50 illustrates the basic supply bypassing configuration for the AD5124/AD5144/AD5144A. VDD where: RWB(D) can be obtained from Equation 1 and Equation 2. RAW(D) can be obtained from Equation 3 and Equation 4. Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors, RAW and RWB, and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C. VSS Rev. C | Page 32 of 36 + C3 10µF C1 0.1µF + C4 10µF C2 0.1µF VDD VLOGIC AD5124/ AD5144/ AD5144A + C5 0.1µF C6 10µF VLOGIC VSS GND 10877-052 W 10877-050 VA W 10877-051 RWB ( D )  TERMINAL VOLTAGE OPERATING RANGE Figure 50. Power Supply Bypassing Data Sheet AD5124/AD5144/AD5144A OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 4.10 4.00 SQ 3.90 1 0.50 BSC 2.20 2.10 SQ 2.00 EXPOSED PAD 13 0.50 0.40 0.30 TOP VIEW 0.80 0.75 0.70 SIDE VIEW PKG-004714 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE P IN 1 IN D IC ATO R AR E A OP T IO N S (SEE DETAIL A) 24 19 18 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 09-07-2018-B PIN 1 INDICATOR AREA 0.30 0.25 0.20 COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8 Figure 51. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.75 mm Package Height (CP-24-10) Dimensions shown in millimeters 6.60 6.50 6.40 20 11 4.50 4.40 4.30 6.40 BSC 1 10 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AC Figure 52. 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters Rev. C | Page 33 of 36 0.75 0.60 0.45 AD5124/AD5144/AD5144A Data Sheet ORDERING GUIDE Model 1, 2 AD5124BCPZ10-RL7 AD5124BCPZ100-RL7 AD5124BRUZ10 AD5124BRUZ100 AD5124BRUZ10-RL7 AD5124BRUZ100-RL7 AD5144BCPZ10-RL7 AD5144BCPZ100-RL7 AD5144BRUZ10 AD5144BRUZ100 AD5144BRUZ10-RL7 AD5144BRUZ100-RL7 AD5144ABRUZ10 AD5144ABRUZ100 AD5144ABRUZ10-RL7 AD5144ABRUZ100-RL7 EVAL-AD5144DBZ 1 2 RAB (kΩ) 10 100 10 100 10 100 10 100 10 100 10 100 10 100 10 100 Resolution 128 128 128 128 128 128 256 256 256 256 256 256 256 256 256 256 Interface SPI/I2C SPI/I2C SPI SPI SPI SPI SPI/I2C SPI/I2C SPI SPI SPI SPI I2 C I2 C I2 C I2 C Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 24-Lead LFCSP 24-Lead LFCSP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 24-Lead LFCSP 24-Lead LFCSP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP 20-Lead TSSOP Evaluation Board Package Option CP-24-10 CP-24-10 RU-20 RU-20 RU-20 RU-20 CP-24-10 CP-24-10 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 RU-20 Z = RoHS Compliant Part. The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with both of the available resistor value options. Rev. C | Page 34 of 36 Data Sheet AD5124/AD5144/AD5144A NOTES Rev. C | Page 35 of 36 AD5124/AD5144/AD5144A Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2012–2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10877-0-7/19(C) Rev. C | Page 36 of 36