AD5204BRU100

a FEATURES 256 Position Multiple Independently Programmable Channels AD5204—4-Channel AD5206—6-Channel Potentiometer Replacement 10 k , 50 k , 100 k 3-Wire SPI-Compatible Serial Data Input +2.7 V to +5.5 V Single Supply; 2.7 V Dual Supply Operation Power ON Midscale Preset APPLICATIONS Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Programmable Filters, Delays, Time Constants Line Impedance Matching CS CLK 4-/6-Channel Digital Potentiometers AD5204/AD5206 FUNCTIONAL BLOCK DIAGRAMS AD5204 EN A2 A1 A0 D7 ADDR DEC D0 D7 RDAC LATCH #1 R VDD A1 W1 B1 SDO DO SER REG D7 SDI DI D0 8 POWERON PRESET RDAC LATCH #4 D0 R A4 W4 B4 SHDN VSS PR GND GENERAL DESCRIPTION The AD5204/AD5206 provides four-/six-channel, 256 position digitally-controlled Variable Resistor (VR) devices. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. Each channel of the AD5204/ AD5206 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either endpoint of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance between the A terminal and the wiper or the B Terminal and the wiper. The fixed A-to-B terminal resistance of 10 kΩ, 50 kΩ, or 100 kΩ has a nominal temperature coefficient of 700 ppm/°C. Each VR has its own VR latch which holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register that is loaded from a standard 3-wire serial-input digital interface. Eleven data bits make up the data word clocked into the serial input register. The first three bits are decoded to determine which VR latch will be loaded with the last eight bits of the data word when the CS strobe is returned to logic high. A serial data output pin at the opposite end of the serial register (AD5204 only) allows simple daisy-chaining in multiple VR applications without additional external decoding logic. CS CLK EN A2 A1 A0 D7 ADDR DEC D0 D7 AD5206 VDD A1 W1 RDAC LATCH #1 R B1 SER REG D7 SDI DI D0 8 POWERON PRESET D0 RDAC LATCH #6 R VSS A6 W6 B6 GND An optional reset (PR) pin forces all the AD5204 wipers to the midscale position by loading 80H into the VR latch. The AD5204/AD5206 is available in both surface mount (SOL-24), TSSOP-24 and the 24-lead plastic DIP package. All parts are guaranteed to operate over the extended industrial temperature range of –40°C to +85 °C. For additional single, dual, and quad channel devices, see the AD8400/AD8402/ AD8403 products. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 ELECTRICAL CHARACTERISTICS unless otherwise noted.) Parameter Symbol Conditions AD5204/AD5206–SPECIFICATIONSor +3 V (V = +5 V 10% DD 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40 C < TA < +85 C Min –1 –2 –30 Typ1 ± 1/4 ± 1/2 700 0.25 50 8 –1 –2 –2 0 VSS Max +1 +2 +30 1.5 100 Units LSB LSB % ppm/° C % Ω Bits LSB LSB ppm/° C LSB LSB V pF pF µA nA V V V V µA pF V V µA µA mW %/% kHz kHz kHz % µs nV/√Hz ns ns ns ns ns ns ns ns ns ns DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs Resistor Differential NL 2 R-DNL RWB , VA = No Connect R-INL RWB , VA = No Connect Resistor Nonlinearity Error2 ∆RAB TA = +25° C Nominal Resistor Tolerance 3 VAB = V DD, Wiper = No Connect Resistance Temperature Coefficient ∆RAB/ ∆T CH1 to 2, 3, 4, or 5, 6; VAB = V DD Nominal Resistance Match ∆R/RAB Wiper Resistance RW IW = 1 V/R, VDD = +5 V DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs Resolution N DNL Differential Nonlinearity 4 INL Integral Nonlinearity 4 Code = 40H Voltage Divider Temperature Coefficient ∆VW/∆T Code = 7FH Full-Scale Error VWFSE Zero-Scale Error VWZSE Code = 00H RESISTOR TERMINALS Voltage Range5 Capacitance6 Ax, Bx Capacitance6 Wx Shutdown Current 7 Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Output Logic High Output Logic Low Input Current Input Capacitance6 POWER SUPPLIES Power Single Supply Range Power Dual Supply Range Positive Supply Current Negative Supply Current Power Dissipation 8 Power Supply Sensitivity DYNAMIC CHARACTERISTICS Bandwidth –3 dB 6, 9 ± 1/4 ± 1/2 15 –1 +1 +1 +2 0 +2 VDD VA, VB, VW CA, C B CW IA_SD ICM VIH VIL VOH VOL IIL CIL VDD Range VDD/SS Range IDD ISS PDISS PSS BW_10K BW_50K BW_100K THDW tS e N_WB f = 1 MHz, Measured to GND, Code = 40H f = 1 MHz, Measured to GND, Code = 40H VA = VB = VW = 0, VDD = +2.7 V, VSS = –2.5 V VDD = +5 V/+3 V VDD = +5 V/+3 V RPULL–UP = 1 kΩ to +5 V IOL = 1.6 mA, VLOGIC = +5 V VIN = 0 V or +5 V 2.4/2.1 45 60 0.01 1 5 0.8/0.6 4.9 0.4 ±1 5 VSS = 0 V VIH = +5 V or V IL = 0 V VSS = –2.5 V, VDD = +2.7 V VIH = +5 V or V IL = 0 V ∆VDD = +5 V ± 10% RAB = 10 kΩ RAB = 50 kΩ RAB = 100 kΩ VA = 1.414 V rms, V B = 0 V dc, f = 1 kHz VA = 5 V, VB = 0 V, ± 1 LSB Error Band RWB = 5 kΩ, f = 1 kHz, PR = 0 2.7 ± 2.3 12 12 0.0002 721 137 69 0.004 2/9/18 9 20 5 5 1 15 40 90 0 0 10 5.5 ± 2.7 60 60 0.3 0.005 Total Harmonic Distortion VW Settling Time (10K/50K/100K) Resistor Noise Voltage INTERFACE TIMING CHARACTERISTICS Applies to All Parts 6, 10 Input Clock Pulsewidth tCH , tCL Clock Level High or Low Data Setup Time tDS Data Hold Time tDH tPD RL = 2 kΩ, CL < 20 pF CLK to SDO Propagation Delay11 CS Setup Time tCSS CS High Pulsewidth tCSW Reset Pulsewidth tRS CLK Fall to CS Fall Setup tCSH0 CLK Fall to CS Rise Hold Time tCSH1 CS Rise to Clock Rise Setup tCS1 NOTES 1 2 150 Typicals represent average readings at +25 °C and VDD = +5 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 23 test circuit. I W = VDD/R for both VDD = +3 V or VDD = +5 V. 3 VAB = V DD, Wiper (VW ) = No connect. 4 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and V B = 0 V. DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions. See Figure 22 test circuit. –2– REV. 0 AD5204/AD5206 Resistor Terminals A, B, W, have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. 7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode. 8 PDISS is calculated from (I DD × V DD). CMOS logic level inputs result in minimum power dissipation. 9 All dynamic characteristics use V DD = +5 V. 10 See timing diagrams for location of measured values. All input control voltages are specified with t R = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both V DD = +3 V or +5 V. 11 Propagation delay depends on value of V DD, R L and C L. See Operation section. 6 5 Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* (TA = +25° C, unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V VA, VB, V W to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS , VDD Ax–Bx, Ax–Wx, Bx–Wx . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Digital Input and Output Voltage to GND . . . . . . . 0 V, +7 V Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C Package Power Dissipation . . . . . . . . . . . . . . (T J max–TA)/θJA Thermal Resistance θ JA P-DIP (N-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63°C/W SOIC (SOL-24) . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W TSSOP-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143°C/W *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5204/AD5206 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 – 3– AD5204/AD5206 1 SDI 0 1 CLK 0 1 CS 0 VOUT VDD 0V RDAC LATCH LOAD VOUT 0V 1 LSB ERROR BAND A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 PR 0 VDD 1 tRS tS 1 LSB Figure 3. AD5204 Preset Timing Diagram Figure 1. Timing Diagram SDI (DATA IN) 1 Ax OR Dx 0 Ax OR Dx tDS SDO (DATA OUT) 1 Ax OR Dx 0 Ax OR Dx tDH tCH 1 CLK 0 1 0 tPD_MAX tCS1 tCL tCSH1 tCSW tS tCSH0 tCSS CS VOUT VDD 0V 1 LSB ERROR BAND 1 LSB Figure 2. Detail Timing Diagram ORDERING GUIDE Model AD5204BN10 AD5204BR10 AD5204BRU10 AD5204BN50 AD5204BR50 AD5204BRU50 AD5204BN100 AD5204BR100 AD5204BRU100 AD5206BN10 AD5206BR10 AD5206BRU10 AD5206BN50 AD5206BR50 AD5206BRU50 AD5206BN100 AD5206BR100 AD5206BRU100 k 10 10 10 50 50 50 100 100 100 10 10 10 50 50 50 100 100 100 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Descriptions 24-Lead Narrow Body (PDIP) 24-Lead Wide Body (SOIC) 24-Lead Thin Shrink SO Package (TSSOP) 24-Lead Narrow Body (PDIP) 24-Lead Wide Body (SOIC) 24-Lead Thin Shrink SO Package (TSSOP) 24-Lead Narrow Body (PDIP) 24-Lead Wide Body (SOIC) 24-Lead Thin Shrink SO Package (TSSOP) 24-Lead Narrow Body (PDIP) 24-Lead Wide Body (SOIC) 24-Lead Thin Shrink SO Package (TSSOP) 24-Lead Narrow Body (PDIP) 24-Lead Wide Body (SOIC) 24-Lead Thin Shrink SO Package (TSSOP) 24-Lead Narrow Body (PDIP) 24-Lead Wide Body (SOIC) 24-Lead Thin Shrink SO Package (TSSOP) Package Options N-24 R-24/SOL-24 RU-24 N-24 R-24/SOL-24 RU-24 N-24 R-24/SOL-24 RU-24 N-24 R-24/SOL-24 RU-24 N-24 R-24/SOL-24 RU-24 N-24 R-24/SOL-24 RU -24 The AD5204/AD5206 contains 5,925 transistors. Die size; 92 mil × 114 mil, 10,488 sq. mil. –4– REV. 0 AD5204/AD5206 AD5204 PIN CONFIGURATION AD5206 PIN CONFIGURATION NC 1 NC 2 GND 3 CS 4 PR 5 VDD 6 SHDN 7 SDI 8 24 23 22 21 20 B4 W4 A4 B2 W2 A2 A1 W1 B1 A3 W3 B3 A6 1 W6 2 B6 3 GND 4 CS 5 VDD 6 SDI 7 CLK 8 VSS 9 B5 10 W5 11 A5 12 24 23 22 21 20 B4 W4 A4 B2 W2 A2 A1 W1 B1 A3 W3 B3 AD5204 (NOT TO SCALE) 19 18 17 16 15 14 13 AD5206 (NOT TO SCALE) 19 18 17 16 15 14 13 CLK 9 SDO 10 VSS 11 NC 12 NC = NO CONNECT AD5204 PIN FUNCTION DESCRIPTIONS AD5206 PIN FUNCTION DESCRIPTIONS Pin No. 1, 2, 12 3 4 Name NC GND CS Description Not Connected. Ground. Chip Select Input, Active Low. When CS returns high, data in the serial input register is decoded based on the address bits and loaded into the target RDAC latch. Active low preset to midscale; sets RDAC registers to 80H. Positive power supply, specified for operation at both +3 V or +5 V. (Sum of |VDD| + |VSS|