AD5231BRU100

FEATURES FUNCTIONAL BLOCK DIAGRAM AD5231 CS ADDR DECODE CLK RDAC REGISTER A SDI SDI W SERIAL INTERFACE GND SDO SDO WP EEMEM(0) DIGITAL REGISTER O1 2 EEMEM CONTROL RDY B DIGITAL OUTOUT BUFFER VSS PR Figure 1. 100 RWA (D), RWB (D); (% of Nominal RAB) Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Programmable voltage to current conversion Programmable filters, delays, time constants Programmable power supply Low resolution DAC replacement Sensor calibration O2 EEMEM(1) 28 BYTES USER EEMEM RWB RWA APPLICATIONS VDD RDAC 02739-001 1024-position resolution Nonvolatile memory maintains wiper setting Power-on refresh with EEMEM setting EEMEM restore time: 140 µs typ Full monotonic operation 10 kΩ, 50 kΩ, and 100 kΩ terminal resistance Permanent memory write protection Wiper setting readback Predefined linear increment/decrement instructions Predefined ±6 dB/step log taper increment/decrement instructions SPI®-compatible serial interface 3 V to 5 V single-supply or ±2.5 V dual-supply operation 28 bytes extra nonvolatile memory for user-defined data 100-year typical data retention, TA = 55°C 75 50 25 0 0 256 512 1023 768 CODE (Decimal) 02739-002 Data Sheet Nonvolatile Memory, 1024-Position Digital Potentiometer AD5231 Figure 2. RWA (D) and RWB (D) vs. Decimal Code GENERAL DESCRIPTION The AD5231 is a nonvolatile memory1, digitally controlled potentiometer2 with 1024-step resolution. The device performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and remote controllability. The AD5231 has versatile programming that uses a standard 3-wire serial interface for 16 modes of operation and adjustment, including scratchpad programming, memory storing and restoring, increment/decrement, ±6 dB/step log taper adjustment, wiper setting readback, and extra EEMEM for user-defined information, such as memory data for other components, look-up table, or system identification information. In scratchpad programming mode, a specific setting can be programmed directly to the RDAC register that sets the resistance between Terminals W–A and Terminals W–B. This setting can be stored into the EEMEM and is transferred automatically to the RDAC register during system power-on. The EEMEM content can be restored dynamically or through external PR strobing, and a WP function protects EEMEM contents. To simplify the programming, the linear-step increment or decrement commands can be used to move the RDAC wiper up or down, one step at a time. The ±6 dB step commands can be used to double or half the RDAC wiper setting. The AD5231 is available in a 16-lead TSSOP. The part is guaranteed to operate over the extended industrial temperature range of −40°C to +85°C. The terms nonvolatile memory and EEMEM are used interchangeably. The terms digital potentiometer and RDAC are used interchangeably. Rev. D Document Feedback 1 2 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2001–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5231 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Latched Digital Outputs ............................................................ 16 Applications ....................................................................................... 1 Advanced Control Modes ......................................................... 18 Functional Block Diagram .............................................................. 1 RDAC Structure.......................................................................... 19 General Description ......................................................................... 1 Programming the Variable Resistor ......................................... 19 Revision History ............................................................................... 2 Programming the Potentiometer Divider ............................... 20 Specifications..................................................................................... 3 Programming Examples ............................................................ 21 Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions .. 3 Flash/EEMEM Reliability .......................................................... 22 Timing Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ...... 5 Applications..................................................................................... 23 Absolute Maximum Ratings ............................................................ 7 Bipolar Operation from Dual Supplies.................................... 23 ESD Caution .................................................................................. 7 High Voltage Operation ............................................................ 23 Pin Configuration and Function Descriptions ............................. 8 Bipolar Programmable Gain Amplifier ................................... 23 Typical Performance Characteristics ............................................. 9 10-Bit Bipolar DAC .................................................................... 23 Test Circuits ..................................................................................... 13 10-Bit Unipolar DAC ................................................................. 24 Theory of Operation ...................................................................... 14 Programmable Voltage Source with Boosted Output ........... 24 Scratchpad and EEMEM Programming.................................. 14 Programmable Current Source ................................................ 24 Basic Operation .......................................................................... 14 Programmable Bidirectional Current Source ......................... 25 EEMEM Protection .................................................................... 14 Resistance Scaling ...................................................................... 25 Digital Input/Output Configuration ........................................ 15 RDAC Circuit Simulation Model ............................................. 26 Serial Data Interface ................................................................... 15 Outline Dimensions ....................................................................... 27 Daisy-Chain Operation ............................................................. 15 Ordering Guide .......................................................................... 27 Terminal Voltage Operation Range ......................................... 16 Power-Up Sequence ................................................................... 16 REVISION HISTORY 3/13—Rev. C to Rev. D 5/04—Rev. 0 to Rev. A Added tWP; Table 2 ............................................................................ 5 Updated formatting ............................................................ Universal Edits to Features, General Description, and Block Diagram ....... 1 Changes to Specifications ................................................................. 3 Replaced Timing Diagrams.............................................................. 6 Changes to Pin Function Descriptions ........................................... 8 Changes to Typical Performance Characteristics.......................... 9 Changes to Test Circuits ................................................................. 13 Edits to Theory of Operation ......................................................... 14 Edits to Applications ....................................................................... 23 Updated Outline Dimensions ........................................................ 27 Changes to Ordering Guide .......................................................... 27 1/07—Rev. B to Rev. C Updated Format .................................................................. Universal Changes to Dynamic Characteristics Specifications..................... 4 Changes to Table 2 Footnote ............................................................ 5 Changes to Table 3 ............................................................................. 7 Changes to Ordering Guide ...........................................................27 9/04—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Table 20 .........................................................................23 Changes to Resistance Scaling Section .........................................25 Changes to Ordering Guide ...........................................................27 12/01—Revision 0: Initial Version Rev. D | Page 2 of 28 Data Sheet AD5231 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS VDD = 3 V ± 10% or 5 V ± 10%, VSS = 0 V, VA = VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS— RHEOSTAT MODE Resistor Differential Nonlinearity 2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient Wiper Resistance DC CHARACTERISTICS— POTENTIOMETER DIVIDER MODE Resolution Differential Nonlinearity 3 Integral Nonlinearity3 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range 4 Capacitance A, B 5 Capacitance W5 Common-Mode Leakage Current5, 6 DIGITAL INPUTS AND OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Logic High Symbol Conditions Min Typ 1 Max Unit R-DNL R-INL ΔRAB/RAB (ΔRWB/RWB)/ΔT × 106 RW RWB, VA = NC, monotonic RWB,VA = NC D = 0x3FF −1 −0.2 −40 ±1/2 +1.8 +0.2 +20 LSB LSB % ppm/°C Ω N DNL Monotonic, TA = 25°C Monotonic, TA = −40°C or +85°C INL (ΔVW/VW)/ΔT × 106 Code = half scale VWFSE VWZSE Code = full scale Code = zero scale VA, B, W CA, B CW ICM VIH VIL VIH VIL VIH Input Logic Low VIL Output Logic High (SDO, RDY) VOH Output Logic Low VOL Input Current Input Capacitance5 Output Current5 IIL CIL IO1, IO2 600 15 IW = 100 µA, VDD = 5.5 V, code = half scale IW = 100 µA, VDD = 3 V, code = half scale 50 −1 −1 −0.4 10 +1 +1.25 +0.4 Bits LSB LSB LSB ppm/°C 0 1.5 % FS % FS VDD 50 V pF 50 pF ±1/2 −3 0 VSS VDD = 5 V, VSS = 0 V, TA = 25°C VDD = 2.5 V, VSS = 0 V, TA = 25°C Rev. D | Page 3 of 28 Ω 15 f = 1 MHz, measured to GND, code = half-scale f = 1 MHz, measured to GND, code = half-scale VW = VDD/2 With respect to GND, VDD = 5 V With respect to GND, VDD = 5 V With respect to GND, VDD = 3 V With respect to GND, VDD = 3 V With respect to GND, VDD = +2.5 V, VSS = −2.5 V With respect to GND, VDD = +2.5 V, VSS = −2.5 V RPULL-UP = 2.2 kΩ to 5 V (see Figure 26) IOL = 1.6 mA, VLOGIC = 5 V (see Figure 26) VIN = 0 V or VDD 100 0.01 1 2.4 0.8 2.1 0.6 2.0 0.5 4.9 µA V V V V V V V 4 50 7 0.4 V ±2.5 µA pF mA mA AD5231 Parameter POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current Data Sheet Symbol Conditions Min VDD VDD/VSS IDD ISS VSS = 0 V 2.7 ±2.25 EEMEM Store Mode Current IDD (store) EEMEM Restore Mode Current 7 ISS (store) IDD (restore) Power Dissipation 8 Power Supply Sensitivity5 DYNAMIC CHARACTERISTICS5, 9 Bandwidth Total Harmonic Distortion ISS (restore) PDISS PSS BW THDW VW Settling Time tS Resistor Noise Voltage eN_WB VIH = VDD or VIL = GND VIH = VDD or VIL = GND, VDD = +2.5 V, VSS = −2.5 V VIH = VDD or VIL = GND, VSS = GND, ISS ≈ 0 VDD = +2.5 V, VSS = −2.5 V VIH = VDD or VIL = GND, VSS = GND, ISS ≈ 0 VDD = +2.5 V, VSS = −2.5 V VIH = VDD or VIL = GND ΔVDD = 5 V ± 10% −3 dB, RAB = 10 kΩ/50 kΩ/ 100 kΩ VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kΩ VA = 1 V rms, VB = 0 V, f = 1 kHz, RAB = 50 kΩ, 100 kΩ VA = VDD, VB = 0 V, VW = 0.50% error band, Code 0x000 to 0x200 for RAB = 10 kΩ/50 kΩ/100 kΩ RWB = 5 kΩ, f = 1 kHz Typ 1 Max Unit 2.7 0.5 5.5 ±2.75 10 10 V V µA µA 40 0.3 −0.3 mA −40 3 9 mA mA −3 0.018 0.002 −9 0.05 0.01 mA mW %/% 370/85/44 kHz 0.045 % 0.022 % 1.2/3.7/7 µs 9 nV/√Hz Typical values represent average readings at 25°C and VDD = 5 V. Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. IW ~ 50 µA @ VDD = 2.7 V and IW ~ 400 µA @ VDD = 5 V for the RAB = 10 kΩ version, IW ~ 50 µA for the RAB = 50 kΩ, and IW ~ 25 µA for the RAB = 100 kΩ version (see Figure 26). 3 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of −1 LSB minimum are guaranteed monotonic operating condition (see Figure 27). 4 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables groundreferenced bipolar signal adjustment. 5 Guaranteed by design and not subject to production test. 6 Common-mode leakage current is a measure of the dc leakage from any Terminal B–W to a common-mode bias level of VDD/2. 7 EEMEM restore mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 23). To minimize power dissipation, a NOP Instruction 0 (0x0) should be issued immediately after Instruction 1 (0x1). 8 PDISS is calculated from (IDD × VDD) + (ISS × VSS). 9 All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V. 1 2 Rev. D | Page 4 of 28 Data Sheet AD5231 TIMING CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted. Table 2. Parameter INTERFACE TIMING CHARACTERISTICS2, 3 Clock Cycle Time (tCYC) CS Setup Time CLK Shutdown Time to CS Rise Input Clock Pulse Width Data Setup Time Data Hold Time CS to SDO-SPI Line Acquire CS to SDO-SPI Line Release CLK to SDO Propagation Delay4 CLK to SDO Data Hold Time CS High Pulse Width5 CS High to CS High5 RDY Rise to CS Fall CS Rise to RDY Fall Time Store/Read EEMEM Time6 Power-On EEMEM Restore Time Dynamic EEMEM Restore Time WP High or Low to CS Fall Time CS Rise to Clock Rise/Fall Setup Preset Pulse Width (Asynchronous) Preset Response Time to Wiper Setting Symbol t1 t2 t3 t4, t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 tEEMEM1 tEEMEM2 tWP t17 tPRW tPRESP Conditions Min Clock level high or low From positive CLK transition From positive CLK transition 20 10 1 10 5 5 RP = 2.2 kΩ, CL < 20 pF RP = 2.2 kΩ, CL < 20 pF FLASH/EE MEMORY RELIABILITY Endurance7 Data Retention8 0 10 4 0 0.1 25 140 140 40 10 50 0.15 Unit ns ns tCYC ns ns ns ns ns ns ns ns tCYC ns ms ms μs μs ns 70 ns ns μs 100 kCycles Years 100 1 Max 40 50 50 Applies to instructions 0x2, 0x3, and 0x9 RAB = 10 kΩ RAB = 10 kΩ Not shown in timing diagram PR pulsed low to refresh wiper positions Typ1 Typical values represent average readings at 25°C and VDD = 5 V. Guaranteed by design and not subject to production test. 3 See timing diagrams (Figure 3 and Figure 4) for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 35 V. 4 Propagation delay depends on the value of VDD, RPULL-UP, and CL. 5 Valid for commands that do not activate the RDY pin. 6 RDY pin low only for Instructions 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_2, 3 ~ 20 ms; CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.12 ms. Device operation at TA = −40°C and VDD < 3 V extends the EEMEM store time to 35 ms. 7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles. 8 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section. 2 Rev. D | Page 5 of 28 AD5231 Data Sheet Timing Diagrams CPHA = 1 t12 CS t3 t13 t1 t2 t5 CLK CPOL = 1 B23 B0 t17 t4 t7 t6 HIGH OR LOW B23–MSB t8 t11 t10 B23–MSB B24* SDO HIGH OR LOW B0–LSB t9 B0–LSB t14 t15 t16 RDY * NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED. THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK. 02739-003 SDI Figure 3. CPHA = 1 Timing Diagram CPHA = 0 CS t12 t1 t2 CLK CPOL = 0 B23 t13 t3 t5 B0 t17 t4 t6 HIGH OR LOW SDI HIGH OR LOW B0–LSB B23–MSB IN t8 SDO t11 t10 B23–MSB OUT B0–LSB t9 * t7 t14 t15 t16 * NOT DEFINED, BUT NORMALLY MSB OF CHARACTER PREVIOUSLY RECEIVED. THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK. Figure 4. CPHA = 0 Timing Diagram Rev. D | Page 6 of 28 02739-004 RDY Data Sheet AD5231 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameters VDD to GND VSS to GND VDD to VSS VA, VB, VW to GND A–B, A–W, B–W Intermittent 1 Continuous Digital Input and Output Voltage to GND Operating Temperature Range 2 Maximum Junction Temperature (TJ max) Storage Temperature Reflow Soldering Peak Temperature Time at Peak Temperature Thermal Resistance Junction-to-Ambient (θJA),TSSOP-16 Junction-to-Case (θJC), TSSOP-16 Package Power Dissipation Ratings –0.3 V, +7 V +0.3 V, −7 V 7V VSS − 0.3 V, VDD + 0.3 V ±20 mA ±2 mA −0.3 V, VDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION −40°C to +85°C 150°C −65°C to +150°C 260°C 20 sec to 40 sec 150°C/W 28°C/W (TJ max − TA)/θJA Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Includes programming of nonvolatile memory. 1 Rev. D | Page 7 of 28 AD5231 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS O1 1 16 O2 CLK 2 15 RDY 14 CS SDI 3 GND 5 AD5231 13 PR TOP VIEW (Not to Scale) 12 WP VSS 6 11 VDD T 7 10 A B 8 9 W 02739-005 SDO 4 Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic O1 2 3 4 CLK SDI SDO 5 6 GND VSS 7 8 9 10 11 12 T B W A VDD WP 13 PR 14 15 16 CS RDY O2 Description Nonvolatile Digital Output 1. ADDR = 0x1, data bit position D0. For example, to store O1 high, the data bit format is 0x310001. Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges. Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. Serial Data Output Pin. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and after the data-word (see Figure 3, Figure 4, and Table 7). In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 3 and Figure 4). This previously shifted-out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed. Ground Pin. Logic ground reference. Negative Supply. Connect to 0 V for single-supply applications. If VSS is used in dual-supply applications, it must be able to sink 40 mA for 25 ms when storing data to EEMEM. Reserved for factory testing. Connect to VDD or VSS. Terminal B of RDAC. Wiper Terminal of RDAC. ADDR (RDAC) = 0x0. Terminal A of RDAC. Positive Power Supply Pin. Optional Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR and Instruction 1 and Instruction 8 and refreshes the RDAC register from EEMEM. Execute a NOP instruction before returning to WP high. Tie WP to VDD, if not used. Optional Hardware Override Preset Pin. Refreshes the scratchpad register with current contents of the EEMEM register. Factory default loads midscale 51210 until EEMEM is loaded with a new value by the user. PR is activated at the logic high transition. Tie PR to VDD, if not used. Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high. Ready. Active-high open-drain output. Identifies completion of Instructions 2, 3, 8, 9, 10, and PR. Nonvolatile Digital Output 2. ADDR = 0x1, data bit position D1. For example, to store O2 high, the data bit format is 0x310002. Rev. D | Page 8 of 28 Data Sheet AD5231 TYPICAL PERFORMANCE CHARACTERISTICS 1.5 2.0 VDD = 5V, VSS = 0V TA = +85°C 1.5 1.0 TA = –40°C R-DNL (LSB) INL ERROR (LSB) 1.0 0.5 TA = +25°C 0 0.5 0 –0.5 TA = +25°C TA = +85°C TA = –40°C –1.0 –0.5 0 128 384 256 640 512 768 896 1024 CODE (Decimal) –2.0 02739-006 –1.0 0 640 512 384 CODE (Decimal) 768 896 1024 3000 2.0 VDD = 5.5V, VSS = 0V TA = –40°C TO +85°C VDD = 5V, VSS = 0V TA = –40°C 0.5 0 –0.5 TA = +85°C TA = +25°C –1.0 –2.0 0 128 256 384 640 512 768 896 1024 CODE (Decimal) 2000 1500 1000 500 0 02739-007 –1.5 2500 0 128 256 384 512 640 768 896 02739-010 1.0 RHEOSTAT MODE TEMPCO (ppm/°C) 1.5 1024 CODE (Decimal) Figure 10. (∆RWB/RWB)/∆T × 106 Figure 7. DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ 1.0 100 POTENTIOMETER MODE TEMPCO (ppm/°C) VDD = 5V, VSS = 0V 0.5 TA = +85°C 0 TA = +25°C –0.5 TA = –40°C –1.0 VDD = 5.5V, VSS = 0V TA = –40°C TO +85°C VB = 0V VA = 2.00V 80 60 40 20 0 128 256 384 512 640 CODE (Decimal) 768 896 1024 02739-008 –20 0 Figure 8. R-INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ Rev. D | Page 9 of 28 0 128 256 384 512 640 768 CODE (Decimal) Figure 11. (∆VW/VW)/∆T × 106 896 1024 02739-011 R-INL (LSB) 256 Figure 9. R-DNL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ Figure 6. INL vs. Code, TA = −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ DNL ERROR (LSB) 128 02739-009 –1.5 AD5231 Data Sheet 2 60 VDD = 2.7V, VSS = 0V TA = 25°C f–3dB = 37kHz, RAB = 10kΩ 0 50 –2 –4 GAIN (dB) RW (Ω) 40 30 f–3dB = 44kHz, RAB = 100kΩ –6 f–3dB = 85kHz, RAB = 50kΩ –8 –10 20 –12 10 128 0 384 256 640 512 768 896 1024 CODE (Decimal) –16 1k 02739-012 0 Figure 12. Wiper On Resistance vs. Code 10k 100k FREQUENCY (Hz) 1M 02739-015 VA = 1mV rms VDD/VSS = ±2.5V D = MIDSCALE –14 Figure 15. −3 dB Bandwidth vs. Resistance (Figure 32) 4 0.12 VDD/VSS = ±2.5V VA = 1V rms 0.10 IDD @ VDD/VSS = 5V/0V THD + NOISE (%) 2 1 ISS @ VDD/VSS = 5V/0V 0 0.08 0.06 RAB = 10kΩ 0.04 50kΩ 0.02 IDD @ VDD/VSS = 2.7V/0V 0 20 40 60 80 100 TEMPERATURE (°C) 02739-013 –20 0 0.01 1 10 100 FREQUENCY (kHz) Figure 13. IDD vs. Temperature, RAB = 10 kΩ Figure 16. Total Harmonic Distortion vs. Frequency 0.25 0 CODE = 0x200 VDD = 5V VSS = 0V –5 0.20 GAIN (dB) 0.15 FULL-SCALE 0.10 –10 0x100 –15 0x80 –20 0.05 0x40 –25 0x20 –30 –35 ZERO-SCALE 0x10 0x08 –40 MIDSCALE –45 0x04 0x02 0 0 2 4 6 8 10 CLOCK FREQUENCY (MHz) 12 02739-014 IDD (mA) 0.1 02739-016 100kΩ ISS @ VDD/VSS = 2.7V/0V –1 –40 Figure 14. IDD vs. Clock Frequency, RAB = 10 kΩ –50 1k 0x01 10k 100k 1M 10M FREQUENCY (Hz) Figure 17. Gain vs. Frequency vs. Code, RAB = 10 kΩ (Figure 32) Rev. D | Page 10 of 28 02739-017 CURRENT (µA) 3 Data Sheet AD5231 0 CODE = 0x200 VDD = 5V VA = 2.25V VB = 0V 100 –10 0x100 VA 90 0x80 –20 GAIN (dB) 0x40 –30 VW 0x20 EXPECTED VALUE 0x10 –40 0x08 MIDSCALE 0x04 0.5V/DIV 0x02 10 0% –60 1k 10k 1M 100k FREQUENCY (Hz) 02739-018 0x01 Figure 18. Gain vs. Frequency vs. Code, RAB = 50 kΩ (Figure 32) 100µs/DIV Figure 21. Power-On Reset, VA = 2.25 V, VB = 0 V, Code = 1010101010B 0 2.55 VDD/VSS = 5V/0V CODE = 0x200 TO 0x1FF CODE = 0x200 –10 02739-021 –50 0x100 2.53 0x80 –30 0x40 VOUT (V) GAIN (dB) –20 0x20 0x10 –40 0x08 –50 0x02 RAB = 10kΩ 2.51 RAB = 50kΩ RAB = 100kΩ 2.49 0x04 2.47 100k 10k 1M FREQUENCY (Hz) 2.45 02739-019 –60 1k 0 70 10 15 20 TIME (µs) 25 Figure 22. Midscale Glitch Energy, Code 0x200 to 0x1FF Figure 19. Gain vs. Frequency vs. Code, RAB = 100 kΩ (Figure 32) 80 5 02739-022 0x01 RAB = 100kΩ 5V/DIV RAB = 50kΩ CS 50 RAB = 10kΩ CLK 5V/DIV 40 30 SDI 5V/DIV 20 IDD 20mA/DIV 1M 10M 4ms/DIV Figure 20. PSRR vs. Frequency Figure 23. IDD vs. Time when Storing Data to EEMEM Rev. D | Page 11 of 28 02739-023 10 VDD = 5.0V ±100mV AC VSS = 0V, VA = 5V, VB = 0V MEASURED AT VW WITH CODE = 0x200 0 100 1k 10k 100k FREQUENCY (Hz) 02739-020 PSRR (–dB) 60 AD5231 Data Sheet 100 VA = VB = OPEN TA = 25°C 5V/DIV THEORETICAL—IWB_MAX (mA) CS CLK 5V/DIV SDI 5V/DIV 10 RAB = 10kΩ 1 RAB = 50kΩ 0.1 RAB = 100kΩ 0.01 0 *SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION IF INSTRUCTION 0 (NOP) IS EXECUTED IMMEDIATELY AFTER INSTRUCTION 1 (READ EEMEM). 02739-024 4ms/DIV Figure 24. IDD vs. Time when Restoring Data from EEMEM 128 256 384 512 640 CODE (Decimal) Figure 25. IWB_MAX vs. Code Rev. D | Page 12 of 28 768 896 1024 02739-025 IDD* 2mA/DIV Data Sheet AD5231 TEST CIRCUITS Figure 26 to Figure 35 define the test conditions used in the specifications. 5V NC DUT A W IW OP279 VIN OFFSET GND Figure 26. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) DUT B W DUT OP42 B OFFSET GND 02739-027 VMS +15V A VIN W V+ +2.5V Figure 27. Potentiometer Divider Nonlinearity Error (INL, DNL) Figure 32. Gain vs. Frequency W RSW = DUT A W IW VW 0.1V ISW CODE = 0x000 + RW = [VMS1 – VMS2]/IW VMS1 02739-028 B B 0.1V ISW – NC = NO CONNECT VBIAS 02739-033 A VOUT –15V NC DUT B Figure 31. Noninverting Gain V+ = VDD 1LSB = V+/2N A DUT OFFSET BIAS 02739-032 NC = NO CONNECT A 02739-026 VMS 02739-031 B VMS2 VOUT W Figure 33. Incremental On Resistance Figure 28. Wiper Resistance NC VA V+ W B VMS PSS (%/%) = ΔVMS% ΔVDD% VSS ICM W GND B VCM NC NC = NO CONNECT Figure 34. Common-Mode Leakage Current Figure 29. Power Supply Sensitivity (PSS, PSRR) A A VDD DUT ΔVMS PSRR (dB) = 20 log ΔVDD 02739-029 A 02739-034 V+ = VDD ±10% VDD 200µA DUT B IOL 5V OP279 OFFSET BIAS Figure 30. Inverting Gain TO OUTPUT PIN VOUT VOH (MIN) OR VOL (MAX) CL 50pF 200µA IOH 02739-057 OFFSET GND W 02739-030 VIN Figure 35. Load Circuit for Measuring VOH and VOL (The diode bridge test circuit is equivalent to the application circuit with RPULL-UP of 2.2 kΩ) Rev. D | Page 13 of 28 AD5231 Data Sheet THEORY OF OPERATION The AD5231 digital potentiometer is designed to operate as a true variable resistor replacement device for analog signals that remain within the terminal voltage range of VSS < VTERM < VDD. The basic voltage range is limited to VDD − VSS < 5.5 V. The digital potentiometer wiper position is determined by the RDAC register contents. The RDAC register acts as a scratchpad register, allowing as many value changes as necessary to place the potentiometer wiper in the correct position. The scratchpad register can be programmed with any position value using the standard SPI serial interface mode by loading the complete representative data-word. Once a desirable position is found, this value can be stored in an EEMEM register. Thereafter, the wiper position is always restored to that position for subsequent power-up. The storing of EEMEM data takes approximately 25 ms; during this time, the shift register is locked, preventing any changes from taking place. The RDY pin pulses low to indicate the completion of this EEMEM storage. The following instructions facilitate the user’s programming needs (see Table 7 for details): 0. Do nothing. 1. Restore EEMEM content to RDAC. 2. Store RDAC setting to EEMEM. 3. Store RDAC setting or user data to EEMEM. 4. Decrement 6 dB. 5. Decrement 6 dB. 6. Decrement one step. 7. Decrement one step. 8. Reset EEMEM content to RDAC. 9. Read EEMEM content from SDO. BASIC OPERATION The basic mode of setting the variable resistor wiper position (programming the scratchpad register) is accomplished by loading the serial data input register with Instruction 11 (0xB), Address 0, and the desired wiper position data. When the proper wiper position is determined, the user can load the serial data input register with Instruction 2 (0x2), which stores the wiper position data in the EEMEM register. After 25 ms, the wiper position is permanently stored in the nonvolatile memory. Table 5 provides a programming example listing the sequence of serial data input (SDI) words with the serial data output appearing at the SDO pin in hexadecimal format. Table 5. Set and Store RDAC Data to EEMEM Register SDI 0xB00100 SDO 0xXXXXXX 0x20XXXX 0xB00100 Action Writes data 0x100 to the RDAC register, Wiper W moves to 1/4 full-scale position. Stores RDAC register content into the EEMEM register. At system power-on, the scratchpad register is automatically refreshed with the value previously stored in the EEMEM register. The factory-preset EEMEM value is midscale, but it can be changed by the user thereafter. During operation, the scratchpad (RDAC) register can be refreshed with the EEMEM register data with Instruction 1 (0x1) or Instruction 8 (0x8). The RDAC register can also be refreshed with the EEMEM register data under hardware control by pulsing the PR pin. The PR pulse first sets the wiper at midscale when brought to logic zero, and then, on the positive transition to logic high, it reloads the RDAC wiper register with the contents of EEMEM. Many additional advanced programming commands are available to simplify the variable resistor adjustment process (see Table 7). For example, the wiper position can be changed one step at a time using the increment/decrement instruction or by 6 dB with the shift left/right instruction. Once an increment, decrement, or shift instruction has been loaded into the shift register, subsequent CS strobes can repeat this command. 10. Read RDAC wiper setting from SDO. 11. Write data to RDAC. 12. Increment 6 dB. 13. Increment 6 dB. A serial data output SDO pin is available for daisy-chaining and for readout of the internal register contents. 14. Increment one step. 15. Increment one step. EEMEM PROTECTION SCRATCHPAD AND EEMEM PROGRAMMING The scratchpad RDAC register directly controls the position of the digital potentiometer wiper. For example, when the scratchpad register is loaded with all zeros, the wiper is connected to Terminal B of the variable resistor. The scratchpad register is a standard logic register with no restriction on the number of changes allowed, but the EEMEM registers have a program erase/write cycle limitation (see the Flash/EEMEM Reliability section). The write protect (WP) pin disables any changes to the scratchpad register contents, except for the EEMEM setting, which can still be restored using Instruction 1, Instruction 8, and the PR pulse. Therefore, WP can be used to provide a hardware EEMEM protection feature. To disable WP, it is recommended to execute a NOP instruction before returning WP to logic high. Rev. D | Page 14 of 28 Data Sheet AD5231 DIGITAL INPUT/OUTPUT CONFIGURATION All digital inputs are ESD-protected, high input impedance that can be driven directly from most digital sources. Active at logic low, PR and WP must be tied to VDD if they are not used. No internal pull-up resistors are present on any digital input pins. The SDO and RDY pins are open-drain digital outputs that need pull-up resistors only if these functions are used. A resistor value in the range of 1 kΩ to 10 kΩ is a proper choice that balances the dissipation and switching speed. The equivalent serial data input and output logic is shown in Figure 36. The open-drain output SDO is disabled whenever chip-select CS is in logic high. ESD protection of the digital inputs is shown in Figure 37 and Figure 38. PR VALID COMMAND COUNTER WP COMMAND PROCESSOR AND ADDRESS DECODE 5V SDO GND DAISY-CHAIN OPERATION SERIAL REGISTER 02739-035 CS AD5231 SDI Figure 36. Equivalent Digital Input-Output Logic VDD INPUT 300Ω 02739-036 LOGIC PINS GND The serial data output pin (SDO) serves two purposes. It can be used to read the contents of the wiper setting and EEMEM values using Instruction 10 and Instruction 9, respectively. The remaining instructions (0 to 8, 11 to 15) are valid for daisychaining multiple devices in simultaneous operations. Daisychaining minimizes the number of port pins required from the controlling IC (see Figure 39). The SDO pin contains an open-drain N-Ch FET that requires a pull-up resistor if this function is used. As shown in Figure 39, users need to tie the SDO pin of one package to the SDI pin of the next package. Users might need to increase the clock period, because the pull-up resistor and the capacitive loading at the SDO to SDI interface might require additional time delay between subsequent packages. When two AD5231s are daisy-chained, 48 bits of data are required. The first 24 bits go to U2 and the second 24 bits go to U1. The CS should be kept low until all 48 bits are clocked into their respective serial registers. The CS is then pulled high to complete the operation. Figure 37. Equivalent ESD Digital Input Protection VDD WP The AD5231 has an internal counter that counts a multiple of 24 bits (a frame) for proper operation. For example, AD5231 works with a 48-bit word, but it cannot work properly with a 23-bit or 25-bit word. In addition, AD5231 has a subtle feature that, if CS is pulsed without CLK and SDI, the part repeats the previous command (except during power-up). As a result, care must be taken to ensure that no excessive noise exists in the CLK or CS line that might alter the effective number of bits (ENOB) pattern. Also, to prevent data from mislocking (due to noise, for example), the counter resets if the count is not a multiple of four when CS goes high. The SPI interface can be used in two slave modes: CPHA = 1, CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to the control bits that dictate SPI timing in the following MicroConverters® and microprocessors: ADuC812/ADuC824, M68HC11, and MC68HC16R1/916R1. RPULL-UP CLK returns high, the serial data-word is decoded according to the instructions in Table 7. The command bits (Cx) control the operation of the digital potentiometer. The address bits (Ax) determine which register is activated. The data bits (Dx) are the values that are loaded into the decoded register. INPUT 300Ω AD5231 µC Figure 38. Equivalent WP Input Protection SERIAL DATA INTERFACE SDI U1 CS The AD5231 contains a 4-wire SPI-compatible digital interface (SDI, SDO, CS, and CLK). It uses a 24-bit serial data-word loaded MSB first. The format of the SPI-compatible word is shown in Table 6. The chip-select CS pin must be held low until the complete data-word is loaded into the SDI pin. When CS Rev. D | Page 15 of 28 AD5231 RP 2kΩ SDO CLK SDI CS SDO U2 CLK 02739-038 GND 02739-037 +V Figure 39. Daisy-Chain Configuration Using SDO AD5231 Data Sheet TERMINAL VOLTAGE OPERATION RANGE POWER-UP SEQUENCE The AD5231’s positive VDD and negative VSS power supplies define the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on the A, B, and W terminals that exceed VDD or VSS are clamped by the internal forward-biased diodes (see Figure 40). Because there are diodes to limit the voltage compliance at the A, B, and W terminals (Figure 40), it is important to power VDD/VSS first before applying any voltage to Terminal A, Terminal B, and Terminal W. Otherwise, the diode is forwardbiased such that VDD/VSS are powered unintentionally and might affect the rest of the user’s circuit. The ideal power-up sequence is GND, VDD, VSS, digital inputs, and VA/VB/VW. The order of powering VA, VB, VW, and digital inputs is not important as long as they are powered after VDD/VSS. The ground pin of the AD5231 device is primarily used as a digital ground reference, which needs to be tied to the common ground of the PCB. The digital input control signals to the AD5231 must be referenced to the device ground pin (GND) and satisfy the logic level defined in the Specifications section. An internal level-shift circuit ensures that the common-mode voltage range of the three terminals extends from VSS to VDD, regardless of the digital input level. LATCHED DIGITAL OUTPUTS A W 02739-039 B A pair of digital outputs, O1 and O2, is available on the AD5231. These outputs provide a nonvolatile Logic 0 or Logic 1 setting. O1 and O2 are standard CMOS logic outputs, shown in Figure 41. These outputs are ideal to replace the functions often provided by DIP switches. In addition, they can be used to drive other standard CMOS logic-controlled parts that need an occasional setting change. Pin O1 and Pin O2 default to Logic 1, and they can drive up to 50 mA of load at 5 V/25°C. VDD Figure 40. Maximum Terminal Voltages Set by VDD and VSS OUTPUTS O1 AND O2 PINS GND Figure 41. Logic Outputs O1 and O2 Rev. D | Page 16 of 28 02739-040 VDD VSS Regardless of the power-up sequence and the ramp rates of the power supplies, once VDD/VSS are powered, the power-on preset remains effective, which restores the EEMEM value to the RDAC register. Data Sheet AD5231 In Table 6, command bits are C0 to C3, address bits are A3 to A0, Data Bit D0 to Data Bit D9 are applicable to RDAC, and D0 to D15 are applicable to EEMEM. Table 6. AD5231 24-Bit Serial Data-Word MSB Command Byte 0 RDAC EEMEM C3 C3 C2 C2 C1 C1 C0 C0 Data Byte 1 0 A3 0 A2 0 A1 0 A0 X D15 X D14 Data Byte 0 X D13 X D12 X D11 X D10 D9 D9 D8 D8 D7 D7 D6 D6 D5 D5 LSB D4 D4 D3 D3 D2 D2 D1 D1 D0 D0 Command instruction codes are defined in Table 7. Table 7. Command/Operation Truth Table 1, 2, 3 Instruction Number 0 1 Command Byte 0 B23 C3 C2 C1 C0 0 0 0 0 0 0 0 1 A1 X 0 B16 A0 X 0 Data Byte 1 B15 X … D9 X … X X … X B8 D8 X X Data Byte 0 B7 B0 D7 … D0 X … X X … X A3 X 0 A2 X 0 0 0 0 X … X X … X A3 A2 A1 A0 D15 … D8 D7 … D0 0 1 0 X 0 X 0 X 0 X X X … … X X X X X X … … X X Operation NOP: Do nothing. See Table 15. Restore EEMEM(0) contents to RDAC register. This command leaves the device in the read program power state. To return the part to the idle state, perform NOP instruction 0. See Table 15. Store Wiper Setting: Store RDAC setting to EEMEM(0). See Table 14. Store contents of Data Bytes 0 and 1 (total 16 bits) to EEMEM (ADDR 1to ADDR 15). See Table 17. Decrement RDAC by 6 dB. Same as Instruction 4. 2 0 0 1 0 0 34 0 0 1 1 45 55 0 0 1 1 0 0 65 0 1 5 7 8 9 0 1 1 0 0 0 0 0 X … X X X … X Decrement RDAC by 1 position. 1 1 X X X X X … X X X … X 1 1 Same as Instruction 6. 0 0 0 0 0 1 X A3 X A2 X A1 X A0 X X … … X X X X X X … … X X 1 0 1 0 0 0 0 0 X … X X X … X 11 1 0 1 1 0 0 0 0 X … D9 D8 D7 … D0 125 1 1 0 0 0 0 0 0 X … X X X … X Reset: Restore RDAC with EEMEM (0) value. Read EEMEM (ADDR 0 to ADDR 15) from SDO output in the next frame. See Table 18. Read RDAC wiper setting from SDO output in the next frame. See Table 19. Write contents of Data Bytes 0 and 1 (total 10 bits) to RDAC. See Table 13. Increment RDAC by 6 dB. See Table 16. 10 5 1 1 0 1 X X X X X … X X X … X Same as Instruction 12. 5 14 1 1 1 0 0 0 0 0 X … X X X … X Increment RDAC by 1 position. See Table 14. 155 1 1 1 1 X X X X X … X X X … X Same as Instruction 14. 13 X The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or Instruction 10, the selected internal register data is present in Data Byte 0 and Data Byte 1. The instruction following 9 and 10 must also be a full 24-bit data-word to completely clock out the contents of the serial register. 2 The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register. 3 Execution of these operations takes place when the CS strobe returns to logic high. 4 Instruction 3 writes two data bytes (16 bits of data) to EEMEM. In the case of 0 addresses, only the last 10 bits are valid for wiper position setting. 5 The increment, decrement, and shift instructions ignore the contents of the shift register Data Byte 0 and Data Byte 1. 1 Rev. D | Page 17 of 28 AD5231 Data Sheet ADVANCED CONTROL MODES makes the left-shift function as ideal a logarithmic adjustment as possible. Key programming features include: • Scratchpad programming to any desirable values • Nonvolatile memory storage of the scratchpad RDAC register value in the EEMEM register • Increment and decrement instructions for the RDAC wiper register The right-shift 4 and 5 instructions are ideal only if the LSB is 0 (ideal logarithmic = no error). If the LSB is 1, the right-shift function generates a linear half-LSB error, which translates to a number-of-bits dependent logarithmic error, as shown in Figure 42. The plot shows the error of the odd numbers of bits for the AD5231. Table 8. Detail Left-Shift and Right-Shift Functions for 6 dB Step Increment and Decrement Left-Shift 00 0000 0000 00 0000 0001 00 0000 0010 00 0000 0100 00 0000 1000 00 0001 0000 00 0010 0000 00 0100 0000 00 1000 0000 01 0000 0000 10 0000 0000 11 1111 1111 11 1111 1111 • Left and right bit shift of the RDAC wiper register to achieve ±6 dB level changes • 28 extra bytes of user-addressable nonvolatile memory Linear Increment and Decrement Instructions For an increment command, executing Instruction 14 with the proper address automatically moves the wiper to the next resistance segment position. Instruction 15 performs the same function, except that the address does not need to be specified. Logarithmic Taper Mode Adjustment Four programming instructions produce logarithmic taper increment and decrement of the wiper. These settings are activated by the 6 dB increment and 6 dB decrement instructions (12, 13, 4, and 5). For example, starting at zero scale, executing the increment Instruction 12 eleven times moves the wiper in 6 dB per step from 0% to full scale, RAB. The 6 dB increment instruction doubles the value of the RDAC register contents each time the command is executed. When the wiper position is near the maximum setting, the last 6 dB increment instruction causes the wiper to go to the full-scale 1023 code position. Further 6 dB per increment instructions do not change the wiper position beyond its full scale. The 6 dB step increments and 6 dB step decrements are achieved by shifting the bit internally to the left or right, respectively. The following information explains the nonideal ±6 dB step adjustment under certain conditions. Table 8 illustrates the operation of the shifting function on the RDAC register data bits. Each table row represents a successive shift operation. Note that the left-shift 12 and 13 instructions were modified such that, if the data in the RDAC register is equal to zero and the data is shifted left, the RDAC register is then set to Code 1. Similarly, if the data in the RDAC register is greater than or equal to midscale and the data is shifted left, then the data in the RDAC register is automatically set to full scale. This Left-Shift (+6 dB/step) Right-Shift (–6 dB/step) Actual conformance to a logarithmic curve between the data contents in the RDAC register and the wiper position for each right-shift 4 and 5 command execution contains an error only for odd numbers of bits. Even numbers of bits are ideal. The graph in Figure 42 shows plots of Log_Error [20 × log10 (error/code)] for the AD5231. For example, Code 3 Log_Error = 20 × log10 (0.5/3) = −15.56 dB, which is the worst case. The plot of Log_Error is more significant at the lower codes. 0 –20 (dB) The increment and decrement instructions (14, 15, 6, and 7) are useful for linear step-adjustment applications. These commands simplify microcontroller software coding by allowing the controller to send just an increment or decrement command to the device. Right-Shift 11 1111 1111 01 1111 1111 00 1111 1111 00 0111 1111 00 0011 1111 00 0001 1111 00 0000 1111 00 0000 0111 00 0000 0011 00 0000 0001 00 0000 0000 00 0000 0000 00 0000 0000 –40 –60 –80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 CODE (From 1 to 1023 by 2.0 × 103) 0.9 1.0 1.1 02739-041 The AD5231 digital potentiometer includes a set of user programming features to address the wide number of applications for these universal adjustment devices. Figure 42. Plot of Log_Error Conformance for Odd Numbers of Bits Only (Even Numbers of Bits Are Ideal) Rev. D | Page 18 of 28 Data Sheet AD5231 Using Additional Internal Nonvolatile EEMEM SWA A The AD5231 contains additional user EEMEM registers for storing any 16-bit data such as memory data for other components, look-up tables, or system identification information. Table 9 provides an address map of the internal storage registers shown in the functional block diagram as EEMEM1, EEMEM2, and 28 bytes (14 addresses × 2 bytes each) of user EEMEM. SW(2N–1) Table 9. EEMEM Address Map Address 0000 0001 0010 0011 … 1110 1111 EEMEM for… RDAC1, 2 O1 and O23 USER14 USER2 … USER13 USER14 RS = RAB/2N DIGITAL CIRCUITRY OMITTED FOR CLARITY RS W SW(2N–2) RS SW(1) RS SW(0) SWB B 02739-042 RDAC WIPER REGISTER AND DECODER Figure 43. Equivalent RDAC Structure (Patent Pending) RDAC data stored in EEMEM location is transferred to the RDAC register at power-on, or when Instruction 1, Instruction 8, or PR are executed. 2 Execution of Instruction 1 leaves the device in the read mode power consumption state. After the last Instruction 1 is executed, the user should perform a NOP, Instruction 0 to return the device to the low power idling state. 3 O1 and O2 data stored in EEMEM locations is transferred to the corresponding digital register at power-on, or when Instruction 1 and Instruction 8 are executed. 4 USERx are internal nonvolatile EEMEM registers available to store 16-bit information using Instruction 3 and restore the contents using Instruction 9. 1 RDAC STRUCTURE The patent-pending RDAC contains multiple strings of equal resistor segments with an array of analog switches that act as the wiper connection. The number of positions is the resolution of the device. The AD5231 has 1024 connection points, allowing it to provide better than 0.1% settability resolution. Figure 43 shows an equivalent structure of the connections among the three terminals of the RDAC. The SWA and SWB are always on, while the switches SW(0) to SW(2N−1) are on one at a time, depending on the resistance position decoded from the data bits. Because the switch is not ideal, there is a 15 Ω wiper resistance, RW. Wiper resistance is a function of supply voltage and temperature. The lower the supply voltage or the higher the temperature, the higher the resulting wiper resistance. Users should be aware of the wiper resistance dynamics if accurate prediction of the output resistance is needed. Table 10. Nominal Individual Segment Resistor (RS) Device Resolution 10-Bit 10 kΩ Version 9.8 Ω 50 kΩ Version 48.8 Ω 100 kΩ Version 97.6 Ω PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminal A and Terminal B, RAB, is available with 10 kΩ, 50 kΩ, and 100 kΩ with 1024 positions (10-bit resolution). The final digit(s) of the part number determine the nominal resistance value, for example, 10 kΩ = 10; 50 kΩ = 50; 100 kΩ = C. The 10-bit data-word in the RDAC latch is decoded to select one of the 1024 possible settings. The following discussion describes the calculation of resistance RWB at different codes of a 10 kΩ part. For VDD = 5 V, the wiper’s first connection starts at Terminal B for data 0x000. RWB(0) is 15 Ω because of the wiper resistance, and because it is independent of the nominal resistance. The second connection is the first tap point where RWB (1) becomes 9.7 Ω + 15 Ω = 24.7 Ω for data 0x001. The third connection is the next tap point representing RWB (2) = 19.4 Ω + 15 Ω = 34.4 Ω for data 0x002 and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at RWB (1023) = 10,005 Ω. See Figure 43 for a simplified diagram of the equivalent RDAC circuit. When RWB is used, Terminal A can be left floating or tied to the wiper. Rev. D | Page 19 of 28 AD5231 Data Sheet The general transfer equation for this operation is 100 RWB RWB (D) = 75 1024 − D × R AB + RW 1024 (2) For example, the output resistance values in Table 12 are set for the RDAC latch codes with VDD = 5 V (applies to RAB = 10 kΩ digital potentiometers). 50 Table 12. RWA(D) at Selected Codes for RAB = 10 kΩ D (DEC) 1023 512 1 0 25 0 0 256 512 CODE (Decimal) 768 1023 02739-043 RWA (D), RWB (D); (% of Nominal RAB) RWA Figure 44. RWA(D) and RWB(D) vs. Decimal Code The general equation that determines the programmed output resistance between W and B is RWB (D) = D × R AB + RW 1024 (1) where: D is the decimal equivalent of the data contained in the RDAC register. RAB is the nominal resistance between Terminal A and Terminal B. RW is the wiper resistance. For example, the output resistance values in Table 11 are set for the given RDAC latch codes with VDD = 5 V (applies to RAB = 10 kΩ digital potentiometers). Table 11. RWB (D) at Selected Codes for RAB = 10 kΩ D (DEC) 1023 512 1 0 RWB(D) (Ω) 10,005 50,015 24.7 15 RWA(D) (Ω) 24.7 5015 10005 10,015 Output State Full scale Midscale 1 LSB Zero scale The typical distribution of RAB from device to device matches tightly when they are processed in the same batch. When devices are processed at a different time, device-to-device matching becomes process-lot dependent and exhibits a −40% to +20% variation. The change in RAB with temperature has a 600 ppm/°C temperature coefficient. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer can be configured to generate an output voltage at the wiper terminal that is proportional to the input voltages applied to Terminal A and Terminal B. For example, connecting Terminal A to 5 V and Terminal B to ground produces an output voltage at the wiper that can be any value from 0 V to 5 V. Each LSB of voltage is equal to the voltage applied across Terminals A–B divided by the 2N position resolution of the potentiometer divider. Because AD5231 can also be supplied by dual supplies, the general equation defining the output voltage at VW with respect to ground for any given input voltages applied to Terminal A and Terminal B is Output State Full scale Midscale 1 LSB Zero scale (wiper contact resistor) Note that, in the zero-scale condition, a finite wiper resistance of 15 Ω is present. Care should be taken to limit the current flow between W and B in this state to no more than 20 mA to avoid degradation or possible destruction of the internal switches. Like the mechanical potentiometer that the RDAC replaces, the AD5231 part is totally symmetrical. The resistance between Wiper W and Terminal A also produces a digitally controlled complementary resistance, RWA. Figure 44 shows the symmetrical programmability of the various terminal connections. When RWA is used, Terminal B can be left floating or tied to the wiper. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch is increased in value. VW (D) = D × V AB + V B 1024 Equation 3 assumes that VW is buffered so that the effect of wiper resistance is minimized. Operation of the digital potentiometer in divider mode results in more accurate operation over temperature. Here, the output voltage is dependent on the ratio of the internal resistors and not the absolute value; therefore, the drift improves to 15 ppm/°C. There is no voltage polarity restriction between Terminal A, Terminal B, and Terminal W as long as the terminal voltage (VTERM) stays within VSS < VTERM < VDD. Rev. D | Page 20 of 28 (3) Data Sheet AD5231 PROGRAMMING EXAMPLES Table 17. Storing Additional User Data in EEMEM The following programming examples illustrate a typical sequence of events for various features of the AD5231. See Table 7 for the instructions and data-word format. The instruction numbers, addresses, and data appearing at SDI and SDO pins are in hexadecimal format. Table 13. Scratchpad Programming SDI 0xB00100 SDO 0xXXXXXX Action Writes data 0x100 into RDAC register, Wiper W moves to 1/4 full-scale position. SDI 0x32AAAA SDO 0xXXXXXX 0x335555 0x32AAAA Table 18. Reading Back Data from Memory Locations Table 14. Incrementing RDAC Followed by Storing the Wiper Setting to EEMEM SDI 0x92XXXX SDO 0xXXXXXX SDI 0xB00100 SDO 0xXXXXXX 0x00XXXX 0x92AAAA 0xE0XXXX 0xB00100 0xE0XXXX 0xE0XXXX 0x20XXXX 0xXXXXXX Action Writes data 0x100 into RDAC register, Wiper W moves to 1/4 full-scale position. Increments RDAC register by one to 0x101. Increments RDAC register by one to 0x102. Continue until desired wiper position is reached. Stores RDAC register data into EEMEM(0). Optionally tie WP to GND to protect EEMEM values. The EEMEM value for the RDAC can be restored by power-on, by strobing the PR pin, or by programming, as shown in Table 15. SDO 0xXXXXXX 0x00XXXX 0x10XXXX SDI 0xB00200 0xC0XXXX SDO 0xXXXXXX 0xB00200 0xA0XXXX 0xC0XXXX 0xXXXXXX 0xA003FF Action Restores the EEMEM(0) value to the RDAC register. NOP. Recommended step to minimize power consumption. Table 16. Using Left-Shift by One to Increment 6 dB Step SDI 0xC0XXXX SDO 0xXXXXXX Action Prepares data read from EEMEM(2) location. NOP Instruction 0 sends a 24-bit word out of SDO, where the last 16 bits contain the contents in the EEMEM(2) location. The NOP command ensures that the device returns to the idle power dissipation state. Table 19. Reading Back Wiper Settings Table 15. Restoring the EEMEM Value to the RDAC Register SDI 0x10XXXX Action Stores data 0xAAAA in the extra EEMEM location USER1. (Allowable to address in 14 locations with a maximum of 16 bits of data.) Stores data 0x5555 in the extra EEMEM location USER2. (Allowable to address in 14 locations with a maximum of 16 bits of data.) Action Moves the wiper to double the present data contained in the RDAC register. Rev. D | Page 21 of 28 Action Writes RDAC to midscale. Doubles RDAC from midscale to full scale (left-shift instruction). Prepares reading wiper setting from RDAC register. Reads back full-scale value from SDO. AD5231 Data Sheet FLASH/EEMEM RELIABILITY The Flash/EE memory array on the AD5231 is fully qualified for two key Flash/EE memory characteristics, namely Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through many program, read, and erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as • Read/verify sequence • Byte program sequence • Second read/verify sequence 300 During reliability qualification, Flash/EE memory is cycled from 0x000 to 0x3FF until a first fail is recorded signifying the endurance limit of the on-chip Flash/EE memory. As indicated in the Specifications section, the AD5231 Flash/EE memory endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of −40°C to +85°C. The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 cycles, with an endurance figure of 700,000 cycles being typical of operation at 25°C. 250 Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the AD5231 has been qualified in accordance with the formal JEDEC Retention Rev. D | Page 22 of 28 200 ANALOG DEVICES TYPICAL PERFORMANCE AT TJ = 55°C 150 100 50 0 40 50 60 70 80 90 100 TJ JUNCTION TEMPERATURE (°C) Figure 45. Flash/EE Memory Data Retention 110 02739-044 Initial page erase sequence RETENTION (Years) • Lifetime Specification (A117) at a specific junction temperature (TJ = 55°C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit, described previously, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash/EE memory is reprogrammed. It should also be noted that retention lifetime, based on an activation energy of 0.6 eV, derates with TJ, as shown in Figure 45. For example, the data is retained for 100 years at 55°C operation, but reduces to 15 years at 85°C operation. Beyond these limits, the part must be reprogrammed so that the data can be restored. Data Sheet AD5231 APPLICATIONS BIPOLAR OPERATION FROM DUAL SUPPLIES VDD U2 AD5231 A W B A B Vi U1 GND SCLK MOSI A W GND VSS D = MIDSCALE –2.5V HIGH VOLTAGE OPERATION The digital potentiometer can be placed directly in the feedback or input path of an op amp for gain control, provided that the voltage across Terminals A–B, Terminals W–A, or Terminals W–B does not exceed |5 V|. When high voltage gain is needed, users should set a fixed gain in an op amp operated at a higher voltage and let the digital potentiometer control the adjustable input. Figure 47 shows a simple implementation. 2R CC 2.2pF 15V A AD5231 – + R1 V+ OP2177 V– VSS VO  R2   2D2  = 1 + − 1 × VI  R1   1024  VO V– 0V TO 15V B Figure 47. 15 V Voltage Span Control BIPOLAR PROGRAMMABLE GAIN AMPLIFIER There are several ways to achieve bipolar gain. Figure 48 shows one versatile implementation. Digital potentiometer U1 sets the adjustment range; the wiper voltage VW2 can, therefore, be programmed between Vi and −KVi at a given U2 setting. For linear adjustment, configure A2 as a noninverting amplifier and the transfer function becomes VO R2   D2   = 1 + × (1 + K ) − K  × 1024 VI R1     (5) Table 20 shows the result of adjusting D with A2 configured as a unity gain, a gain of 2, and a gain of 10. The result is a bipolar amplifier with linearly programmable gain and 1024-step resolution. Table 20. Result of Bipolar Gain Amplifier D 0 256 512 768 1023 R1 = ∞, R2 = 0 −1 −0.5 0 0.5 0.992 R1 = R2 −2 −1 0 1 1.984 R2 = 9 × R1 −10 −5 0 5 9.92 10-BIT BIPOLAR DAC V+ A1 W 02739-046 5V VDD In the simpler (and much more usual) case where K = 1, a pair of matched resistors can replace U1. Equation 4 can be simplified to Figure 46. Bipolar Operation from Dual Supplies R VSS Figure 48. Bipolar Programmable Gain Amplifier B AD5231 –KVi A ±2.5V p-p ±1.25V p-p 02739-045 µC VDD CS CLK SDI A2 W AD5231 SS VO CC 2.2pF R2 +2.5V VDD V+ OP2177 V– 02739-047 The AD5231 can be operated from dual supplies ±2.5 V, which enables control of ground referenced ac signals or bipolar operation. AC signals as high as VDD/VSS can be applied directly across Terminal A to Terminal B with output taken from Terminal W. See Figure 46 for a typical circuit connection. If the circuit in Figure 48 is changed with the input taken from a voltage reference and A2 configured as a buffer, a 10-bit bipolar DAC can be realized. Compared to the conventional DAC, this circuit offers comparable resolution but not the precision because of the wiper resistance effects. Degradation of the nonlinearity and temperature coefficient is prominent near both ends of the adjustment range. On the other hand, this circuit offers a unique nonvolatile memory feature that in some cases outweighs any shortfall in precision. The output of this circuit is (4) where: K is the ratio of RWB/RWA that is set by U1. D is the decimal equivalent of the input code. Rev. D | Page 23 of 28  2D 2  − 1 × V REF VO =   1024  (6) AD5231 Data Sheet PROGRAMMABLE CURRENT SOURCE +5V U1 W +5V A A2 R VIN VOUT +5V +2.5VREF TRIM GND –5V –2.5VREF VIN 3 V+ AD8552 V– SLEEP VOUT GND A1 –5V –2.048V TO VL V+ RS 102Ω OP1177 U2 V– –5V VL RL 100Ω IL Figure 52. Programmable Current Source 5V AD5231 U1 3 VIN V OUT A W REF191 is a unique low supply, headroom precision reference that can deliver the 20 mA needed at 2.048 V. The load current is simply the voltage across Terminals B–W of the digital potentiometer divided by RS: 1 AD1582 5V V+ AD8601 V– VO IL = 02739-049 B GND A1 Figure 50. 10-Bit Unipolar DAC PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT For applications that require high current adjustment, such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see Figure 51). VIN VOUT AD5231 2N7002 SIGNAL CC U2 RBIAS IL V+ AD8601 V– V REF × D R S × 1024 (7) The circuit is simple, but be aware that there are two issues. First, dual-supply op amps are ideal because the ground potential of REF191 can swing from −2.048 V at zero scale to VL at full scale of the potentiometer setting. Although the circuit works under single-supply, the programmable resolution of the system is reduced. Second, the voltage compliance at VL is limited to 2.5 V or equivalently a 125 Ω load. Should higher voltage compliance be needed, users can consider digital potentiometers AD5260, AD5280, and AD7376. Figure 53 shows an alternate circuit for high voltage compliance. To achieve higher current, such as when driving a high power LED, the user can replace the UI with an LDO, reduce RS, and add a resistor in series with the digital potentiometer’s A terminal. This limits the potentiometer’s current and increases the current adjustment resolution. LD 02739-058 B W +5V Figure 50 shows a unipolar 10-bit DAC using AD5231. The buffer is needed to drive various leads. W B C1 1µF A AD5231 10-BIT UNIPOLAR DAC A 0V TO (2.048V + VL) 4 Figure 49. 10-Bit Bipolar DAC 2 6 REF191 02739-048 ADR421 U1 2 R 02739-051 B A programmable current source can be implemented with the circuit shown in Figure 52. VO + +5V V+ AD8552 V– – AD5231 Figure 51. Programmable Booster Voltage Source In this circuit, the inverting input of the op amp forces the VOUT to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-Ch FET N1. N1 power handling must be adequate to dissipate (Vi − VO) × IL power. This circuit can source a maximum of 100 mA with a 5 V supply. For precision applications, a voltage reference such as ADR421, ADR03, or ADR370 can be applied at Terminal A of the digital potentiometer. Rev. D | Page 24 of 28 Data Sheet AD5231 RESISTANCE SCALING For applications that require bidirectional current control or higher voltage compliance, a Howland current pump can be a solution. If the resistors are matched, the load current is (R2A + R2B ) × VW (8) R2 15kΩ A1 A2 W1 B1 C1 +15V 10pF – +15V A + AD5231 B W –2.5V V+ OP2177 – V– In voltage diver mode, by paralleling a discrete resistor as shown in Figure 55, a proportionately lower voltage appears at Terminals A–B. This translates into a finer degree of precision, because the step size at Terminal W is smaller. The voltage can be found as follows: R2B 50Ω –15V R1 150kΩ A1 –15V R2A 14.95kΩ VL RL 500Ω IL 02739-052 +2.5V LD Figure 54. Reduce Resistance by Half with Linear Adjustment Characteristics V+ OP2177 + V– A2 VW (D) = Figure 53. Programmable Bidirectional Current Source (RAB // R2 ) R3 + RAB // R2 R2B, in theory, can be made as small as necessary to achieve the current needed within the A2 output current-driving capability. In this circuit, OP2177 delivers ±5 mA in both directions, and the voltage compliance approaches 15 V. It can be shown that the output impedance is ZO = R1' R2B (R1 + R2A) R1R2' − R1' (R2A + R2B) W2 B2 D 1024 × VDD (10) R3 A R1 R2 B (9) ZO can be infinite if resistors R1 and R2 match precisely with R1 and R2A + R2B, respectively. On the other hand, ZO can be negative if the resistors are not matched. As a result, C1, in the range of 1 pF to 10 pF, is needed to prevent oscillation from the negative impedance. × W 02739-059 R1 150kΩ Figure 55. Lowering the Nominal Resistance Figure 54 and Figure 55 show that the digital potentiometers change steps linearly. On the other hand, pseudo log taper adjustment is usually preferred in applications such as audio control. Figure 56 shows another type of resistance scaling. In this configuration, the smaller the R2 with respect to R1, the more the pseudo log taper characteristic of the circuit behaves. A VO R1 B W R2 02739-055 R1 R2B IL = The AD5231 offers 10 kΩ, 50 kΩ, and 100 kΩ nominal resistance. For users who need lower resistance but want to maintain the number of adjustment steps, they can parallel multiple devices. For example, Figure 54 shows a simple scheme of paralleling two AD5231s. To adjust half the resistance linearly per step, users need to program both devices coherently with the same settings and tie the terminals as shown. 02739-053 PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE Figure 56. Resistor Scaling with Pseudo Log Adjustment Characteristics Rev. D | Page 25 of 28 AD5231 Data Sheet RDAC CIRCUIT SIMULATION MODEL The internal parasitic capacitances and the external load dominates the ac characteristics of the RDACs. The −3 dB bandwidth of the AD5231BRU10 (10 kΩ resistor) measures 370 kHz at half scale when configured as a potentiometer divider. Figure 15 provides the large signal BODE plot characteristics. A parasitic simulation mode is shown in Figure 57. RDAC 10kΩ B CA 50pF CB 50pF CW 50pF W .PARAM D = 1024, RDAC = 10E3 * .SUBCKT DPOT (A, W, B) * CA A 0 50E-12 RWA A W {(1-D/1024)* RDAC + 15} CW W 0 50E-12 RWB W B {D/1024 * RDAC + 15} CB B 0 50E-12 * .ENDS DPOT 02739-056 A The following code provides a macro model net list for the 10 kΩ RDAC: Figure 57. RDAC Circuit Simulation Model for RDAC = 10 kΩ Rev. D | Page 26 of 28 Data Sheet AD5231 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.65 BSC 0.30 0.19 COPLANARITY 0.10 8° 0° SEATING PLANE 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 58. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5231BRU10 AD5231BRU10-REEL7 AD5231BRUZ10 AD5231BRUZ10-REEL7 AD5231BRUZ50 AD5231BRUZ50-REEL7 AD5231BRU100 AD5231BRU100-REEL7 AD5231BRUZ100 AD5231BRUZ100-RL7 1 RAB (kΩ) 10 10 10 10 50 50 100 100 100 100 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP 16-Lead TSSOP Z = RoHS Compliant Part. Rev. D | Page 27 of 28 Package Option RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 Ordering Quantity 96 1,000 96 1,000 96 1,000 96 1,000 96 1,000 AD5231 Data Sheet NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. ©2001–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02739-0-3/13(D) Rev. D | Page 28 of 28