AD5292SRU-20-EP

1024-Position, Digital Potentiometer with Maximum ±1% R-Tolerance Error and 20-TP Memory AD5292-EP Enhanced Product FEATURES FUNCTIONAL BLOCK DIAGRAM ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC) Temperature range: −55°C to +125°C Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request VDD RESET AD5292-EP POWER-ON RESET VLOGIC RDAC REGISTER SCLK SYNC SERIAL INTERFACE A DATA W OTP MEMORY BLOCK DIN B SDO RDY VSS EXT_CAP GND 10095-001 Single-channel, 1024-position resolution 20 kΩ nominal resistance Maximum ±1% nominal resistor tolerance error (resistor performance mode) 20-times programmable wiper memory Rheostat mode temperature coefficient: 35 ppm/°C Voltage divider temperature coefficient: 5 ppm/°C +9 V to +33 V single-supply operation ±9 V to ±16.5 V dual-supply operation SPI-compatible serial interface Wiper setting readback Power-on refreshed from 20-TP memory Figure 1. APPLICATIONS Mechanical potentiometer replacement Instrumentation: gain and offset adjustment Programmable voltage-to-current conversion Programmable filters, delays, and time constants Programmable power supply Low resolution DAC replacement Sensor calibration GENERAL DESCRIPTION The AD5292-EP is a single-channel, 1024-position digital potentiometer1 that combines industry leading variable resistor performance with nonvolatile memory (NVM) in a compact package. This device is capable of operating across a wide voltage range, supporting both dual supply operation at ±10.5 V to ±16.5 V and single-supply operation at +21 V to +33 V, while ensuring less than 1% end-to-end resistor tolerance error and offering 20time programmable (20-TP) memory. The AD5292-EP device wiper settings are controllable through the SPI digital interface. Unlimited adjustments are allowed before programming the resistance value into the 20-TP memory. The AD5292-EP does not require any external voltage supply to facilitate fuse blow, and there are 20 opportunities for permanent programming. During 20-TP activation, a permanent blow fuse command freezes the wiper position (analogous to placing epoxy on a mechanical trimmer). The guaranteed industry leading low resistor tolerance error feature simplifies open-loop applications as well as precision calibration and tolerance matching applications. The AD5292-EP is available in a compact 14-lead TSSOP package. The part is guaranteed to operate over the extended industrial temperature range of −55°C to +125°C. 1 The terms digital potentiometer and RDAC are used interchangeably. Rev. A Additional application and technical information can be found in the AD5292 data sheet. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2011–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD5292-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Interface Timing Specifications ...................................................5 Enhanced Product Features ............................................................ 1 Absolute Maximum Ratings ............................................................7 Applications ....................................................................................... 1 Thermal Resistance .......................................................................7 Functional Block Diagram .............................................................. 1 ESD Caution...................................................................................7 General Description ......................................................................... 1 Pin Configuration and Function Descriptions..............................8 Revision History ............................................................................... 2 Typical Performance Characteristics ..............................................9 Specifications..................................................................................... 3 Test Circuits..................................................................................... 14 Electrical Characteristics—AD5292-EP.................................... 3 Outline Dimensions ....................................................................... 15 Resistor Performance Mode Code Range ................................. 4 Ordering Guide .......................................................................... 15 REVISION HISTORY 4/2018—Rev. 0 to Rev. A Change to Enhanced Product Features Section ........................... 1 Changes to Ordering Guide .......................................................... 15 9/2011—Revision 0: Initial Version Rev. A | Page 2 of 16 Enhanced Product AD5292-EP SPECIFICATIONS ELECTRICAL CHARACTERISTICS—AD5292-EP VDD = 21 V to 33 V, VSS = 0 V; VDD = 10.5 V to 16.5 V, VSS = −10.5 V to −16.5 V; VLOGIC = 2.7 V to 5.5 V, VA = VDD, VB = VSS, −55°C < TA < +125°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS—RHEOSTAT MODE Resolution Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance (R-Perf Mode)3 Nominal Resistor Tolerance (Normal Mode)4 Resistance Temperature Coefficient Wiper Resistance DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE Resolution Differential Nonlinearity5 Integral Nonlinearity5 Voltage Divider Temperature Coefficient4 Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Terminal Voltage Range6 Capacitance A, Capacitance B4 Capacitance W4 Common-Mode Leakage Current4 DIGITAL INPUTS Input Logic High4 Input Logic Low4 Input Current Input Capacitance4 DIGITAL OUTPUTS (SDO and RDY) Output High Voltage4 Output Low Voltage4 Three-State Leakage Current Output Capacitance4 POWER SUPPLIES Single-Supply Power Range Dual-Supply Power Range Positive Supply Current Negative Supply Current Logic Supply Range Logic Supply Current OTP Store Current4, 7 OTP Read Current4, 8 Power Dissipation9 Power Supply Rejection Ratio Symbol Conditions Min N R-DNL R-INL R-INL ∆RAB/RAB ∆RAB/RAB RWB, VA = NC RAB =20 kΩ, |VDD − VSS| = 26 V to 33 V RAB =20 kΩ, |VDD − VSS| = 21 V to 26 V See Table 2 10 −1 −2 −3 −1 (∆RAB/RAB)/∆T × 106 RW Code = full scale; see Figure 14 Code= zero scale N DNL INL (∆VW/VW)/∆T × 106 VWFSE VWZSE VA, VB, VW CA, CB CW ICM VIH VIL IIL CIL VOH VOL Typ1 ±0.5 ±7 35 60 10 −1 −2.5 Code = half scale; see Figure 17 Code = full scale Code = zero scale +1 +2 +3 +1 Bits LSB LSB LSB % % 100 5 −8 0 −120 +1 10 VDD 65 pF ±1 120 nA 0.8 ±1 V V µA pF GND + 0.4 +1 V V µA pF VLOGIC − 0.4 −1 5 VSS = 0 V VDD/VSS = ±16.5 V VDD/VSS = ±16.5 V VLOGIC = 5 V, VIH = 5 V or VIL = GND VIH = 5 V or VIL = GND VIH = 5 V or VIL = GND VIH = 5 V or VIL = GND ∆VDD/∆VSS = ±15 V ± 10% Rev. A | Page 3 of 16 9 ±9 −2 2.7 Bits LSB LSB ppm/°C LSB LSB V pF 5 RPULL_UP = 2.2 kΩ to VLOGIC RPULL_UP = 2.2 kΩ to VLOGIC ppm/°C Ω 85 2.0 COL VDD VDD/VSS IDD ISS VLOGIC ILOGIC ILOGIC_PROG ILOGIC_FUSE_READ PDISS PSRR Unit +1 +2.5 VSS f = 1 MHz, measured to GND, code = half scale f = 1 MHz, measured to GND, code = half scale VA = VB = VW JEDEC compliant VLOGIC = 2.7 V to 5.5 V VLOGIC = 2.7 V to 5.5 V VIN = 0 V or VLOGIC Max 0.1 −0.1 1 25 25 8 0.103 33 ±16.5 2 5.5 10 110 V V µA µA V µA mA mA µW %/% AD5292-EP Enhanced Product Parameter DYNAMIC CHARACTERISTICS5, 10 Bandwidth Total Harmonic Distortion VW Settling Time Resistor Noise Density Symbol Conditions BW THDW tS −3 dB VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 30 V, VB = 0 V, ±0.5 LSB error band, initial code = zero scale, board capacitance = 170 pF Code = full-scale, normal mode Code = full-scale, R-Perf mode Code = half-scale, normal mode Code = half-scale, R-Perf mode Code = half-scale, TA = 25°C, 0 kHz to 200 kHz eN_WB Min Typ1 Max Unit 520 −93 kHz dB 750 2.5 2.5 5 10 ns µs µs µs nV/√Hz Typical values represent average readings at 25°C, VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V. Resistor position nonlinearity error. R-INL is the deviation from an ideal value measured between RWB at Code 0x00B and Code 0x3FF or between RWA at Code 0x3F3 and Code 0x000. R-DNL measures the relative step change from ideal between successive tap positions. The specification is guaranteed in resistor performance mode, with a wiper current of 1 mA for VA < 12 V and 1.2 mA for VA ≥ 12 V. 3 Resistor performance mode. The terms resistor performance mode and R-Perf mode are used interchangeably. 4 Guaranteed by design and characterization, not subject to production test. 5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables groundreferenced bipolar signal adjustment. 7 Different from operating current; supply current for fuse program lasts approximately 550 µs. 8 Different from operating current; supply current for fuse read lasts approximately 550 µs. 9 PDISS is calculated from (IDD × VDD) + (ISS × VSS) + (ILOGIC × VLOGIC). 10 All dynamic characteristics use VDD = 15 V, VSS = −15 V, and VLOGIC = 5 V. 1 2 RESISTOR PERFORMANCE MODE CODE RANGE Table 2. Resistor Tolerance per Code 1% R-Tolerance 2% R-Tolerance 3% R-Tolerance |VDD − VSS| = 30 V to 33 V RWB RWA From 0x1EF From 0x000 to 0x3FF to 0x210 From 0x0C3 From 0x000 to 0x3FF to 0x33C From 0x073 From 0x000 to 0x3FF to 0x38C −55°C < TA < +125°C |VDD − VSS| = 26 V to 30 V |VDD − VSS| = 22 V to 26 V RWB RWA RWB RWA From 0x1F4 From 0x000 From 0x1F4 From 0x000 to 0x3FF to 0x20B to 0x3FF to 0x20B From 0x0E6 From 0x000 From 0x131 From 0x000 to 0x3FF to 0x319 to 0x3FF to 0x2CE From 0x087 From 0x000 From 0x0AF From 0x000 to 0x3FF to 0x378 to 0x3FF to 0x350 Rev. A | Page 4 of 16 |VDD − VSS| = 21 V to 22 V RWB RWA N/A N/A From 0x131 to 0x3FF From 0x0AF to 0x3FF From 0x000 to 0x2CE From 0x000 to 0x350 Enhanced Product AD5292-EP INTERFACE TIMING SPECIFICATIONS VDD/VSS = ±15 V, VLOGIC = 2.7 V to 5.5 V, −55°C < TA < +125°C. All specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter t12 t2 t3 t4 t5 t6 t7 t8 t9 t104 t114 Limit1 20 10 10 10 5 5 1 4003 14 1 40 t124 t124 t Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max Description SCLK cycle time SCLK high time SCLK low time SYNC to SCLK falling edge setup time Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time SYNC rising edge to next SCLK fall ignore RDY rising edge to SYNC falling edge SYNC rising edge to RDY fall time 2.4 μs max RDY low time, RDAC register write command execute time (R-Perf mode) 410 ns max RDY low time, RDAC register write command execute time (normal mode) 8 ms max RDY low time, memory program execute time t124 1.5 ms min Software/hardware reset t 134 450 ns max RDY low time, RDAC register readback execute time t134 1.3 ms max RDY low time, memory readback execute time t144 450 ns max SCLK rising edge to SDO valid tRESET tPOWER-UP5 20 2 ns min ms max Minimum RESET pulse width (asynchronous) Power-on OTP restore time 124 1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Maximum SCLK frequency is 50 MHz. Refer to t12 and t13 for RDAC register and memory commands operations. 4 RPULL_UP = 2.2 kΩ to VLOGIC, with a capacitance load of 168 pF. 5 Maximum time after VLOGIC is equal to 2.5 V. 2 3 0 0 C3 C2 C1 C0 D9 D8 DB0 (LSB) D7 D6 D5 D4 DATA BITS CONTROL BITS Figure 2. Shift Register Content Rev. A | Page 5 of 16 D3 D2 D1 D0 10095-003 DB9 (MSB) AD5292-EP Enhanced Product Timing Diagrams t4 t2 t7 t1 SCLK t9 t3 t8 SYNC t5 t6 DIN X X C3 C2 D7 D6 D2 D1 D0 SDO t11 t10 t12 RDY 10095-004 tRESET RESET Figure 3. Write Timing Diagram, CPOL = 0, CPHA = 1 SCLK t9 SYNC DIN X X C3 D0 D0 X X C3 D1 D0 t14 X t11 RDY X t13 Figure 4. Read Timing Diagram, CPOL = 0, CPHA = 1 Rev. A | Page 6 of 16 C3 D1 D0 10095-005 SDO Enhanced Product AD5292-EP ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 4. Parameter VDD to GND VSS to GND VLOGIC to GND VDD to VSS VA, VB, VW to GND Digital Input and Output Voltage to GND EXT_CAP Voltage to GND IA, IB, IW Continuous Pulsed1 Frequency > 10 kHz Frequency ≤ 10 kHz Operating Temperature Range3 Maximum Junction Temperature (TJ max) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Package Power Dissipation Rating −0.3 V to +35 V +0.3 V to −25 V −0.3 V to +7 V 35 V VSS − 0.3 V, VDD + 0.3 V −0.3 V to VLOGIC + 0.3 V −0.3 V to +7 V ±3 mA Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE θJA is defined by JEDEC specification JESD-51 and the value is dependent on the test board and test environment. Table 5. Thermal Resistance ±3/d2 ±3/√d2 −55°C to +125°C 150°C −65°C to +150°C Package Type 14-Lead TSSOP 1 θJC 20 JEDEC 2S2P test board, still air (0 m/sec to 1 m/sec air flow). ESD CAUTION 260°C 20 sec to 40 sec (TJ max − TA)/θJA θJA 931 Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 2 Pulse duty factor. 3 Includes programming of OTP memory. 1 Rev. A | Page 7 of 16 Unit °C/W AD5292-EP Enhanced Product RESET 1 14 RDY VSS 2 13 SDO A 3 AD5292-EP 12 TOP VIEW (Not to Scale) 11 SYNC SCLK W 4 B 5 10 DIN VDD 6 9 GND EXT_CAP 7 8 VLOGIC 10095-006 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 Mnemonic RESET 2 VSS 3 4 5 6 7 8 A W B VDD EXT_CAP VLOGIC 9 10 GND DIN 11 SCLK 12 SYNC 13 SDO 14 RDY Description Hardware Reset Pin. Refreshes the RDAC register with the contents of the 20-TP memory register. Factory default loads midscale until the first 20-TP wiper memory location is programmed. RESET is activated at the logic high transition. Tie RESET to VLOGIC if not used. Negative Supply. Connect to 0 V for single-supply applications. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. Terminal A of RDAC. VSS ≤ VA ≤ VDD. Wiper Terminal of RDAC. VSS ≤ VW ≤ VDD. Terminal B of RDAC. VSS ≤ VB ≤ VDD. Positive Power Supply. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. External Capacitor. Connect a 1 μF capacitor to EXT_CAP. This capacitor must have a voltage rating of ≥7 V. Logic Power Supply; 2.7 V to 5.5 V. This pin should be decoupled with 0.1 μF ceramic capacitors and 10 μF capacitors. Ground Pin, Logic Ground Reference. Serial Data Input. The AD5292-EP has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. Serial Clock Input. Data is clocked into the shift register on the falling edge of the serial clock input. Data can be transferred at rates up to 50 MHz. Falling Edge Synchronization Signal. This is the frame synchronization signal for the input data. When SYNC goes low, it enables the shift register and data is transferred in on the falling edges of the following clocks. The selected register is updated on the rising edge of SYNC following the 16th clock cycle. If SYNC is taken high before the 16th clock cycle, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC. Serial Data Output. This open-drain output requires an external pull-up resistor. SDO can be used to clock data from the shift register in daisy-chain mode or in readback mode. Ready Pin. This active-high open-drain output identifies the completion of a write or read operation to or from the RDAC register or memory. Rev. A | Page 8 of 16 Enhanced Product AD5292-EP TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.6 –40°C +25°C +105°C 0.8 0.5 0.6 0.4 0.3 0.2 DNL (LSB) 0 –0.2 0.2 0.1 0 –0.4 –0.1 –0.6 –0.2 –0.8 128 256 384 512 640 768 896 1023 CODE (Decimal) –0.3 10095-106 0 +105°C +25°C –40°C –1.0 0 128 256 384 512 640 768 896 1023 896 1023 896 1023 CODE (Decimal) Figure 6. R-INL in R-Perf Mode vs. Code 10095-007 INL (LSB) 0.4 Figure 9. R-DNL in R-Perf Mode vs. Code 1.5 0.6 0.5 1.0 0.4 DNL (LSB) INL (LSB) 0.5 0 0.3 0.2 0.1 –0.5 0 –1.0 –0.1 128 256 384 512 640 768 896 1023 CODE (Decimal) 0 128 256 384 512 640 768 CODE (Decimal) Figure 7. INL in R-Perf Mode vs. Code Figure 10. DNL in R-Perf Mode vs. Code 1.0 0.15 0.8 0.10 0.6 0.05 DNL (LSB) 0.4 0.2 0 –0.05 0 –0.10 –0.2 –0.15 +105°C +25°C –40°C 0 128 256 384 512 640 768 CODE (Decimal) 896 1023 Figure 8. R-INL in Normal Mode vs. Code +105°C +25°C –40°C –0.6 –0.20 0 128 256 384 512 640 768 CODE (Decimal) Figure 11. R-DNL in Normal Mode vs. Code Rev. A | Page 9 of 16 10095-011 –0.4 10095-010 INL (LSB) +105°C –0.2 10095-014 0 +25°C –40°C –1.5 10095-015 +105°C +25°C –40°C AD5292-EP Enhanced Product 0.8 0.10 –40°C +25°C +105°C 0.6 –40°C +25°C +105°C 0.05 0.4 0 DNL (LSB) INL (LSB) 0.2 0 –0.05 –0.2 –0.10 –0.4 –0.15 0 128 256 384 512 640 768 896 –0.20 10095-018 –0.8 1023 CODE (Decimal) 0 512 640 768 896 1023 0.20 VDD = ±15V 0.18 SUPPLY CURRENT I LOGIC (mA) 350 SUPPLY CURRENT (nA) 384 Figure 15. DNL in Normal Mode vs. Code VDD/VSS = ±15V VLOGIC = +5V 400 256 CODE (Decimal) Figure 12. INL in Normal Mode vs. Code 450 128 10095-019 –0.6 ILOGIC 300 250 200 150 100 IDD 50 0 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 ISS 0 1.0 3.0 3.5 2.0 2.5 1.5 DIGITAL INPUT VOLTAGE (V) 4.0 5.0 1023 4.5 Figure 16. Supply Current ILOGIC vs. Digital Input Voltage Figure 13. Supply Current (IDD, ISS, ILOGIC) vs. Temperature 700 700 POTENTIOMETER MODE TEMPCO (ppm/°C) VDD = 30V VSS = 0V 600 500 400 300 200 100 VDD = 30V VSS = 0V 600 500 400 300 200 100 0 0 0 256 512 CODE (Decimal) 768 1023 10095-024 RHEOSTAT MODE TEMPCO (ppm/°C) 0.5 10095-031 TEMPERATURE (°C) 0 10095-023 10 20 30 40 50 60 70 80 90 100 10095-022 –50 –40 –30 –20 –10 0 Figure 14. Rheostat Mode Tempco ΔRWB/ΔT vs. Code 0 256 512 CODE (Decimal) 768 Figure 17. Potentiometer Mode Tempco ΔRWB/ΔT vs. Code Rev. A | Page 10 of 16 Enhanced Product AD5292-EP 0 0 –5 0x200 –10 0x100 –10 –20 0x080 –20 PSRR (dB) GAIN (dB) –15 0x040 –25 0x020 –30 –30 –40 0x010 –35 –50 0x008 –40 –60 0x004 –50 10 0x001 100 1k 10k 100k 1M FREQUENCY (Hz) –70 100 –15 100k 1M Figure 21. Power Supply Rejection Ratio vs. Frequency 0 VDD/VSS = ±15V CODE = HALF SCALE VIN = 1V rms NOISE BW = 22kHz VDD/VSS = ±15V, CODE = HALF SCALE fIN = 1kHz NOISE BW = 22kHz –20 –30 –40 –45 THD + N (dB) THD + N (dB) 10k FREQUENCY (Hz) Figure 18. 20 kΩ Gain vs. Frequency vs. Code 0 1k 10095-026 0x002 10095-025 –45 –60 –75 –60 –80 –100 –90 1k 10k 100k FREQUENCY (Hz) –140 0.001 10095-027 –120 100 1 10 Figure 22. THD + Noise vs. Amplitude 1,000,000 35 0pF 75pF 150pF 250pF 800,000 30 SUPPLY CURRENT I DD (mA) 900,000 700,000 600,000 500,000 400,000 300,000 200,000 25 20 15 10 5 0 8 16 32 64 CODE (Decimal) 128 256 512 Figure 20. Bandwidth vs. Code vs. Net Capacitance –5 –0.4 –0.2 0 0.2 0.4 0.6 TIME (ms) 0.8 1.0 Figure 23. IDD Waveform While Blowing/Reading Fuse Rev. A | Page 11 of 16 1.2 10095-034 0 100,000 10095-222 BANDWIDTH (Hz) 0.1 AMPLITUDE (V rms) Figure 19. THD + Noise vs. Frequency 0 0.01 10095-220 –120 –105 AD5292-EP Enhanced Product 40 35 VWB, CODE: FULL SCALE, NORMAL MODE VDD/VSS = 30V/0V VLOGIC = 5V VA = VDD VB = VSS 30 VDD/VSS = ±15V VA = VDD VB = VSS CODE = HALF CODE 32 24 25 VOLTAGE (μV) VOLTAGE (V) 16 VWB, CODE: FULL SCALE, R-PERF MODE 20 15 10 SYNC 8 0 –8 –16 –32 –40 –0.5 TIME (µs) 0 5 Figure 24. Large-Signal Settling Time from Code Zero Scale 15 20 25 TIME (µs) 30 6 VDD/VSS = 30V/0V VA = VDD VB = VSS 7 35 40 45 Figure 27. Digital Feedthrough 8 VDD/VSS = ±15V VLOGIC = +5V 5 6 4 5 VOLTAGE (V) 4 3 3 2 1 2 8.6 10095-036 8.0 Figure 28. VEXT_CAP Waveform While Reading Fuse Or Calibration 1.2 8 VDD/VSS = ±15V VLOGIC = +5V VA = VDD VB = VSS 0.8 7.4 TIME (ms) Figure 25. Theoretical Maximum Current vs. Code 1.0 6.8 6.2 5.6 5.0 4.4 3.8 3.2 2.6 –1 2.0 1023 1.4 768 0.8 512 CODE (Decimal) 256 0.2 0 10095-029 0 –0.4 0 1 –1.0 THEORETICAL IWB_MAX (mA) 10 10095-032 15 14 12 13 11 9 10 7 6 5 4 3 2 1 0 –1 –2 –5 –24 10095-033 0 VWB, CODE: HALF-SCALE, NORMAL MODE VWB, CODE: HALF-SCALE, R-PERF MODE 8 5 VDD/VSS = ±15V VLOGIC = +5V 6 VOLTAGE (V) 0.4 0.2 0 3 2 –0.2 –0.4 0 Rev. A | Page 12 of 16 10095-037 TIME (ms) Figure 29. VEXT_CAP Waveform While Writing Fuse Figure 26. Maximum Transition Glitch 17.2 16.0 14.8 13.6 12.4 11.2 10.0 –2 8.8 16 7.6 14 6.4 12 5.2 10 4.0 6 8 TIME (µs) 2.8 4 1.6 2 0.4 0 –0.8 –0.8 –2 –2.0 –0.6 10095-035 VOLTAGE (V) 0.6 Enhanced Product 300 AD5292-EP 80 VDD/VSS = ±15V VA = VDD VB = VSS TEMPERATURE = 25°C 70 250 NUMBER OF CODES 150 100 50 40 30 20 50 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (°C) 0 21 Figure 30. Code Range > 1% R-Tolerance Error vs. Temperature 26 30 VOLTAGE V DD/VSS 33 Figure 31. Code Range > 1% R-Tolerance Error vs. Voltage Rev. A | Page 13 of 16 10095-219 0 –40 –30 –20 –10 0 10 10095-056 NUMBER OF CODES 60 200 AD5292-EP Enhanced Product TEST CIRCUITS Figure 32 to Figure 37 define the test conditions used in the Specifications section. NC IW VA B A V+ ~ VMS W B 10095-041 Figure 32. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) PSS (%/%) = VMS Figure 35. Power Supply Sensitivity (PSS, PSRR) +15V A DUT A V+ = VDD 1LSB = V+/2N VIN W W DUT B VMS 2.5V Figure 33. Potentiometer Divider Nonlinearity Error (INL, DNL) +15V RWB= CODE = 0x00 RW = W + B A = NC 2 0.1V IWB –15V GND VDD DUT A VSS GND B ICM +15V –15V W GND – VSS TO VDD –15V GND 0.1V IWB RWB 10095-043 A VOUT Figure 36. Gain vs. Frequency NC DUT OP42 B OFFSET GND 10095-042 V+ ΔVMS% ΔVDD% 10095-047 NC = NO CONNECT V+ = VDD ± 10% ΔVMS PSRR (dB) = 20 log ΔV DD 10095-044 VDD NC GND NC = NO CONNECT +15V –15V Figure 37. Common-Mode Leakage Current Figure 34. Wiper Resistance Rev. A | Page 14 of 16 10095-048 DUT A W Enhanced Product AD5292-EP OUTLINE DIMENSIONS 5.10 5.00 4.90 14 8 4.50 4.40 4.30 6.40 BSC 1 7 PIN 1 0.65 BSC 1.20 MAX 0.15 0.05 COPLANARITY 0.10 0.30 0.19 0.20 0.09 SEATING PLANE 0.75 0.60 0.45 8° 0° 061908-A 1.05 1.00 0.80 COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 38. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters ORDERING GUIDE Model1 AD5292SRU-20-EP AD5292SRUZ-20-EP 1 RAB (kΩ) 20 20 Resolution 1024 1024 Memory 20-TP 20-TP Temperature Range −55°C to +125°C −55°C to +125°C Z = RoHS Compliant Part. Rev. A | Page 15 of 16 Package Description 14-Lead TSSOP 14-Lead TSSOP Package Option RU-14 RU-14 AD5292-EP Enhanced Product NOTES ©2011–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10095-0-4/18(A) Rev. A | Page 16 of 16