AD5533B

a FEATURES Infinite Sample-and-Hold Capability to 0.018% Accuracy Infinite Sample-and-Hold Total Unadjusted Error 2.5 m V High Integration: 32-Channel DAC in 12 mm 12 mm CSPBGA Per Channel Acquisition Time of 16 s Max Adjustable Voltage Output Range Output Impedance 0.5 Output Voltage Span 10 V Readback Capability DSP/Microcontroller Compatible Serial Interface Parallel Interface Temperature Range –40 C to +85 C APPLICATIONS Optical Networks Automatic Test Equipment Level Setting Instrumentation Industrial Control Systems Data Acquisition Low Cost I/O 32-Channel Precision Infinite Sample-and-Hold AD5533B* GENERAL DESCRIPTION The AD5533B combines a 32-channel voltage translation function with an infinite output hold capability. An analog input voltage on the common input pin, VIN, is sampled and its digital representation transferred to a chosen DAC register. VOUT for this DAC is then updated to reflect the new contents of the DAC register. Channel selection is accomplished via the parallel address inputs A0–A4 or via the serial input port. The output voltage range is determined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier. It is restricted to a range from VSS + 2 V to VDD – 2 V because of the headroom of the output amplifier. The device is operated with AVCC = +5 V ± 5%, DVCC = +2.7 V to +5.25 V, VSS = –4.75 V to –16.5 V, and VDD = +8 V to +16.5 V and requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN. PRODUCT HIGHLIGHTS 1. Precision infinite droopless sample-and-hold capability. 2. The AD5533B is available in a 74-lead CSPBGA with a body size of 12 mm 12 mm. 3. In infinite sample-and-hold mode, a total unadjusted error of ± 2.5 mV is achieved by laser-trimming on-chip resistors. FUNCTIONAL BLOCK DIAGRAM DVCC AVCC REF IN REF OUT OFFS IN VDD VSS VOUT 0 VIN TRACK / RESET BUSY DAC GND AGND DAC DGND INTERFACE CONTROL LOGIC VOUT 31 ADC DAC AD5533B DAC OFFS OUT SER / PAR ADDRESS INPUT REGISTER WR SCLK DIN DOUT SYNC / CS A4 –A0 CAL OFFSET SEL *Protected by U.S. Patent No. 5,969,657; other patents pending. R EV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 2.7 V to 5.25 V; REF_IN AD5533B–SPECIFICATIONS DV All=specificationsV;TAGNDo = DGND = DAC_GND = 0noted.) = 3 V; OFFS_IN = 0 V; Output Range from V + 2 V to V – 2 V. All outputs unloaded. t T , unless otherwise CC SS DD MIN MAX (VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V; Parameter1 ANALOG CHANNEL VIN to VOUT Nonlinearity Total Unadjusted Error (TUE) B Version2 ± 0.006 ± 0.018 3.51/3.52/3.53 ±1 ± 10 Unit % typ % max mV typ mV max Conditions/Comments Input Range 100 mV to 2.96 V After Gain and Offset Adjustment See TPC 6. ± 2.5 ± 12 Gain Offset Error ANALOG INPUT (VIN) Input Voltage Range Input Lower Dead Band Input Upper Dead Band Input Current Input Capacitance3 ANALOG INPUT (OFFS_IN) Input Voltage Range Input Current VOLTAGE REFERENCE REF_IN Nominal Input Voltage Input Voltage Range3 Input Current REF_OUT Output Voltage Output Impedance3 Reference Temperature Coefficient3 ANALOG OUTPUTS (VOUT 0–31) Output Temperature Coefficient3, 4 DC Output Impedance Output Range Resistive Load3, 5 Capacitive Load3, 5 Short-Circuit Current3 DC Power Supply Rejection Ratio3 DC Crosstalk3 ANALOG OUTPUT (OFFS_OUT) Output Temperature Coefficient3, 4 DC Output Impedance3 Output Range Output Current Capacitive Load DIGITAL INPUTS3 Input Current Input Low Voltage Input High Voltage Input Hysteresis (SCLK and CS Only) Input Capacitance min/typ/max mV typ mV max V mV max mV max µA max pF typ V min/max µA max See TPC 2. 0 to 3 70 40 1 20 0/4 1 Nominal Input Range 50 mV typ. Referred to VIN. See Figure 5. 12 mV typ. Referred to VIN. See Figure 5. 100 nA typ. VIN acquired on one channel. Output Range Restricted from VSS + 2 V to VDD – 2 V 100 nA typ 3.0 2.85/3.15 1 3 280 60 10 0.5 VSS + 2/VDD – 2 5 100 7 –70 –70 250 10 1.3 50 to REF_IN – 12 10 100 ± 10 0.8 0.4 2.4 2.0 200 10 V V min/max µA max V typ kΩ typ VOUT = (Gain VDAC) – (Gain – 1) VOFFS_IN = 50 mV. Analog Input Figure 6. Analog Input Circuit Large source impedances will significantly affect the performance of the ADC. This may necessitate the use of an input buffer amplifier. Output Buffer Stage—Gain and Offset The function of the output buffer stage is to translate the 50 mV–3 V typical output of the DAC to a wider range. This is done by gaining up the DAC output by 3.52 and offsetting the voltage by the voltage on OFFS_IN pin. VOUT = 3.52 × VDAC − 2.52 × VOFFS_IN VDAC is the output of the DAC. VOFFS_IN is the voltage at the OFFS_IN pin. Table I shows how the output range on VOUT relates to the offset voltage supplied by the user. Table I. Sample Output Voltage Ranges VOFFS_IN (V) 0 1 2.130 VDAC (V) 0.05 to 3 0.05 to 3 0.05 to 3 VOUT (V) 0.176 to 10.56 –2.34 to +8.04 –5.192 to +5.192 VOUT is limited only by the headroom of the output amplifiers. VOUT must be within maximum ratings. Offset Voltage Channel The equivalent analog input circuit is shown in Figure 6. The capacitor C1 is typically 20 pF and can be attributed to pin capacitance and 32 off-channels. When a channel is selected, an extra 7.5 pF (typ) is switched in. This capacitor C2 is charged to the previously acquired voltage on that particular channel so it must charge/discharge to the new level. It is essential that the external source can charge/discharge this additional capacitance within 1 µs–2 µs of channel selection so that VIN can be acquired accurately. For this reason, a low impedance source is recommended. The offset voltage can be externally supplied by the user at OFFS_IN or it can be supplied by an additional offset voltage channel on the device itself. The required offset voltage is set up on VIN and acquired by the offset DAC. This offset channel’s DAC output is directly connected to OFFS_OUT. By connecting OFFS_OUT to OFFS_IN, this offset voltage can be used as the offset voltage for the 32 output amplifiers. It is important to choose the offset so that VOUT is within maximum ratings. PIN DRIVER VIN CONTROLLER CONTROLLER DAC BUSY TRACK OUTPUT STAGE VOUT1 DEVICE UNDER TEST ACQUISITION ACQUISITION CIRCUIT CIRCUIT AD5533B THRESHOLD VOLTAGE ONLY ONE CHANNEL SHOWN FOR SIMPLICITY Figure 7. Typical ATE Circuit Using TRACK Input REV. A –11– AD5533B Reset Function 1. ISHA Mode The reset function on the AD5533B can be used to reset all nodes on this device to their power-on-reset condition. This is implemented by applying a low-going pulse of between 90 ns and 200 ns to the TRACK/RESET pin on the device. If the applied pulse is less than 90 ns, it is assumed to be a glitch and no operation takes place. If the applied pulse is wider than 200 ns, this pin adopts its track function on the selected channel, VIN is switched to the output buffer, and an acquisition on the channel will not occur until a rising edge of TRACK. TRACK Function In this standard mode, a channel is addressed and that channel acquires the voltage on VIN. This mode requires a 10-bit write (see Figure 3) to address the relevant channel (VOUT0–VOUT31, offset channel, or all channels). MSB is written first. 2. Acquire and Readback Mode Normally in ISHA mode of operation, TRACK is held high and the channel begins to acquire when it is addressed. However, if TRACK is low when the channel is addressed, VIN is switched to the output buffer and an acquisition on the channel will not occur until a rising edge of TRACK. At this stage the BUSY pin will go low until the acquisition is complete, at which point the DAC assumes control of the voltage to the output buffer and VIN is free to change again without affecting this output value. This is useful in an application where the user wants to ramp up VIN until VOUT reaches a particular level (Figure 7). VIN does not need to be acquired continuously while it is ramping up. TRACK can be kept low and only when VOUT has reached its desired voltage is TRACK brought high. At this stage, the acquisition of VIN begins. In the example shown, a desired voltage is required on the output of the pin driver. This voltage is represented by one input to a comparator. The microcontroller/microprocessor ramps up the input voltage on VIN through a DAC. TRACK is kept low while the voltage on VIN ramps up so that VIN is not continually acquired. When the desired voltage is reached on the output of the pin driver, the comparator output switches. The µC/µP then knows what code is required to be input in order to obtain the desired voltage at the DUT. The TRACK input is now brought high and the part begins to acquire VIN. BUSY goes low until VIN has been acquired. When BUSY goes high, the output buffer is switched from VIN to the output of the DAC. MODES OF OPERATION This mode allows the user to acquire VIN and read back the data in a particular DAC register. The relevant channel is addressed (10-bit write, MSB first) and VIN is acquired in 16 µs (max). Following the acquisition, after the next falling edge of SYNC, the data in the relevant DAC register is clocked out onto the DOUT line in a 14-bit serial format (see Figure 4). During readback, DIN is ignored. The full acquisition time must elapse before the DAC register data can be clocked out. 3. Readback Mode Again, this is a readback mode but no acquisition is performed. The relevant channel is addressed (10-bit write, MSB first) and on the next falling edge of SYNC, the data in the relevant DAC register is clocked out onto the DOUT line in a 14-bit serial format (see Figure 4). The user must allow 400 ns (min) between the last SCLK falling edge in the 10-bit write and the falling edge of SYNC in the 14-bit readback. The serial write and read words can be seen in Figure 8. This feature allows the user to read back the DAC register code of any of the channels. Readback is useful if the system has been calibrated and the user wants to know what code in the DAC corresponds to a desired voltage on VOUT. INTERFACES Serial Interface The SER/PAR pin is tied high to enable the serial interface and to disable the parallel interface. The serial interface is controlled by four pins as follows: SYNC, DIN, SCLK Standard 3-wire interface pins. The SYNC pin is shared with the CS function of the parallel interface. DOUT The AD5533B can be used in three different modes. These modes are set by two mode bits, the first two bits in the serial word. The 01 option (DAC Mode) is not available for the AD5533B. For information on this mode, refer to the AD5532B data sheet. If you attempt to set up DAC Mode, the AD5533B will enter a test mode and a 24-clock write will be necessary to clear this. Table II. Modes of Operation Data out pin for reading back the contents of the DAC registers. The data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. Mode Bits There are four different modes of operation as described above. Cal Bit Mode Bit 1 0 0 1 1 Mode Bit 2 0 1 0 1 Operating Mode ISHA Mode DAC Mode (Not Available) Acquire and Readback Readback When this is high, all 32 channels acquire VIN simultaneously. The acquisition time is then 45 µs (typ) and accuracy may be reduced. This bit is set low for normal operation. Offset_Sel Bit If this bit is set high, the offset channel is selected and bits A4–A0 are ignored. Test Bit This must be set low for correct operation of the part. A4–A0 Bit Used to address any one of the 32 channels (A4 = MSB of address, A0 = LSB). –12– REV. A AD5533B MSB 0 MODE BIT 1 0 MODE BIT 2 CAL OFFSET SEL 0 TEST BIT LSB A4–A0 MODE BITS a. 10-Bit Input Serial Write Word (ISHA Mode) MSB 1 0 CAL OFFSET SEL 0 TEST BIT MODE BITS 10-BIT SERIAL WORD WRITTEN TO PART 14-BIT DATA READ FROM PART AFTER NEXT FALLING EDGE OF SYNC (DB13 = MSB OF DAC WORD) LSB A4–A0 MSB DB1 3 –DB0 LSB b. Input Serial Interface (Acquire and Readback Mode) MSB 1 1 0 OFFSET SEL 0 TEST BIT MODE BITS 10-BIT SERIAL WORD WRITTEN TO PART 14-BIT DATA READ FROM PART AFTER NEXT FALLING EDGE OF SYNC (DB13 = MSB OF DAC WORD) LSB A4–A0 MSB DB1 3 –DB0 LSB c. Input Serial Interface (Readback Mode) Figure 8. Serial Interface Formats DB13–DB0 Bit Parallel Interface These are used in both readback modes to read a 14-bit word from the addressed DAC register. The serial interface is designed to allow easy interfacing to most microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI™, SPI™, DSP56000, TMS320, and ADSP-21xx, without the need for any glue logic. When interfacing to the 8051, the SCLK must be inverted. The Microprocessor/Microcontroller Interface section explains how to interface to some popular DSPs and microcontrollers. Figures 3 and 4 show the timing diagram for a serial read and write to the AD5533B. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling edge of SYNC resets a counter that counts the number of serial clocks to ensure the correct number of bits are shifted in and out of the serial shift registers. Any further edges on SYNC are ignored until the correct number of bits are shifted in or out. Once the correct number of bits have been shifted in or out, the SCLK is ignored. In order for another serial transfer to take place, the counter must be reset by the falling edge of SYNC. In readback, the first rising SCLK edge after the falling edge of SYNC causes DOUT to leave its high impedance state and data is clocked out onto the DOUT line and also on subsequent SCLK rising edges. The DOUT pin goes back into a high impedance state on the falling edge of the 14th SCLK. Data on the DIN line is latched in on the first SCLK falling edge after the falling edge of the SYNC signal and on subsequent SCLK falling edges. The serial interface will not shift data in or out until it receives the falling edge of the SYNC signal. *SPI and QSPI are trademarks of Motorola, Inc. The SER/PAR bit is tied low to enable the parallel interface and disable the serial interface. The parallel interface is controlled by nine pins as follows: CS Active low package select pin. This pin is shared with the SYNC function for the serial interface. WR Active low write pin. The values on the address pins are latched on a rising edge of WR. A4–A0 Five address pins (A4 = MSB of address, A0 = LSB). These are used to address the relevant channel (out of a possible 32). Offset_Sel Offset select pin. This has the same function as the Offset_Sel bit in the serial interface. When it is high, the offset channel is addressed and the address on A4–A0 is ignored. Cal Same functionality as the Cal bit in the serial interface. When this pin is high, all 32 channels acquire VIN simultaneously. MICROPROCESSOR INTERFACING AD5533B to ADSP-21xx Interface The ADSP-21xx family of DSPs is easily interfaced to the AD5533B without the need for extra logic. A data transfer is initiated by writing a word to the TX register after the SPORT has been enabled. In a write sequence, data is clocked out on each rising edge of the DSP’s serial clock and clocked into the AD5533B on the falling edge of its SCLK. In REV. A –13– AD5533B readback, 16 bits of data are clocked out of the AD5533B on each rising edge of SCLK and clocked into the DSP on the rising edge of SCLK. DIN is ignored. The valid 14 bits of data will be centered in the 16-bit RX register when using this configuration. The SPORT control register should be set up as follows: TFSW INVRFS DTYPE ISCLK TFSR IRFS ITFS SLEN SLEN = RFSW = 1, Alternate Framing = INVTFS = 1, Active Low Frame Signal = 00, Right-Justify Data = 1, Internal Serial Clock = RFSR = 1, Frame Every Word = 0, External Framing Signal = 1, Internal Framing Signal = 1001, 10-Bit Data-Words (ISHA Mode Write) = 1111, 16-Bit Data-Words (Readback Mode) AD5533B to PIC16C6x/7x The PIC16C6x synchronous serial port (SSP) is configured as an SPI Master with the clock polarity bit = 0. This is done by writing to the Synchronous Serial Port Control Register (SSPCON). See PIC16/17 Microcontroller User Manual. In this example I/O port RA1 is being used to pulse SYNC and enable the serial port of the AD5533B. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive read/write operations are needed for a 10-bit write and a 14-bit readback. Figure 11 shows the connection diagram. AD5533B* SCLK DOUT DIN SYNC PIC16C6x/7x* SCK/RC3 SDO/RC5 SDI/RC4 RA1 Figure 9 shows the connection diagram. AD5533B* DOUT SYNC DR TFS RFS DIN SCLK *ADDITIONAL PINS OMITTED FOR CLARITY DT SCLK ADSP-2101/ ADSP-2103* *ADDITIONAL PINS OMITTED FOR CLARITY Figure 11. AD5533B to PIC16C6x/7x Interface AD5533B to 8051 Figure 9. AD5533B to ADSP-2101/ADSP-2103 Interface AD5533B to MC68HC11 The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), clock polarity bit (CPOL) = 0 and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)— see 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5533B, the MOSI output drives the serial data line (DIN) of the AD5533B, and the MISO input is driven from DOUT. The SYNC signal is derived from a port line (PC7). When data is being transmitted to the AD5533B, the SYNC line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to transmit 10 data bits in ISHA mode it is important to left-justify the data in the SPDR register. PC7 must be pulled low to start a transfer. It is taken high and pulled low again before any further read/write cycles can take place. A connection diagram is shown in Figure 10. AD5533B* DOUT SYNC SCLK DIN *ADDITIONAL PINS OMITTED FOR CLARITY MISO PC7 SCK MOSI The AD5533B requires a clock synchronized to the serial data. The 8051 serial interface must therefore be operated in Mode 0. In this mode, serial data enters and exits through RxD and a shift clock is output on TxD. Figure 12 shows how the 8051 is connected to the AD5533B. Because the AD5533B shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD5533B requires its data with the MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account. AD5533B* SCLK DOUT DIN SYNC *ADDITIONAL PINS OMITTED FOR CLARITY P1.1 TXD RXD 8051* Figure 12. AD5533B to 8051 Interface APPLICATION CIRCUITS AD5533B in a Typical ATE System MC68HC11* The AD5533B infinite sample-and-hold is ideally suited for use in automatic test equipment. Several ISHAs are required to control pin drivers, comparators, active loads, and signal timing. Traditionally, sample-and-hold devices with droop were used in these applications. These required refreshing to prevent the voltage from drifting. The AD5533B has several advantages: no refreshing is required, there is no droop, pedestal error is eliminated, and there is no need for extra filtering to remove glitches. Overall, a higher level of integration is achieved in a smaller area. See Figure 13. Figure 10. AD5533B to MC68HC11 Interface –14– REV. A AD5533B PARAMETRIC MEASUREMENT SYSTEM BUS UNIT ISHA ISHA ISHA ACTIVE LOAD POWER SUPPLY DECOUPLING STORED DATA AND INHIBIT PATTERN FORMATTER DRIVER ISHA ISHA PERIOD GENERATION AND DELAY TIMING DUT ISHA COMPARE REGISTER ISHA COMPARATOR ISHAs SYSTEM BUS In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5533B is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5533B is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (VSS, VDD, AVCC) it is recommended to tie those pins together. The AD5533B should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. The power supply lines of the AD5533B should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). It is essential to minimize noise on VIN and REFIN lines. Note it is essential to minimize noise on VIN and REFIN lines. Particularly for optimum ISHA performance, the VIN line must be kept noise-free. Depending on the noise performance of the board, a noise filtering capacitor may be required on the VIN line. If this capacitor is necessary, then for optimum throughput it may be necessary to buffer the source that is driving VIN. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. As is the case for all thin packages, care must be taken to avoid flexing the CSPBGA package and to avoid a point load on the surface of this package during the assembly process. Figure 13. AD5533B in an ATE System Typical Application Circuit The AD5533B can be used to set up voltage levels on 32 channels as shown in the circuit below. An AD780 provides the 3 V reference for the AD5533B, and for the AD5541 16-bit DAC. A simple 3-wire serial interface is used to write to the AD5541. Because the AD5541 has an output resistance of 6.25 kΩ (typ), the time taken to charge/ discharge the capacitance at the VIN pin is significant. Thus an AD820 is used to buffer the DAC output. Note that it is important to minimize noise on VIN and REFIN when laying out this circuit. AVCC AVCC DVCC VSS VDD CS DIN SCLK AD5541* AD820 VIN AD5533B* REF OFFS_IN OFFS_OUT REFIN VOUT 0–31 AD780* VOUT SCLK DIN *ADDITIONAL PINS OMITTED FOR CLARITY SYNC Figure 14. Typical Application Circuit REV. A –15– AD5533B OUTLINE DIMENSIONS 74-Lead Chip Scale Ball Grid Array [CSPBGA] (BC-74) Dimensions shown in millimeters A1 CORNER INDEX AREA 11 10 9 8 7 6 5 4 3 2 1 A1 TOP VIEW 1.00 BSC BOT TOM VIEW A B C D E F G H J K L 10.00 BSC SQ 1.00 BSC 1.70 MAX DETAIL A DETAIL A 0.30 MIN 0.20 MAX COPLANARITY 0.70 SEATING 0.60 PLANE 0.50 BALL DIAMETER COMPLIANT TO JEDEC STANDARDS MO-192ABD-1 Revision History Location 9/02—Data Sheet changed from REV. 0 to REV. A. Page Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global Replaced FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Additions to SERIAL INTERFACE Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Replaced Figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Additions to POWER SUPPLY DECOUPLING section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Updated BC-74 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 – 16– REV. A PRINTED IN U.S.A. C02715–0–9/02(A) 12.00 BSC SQ