2.7 V to 5.5 V, Serial-Input,
Voltage-Output, 12-/16-Bit DAC
AD5512A/AD5542A
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
12-/16-bit resolution
1 LSB INL
11.8 nV/√Hz noise spectral density
1 µs settling time
1.1 nV-sec glitch energy
0.05 ppm/°C temperature drift
5 kV HBM ESD classification
VDD
REFF
INV
RINV
VOUT
16-BIT DAC
REFS
AGNDF
VLOGIC
0.375 mW power consumption at 3 V
16-BIT DAC LATCH
AGNDS
CS
2.7 V to 5.5 V single-supply operation
Hardware CLR and LDAC functions
50 MHz SPI-/QSPI-/MICROWIRE-/DSP-compatible interface
Power-on reset clears DAC output to midscale
Available in 3 mm × 3 mm, 10-/16-lead LFCSP and
16-lead TSSOP
CONTROL
LOGIC
LDAC
SCLK
SERIAL INPUT REGISTER
DIN
CLR
09199-001
AD5512A/
AD5542A
DGND
Figure 1. 16-Lead TSSOP and 16-Lead LFCSP
APPLICATIONS
GND
10
Automatic test equipment
Precision source-measure instruments
Data acquisition systems
Medical and aerospace instrumentation
Communication equipment
AD5542A-1
8
RFB
7
INV
6
VOUT
RFB
RINV
16-BIT DAC
16-BIT DAC LATCH
CS 2
SCLK 3
GENERAL DESCRIPTION
CONTROL
LOGIC
DIN 4
The AD5512A/AD5542A are single, 12-/16-bit, serial input,
unbuffered voltage output digital-to-analog converters (DAC)
that operate from a single 2.7 V to 5.5 V supply. The DAC
output range extends from 0 V to VREF and is guaranteed
monotonic, providing 1 LSB INL accuracy at 16 bits without
adjustment over the full specified temperature range of −40°C
to +85°C (AD5542A) or −40°C to +125°C (AD5512A).
Offering unbuffered outputs, the AD5512A/AD5542A achieve
a 1 μs settling time with low offset errors ideal for high speed
open loop control.
The AD5512A/AD5542A incorporate a bipolar mode of
operation that generates a ±VREF output swing. The
AD5512A/AD5542A also include Kelvin sense connections for
the reference and analog ground pins to reduce layout sensitivity.
The AD5512A/AD5542A are available in a 16-lead LFCSP with
the AD5542A also available in a 10-lead LFCSP and a 16-lead
TSSOP. The AD5512A/AD5542A use a versatile 3-wire interface
that is compatible with 50 MHz SPI, QSPI™, MICROWIRE™, and
DSP interface standards.
SERIAL INPUT REGISTER
9
VDD
09199-002
REF
1
CLR 5
Rev. C
RFB
RFB
Figure 2. 10-Lead LFCSP
Table 1. Related Devices
Part No.
AD5040/AD5060
AD5541/AD5542
AD5781/AD5791
AD5570
AD5024/AD5064
AD5764
Description
2.7 V to 5.5 V 14-/16-bit buffed output DACs
2.7 V to 5.5 V 16-bit voltage output DACs
18-/20-bit voltage output DACs
16-bit ±12 V/±15 V bipolar output DAC
4.5 V to 5.5 V, 12-/16-bit quad channel DAC
16-bit, bipolar, voltage output DAC
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
16-bit performance without adjustment.
2.7 V to 5.5 V single supply operation.
Low 11.8 nV/√Hz noise spectral density.
Low 0.05 ppm/°C temperature drift.
3 mm × 3 mm LFCSP and TSSOP packaging.
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Technical Support
www.analog.com
AD5512A/AD5542A
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Unipolar Output Operation ...................................................... 15
Applications ....................................................................................... 1
Bipolar Output Operation ......................................................... 16
General Description ......................................................................... 1
Output Amplifier Selection....................................................... 17
Functional Block Diagram .............................................................. 1
Force Sense Amplifier Selection ............................................... 17
Product Highlights ........................................................................... 1
Reference and Ground ............................................................... 17
Revision History ............................................................................... 2
Power-On Reset .......................................................................... 17
Specifications..................................................................................... 3
Power Supply and Reference Bypassing .................................. 17
AD5512A ....................................................................................... 3
Applications Information .............................................................. 18
AD5542A ....................................................................................... 4
Microprocessor Interfacing ....................................................... 18
AC Characteristics........................................................................ 5
AD5512A/AD5542A to ADSP-BF531 Interface .................... 18
Timing Characteristics ................................................................ 6
AD5512A/AD5542A to SPORT Interface .............................. 18
Absolute Maximum Ratings............................................................ 7
AD5512A/AD5542A to 68HC11/68L11 Interface ................... 18
ESD Caution .................................................................................. 7
AD5512A/AD5542A to MICROWIRE Interface .................. 18
Pin Configuration and Function Descriptions ............................. 8
Layout Guidelines....................................................................... 19
Typical Performance Characteristics ........................................... 10
Galvanically Isolated Interface ................................................. 19
Terminology .................................................................................... 14
Decoding Multiple DACs .......................................................... 19
Theory of Operation ...................................................................... 15
Outline Dimensions ....................................................................... 20
Digital-to-Analog Section ......................................................... 15
Ordering Guide .......................................................................... 21
Serial Interface ............................................................................ 15
REVISION HISTORY
2/2017—Rev. B to Rev. C
Changes to Figure 4 and Table 7 ..................................................... 8
4/2015—Rev. A to Rev. B
Changes to Power-On Reset Section............................................ 17
Deleted AD5512A/AD5542A to ADSP-2101 Interface Section .. 18
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
5/2011—Rev. 0 to Rev. A
Changes to Table 3, Power Dissipation Value and Endnote 1 .... 4
Changes to Table 5 ............................................................................ 6
Changes to Ordering Guide .......................................................... 21
10/2010—Revision 0: Initial Version
Rev. C | Page 2 of 21
Data Sheet
AD5512A/AD5542A
SPECIFICATIONS
AD5512A
VDD = 2.7 V to 5.5 V, VLOGIC = 2.7 V to 5.5 V, VREF = 2.5 V, AGND = DGND = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter 1
STATIC PERFORMANCE
Resolution
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Gain Error
Gain Error Temperature Coefficient
Unipolar Zero-Code Error
Unipolar Zero-Code Temperature Coefficient
Bipolar Resistor Matching
Bipolar Zero Offset Error
Bipolar Zero Temperature Coefficient
Bipolar Zero-Code Offset Error
Bipolar Gain Error
Bipolar Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Voltage Range
Min
1
2
3
±0.5
±0.5
+0.5
±0.1
0.03
±0.05
1
±0.02
±0.07
±0.2
±0.02
±0.07
±0.1
±1.0
±1.0
±2
0
−VREF
±0.5
±0.08
±2
±0.5
±2
VREF − 1 LSB
+VREF − 1 LSB
Unit
Bits
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
Ω/Ω
%
LSB
ppm/°C
LSB
LSB
ppm/°C
Test Condition
Guaranteed monotonic
RFB/RINV, typically RFB = RINV = 28 kΩ
Ratio error
11.8
V
V
kΩ
LSB
nV/√Hz
0.134
μV p-p
Unipolar operation
Bipolar operation
Tolerance typically 20%
ΔVDD ± 10%
DAC code = 0x840 (AD5512A) or
0x8400 (AD5542A), frequency = 1 kHz,
unipolar mode
0.1 Hz to 10 Hz, unipolar mode
V
kΩ
kΩ
pF
pF
Unipolar operation
Bipolar operation
Code 0x0000
Code 0x3FFF
6.25
±1.0
2.0
9
7.5
Reference Input Capacitance
LOGIC INPUTS
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Input Capacitance2
Hysteresis Voltage2
POWER REQUIREMENTS
VDD
IDD
VLOGIC
ILOGIC
Power Dissipation
Max
12
DAC Output Impedance
Power Supply Rejection Ratio
Output Noise Spectral Density
Output Noise
DAC REFERENCE INPUT 2
Reference Input Range
Reference Input Resistance 3
Typ
VDD
26
26
±1
0.8
2.4
10
0.15
2.7
125
1.8
15
1.5
5.5
150
5.5
24
6.05
Temperatures are as follows: A version −40°C to +125°C.
Guaranteed by design, not subject to production test.
Reference input resistance is code-dependent, minimum at 0x855.
Rev. C | Page 3 of 21
μA
V
V
pF
V
V
µA
V
µA
mW
VDD = 2.7 V to 5.5 V
VDD = 2.7 V to 5.5 V
All digital inputs at 0 V, VLOGIC, or VDD
VIH = VLOGIC or VDD and VIL = GND
All digital inputs at 0 V, VLOGIC, or VDD
AD5512A/AD5542A
Data Sheet
AD5542A
VDD = 2.7 V to 5.5 V, VLOGIC = 2.7 V to 5.5 V, VREF = 2.5 V, AGND = DGND = 0 V, −40°C < TA < +85°C, unless otherwise noted.
Table 3.
Parameter 1
STATIC PERFORMANCE
Resolution
Relative Accuracy (INL)
Min
±1.0
±2.0
±1.0
±2
±3
Gain Error Temperature Coefficient
Unipolar Zero-Code Error
±0.1
0.3
Unipolar Zero-Code Temperature Coefficient
Bipolar Resistor Matching
Bipolar Zero Offset Error
±0.05
1.000
±0.0015
±1
Bipolar Zero Temperature Coefficient
Bipolar Zero-Code Offset Error
±0.2
±1
Bipolar Gain Error
±1
±0.7
±1.5
±0.0076
±5
±6
±5
±6
±5
±6
±0.1
0
−VREF
VREF − 1 LSB
+VREF − 1 LSB
Unit
Bits
LSB
Test Condition
B grade
A grade
Guaranteed monotonic
TA = 25°C
LSB
LSB
LSB
ppm/°C
LSB
LSB
ppm/°C
Ω/Ω
%
LSB
LSB
ppm/°C
LSB
LSB
LSB
LSB
ppm/°C
RFB/RINV, typically RFB = RINV = 28 kΩ
Ratio error
TA = 25°C
V
V
kΩ
LSB
Unipolar operation
Bipolar operation
Tolerance typically 20%
ΔVDD ± 10%
TA = 25°C
TA = 25°C
TA = 25°C
DAC Output Impedance
Power Supply Rejection Ratio
6.25
Output Noise Spectral Density
11.8
nV/√Hz
Output Noise
0.134
μV p-p
DAC code = 0x840 (AD5512A) or
0x8400 (AD5542A), frequency = 1 kHz,
unipolar mode
0.1 Hz to 10 Hz
V
kΩ
kΩ
pF
pF
Unipolar operation
Bipolar operation
Code 0x0000
Code 0xFFFF
±1.0
2.0
9
7.5
Reference Input Capacitance
LOGIC INPUTS
Input Current
Input Low Voltage, VINL
Input High Voltage, VINH
Input Capacitance2
Hysteresis Voltage2
POWER REQUIREMENTS
VDD
IDD
VLOGIC
ILOGIC
Power Dissipation
3
±0.5
16
±0.5
+0.5
DAC REFERENCE INPUT 2
Reference Input Range
Reference Input Resistance 3
2
Max
Differential Nonlinearity (DNL)
Gain Error
Bipolar Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
Output Voltage Range
1
Typ
VDD
26
26
±1
0.8
2.4
10
0.15
2.7
125
1.8
15
0.625
5.5
150
5.5
24
0.825
For 2.7 V ≤ VLOGIC ≤ 5.5 V, temperatures are as follows: A, B versions −40°C to +85°C.
Guaranteed by design, not subject to production test.
Reference input resistance is code-dependent, minimum at 0x8555.
Rev. C | Page 4 of 21
μA
V
V
pF
V
V
µA
V
µA
mW
VDD = 2.7 V to 5.5 V
VDD = 2.7 V to 5.5 V
All digital inputs at 0 V, VLOGIC, or VDD
VIH = VLOGIC or VDD and VIL = GND
All digital inputs at 0 V, VLOGIC, or VDD
Data Sheet
AD5512A/AD5542A
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VLOGIC = 2.7 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 4.
Parameter
Output Voltage Settling Time
Slew Rate
Digital-to-Analog Glitch Impulse
Reference −3 dB Bandwidth
Reference Feedthrough
Digital Feedthrough
Signal-to-Noise Ratio
Spurious Free Dynamic Range
Total Harmonic Distortion
Min
Typ
1
17
1.1
2.2
1
0.2
92
80
74
Max
Unit
μs
V/µs
nV-sec
MHz
mV p-p
nV-sec
dB
dB
dB
Test Condition
To 1/2 LSB of FS, CL = 10 pF
CL = 10 pF, measured from 0% to 63%
1 LSB change around major carry
All 1s loaded
All 0s loaded, VREF = 1 V p-p at 100 kHz
Digitally generated sine wave at 1 kHz
DAC code = 0x3FFF (AD5512A) or 0xFFFF (AD5542A), frequency 10 kHz,
VREF = 2.5 V ± 1 V p-p
Rev. C | Page 5 of 21
AD5512A/AD5542A
Data Sheet
TIMING CHARACTERISTICS
VDD = 5 V, 2.5 V ≤ VREF ≤ VDD, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V, unless otherwise noted.
Table 5.
Parameter 1, 2
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t9
t10
t11
t12
t13
Limit 1.8 ≤ VLOGIC ≤ 2.7 V 3
14
70
35
35
5
5
5
10
35
5
5
20
10
15
15
Limit 2.7 V ≤ VLOGIC ≤ 5.5 V 4
50
20
10
10
5
5
5
5
10
4
5
20
10
15
15
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time (VINH = 90% of VDD, VINL = 10% of VDD)
Data hold time (VINH = 3 V, VINL = 0 V)
LDAC pulsewidth
CS high to LDAC low setup
CS high time between active periods
CLR pulsewidth
Guaranteed by design and characterization, not production tested.
All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
3
−40°C < TA < +105°C.
4
−40°C < TA < +125°C.
1
2
t1
SCLK
t2
t6
t3
CS
t5
t7
t4
t12
t8
t9
DIN
DB15 1
DB112
t11
t10
LDAC
t13
09199-003
CLR
NOTES
1. FOR AD5542A = DB15.
2. FOR AD5512A = DB11.
Figure 3. Timing Diagram
Rev. C | Page 6 of 21
Data Sheet
AD5512A/AD5542A
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to AGND
Digital Input Voltage to DGND
VOUT to AGND
AGNDF, AGNDS to DGND
Input Current to Any Pin Except Supplies
Operating Temperature Range
AD5512A Industrial (A Version)
AD5542A Industrial (A, B Versions)
Storage Temperature Range
Maximum Junction Temperature (TJ max)
Package Power Dissipation
Thermal Impedance, θJA
TSSOP (RU-16)
LFCSP (CP-16-22)
LFCSP (CP-10-9)
Lead Temperature, Soldering
Peak Temperature1
ESD2
1
2
Rating
−0.3 V to +6 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +0.3 V
±10 mA
−40°C to +125°C
−40°C to +85°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
113°C/W
73°C/W
74°C/W
260°C
5 kV
As per JEDEC Standard 20.
HBM classification.
Rev. C | Page 7 of 21
AD5512A/AD5542A
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13 INV
14 VLOGIC
16 RFB
VOUT 1
15 VDD
AD5512A/AD5542A
12 DGND
TOP
VIEW
(Not to
Scale)
AGNDS 3
11 LDAC
10 CLR
9
REFS 4
REF 1
DIN
DIN 4
CLR 5
AD5542A-1
TOP VIEW
(Not to Scale)
9
VDD
8
RFB
7
INV
6
VOUT
NOTES
1. THE EXPOSED PAD SHOULD BE TIED
TO THE POINT OF LOWEST POTENTIAL,
IN THIS CASE, GND.
09199-036
NC 7
SCLK 8
CS 6
REFF 5
SCLK 3
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD SHOULD BE TIED
TO THE POINT OF LOWEST POTENTIAL,
IN THIS CASE, GND.
10 GND
CS 2
09199-034
AGNDF 2
Figure 5. AD5542A-1 10-Lead LFCSP Pin Configuration
Figure 4. AD5512A/AD5542A 16-Lead LFCSP Pin Configuration
Table 7. AD5512A/AD5542A Pin Function Descriptions
Pin No.
16-Lead
10-Lead
LFCSP
LFCSP
1
6
2
3
4
Mnemonic
VOUT
AGNDF
AGNDS
REFS
5
REFF
6
7
8
2
3
CS
NC
SCLK
9
4
DIN
10
5
CLR
11
12
13
14
15
16
EPAD
LDAC
7
DGND
INV
9
8
1
VLOGIC
VDD
RFB
REF
10
EPAD
GND
Exposed Pad
Description
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can
range from 2 V to VDD.
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can
range from 2 V to VDD.
Logic Input Signal. The chip select signal is used to frame the serial data input.
No Connect.
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be
between 40% and 60%.
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the
rising edge of SCLK.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses
are ignored. When CLR is activated, the DAC register is cleared to the model selectable midscale.
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the
contents of the input register.
Digital Ground. Ground reference for digital circuitry.
Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op
amps inverting input in bipolar mode.
Logic Power Supply.
Analog Supply Voltage, 5 V ± 10%.
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
Voltage Reference Input for the DAC. Connect this pin to an external 2.5 V reference. Reference can
range from 2 V to VDD.
Ground.
The exposed pad should be tied to the point of lowest potential, in this case, GND.
Rev. C | Page 8 of 21
AD5512A/AD5542A
RFB 1
16
VDD
VOUT
2
15
VLOGIC
AGNDF
3
AD5542A
14
INV
TOP VIEW
(Not to Scale)
13
DGND
REFS 5
12
LDAC
REFF 6
11
CLR
DIN
AGNDS 4
NC
7
10
CS
8
9
NC = NO CONNECT
SCLK
09199-035
Data Sheet
Figure 6. AD5542A 16-Lead TSSOP Pin Configuration
Table 8. AD5542A Pin Function Descriptions
Pin No.
1
2
3
4
5
Mnemonic
RFB
VOUT
AGNDF
AGNDS
REFS
6
REFF
7
8
9
NC
CS
SCLK
10
11
DIN
CLR
12
LDAC
13
14
DGND
INV
15
16
VLOGIC
VDD
Description
Feedback Resistor Pin. In bipolar mode, connect this pin to the external op amp output.
Analog Output Voltage from the DAC.
Ground Reference Point for Analog Circuitry (Force).
Ground Reference Point for Analog Circuitry (Sense).
Voltage Reference Input (Sense) for the DAC. Connect to an external 2.5 V reference. Reference can range from
2 V to VDD.
Voltage Reference Input (Force) for the DAC. Connect to an external 2.5 V reference. Reference can range from
2 V to VDD.
No Connect.
Logic Input Signal. The chip select signal is used to frame the serial data input.
Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle must be between 40%
and 60%.
Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the rising edge of SCLK.
Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are ignored.
When CLR is activated, the DAC register is cleared to the model selectable midscale.
LDAC Input. When this input is taken low, the DAC register is simultaneously updated with the contents of the
input register.
Digital Ground. Ground reference for digital circuitry.
Connection to the Internal Scaling Resistors of the DAC. Connect the INV pin to the external op amps inverting
input in bipolar mode.
Logic Power Supply.
Analog Supply Voltage, 5 V ± 10%.
Rev. C | Page 9 of 21
AD5512A/AD5542A
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.50
0.50
0
–0.25
–0.50
–0.75
8192
0
16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE
VDD = 5V
VREF = 2.5V
0.25
0
–0.25
–0.50
0
Figure 7. AD5542A Integral Nonlinearity vs. Code
0.75
0
–0.25
–0.50
–1.00
–60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
0.50
0.25
0
–0.25
–0.50
–60
09199-007
–0.75
VDD = 5V
VREF = 2.5V
Figure 8. AD5542A Integral Nonlinearity vs. Temperature
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
09199-010
DIFFERENTIAL NONLINEARITY (LSB)
VDD = 5V
VREF = 2.5V
Figure 11. AD5542A Differential Nonlinearity vs. Temperature
0.50
0.75
VDD = 5V
TA = 25°C
VREF = 2.5V
TA = 25°C
0.50
0.25
LINEARITY ERROR (LSB)
DNL
0
–0.25
DNL
0.25
0
INL
–0.25
–0.50
2
3
4
5
SUPPLY VOLTAGE (V)
6
7
09199-008
INL
–0.75
Figure 9. AD5542A Linearity Error vs. Supply Voltage
–0.50
0
1
2
3
4
REFERENCE VOLTAGE (V)
5
Figure 12. AD5542A Linearity Error vs. Reference Voltage
Rev. C | Page 10 of 21
6
09199-011
INTEGRAL NONLINEARITY (LSB)
16,384 24,576 32,768 40,960 49,152 57,344 65,536
CODE
Figure 10. AD5542A Differential Nonlinearity vs. Code
0.25
LINEARITY ERROR (LSB)
8192
09199-009
DIFFERENTIAL NONLINEARITY (LSB)
0.25
09199-006
INTEGRAL NONLINEARITY (LSB)
VDD = 5V
VREF = 2.5V
Data Sheet
AD5512A/AD5542A
0
0.15
VDD = 5V
VREF = 2.5V
TA = 25°C
–0.1
0.10
ZERO-CODE ERROR (LSB)
GAIN ERROR (LSB)
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
VDD = 5V
VREF = 2.5V
TA = 25°C
0.05
0
–0.05
–0.10
–0.8
25
TEMPERATURE (°C)
85
–0.15
–40
Figure 13. AD5512A/AD5542A Gain Error vs. Temperature
25
TEMPERATURE (°C)
09199-015
–40
09199-012
–0.9
85
Figure 16. AD5512A/AD5542A Zero-Code Error vs. Temperature
2.0
TA = 25°C
132
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
VDD = 5V
VREF = 2.5V
130 TA = 25°C
128
126
124
122
120
1.5
REFERENCE VOLTAGE
VDD = 5V
1.0
SUPPLY VOLTAGE
VREF = 2.5V
0.5
118
25
TEMPERATURE (°C)
0
09199-013
–40
85
2
1
3
4
6
Figure 17. AD5512A/AD5542A Supply Current vs. Reference Voltage or
Supply Voltage
Figure 14. AD5512A/AD5542A Supply Current vs. Temperature
200
200
VDD = 5V
VREF = 2.5V
TA = 25°C
180
REFERENCE CURRENT (µA)
160
SUPPLY CURRENT (µA)
5
VOLTAGE (V)
09199-016
0
116
140
120
100
80
60
40
150
100
50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
DIGITAL INPUT VOLTAGE (V)
0
09199-014
0
0
Figure 15. AD5512A/AD5542A Supply Current vs. Digital Input Voltage
Rev. C | Page 11 of 21
10,000
20,000
30,000 40,000
CODE (Decimal)
50,000
60,000
70,000
Figure 18. AD5512A/AD5542A Reference Current vs. Code
09199-017
20
AD5512A/AD5542A
Data Sheet
VREF = 2.5V
VDD = 5V
TA = 25°C
VREF = 2.5V
VDD = 5V
TA = 25°C
100
100
DIN (5V/DIV)
90
VOUT (1V/DIV)
90
VOUT (50mV/DIV)
GAIN = –216
1LSB = VREF /(2N)–1
0
0
09199-018
10
2µs/DIV
09199-021
VOUT (50mV/DIV)
10
0.5µs/DIV
Figure 19. AD5512A/AD5542A Digital Feedthrough
Figure 22. AD5512A/AD5542A Small Signal Settling Time
5
1.236
5
+125°C
+25°C
–55°C
CS
0
1.234
4
–5
3
–10
HITS
VOLTAGE (V)
1.232
1.230
–15
2
1.228
VOUT
–20
1
1.226
0
0.5
1.0
1.5
–30
2.0
TIME (ns)
0
09199-032
1.224
–0.5
90
Figure 20. AD5512A/AD5542A Digital-to-Analog Glitch Impulse
100
110
IDD SUPPLY (µA)
120
Figure 23. AD5512A/AD5542A Analog Supply Current Histogram
6
VREF = 2.5V
VDD = 5V
TA = 25°C
2µs/DIV
100
09199-042
–25
+125°C
+25°C
–55°C
5
CS (5V/DIV)
4
90
HITS
10pF
50pF
3
100pF
2
200pF
1
10
09199-020
0
VOUT (0.5V/DIV)
Figure 21. AD5512A/AD5542A Large Signal Settling Time
15
16
17
18
ILOGIC AT RAILS (µA)
19
09199-043
0
Figure 24. AD5512A/AD5542A Digital Supply Current Histogram
Rev. C | Page 12 of 21
Data Sheet
AD5512A/AD5542A
40
10
OUTPUT NOISE (µV rms)
VDD = 5V
VREF = 2.5V
TA = 25°C
DATA = 0x0000
VDD = 5V
VREF = 5V
TA = 25°C
20
0
VOUT (dBm)
5
–20
–40
0
–60
40
20
0
80
60
FREQUENCY (Hz)
100
120
–100
09199-037
–5
0
Figure 25. AD5512A/AD5542A 0.1 Hz to 10 Hz Output Noise
60,000
70,000
0
VOUT/VREF (dBm)
–10
25
20
15
–20
–30
–40
10
800
900
1000
1100
FREQUENCY (Hz)
1200
1300
1400
14
12
10
8
6
4
9700
9800
9900 10,000 10,100 10,200 10,300 10,400
FREQUENCY (Hz)
09199-039
VDD = 5V
VREF = 2.5V
TA = 25°C
2
Figure 27. AD5512A/AD5542A Noise Spectral Density vs. Frequency, 10 kHz
Rev. C | Page 13 of 21
–60
1k
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 29. AD5512A/AD5542A Multiplying Bandwidth
100M
09199-041
700
Figure 26. AD5512A/AD5542A Noise Spectral Density vs. Frequency,1 kHz
0
9600
VDD = 5V
VREF = 2.5V ± 0.2V
–50
5
09199-038
NOISE SPECTRAL DENSITY (nV rms/ Hz)
30,000 40,000 50,000
FREQUENCY (Hz)
10
VDD = 5V
VREF = 2.5V
TA = 25°C
30
0
600
NOISE SPECTRAL DENSITY (nV rms/ Hz)
20,000
Figure 28. AD5512A/AD5542A Total Harmonic Distortion
40
35
10,000
09199-040
–80
AD5512A/AD5542A
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or INL is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL vs. code plot is shown in Figure 7.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures monotonicity. A typical DNL vs. code plot is shown in Figure 10.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range.
It is the deviation in slope of the DAC transfer characteristic
from ideal.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change
in gain error with changes in temperature. It is expressed in
ppm/°C.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code is loaded to the DAC register.
Zero-Code Temperature Coefficient
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in mV/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by
1 LSB at the major carry transition. A digital-to-analog glitch
impulse plot is shown in Figure 20.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but it is measured when the DAC output is not updated.
CS is held high while the SCLK and DIN signals are toggled. It
is specified in nV-sec and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice
versa. A typical digital feedthrough plot is shown in Figure 19.
Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the power supply voltage. The power supply rejection ratio is
quoted in terms of percent change in output per percent change
in VDD for full-scale output of the DAC. VDD is varied by ±10%.
Reference Feedthrough
Reference feedthrough is a measure of the feedthrough from the
VREF input to the DAC output when the DAC is loaded with all 0s.
A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough is
expressed in mV p-p.
Rev. C | Page 14 of 21
Data Sheet
AD5512A/AD5542A
THEORY OF OPERATION
The AD5512A/AD5542A are single, 12-/16-bit, serial input,
voltage output DACs. They operate from a single supply
ranging from 2.7 V to 5 V and consume typically 125 µA
with a supply of 5 V. Data is written to these devices in a
12-bit (AD5512A) or 16-bit (AD5542A) word format, via a
3- or 4-wire serial interface. To ensure a known power-up
state, these parts are designed with a power-on reset function.
In unipolar mode, the output is reset to midscale; in bipolar
mode, the output is set to 0 V. Kelvin sense connections for the
reference and analog ground are included on the AD5512A/
AD5542A.
DIGITAL-TO-ANALOG SECTION
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 30. The DAC
architecture of the AD5512A/AD5542A is segmented. The four
MSBs of the 16-bit (AD5542A)/12-bit (AD5512A) data-word
are decoded to drive 15 switches, E1 to E15. Each switch
connects one of 15 matched resistors to either AGND or VREF.
The remaining 12 bits of the data-word drive the S0 to S11
switches of a 12-bit voltage mode R-2R ladder network.
VOUT
2R
2R . . . . .
2R
2R
2R . . . . .
2R
S0
S1 . . . . .
S11
E1
E2 . . . . .
E15
UNIPOLAR OUTPUT OPERATION
FOUR MSBs DECODED
INTO 15 EQUAL SEGMENTS
09199-022
VREF
12-BIT R-2R LADDER
Figure 30. DAC Architecture
With this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by
the reference is heavily code dependent. The output voltage is
dependent on the reference voltage, as shown in the following
equation:
VOUT =
VREF × D
2
The AD5512A/AD5542A have an LDAC function that allows
the DAC latch to be updated asynchronously by bringing LDAC
low after CS goes high. LDAC should be maintained high while
data is written to the shift register. Alternatively, LDAC can be
tied permanently low to update the DAC synchronously. With
LDAC tied permanently low, the rising edge of CS loads the data to
the DAC.
These DACs are capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low supply current, typically
300 μA, and a low offset error. The AD5512A/AD5542A
provide a unipolar output swing ranging from 0 V to VREF.
The AD5512A/AD5542A can be configured to output both
unipolar and bipolar voltages. Figure 31 shows a typical
unipolar output voltage circuit. The code table for this
mode of operation is shown in Table 9.
5V
10µF
0.1µF
SERIAL
INTERFACE
N
0.1µF
VDD
REFF
REFS
AD820/
OP196
CS
DIN
where:
D is the decimal data-word loaded to the DAC register.
N is the resolution of the DAC.
SCLK
AD5512A/
AD5542A
VOUT
LDAC
DGND AGNDF AGNDS
For a reference of 2.5 V, the equation simplifies to the following:
VOUT =
2.5V
Table 9. AD5542A Unipolar Code Table
65,536
DAC Latch Contents
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
The LSB size is VREF/65,536.
EXTERNAL
OP AMP
Figure 31. Unipolar Output
2. 5 × D
This gives a VOUT of 1.25 V with midscale loaded, and 2.5 V
with full scale loaded to the DAC.
UNIPOLAR
OUTPUT
Rev. C | Page 15 of 21
Analog Output
VREF × (65,535/65,536)
VREF × (32,768/65,536) = ½ VREF
VREF × (1/65,536)
0V
09199-023
2R
R
The AD5512A/AD5542A are controlled by a versatile 3- or 4wire serial interface that operates at clock rates of up to 50 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards. The timing diagram is shown in Figure 3.
Input data is framed by the chip select input, CS. After a highto-low transition on CS, data is shifted synchronously and
latched into the input register on the rising edge of the serial
clock, SCLK. Data is loaded MSB first in 12-bit (AD5512A)
or 16-bit (AD5542A) words. After 12 (AD5512A) or 16
(AD5542A) data bits have been loaded into the serial input
register, a low-to-high transition on CS transfers the contents
of the shift register to the DAC. Data can be loaded to the part
only while CS is low.
+
R
SERIAL INTERFACE
AD5512A/AD5542A
Data Sheet
2.5 V reference and the AD8628 low offset and zero-drift
reference buffer.
Assuming a perfect reference, the unipolar worst-case output
voltage can be calculated from the following equation:
D
V REF V GE V ZSE INL
2N
Table 10. AD5542A Bipolar Code Table
DAC Latch Contents
MSB
LSB
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
where:
VOUT−UNI is the unipolar mode worst-case output.
D is the code loaded to DAC.
N is the resolution of the DAC.
VREF is the reference voltage applied to the part.
VGE is the gain error in volts.
VZSE is the zero-scale error in volts.
INL is the integral nonlinearity in volts.
Analog Output
+VREF × (32,767/32,768)
+VREF × (1/32,768)
0V
−VREF × (1/32,768)
−VREF × (32,768/32,768) = −VREF
Assuming a perfect reference, the worst-case bipolar output
voltage can be calculated from the following equation:
BIPOLAR OUTPUT OPERATION
V OUT BIP
With the aid of an external op amp, the AD5512A/AD5542A
can be configured to provide a bipolar voltage output. A typical
circuit is shown in Figure 32. The matched bipolar offset resistors,
RFB and RINV, are connected to an external op amp to achieve
this bipolar output swing, typically RFB = RINV = 28 kΩ. Table 10
shows the transfer function for this output operating mode.
Also provided on the AD5542A are a set of Kelvin connections
to the analog ground inputs. The example includes the ADR421
[(VOUT UNI V OS )(2 RD ) V REF (1 RD )]
1 (2 RD )
A
where:
VOUT−BIP is the bipolar mode worst-case output
VOUT−UNI is the unipolar mode worst-case output.
VOS is the external op amp input offset voltage.
RD is the RFB and RINV resistor matching error.
A is the op amp open-loop gain.
+5V +2.5V
+
10µF
0.1µF
0.1µF
RFB
SERIAL
INTERFACE
VDD
REFF
REFS
CS
DIN
SCLK
LDAC
AD5512A/
AD5542A
RINV
RFB
+5V
INV
VOUT
DGND AGNDF AGNDS
Figure 32. Bipolar Output
Rev. C | Page 16 of 21
BIPOLAR
OUTPUT
–5V
EXTERNAL
OP AMP
09199-024
V OUT UNI
Data Sheet
AD5512A/AD5542A
OUTPUT AMPLIFIER SELECTION
REFERENCE AND GROUND
For bipolar mode, a precision amplifier should be used and
supplied from a dual power supply. This provides the ±VREF
output. In a single-supply application, selection of a suitable op
amp may be more difficult because the output swing of the amplifier does not usually include the negative rail, in this case,
AGND. This can result in some degradation of the specified
performance unless the application does not use codes near zero.
Because the input impedance is code-dependent, the reference pin should be driven from a low impedance source. The
AD5512A/AD5542A operate with a voltage reference ranging
from 2 V to VDD. References below 2 V result in reduced accuracy.
The full-scale output voltage of the DAC is determined by the
reference. Table 9 and Table 10 outline the analog output voltage
or particular digital codes. For optimum performance, Kelvin
sense connections are provided on the AD5512A/AD5542A.
The selected op amp must have a very low-offset voltage (the
DAC LSB is 38 μV for the AD5542A with a 2.5 V reference)
to eliminate the need for output offset trims. Input bias current
should also be very low because the bias current, multiplied by
the DAC output impedance (approximately 6 kΩ), adds to the
zero-code error. Rail-to-rail input and output performance is
required. For fast settling, the slew rate of the op amp should
not impede the settling time of the DAC. Output impedance
of the DAC is constant and code-independent, but to minimize
gain errors, the input impedance of the output amplifier should
be as high as possible. The amplifier should also have a 3 dB
bandwidth of 1 MHz or greater. The amplifier adds another
time constant to the system, thus increasing the settling time
of the output. A higher 3 dB amplifier bandwidth results in a
shorter effective settling time of the combined DAC and amplifier.
FORCE SENSE AMPLIFIER SELECTION
Use single-supply, low-noise amplifiers. A low-output impedance
at high frequencies is preferred because the amplifiers must be
able to handle dynamic currents of up to ±20 mA.
If the application doesn’t require separate force and sense lines,
tie the lines close to the package to minimize voltage drops
between the package leads and the internal die.
POWER-ON RESET
The AD5512A/AD5542A have a power-on reset function to
ensure that the output is at a known state on power-up. On
power-up, the DAC register MSB is 1 and all other bits are 0
until the data is loaded from the serial register. However, the
serial register is not cleared on power-up; therefore, its contents
are undefined. When loading data initially to the DAC, 16 bits or
more should be loaded to prevent erroneous data appearing on
the output. If more than 16 bits are loaded, the last 16 are kept,
and if less than 16 bits are loaded, bits remain from the previous
word. If the AD5512A/AD5542A must be interfaced with data
shorter than 16 bits, the data should be padded with 0s at the
LSBs.
POWER SUPPLY AND REFERENCE BYPASSING
For accurate high-resolution performance, it is recommended
that the reference and supply pins be bypassed with a 10 μF
tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.
Rev. C | Page 17 of 21
AD5512A/AD5542A
Data Sheet
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
AD5512A/AD5542A TO 68HC11/68L11 INTERFACE
Microprocessor interfacing to the AD5512A/AD5542A is via
a serial bus that uses standard protocol that is compatible with
DSP processors and microcontrollers. The communications
channel requires a 3- or 4-wire interface consisting of a clock
signal, a data signal, and a synchronization signal. The
AD5512A/AD5542A require a 16-bit data-word with data
valid on the rising edge of SCLK. The DAC update can be
done automatically when all the data is clocked in, or it can
be done under the control of the LDAC.
Figure 35 shows a serial interface between the AD5512A/
AD5542A and the 68HC11/68L11 microcontroller. SCK of
the 68HC11/68L11 drives the SCLK of the DAC, and the
MOSI output drives the serial data line serial DIN. The CS
signal is driven from one of the port lines. The 68HC11/68L11 is
configured for master mode: MSTR = 1, CPOL = 0, and CPHA =
0. Data appearing on the MOSI output is valid on the rising
edge of SCK.
The SPI interface of the AD5512A/AD5542A is designed to be
easily connected to industry-standard DSPs and microcontrollers. Figure 33 shows how the AD5512A/AD5542A
can be connected to the Analog Devices, Inc., Blackfin® DSP.
The Blackfin has an integrated SPI port that can be connected
directly to the SPI pins of the AD5512A/AD5542A.
SCK
MOSI
CS
SCLK
DIN
SCK
SPORT_DTO
MICROWIRE*
AD5512A/
AD5542A
SCLK
DIN
09919-045
LDAC
CS
CS
SO
DIN
SCLK
ADSP-BF527
GPIO0
SCLK
AD5512A/AD5542A TO MICROWIRE INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 34 shows how one SPORT interface can be used to
control the AD5512A/AD5542A.
SPORT_TSCK
AD5512A/
AD5542A*
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5512A/AD5542A TO SPORT INTERFACE
CS
DIN
Figure 35. AD5512A/AD5542A to 68HC11/68L11 Interface
Figure 33. AD5512A/AD5542A to ADSP-BF531 Interface
SPORT_TFS
CS
MOSI
09199-044
LDAC
LDAC
PC7
Figure 36 shows an interface between the AD5512A/AD5542A
and any MICROWIRE-compatible device. Serial data is shifted
out on the falling edge of the serial clock and into the AD5512A/
AD5542A on the rising edge of the serial clock. No glue logic
is required because the DAC clocks data into the input shift
register on the rising edge.
AD5512A/
AD5542A
ADSP-BF531
PF9
PC6
Figure 34. AD5512A/AD5542A to ADSP-BF527 Interface
Rev. C | Page 18 of 21
AD5512A/
AD5542A*
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY.
09199-027
SPISELx
68HC11/
68L11*
09199-026
AD5512A/AD5542A TO ADSP-BF531 INTERFACE
Figure 36. AD5512A/AD5542A to MICROWIRE Interface
Data Sheet
AD5512A/AD5542A
LAYOUT GUIDELINES
DECODING MULTIPLE DACS
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. Design the printed circuit board
(PCB) on which the AD5512A/AD5542A is mounted so that
the analog and digital sections are separated and confined to
certain areas of the board. If the AD5512A/AD5542A are in a
system where multiple devices require an analog ground-todigital ground connection, make the connection at one point
only. Establish the star ground point as close as possible to the
device.
The CS pin of the AD5512A/AD5542A can be used to select
one of a number of DACs. All devices receive the same serial
clock and serial data, but only one device receives the CS signal
at any one time. The DAC addressed is determined by the
decoder. There is some digital feedthrough from the digital
input lines. Using a burst clock minimizes the effects of digital
feedthrough on the analog signal channels. Figure 38 shows a
typical circuit.
CS
DIN
CODED
ADDRESS
SCLK
EN
CS
DECODER
DGND
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry
from any hazardous common-mode voltages that may occur.
iCoupler® products from Analog Devices provide voltage
isolation in excess of 2.5 kV. The serial loading structure
of the AD5512A/AD5542A makes the parts ideal for isolated
interfaces because the number of interface lines is kept to a
minimum. Figure 37 shows a 4-channel isolated interface to
the AD5512A/AD5542A using an ADuM1400. For further
information, visit http://www.analog.com/icouplers.
DIN
SERIAL
DATA OUT
VOA
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
VIB
VOB
VIC
SYNC OUT
LOAD DAC
OUT
1
VOC
VID
VOD
ADDITIONAL PINS OMITTED FOR CLARITY.
TO
SCLK
TO
DIN
TO
CS
TO
LDAC
09199-046
SERIAL
CLOCK IN
ADuM14001
Figure 37. Isolated Interface
Rev. C | Page 19 of 21
VOUT
SCLK
CS
VIA
AD5512A/
AD5542A
DIN
GALVANICALLY ISOLATED INTERFACE
CONTROLLER
VOUT
DIN
VDD
ENABLE
AD5512A/
AD5542A
AD5512A/
AD5542A
VOUT
SCLK
CS
AD5512A/
AD5542A
DIN
SCLK
Figure 38. Addressing Multiple DACs
VOUT
09199-030
The AD5512A/AD5542A should have ample supply bypassing
of 10 μF in parallel with 0.1 μF on each supply located as close
to the package as possible, ideally right up against the device.
The 10 μF capacitors are the tantalum bead type. The 0.1 μF
capacitor should have low effective series resistance (ESR)
and low effective series inductance (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching.
SCLK
AD5512A/AD5542A
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.50
BSC
13
PIN 1
INDICATOR
16
1
12
EXPOSED
PAD
1.75
1.60 SQ
1.45
9
TOP VIEW
0.80
0.75
0.70
4
5
8
0.50
0.40
0.30
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-16-2010-E
PIN 1
INDICATOR
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 39. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.65
BSC
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 40. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. C | Page 20 of 21
0.75
0.60
0.45
Data Sheet
AD5512A/AD5542A
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
1
5
BOTTOM VIEW
0.80
0.75
0.70
SEATING
PLANE
0.30
0.25
0.20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-05-2013-C
TOP VIEW
0.20 REF
Figure 41. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD5512AACPZ-REEL7
AD5512AACPZ-500RL7
AD5542ABRUZ
AD5542ABRUZ-REEL7
AD5542AARUZ
AD5542AARUZ-REEL7
AD5542ABCPZ-REEL7
AD5542AACPZ-REEL7
AD5542ABCPZ-1-RL7
AD5542ABCPZ-500RL7
EVAL-AD5542ASDZ
1
INL
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±2 LSB
±2 LSB
±1 LSB
±2 LSB
±1 LSB
±1 LSB
DNL
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
±1 LSB
Power On
Reset to Code
Midscale
Midscale
Midscale
Midscale
Midscale
Midscale
Midscale
Midscale
Midscale
Midscale
Temperature
Range
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Z = RoHS Compliant Part.
©2010–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09199-0-2/17(C)
Rev. C | Page 21 of 21
Package Description
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
10-Lead LFCSP_WD
16-Lead LFCSP_WQ
AD5541A Evaluation Board
Package Option
CP-16-22
CP-16-22
RU-16
RU-16
RU-16
RU-16
CP-16-22
CP-16-22
CP-10-9
CP-16-22
Branding
DFQ
DFQ
DFL
DFK
DFM
DFL
工商网监
湘ICP备2023018690号
