AD5592RBRUZ

Data Sheet AD5592R 8-Channel, 12-Bit, Configurable ADC/DAC with On-Chip Reference, SPI Interface (DAC) outputs, analog-to-digital converter (ADC) inputs, digital outputs, or digital inputs. When an I/Ox pin is configured as an analog output, it is driven by a 12-bit DAC. The output range of the DAC is 0 V to VREF or 0 V to 2 × VREF. When an I/Ox pin is configured as an analog input, it is connected to a 12-bit ADC via an analog multiplexer. The input range of the ADC is 0 V to VREF or 0 V to 2 × VREF. The ADC has a total throughput rate of 400 kSPS. The I/Ox pins can also be configured as digital, general-purpose input or output (GPIO) pins. The state of the GPIO pins can be set or read back by accessing the GPIO write data register or the GPIO read configuration register, respectively, via a serial peripheral interface (SPI) write or read operation. FEATURES ► ► ► ► ► ► ► ► 8-channel, configurable ADC/DAC/GPIO Configurable as any combination of ► 8 × 12-bit DAC channels ► 8 × 12-bit ADC channels ► 8 × general-purpose digital input/output pins Integrated temperature sensor SPI interface 2.7 V to 5.5 V power supply 1.8 V logic compatibility (AD5592R-1) Available in ► 16-ball, 2 mm × 2 mm WLCSP ► 16-lead, 3 mm × 3 mm LFCSP ► 16-lead TSSOP AEC-Q100 qualified for automotive applications The AD5592R/AD5592R-1 have an integrated 2.5 V, 20 ppm/°C reference, which is turned off by default, and an integrated temperature indicator, which gives an indication of the die temperature. The temperature value is read back as part of an ADC read sequence. APPLICATIONS ► ► Control and monitoring General-purpose analog and digital inputs/outputs The AD5592R/AD5592R-1 are available in 16-ball, 2 mm × 2 mm WLCSP, 16-lead, 3 mm × 3 mm LFCSP, and 16-lead TSSOP. The AD5592R/AD5592R-1 operate over a temperature range of −40 °C (TA) to +125 °C (TJ). Table 1. Related Products GENERAL DESCRIPTION The AD5592R/AD5592R-1 have eight I/Ox pins (I/O0 to I/O7) that can be independently configured as digital-to-analog converter FUNCTIONAL BLOCK DIAGRAM Part No. Description AD5593R AD5592R equivalent with VLOGIC and RESET pins and an I2C interface Figure 1. AD5592R Functional Block Diagram Rev. G DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Data Sheet AD5592R TABLE OF CONTENTS Features................................................................ 1 Applications........................................................... 1 General Description...............................................1 Functional Block Diagram......................................1 Functional Block Diagram (AD5592R-1)............... 5 Specifications........................................................ 6 Timing Characteristics........................................9 Absolute Maximum Ratings.................................12 Thermal Resistance......................................... 12 Electrostatic Discharge (ESD) Ratings.............12 ESD Caution.....................................................12 Pin Configurations and Function Descriptions.....13 Typical Performance Characteristics................... 16 Terminology......................................................... 21 ADC Terminology............................................. 21 DAC Terminology............................................. 21 Theory of Operation.............................................23 DAC Section.....................................................23 ADC Section.....................................................24 GPIO Section................................................... 25 Internal Reference............................................25 RESET Function...............................................25 Temperature Indicator...................................... 25 Serial Interface.................................................... 26 Power-Up Time................................................ 27 Write Mode....................................................... 27 Read Mode.......................................................27 Configuring the AD5592R/AD5592R-1.............27 General-Purpose Control Register................... 29 DAC Write Operation........................................29 DAC Readback.................................................29 ADC Operation................................................. 29 GPIO Operation................................................32 Three-State Pins.............................................. 33 85 KΩ Pull-Down Resistor Pins........................33 Power-Down Mode...........................................33 Reset Function................................................. 33 Readback and LDAC Mode Register............... 33 Applications Information...................................... 34 Microprocessor Interfacing............................... 34 AD5592R/AD5592R-1 to SPI Interface............ 34 AD5592R/AD5592R-1 to SPORT Interface......34 Layout Guidelines.............................................34 Register Map....................................................... 35 Register Summary: AD5592R/AD5592R-1 Control Register Map..................................... 35 Register Details: AD5592R/AD5592R-1 Control Register Map..................................... 35 Data Format Details: AD5592R/AD5592R-1 ADC and DAC Readback .............................. 51 Outline Dimensions............................................. 53 Ordering Guide.................................................54 Evaluation boards.............................................54 Automotive Products........................................ 54 REVISION HISTORY 8/2022—Rev. F to Rev. G Changes to Features Section.......................................................................................................................... 1 Changes to General Description Section.........................................................................................................1 Changes to Specifications Section and Table 2...............................................................................................6 Changes to Timing Characteristics Section and t4 Parameter, Table 3........................................................... 9 Changes to t1 Parameter and t4 Parameter, Table 3; and Figure 4............................................................... 10 Added Figure 5; Renumbered Sequentially................................................................................................... 11 Changes to Thermal Resistance Section and Table 6................................................................................... 12 Added Electrostatic Discharge (ESD) Ratings Section, ESD Ratings for AD5592R/AD5592R-1 Section, and Table 7; Renumbered Sequentially....................................................................................................... 12 Changes to Table 8........................................................................................................................................ 13 Deleted Table 8, Table 9, and Table 11; Renumbered Sequentially...............................................................13 Moved Figure 7 and Figure 8.........................................................................................................................13 Moved Figure 10............................................................................................................................................ 15 Changes to Table 9........................................................................................................................................ 15 Added DAC Output Range Section, Figure 40, and Figure 41...................................................................... 23 Changes to ADC Section............................................................................................................................... 24 Deleted Table 12............................................................................................................................................ 24 Changes to GPIO Section..............................................................................................................................25 analog.com Rev. G | 2 of 54 Data Sheet AD5592R TABLE OF CONTENTS Changes to Internal Reference Section......................................................................................................... 25 Changes to RESET Function Section............................................................................................................25 Changes to Temperature Indicator Section....................................................................................................25 Changes to Serial Interface Section.............................................................................................................. 26 Moved Table 10..............................................................................................................................................26 Changes to Read Mode Section.................................................................................................................... 27 Changes to Configuring the AD5592R/AD5592R-1 Section, Table 11, and Table 12....................................27 Changes to General-Purpose Control Register Section................................................................................ 29 Deleted Table 17 and Table 18...................................................................................................................... 29 Changes to DAC Write Operation Section.....................................................................................................29 Changes to LDAC Mode Operation Section.................................................................................................. 29 Deleted Table 19 to Table 22......................................................................................................................... 29 Changes to DAC Readback Section..............................................................................................................29 Deleted Table 23 and Table 24...................................................................................................................... 29 Changes to ADC Operation Section.............................................................................................................. 29 Moved Figure 45 to Figure 48........................................................................................................................30 Changes to Changing an ADC Sequence Section........................................................................................ 31 Deleted Table 25 to Table 29......................................................................................................................... 31 Added ADC Conversion Result Section.........................................................................................................32 Changes to Setting Pins as Outputs Section................................................................................................. 32 Changes to Setting Pins as Inputs Section....................................................................................................32 Moved Figure 50............................................................................................................................................ 32 Deleted Table 30 to Table 37......................................................................................................................... 32 Deleted Table 38 to Table 41......................................................................................................................... 33 Changes to Power-Down Mode Section........................................................................................................ 33 Deleted Table 42 and Table 43...................................................................................................................... 33 Changes to Reset Function Section.............................................................................................................. 33 Changes to Readback and LDAC Mode Register Section............................................................................ 33 Deleted Table 44 to Table 46......................................................................................................................... 33 Added Register Map Section......................................................................................................................... 35 Added Register Summary: AD5592R/AD5592R-1 Control Register Map Section........................................ 35 Moved Table 13..............................................................................................................................................35 Changes to Table 13...................................................................................................................................... 35 Added Register Details: AD5592R/AD5592R-1 Control Register Map Section.............................................35 Added NOP Register Section and Table 14...................................................................................................36 Added DAC Readback Register Section and Table 15..................................................................................36 Added ADC Sequence Register Section and Table 16..................................................................................37 Added General-Purpose Control Register Section and Table 17...................................................................38 Added ADC Pin Configuration Register Section and Table 18...................................................................... 39 Added DAC Pin Configuration Register Section and Table 19...................................................................... 40 Added Pull-Down Configuration Register Section and Table 20....................................................................41 Added Configuration Register Readback and LDAC Mode Register Section and Table 21.......................... 42 Added GPIO Write Configuration Register Section and Table 22..................................................................43 Added GPIO Write Data Register Section and Table 23................................................................................44 Added GPIO Read Configuration Register Section and Table 24..................................................................46 Added Power-Down/Reference Control Register Section and Table 25........................................................47 Added GPIO Open-Drain Configuration Register Section and Table 26........................................................48 Added Three-State Configuration Register Section and Table 27................................................................. 49 Added Software Reset Register Section and Table 28.................................................................................. 50 analog.com Rev. G | 3 of 54 Data Sheet AD5592R TABLE OF CONTENTS Added DAC Write Register Section and Table 29..........................................................................................50 Added Data Format Details: AD5592R/AD5592R-1 ADC and DAC Readback Section................................51 Added ADC Conversion Result Format Section and Table 30.......................................................................51 Added Temperature Reading Format Section and Table 31.......................................................................... 52 Added DAC Data Read Back Format Section and Table 32..........................................................................52 Changes to Ordering Guide........................................................................................................................... 54 Added Automotive Products Section............................................................................................................. 54 analog.com Rev. G | 4 of 54 Data Sheet AD5592R FUNCTIONAL BLOCK DIAGRAM (AD5592R-1) Figure 2. AD5592R-1 Functional Block Diagram analog.com Rev. G | 5 of 54 Data Sheet AD5592R SPECIFICATIONS VDD = 2.7 V to 5.5 V, VLOGIC = 2.7 V to 5.5 V (AD5592R-1 only), VREF = 2.5 V (external), RL = 2 kΩ to GND, CL = 200 pF to GND, typical values are at TA = 25°C, unless otherwise noted. Typical specifications are verified by characterization, not production tested. Table 2. Max Unit1 +105 +125 °C °C 0 VREF Bits V 0 −2 −2.5 2 × VREF +2 +2.5 V LSB LSB Differential Nonlinearity (DNL) Offset Error Gain Error Throughput Rate3 −1 +1 ±5 0.3 400 350 Track Time (tTRACK)3, 4 Conversion Time (tCONV)3, 4 500 LSB mV % FSR kSPS kSPS ns µs µs dB dB dB dB dB dB dB dB dB dB dB dB ns ns ps dB pF MHz MHz Parameter TEMPERATURE RANGE Specified Performance2 ADC PERFORMANCE Resolution Input Range Integral Nonlinearity (INL) Min −40 −40 12 2 69 67 61 69 67 60 −91 −89 −72 91 91 72 15 12 50 −95 45 8.2 1.6 Signal-to-Noise Ratio (SNR) Signal-to-Noise-and-Distortion (SINAD) Ratio Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Aperture Delay3 Aperture Jitter3 Channel-to-Channel Isolation Input Capacitance Full Power Bandwidth DAC PERFORMANCE5 Resolution Output Range Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Offset Error Offset Error Drift3 analog.com Typ 2 2.36 12 0 0 −1 −1 −3 VREF 2 × VREF +1 +1 +3 8 Test Conditions/Comments AD5592RWBCPZ-RL7 and AD5592RWBCPZ-1-RL7 fIN = 10 kHz sine wave When using the internal ADC buffer, there is a dead band of 0 V to 5 mV VDD = 5.5 V, input range = 0 V to VREF, AD5592RWBCPZRL7 and AD5592RWBCPZ-1-RL7 AD5592RWBCPZ-RL7 and AD5592RWBCPZ-1-RL7 AD5592RWBCPZ-RL7 and AD5592RWBCPZ-1-RL7 VDD = 2.7 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to 2 × VREF VDD = 2.7 V, input range = 0 V to VREF VDD = 3.3 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to 2 × VREF VDD = 2.7 V, input range = 0 V to VREF VDD = 3.3 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to 2 × VREF VDD = 2.7 V, input range = 0 V to VREF VDD = 3.3 V, input range = 0 V to VREF VDD = 5.5 V, input range = 0 V to 2 × VREF VDD = 3 V VDD = 5 V fIN = 5 kHz At 3 dB At 0.1 dB Bits V V LSB LSB mV µV/°C Rev. G | 6 of 54 Data Sheet AD5592R SPECIFICATIONS Table 2. Parameter Min Typ Max Unit1 Test Conditions/Comments % FSR % FSR mV % FSR Output range = 0 V to VREF Output range = 0 V to 2 × VREF 0.65 ±0.03 ±0.015 ±0.2 ±0.1 2 ±0.25 ±0.1 2 10 Gain Error Zero Code Error Total Unadjusted Error Capacitive Load (CL) Stability3 Resistive Load (RL) Short-Circuit Current DC Crosstalk3 DC Output Impedance DC Power Supply Rejection Ratio (PSRR)3 Load Impedance at Rails6 Load Regulation REFERENCE OUTPUT VREF Output Voltage VREF Temperature Coefficient Capacitive Load (CL) Stability Output Impedance3 Output Voltage Noise Output Voltage Noise Density Line Regulation analog.com 200 µV/mA 7 µs 1.25 6 2 1 0.1 1 0.1 240 200 V/µs µs nV-sec nV-sec nV-sec nV-sec nV-sec kHz nV/√Hz 81 77 74 −76 dB dB dB dB 1 25 −4 Power-Up Time DAC AC SPECIFICATIONS Slew Rate Settling Time DAC Glitch Impulse DAC to DAC Crosstalk Digital Crosstalk Analog Crosstalk Digital Feedthrough Multiplying Bandwidth Output Voltage Noise Spectral Density Signal-to-Noise Ratio (SNR) Peak Harmonic or Spurious Noise (SFDR) Signal-to-Noise-and-Distortion (SINAD) Ratio Total Harmonic Distortion (THD) REFERENCE INPUT VREF Input Voltage DC Leakage Current Reference Input Impedance 0.2 0.15 25 200 nF nF kΩ mA µV Ω mV/V Ω µV/mA +4 1 −1 VDD +1 V µA kΩ kΩ 2.505 2.515 V V 12 24 2.495 2.485 2.5 2.5 20 5 0.15 0.7 10 240 20 ppm/°C μF Ω Ω µV p-p nV/√Hz µV/V Output range = 0 V to VREF Output range = 0 V to 2 × VREF RL = ∞ RL = 1 kΩ Due to single channel, full-scale output change DAC code = midscale, VDD = 3 V ± 10% or 5 V ± 10% VDD = 5 V ± 10%, DAC code = midscale, −10 mA ≤ IOUT ≤ +10 mA VDD = 3 V ± 10%, DAC code = midscale, −10 mA ≤ IOUT ≤ +10 mA Coming out of power-down mode, VDD = 5 V Measured from 10% to 90% of full scale ¼ scale to ¾ scale settling to 1 LSB DAC code = full scale, output range = 0 V to VREF DAC code = midscale, output range = 0 V to 2 × VREF, measured at 10 kHz No I/Ox pins configured as DACs DAC output range = 0 V to 2 × VREF DAC output range = 0 V to VREF TA = 25°C TA = 25°C, AD5592RWBCPZ-RL7 and AD5592RWBCPZ-1-RL7 RL = 2 kΩ VDD = 2.7 V VDD = 5 V 0.1 Hz to 10 Hz TA = 25°C, f = 10 kHz, CL = 10 nF TA = 25°C, sweeping VDD from 2.7 V to 5.5 V Rev. G | 7 of 54 Data Sheet AD5592R SPECIFICATIONS Table 2. Parameter Load Regulation Sourcing Sinking Output Current Load Capability GPIO OUTPUT ISOURCE, ISINK Output Voltage High (VOH) Low (VOL) GPIO INPUT Input Voltage High (VIH) Low (VIL) Input Capacitance Hysteresis Input Current LOGIC INPUTS AD5592R Input Voltage High (VINH) Low (VINL) AD5592R-1 Input Voltage High (VINH) Min Unit1 Test Conditions/Comments 10 µV/V TA = 25°C, sweeping VDD from 2.7 V to 3.3 V 210 120 ±5 µV/mA µV/mA mA TA = 25°C, −5 mA ≤ load current ≤ +5 mA TA = 25°C, −5 mA ≤ load current ≤ +5 mA VDD ≥ 3 V 1.6 mA Typ VDD − 0.2 0.4 0.3 × VDD 20 0.2 ±1 Power-Down Mode VDD = 5 V (Normal Mode) analog.com ISOURCE = 1 mA ISINK = 1 mA V V pF V µA VDD = 2.7 V to 5.5 V 0.7 × VDD 0.3 × VDD V V VLOGIC = 2.7 V to 5.5 V 0.7 × VLOGIC V 0.3 × VLOGIC V −1 +1 10 VDD − 0.2 VLOGIC − 0.2 µA pF V 0.4 0.4 10 12 −40 −40 Accuracy Track Time POWER REQUIREMENTS VDD IDD V V VDD = 2.7 V to 5.5 V 0.7 × VDD Low (VINL) Input Current (IIN) Input Capacitance (CIN) LOGIC OUTPUT (SDO) Output High Voltage (VOH) AD5592R AD5592R-1 Output Low Voltage (VOL) AD5592R AD5592R-1 Floating-State Output Capacitance TEMPERATURE SENSOR3 Resolution Operating Range2 Max 5 20 Bits °C °C °C µs µs 5.5 2.7 V mA 3.5 µA mA +105 +125 ±3 2.7 1.6 V V pF Typically 10 nA, RESET = 1 µA typical ISOURCE = 200 µA VDD = 2.7 V to 5.5 V VLOGIC = 2.7 V to 5.5 V ISINK = 200 µA VDD = 2.7 V to 5.5 V VLOGIC = 2.7 V to 5.5 V AD5592RWBCPZ-RL7 and AD5592RWBCPZ-1-RL7 5 sample averaging ADC buffer enabled ADC buffer disabled Digital inputs = 0 V or VDD, I/O0 to I/O7 configured as DACs and ADCs, internal reference on, ADC buffer on, DAC code = 0xFFF, range is 0 V to 2 × VREF for DACs and ADCs I/O0 to I/O7 are DACs, internal reference, gain = 2 Rev. G | 8 of 54 Data Sheet AD5592R SPECIFICATIONS Table 2. Parameter Min VDD = 3 V (Normal Mode) VLOGIC ILOGIC Unit1 Test Conditions/Comments 1 2.4 mA mA 1.1 mA 1 0.75 0.5 0.5 0.5 mA mA mA mA mA 1.1 1 1.1 mA mA mA 0.78 mA 0.75 0.5 0.45 0.45 mA mA mA mA V µA I/O0 to I/O7 are DACs, external reference, gain = 2 I/O0 to I/O7 are DACs and sampled by the ADC, internal reference, gain = 2 I/O0 to I/O7 are DACs and sampled by the ADC, external reference, gain = 2 I/O0 to I/O7 are ADCs, internal reference, gain = 2 I/O0 to I/O7 are ADCs, external reference, gain = 2 I/O0 to I/O7 are general-purpose outputs I/O0 to I/O7 are general-purpose inputs I/O0 to I/O3 are general-purpose outputs, I/O4 to I/O7 are general-purpose inputs I/O0 to I/O7 are DACs, internal reference, gain = 1 I/O0 to I/O7 are DACs, external reference, gain = 1 I/O0 to I/O7 are DACs and sampled by the ADC, internal reference, gain = 1 I/O0 to I/O7 are DACs and sampled by the ADC, external reference, gain = 1 I/O0 to I/O7 are ADCs, internal reference, gain = 1 I/O0 to I/O7 are ADCs, external reference, gain = 1 I/O0 to I/O7 are general-purpose outputs I/O0 to I/O7 are general-purpose inputs AD5592R-1 only AD5592R-1 only Typ Max 1.62 VDD 3 1 All specifications expressed in decibels are referred to full-scale input (FSR) and tested with an input signal at 0.5 dB below full scale, unless otherwise noted. 2 The minimum is the ambient temperature (TA) and the maximum is the junction temperature (TJ). 3 Guaranteed by design and characterization; not production tested. 4 See Figure 5. 5 DC specifications tested with the outputs unloaded, unless otherwise noted. Linearity calculated using a code range of 8 to 4095. There is an upper dead band of 10 mV when VREF = VDD. 6 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 34). TIMING CHARACTERISTICS Guaranteed by design and characterization, not production tested; all input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; TA = TA, MIN to TA, MAX, unless otherwise noted. Table 3. AD5592R Timing Characteristics Parameter 2.7 V ≤ VDD < 3 V 3 V ≤ VDD ≤ 5.5 V Unit Test Conditions/Comments t1 33 50 16 16 15 1.65 7 5 15 30 20 50 10 10 10 1.65 7 5 10 30 ns min ns min ns min ns min ns min µs max ns min ns min ns min ns min SCLK cycle time, write operation SCLK cycle time, read operation SCLK high time SCLK low time SYNC falling edge to SCLK falling edge setup time SYNC falling edge to SCLK falling edge setup time1 Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time for register write operations t2 t3 t4 t5 t6 t7 t8 analog.com Rev. G | 9 of 54 Data Sheet AD5592R SPECIFICATIONS Table 3. AD5592R Timing Characteristics Parameter 2.7 V ≤ VDD < 3 V 3 V ≤ VDD ≤ 5.5 V Unit Test Conditions/Comments t9 t10 t11 60 0 25 250 60 0 25 250 ns min ns min ns max ns min Minimum SYNC high time for register read operations SYNC rising edge to next SCLK falling edge SCLK rising edge to SDO valid RESET low pulse width (not shown in Figure 4) 1 When reading an ADC conversion (see Figure 5). Table 4. AD5592R-1 Timing Characteristics Parameter 1.62 V ≤ VLOGIC < 3 V 3 V ≤ VLOGIC ≤ 5.5 V Unit Test Conditions/Comments t1 33 100 16 16 15 1.65 7 5 15 30 60 0 56 20 50 10 10 10 1.65 7 5 10 30 60 0 25 ns min ns min ns min ns min ns min µs max ns min ns min ns min ns min ns min ns min ns max SCLK cycle time, write operation SCLK cycle time, read operation SCLK high time SCLK low time SYNC to SCLK falling edge setup time SYNC to SCLK falling edge setup time1 Data setup time Data hold time SCLK falling edge to SYNC rising edge Minimum SYNC high time for write operations Minimum SYNC high time for register read operations SYNC rising edge to next SCLK falling edge SCLK rising edge to SDO valid t2 t3 t4 t5 t6 t7 t8 t9 t10 1 When reading an ADC conversion (see Figure 5). Figure 3. Load Circuit for Logic Output (SDO) Timing Specifications Figure 4. Serial Read and Write Timing Diagram analog.com Rev. G | 10 of 54 Data Sheet AD5592R SPECIFICATIONS Figure 5. ADC Conversion Timing Diagram analog.com Rev. G | 11 of 54 Data Sheet AD5592R ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. Table 5. Parameter Rating VDD to GND VLOGIC to GND Analog Input Voltage to GND AD5592R Digital Input Voltage to GND Digital Output Voltage to GND AD5592R-1 Digital Input Voltage to GND Digital Output Voltage to GND VREF to GND Operating Temperature Range Storage Temperature Range Junction Temperature (TJ max) Lead Temperature Soldering −0.3 V to + 7 V −0.3 V to + 7 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VLOGIC + 0.3 V −0.3 V to VLOGIC + 0.3 V −0.3 V to VDD + 0.3 V −40 °C (TA) to +125 °C (TJ) −65 °C to +150 °C 150 °C JEDEC industry standard J-STD-020 Do not use θJA, θJC, and θJB thermal resistances to perform direct calculation/measurement of the die temperature because doing so results in incorrect values. The thermal resistances assume 100% of the power that is dissipated along the specified path between the measurement points. The thermal resistances are directly dependent on the PCB design and environment. If direct measurement of the package is required, the ΨJT and ΨJB values must be used because they more accurately reflect the true thermal dissipation paths. θJC must only be used where an external heat sink is attached directly to the package. System level thermal simulation is highly recommended. For more details about the thermal resistances, refer to JEDEC51-12: Guidelines for Reporting and Using Electronic Package Thermal Information. Table 6. Thermal Resistance Package Type θJA θJB θJC-TOP ΨJT ΨJB Unit CP-16-32 RU-16 CB-16-3 92.4 127 103.2 39.6 60.2 64 48.2 42.2 0 37.4 59.1 78 °C/W °C/W °C/W 0.9 2.6 0 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ELECTROSTATIC DISCHARGE (ESD) RATINGS THERMAL RESISTANCE Human body model (HBM) per ANSI/ESDA/JEDEC JS-001. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Field induced charged device model (FICDM) per ANSI/ESDA/JEDEC JS-002. Thermal characteristics are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Thermal resistance values specified in Table 6 are simulated based on JEDEC specifications using a 2S2P thermal test board (see JEDEC JESD51), except for θJC-TOP, which uses a JEDEC 1S test board. θJA is the junction to ambient thermal resistance, measured in a JEDEC natural convection environment. θJC is the junction to case thermal resistance, measured at the centre of the package top surface, with an infinite heat sink attached to the package surface. θJB is the junction to board thermal resistance, measured at a point on the board 1mm from the package edge, along the package centre line, measured in a JEDEC θJB environment. The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only. ESD Ratings for AD5592R/AD5592R-1 Table 7. AD5592R/AD5592R-1, 16-Ball WLCSP, 16-lead LFCSP, and 16-Lead TSSOP ESD Model Withstand Voltage (V) Class HBM FICDM 1000 1250 1C C3 ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. ΨJB is the junction to board thermal characterization parameter, measured in a JEDEC natural convection environment. ΨJT is the junction to package top thermal characterization parameter, measured in a JEDEC natural convection environment. analog.com Rev. G | 12 of 54 Data Sheet AD5592R PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 6. AD5592R 16-Ball WLCSP Pin Configuration Figure 8. AD5592R 16-Lead TSSOP Pin Configuration Figure 7. AD5592R 16-Lead LFCSP Pin Configuration Table 8. AD5592R Pin Function Descriptions Pin No. WLCSP LFCSP TSSOP Mnemonic Description A1 13 15 SDI A2 14 16 SCLK A3 15 1 RESET A4 16 2 SYNC B1 B2 12 11 14 13 GND I/O7 B3, C4, C3, C2, D1, D4, C1 B4 2, 3, 4, 5, 8, 9, 10 4, 5, 6, 7, 10, I/O0 to I/O6 11, 12 1 3 Data In. Logic input. Data that is to be written to the DACs and control registers is provided on this input and is clocked into the register on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum speed of 20 MHz when performing a conversion or clocking data from the AD5592R. Asynchronous Reset Pin. Tie this pin high for normal operation. When this pin is brought low, the AD5592R is reset to its default configuration. Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks. Ground Reference Point for All Circuitry on the AD5592R. Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output. The function of this pin is determined by programming the I/Ox pin configuration registers (see Table 11 and Table 12). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking place (see Table 22). Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs, or general-purpose digital inputs or outputs. The function of each pin is determined by programming the I/Ox pin configuration registers (see Table 11 and Table 12). Power Supply Input. The AD5592R operates from 2.7 V to 5.5 V, and this pin must be decoupled with a 0.1 µF capacitor to GND. analog.com VDD Rev. G | 13 of 54 Data Sheet AD5592R PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Table 8. AD5592R Pin Function Descriptions Pin No. WLCSP LFCSP TSSOP Mnemonic Description D2 7 9 SDO D3 6 8 VREF Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor information are provided on this output as a serial data stream. The bits are clocked out on the rising edge of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the SCLK can idle high or low, the next bit is clocked out on the first rising edge of SCLK that follows a falling edge SCLK while SYNC is low (see Figure 4). Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on this pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the AD5592R. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD. analog.com Rev. G | 14 of 54 Data Sheet AD5592R PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 9. AD5592R-1 16-Lead LFCSP Pin Configuration Figure 10. AD5592R-1 16-Ball WLCSP Pin Configuration Table 9. AD5592R-1 Pin Function Descriptions Pin No. LFCSP WLCSP Mnemonic Description 1 B4 VDD 2 to 5, 8 to 10 B3, C4, C3, C2, D1, D4, C1 I/O0 to I/O6 6 D3 VREF 7 D2 SDO 11 B2 I/O7 12 13 B1 A1 GND SDI 14 A2 SCLK 15 16 A3 A4 VLOGIC SYNC Power Supply Input. The AD5592R-1 operates from 2.7 V to 5.5 V, and this pin must be decoupled with a 0.1 µF capacitor to GND. Input/Output 0 Through Input/Output 6. These pins can be independently configured as DACs, ADCs, or general-purpose digital inputs or outputs. The function of each pin is determined by programming the I/Ox pin configuration registers (see Table 11 and Table 12). Reference Input/Output. When the internal reference is enabled, the 2.5 V reference voltage is available on this pin. A 0.1 µF capacitor connected from the VREF pin to GND is recommended to achieve the specified performance from the AD5592R-1. When the internal reference is disabled, an external reference must be applied to this pin. The voltage range for the external reference is 1 V to VDD. Data Out. Logic output. The conversion results from the ADC, register reads, and temperature sensor information are provided on this output as a serial data stream. The bits are clocked out on the rising edge of the SCLK input. The MSB is placed on the SDO pin on the falling edge of SYNC. Because the SCLK can idle high or low, the next bit is clocked out on the first rising edge of SCLK that follows a falling edge SCLK while SYNC is low (see Figure 4). Input/Output 7. This pin can be configured as a DAC, ADC, or general-purpose digital input or output. The function of this pin is determined by programming the I/Ox pin configuration registers (see Table 11 and Table 12). I/O7 can also be configured as a BUSY signal to indicate when an ADC conversion is taking place (see Table 22). Ground Reference Point for All Circuitry on the AD5592R-1. Data In. Logic input. Data to be written to the DACs and control registers is provided on this input and is clocked into the register on the falling edge of SCLK. Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 50 MHz when writing to the DACs. SCLK has a maximum speed of 20 MHz when performing a conversion or clocking data from the AD5592R-1. Interface Power Supply. The voltage of this pin ranges from 1.62 V to 5.5 V. Synchronization. Active low control input. SYNC is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 16 clocks. analog.com Rev. G | 15 of 54 Data Sheet AD5592R TYPICAL PERFORMANCE CHARACTERISTICS analog.com Figure 11. ADC INL, VDD = 5.5 V Figure 14. ADC DNL, VDD = 2.7 V Figure 12. ADC DNL, VDD = 5.5 V Figure 15. Histogram of ADC Codes, VDD = 2.7 V Figure 13. ADC INL, VDD = 2.7 V Figure 16. Histogram of ADC Codes, VDD = 5.5 V Rev. G | 16 of 54 Data Sheet AD5592R TYPICAL PERFORMANCE CHARACTERISTICS analog.com Figure 17. ADC Multiplying Bandwidth Figure 20. DAC Adjacent Code Glitch Figure 18. DAC INL Figure 21. DAC Digital-to-Analog Glitch (Rising) Figure 19. DAC DNL Figure 22. DAC Digital-to-Analog Glitch (Falling) Rev. G | 17 of 54 Data Sheet AD5592R TYPICAL PERFORMANCE CHARACTERISTICS Figure 23. DAC Settling Time (100 Code Change, Rising Edge) Figure 26. DAC Settling Time, Output Range = 0 V to 2 × VREF Figure 24. DAC Settling Time (100 Code Change, Falling Edge) Figure 27. DAC Settling Time for Various Capacitive Loads Figure 25. DAC Settling Time, Output Range = 0 V to VREF Figure 28. DAC Sine Wave Output, Output Range = 0 V to 2 × VREF, Bandwidth = 0 Hz to 20 kHz analog.com Rev. G | 18 of 54 Data Sheet AD5592R TYPICAL PERFORMANCE CHARACTERISTICS Figure 29. DAC Sine Wave Output, Output Range = 0 V to VREF, Bandwidth = 0 Hz to 20 kHz Figure 30. DAC 1/f Noise with External Reference Figure 31. DAC 1/f Noise with Internal Reference analog.com Figure 32. DAC Output Noise Spectral Density (NSD) Figure 33. DAC Output Sink and Source Capability, Output Range = 0 V to VREF Figure 34. DAC Output Sink and Source Capability, Output Range = 0 V to 2 × VREF Rev. G | 19 of 54 Data Sheet AD5592R TYPICAL PERFORMANCE CHARACTERISTICS Figure 35. Internal Reference 1/f Noise Figure 36. Reference Noise Spectral Density (NSD) Figure 37. Reference Line Regulation analog.com Rev. G | 20 of 54 Data Sheet AD5592R TERMINOLOGY ADC TERMINOLOGY Thus, for a 12-bit converter, SINAD is 74 dB. Integral Nonlinearity (INL) Total Harmonic Distortion (THD) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end-points of the transfer function are zero scale, a point that is 1 LSB below the first code transition, and full scale, a point that is 1 LSB above the last code transition. THD is the ratio of the rms sum of harmonics to the fundamental. For the AD5592R/AD5592R-1, it is defined as Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Offset Error Peak Harmonic or Spurious Noise (SFDR) Offset error is the deviation of the first code transition (00 … 000) to (00 … 001) from the ideal, that is, AGND + 1 LSB. Offset error match is the difference in offset error between any two channels. Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it is a noise peak. Gain Error DAC TERMINOLOGY Gain error is the deviation of the last code transition (111 … 110) to (111 … 111) from the ideal (that is, VREF − 1 LSB) after the offset error has been adjusted out. Relative Accuracy or Integral Nonlinearity (INL) Offset Error Match Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between channels. It is measured by applying a full-scale, 5 kHz sine wave signal to all non-selected ADC input channels and determining how much that signal is attenuated in the selected channel. This specification is the worst case across all ADC channels for the AD5592R/AD5592R-1. Track-and-Hold Acquisition Time The track-and-hold amplifier enters hold mode on the falling edge of SYNC and returns to track mode when the conversion is complete. The track-and-hold acquisition time is the minimum time required for the track-and-hold amplifier to remain in track mode for its output to reach and settle to within ±1 LSB of the applied input signal, given a step change to the input signal. Signal-to-Noise-and-Distortion (SINAD) Ratio SINAD is the measured ratio of signal-to-noise-and-distortion at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all non-fundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical SINAD ratio for an ideal N-bit converter with a sine wave input is given by SINAD (dB) = 6.02N + 1.76 analog.com (1) THD dB = 20 × log V22 + V32 + V42 + V52 + V62 V1 (2) For the DAC, relative accuracy or integral nonlinearity is a measurement of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A typical INL vs. code plot is shown in Figure 18. Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. A typical DNL vs. code plot can be seen in Figure 19. Zero Code Error Zero code error is a measurement of the output error when zero code (0x000) is loaded to the DAC register. Ideally, the output is 0 V. The zero code error is always positive in the AD5592R/ AD5592R-1 because the output of the DAC cannot go below 0 V due to a combination of the offset errors in the DAC and the output amplifier. Zero code error is expressed in mV. Gain Error Gain error is a measure of the span error of the DAC. It is the deviation in slope of the DAC transfer characteristic from the ideal expressed as % FSR. Offset Error Drift Offset error drift is a measurement of the change in offset error with a change in temperature. It is expressed in µV/°C. Rev. G | 21 of 54 Data Sheet AD5592R TERMINOLOGY Gain Temperature Coefficient Gain temperature coefficient is a measurement of the change in gain error with changes in temperature. It is expressed in ppm of FSR/°C. Offset Error Offset error is a measurement of the difference between VOUT (actual) and VOUT (ideal), expressed in mV, in the linear region of the transfer function. Offset error can be negative or positive. DC Power Supply Rejection Ratio (PSRR) PSRR indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for a full-scale output of the DAC. It is measured in mV/V. VREF is held at 2 V, and VDD is varied by ±10%. Output Voltage Settling Time Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾ full-scale input change and is measured from the rising edge of SYNC. Digital-to-Analog Glitch Impulse Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec, and is measured when the digital input code is changed by 1 LSB at the major carry transition (0x7FF to 0x800). Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-sec, and measured with a full-scale code change on the data bus, that is, from all 0s to all 1s and vice versa. Reference Feedthrough Reference feedthrough is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. Noise Spectral Density Noise spectral density is a measurement of the internally generated random noise. Random noise is characterized as a spectral density (nV/√Hz). It is measured by loading the DAC to midscale and measuring noise at the output. It is measured in nV/√Hz. DC Crosstalk DC crosstalk is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC (or soft power-down and power-up) while monitoring another DAC maintained at midscale. It is expressed in μV. analog.com DC crosstalk due to load current change is a measure of the impact that a change in load current on one DAC has to another DAC kept at midscale. It is expressed in μV/mA. Digital Crosstalk Digital crosstalk is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-sec. Analog Crosstalk Analog crosstalk is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa), then executing a software LDAC (see Table 21), and monitoring the output of the DAC whose digital code was not changed. The area of the glitch is expressed in nV-sec. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent analog output change of another DAC. It is measured by loading the attack channel with a full-scale code change (all 0s to all 1s and vice versa), using the write to and update commands while monitoring the output of the victim channel that is at midscale. The energy of the glitch is expressed in nV-sec. Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth; the multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. Voltage Reference Temperature Coefficient (TC) Voltage reference TC is a measure of the change in the reference output voltage with a change in temperature. The voltage reference TC is calculated using the box method, which defines the TC as the maximum change in the reference output over a given temperature range expressed in ppm/°C, as follows: TC = VREF MAX − VREF MIN VREF NOM × Temp Range × 106 (3) where: VREF(MAX) is the maximum reference output measured over the total temperature range. VREF(MIN) is the minimum reference output measured over the total temperature range. VREF(NOM) is the nominal reference output voltage, 2.5 V. Temp Range is the specified temperature range of −40°C to +125°C. Rev. G | 22 of 54 Data Sheet AD5592R THEORY OF OPERATION The AD5592R/AD5592R-1 are 8-channel configurable analog and digital input/output ports. The AD5592R/AD5592R-1 have eight pins that can be independently configured as a 12-bit DAC output channel, a 12-bit ADC input channel, a digital input pin, or a digital output pin. The function of each pin is determined by programming the ADC, DAC, or GPIO configuration registers as appropriate. See the Configuring the AD5592R/AD5592R-1 section and Table 12 for more information. DAC SECTION The AD5592R/AD5592R-1 contain eight 12-bit DACs and implement a segmented string DAC architecture with an internal output buffer. Figure 38 shows the internal block diagram of the DAC architecture. Figure 39. Simplified Resistor String Structure Output Buffer The output buffer is designed as an input/output rail-to-rail buffer. The output buffer can drive 2 nF capacitance with a 1 kΩ resistor in parallel. The slew rate is 1.25 V/µs with a ¼ to ¾ scale settling time of 6 µs. By default, the DAC outputs update directly after data has been written to the input register. The LDAC register is used to delay the updates until additional channels have been written to, if required. See the Readback and LDAC Mode Register section for more information. Figure 38. Internal Block Diagram of the DAC Architecture The DAC channels have a shared gain bit that sets the output range as 0 V to VREF or 0 V to 2 × VREF. Because the gain bit is shared by all channels, it is not possible to set different output ranges on a per channel basis. The input coding to the DAC is straight binary. The ideal output voltage is given by VOUT = G × VREF × D 2N DAC Output Range (4) where: D is the decimal equivalent of the binary code (0 to 4095) that is loaded to the DAC register. G = 1 for an output range of 0 V to VREF, or G = 2 for an output range of 0 V to 2 × VREF. N = 12. The DAC output voltage range can be configured to 0 V to VREF (gain = 1) or 0 V to 2 × VREF (gain = 2) using the DAC range bit of the general-purpose control register, as shown in Figure 40 and Figure 41, respectively. When VREF = VDD, the 0 V to 2 × VREF range does not allow the DAC to swing the output beyond VDD. Resistor String The simplified segmented resistor string DAC structure is shown in Figure 39. The code loaded to the DAC register determines the switch on the string that is connected to the output buffer. Because each resistance in the string has the same value, R, the string DAC is guaranteed monotonic. Figure 40. Output Voltage Range of the DAC with Gain = 1 (Unloaded Condition) analog.com Rev. G | 23 of 54 Data Sheet AD5592R THEORY OF OPERATION of the ADC is straight binary. It is possible to set each I/Ox pin as both a DAC and an ADC. When an I/Ox pin is set as both a DAC and an ADC, the primary function is that of the DAC. If the pin is selected for inclusion in an ADC conversion sequence, the voltage on the pin is converted and made available via the serial interface, allowing the DAC voltage to be monitored. Calculating ADC Input Current Figure 41. Output Voltage Range of the DAC with Gain = 2 (Unloaded Condition) When VREF = VDD for gain = 1 or VREF = 0.5 × VDD for gain = 2, there is an upper dead band of 10 mV at the DAC channel output in unloaded conditions. Additionally, there is a lower dead band of ~4.88 mV at the DAC channel output in unloaded conditions. When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the DAC channel. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV. ADC SECTION The 12-bit, single-supply ADC is capable of throughput rates of 400 kSPS. The ADC is preceded by a multiplexer that switches selected I/Ox pins to the ADC. A sequencer is included to automatically switch the multiplexer to the next selected channel. Channels are selected for conversion by writing to the ADC sequence register. When the write to the ADC sequence register has completed, the first channel in the conversion sequence is put into track mode. Allow each channel to track the input signal for a minimum of 500 ns. The first SYNC falling edge following the write to the ADC sequence register begins the conversion of the first channel in the sequence. The next SYNC falling edge starts a conversion on the second channel in the sequence and also begins to clock the first ADC result onto the serial interface. ADC data is clocked out of the AD5592R/AD5592R-1 in a 16-bit frame. Bit 15 is 0 to indicate that the data contains ADC data, Bits[14:12] are the binary representation of the ADC address, and Bits[11:0] represent the ADC result (see Table 30). Each conversion takes 2 µs, and the conversion must be completed before another conversion is initiated. Only write to the AD5592R/ AD5592R-1 when no conversion is taking place. I/O7 can be configured as a BUSY signal to indicate when a conversion is taking place. BUSY goes low while a conversion is in progress, and high when an ADC result is available. The ADC has an input range selection bit (Bit 5 in the General-Purpose Control Register section, Table 17), which sets the input range as 0 V to VREF or 0 V to 2 × VREF. All input channels share the same range. The output coding analog.com The current flowing into the I/Ox pins configured as ADC inputs vary with the sampling rate (fS), the voltage difference between successive channels (VDIFF), and whether buffered or unbuffered mode is used. Figure 42 shows a simplified version of the ADC input structure. When a new channel is selected for conversion, the 5.8 pF capacitor must be charged or discharged of the voltage that was on the previously selected channel. The time required by the charge or discharge depends on the voltage difference between the two channels. This affects the input impedance of the multiplexer and therefore the input current flowing into the I/Ox pins. In buffered mode, Switch S1 is open and Switch S2 is closed, in which case the U1 buffer is directly driving the 23.1 pF capacitor, and its charging time is negligible. In unbuffered mode, Switch S1 is closed and Switch S2 is closed. In unbuffered mode, the 23.1 pF capacitor must be charged from the I/Ox pins, which contributes to the input current. For applications where the ADC input current is too high, an external input buffer may be required. The choice of buffer is a function of the particular application. Calculate the input current for buffered mode as follows: fS × C × VDIFF + 1 nA where: fS is the ADC sample rate in Hertz. C is the sampling capacitance in Farads. VDIFF is the voltage change between successive channels. 1 nA is the dc leakage current associated with buffered mode. Calculate the input current for unbuffered mode as follows: fS × C × VDIFF An example solution is as follows: for the ADC input current in buffered mode, where I/O0 = 0.5 V, I/O1 = 2 V, and fS = 10 kHz, (10,000 × 5.8 × 10−12 × 1.5) + 1 nA = 88 nA Under the same conditions, the ADC input current in unbuffered mode is as follows: (10,000 × 28.9 × 10−12 × 1.5) = 433.5 nA Figure 42. ADC Input Structure Rev. G | 24 of 54 Data Sheet AD5592R THEORY OF OPERATION GPIO SECTION Each of the eight I/Ox pins can be configured as a general-purpose digital input pin by programming the GPIO read configuration register (see the GPIO Read Configuration Register section) or as a digital output pin by programming the GPIO write configuration register (see the GPIO Write Configuration Register section). When an I/Ox pin is configured as an output, the pin can be set high or low by programming the GPIO write data register (see the GPIO Write Data Register section). Logic levels for general-purpose outputs are relative to VDD and GND. When an I/Ox pin is configured as an input, its status can be determined by setting Bit 10 in the GPIO read configuration register. The next SPI operation clocks out the state of the GPIO pins. When an I/Ox pin is set as an output, it is possible to read its status by also setting it as an input pin. When reading the status of the I/Ox pins set as inputs, the status of an I/Ox pin set as both an input and output pin is also returned. INTERNAL REFERENCE that this result is not confused with the readback from the DAC0 channel. The temperature conversion takes 5 µs with the ADC buffer enabled and 20 µs when the buffer is disabled. Calculate the temperature by using the following formulae: For ADC gain = 1, Temperature (°C) = 25 + For ADC gain = 2, ADC Code − 0.5 / VREF × 4095 2.654 × 2.5 / VREF Temperature (°C) = 25 + ADC Code − 0.5 / 2 × VREF 1.327 × 2.5 / VREF × 4095 The range of codes returned by the ADC when reading from the temperature indicator is approximately 645 to 1084 (for ADC gain = 1), corresponding to a temperature between −40°C (TA) and +125°C (TJ). The accuracy of the temperature indicator, averaged over five samples, is typically 3°C. The AD5592R/AD5592R-1 contain an on-chip 2.5 V reference. The reference is powered down by default and is enabled by setting Bit 9 in the power-down/reference control register (see the Power-Down/Reference Control Register section). When the on-chip reference is powered up, the reference voltage appears on the VREF pin and may be used as a reference source for other components. When the internal reference is used, it is recommended to decouple the internal reference to GND using a 100 nF capacitor. It is recommended that the internal reference be buffered before using it elsewhere in the system. When the reference is powered down, an external reference must be connected to the VREF pin. Suitable external reference sources for the AD5592R/AD5592R-1 include the AD780, AD1582, ADR431, REF193, and ADR391. RESET FUNCTION The AD5592R has an asynchronous RESET pin. For normal operation, RESET is tied high. A falling edge on RESET resets all registers to their default values and reconfigures the I/Ox pins to their default values (85 kΩ pull-down to GND). The reset function takes 250 µs maximum; do not write new data to the AD5592R during this time. The AD5592R has a software reset that performs the same function as the RESET pin. The reset function is activated by writing 0x5AC to the software reset register (see the Software Reset Register section). TEMPERATURE INDICATOR The AD5592R/AD5592R-1 contain an integrated temperature indicator, which can be read to provide an estimation of the die temperature. The temperature reading can be used in fault detection where a sudden rise in die temperature may indicate a fault condition such as a shorted output. Temperature readback is enabled by setting Bit 8 in the ADC sequence register (see the ADC Sequence Register section) to 1. The temperature result is then added to the ADC sequence. The temperature result has an address of 0b1000 (see the Temperature Reading Format section, Table 31); take care analog.com Rev. G | 25 of 54 Data Sheet AD5592R SERIAL INTERFACE The AD5592R/AD5592R-1 have a serial interface (SYNC, SCLK, SDI, and SDO), which is compatible with SPI standards, as well as with most DSPs. The input shift register is 16 bits wide (see Table 10). The MSB (Bit 15) determines what type of write function is required. When Bit 15 is 0, a write to the control register is selected. The control register address is selected by Bits[14:11]. Bits[10:9] are reserved and are 0s. Bits[8:0] set the data that is written to the selected control register. When Bit 15 is 1, data is written to a DAC channel (assuming that channel has been set to be a DAC). Bits[14:12] select which DAC is addressed. Bits[11:0] are the 12-bit data loaded to the selected DAC, with Bit 11 being the MSB of the DAC data. Table 13 shows the control register map for the AD5592R/AD5592R-1. The register map allows the operation of each of the I/Ox pins to be configured. ADCs can be selected for inclusion in sampling sequences. DACs can be updated individually or simultaneously (see the LDAC Mode Operation section). GPIO settings are also controlled via the register map. Table 10. Input Shift Register Format MSB 15 0 1 analog.com 14 13 LSB 12 Control register address DAC address 11 10 9 0 0 8 7 6 5 4 3 2 1 0 Control register data 12-bit DAC data Rev. G | 26 of 54 Data Sheet AD5592R SERIAL INTERFACE have the additional option of being configured as push/pull or opendrain. The input/output channels are configured by writing to the appropriate configuration registers, as shown in Table 11 and Table 12 (see the Register Map section). To assign a particular function to an input/output channel, the user writes to the appropriate register and sets the corresponding bit to 1. For example, setting Bit 0 in the DAC configuration register to 1 configures I/O0 as a DAC (see Table 19). See the Register Map section for details. POWER-UP TIME When power is applied to the AD5592R/AD5592R-1, the power-on reset block begins to configure the device and to load the registers with their default values. The configuration process takes 250 µs; do not write to any of the registers during this time. WRITE MODE Figure 4 shows the read and write timing for the AD5592R/ AD5592R-1. A write sequence begins by bringing the SYNC line low. Data on SDI is clocked into the 16-bit shift register on the falling edge of SCLK. After the 16th falling clock edge, the last data bit is clocked in. SYNC is brought high, and the programmed function is executed (that is, a change in a DAC input register or a change in a control register). SYNC must be brought high for a minimum of 20 ns before the next write. All interface pins must be operated close to the VDD or VLOGIC rails to minimize power consumption in the digital input buffers. In the event that the bit for an input/output channel is set in multiple configuration registers, the input/output channel takes the function dictated by the last write operation. The exceptions to this rule are that an I/Ox pin can be set as both a DAC and an ADC or as a digital input and output. When an I/Ox pin is configured as a DAC and ADC, its primary function is as a DAC, and the ADC can measure the voltage being provided by the DAC. This feature can monitor the output voltage to detect short circuits or overload conditions. When a pin is configured as both a general-purpose input and output, the primary function is as an output pin. This configuration allows the status of the output pin to be determined by reading the GPIO register. Figure 43 shows a typical configuration example where I/O0 and I/O1 are configured as ADCs, I/O2 and I/O3 are configured as DACs, I/O4 is a general-purpose output pin, I/O5 is a general-purpose input pin, and I/O6 and I/O7 are three-state. READ MODE The AD5592R/AD5592R-1 allow data readback from the ADCs and control registers via the serial interface. ADC conversions are automatically clocked out on the serial interface as part of a sequence or as a single ADC conversion. Reading from a register first requires a write to the readback and LDAC mode register to select the register to read back. The contents of the selected register are clocked out on the next 16 SCLKs following a falling edge of SYNC. Note that due to timing requirements of t10 (25 ns), the maximum speed of the SPI interface during a read operation must not exceed 20 MHz. The general-purpose control register (see the General-Purpose Control Register section) also contains other functions associated with the DAC and ADC, such as the lock configuration bit. When the lock configuration (IO_LOCK) bit is set to 1, any writes to the pin configuration registers are ignored, thus preventing the function of the I/Ox pins from being changed. During the ADC conversion cycle, only the ADC conversion result and the temperature reading results can be read back and all other read requests are ignored. The I/Ox pins can be reconfigured at any time when the AD5592R/ AD5592R-1 is in an idle state, that is, no ADC conversions are taking place and no registers are being read back. The lock configuration bit must also be 0. CONFIGURING THE AD5592R/AD5592R-1 The AD5592R/AD5592R-1 I/Ox pins are configured by writing to a series of configuration registers. The control registers are accessed when the MSB of a serial write is 0, as shown in Table 10. The control register map for the AD5592R/AD5592R-1 is shown in Table 13. At power-up, the I/Ox pins are configured as 85 kΩ pull-down resistors connected to GND. The input/output channels of the AD5592R/AD5592R-1 can be configured to operate as DAC outputs, ADC inputs, digital outputs, digital inputs, three-state, or connected to GND with 85 kΩ pulldown resistors. When configured as digital outputs, the I/Ox pins Figure 43. Typical Configuration Example Table 11. I/Ox Pin Configuration Registers MSB 15 14 0 analog.com 13 12 Register address LSB 11 10 9 Reserved 8 7 6 5 4 3 2 1 0 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 Rev. G | 27 of 54 Data Sheet AD5592R SERIAL INTERFACE Table 12. Bit Descriptions for the I/Ox Pin Configuration Registers Bit(s) Bit Name Description 15 [14:11] MSB Register address [10:8] [7:0] Reserved IO7 to IO0 Set this bit to 0. Selects which pin configuration register is addressed. 0100: ADC pin configuration. 0101: DAC pin configuration. 0110: pull-down configuration (default condition at power-up). 1000: GPIO write configuration. 1010: GPIO read configuration. 1100: GPIO open-drain configuration. 1101: three-state configuration. Reserved. Set these bits to 0. Enable register function on selected I/Ox pin. 0: no function selected. 1: set the selected I/Ox pin to the register function. analog.com Rev. G | 28 of 54 Data Sheet AD5592R SERIAL INTERFACE GENERAL-PURPOSE CONTROL REGISTER The general-purpose control register (see the General-Purpose Control Register section) enables or disables certain functions associated with the DAC, ADC, and I/Ox pin configuration (see Table 17). The general-purpose control register sets the gain of the DAC and ADC. Bit 5 sets the input range for the ADC, and Bit 4 sets the output range of the DAC. midscale. The input data is then read back. Bits[14:12] contain the address of the DAC register being read back, and Bit 15 is 1 (see Table 32). The general-purpose control register also enables/disables the ADC buffer and precharge function (see the ADC Section section for more details). The register can also be used to lock the I/Ox pin configuration to prevent accidental change. When Bit 7 (IO_LOCK bit) is set to 1, writes to the configuration registers are ignored. DAC WRITE OPERATION To set a pin as a DAC, set the appropriate bit in the DAC pin configuration register to 1 (see Table 19). For example, setting Bit 0 to 1 enables I/O0 as a DAC output. Data is written to a DAC when the MSB (Bit 15) of the serial write is 1. Bits[14:12] determine which DAC is addressed, and Bits[11:0] contain the 12-bit data to be written to the DAC, as shown in Table 29. Data is written to the selected DAC input register. Data written to the input register can be automatically copied to the DAC register, if required. Data is transferred to the DAC register based on the setting of the LDAC mode register (see Table 21). LDAC Mode Operation When the LDAC mode bits (Bits[1:0]) are 00 respectively, new data is automatically transferred from the input register to the DAC register, and the analog output updates. When the LDAC mode bits are 01, data remains in the input register. This LDAC mode allows writes to input registers without affecting the analog outputs. When the input registers have been loaded with the desired values, setting the LDAC mode bits to 10 transfers the values in the input registers to the DAC registers, and the analog outputs update simultaneously. The LDAC mode bits then revert back to 01, assuming their previous setting was 01 (see Table 21). DAC READBACK The input register of each DAC can be read back via the SPI interface. Reading back the DAC register value can be used to confirm that the data was received correctly before writing to the LDAC register, or to check what value was last loaded to a DAC. Data can only be read back from a DAC when there is no ADC conversion sequence taking place. To read back a DAC input register, it is first necessary to enable the readback function and select which DAC register is required. This is achieved by writing to the DAC read back register (see Table 15). Set the Bits[4:3] to 11 to enable the readback function. Bits[2:0] select which DAC data is required. The DAC data is clocked out of the AD5592R/AD5592R-1 on the subsequent SPI operation. Figure 44 shows an example of setting I/O3, configured as a DAC, to analog.com Figure 44. DAC Readback Operation ADC OPERATION To set a pin as an ADC, set the appropriate bit in the ADC pin configuration register to 1 (see Table 18). For example, setting Bit 0 to 1 enables I/O0 as an ADC input. The ADC channels of the AD5592R/AD5592R-1 operate as a traditional multichannel ADC, where each serial transfer selects the next channel for conversion. Writing to the ADC sequence register (see the ADC Sequence Register section and Table 16) selects the ADC channels to be included in the sequence, and the REP bit determines if the sequence is repeated. The SYNC signal is used to frame the write to the converter on the SDI pin. The data that appears on the SDO pin during the initial write to the ADC sequence register is invalid. When the sequence register is written to, the ADC begins to track the first channel in the sequence. Tracking takes 500 ns; do not initiate a conversion until this time has passed. The next SYNC falling edge initiates a conversion on the selected channel. The subsequent SYNC falling edge begins clocking out the ADC result and also initiates the next conversion. The ADC operates with one cycle latency. Thus, the conversion result corresponding to each conversion is available one serial read cycle after the cycle in which the conversion was initiated. Note that for a valid ADC conversion, the first falling edge of SCLK must occur within the time t4 (mentioned in Table 3 and Table 4) after every falling edge of SYNC (see Figure 5). If more than one channel is selected in the ADC sequence register, the ADC converts all selected channels sequentially in ascending order on successive SYNC falling edges. Once all the selected channels in the sequence register are converted, the ADC repeats the sequence if the REP bit is set. If the REP bit is clear, the ADC goes three-state. Figure 45 to Figure 48 show typical ADC modes of operation. I/O7 can be configured as a BUSY output pin to indicate when a conversion result is available. BUSY goes low while a conversion takes place and goes high when the conversion result is available. The conversion result is clocked out on the SDO pin on the following read/write operation. For an ADC conversion, Bit 15 is 0, Bits[14:12] contain the ADC address, and Bits[11:0] contain the Rev. G | 29 of 54 Data Sheet AD5592R SERIAL INTERFACE 12-bit conversion result, as shown in the ADC Conversion Result Format section, Table 30. Figure 45. Single-Channel ADC Conversion Sequence, No Repeat Figure 46. Single-Channel, Repeating, ADC Conversion Sequence Figure 47. Multichannel ADC Conversion Sequence, No Repeat Figure 48. Multichannel, Repeating, ADC Conversion Sequence analog.com Rev. G | 30 of 54 Data Sheet AD5592R SERIAL INTERFACE Changing an ADC Sequence The channels included in an ADC sequence can be changed by first stopping an existing conversion sequence (see Figure 49). The ADC conversion sequence is stopped by clearing the REP, TEMP, and ADC7 to ADC0 bits in the ADC sequence register (see the ADC Sequence Register section) to 0. As the command to stop the sequence is written, an ADC conversion is also taking place. This conversion must finish before a new sequence can be written to the ADC sequence register. Allow a minimum of 2 µs between starting the write to end the current sequence and starting the write to select a new sequence. After selecting the new sequence, allow an ADC track time of 500 ns before initiating the next conversion. Figure 49. Changing a Multichannel, Repeating, ADC Conversion Sequence analog.com Rev. G | 31 of 54 Data Sheet AD5592R SERIAL INTERFACE ADC Conversion Result For every selected channel in the ADC sequencer, the ADC conversion result is clocked out on SDO in the format given in Table 30. The ADC channel address is provided along with the 12-bit ADC data for every valid ADC conversion result. Use the ADC channel address while assigning the ADC data for further processing. GPIO OPERATION Each of the I/Ox pins of the AD5592R/AD5592R-1 can operate as a general-purpose, digital input or output pin. The function of the pins is determined by writing to the appropriate bit in the GPIO read configuration register (see the GPIO Read Configuration Register section) and the GPIO write configuration register (see the GPIO Write Configuration Register section). Setting Pins as Outputs To set a pin as a general-purpose output, set the appropriate bit in the GPIO write configuration register to 1 (see Table 22). For example, setting Bit 0 to 1 enables I/O0 as a general-purpose output. The state of the output pin is controlled by setting or clearing the bits in the GPIO write data register (see the GPIO Write Data Register section and Table 23). A data bit is ignored if it is written to a location that is not configured as an output. The outputs can be independently configured as push/pull or opendrain outputs. When in a push/pull configuration, the output is driven to VDD or GND, as determined by the data in the GPIO write data register. To set a pin as an open-drain output, set the appropriate bit in the GPIO open-drain configuration register to 1 (see the GPIO Open-Drain Configuration Register section and Table 26). When in an open-drain configuration, the output is driven to GND when a data bit in the GPIO write data register sets the pin low. When the pin is set high, the output is not driven and must be pulled high by an external resistor. Open-drain configuration allows for multiple output pins to be tied together. If all the pins are normally high, the open-drain configuration allows for one pin to pull down the others pins. This method is commonly used where multiple pins are used to trigger an alarm or an interrupt pin. To change the state of the I/Ox pins, a write to the GPIO write data register (see the GPIO Write Data Register section) is required. Setting a bit to 1 gives a Logic 1 on the selected output. Clearing a bit to 0 gives a Logic 0 on the selected output. Setting Pins as Inputs To set a pin as a general-purpose input, set the appropriate bit in the GPIO read configuration register to 1 (see the GPIO Read Configuration Register section and Table 24). For example, setting Bit 0 to 1 enables I/O0 as a general-purpose input. To read the state of the general-purpose inputs, write to the GPIO read configuration register to set Bit 10 to 1 and also any of Bits[7:0] that correspond to a general-purpose input pin. The following SPI operation clocks out the state of any pins set as general-purpose inputs. Figure 50 shows an example where I/O4 to I/O7 are set as general-purpose inputs. I/O3 is assumed to be a DAC. To read the status of I/O7 to I/O4, Bit 10 and Bits[7:4] are set to 1. To read the status of I/O5 and I/O4, only Bit 10, Bit 5, and Bit 4 need to be set to 1. The status of I/O7 and I/O6 are not read, and Bits[7:6] are read as 0. Figure 50 also has a write to a DAC to show that other operations can be included when reading the status of the general-purpose pins. Figure 50. Configuring and Reading General-Purpose Input Pins analog.com Rev. G | 32 of 54 Data Sheet AD5592R SERIAL INTERFACE THREE-STATE PINS The I/Ox pins can be set to three-state by writing to the three-state configuration register, as shown in the Three-State Configuration Register section and Table 27. register. See the LDAC Mode Operation section for details of the LDAC mode function. 85 KΩ PULL-DOWN RESISTOR PINS The I/Ox pins can be connected to GND via a pull-down resistor (85 kΩ) by setting the appropriate bits in the pull-down configuration register, as shown in the Pull-Down Configuration Register section and Table 20. POWER-DOWN MODE The AD5592R/AD5592R-1 have a power configuration register to reduce the power consumption when certain functions are not needed. The power-down register allows any channels set as DACs to be individually placed in a power-down state. When in a power-down state, the DAC outputs are three-state. When a DAC channel is put back into normal mode, the DAC output returns to its previous value. The internal reference and its buffer are powered down by default and are enabled by setting the EN_REF bit in the power-down register. The internal reference voltage then appears at the VREF pin. There is no dedicated power-down function for the ADC, but the ADC is automatically powered down if none of the I/Ox pins are selected as ADCs. The PD_ALL bit powers down all the DACs, the reference and its buffer, and the ADC simultaneously. The PowerDown/Reference Control Register section shows the power-down register. RESET FUNCTION The AD5592R/AD5592R-1 can be reset to their default conditions by writing to the software reset register, as shown in the Software Reset Register section and Table 28. This write resets all registers to their default values and reconfigures the I/Ox pins to their default values (85 kΩ pull-down resistor to GND). The reset function takes 250 µs maximum; do not write new data to the AD5592R/ AD5592R-1 during this time. The AD5592R has a RESET pin that performs the same function. For normal operation, RESET is tied high. A falling edge on RESET triggers the reset function. READBACK AND LDAC MODE REGISTER The values contained in the AD5592R/AD5592R-1 registers can be read back to ensure that the registers are correctly set up. The register readback is initiated by writing to the configuration register readback and LDAC mode register (see the Configuration Register Readback and LDAC Mode Register section and Table 21) with Bit 6 set to 1. Bits[5:2] select which register is to be read back. The register data is clocked out of the AD5592R/AD5592R-1 on the next SPI transfer. Bits[1:0] of the configuration register readback and LDAC mode register select the LDAC mode. The LDAC mode determines if data written to a DAC input register is also transferred to the DAC analog.com Rev. G | 33 of 54 Data Sheet AD5592R APPLICATIONS INFORMATION MICROPROCESSOR INTERFACING Microprocessor interfacing to the AD5592R/AD5592R-1 is via a serial bus that uses a standard protocol compatible with DSPs and microcontrollers. The communications channel requires a 4-wire interface consisting of a clock signal, a data input signal, a data output signal, and a synchronization signal. The devices require a 16-bit data-word with data valid on the falling edge of SCLK. can also be used. This method is the same as when using the ADSP-BF531. AD5592R/AD5592R-1 TO SPI INTERFACE The SPI interface of the AD5592R/AD5592R-1 is designed to be easily connected to industry-standard DSPs and microcontrollers. Figure 51 shows the AD5592R/AD5592R-1 connected to the Analog Devices, Inc., ADSP-BF531 Blackfin® DSP. The Blackfin has an integrated SPI port that can be connected directly to the SPI pins of the AD5592R/AD5592R-1. Figure 52. ADSP-BF527 SPORT Interface LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board (PCB) on which the AD5592R or the AD5592R-1 is mounted must be designed so that the AD5592R/AD5592R-1 lie on the analog plane. Figure 51. ADSP-BF531 SPI Interface AD5592R/AD5592R-1 TO SPORT INTERFACE The Analog Devices ADSP-BF527 has two serial ports (SPORT). Figure 52 shows how a SPORT interface can be used to control the AD5592R/AD5592R-1. The ADSP-BF527 has an SPI port that analog.com The AD5592R/AD5592R-1 must have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor must have low effective series resistance (ESR) and low effective series inductance (ESI). Ceramic capacitors, for example, provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Rev. G | 34 of 54 Data Sheet AD5592R REGISTER MAP The AD5592R/AD5592R-1 has programmable user configuration The Data Format Details: AD5592R/AD5592R-1 ADC and DAC registers that are used to configure the device. Table 13 shows a Readback section provides data formats for the ADC and the DAC complete list of the user configuration registers. See the Register readback. Details: AD5592R/AD5592R-1 Control Register Map section for details about the functions of each of the bits. REGISTER SUMMARY: AD5592R/AD5592R-1 CONTROL REGISTER MAP Table 13. AD5592R/AD5592R-1 Control Register Summary MSB Bit 15 Address Bits[14:11] Register Name Register Description 0 0000 NOP NOP. No operation. 0x000 0 0001 DAC_RD DAC Readback Register. Selects and enables DAC readback. 0x000 0 0001 ADC_SEQ ADC Sequence Register. Selects ADCs for conversion. 0x000 0 0011 GEN_CTRL_REG General-Purpose Control Register. DAC and ADC control register. 0x000 0 0100 ADC_CONFIG ADC Pin Configuration Register. Selects which pins are ADC inputs. 0x000 0 0101 DAC_CONFIG DAC Pin Configuration Register. Selects which pins are DAC outputs. 0x000 0 0110 PULLDWN_CONFIG Pull-Down Configuration Register. Selects which pins have a 85 kΩ pull-down resistor to GND. 0x0FF 0 0111 CONFIG_READ_AND_LDAC Configuration Register readback and LDAC Mode Register. Selects the operation of the Load DAC (LDAC) function and/or which configuration register is read back. 0x000 0 1000 GPIO_CONFIG1 GPIO Write Configuration Register. Selects which pins are general-purpose outputs. 0x000 0 1001 GPIO_OUTPUT GPIO Write Data Register. Writes data to the general-purpose outputs. 0x000 0 1010 GPIO_INPUT GPIO Read Configuration Register. Selects which pins are general-purpose inputs 0x000 0 1011 PD_REF_CTRL Power-Down/Reference Control Register. Powers down DACs and enables/disables the reference. 0x000 0 1100 GPIO_OPENDRAIN_CONFIG GPIO Open-Drain Configuration Register. Selects open-drain or push/pull for general-purpose outputs. 0x000 0 1101 IO_TS_CONFIG Three-State Configuration Register. Selects which pins are three-state. 0x000 0 1111 SW_RESET Software Reset. Resets the AD5592R/AD5592R-1. 0x000 1 XXX2 DAC_WR DAC Write. Writes to addressed DAC register. 0x000 1 This register is also used to set I/O7 as a BUSY output. 2 Bits[14:12] represent the DAC register address. Default Value Bits[10:0] REGISTER DETAILS: AD5592R/AD5592R-1 CONTROL REGISTER MAP analog.com Rev. G | 35 of 54 Data Sheet AD5592R REGISTER MAP NOP Register Name: NOP No operation. Table 14. Bit Descriptions for NOP Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. 0x0 [10:0] NOP No operation. 0x0 DAC Readback Register Name: DAC_RD Selects and enables DAC readback. Table 15. Bit Descriptions for DAC_RD Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b0001. 0x1 [10:5] RESERVED Reserved. Set this bit to 0. 0x0 [4:3] DAC_RD_EN Enable readback of the DAC input register. 0x0 0: DAC register readback disabled. 1: DAC register readback enabled. [2:0] DAC_CH_SEL Select DAC channel. 0x0 000: DAC0. 001: DAC1. 010: DAC2. 011: DAC3. 100: DAC4. 101: DAC5. 110: DAC6. 111: DAC7. analog.com Rev. G | 36 of 54 Data Sheet AD5592R REGISTER MAP ADC Sequence Register Name: ADC_SEQ Selects ADCs for conversion. Table 16. Bit Descriptions for ADC_SEQ Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b0010. 0x2 10 RESERVED Reserved. Set this bit to 0. 0x0 9 REP ADC sequence repetition. 0x0 0: Sequence repetition disabled. 1: Sequence repetition enabled. 8 TEMP Include temperature indicator in ADC sequence. 0x0 0: Disable temperature indicator readback. 1: Enable temperature indicator readback. 7 ADC7 Include the ADC7 channel in conversion sequence. 0x0 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. 6 ADC6 Include the ADC6 channel in conversion sequence. 0x0 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. 5 ADC5 Include the ADC5 channel in conversion sequence. 0x0 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. 4 ADC4 Include the ADC4 channel in conversion sequence. 0x0 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. 3 ADC3 Include the ADC3 channel in conversion sequence. 0x0 0: The selected ADC channel is not included in the conversion sequence. analog.com Rev. G | 37 of 54 Data Sheet AD5592R REGISTER MAP Table 16. Bit Descriptions for ADC_SEQ Bits Bit Name Description Default Value 1: Include the selected ADC channel in the conversion sequence. 2 ADC2 Include the ADC2 channel in conversion sequence. 0x0 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. 1 ADC1 Include the ADC1 channel in conversion sequence. 0x0 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. 0 ADC0 Include the ADC0 channel in conversion sequence. 0x0 0: The selected ADC channel is not included in the conversion sequence. 1: Include the selected ADC channel in the conversion sequence. General-Purpose Control Register Name: GEN_CTRL_REG DAC and ADC control register. Table 17. Bit Descriptions for GEN_CTRL_REG Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b0011. 0x3 10 RESERVED Reserved. Set this bit to 0. 0x0 9 ADC_BUF_PRECH ADC buffer precharge. 0x0 0: ADC buffer is not used to precharge the ADC. If the ADC buffer is enabled, it is always powered up. 1: ADC buffer is used to precharge the ADC. If the ADC buffer is enabled, it is powered up while the conversion takes place and then powered down until the next conversion takes place. 8 ADC_BUF_EN ADC buffer enable. 0x0 0: ADC buffer is disabled. 1: ADC buffer is enabled. 7 IO_LOCK Lock configuration. 0x0 0: The contents of the I/Ox pin configuration register can be changed. 1: The contents of the I/Ox pin configuration register cannot be changed. 6 ALL_DAC Write all DACs. 0x0 0: For future DAC writes, the DAC address bits determine which DAC is written to. analog.com Rev. G | 38 of 54 Data Sheet AD5592R REGISTER MAP Table 17. Bit Descriptions for GEN_CTRL_REG Bits Bit Name Description Default Value 1: For future DAC writes, the DAC address bits are ignored, and all channels configured as DACs are updated with the same data. 5 ADC_RANGE ADC input range select. 0x0 0: ADC gain is 0 V to VREF. 1: ADC gain is 0 V to 2 × VREF. 4 DAC_RANGE DAC output range select. 0x0 0: DAC output range is 0 V to VREF. 1: DAC output range is 0 V to 2 × VREF. [3:0] RESERVED Reserved. Set these bits to 0b0000. 0x0 ADC Pin Configuration Register Name: ADC_CONFIG Selects which pins are ADC inputs. Table 18. Bit Descriptions for ADC_CONFIG Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b0100. 0x4 [10:8] RESERVED Reserved. Set these bits to 0b000. 0x0 7 ADC7 Select the I/O7 pin as ADC input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 6 ADC6 Select the I/O6 pin as ADC input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 5 ADC5 Select the I/O5 pin as ADC input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 4 ADC4 Select the I/O4 pin as ADC input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 3 ADC3 analog.com Select the I/O3 pin as ADC input. 0x0 Rev. G | 39 of 54 Data Sheet AD5592R REGISTER MAP Table 18. Bit Descriptions for ADC_CONFIG Bits Bit Name Description Default Value 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 2 ADC2 Select the I/O2 pin as ADC input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 1 ADC1 Select the I/O1 pin as ADC input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. 0 ADC0 Select the I/O0 pin as ADC input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is an ADC input. DAC Pin Configuration Register Name: DAC_CONFIG Selects which pins are DAC outputs. Table 19. Bit Descriptions for DAC_CONFIG Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b0101. 0x5 [10:8] RESERVED Reserved. Set these bits to 0b000. 0x0 7 DAC7 Select the I/O7 pin as DAC output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 6 DAC6 Select the I/O6 pin as DAC output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 5 DAC5 Select the I/O5 pin as DAC output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 4 DAC4 analog.com Select the I/O4 pin as DAC output. 0x0 Rev. G | 40 of 54 Data Sheet AD5592R REGISTER MAP Table 19. Bit Descriptions for DAC_CONFIG Bits Bit Name Description Default Value 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 3 DAC3 Select the I/O3 pin as DAC output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 2 DAC2 Select the I/O2 pin as DAC output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 1 DAC1 Select the I/O1 pin as DAC output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. 0 DAC0 Select the I/O0 pin as DAC output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a DAC output. Pull-Down Configuration Register Name: PULLDWN_CONFIG Selects which pins have a 85 kΩ pull-down resistor to GND. Table 20. Bit Descriptions for PULLDWN_CONFIG Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b0110. 0x6 [10:8] RESERVED Reserved. Set these bits to 0b000. 0x0 7 PULL_DWN_7 Set the I/O7 pin as weak pull-down output. 0x1 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 6 PULL_DWN_6 Set the I/O6 pin as weak pull-down output. 0x1 0: The I/O pin function is determined by the pin configuration registers. analog.com Rev. G | 41 of 54 Data Sheet AD5592R REGISTER MAP Table 20. Bit Descriptions for PULLDWN_CONFIG Bits Bit Name Description Default Value 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 5 PULL_DWN_5 Set the I/O5 pin as weak pull-down output. 0x1 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 4 PULL_DWN_4 Set the I/O4 pin as weak pull-down output. 0x1 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 3 PULL_DWN_3 Set the I/O3 pin as weak pull-down output. 0x1 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 2 PULL_DWN_2 Set the I/O2 pin as weak pull-down output. 0x1 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 1 PULL_DWN_1 Set the I/O1 pin as weak pull-down output. 0x1 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. 0 PULL_DWN_0 Set the I/O0 pin as weak pull-down output. 0x1 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is connected to GND via an 85 kΩ pull-down resistor. Configuration Register Readback and LDAC Mode Register Name: CONFIG_READ_AND_LDAC Selects the operation of the Load DAC (LDAC) function and/or which configuration register is read back. Table 21. Bit Descriptions for CONFIG_READ_AND_LDAC Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b0111. 0x7 [10:7] RESERVED Reserved. Set these bits to 0b0000. 0x0 6 REG_RD_EN Enable Configuration Register readback. Note that the LDAC mode bits are always used regardless of the REG_RD_EN bit. 0x0 0: No readback is initiated. analog.com Rev. G | 42 of 54 Data Sheet AD5592R REGISTER MAP Table 21. Bit Descriptions for CONFIG_READ_AND_LDAC Bits Bit Name Description Default Value 1: REG_RD bits select which register is read back. REG_RD_EN automatically clears when the read is complete. [5:2] REG_RD If REG_RD_EN bit is 1, REG_RD bits determine which register is to be read back. 0x0 0000: NOP. 0001: DAC readback. 0010: ADC sequence. 0011: General-purpose configuration. 0100: ADC pin configuration. 0101: DAC pin configuration. 0110: Pull-down configuration. 0111: LDAC configuration. 1000: GPIO write configuration. 1001: GPIO write data. 1010: GPIO read configuration. 1011: Power-down and reference control. 1100: Open-drain configuration. 1101: Three-state pin configuration. 1111: Software reset. [1:0] LDAC_MODE Determines how data written to an input register of a DAC is handled. 0x0 00: Data written to an input register is immediately copied to a DAC register, and the DAC output updates. 01: Data written to an input register is not copied to a DAC register. The DAC output is not updated. 10: Data in the input registers is copied to the corresponding DAC registers. When the data has been transferred, the DAC outputs are updated simultaneously. GPIO Write Configuration Register Name: GPIO_CONFIG Selects which pins are general-purpose outputs. This register is used to set I/O7 as a BUSY output. Table 22. Bit Descriptions for GPIO_CONFIG Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 analog.com Rev. G | 43 of 54 Data Sheet AD5592R REGISTER MAP Table 22. Bit Descriptions for GPIO_CONFIG Bits Bit Name Description Default Value [14:11] REG_ADDR Register address. Set these bits to 0b1000. 0x8 [10:9] RESERVED Reserved. Set these bits to 0b00. 0x0 8 EN_BUSY Enable the I/O7 pin as BUSY. 0x0 0: I/O7 is not configured as BUSY. 1: I/O7 pin is configured as BUSY. GPIO7 must be set to 1 to enable the I/O7 pin as an output. 7 GPIO7 Select the I/O7 pin as GPIO output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 6 GPIO6 Select the I/O6 pin as GPIO output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 5 GPIO5 Select the I/O5 pin as GPIO output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 4 GPIO4 Select the I/O4 pin as GPIO output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 3 GPIO3 Select the I/O3 pin as GPIO output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 2 GPIO2 Select the I/O2 pin as GPIO output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 1 GPIO1 Select the I/O1 pin as GPIO output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. 0 GPIO0 Select the I/O0 pin as GPIO output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose output pin. GPIO Write Data Register Name: GPIO_OUTPUT Writes data to the general-purpose outputs. analog.com Rev. G | 44 of 54 Data Sheet AD5592R REGISTER MAP Table 23. Bit Descriptions for GPIO_OUTPUT Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b1001. 0x9 [10:8] RESERVED Reserved. Set these bits to 0b000. 0x0 7 GPIO7 Set the GPIO7 output pin as logic high or low. 0x0 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 6 GPIO6 Set the GPIO6 output pin as logic high or low. 0x0 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 5 GPIO5 Set the GPIO5 output pin as logic high or low. 0x0 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 4 GPIO4 Set the GPIO4 output pin as logic high or low. 0x0 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 3 GPIO3 Set the GPIO3 output pin as logic high or low. 0x0 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 2 GPIO2 Set the GPIO2 output pin as logic high or low. 0x0 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 1 GPIO1 Set the GPIO1 output pin as logic high or low. 0x0 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. 0 GPIO0 Set the GPIO0 output pin as logic high or low. 0x0 0: The I/O pin is a Logic 0 output. 1: The I/O pin is a Logic 1 output. analog.com Rev. G | 45 of 54 Data Sheet AD5592R REGISTER MAP GPIO Read Configuration Register Name: GPIO_INPUT Selects which pins are general-purpose inputs. Table 24. Bit Descriptions for GPIO_INPUT Bits Bit Name Description Default value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b1010. 0xA 10 GPIO_RD_EN Enable GPIO readback. 0x0 0: GPIO7 to GPIO0 bits determine which pins are set as general-purpose inputs. 1: The next SPI operation clocks out the state of the GPIO pins. [9:8] RESERVED Reserved. Set these bits to 0b00. 0x0 7 GPIO7 Set the I/O7 pin as GPIO input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 6 GPIO6 Set the I/O6 pin as GPIO input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 5 GPIO5 Set the I/O5 pin as GPIO input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 4 GPIO4 Set the I/O4 pin as GPIO input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 3 GPIO3 Set the I/O3 pin as GPIO input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 2 GPIO2 Set the I/O2 pin as GPIO input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. 1 GPIO1 Set the I/O1 pin as GPIO input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. analog.com Rev. G | 46 of 54 Data Sheet AD5592R REGISTER MAP Table 24. Bit Descriptions for GPIO_INPUT Bits Bit Name Description Default value 0 GPIO0 Set the I/O0 pin as GPIO input. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a general-purpose input pin. Power-Down/Reference Control Register Name: PD_REF_CTRL Powers down DACs and enables/disables the reference. Table 25. Bit Descriptions for PD_REF_CTRL Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b1011. 0xB 10 PD_ALL Power down DACs and Internal Reference. 0x0 0: The reference and DACs power-down states are determined by EN_REF and PD7 to PD0 bits. 1: The reference, DACs and ADC are powered down. 9 EN_REF Enable internal reference. Set this bit to 0 if an external reference is used. 0x0 0: The reference and its buffer are powered down. 1: The reference and its buffer are powered up. The reference is available on the VREF pin. 8 RESERVED Reserved. Set this bit to 0. 0x0 7 PD7 Power down the DAC7 channel. 0x0 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 6 PD6 Power down the DAC6 channel. 0x0 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 5 PD5 Power down the DAC5 channel. 0x0 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 4 PD4 analog.com Power down the DAC4 channel. 0x0 Rev. G | 47 of 54 Data Sheet AD5592R REGISTER MAP Table 25. Bit Descriptions for PD_REF_CTRL Bits Bit Name Description Default Value 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 3 PD3 Power down the DAC3 channel. 0x0 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 2 PD2 Power down the DAC2 channel. 0x0 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 1 PD1 Power down the DAC1 channel. 0x0 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. 0 PD0 Power down the DAC0 channel. 0x0 0: The channel is in normal operating mode. 1: The channel is powered down if it is configured as a DAC. GPIO Open-Drain Configuration Register Name: GPIO_OPENDRAIN_CONFIG Selects open-drain or push/pull for general-purpose outputs. The selected I/Ox pin must be set as digital output pin in the GPIO_CONFIG register. Table 26. Bit Descriptions for GPIO_OPENDRAIN_CONFIG Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b1100. 0xC [10:8] RESERVED Reserved. Set these bits to 0b000. 0x0 7 GPIO7 Set the I/O7 pin as open-drain. 0x0 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 6 GPIO6 Set the I/O6 pin as open-drain. 0x0 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 5 GPIO5 analog.com Set the I/O5 pin as open-drain. 0x0 Rev. G | 48 of 54 Data Sheet AD5592R REGISTER MAP Table 26. Bit Descriptions for GPIO_OPENDRAIN_CONFIG Bits Bit Name Description Default Value 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 4 GPIO4 Set the I/O4 pin as open-drain. 0x0 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 3 GPIO3 Set the I/O3 pin as open-drain. 0x0 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 2 GPIO2 Set the I/O2 pin as open-drain. 0x0 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 1 GPIO1 Set the I/O1 pin as open-drain. 0x0 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. 0 GPIO0 Set the I/O0 pin as open-drain. 0x0 0: The I/O pin is a push/pull output pin. 1: The I/O pin is an open-drain output pin. Three-State Configuration Register Name: IO_TS_CONFIG Selects which pins are three-state. Table 27. Bit Descriptions for IO_TS_CONFIG Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b1101. 0xD [10:8] RESERVED Reserved. Set these bits to 0b000. 0x0 7 TS7 Set the I/O7 pin as three-state output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 6 TS6 analog.com Set the I/O6 pin as three-state output. 0x0 Rev. G | 49 of 54 Data Sheet AD5592R REGISTER MAP Table 27. Bit Descriptions for IO_TS_CONFIG Bits Bit Name Description Default Value 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 5 TS5 Set the I/O5 pin as three-state output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 4 TS4 Set the I/O4 pin as three-state output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 3 TS3 Set the I/O3 pin as three-state output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 2 TS2 Set the I/O2 pin as three-state output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 1 TS1 Set the I/O1 pin as three-state output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. 0 TS0 Set the I/O0 pin as three-state output. 0x0 0: The I/O pin function is determined by the pin configuration registers. 1: The I/O pin is a three-state output pin. Software Reset Register Name: SW_RESET Resets the AD5592R/AD5592R-1. Table 28. Bit Descriptions for SW_RESET Bits Bit Name Description Default Value 15 MSB Set this bit to 0. 0x0 [14:11] REG_ADDR Register address. Set these bits to 0b1111. 0xF [10:0] SW_RESET Write to RESET register. 0x0 10110101100: Reset the AD5592R/AD5592R-1. DAC Write Register Name: DAC_WR Writes to addressed DAC register. analog.com Rev. G | 50 of 54 Data Sheet AD5592R REGISTER MAP Table 29. Bit Descriptions for DAC_WR Bits Bit Name Description Default Value 15 MSB Set this bit to 1. 0x1 [14:12] DAC_ADDR DAC Address. 0x0 000: DAC0. 001: DAC1. 010: DAC2. 011: DAC3. 100: DAC4. 101: DAC5. 110: DAC6. 111: DAC7. [11:0] DAC_DATA_WR 12-bit DAC data. 0x0 DATA FORMAT DETAILS: AD5592R/AD5592R-1 ADC AND DAC READBACK ADC Conversion Result Format Name: ADC_RESULT ADC Conversion Result. Table 30. Bit Descriptions for ADC_RESULT Bits Bit Name Description 15 MSB MSB. This bit is read as 0 during ADC channel readback. [14:12] ADC_ADDR ADC address. 000: ADC0. 001: ADC1. 010: ADC2. 011: ADC3. 100: ADC4. 101: ADC5. 110: ADC6. 111: ADC7. [11:0] analog.com ADC_DATA 12-bit ADC result. Rev. G | 51 of 54 Data Sheet AD5592R REGISTER MAP Temperature Reading Format Name: TMP_SENSE_RESULT Temperature Reading. Table 31. Bit Descriptions for TMP_SENSE_RESULT Bits Bit Name Description [15:12] TEMPSENSE_ADDR Temperature Indicator Address. The address is 0b1000 for the temperature reading readback. [11:0] ADC_DATA 12-bit ADC result. DAC Data Read Back Format Name: DAC_DATA_RD Read back the 12-bit DAC Input Register Data. Table 32. Bit Descriptions for DAC_DATA_RD Bits Bit Name Description 15 MSB MSB. This bit is read as 1 during DAC register read back. [14:12] DAC_ADDR DAC Address. 000: DAC0. 001: DAC1. 010: DAC2. 011: DAC3. 100: DAC4. 101: DAC5. 110: DAC6. 111: DAC7. [11:0] analog.com DAC_DATA 12-bit DAC Input Register Data. Rev. G | 52 of 54 Data Sheet AD5592R OUTLINE DIMENSIONS Figure 53. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters Figure 54. 16-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body, Very Very Thin Quad (CP-16-32) Dimensions shown in millimeters Figure 55. 16-Ball Wafer Level Chip Scale Package [WLCSP] (CB-16-3) Dimensions shown in millimeters analog.com Rev. G | 53 of 54 Data Sheet AD5592R OUTLINE DIMENSIONS Updated: July 21, 2022 ORDERING GUIDE Model1 Temperature Range Package Description Packing Quantity AD5592RBCBZ-1-RL7 AD5592RBCBZ-RL7 AD5592RBCPZ-1-RL7 AD5592RBCPZ-RL7 AD5592RBRUZ AD5592RBRUZ-RL7 AD5592RWBCPZ-RL7 AD5592RWBCPZ-1-RL7 −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +125°C −40°C to +125°C 16-Ball WLCSP (1.96 mm × 1.96 mm) 16-Ball WLCSP (1.96 mm × 1.96 mm) 16-Lead LFCSP (3 mm × 3 mm × 0.75 mm) 16-Lead LFCSP (3 mm × 3 mm × 0.75 mm) 16-Lead TSSOP 16-Lead TSSOP 16-Lead LFCSP (3 mm × 3 mm × 0.75 mm) 16-Lead LFCSP (3 mm × 3 mm × 0.75 mm) Reel, 3000 Reel, 3000 Reel, 1500 Reel, 1500 1 Reel, 1000 Reel, 1500 Reel, 1500 Package Option CB-16-3 CB-16-3 CP-16-32 CP-16-32 RU-16 RU-16 CP-16-32 CP-16-32 Marking Code DMD DMG DNR DNS Z = RoHS Compliant Part. EVALUATION BOARDS Model1 Description EVAL-AD5592R-1SDZ EVAL-SDP-CB1Z Evaluation Board Controller Board 1 Z = RoHS Compliant Part. AUTOMOTIVE PRODUCTS The AD5592RW and AD5592RW-1 models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these models. ©2014-2022 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. Rev. G | 54 of 54