FEATURES
FUNCTIONAL BLOCK DIAGRAM
High temperature operation: −55°C to +175°C
16-bit resolution
Fully monotonic
3-wire SPI
Power-on reset feature
Hardware LDAC feature
2.7 V to 5.5 V single-supply operation
Small footprint
10-lead, 3 mm × 3 mm, monometallic wire bonding MSOP
1.8 V logic compatible
IOVDD
VDD
VREF
AD5600
CS
SCLK
DIN
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
DAC
VOUT
LDAC
DGND
APPLICATIONS
AGND
15708-001
Data Sheet
High Temperature, 16-Bit, Unbuffered
Voltage Output DAC, SPI Interface
AD5600
Figure 1.
Downhole drilling and instrumentation
Heavy industrial
High temperature environments
GENERAL DESCRIPTION
The AD5600 is a single channel, 16-bit resolution, voltage
output digital-to-analog converter (DAC) designed for high
temperature operation.
The AD5600 guarantees 16-bit monotonicity over the specified
temperature range and operates from a single 2.7 V to 5.5 V
voltage supply.
For space constrained applications, the AD5600 is available in a
10-lead MSOP with operation specified from −55°C to +175°C.
This package is designed for robustness at extreme temperatures,
including monometallic wire bonding, and is qualified for up to
1000 hours of operation at the maximum temperature rating.
The AD5600 is a member of a growing series of high temperature
qualified products offered by Analog Devices, Inc. For a
complete selection of available high temperature products, see
the high temperature product list and qualification data
available at www.analog.com/hightemp.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
16-bit monotonic DAC
2.7 V to 5.5 V single-supply operation
1.8 V logic compatible
Wide operating temperature range: −55°C to +175°C
The AD5600 uses a versatile 3-wire serial peripheral interface (SPI)
that is compatible with 50 MHz SPI, QSPI™, MICROWIRE™,
and DSP interface standards.
Rev. A
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Tel: 781.329.4700 ©2019–2020 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5600
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Applications ....................................................................................... 1
Terminology .................................................................................... 11
Functional Block Diagram .............................................................. 1
Theory of Operation ...................................................................... 12
General Description ......................................................................... 1
DAC.............................................................................................. 12
Product Highlights ........................................................................... 1
Serial Interface ............................................................................ 12
Revision History ............................................................................... 2
Hardware LDAC ......................................................................... 12
Specifications..................................................................................... 3
Power-On Reset .......................................................................... 12
AC Characteristics ........................................................................ 4
Applications Information .............................................................. 13
Timing Characteristics ................................................................ 4
Layout Guidelines....................................................................... 13
Absolute Maximum Ratings ............................................................ 5
Decoding Multiple DACs .......................................................... 13
Thermal Resistance ...................................................................... 5
Outline Dimensions ....................................................................... 14
ESD Caution .................................................................................. 5
Ordering Guide .......................................................................... 14
Pin Configuration and Function Descriptions ............................. 6
REVISION HISTORY
3/2020—Rev. 0 to Rev. A
Changes to Figure 4 and Figure 7 ................................................... 7
Changes to Figure 9, Figure 10, and Figure 12 ............................. 8
10/2019—Revision 0: Initial Version
Rev. A | Page 2 of 14
Data Sheet
AD5600
SPECIFICATIONS
VDD = 2.7 V to 5.5 V, IOVDD = 1.8 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V, and TA = −55°C to +175°C, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error
Temperature Coefficient
Gain Error
Temperature Coefficient
DC Power Supply Rejection Ratio (PSRR)
OUTPUT CHARACTERISTICS
Voltage Range
Impedance
VOLTAGE REFERENCE INPUT
Impedance
Range
Capacitance
LOGIC INPUTS
Input Current
Input Voltage
Low (VINL)
High (VINH)
Pin Capacitance
Hysteresis Voltage
POWER REQUIREMENTS
Power Supply
VDD Voltage
IOVDD Voltage
Analog Current (AIDD)
IOVDD Current (IOIDD)
Test Conditions/Comments
Min
Typ
Max
±0.5
±0.5
0.3
±0.05
0.5
±0.1
±17
±1.0
±16
16
Guaranteed monotonic
±22
±1.2
0
VREF − 1 LSB
6.25
9
2
±1.0
μA
0.4
0.8
V
V
V
V
pF
V
5.5
5.5
130
24
V
V
μA
μA
1.3
2.4
2.7
1.65
125
15
Rev. A | Page 3 of 14
V
kΩ
kΩ
V
pF
10
0.15
VINH = IOVDD or VINL = DGND
VINH = IOVDD or VINL = DGND
Bit
LSB
LSB
LSB
ppm/°C
LSB
ppm/°C
LSB
VDD
26
IOVDD = 1.65 V to 5.5 V
IOVDD = 2.7 V to 5.5 V
IOVDD = 1.65 V to 5.5 V
IOVDD = 2.7 V to 5.5 V
Unit
AD5600
Data Sheet
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, IOVDD = 1.8 V to 5.5 V, 2.5 V ≤ VREF ≤ VDD, AGND = DGND = 0 V, and TA = −55°C to +175°C, unless otherwise
noted.
Table 2.
Parameter
OUTPUT VOLTAGE SETTLING TIME
SLEW RATE
DIGITAL-TO-ANALOG GLITCH IMPULSE
REFERENCE
−3 dB Bandwidth
Feedthrough
DIGITAL FEEDTHROUGH
SIGNAL-TO-NOISE RATIO
SPURIOUS-FREE DYNAMIC RANGE
TOTAL HARMONIC DISTORTION
OUTPUT
Noise Spectral Density
Noise
Min
Typ
30
7
1.5
Max
Unit
µs
V/µs
nV-sec
Test Condition
To divide the LSB of the full scale in half, load capacitance (CL) = 18 pF
CL = 18 pF, measured from 0% to 63%
1 LSB change around major carry
1.2
1.4
0.4
95
80
74
MHz
mV p-p
nV-sec
dB
dB
dB
All 1s loaded, VREF capacitance (CREF) = 0.1 µF
All 0s loaded, VREF = 1 V p-p at 100 kHz
14
1.25
nV/√Hz
µV p-p
DAC code = 0x0000, frequency = 1 kHz
0.1 Hz to 10 Hz
Digitally generated sine wave at 1 kHz
DAC code = 0xFFFF, frequency 10 kHz, VREF = 2.5 V ± 1 V p-p
TIMING CHARACTERISTICS
VDD = 5 V, 2.5 V ≤ VREF ≤ VDD, VINH = 90% of IOVDD, VINL = 10% of IOVDD, AGND = DGND = 0 V, and−55°C < TA < +175°C, unless
otherwise noted.
Table 3.
Parameter1, 2
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t9
t10
t11
t12
1
2
Limit at
1.62 ≤ IOVDD ≤ 2.7 V
14
70
35
35
5
5
5
10
35
5
5
20
10
15
Limit at
2.7 V ≤ IOVDD ≤ 5.5 V
50
20
10
10
5
5
5
5
10
4
5
20
10
15
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
SCLK cycle frequency
SCLK cycle time
SCLK high time
SCLK low time
CS low to SCLK high setup
CS high to SCLK high setup
SCLK high to CS low hold time
SCLK high to CS high hold time
Data setup time
Data hold time (VINH = 90% of IOVDD, VINL = 10% of IOVDD)
Data hold time (VINH = 3 V, VINL = 0 V)
LDAC pulse width
CS high to LDAC low setup
CS high time between active periods
Guaranteed by design and characterization. Not production tested.
All input signals are specified with rise time (tR) = fall time (tF) = 1 ns/V and timed from a voltage level of (VINL + VINH)/2.
Rev. A | Page 4 of 14
Data Sheet
AD5600
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 4.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
VDD to AGND
IOVDD to AGND
Digital Inputs1 to DGND
VOUT to AGND
AGND to DGND
Digital Input Pin Current
Temperature
Operating Range2
Junction Temperature, TJMAX
Power Dissipation
Reflow Soldering Peak, Pb Free
Electrostatic Discharge (ESD)
1
2
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to VDD + 0.3 V
0.3 V
±10 mA
−55°C to +175°C
175°C
(TJMAX − TA)/θJA
260°C
5 kV
Table 5. Thermal Resistance
Package Type
RM-101
1
θJA
146.76
θJB
84.21
θJC
38.12
ΨJT
2.56
ΨJB
82.41
Unit
°C/W
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD-51.
ESD CAUTION
The digital inputs include SCLK, DIN, CS, and LDAC.
Qualified for up to 1000 hours of operation at the maximum temperature
range.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 5 of 14
AD5600
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10 IOVDD
AGND 3
VREF 4
CS 5
AD5600
9
DGND
8 LDAC
TOP VIEW
(Not to Scale)
7 DIN
6
SCLK
15708-002
VDD 1
VOUT 2
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
VDD
VOUT
AGND
VREF
CS
SCLK
DIN
8
LDAC
9
10
DGND
IOVDD
Description
Power Supply Input. The device can operate from 2.7 V to 5.5 V. Decouple VDD to AGND.
Analog Output Voltage from the DAC.
Analog Ground. Ground reference point for all analog circuitry on the device.
Voltage Reference Input. Connect this pin to an external voltage reference.
Chip Select Input Signal. CS frames the serial data input.
Serial Clock Input Signal. Data is clocked into the serial input register on the rising edge of SCLK.
Serial Data Input Signal. This device accepts 16-bit words. Data is clocked into the serial input register on the rising
edge of SCLK.
LDAC Input Signal. Pulsing this pin low allows the DAC register to be updated if the input register has new
data. This pin can be tied permanently low. In this case, the DAC is automatically updated when new data is
written to the input register on the rising edge of CS.
Digital Ground. Ground reference point for all digital circuitry on the device.
Digital Interface Supply Voltage. The voltage range is 1.65 V to 5.5 V. Decouple IOVDD to DGND.
Rev. A | Page 6 of 14
Data Sheet
AD5600
TYPICAL PERFORMANCE CHARACTERISTICS
0.50
0.50
VDD = 5V
VREF = 2.5V
VDD = 5V
VREF = 2.5V
0.25
0
DNL (LSB)
INL (LSB)
0.25
–0.25
0
–0.25
–0.50
8192
16384 24576 32768 40960 49152
CODE
57344 65536
–0.50
0
8192
16384 24576 32768 40960 49152
CODE
Figure 3. INL vs. Code
15708-006
0
15708-003
–0.75
57344 65536
Figure 6. DNL vs. Code
1
1.0
MAXIMUM DNL
MINIMUM DNL
VDD = 5.5V
VREF = 2.5V
0.8
0
0.6
DNL ERROR (LSB)
INL ERROR (LSB)
–1
MAXIMUM INL
MINIMUM INL
–2
–3
VDD = 5.5V
VREF = 2.5V
–4
0.4
0.2
0
–0.2
–0.4
–5
–0.6
–6
–25
0
25
50
75
100
125
150
175
200
TEMPERATURE (°C)
–1.0
–75
15708-004
–50
–25
0
25
50
75
100
125
150
175
200
TEMPERATURE (°C)
Figure 4. INL Error vs. Temperature
Figure 7. DNL Error vs. Temperature
0.50
0.75
VDD = 5V
TA = 25°C
VREF = 2.5V
TA = 25°C
0.50
0.25
LINEARITY ERROR (LSB)
DNL
0
–0.25
DNL
0.25
0
INL
–0.25
–0.50
2
3
4
5
SUPPLY VOLTAGE (V)
6
7
Figure 5. Linearity Error vs. Supply Voltage
–0.50
0
1
2
3
4
REFERENCE VOLTAGE (V)
5
Figure 8. Linearity Error vs. Reference Voltage
Rev. A | Page 7 of 14
6
15708-008
INL
–0.75
15708-005
LINEARITY ERROR (LSB)
–50
15708-007
–0.8
–7
–75
AD5600
Data Sheet
7
3
VDD = 5.5V
VREF = 2.5V
VDD = 5.5V
2
6
ZERO-SCALE ERROR (LSB)
0
–1
VREF = 2.0V
VREF = 2.5V
VREF = 5.5V
–2
–3
–4
–5
5
4
3
2
1
0
–6
–50
–25
0
25
50
75
100
125
150
175
–1
–75
15708-009
–7
–75
200
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
150
175
200
TEMPERATURE (°C)
15708-012
GAIN ERROR (LSB)
1
Figure 12. Zero-Scale Error vs. Temperature
Figure 9. Gain Error vs. Temperature
120
TA = 25°C
VDD = 5.5V
VREF = 2.5V
REFERENCE VOLTAGE
VDD = 5V
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
100
80
60
AIDD
IOIDD
40
SUPPLY VOLTAGE
VREF = 2.5V
–50
–25
0
25
50
75
100
125
150
175
200
TEMPERATURE (°C)
15708-013
0
–75
15708-010
20
VOLTAGE (V)
Figure 13. Supply Current vs. Voltage (Reference and Supply)
Figure 10. Supply Current vs. Temperature
200
200
VDD = 5V
VREF = 2.5V
TA = 25°C
180
REFERENCE CURRENT (µA)
140
120
100
80
60
40
150
100
50
0
1.0
1.1
1.2
1.3 1.4 1.5 1.6 1.7 1.8
DIGITAL INPUT VOLTAGE (V)
1.9
2.0
0
0
Figure 11. Supply Current vs. Digital Input Voltage
10,000
20,000
30,000 40,000
CODE (Decimal)
50,000
60,000
Figure 14. Reference Current vs. Code
Rev. A | Page 8 of 14
70,000
15708-014
20
15708-011
SUPPLY CURRENT (µA)
160
Data Sheet
AD5600
VREF = 2.5V
VDD = 5V
TA = 25°C
VREF = 2.5V
VDD = 5V
TA = 25°C
VOUT (1V/DIV)
100
DIN (5V/DIV)
90
VOUT (50mV/DIV)
GAIN = –216
1LSB = 8.2mV
VOUT (50mV/DIV)
10
2µs/DIV
0.5µs/DIV
Figure 15. Digital Feedthrough
Figure 18. Small Signal Settling Time
30
1.236
CS
25
1.232
20
1.230
HITS
VOLTAGE (V)
1.234
1.228
–55°C
+25°C
+175°C
15
10
VOUT
1.226
5
AIDD (uA)
Figure 16. Digital-to-Analog Glitch Impulse
VREF = 2.5V
VDD = 5V
TA = 25°C
2µs/DIV
15708-019
120
118
116
114
112
110
108
106
104
98
102
TIME (ns)
0
100
2.0
96
1.5
94
1.0
92
0.5
90
0
15708-016
1.224
–0.5
Figure 19. AIDD Histogram
16
–55°C
+25°C
+175°C
CS (5V/DIV)
12
10pF
50pF
HITS
100pF
8
200pF
4
VOUT (0.5V/DIV)
15708-017
Figure 20. IOIDD Histogram
Figure 17. Large Signal Settling Time
Rev. A | Page 9 of 14
MORE
20.7
20.3
19.9
15708-020
IOIDD (µA)
19.5
19.1
18.7
18.3
17.9
17.5
17.1
16.7
16.3
15.9
15.5
0
15.1
VOLTAGE (V)
15708-018
15708-015
0%
Data Sheet
1.5
40
1.0
20
0
0.5
VOUT (dBm)
0
–20
–40
–0.5
–60
–1.0
0
20
40
60
TIME (Seconds)
80
–100
15708-021
–1.5
100
0
Figure 21. 0.1 Hz to 10 Hz Output Noise
30
40
FREQUENCY (kHz)
50
60
70
10
35
0
30
VOUT/VREF (dBm)
–10
25
20
15
–20
–30
–40
10
–50
5
0
600
700
800
900
1000
1100
FREQUENCY (Hz)
1200
1300
1400
15708-022
NOISE SPECTRAL DENSITY (nV rms/ Hz)
20
Figure 24. Total Harmonic Distortion
40
Figure 22. Noise Spectral Density vs. Frequency,1 kHz
12
10
8
6
4
9.7
9.8
9.9
10.0
10.1
FREQUENCY (kHz)
10.2
10.3
10.4
15708-023
2
0
9.6
–60
1k
10k
100k
1M
FREQUENCY (Hz)
10M
Figure 25. Multiplying Bandwidth
14
NOISE SPECTRAL DENSITY (nV rms/ Hz)
10
15708-024
–80
Figure 23. Noise Spectral Density vs. Frequency, 10 kHz
Rev. A | Page 10 of 14
100M
15708-025
OUTPUT NOISE (µV rms)
AD5600
Data Sheet
AD5600
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or INL is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function. A typical
INL vs. code plot is shown in Figure 3.
Differential Nonlinearity (DNL)
DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of ±1 LSB maximum ensures
monotonicity. A typical DNL vs. code plot is shown in Figure 6.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as LSB. It is the deviation in slope of the
DAC transfer characteristic from the ideal.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change in
gain error with changes in temperature. This temperature
coefficient is expressed in ppm/°C.
Zero-Scale Error
Zero-scale error is a measure of the output error when zero
scale is loaded to the DAC register.
Zero-Scale Temperature Coefficient
Zero-scale temperature coefficient is a measure of the change in
zero-scale error with a change in temperature. This temperature
coefficient is expressed in ppm/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. This impulse is normally specified as the area of the glitch
in nV-sec and is measured when the digital input code is changed
by 1 LSB at the major carry transition. A digital-to-analog glitch
impulse plot is shown in Figure 16.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC. However, this feedthrough is measured when the DAC
output is not updated. CS is held high while the SCLK and DIN
signals are toggled. Digital feedthrough is specified in nV-sec
and is measured with a full-scale code change on the data bus,
that is, from all 0s to all 1s and vice versa. A typical digital
feedthrough plot is shown in Figure 15.
DC Power Supply Rejection Ratio (PSRR)
DC PSRR indicates how the output of the DAC is affected by
changes in the power supply voltage. The DC power supply
rejection ratio is expressed in terms of the LSB number change
in the output of the DAC. VDD is varied by ±10%.
Reference Feedthrough
Reference feedthrough is a measure of the feedthrough from the
VREF input to the DAC output when the DAC is loaded with all
0s. A 100 kHz, 1 V p-p is applied to VREF. Reference feedthrough
is expressed in mV p-p.
Rev. A | Page 11 of 14
AD5600
Data Sheet
THEORY OF OPERATION
The AD5600 is a single channel, 16-bit, serial input, voltage
output DAC designed for high temperature operation. The
device operates from a supply voltage range of 2.7 V to 5.5 V.
The AD5600 input shift register is 16 bits wide. Data is written
to the device through the 3-wire SPI at clock speeds up to
50 MHz.
The AD5600 incorporates a power-on reset circuit that ensures
that the DAC output register powers up to a known state.
DAC
The AD5600 has a 16-bit wide input shift register. When
writing to the input shift register, the CS pin frames the SPI
transaction. A high to low transition on the CS pin starts a write
transaction, and a low to high transition on the CS pin ends the
transaction. Data is loaded into the input shift register, MSB
first, on the rising edge of the serial clock (SCLK).
If more than 16 bits of data are loaded to the input shift register,
the last 16 bits are kept. If less than 16 bits of data are loaded,
bits remain from the previous word loaded in.
DAC Architecture
HARDWARE LDAC
The DAC architecture consists of two matched DAC sections. A
simplified circuit architecture is shown in Figure 26. The DAC
architecture of the AD5600 is segmented. The four MSBs of the
16-bit DAC word drive are decoded to drive 15 switches, E1 to
E15. Each switch connects one of 15 matched resistors to either
AGND or VREF. The remaining twelve bits of the DAC word
drive switch S0 to S11 of a 12-bit voltage mode R-2R ladder
network.
The AD5600 features a hardware LDAC pin that can control the
transfer of data from the input shift register to the DAC register.
R
2R
R
VOUT
2R
2R . . . . .
2R
2R
2R . . . . .
2R
S0
S1 . . . . .
S11
E1
E2 . . . . .
E15
Figure 26. Simplified DAC Architecture
Transfer Function
The input coding to the DAC is straight binary. The ideal
output voltage is given by
VOUT = VREF × (D/65,536)
where:
D is the decimal equivalent of the binary code that is loaded
into the DAC register.
SERIAL INTERFACE
15708-026
FOUR MSBs DECODED
INTO 15 EQUAL SEGMENTS
If LDAC is held low on the falling edge of CS during a SPI write
transaction, the DAC register is updated with the contents of
the input register on the rising edge of CS at the end of the
frame.
Deferred Updating
If LDAC is held high during a SPI write frame, the contents of
the input register are not transferred into the DAC register until
a falling edge is detected on the LDAC pin. Falling edges on the
LDAC pin are ignored while the CS pin is low.
VREF
12-BIT R-2R LADDER
Instantaneous Updating
POWER-ON RESET
The AD5600 has a power-on reset circuit that ensures that the
DAC output powers up to a known state. On power-up, the
content of the AD5600 DAC register is cleared to all 0s. This
register remains in this state until the user loads data from the
input register. The input register of the AD5600 is not cleared
on power-up. When initially loading data into the DAC, at least
16 bits of data must be loaded to the DAC to overwrite the
undefined data from power-up.
If LDAC is held low on power-up, a low to high transition on
CS may transfer the erroneous contents in the input register to
the DAC register. Clear the input register contents before
bringing CS high.
The AD5600 uses a 3-wire serial interface that is compatible
with SPI, QSPI, MICROWIRE and DSP interface standards.
The serial interface can operate at clock rates up to 50 MHz.
Rev. A | Page 12 of 14
Data Sheet
AD5600
APPLICATIONS INFORMATION
LAYOUT GUIDELINES
AD5600
SCLK
DIN
ENABLE
CODED
ADDRESS
The AD5600 must have 10 µF supply bypassing capacitors in
parallel with 0.1 µF capacitors on each supply located as close to
the package as possible, ideally right up against the device. It is
recommended to use 10 µF tantalum bead capacitors. The 0.1 μF
capacitor must have low effective series resistance (ESR) and low
effective series inductance (ESI), such as the common ceramic
types, to provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
DECODING MULTIPLE DACs
The CS pin of the AD5600 can select one of a number of DACs.
All devices receive the same serial clock and serial data, but only
one device receives the CS signal at any one time. The DAC
addressed is determined by the decoder. Some digital feedthrough
from the digital input lines exists. Use a burst clock to minimize
the effects of digital feedthrough on the analog signal channels.
Figure 27 shows a typical circuit.
Rev. A | Page 13 of 14
VOUT
DIN
VDD
SCLK
AD5600
EN
CS
DECODER
VOUT
DIN
SCLK
DGND
AD5600
CS
VOUT
DIN
SCLK
AD5600
CS
DIN
SCLK
Figure 27. Addressing Multiple DACs
VOUT
15708-027
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. Design the PCB on which the AD5600
is mounted so that the analog and digital sections are separated
and confined to certain areas of the board. If the AD5600 is in
a system where multiple devices require an analog ground to
digital ground connection, make the connection at one point
only. Establish the star ground point as close as possible to the
device.
CS
AD5600
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
6°
0°
0.23
0.13
COMPLIANT TO JEDEC STANDARDS MO-187-BA
0.70
0.55
0.40
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 28. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD5600HRMZ
EVAL-AD5600PMDZ
1
Temperature Range
−55°C to +175°C
Package Description
10-Lead Mini Small Outline Package [MSOP]
Evaluation Board
Z = RoHS Compliant Part.
©2019–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15708-3/20(A)
Rev. A | Page 14 of 14
Package Option
RM-10
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