Single-Channel, 16-Bit Current and Voltage Output
DAC with Dynamic Power Control and
HART Connectivity
AD5758
Data Sheet
FEATURES
16-bit resolution and monotonicity
DPC for thermal management
Current/voltage output available on a single terminal
Current output ranges: 0 mA to 20 mA, 4 mA to 20 mA,
0 mA to 24 mA, ±20 mA, ±24 mA, −1 mA to +22 mA
Voltage output ranges (with 20% overrange): 0 V to 5 V,
0 V to 10 V, ±5 V, and ±10 V
User-programmable offset and gain
Advanced on-chip diagnostics, including a 12-bit ADC
On-chip reference
Robust architecture, including output fault protection
EMC test standards:
IEC 61000-4-6 conducted immunity (10 V, Class A)
IEC 61000-4-3 radiated immunity (20 V/m, Class A)
IEC 61000-4-2 ESD (±6 kV contact, Class B)
IEC 61000-4-4 electrical fast transient (EFT) (±4 kV, Class B)
IEC 61000-4-5 surge (±4 kV, Class B)
32-lead, 5 mm × 5 mm LFCSP
−40°C to +115°C temperature range
converter, optimized for minimum on-chip power dissipation. The
CHART pin enables a HART® signal to be coupled onto the current
output.
The device uses a versatile 4-wire serial peripheral interface (SPI)
that operates at clock rates of up to 50 MHz and is compatible
with standard SPI, QSPI™, MICROWIRE™, DSP, and
microcontroller interface standards. The interface also features an
optional SPI cyclic redundancy check (CRC) and a watchdog
timer (WDT). The AD5758 offers improved diagnostic features
from its predecessors, such as an integrated 12-bit diagnostic
analog-to-digital converter (ADC). Additional robustness is
provided by the inclusion of a line protector on the VIOUT,
+VSENSE, and −VSENSE pins. When used with its companion
power management unit (PMU)/isolator (ADP1031), the
AD5758 is capable of enabling customers to develop an eight
channel to channel isolated analog output module with less
than 2 W power dissipation, while meeting CISPR 11 Class B.
PRODUCT HIGHLIGHTS
1.
APPLICATIONS
Process control
Actuator control
Channel isolated analog outputs
Programmable logic controller (PLC) and distributed control
systems (DCS) applications
HART network connectivity
GENERAL DESCRIPTION
The AD5758 is a single-channel, voltage and current output
digital-to-analog converter (DAC) that operates with a power
supply range from −33 V (minimum) on AVSS to +33 V
(maximum) on AVDD1 with a maximum operating voltage
between the two rails of 60 V. On-chip dynamic power
control (DPC) minimizes package power dissipation, which is
achieved by regulating the supply voltage (VDPC+) to the VIOUT
output driver circuitry from 5 V to 27 V using a buck dc-to-dc
Rev. B
2.
3.
4.
DPC, using an integrated buck dc-to-dc converter for
thermal management. When used with the ADP1031, the
AD5758 enables eight channel to channel isolated outputs
at 15 V is required. When driving 20 mA into a 50 Ω load, the
required compliance is reduced to >1 V.
In DPC current mode, the AD5758 dc-to-dc circuitry senses
the output voltage and regulates the VDPC+ supply voltage to
meet compliance requirements plus an optimized headroom
voltage for the output buffer. VDPC+ is dynamically regulated to
4.95 V or (IOUT × RLOAD + headroom), whichever is greater,
which excludes the light load condition whereby the VDPC+
voltage can rise beyond the target value. As previously noted,
this exclusion does not represent the worst case power
dissipation condition in an application. The AD5758 is capable
of driving up to 24 mA through a 1 kΩ load, for a given input
supply (24 V + headroom).
At low output power levels, the regulated headroom increases
above 2.3 V due to the fact that the dc-to-dc circuitry uses a
minimum on time duty cycle. This behaviour is expected and
does not impact any worse case power dissipation.
PPC Current Mode
The dc-to-dc converter may also operate in programmable power
control mode, where the VDPC+ voltage is user-programmable to a
given level to accommodate the maximum output load required.
This mode represents a trade-off between the optimized power
efficiency of the DPC current mode and the settling time of a
system with a fixed supply (dc-to-dc disabled). In PPC current
mode, VDPC+ is regulated to a user-programmable level between 5 V
and 25.677 V with respect to −VSENSE (in steps of 0.667 V). This
mode is useful if settling time is an important requirement of the
design. See the DC-to-DC Converter Settling Time section. Care
is needed in selecting the programmed level of VDPC+ if the load
is nonlinear in nature. VDPC+ must be set high enough to obey the
output compliance voltage specification. If the load is unknown,
the +VSENSE input to the ADC can be used to monitor the VIOUT pin
in current mode to determine the user-programmable value at
which to set VDPC+.
Rev. B | Page 34 of 69
Data Sheet
AD5758
DC-to-DC Converter Settling Time
When in DPC current mode, the settling time is dominated by the
settling time of the dc-to-dc converter and is typically 200 µs
without the digital slew rate control feature enabled. To reduce
initial VIOUT waveform overshoot without adding a capacitor on
VIOUT and thereby affecting HART operation, enable the digital
slew rate control feature using the DAC_CONFIG register (see
Table 32).
Table 11 shows the typical settling time for each of the dc-todc converter modes. All values shown assume the use of the
components recommended by Analog Devices, Inc., listed in
Table 10. The achievable settling time in any given application is
dependent on the choice of external inductor and capacitor
components used, as well as the current-limit setting of the dcto-dc converter.
Table 11. Settling Time vs. DC-to-DC Converter Mode
DC-to-DC Converter Mode
DPC Current Mode
PPC Current Mode
DPC Voltage Mode
Settling Time (µs)
200
15
15
DC-to-DC Converter Inductor Selection
For typical 4 mA to 20 mA applications, a 47 μH inductor (per
Table 10), combined with the switching frequency of 500 kHz,
allows up to 24 mA to be driven into a load resistance of up to 1 kΩ
with an AVDD1 supply of greater than 24 V + headroom. It is
important to ensure that the peak current does not cause the
inductor to saturate, especially at the maximum ambient
temperature. If the inductor enters saturation mode, it results
in a decrease in efficiency. Larger size inductors translate to
lower core losses. The slew rate control feature of the AD5758
can be used to limit peak currents during slewing. Program an
appropriate current limit (via the DCDC_CONFIG2 register) to
shut off the internal switch if the inductor current reaches that
limit.
DC-to-DC Converter Input and Output Capacitor Selection
The output capacitor, CDCDC, affects the ripple voltage of the dcto-dc converter and limits the maximum slew rate at which the
output current can rise. The ripple voltage is directly related to
the output capacitance. The CDCDC capacitor recommended by
Analog Devices (see Table 10), combined with the recommended
47 µH inductor, results in a 500 kHz ripple with amplitude less
than 50 mV and guarantees stability and operation with HART
capability across all operating modes.
For high voltage capacitors, the size of the capacitor is often an
indication of the charge storage ability. It is important to
characterize the dc bias voltage vs. capacitance curve for this
capacitor. Any capacitance values specified are with reference
to a dc bias corresponding to the maximum VDPC+ voltage in the
application. As well as the voltage rating, the temperature range
of the capacitor must also be considered for a given application.
These considerations are key in selection of the components
described in Table 10.
The input capacitor, CIN, provides much of the dynamic current
required for the dc-to-dc converter, and a low effective series
resistance (ESR) component is recommended. For the AD5758,
a low ESR tantalum or ceramic capacitor of 4.7 μF (1206 size)
in parallel with a 0.1 μF (0402 size) capacitor is recommended.
Ceramic capacitors must be chosen carefully because they can
exhibit a large sensitivity to dc bias voltages and temperature.
X5R or X7R dielectrics are preferred because these capacitors
remain stable over wider operating voltage and temperature
ranges. Care must be taken if selecting a tantalum capacitor to
ensure a low ESR value.
CLKOUT
The AD5758 can provide a CLKOUT signal to the system for
synchronization purposes. This signal is programmable to eight
frequency options between 416 kHz and 588 kHz, with the
default option being 500 kHz—the same switching frequency of
the dc-to-dc converter. This feature is configured in the
GP_CONFIG1 register and is disabled by default
INTERDIE 3-WIRE INTERFACE
A 3-wire interface is used to communicate between the two die
in the AD5758. The 3-wire interface master is located on the
main die, and the 3-wire interface slave is on the dc-to-dc die.
The three interface signals are data, DCLK (running at
MCLK/8), and interrupt.
The main purpose of the 3-wire interface is to read from or write
to the DCDC_CONFIG1 and DCDC_CONFIG2 registers.
Addressing these registers via the SPI interface initiates an
internal 3-wire interface transfer from the main die to the dc-todc die. The 3-wire interface master on the main die initiates
writes and reads to the registers on the dc-to-dc die using
DCLK as the serial clock. The slave uses an interrupt signal to
the dc-to-dc die to indicate that a read of the dc-to-dc die
internal status register is required.
For every 3-wire interface write, an automatic read and compare
process can be enabled (default case) to ensure that the contents of
the copy of the DCDC_CONFIGx registers on the main die
match the contents of the registers on the dc-to-dc die. This
comparison is performed to ensure the integrity of the digital
circuitry on the dc-to-dc die. With this feature enabled, a 3-wire
interface transfer takes approximately 300 µs. When disabled,
this transfer time reduces to 30 µs.
The BUSY_3WI flag in the DCDC_CONFIG2 register is asserted
during the 3-wire interface transaction. The BUSY_3WI flag
is also set when the user updates the DAC range (via the DAC_
CONFIG register, Bits[4:0]) due to the internal calibration
memory refresh caused by this action, which requires a 3-wire
interface transfer between the two die. A write to either of the
DCDC_CONFIGx registers must not be initiated while
BUSY_3WI is asserted. If a write occurs while BUSY_3WI is
asserted, the new write is delayed until the current 3-wire
interface (3WI) transfer completes.
Rev. B | Page 35 of 69
AD5758
Data Sheet
3-Wire Interface Diagnostics
Driving Large Capacitive Loads
Any faults on the dc-to-dc die triggers an interrupt to the main
die. An automatic status read of the dc-to-dc die is performed.
After the read transaction, the main die retains a copy of the dc-todc die status bits (VIOUT_OV_ERR, DCDC_P_SC_ERR, and
DCDC_P_PWR_ERR). These values are available in the
ANALOG_DIAG_RESULTS register and via the OR’d analog
diagnostic results bits in the status register. These bits also
trigger the FAULT pin.
The voltage output amplifier is capable of driving capacitive
loads of up to 2 µF with the addition of a 220 pF nonpolarized
compensation capacitor. This capacitor, while allowing the
AD5758 to drive higher capacitive loads and reduce overshoot,
increases the settling time of the device and, therefore, affects
the bandwidth of the system. Without the compensation
capacitor, capacitive loads of up to 10 nF can be driven.
In response to the interrupt request, the main die (master)
performs a 3-wire interface read operation to read the status of
the dc-to-dc die. The interrupt is only asserted again by a
subsequent dc-to-dc die fault flag, upon which the 3-wire
interface initiates another status read transaction. If an interrupt
signal is detected six times in a row, the interrupt detection
mechanism is disabled until a 3-wire interface write transaction
completes. This disabling prevents the 3-wire interface from
being blocked because of the constant dc-to-dc die status read
when the interrupt is toggling. The INTR_SAT_3WI flag in the
DCDC_CONFIG2 register indicates when this event occurs, and
a write to either DCDC_CONFIGx register resets this bit to 0.
Under normal operation, the voltage output sinks/sources up to
12 mA and maintains specified operation. The short-circuit
current is typically 16 mA. If a short circuit is detected, the
FAULT pin goes low and the VOUT_SC_ERR bit in the
ANALOG_DIAG_RESULTS register is set.
FAULT PROTECTION
During a 3-wire read or write operation, the address and data bits
in the transaction produce parity bits. These parity bits are checked
on the receive side and, if they do not match on both die, the ERR_
3WI bit in the DIGITAL_DIAG_RESULTS register is set. If the
read and compare process is enabled and a parity error occurs, the
3WI_RC_ERR bit in the DIGITAL_DIAG_ RESULTS register is
also set.
VOLTAGE OUTPUT
Voltage Output Amplifier and VSENSE Functionality
The voltage output amplifier is capable of generating both unipolar
and bipolar output voltages, and is also capable of driving a
load of 1 kΩ in parallel with 2 µF (with an external compensation
capacitor) to AGND. Figure 78 shows the voltage output driving a
load, RLOAD, on top of a common-mode voltage (VCM) of ±10 V. An
integrated 2 MΩ resistor ensures that the amplifier loop is kept
closed, thus preventing potential large destructive voltages on
VIOUT due to the broken amplifier loop in applications where a
cable may become disconnected from +VSENSE. If remote sensing of
the load is not required, connect +VSENSE directly to VIOUT via a
1 kΩ resistor and connect −VSENSE directly to AGND via a 1 kΩ
resistor.
AD5758
+VSENSE
VOUT
RANGE
SCALING
2MΩ VIOUT
–VSENSE
2MΩ
Figure 78. Voltage Output
RLOAD
±10V VCM
11840-121
16-BIT
DAC
Voltage Output Short-Circuit Protection
The AD5758 incorporates a line protector on the VIOUT pin,
+VSENSE pin, and −VSENSE pin. The line protector operates by
clamping the voltage internal to the line protector to the VDPC+
and AVSS rails, thereby protecting internal circuitry from
external voltage faults. If a voltage outside of these limits is
detected on the VIOUT pin, an error flag (VIOUT_OV_ERR) is
also set and is located in the ANALOG_DIAG_RESULTS register.
CURRENT OUTPUT
External Current Setting Resistor
As shown in Figure 74, RSET is an internal sense resistor that forms
part of the voltage to current conversion circuitry. The stability
of the output current value over temperature is dependent on
the stability of the value of RSET. As a method of improving the
stability of the output current over temperature, an external,
13.7 kΩ, low drift resistor can be connected between the RA and
RB pins of the AD5758, to be used instead of the internal resistor.
Table 1 shows the performance specifications of the AD5758 with
both the internal RSET resistor and an external, 13.7 kΩ RSET resistor.
The external RSET resistor specification assumes an ideal resistor.
The actual performance depends on the absolute value and
temperature coefficient of the resistor used. Therefore, the
resistor specifications directly affect the gain error of the
output and the TUE.
To arrive at the absolute worst case overall TUE of the output
with a particular external RSET resistor, add the percentage absolute
error of the RSET resistor directly to the TUE of the AD5758 with
the external RSET resistor, shown in Table 1 (expressed in % FSR).
The temperature coefficient must also be considered, as well as
the specifications of the external reference, if this is the option
being used in the system.
The magnitude of the error derived from directly summing the
absolute error and TC error of both the external RSET resistor and
the external reference with the TUE specification of the
AD5758 is unlikely to occur because the TC values of the
individual components are not likely to exhibit the same drift
polarity, and, therefore, an element of cancelation occurs. For
Rev. B | Page 36 of 69
Data Sheet
AD5758
SR_STEP. SR_CLOCK defines the rate at which the digital slew
is updated. For example, if the selected update rate is 8 kHz, the
output updates every 125 µs. In conjunction with SR_CLOCK,
SR_STEP defines by how much the output value changes at
each update. Together, both parameters define the rate of
change of the output value.
this reason, add the TC values in a root of squares fashion. A
further improvement can be gained by performing a two point
calibration at zero scale and full scale, thus reducing the absolute
errors of the voltage reference and the RSET resistor.
Current Output Open-Circuit Detection
When in current output mode, if the headroom available falls
below the compliance range due to an open-loop circuit or an
insufficient power supply voltage, the IOUT_OC_ERR flag in
the ANALOG_DIAG_RESULTS register is asserted, and the
FAULT pin goes low.
The following equation describes the slew rate as a function of
the step size, the slew rate frequency, and the LSB size:
Slew Time =
HART CONNECTIVITY
When the slew rate control feature is enabled, all output changes
occur at the programmed slew rate. For example, if the WDT times
out and an automatic clear occurs, the output slews to the clear
value at the programmed slew rate (setting the CLEAR_NOW_
EN bit in the GP_CONFIG1 register overrides this default
behavior to cause the output to update to the clear code
immediately, rather than at the programmed slew rate).
Figure 79 shows the recommended circuit for attenuating and
coupling the HART signal into the AD5758. To achieve 1 mA p-p
at the VIOUT pin, a signal of approximately 125 mV p-p is required
at the CHART pin. The HART signal appearing at the VIOUT pin is
inverted relative to the signal input at the CHART pin.
The slew rate frequency for any given value is the same for all
output ranges. The step size, however, varies across output
ranges for a given value of step size because the LSB size is
different for each output range.
IOUT
CHART
HART_EN
C1
C2
HART MODEM
OUTPUT
Figure 79. Coupling the HART Signal
As well as their use in attenuating the incoming HART modem
signal, a minimum capacitance of the combination of C1 and
C2 is required to ensure that the bandwidth presented to the
modem output signal passes the 1.2 kHz and 2.2 kHz frequencies.
Assuming a HART signal of 500 mV p-p, the recommended
values are C1 = 47 nF and C2 = 150 nF. Digitally controlling the
slew rate of the output is necessary to meet the analog rate of
change requirements for HART.
If the HART feature is not required, disable the HART_EN bit
and leave the CHART pin open circuit. However, if it is required
to slow the DAC output signal with a capacitor, the HART_EN
bit must be enabled and the required CSLEW capacitor connected
to the CHART pin.
DIGITAL SLEW RATE CONTROL
The slew rate control feature of the AD5758 allows the user to
control the rate at which the output value changes. This feature
is available in both current and voltage mode. With the slew
rate control feature disabled, the output value changes at a rate
limited by the output drive circuitry and the attached load. To
reduce the slew rate, enable the slew rate control feature. With
this feature enabled, the output steps digitally from one value to
the next at a rate defined by two parameters accessible via the
DAC_CONFIG register. The parameters are SR_CLOCK and
11840-027
IOUT
RANGE
SCALING
Step Size × Slew Rate Frequency × LSB Size
where:
Slew Time is expressed in seconds.
Output Change is expressed in amps for current output mode or
volts for voltage output mode.
The AD5758 has a CHART pin, onto which a HART signal can be
coupled. The HART signal appears on the current output if the
HART_EN bit in the GP_CONFIG1 register is enabled and the
VIOUT output is also enabled.
16-BIT
DAC
Output Change
AD5758 ADDRESS PINS
The AD5758 address pins (AD0 and AD1) are used in
conjunction with the address bits within the SPI frame (see
Table 12) to determine which AD5758 device is being
addressed by the system controller. With the two address pins,
up to four devices can be independently addressed on one board.
SPI Interface and Diagnostics
The AD5758 is controlled over a 4-wire serial interface with an
8-bit cyclic redundancy check (CRC-8) enabled by default. The
input shift register is 32 bits wide, and data is loaded into the
device MSB first under the control of a serial clock input, SCLK.
Data is clocked in on the falling edge of SCLK. If CRC is disabled,
the serial interface is reduced to 24 bits; a 32-bit frame is still
accepted but the last 8 bits are ignored.
Table 12. Writing to a Register (CRC Enabled)
MSB
D31
Slip bit
[D30:D29]
AD5758
address
[D28:D24]
Register address
[D23:D8]
Data
LSB
[D7:D0]
CRC
As shown in Table 12, every SPI frame contains two address
bits. These bits must match the hardware address pins
(AD0 and AD1) for a particular device to accept the SPI frame
on the bus.
Rev. B | Page 37 of 69
AD5758
Data Sheet
SPI Cyclic Redundancy Check
To verify that data has been received correctly in noisy environments, the AD5758 offers the option of CRC based on a CRC-8.
The device controlling the AD5758 generates an 8-bit frame
check sequence using the following polynomial:
C(x) = x8 + x2 + x1 + 1
This sequence is added to the end of the data-word, and 32 bits
are sent to the AD5758 before taking SYNC high.
If the SPI_CRC_EN bit is set high (default state), the user must
supply a frame of exactly 32 bits wide that contains the 24 data bits
and 8-bit CRC. If the CRC check is valid, the data is written to
the selected register. If the CRC check fails, the data is ignored,
the FAULT pin goes low and the FAULT pin status bit and the
digital diagnostic status bit (DIG_DIAG_STATUS) in the status
register are asserted. A subsequent readback of the
DIGITAL_DIAG_RESULTS register reveals that the
SPI_CRC_ERR bit is also set. This register is a per bit, write to
clear register (see the Sticky Diagnostic Results Bits section);
therefore, the SPI_CRC_ERR bit can be cleared by writing a 1 to
Bit D0 of the DIGITAL_DIAG_RESULTS register. Doing so
clears the SPI_CRC_ERROR bit and causes the FAULT pin to
return high (assuming that there are no other active faults).
When configuring the FAULT_PIN_CONFIG register, the user
can decide whether the SPI CRC error affects the FAULT pin.
See the FAULT Pin Configuration Register section for further
details. The SPI CRC feature can be used for both the
transmission and receipt of data packets.
UPDATE ON SYNC HIGH
SYNC
LSB
D0
24-BIT DATA
24-BIT DATA TRANSFER—NO CRC ERROR CHECKING
UPDATE ON SYNC HIGH
ONLY IF CRC CHECK PASSED
SYNC
LSB
D8
24-BIT DATA
D7
D0
8-BIT CRC
FAULT PIN GOES LOW
IF CRC CHECK FAILS
FAULT
32-BIT DATA TRANSFER WITH CRC ERROR CHECKING
11840-025
SDI
Readback Modes
The AD5758 offers four readback modes, as follows:
•
•
•
•
Two stage readback mode
Autostatus readback mode
Shared SYNC autostatus readback mode
Echo mode
The two stage readback consists of a write to a dedicated
register, TWO_STAGE_READBACK_SELECT, to select the
register location to be read back. This write is followed by a no
operation (NOP) command, during which the contents of the
selected register are available on SDO.
Table 13. SDO Contents for Read Operation
MSB
[D31:D30] D29
[D28:24]
0b10
FAULT pin status Register address
LSB
[D23:D8] [D7:D0]
Data
CRC
Bits[D31:D30] = 0b10 are used for synchronization purposes
during readback.
The shared SYNC autostatus readback is a special version of the
autostatus readback mode used to avoid SDO bus contention
when multiple devices are sharing the same SYNC line.
SCLK
MSB
D31
An SCLK count feature is also built into the SPI diagnostics,
meaning that only SPI frames with exactly 32 SCLK falling
edges (32 or 24 if SPI CRC is disabled) are accepted by the
interface as a valid write. SPI frames of lengths other than these
values are ignored and the SCLK_COUNT_ERR flag asserts in
the DIGITAL_DIAG_RESULTS register.
Figure 80. CRC Timing (Assume LDAC = 0)
Echo mode behaves similarly to autostatus readback mode,
except that every second readback consists of an echo of the
previous command written to the AD5758 (see Figure 81). See
the Reading from Registers section for further details on the
readback modes.
SPI Interface Slip Bit
A further enhancement to the robustness of the interface is the
addition of the slip bit. The MSB of the SPI frame must equal
the inverse of the MSB − 1 for the frame to be considered valid.
Rev. B | Page 38 of 69
PREVIOUS
COMMAND
STATUS
REGISTER
CONTENTS
PREVIOUS
COMMAND
Figure 81. SDO Contents, Echo Mode
11840-019
SDI
SPI Interface SCLK Count Feature
If autostatus readback mode is selected, the contents of the status
register are available on the SDO line during every SPI transaction.
This feature allows the user to continuously monitor the status
register and act quickly in the case of a fault. The AD5758 powers
up with this feature disabled. When this feature is enabled, the
normal two stage readback feature is not available. Only the
status register is available on SDO. To read back any other
register, disable the automatic readback feature first before
following the two stage readback sequence. The automatic
status readback can be reenabled after the register is read back.
SCLK
MSB
D23
If an incorrect slip bit is detected, the data is ignored and the
SLIPBIT_ERROR bit in the DIGITAL_DIAG_RESULTS register
is asserted.
Data Sheet
AD5758
WATCHDOG TIMER (WDT)
Table 14. Gain Register Adjustment
The WDT feature is useful to ensure that communication is not
lost between the system controller and the AD5758 and that the
SPI datapath lines function as expected.
Gain Adjustment Factor
1
65,535/65,536
…
2/65,536
1/65,536
When enabled, the WDT alerts the system if the AD5758 has not
received a specific SPI frame in the user-programmable timeout
period. When the specific SPI frame is received, the watchdog
resets the timer controlling the timeout alert. The SPI frame
used to reset the WDT is configurable as one of the two
following choices:
•
•
A specific key code write to the key register (default).
A valid SPI write to any register.
When a watchdog timeout event occurs, there are two user
configurable actions the AD5758 can take. The first user
configurable action is to load the DAC output with a user
defined clear code stored in the CLEAR_CODE register. The
second user configurable action is to perform a software reset.
These actions can be enabled via Bit 10 and Bit 9, respectively,
in the WDT_CONFIG register. On a watchdog timeout event
(regardless of Bit 10 or Bit 9 being enabled), a dedicated
WDT_STATUS bit in the status register, as well as a WDT_ERR
bit in the DIGITAL_DIAG_RESULTS register, alerts the user
that the WDT timed out. Note that, after a WDT timeout occurs,
all writes to the DAC_INPUT register, as well as the hardware
or software LDAC events, are ignored until the active WDT
fault flag within the DIGITAL_DIAG_RESULTS register clears.
After this flag clears, the WDT can be restarted by performing a
subsequent WDT reset command.
On power-up, the WDT is disabled by default. The default
timeout setting is 1 sec. The default method to reset the WDT is
to write one specific key and, on timeout, the default action is
to set the relevant flag bits and the FAULT pin. See Table 39 for
the specific register bit details to support the configurability of
the WDT operation.
USER DIGITAL OFFSET AND GAIN CONTROL
The AD5758 has a USER_GAIN register and a USER_OFFSET
register that allow trimming of the gain and offset errors from
the entire signal chain. The 16-bit USER_GAIN register allows
the user to adjust the gain of the DAC channel in steps of 1
LSB. The USER_GAIN register coding is straight binary, as
shown in Table 14. The default code in the USER_GAIN register is
0xFFFF, which results in no gain factor applied to the programmed
output. In theory, the gain can be tuned across the full range of the
output. In practice, the maximum recommended gain trim is
approximately 50% of the programmed range to maintain
accuracy.
D15
1
1
…
0
0
D14 to D1
1
1
…
0
0
D0
1
0
…
1
0
The 16-bit USER_OFFSET register allows the user to adjust the
offset of the DAC channel by −32,768 LSBs to +32,768 LSBs in
steps of 1 LSB. The USER_OFFSET register coding is straight
binary, as shown in Table 15. The default code in the USER_
OFFSET register is 0x8000, which results in zero offset
programmed to the output.
Table 15. Offset Register Adjustment
Gain Adjustment
+32,768 LSBs
+32,767 LSBs
…
No Adjustment (Default)
…
−32,767 LSBs
−32,768 LSBs
D15
1
1
…
1
…
0
0
D13 to D2
1
1
…
0
…
0
0
D0
1
0
…
0
…
1
0
The value (in decimal) that is written to the internal DAC
register can be calculated by
DAC _ Code = D ×
( M + 1)
216
+ C − 215
(1)
where:
D is the code loaded to the DAC_INPUT register.
M is the code in the USER_GAIN register (default code = 216 − 1).
C is the code in the USER_OFFSET register (default code = 215).
Data from the DAC_INPUT register is processed by a digital
multiplier and adder, controlled by the contents of the user
gain and USER_OFFSET registers, respectively. The calibrated
DAC data is then loaded to the DAC, dependent on the state of
the LDAC pin.
Each time data is written to the USER_GAIN or USER_
OFFSET register, the DAC output is not automatically updated.
Instead, the next write to the DAC_INPUT register uses these
user gain and user offset values to perform a new calibration
and automatically updates the channel. The read only DAC_
OUTPUT register represents the value currently available at the
DAC output, except in the case of user gain and user offset
calibration. In this case, the DAC_OUTPUT register represents
the DAC data input by the user, on which the calibration is
performed and not the result of the calibration.
Both the USER_GAIN register and the USER_OFFSET register
have 16 bits of resolution. The correct method to calibrate the gain
and offset is to first calibrate the gain and then calibrate the offset.
Rev. B | Page 39 of 69
AD5758
Data Sheet
DAC OUTPUT UPDATE AND DATA INTEGRITY
DIAGNOSTICS
Figure 82 shows a simplified version of the DAC input loading
circuitry. If used, the USER_GAIN and USER_OFFSET registers
must be updated before writing to the DAC_INPUT register.
REFIN
OUTPUT
AMPLIFIER
DAC OUTPUT
REGISTER
(READ ONLY)
16-BIT
DAC
VIOUT
LDAC
(HARDWARE OR SOFTWARE)
CLEAR EVENT
(WDT TIMEOUT)
USER
GAIN AND OFFSET
CALIBRATION
SCLK
SYNC
SDI
DAC INPUT
REGISTER
INTERFACE LOGIC
Figure 82. Simplified Serial Interface of Input Loading Circuitry
Rev. B | Page 40 of 69
SDO
11840-026
CLEAR CODE
REGISTER
Data Sheet
AD5758
•
•
•
•
If a write is performed to the DAC_INPUT register with the
hardware LDAC pin tied low, the DAC_OUTPUT register is
updated on the rising edge of SYNC and is subject to the
timing specifications in Table 2.
If the hardware LDAC pin is high and a write to the
DAC_INPUT register occurs, the DAC_OUTPUT register
does not update until a software LDAC instruction is
issued or the hardware LDAC pin is pulsed low.
If a WDT timeout occurs with the CLEAR_ON_WDT_
FAIL bit set, the CLEAR_CODE register contents are
loaded into the DAC_OUTPUT register.
If the slew rate control feature is enabled, the DAC_
OUTPUT register contains the dynamic value of the
DAC as it slews between values.
Note that, while a WDT fault is active, all writes to the DAC_
INPUT register, as well as hardware or software LDAC events,
are ignored. If the CLEAR_ON_WDT_FAIL bit is set such that
the output is set to the clear code, when the WDT fault flag
clears, the DAC_INPUT register must be written to before an
update to the DAC_OUTPUT register occurs; that is, performing a
software or hardware LDAC only reloads the DAC with the clear
code. As described in the Programming Sequence to Enable the
Output section, after configuring the DAC range via the DAC_
CONFIG register, a write to the DAC_INPUT register must
occur, even if the contents of the DAC_INPUT register are not
changing from their current value.
The GP_CONFIG2 register contains a bit to enable a global
software LDAC mode, whereby the AD5758 address bits of the
SW_LDAC command are ignored, thus enabling multiple
AD5758 devices to be simultaneously updated using a single
SW_LDAC command. This feature is useful if the hardware
LDAC pin is not being used in a system containing multiple
AD5758 devices.
DAC Data Integrity Diagnostics
To protect against transient changes to the internal digital
circuitry, the digital block stores both the digital DAC value
and an inverted copy of the digital DAC value. A check is
completed to ensure that the two values correspond to each
other before the DAC is strobed to update to the DAC code.
This feature is enabled by default via the INVERSE_DAC_
CHECK_EN bit in the DIGITAL_DIAG_CONFIG register.
Outside of the digital block, the DAC code is stored in latches,
as shown in Figure 83. These latches are potentially vulnerable
to the same transient events as those protected against within
the digital block. To protect the DAC latches against such
transients, the DAC latch monitor feature can be enabled via
the DAC_LATCH_MON_EN bit within the DIGITAL_DIAG_
CONFIG register. This feature monitors the actual digital code
driving the DAC and compares it with the digital code generated
within the digital block. Any difference between the two codes
causes the DAC_LATCH_MON_ERR flag to be set in the
DIGITAL_DIAG_RESULTS register.
DAC LATCHES
DIGITAL
BLOCK
Q
D
Q
D
16-BIT
DAC
Q
Q
11840-028
The DAC_OUTPUT register (and ultimately the DAC output)
updates in any of the following cases:
Figure 83. DAC Data Integrity
USE OF KEY CODES
Key codes (via the key register) are used for the following
functions (see the Key Register section for full details):
• Initiate calibration memory refresh.
• Initiate a software reset.
• WDT reset key.
Using specific keys for initiating such actions as a calibration
memory refresh or a device reset provides extra system
robustness because it reduces the probability of either of these
tasks being initiated in error.
SOFTWARE RESET
A software reset requires two consecutive writes to the key register,
0x15FA and 0xAF51, respectively. A reset of the device can be
initiated via the hardware RESET pin, the software reset keys,
or automatically after a WDT timeout (if configured to do so).
The RESET_OCCURRED bit in the DIGITAL_DIAG_
RESULTS register flags when the device is reset. This bit
defaults to 1 on power-up. Both of the diagnostic results
registers implement a write 1 to clear feature; that is, a 1 must
be written to this bit to clear it (see the Sticky Diagnostic
Results Bits section).
CALIBRATION MEMORY CRC
For every calibration memory refresh cycle (which is initiated
via a key code write to the key register or automatically initiated
when the range bits, Bits[3:0] of the DAC_CONFIG register,
are changed), an automatic CRC is calculated on the contents
of the calibration memory shadow registers. The result of this
CRC is compared with the factory stored reference CRC value.
If the CRC values match, the read of the entire calibration
memory is considered valid. If they do not match, the CAL_
MEM_CRC_ERR bit in the DIGITAL_DIAG_RESULTS register
is set to 1. This feature is enabled by default and can be disabled
via the CAL_MEM_CRC_EN bit in the
DIGITAL_DIAG_CONFIG register.
While this calibration memory refresh cycle is active, two stage
readback commands are permitted, but a write to any register
(other than the TWO_STAGE_READBACK_SELECT register
or the NOP register) causes the INVALID_SPI_ACCESS_ERR
bit in the DIGITAL_DIAG_RESULTS register to set. As described
in the Programming Sequence to Enable the Output section, a
wait period of 500 µs is recommended after a calibration
memory refresh cycle is initiated.
Rev. B | Page 41 of 69
AD5758
Data Sheet
INTERNAL OSCILLATOR DIAGNOSTICS
An internal frequency monitor uses the internal oscillator (MCLK)
to increment a 16-bit counter at a rate of 1 kHz (MCLK/10,000).
The value of the counter is available to be read in the FREQ_
MONITOR register. The user can poll this register periodically
and use it both as a diagnostic tool for the internal oscillator
(to monitor that the oscillator is running), and to measure the
frequency. This feature is enabled by default via the FREQ_
MON_EN bit in the DIGITAL_DIAG_CONFIG register.
In the event that the internal MCLK oscillator stops, the
AD5758 sends a specific code of 0x07DEAD to the SDO line for
every SPI frame. This feature is enabled by default and can be
disabled by clearing the OSC_STOP_DETECT_EN bit in the
GP_CONFIG1 register. Note that this feature is limited to the
maximum readback timing specifications as outlined in Table 3.
STICKY DIAGNOSTIC RESULTS BITS
The AD5758 contains two diagnostic results registers: digital
and analog (see Table 44 and Table 45, respectively). The
diagnostic result bits contained within these registers are sticky
(R/W-1-C), that is, each bit needs a 1 to be written to it to clear
it. A more appropriate word here is update rather than clear
because if the fault is still present, even after writing a 1 to the
bit in question, it does not clear to 0. Upon writing Logic 1 to
the bit, it updates to its latest value, which is Logic 1 if the fault
is still present and Logic 0 if the fault is no longer present.
There are two exceptions to this R/W-1-C access within the
DIGITAL_DIAG_RESULTS register: CAL_MEMORY_
UNREFRESHED and SLEW_BUSY. These flags automatically
clear when the calibration memory refresh or output slew,
respectively, is complete.
The status register contains a DIG_DIAG_STATUS and
ANA_DIAG_STATUS bit, which is the result of a logical OR of
the diagnostic results bits contained in each of the diagnostic
results registers. All analog diagnostic flag bits are included in
the logical OR of the ANA_DIAG_STATUS bit and all digital
diagnostic flag bits, with the exception of the SLEW_BUSY bit,
are included in the logical OR of the DIG_DIAG_STATUS bit.
The OR’d bits within the status register are read only and not
sticky (R/W-1-C).
BACKGROUND SUPPLY AND TEMPERATURE
MONITORING
Excessive die temperature and overvoltage are known to be related
to common cause failures. These conditions can be monitored in
a continuous fashion using comparators, eliminating the
requirement to poll the ADC.
exceeds the programmed limit, the relevant status bit in the
ANALOG_DIAG_RESULTS register is set and the FAULT pin is
asserted low.
The low voltage supplies on the AD5758 are monitored via low
power static comparators. This function is disabled by default
and can be enabled via the COMPARATOR_CONFIG bits in
the GP_CONFIG2 register. Note that the INT_EN bit in the
DAC_CONFIG register must be set for the REFIN buffer to be
powered up and for this node to be available to the REFIN
comparator. The monitored nodes are REFIN, REFOUT, VLDO,
and an internal AVCC voltage node (INT_AVCC). There is a status
bit in the ANALOG_DIAG_RESULTS register corresponding to
each monitored node. If any of the supplies exceed the upper
or lower threshold values (see Table 16), the corresponding
status bit is set. Note that, in the case of a REFOUT fault, the
REFOUT_ERR status bit is set. In this case, the INT_AVCC,
VLDO, and temperature comparator status bits may also become
set because REFOUT is used as the comparison voltage for
these nodes. Like all the other status bits in the ANALOG_
DIAG_RESULTS register, these bits are sticky and need a 1 to
be written to them to clear them, assuming that the error
condition subsided. If the error condition is still present, the
flag remains high, even after a 1 is written to clear it.
Table 16. Comparator Supply Activation Thresholds
Supply
INT_AVCC
VLDO
REFIN
REFOUT
Lower
Threshold (V)
3.8
2.8
2.24
2.24
Nominal
Value/Range (V)
4 to 5
3 to 3.6
2.5
2.5
Upper
Threshold (V)
5.2
3.8
2.83
2.83
OUTPUT FAULT
The AD5758 is equipped with a FAULT pin. This pin is an active
low, open-drain output allowing several AD5758 devices to be
connected together to one pull-up resistor for global fault
detection. This pin is high impedance when no faults are
detected and is asserted low when certain faults are detected,
for example, an open circuit in current mode, a short circuit in
voltage mode, a CRC error, or an overtemperature error. Table 17
shows the fault conditions that automatically force the FAULT
pin active and highlights the user maskable fault bits available
via the FAULT_PIN_CONFIG register (see Table 42). Note
that all registers contain a corresponding FAULT pin status bit,
FAULT_PIN_STATUS, that mirrors the inverted current state
of the FAULT pin. For example, if the FAULT pin is active, the
FAULT_PIN_STATUS bit is 1.
Both die have a built-in temperature sensor with an accuracy of
typically ±5oC. The die temperature is monitored by a
comparator. The background temperature comparator is
permanently enabled. Programmable trip points corresponding
to 142°C, 127°C, 112°C, and 97°C can be configured in the
GP_CONFIG1 register. If the temperature of the either die
Rev. B | Page 42 of 69
Data Sheet
AD5758
Table 17. FAULT Pin Trigger Sources1
Fault Type
Digital Diagnostic Faults
Oscillator Stop Detect
Calibration Memory Not Refreshed
Reset Detected
3-Wire Interface Error
WDT Error
3-Wire Read and Compare Parity
Error
DAC Latch Monitor Error
Inverse DAC Check Error
Calibration Memory CRC Error
Invalid SPI Access
SCLK Count Error
Slip Bit Error
SPI CRC Error
Analog Diagnostic Faults
VIOUT Overvoltage Error
DC-to-DC Short Circuit Error
DC-to-DC Power Error
Current Output Open Circuit Error
Voltage Output Short-Circuit Error
DC-to-DC Die Temperature Error
Main Die Temperature Error
REFFOUT Comparator Error
REFIN Comparator Error
INT_AVCC Comparator Error
VLDO Comparator Error
1
2
Mapped to
FAULT Pin
Mask
Ability
Yes
No
No
Yes
Yes
Yes
Yes
N/A
N/A
No
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
No
No
No
No
The DIG_DIAG_STATUS, ANA_DIAG_STATUS, and WDT_
STATUS bits of the status register are used in conjunction with
the FAULT pin and the FAULT_PIN_STATUS bit to inform
the user which one of the fault conditions caused the FAULT
pin or the FAULT_PIN_STATUS bit to be activated.
ADC MONITORING
The AD5758 incorporates a 12-bit ADC to provide diagnostic
information on user-selectable inputs, such as supplies, grounds,
internal die temperatures, references, and external signals. See
Table 18 for a full list of the selectable inputs. The reference used
for the ADC is derived from REFOUT, providing a means of
independence from the DAC reference (REFIN), if necessary.
The ADC_CONFIG register configures the selection of the
multiplexed ADC input channel via the ADC_IP_SELECT bits
(see Table 41).
ADC Transfer Function Equations
The ADC has an input range of 0 V to 2.5 V and can be used to
digitize a variety of different nodes. The set of inputs to the ADC
encompasses both unipolar and bipolar ranges, varying from
high to low voltage values. Therefore, to be able to digitize them,
the voltage ranges outside of the 0 V to 2.5 V ADC input range
must be divided down. The ADC transfer function equation is
dependent on the selected ADC input node (see Table 18 for a
summary of all transfer function equations).
N/A means not applicable.
Although the SCLK count error cannot be masked in the FAULT_PIN_CONFIG
register, it can be excluded from the FAULT pin by enabling the SPI_DIAG_
QUIET_EN bit (Bit D3 in the GP_CONFIG1 register).
Table 18. ADC Input Node Summary
ADC_IP_SELECT
00000
00001
00010
00011
00100
00101
00110
01100
01101
01110
10000
10001
10010
10011
10100
10101
10110
VIN Node Description
Main die temperature
DC-to-dc die temperature
Reserved
REFIN
Internal 1.23 V reference voltage (REF2)
Reserved
Reserved
Reserved
Voltage on the +VSENSE buffer output
Voltage on the −VSENSE buffer output
Reserved
Reserved
Reserved
Reserved
INT_AVCC
VLDO
VLOGIC
ADC Transfer Function
T (°C) = (−0.09369 × D) + 307
T (°C) = (−0.11944 × D) + 436
Reserved
REFIN (V) = (D/212) × 2.75
REF2 (V) = (D/212) × 2.5
Reserved
Reserved
Reserved
+VSENSE (V) = ((50 × D)/212) − 25
−VSENSE (V) = ((50 × D)/212) − 25
Reserved
Reserved
Reserved
Reserved
INT_AVCC (V) = D/212 × 10
VLDO (V) = D/212 × 10
VLOGIC (V) = D/212 × 10
Rev. B | Page 43 of 69
AD5758
ADC_IP_SELECT
11000
11001
11010
11011
11100
11101
11110
11111
Data Sheet
VIN Node Description
REFGND
AGND
DGND
VDPC+
AVDD2
AVSS
DC-to-dc die node; configured in the DCDC_CONFIG2 register
00: AGND on dc-to-dc die
01: internal 2.5 V supply on dc-to-dc die
10: AVDD1
11: reserved
REFOUT
AVDD2
AGND (dc-dc) (V) = (D/212) × 2.5
Internal 2.5 V (dc-dc) (V) = (D/212) × 5
AVDD1 (V) = D/212 × 37.5
Reserved
REFOUT (V) = (D/212) × 2.5
AVDD1
AGND
POWER MANAGEMENT
BLOCK
VLDO
ADC Transfer Function
REFGND (V) = D/212 × 2.5
AGND (V) = D/212 × 2.5
DGND (V) = D/212 × 2.5
VDPC+ (V) = D/212 × 37.5
AVDD2 (V) = D/212 × 37.5
AVSS (V) = (15 × D/212 − 14) × 2.5
MCLK
10MHz
POWER-ON
RESET
SW+
CALIBRATION
MEMORY
TEMPERATURE,
INTERNAL 2.5V SUPPLY,
DC-TO-DC DIE TO GND
INT_AVCC, REF2
VLOGIC
DGND
CLKOUT
AD0
AD1
RESET
LDAC
SCLK
SDI
SYNC
SDO
FAULT
DIGITAL
BLOCK
DC-TO-DC DIE
3-WIRE INTERFACE
DATA AND
CONTROL
REGISTERS
WATCHDOG
TIMER
PGND1
VDPC+
16
DAC
REG
16
VDPC+
16-BIT
DAC
IOUT
RANGE
SCALING
–
RB
IOUT
RSET
RA
VX
USER GAIN
USER OFFSET
HART_EN
CHART
STATUS
REGISTER
REFERENCE
BUFFERS
+VSENSE BUFFER
REFIN BUFFER
REFOUT
REFOUT
REFGND
TEMPERATURE
SENSOR
VREF
VOUT
RANGE
SCALING
VDPC+
VOUT
VIOUT
–VSENSE
12-BIT
ADC
–VSENSE BUFFER
ANALOG
DIAGNOSTICS
CCOMP
AD5758
AVSS
NOTES
1. GRAY ITEMS REPRESENT DIAGNOSTIC ADC INPUT NODES.
Figure 84. Diagnostic ADC Input Nodes
Rev. B | Page 44 of 69
+VSENSE
11840-041
REFIN
Data Sheet
AD5758
ADC Configuration
ADC Conversion Timing
The ADC muxed input is configured using the
ADC_CONFIG register via ADC_IP_SELECT (Bits[4:0]).
Figure 85 shows an example where autostatus readback mode is
enabled. The status register always contains the last completed
ADC conversion result, together with the associated mux
address, ADC_IP_SELECT.
Table 19. ADC Configuration Register
D7 to D5
000
D4 to D0
ADC input select
During the first ADC conversion command shown, the
contents of the status register are available on the SDO line.
The ADC portion of this data contains the conversion result of
the previously converted ADC node (ADC Conversion Result 0),
as well as the associated channel address. Assuming another
SPI frame is not received while the ADC is busy converting due
to Command 1, the next data to appear on the SDO line contains
the associated conversion result, ADC Conversion Result 1.
However, if an SPI frame is received while the ADC is busy, the
status register contents available on SDO still contain the
previous conversion result and indicates that the ADC_BUSY flag
is high. Any new ADC conversion instructions received while the
ADC_BUSY bit is active are ignored.
This write to the ADC Configuration register initiates a single
conversion on the node currently selected in the ADC input
select bits of the ADC_CONFIG register.
When a conversion is complete, the ADC result is available in the
status register. If a node from the dc-to-dc die is required,
perform this configuration using the
DCDC_ADC_CONTROL_DIAG bits in the DCDC_CONFIG2
register before configuring the ADC.
ADC CONVERSION TIME
SCLK
1
1
24/
32
24/
32
SYNC
INITIATE
CONVERSION 1
ADC CONVERSION
COMMAND NUMBER 2
ADC CONVERSION
COMMAND NUMBER 1
SDI
ASSUME AUTOSTATUS
READBACK IS ALREADY
ENABLED
ADC CONVERSION
RESULT NUMBER 1
ADC CONVERSION
RESULT NUMBER 0
SDO
CONTENTS OF STATUS
REGISTER CLOCKED OUT
1
0
FAULT
PIN
DIG
DIAG
ANA
DIAG
CONTENTS OF STATUS
REGISTER CLOCKED OUT
WDT
STATUS
ADC
BUSY
ADC
ADC
ADC
ADC
ADC
CHN[4]
CHN[0]
DATA[11]
DATA[1]
DATA[0]
NOTES
1. STATUS REGISTER CONTENTS CONTAINING ADC CONVERSION RESULT, CORRESPONDING
ADDRESS, AND ADC BUSY INDICATOR.
Figure 85. ADC Conversion Timing Example
Rev. B | Page 45 of 69
11840-034
D10 to D8
100
AD5758
Data Sheet
REGISTER MAP
WRITING TO REGISTERS
The AD5758 is controlled and configured via 29 on-chip
registers described in the Register Details section. The four
possible access permissions are as follows:
•
•
•
•
R/W: read/write
R: read only
R/W-1-C: read/write 1 to clear
R0/W: read zero/write
Reading from and writing to reserved registers is flagged as an
invalid SPI access (see Table 44). When accessing registers with
reserved bit fields, the default value of those bit fields must be
written. These values are listed in the Reset column of Table 26
to Table 49.
When writing to any register, the format in Table 20 is used. By
default, the SPI CRC is enabled and the input register is 32 bits
wide, with the last eight bits corresponding to the CRC code.
Only frames of exactly 32 bits wide are accepted as valid. If
CRC is disabled, the input register is 24 bits wide;, and 32-bit
frames are also accepted, with the final 8 bits ignored. Table 21
describes the function of Bit D23 to Bit D16. Bit D15 to Bit D0
depend on the register that is being addressed.
Table 20. Writing to a Register
MSB
D23
AD1
D22
AD1
D21
AD0
D20
REG_ADR4
D19
REG_ADR3
D18
REG_ADR2
D17
REG_ADR1
D16
REG_ADR0
LSB
D15 to D0
Data
Table 21. Input Register Decode
Bit
AD1
AD1, AD0
REG_ADR4, REG_ADR3, REG_ADR2,
REG_ADR1, REG_ADR0
Description
Slip bit. This bit must equal the inverse of Bit D22 (that is, AD1).
Used in association with the external pins, AD1 and AD0, to determine which AD5758 device is
being addressed by the system controller. Up to four unique devices can be addressed,
corresponding to the AD1 and AD0 addresses of 0b00, 0b01, 0b10, and 0b11.
Selects which register is written to. See Table 25 for a summary of the available registers.
Rev. B | Page 46 of 69
Data Sheet
AD5758
Two Stage Readback Mode
READING FROM REGISTERS
Two stage readback mode consists of a write to the TWO_
STAGE_READBACK_SELECT register to select the register
location to be read back, followed by a NOP command. To
perform a NOP command, write all zeros to Bits[D15:D0] of
the NOP register. During the NOP command, the contents of
the selected register are available on SDO in the format shown
in Table 22. It is also possible to write a new two stage readback
command during the second frame, such that the corresponding
new data is available on SDO in the subsequent frame (see
Figure 86). Bits[D31:D30] (or Bits[D23:D22], if SPI CRC is not
enabled) = 0b10 are used as part of the synchronization during
readback. The contents of the first write instruction to the TWO_
STAGE_READBACK_SELECT register is shown in Table 23.
The AD5758 has four options for readback mode that can be
configured in the TWO_STAGE_READBACK_SELECT register
(see Table 43). These options are as follows:
•
•
•
•
Two stage readback
Autostatus readback
Shared SYNC autostatus readback
Echo mode
Table 22. SDO Contents for Read Operation
MSB
D23 to D22
0b10
LSB
D21
FAULT pin status
D20 to 16
Register address
D15 to D0
Data
Table 23. Reading from a Register Using Two Stage Readback Mode
D22
AD1
SCLK
D21
AD0
D20
D19
24/
32
1
D18
0x13
D17
D16
[D15:D5]
Reserved
24/
32
1
LSB
D4 D3 D2 D1 D0
READBACK_SELECT[4:0]
24/
32
1
SYNC
SDI
2-STAGE READBACK
*NOP
INPUT WORD SPECIFIES
REGISTER TO BE READ
*ALTERNATIVELY COULD
WRITE ANOTHER
TWO-STAGE READBACK
NOP
SDO
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 86. Two Stage Readback Example
Rev. B | Page 47 of 69
SELECTED REGISTER DATA
CLOCKED OUT
11840-037
MSB
D23
AD1
AD5758
Data Sheet
Autostatus Readback Mode
contents differ from the format shown in Table 22. The
contents of the status register are shown in Table 24.
If autostatus readback mode is selected, the contents of the
status register are available on the SDO line during every SPI
transaction. When reading back the status register, the SDO
The autostatus readback mode can be configured via the
READBACK_MODE bits in the two stage readback select
register (see the Two Stage Readback Select Register section).
Table 24. SDO Contents for a Read Operation on the Status Register
MSB
LSB
D23 D22 D21
D20
D19
D18
D17
D16 to D12 D11 to D0
1
0
FAULT_PIN_STATUS DIG_DIAG_STATUS ANA_DIAG_STATUS WDT_STATUS ADC_BUSY ADC_CH[4:0] ADC_DATA[11:0]
SCLK
1
24/
32
1
24/
32
1
24/
32
SYNC
SDI
ANY WRITE COMMAND
ANY WRITE COMMAND
ANY WRITE COMMAND
ASSUME AUTOSTATUS
READBACK IS ALREADY
ENABLED
CONTENTS OF STATUS
REGISTER CLOCKED OUT
CONTENTS OF STATUS
REGISTER CLOCKED OUT
Figure 87. Autostatus Readback Example
Rev. B | Page 48 of 69
CONTENTS OF STATUS
REGISTER CLOCKED OUT
11840-038
SDO
Data Sheet
AD5758
Shared SYNC Autostatus Readback Mode
Figure 88. The shared SYNC autostatus readback mode can be
configured via the READBACK_MODE bits in the two stage
readback select register (see the Two Stage Readback Select
Register section).
The shared SYNC autostatus readback is a special version of the
autostatus readback mode used to avoid SDO bus contention
when multiple AD5758 devices are sharing the same SYNC line
(whereby AD5758 devices are distinguished from each other
using the hardware address pins). After each valid write to a
device, a flag is set. On the subsequent falling edge of SYNC,
the flag is cleared. This mode behaves in a similar manner to
the normal autostatus readback mode, except that the device
does not output the status register contents on SDO when
SYNC goes low, unless the internal flag is set (that is, the
previous SPI write was valid). Refer to the example shown in
SCLK
1
24/
32
1
24/
32
Echo Mode
Echo mode behaves in a similar manner to the autostatus
readback mode, except that every second readback consists of
an echo of the previous command written to the AD5758. Echo
mode is useful for checking which SPI instruction was received
in the previous SPI frame. Echo mode can be configured via the
READBACK_MODE bits in the two stage readback select
register (see the Two Stage Readback Select Register section).
1
24/
32
24/
32
1
24/
32
1
SYNC
DEVICE 0
FLAG SET
SDI
VALID WR TO DEVICE 0
DEVICE 1
FLAG SET
NO FLAG SET
VALID WR TO DEVICE 1
INVALID WR TO DEVICE 0
DEVICE 0 STATUS REG
DEVICE 1 STATUS REG
DEVICE 0
FLAG SET
VALID WR TO DEVICE 0
DEVICE 1
FLAG SET
VALID WR TO DEVICE 1
DEVICE 0 STATUS REG
Figure 88. Shared SYNC Autostatus Readback Example
PREVIOUS COMMAND
STATUS REGISTER CONTENTS
Figure 89. SDO Contents—Echo Mode
Rev. B | Page 49 of 69
PREVIOUS COMMAND
11840-040
SDO
11840-039
ASSUME SHARED SYNC
AUTOSTATUS READBACK
IS ALREAD Y ENABLED
FOR BOTH DUTS
AD5758
Data Sheet
PROGRAMMING SEQUENCE TO ENABLE THE
OUTPUT
To write to and set up the device from a power-on or reset
condition, use the following procedure:
1.
2.
3.
4.
5.
6.
7.
Perform a hardware or software reset and wait 100 µs.
Perform a calibration memory refresh by writing 0xFCBA to
the key register. Wait a minimum of 500 µs before proceeding
to Step 3 to allow time for the internal calibrations to
complete. As an alternative to waiting 500 µs for the
refresh cycle to complete, poll the
CAL_MEM_UNREFRESHED bit in the
DIGITAL_DIAG_RESULTS register until it is 0.
Write 1 to Bit D13 in the DIGITAL_DIAG_RESULTS
register to clear the RESET_OCCURRED flag.
If CLKOUT is required, configure and enable this feature
via the GP_CONFIG1 register. It is important to configure
this feature before enabling the dc-to-dc converter.
Write to the DCDC_CONFIG2 register to set the dc-to-dc
current limit. Wait 300 µs to allow the 3-wire interface
communication to complete. As an alternative to waiting
300 µs for the 3-wire interface communication to
complete, poll the BUSY_3WI bit in the
DCDC_CONFIG2 register until it is 0.
Write to the DCDC_CONFIG1 register to set up the dcto-dc converter mode (thereby enabling the dc-to-dc
converter). Wait 300 µs to allow the 3-wire interface
communication to complete. As an alternative to waiting
300 µs to the 3-wire interface communication to complete,
poll the BUSY_3WI bit in the DCDC_CONFIG2 register
until it is 0.
Write to the DAC_CONFIG register to set the INT_EN bit
(powers up the DAC and internal amplifiers without enabling
the output) and configure the output range, internal/external
RSET, and slew rate. Keep the OUT_EN bit disabled at this
point. Wait 500 µs minimum before proceeding to Step 8 to
allow time for the internal calibrations to complete. As an
alternative to waiting 500 µs for the refresh cycle to
complete, poll the CAL_MEM_ UNREFRESHED bit in the
DIGITAL_DIAG_RESULTS register until it is 0.
8. Write zero-scale DAC code to the DAC_INPUT register.
(If a bipolar range was selected in Step 7, then a DAC code
that represents a 0 mA/0 V output must be written to the
DAC_INPUT register). It is important that this step be
completed even if the contents of the DAC_INPUT
register are not changing.
9. If LDAC functionality is being used, perform either a
software or hardware LDAC command.
10. Rewrite the same word to the DAC_CONFIG register as in
Step 7 except, this time, with the OUT_EN bit enabled.
Allow 1.25 ms minimum between Step 6 and Step 9; this is
the time from when the dc-to-dc is enabled to when the
VIOUT output is enabled.
11. Write the required DAC code to the DAC_INPUT
register.
An example configuration is shown in Figure 90.
Changing and Reprogramming the Range
After the output is enabled, use the following recommended
steps when changing the output range:
1.
2.
3.
4.
5.
Rev. B | Page 50 of 69
Write to the DAC_INPUT register. Set the output to 0 mA
or 0 V.
Write to the DAC_CONFIG register. Disable the output
(OUT_EN = 0), and set the new output range. Keep the
INT_EN bit set. Wait 500 µs minimum before proceeding
to Step 3 to allow time for internal calibrations to
complete.
Write Code 0x0000 (in the case of bipolar ranges, write
Code 0x8000) to the DAC_INPUT register. It is important
that this step be completed even if the contents of the
DAC_INPUT register are not changing.
Reload the DAC_CONFIG register word from Step 2 except,
this time, set the OUT_EN bit to 1 to enable the output.
Write the required DAC code to the DAC_INPUT
register.
Data Sheet
AD5758
EXAMPLE CONFIGURATION TO ENABLE THE OUTPUT CORRECTLY
1. PERFORM HARDWARE OR
SOFTWARE RESET
ADDRESS[D23:D21]
WRITE
2. PERFORM CALIBRATION
MEMORY REFRESH
SLIPBIT + AD[1:0]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
0x08
0xFCBA
WAIT = 0
IS CAL_MEM_
UNREFRESHED
== 0?
NO
IS WAIT
= 500µs?
NO
WAIT = WAIT + 1
3. CLEAR RESET_
OCCURRED BIT
WRITE
4. CONFIGURE CLKOUT
IF REQUIRED
WRITE
5. SET UP THE
DC‐TO‐DC CONVERTER
SETTINGS
WRITE
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x14
D13 = 1
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x09
GP CONFIG1 SETTINGS
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x0C
DC-TO-DC SETTINGS
WAIT = 0
IS BUSY_3WI
== 0?
NO
IS WAIT
= 300µs?
NO
6. SET UP THE
DC‐TO‐DC
CONVERTER MODE
WAIT = WAIT + 1
WRITE
ADDRESS[D23:D20]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x0B
DC-TO-DC MODE
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x06
D6 = 0
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x01
DAC CODE
ADDRESS[D23:D21]
REGISTER ADDRESS[D19:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x07
0x1DAC
ADDRESS[D23:D21]
REGISTER ADDRESS[D19:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x06
D6 = 1
ADDRESS[D23:D21]
REGISTER ADDRESS[D20:D16]
DATA[D15:D0]
SLIPBIT + AD[1:0]
0x01
DAC CODE
WAIT = 0
IS BUSY_3WI
= 0?
NO
IS WAIT
= 300µs?
NO
WAIT = WAIT + 1
WRITE
7. CONFIGURE THE DAC
(OUTPUT DISABLED)
WAIT = 0
NO
IS WAIT
= 500µs?
NO
8. WRITE 0mV/0mA
DAC CODE
9. PERFORM AN LDAC COMMAND
WAIT = WAIT + 1
WRITE
WRITE
10. CONFIGURE THE DAC
(OUTPUT ENABLED)
WRITE
11. WRITE THE REQUIRED
DAC CODE
WRITE
Figure 90. Example Configuration to Enable the Output Correctly (CRC Disabled for Simplicity)
Rev. B | Page 51 of 69
11840-118
IS CAL_MEM_
UNREFRESHED
= 0?
AD5758
Data Sheet
REGISTER DETAILS
Table 25. Register Summary
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
Name
NOP
DAC_INPUT
DAC_OUTPUT
CLEAR_CODE
USER_GAIN
USER_OFFSET
DAC_CONFIG
SW_LDAC
Key
GP_CONFIG1
GP_CONFIG2
DCDC_CONFIG1
DCDC_CONFIG2
Reserved
Reserved
WDT_CONFIG
DIGITAL_DIAG_CONFIG
ADC_CONFIG
FAULT_PIN_CONFIG
TWO_STAGE_READBACK_SELECT
DIGITAL_DIAG_RESULTS
ANALOG_DIAG_RESULTS
Status
CHIP_ID
FREQ_MONITOR
Reserved
Reserved
Reserved
DEVICE_ID_3
Description
NOP register.
DAC input register.
DAC output register.
Clear code register.
User gain register.
User offset register.
DAC configuration register.
Software LDAC register.
Key register.
General-Purpose Configuration 1 register.
General-Purpose Configuration 2 register.
DC-to-DC Configuration 1 register.
DC-to-DC Configuration 2 register.
Reserved (do not write to this register).
Reserved (do not write to this register).
WDT configuration register.
Digital diagnostic configuration register.
ADC configuration register.
FAULT pin configuration register.
Two stage readback select register.
Digital diagnostic results register.
Analog diagnostic results register.
Status register.
Chip ID register.
Frequency monitor register.
Reserved.
Reserved.
Reserved.
Generic ID register.
Rev. B | Page 52 of 69
Reset
0x000000
0x010000
0x020000
0x030000
0x04FFFF
0x058000
0x060C00
0x070000
0x080000
0x090204
0x0A0200
0x0B0000
0x0C100
0x0D0000
0x0E0000
0x0F0009
0x10005D
0x110000
0x120000
0x130000
0x14A000
0x150000
0x100000
0x170101
0x180000
0x190000
0x1A0000
0x1B0000
0x1C0000
Access
R0/W
R/W
R
R/W
R/W
R/W
R/W
R0/W
R0/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W-1-C
R/W-1-C
R
R
R
R
R
R
R
Data Sheet
AD5758
NOP Register
Address: 0x00, Reset: 0x000000, Name: NOP
Write 0x0000 to Bits[D15:D0] at this address to perform a no operation (NOP) command. Bits[15:0] of this register always read back as 0x0000.
Table 26. Bit Descriptions for NOP
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
NOP command
Register address.
Write 0x0000 to perform a NOP command.
0x0
0x0
R
R0/W
DAC Input Register
Address: 0x01, Reset: 0x010000, Name: DAC_INPUT
Bits[D15:D0] consists of the 16-bit data to be written to the DAC. If the LDAC pin is tied low (that is, active), the DAC_INPUT register
contents are written directly to the DAC_OUTPUT register without any LDAC functionality dependence. If the LDAC pin is tied high,
the contents of the DAC_INPUT register are written to the DAC_OUTPUT register when the LDAC pin is brought low or when the
software LDAC command is written.
Table 27. Bit Descriptions for DAC_INPUT
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
DAC_INPUT_DATA
Register address.
DAC input data.
0x0
0x0
R
R/W
DAC Output Register
Address: 0x02, Reset: 0x020000, Name: DAC_OUTPUT
DAC_OUTPUT is a read only register and contains the latest calibrated 16-bit DAC output value. If a clear event occurs due to a WDT
fault, this register contains the clear code until the DAC is updated to another code.
Table 28. Bit Descriptions for DAC_OUTPUT
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
DAC_OUTPUT_DATA
Register address.
DAC output data. For example, the last calibrated 16-bit DAC output value.
0x0
0x0
R
R
Clear Code Register
Address: 0x03, Reset: 0x030000, Name: CLEAR_CODE
When writing to the CLEAR_CODE register, Bits[D15:D0] consist of the clear code to which the DAC clears on the occurrence of a clear
event (for example, a WDT fault). After a clear event, the DAC_INPUT register must be rewritten to with the 16-bit data to be written to
the DAC, even if it is the same data as previously written before the clear event. Performing an LDAC write (either hardware or software)
does not update the DAC_OUTPUT register to a new code until the DAC_INPUT register is first written to.
Table 29. Bit Descriptions for CLEAR_CODE
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
CLEAR_CODE
Register address.
Clear code. The DAC clears to this code upon a clear event, for example, a WDT fault.
0x0
0x0
R
R/W
Rev. B | Page 53 of 69
AD5758
Data Sheet
User Gain Register
Address: 0x04, Reset: 0x04FFFF, Name: USER_GAIN
The 16-bit USER_GAIN register allows the user to adjust the gain of the DAC channel in steps of 1 LSB. The USER_GAIN register
coding is straight binary. The default code is 0xFFFF. In theory, the gain can be tuned across the full range of the output. In practice, the
maximum recommended gain trim is approximately 50% of the programmed range to maintain accuracy.
Table 30. Bit Descriptions for USER_GAIN
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
USER_GAIN
Register address.
User gain correction code.
0x0
0xFFFF
R
R/W
User Offset Register
Address: 0x05, Reset: 0x058000, Name: USER_OFFSET
The 16-bit USER_OFFSET register allows the user to adjust the offset of the DAC channel by −32,768 LSBs to +32,768 LSBs in steps of 1 LSB.
The USER_OFFSET register coding is straight binary. The default code is 0x8000, which results in zero offset programmed to the output.
Table 31. Bit Descriptions for USER_OFFSET
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
USER_OFFSET
Register address.
User offset correction code.
0x0
0x8000
R
R/W
DAC Configuration Register
Address: 0x06, Reset: 0x060C00, Name: DAC_CONFIG
This register configures the DAC (range, internal/external RSET, and output enable), enables the output stage circuitry, and configures the
slew rate control function.
Table 32. Bit Descriptions for DAC_CONFIG
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:13]
REGISTER_ADDRESS
SR_STEP
0x0
0x0
R
R/W
[12:9]
SR_CLOCK
Register address.
Slew rate step. In conjunction with the slew rate clock, the slew rate step defines by
how much the output value changes at each update. Together, both parameters
define the rate of change of the output value.
000: 4 LSB (default).
001: 12 LSB.
010: 64 LSB.
011: 120 LSB.
100: 256 LSB.
101: 500 LSB.
110: 1820 LSB.
111: 2048 LSB.
Slew rate clock. Slew rate clock defines the rate at which the digital slew is updated.
0000: 240 kHz.
0001: 200 kHz.
0010: 150 kHz.
0011: 128 kHz.
0100: 64 kHz.
0101: 32 kHz.
0110: 16 kHz (default).
0111: 8 kHz.
0x6
R/W
Rev. B | Page 54 of 69
Data Sheet
Bits
Bit Name
8
SR_EN
7
RSET_EXT_EN
6
OUT_EN
5
INT_EN
4
OVRNG_EN
[3:0]
Range
AD5758
Description
1000: 4 kHz.
1001: 2 kHz.
1010: 1 kHz.
1011: 512 Hz.
1100: 256 Hz.
1101: 128Hz.
1110: 64 Hz.
1111: 16 Hz.
Enable slew rate control.
0: disable (default).
1: enable.
Enable external current setting resistor.
0: select internal RSET resistor (default).
1: select external RSET resistor.
Enable VIOUT.
0: disable VIOUT output (default).
1: enable VIOUT output.
Enable internal buffers.
0: disable (default).
1: enable. Setting this bit powers up the DAC and internal amplifiers. Setting this bit
does not enable the output. It is recommended to set this bit and allow a >200 μs
delay before enabling the output. This delay results in a reduced output enable glitch.
Enable 20% voltage overrange.
0: disable (default).
1: enable.
Select output range. Note that changing the contents of the range bits initiates an
internal calibration memory refresh and, therefore, a subsequent SPI write must not be
performed until the CAL_MEM_UNREFRESHED bit in the DIGITAL_DIAG_RESULTS register
returns to 0. Writes to invalid range codes are ignored.
0000: 0 V to 5 V voltage range (default).
0001: 0 V to 10 V voltage range.
0010: ±5 V voltage range.
0011: ±10 V voltage range.
1000: 0 mA to 20 mA current range.
1001: 0 mA to 24 mA current range.
1010: 4 mA to 20 mA current range.
1011: ±20 mA current range.
1100: ±24 mA current range.
1101: −1 mA to +22 mA current range.
Reset
Access
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Software LDAC Register
Address: 0x07, Reset: 0x070000, Name: SW_LDAC
Writing 0x1DAC to this register performs a software LDAC update on the device matching the ADDRESS bits within the SPI frame. If
the GLOBAL_SW_LDAC bit in the GP_CONFIG2 register is set, the AD0 and AD1 bits are ignored and all devices sharing the same SPI
bus are updated via the SW_LDAC command. Bits[15:0] of this register always read back as 0x0000.
Table 33. Bit Descriptions for SW_LDAC
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
LDAC_COMMAND
Register address.
Software LDAC. Write 0x1DAC to this register to perform a software LDAC instruction.
0x0
0x0
R
R0/W
Rev. B | Page 55 of 69
AD5758
Data Sheet
Key Register
Address: 0x08, Reset: 0x080000, Name: Key
This register accepts specific key codes to perform tasks such as calibration memory refresh and software reset. Bits[15:0] of this register
always read back as 0x0000. All unlisted key codes are reserved.
Table 34. Bit Descriptions for Key
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
KEY_CODE
Register address.
Key code.
0x15FA: first of two keys to initiate a software reset.
0xAF51: second of two keys to initiate a software reset.
0x0D06: key to reset the WDT.
0xFCBA: key to initiate a calibration memory refresh to the shadow registers. This key
is only valid the first time it is run and has no effect if subsequent writes occur within a
given system reset cycle.
0x0
0x0
R
R0/W
General-Purpose Configuration 1 Register
Address: 0x09, Reset: 0x090204, Name: GP_CONFIG1
This register is used to configure functions such as the temperature comparator threshold and CLKOUT, as well as enabling other
miscellaneous features.
Table 35. Bit Descriptions for GP_CONFIG1
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:14]
[13:12]
REGISTER_ADDRESS
Reserved
SET_TEMP_THRESHOLD
0x0
0x0
0x0
R
R
R/W
[11:10]
CLKOUT_CONFIG
0x0
R/W
[9:7]
CLKOUT_FREQ
0x4
R/W
6
HART_EN
Register address.
Reserved. Do not alter the default value of this bit.
Set the temperature comparator threshold value.
00: 142°C (default).
01: 127°C.
10: 112°C.
11: 97°C.
Configure the CLKOUT pin.
00: disable; no clock is output on the CLKOUT pin (default).
01: enable; clock is output on CLKOUT pin according to the CLKOUT_FREQ bits
(Bits[9:7]).
10: reserved (do not select this option).
11: reserved (do not select this option).
Configure the frequency of CLKOUT.
000: 416 kHz.
001: 435 kHz.
010: 454 kHz.
011: 476 kHz.
100: 500 kHz (default).
101: 526 kHz.
110: 555 kHz.
111: 588 kHz.
Enable the path to the CHART pin.
0: output of the DAC drives the output stage directly (default).
1: CHART path is coupled to the DAC output to allow a HART modem connection or
connection of a slew capacitor.
0x0
R/W
Rev. B | Page 56 of 69
Data Sheet
Bits
5
Bit Name
NEG_OFFSET_EN
4
CLEAR_NOW_EN
3
SPI_DIAG_QUIET_EN
2
OSC_STOP_DETECT_EN
1
0
Reserved
Reserved
AD5758
Description
Enable negative offset in unipolar VOUT mode. When set, this bit offsets the
currently enabled unipolar output range by the value listed here. This bit is only
applicable to the 0 V to 6 V range and the 0 V to 12 V range. The 0 V to 6 V range
becomes −300 mV to 5.7 V; the 0 V to 12 V range becomes −400 mV to 11.6 V.
0: disable (default).
1: enable.
Enables clear to occur immediately, even if the output slew feature is currently enabled.
0: disable (default).
1: enable.
Enable SPI diagnostic quiet mode. When this bit is enabled, SPI_CRC_ERR, SLIPBIT_ERR,
and SCLK_COUNT_ERR are not included in the logical OR calculation, which creates the
DIG_DIAG_STATUS bit in the status register. They are also masked from affecting
the FAULT pin if this bit is set.
0: disable (default).
1: enable.
Enable automatic 0x07DEAD code on SDO if the internal oscillator (MCLK) stops.
0: disable.
1: enable (default).
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
Reset
0x0
Access
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x0
0x0
R/W
R/W
General-Purpose Configuration 2 Register
Address: 0x0A, Reset: 0x0A0200, Name: GP_CONFIG2
This register is used to configure and enable functions such as the voltage comparators and the global software LDAC.
Table 36. Bit Descriptions for GP_CONFIG2
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the
FAULT pin.
Reset
0x0
Access
R
[20:16]
15
[14:13]
REGISTER_ADDRESS
Reserved
COMPARATOR_CONFIG
0x0
0x0
0x0
R
R0
R/W
12
11
10
Reserved
Reserved
GLOBAL_SW_LDAC
0x0
0x0
0x0
R/W
R/W
R/W
9
FAULT_TIMEOUT
0x1
R/W
[8:5]
Reserved
Register address.
Reserved. Do not alter the default value of this bit.
Enable/disable the voltage comparator inputs for test purposes. The
temperature comparator is permanently enabled. See the Background
Supply and Temperature Monitoring section.
00: disable voltage comparators (default).
01: reserved.
10: reserved.
11: enable voltage comparators. The INT_EN bit in the DAC_CONFIG register
must be set for the REFIN buffer to be powered up and this node available to
the REFIN comparator.
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
When enabled, the address bits are ignored when performing a software
LDAC command, enabling multiple devices to be simultaneously updated
using one SW_LDAC command.
0: disable (default).
1: enable.
Enable reduced fault detect timeout. This bit configures the delay from when
the analog block indicates a VIOUT fault has been detected to the associated
change of the relevant bit in the ANALOG_DIAG_RESULTS register. This
feature provides flexibility to accommodate a variety of output load values.
0: fault detect timeout = 25 ms.
1: fault detect timeout = 6.5 ms (default).
Reserved. Do not alter the default value of these bits.
0x0
R/W
Rev. B | Page 57 of 69
AD5758
Bits
4
3
2
1
0
Data Sheet
Bit Name
Reserved
Reserved
Reserved
Reserved
Reserved
Description
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
Reserved. Do not alter the default value of this bit.
Reset
0x0
0x0
0x0
0x0
0x0
Access
R/W
R/W
R/W
R/W
R/W
DC-to-DC Configuration 1 Register
Address: 0x0B, Reset: 0x0B0000, Name: DCDC_CONFIG1
This register is used to configure the dc-to-dc controller mode.
Table 37. Bit Descriptions for DCDC_CONFIG1
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:8]
7
[6:5]
REGISTER_ADDRESS
Reserved
Reserved
DCDC_MODE
0x0
0x0
0x0
0x0
R
R0
R/W
R/W
[4:0]
DCDC_VPROG
Register address.
Reserved. Do not alter the default value of these bits.
Reserved. Do not alter the default value of this bit.
These two bits configure the dc-to-dc converters.
00: DC-to-DC converter powered off (default).
01: DPC current mode. The positive DPC rail tracks the headroom of the current
output buffer.
10: DPC voltage mode. The positive DPC rail is regulated to 15 V with respect to
−VSENSE.
11: PPC current mode. VDPC+ is regulated to a user programmable level between 5 V
and 25.677 V (depending on the DCDC_VPROG bits, Bits[4:0]) with respect to −VSENSE.
The ENABLE_PPC_BUFFERS bit (Bit 11 in the ADC_CONFIG register) must be set prior
to enabling PPC current mode.
DC-to-dc programmed voltage in PPC mode. VDPC+ is regulated to a user programmable
level between 5 V (0b00000) and 25.677 V (0b11111), in steps of 0.667 V. VDPC+ is
regulated with respect to −VSENSE.
0x0
R/W
DC-to-DC Configuration 2 Register
Address: 0x0C, Reset: 0x0C0100, Name: DCDC_CONFIG2
This register configures various dc-to-dc die features, such as the dc-to-dc converter current limit and the dc-to-dc die node, to be
multiplexed to the ADC.
Table 38. Bit Descriptions for DCDC_CONFIG2
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the
FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:13]
12
REGISTER_ADDRESS
Reserved
BUSY_3WI
0x0
0x0
0x0
R
R0
R
11
INTR_SAT_3WI
0x0
R
10
DCDC_READ_COMP_DIS
Register address.
Reserved. Do not alter the default value of these bits.
Three-wire interface busy indicator.
0: 3-wire interface not currently active.
1: 3-wire interface busy.
Three-wire interface saturation flag. This flag is set to 1 when the
interrupt detection circuitry is automatically disabled due to six
consecutive interrupt signals. A write to either of the dc-to-dc
configuration registers clears this bit to 0.
Disable 3-wire interface read and compare cycle. This read and compare
cycle ensures that the contents of the copy of the dc-to-dc configuration
registers on the main die match the contents on the dc-to-dc die.
0: enable automatic read and compare cycle (default).
0x0
R/W
Rev. B | Page 58 of 69
Data Sheet
AD5758
Bits
Bit Name
[9:8]
7
Reserved
VIOUT_OV_ERR_DEGLITCH
6
VIOUT_PULLDOWN_EN
[5:4]
DCDC_ADC_CONTROL_DIAG
[3:1]
DCDC_ILIMIT
0
Reserved
Description
1: when set, this bit disables the automatic read and compare cycle
after each 3-wire interface write.
Reserved. Do not alter the default value of these bits.
Adjust the deglitch time on VIOUT overvoltage error flag.
0: deglitch time set to 1.02 ms (default).
1: deglitch time set to 128 μs.
Enable the 30 kΩ resistor to ground on VIOUT.
0: disable (default).
1: enable.
Select which dc-to-dc die node is multiplexed to the ADC on the
main die.
00: AGND on dc-to-dc die.
01: internal 2.5 V supply on dc-to-dc die.
10: AVDD1.
11: reserved (do not select this option).
These three bits set the dc-to-dc converter current limit.
000: 150 mA (default).
001: 200 mA.
010: 250 mA.
011: 300 mA.
100: 350 mA.
101: 400 mA.
110: 400 mA.
111: 400 mA.
Reserved. Do not alter the default value of this bit.
Reset
Access
0x1
0x0
R/W
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Watchdog Timer (WDT) Configuration Register
Address: 0x0F, Reset: 0x0D0009, Name: WDT_CONFIG
This register configures the WDT timeout values. This register also configures the WDT setup in terms of acceptable resets and the
resulting response to a WDT fault (for example, clear the output or reset the device).
Table 39. Bit Descriptions for WDT_CONFIG
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:11]
10
REGISTER_ADDRESS
Reserved
CLEAR_ON_WDT_FAIL
0x0
0x0
0x0
R
R
R/W
9
RESET_ON_WDT_FAIL
0x0
R/W
8
KICK_ON_VALID_WRITE
0x0
R/W
7
6
Reserved
WDT_EN
0x0
0x0
R/W
R/W
[5:4]
Reserved
Register address.
Reserved. Do not alter the default value of these bits.
Enable clear on WDT fault. If the WDT times out, a clear event occurs, whereby the
output is loaded with the clear code stored in the CLEAR_CODE register.
0: disable (default).
1: enable.
Enable a software reset to automatically occur if the WDT times out.
0: disable (default).
1: enable.
Enable any valid SPI command to reset the WDT. Any active WDT error flags must
be cleared before the WDT can be restarted.
0: disable (default).
1: enable.
Reserved. Do not alter the default value of this bit.
Enables the WDT, then starts the WDT, assuming there are no active WDT fault flags.
0: disable (default).
1: enable.
Reserved. Do not alter the default value of these bits.
0x0
R/W
Rev. B | Page 59 of 69
AD5758
Bits
[3:0]
Bit Name
WDT_TIMEOUT
Data Sheet
Description
Set the WDT timeout value. Setting WDT_TIMEOUT to a binary value beyond
0b1010 results in the default setting of 1 sec.
0000: 1 ms.
0001: 5 ms.
0010: 10 ms.
0011: 25 ms.
0100: 50 ms.
0101: 100 ms.
0110: 250 ms.
0111: 500 ms.
1000: 750 ms.
1001: 1 sec (default).
1010: 2 sec.
Reset
0x9
Access
R/W
Digital Diagnostic Configuration Register
Address: 0x10, Reset: 0x10005D, Name: DIGITAL_DIAG_CONFIG
This register configures various digital diagnostic features of interest for a particular application.
Table 40. Bit Descriptions for DIGITAL_DIAG_CONFIG
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:9]
[8:7]
6
REGISTER_ADDRESS
Reserved
Reserved
DAC_LATCH_MON_EN
0x0
0x0
0x0
0x1
R
R0
R/W
R/W
5
4
Reserved
INVERSE_DAC_CHECK_EN
0x0
0x1
R/W
R/W
3
CAL_MEM_CRC_EN
0x1
R/W
2
FREQ_MON_EN
0x1
R/W
1
0
Reserved
SPI_CRC_EN
Register address.
Reserved. Do not alter the default value of these bits.
Reserved. Do not alter the default value of these bits.
Enable a diagnostic monitor on the DAC latches. This feature monitors the actual
digital code driving the DAC and compares it with the digital code generated
within the digital block. Any difference between the two codes causes the
DAC_LATCH_MON_ERR flag to be set in the DIGITAL_DIAG_RESULTS register.
0: disable.
1: enable (default).
Reserved. Do not alter the default value of this bit.
Enable check for DAC code vs. inverse DAC code error.
0: disable.
1: enable (default).
Enable CRC of calibration memory on a calibration memory refresh.
0: disable.
1: enable (default).
Enable the internal frequency monitor on the internal oscillator (MCLK).
0: disable.
1: enable (default).
Reserved. Do not alter the default value of this bit.
Enable SPI CRC function.
0: disable.
1: enable (default).
0x0
0x1
R/W
R/W
Rev. B | Page 60 of 69
Data Sheet
AD5758
ADC Configuration Register
Address: 0x11, Reset: 0x110000, Name: ADC_CONFIG
This register configures the ADC into one of four modes of operation: key sequencing, automatic sequencing, single immediate
conversion of the currently selected ADC_IP_SELECT node, or single-key conversion.
Table 41. Bit Descriptions for ADC_CONFIG
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:12]
11
[10:8]
REGISTER_ADDRESS
Reserved
ENABLE_PPC_BUFFERS
SEQUENCE_COMMAND
0x0
0x0
0x0
0x0
R
R/W
R/W
R/W
[7:5]
[4:0]
Reserved
ADC_IP_SELECT
Register address. Do not alter the default value.
Reserved. Do not alter the default value of these bits.
Enable the sense buffers for PPC mode.
ADC sequence command bits.
000: reserved (do not select this option).
001: reserved (do not select this option).
010: reserved (do not select this option).
011: reserved (do not select this option).
100: initiate a single conversion on the ADC_IP_SELECT (Bits[4:0]) input.
101: reserved (do not select this option).
110: reserved (do not select this option).
111: reserved (do not select this option).
Reserved. Do not alter the default value of these bits.
Select which node to multiplex to the ADC. All unlisted 5-bit codes are reserved
and return an ADC result of zero.
00000: Main die temperature.
00001: DC-to-dc die temperature.
00010: Reserved (do not select this option).
00011: REFIN. The INT_EN bit in the DAC_CONFIG register must be set for the
REFIN buffer to be powered up and this node to be available to the ADC.
00100: REF2; internal 1.23 V reference voltage.
00101: Reserved (do not select this option).
00110: Reserved (do not select this option).
01100: Reserved (do not select this option).
01101: Voltage on the +VSENSE buffer output.
01110: Voltage on the −VSENSE buffer output
10000: Reserved (do not select this option).
10001: Reserved (do not select this option).
10010: Reserved (do not select this option).
10011: Reserved (do not select this option).
10100: INT_AVCC.
10101: VLDO.
10110: VLOGIC.
11000: REFGND.
11001: AGND.
11010: DGND.
11011: VDPC+.
11100: AVDD2.
11101: AVSS.
11110: DC-to-dc die node; configured in the DCDC_CONFIG2 register.
11111: REFOUT.
0x0
0x0
R/W
R/W
Rev. B | Page 61 of 69
AD5758
Data Sheet
FAULT Pin Configuration Register
Address: 0x12, Reset: 0x120000, Name: FAULT_PIN_CONFIG
This register is used to mask particular fault bits from the FAULT pin, if so desired.
Table 42. Bit Descriptions for FAULT_PIN_CONFIG
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
15
REGISTER_ADDRESS
INVALID_SPI_ACCESS_ERR
Register address.
If this bit is set, do not map the INVALID_SPI_ACCESS_ERR fault flag to the
FAULT pin.
0x0
0x0
R
R/W
14
VIOUT_OV_ERR
If this bit is set, do not map the VIOUT_OV_ERR fault flag to the FAULT pin.
0x0
R/W
13
12
Reserved
INVERSE_DAC_CHECK_ERR
Reserved. Do not alter the default value of this bit.
If this bit is set, do not map the INVERSE_DAC_CHECK_ERR flag to the FAULT pin.
0x0
0x0
R/W
R/W
11
10
Reserved
OSCILLATOR_STOP_DETECT
Reserved. Do not alter the default value of this bit.
If this bit is set, do not map the clock stop error to the FAULT pin.
0x0
0x0
R/W
R/W
9
DAC_LATCH_MON_ERR
If this bit is set, do not map the DAC_LATCH_MON_ERR fault flag to the FAULT pin.
0x0
R/W
8
WDT_ERR
If this bit is set, do not map the WDT_ERR flag to the FAULT pin.
0x0
R/W
7
SLIPBIT_ERR
If this bit is set, do not map the SLIPBIT_ERR error flag to the FAULT pin.
0x0
R/W
6
5
4
SPI_CRC_ERR
Reserved
DCDC_P_SC_ERR
If this bit is set, do not map the SPI_CRC_ERR error flag to the pin.
Reserved. Do not alter the default value of this bit.
If this bit is set, do not map the positive rail dc-to-dc short circuit error flag to the
FAULT pin.
0x0
0x0
0x0
R/W
R/W
R/W
3
IOUT_OC_ERR
If this bit is set, do not map the current output open-circuit error flag to the FAULT pin.
0x0
R/W
2
VOUT_SC_ERR
If this bit is set, do not map the voltage output short-circuit error flag to the FAULT pin.
0x0
R/W
1
DCDC_DIE_TEMP_ERR
If this bit is set, do not map the dc-to-dc die temperature error flag to the FAULT pin.
0x0
R/W
0
MAIN_DIE_TEMP_ERR
If this bit is set, do not map the main die temperature error flag to the FAULT pin.
0x0
R/W
Two Stage Readback Select Register
Address: 0x13, Reset: 0x130000, Name: TWO_STAGE_READBACK_SELECT
This register selects the address of the register required for a two stage readback operation. The address of the register selected for
readback is stored in Bits[D4:D0].
Table 43. Bit Descriptions for TWO_STAGE_READBACK_SELECT
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:7]
[6:5]
REGISTER_ADDRESS
Reserved
READBACK_MODE
0x0
0x0
0x0
R
R
R/W
[4:0]
READBACK_SELECT
Register address.
Reserved.
These bits control the SPI readback mode.
0: two stage SPI readback mode (default).
01: autostatus readback mode: the status register contents are shifted out on SDO for
every SPI frame.
10: shared SYNC autostatus readback mode. This mode allows the use of a shared SYNC
line on multiple devices (distinguished using the hardware address pins). After each valid
write to a device, a flag is set. This mode behaves similar to the normal autostatus readback mode, except that the device does not output the status register contents on SDO
as SYNC goes low, unless the internal flag is set (that is, the previous SPI write is valid).
11: the status register contents and the previous SPI frame instruction are alternately
available on SDO.
Select readback address for a two stage readback.
0x00: NOP register (default).
0x01: DAC_INPUT register.
0x02: DAC_OUTPUT register.
0x0
R/W
Rev. B | Page 62 of 69
Data Sheet
Bits
Bit Name
AD5758
Description
0x03: CLEAR_CODE register.
0x04: USER_GAIN register.
0x05: USER_OFFSET register.
0x06: DAC_CONFIG register.
0x07: SW_LDAC register.
0x08: Key register.
0x09: GP_CONFIG1 register.
0x0A: GP_CONFIG2 register.
0x0B: DCDC_CONFIG1 register.
0x0C: DCDC_CONFIG2 register.
0x0D: Reserved (do not select this option).
0x0E: Reserved (do not select this option).
0x0F: WDT_CONFIG register.
0x10: DIGITAL_DIAG_CONFIG register.
0x11: ADC_CONFIG register.
0x12: FAULT_PIN_CONFIG register.
0x13: TWO_STAGE_READBACK_SELECT register.
0x14: DIGITAL_DIAG_RESULTS register.
0x15: ANALOG_DIAG_RESULTS register.
0x16: Status register.
0x17: CHIP_ID register.
0x18: FREQ_MONITOR register.
0x19: Reserved (do not select this option).
0x1A: Reserved (do not select this option).
0x1B: Reserved (do not select this option).
0x1C: DEVICE_ID_3 register.
Reset
Access
Digital Diagnostic Results Register
Address: 0x14, Reset: 0x14A000, Name: DIGITAL_DIAG_RESULTS
This register contains an error flag for the on-chip digital diagnostic features, most of which are configurable using the digital diagnostic
configuration register. This register also contains a flag to indicate that a reset occurred, as well as a flag to indicate that the calibration
memory has not refreshed or an invalid SPI access attempted. With the exception of the CAL_MEM_UNREFRESHED and SLEW_BUSY
flags, all of these flags require a 1 to be written to them to update them to their current value. The CAL_MEM_UNREFRESHED and
SLEW_BUSY flags automatically clear when the calibration memory refresh or output slew, respectively, is complete. When the
corresponding enable bits in the DIGITAL_DIAG_CONFIG register are not enabled, the respective flag bits read as zero.
Table 44. Bit Descriptions for DIGITAL_DIAG_RESULTS
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
15
REGISTER_ADDRESS
CAL_MEM_UNREFRESHED
0x0
0x1
R
R
14
SLEW_BUSY
0x0
R
13
12
11
10
RESET_OCCURRED
ERR_3WI
WDT_ERR
Reserved
Register address.
Calibration memory unrefreshed flag. Note that modifying the range bits in
the DAC_CONFIG register also initiates a calibration memory refresh, which
asserts this bit. Unlike the R/W-1-C bits in this register, this bit is automatically
cleared after the calibration memory refresh completes.
0: calibration memory is refreshed.
1: calibration memory is unrefreshed (default on power-up). Note that this
bit asserts if the range bits are modified in the DAC_CONFIG register.
This flag is set to 1 when the DAC is actively slewing. Unlike the R/W-1-C bits
in this register, this bit is automatically cleared when slewing is complete.
This bit flags that a reset occurred (default on power-up is therefore Logic 1).
This bit flags an error in the interdie 3-wire interface communications.
This bit flags a WDT fault.
Reserved.
0x1
0x0
0x0
0x0
R/W-1-C
R/W-1-C
R/W-1-C
R/W-1-C
Rev. B | Page 63 of 69
AD5758
Data Sheet
Bits
9
Bit Name
3WI_RC_ERR
8
7
6
DAC_LATCH_MON_ERR
Reserved
INVERSE_DAC_CHECK_ERR
5
CAL_MEM_CRC_ERR
4
INVALID_SPI_ACCESS_ERR
3
2
Reserved
SCLK_COUNT_ERR
1
SLIPBIT_ERR
0
SPI_CRC_ERR
Description
This bit flags an error if the 3-wire read and compare process is enabled and
a parity error occurs.
This bit flags if the output of the DAC latches does not match the input.
Reserved.
This bit flags if a fault it detected between the DAC code driven by the
digital core and an inverted copy.
This bit flags a CRC error for the CRC calculation of the calibration memory
upon refresh.
This bit flags if an invalid SPI access is attempted, such as writing to or
reading from an invalid or reserved address. This bit also flags if an SPI write
is attempted directly after powering up but before a calibration memory
refresh is performed or if an SPI write is attempted while a calibration
memory refresh is in progress. Performing a two stage readback is permitted
during a calibration memory refresh and does not cause this flag to set.
Attempting to write to a read only register also causes this bit to assert.
Reserved.
This bit flags an SCLK falling edge count error. 32 clocks are required if SPI
CRC is enabled and 24 clocks or 32 clocks are required if SPI CRC is not enabled.
This bit flags an SPI frame slip bit error, that is, the MSB of the SPI word is not
equal to the inverse of MSB − 1.
This bit flags an SPI CRC error.
Reset
0x0
Access
R/W-1-C
0x0
0x0
0x0
R/W-1-C
R/W-1-C
R/W-1-C
0x0
R/W-1-C
0x0
R/W-1-C
0x0
0x0
R/W-1-C
R/W-1-C
0x0
R/W-1-C
0x0
R/W-1-C
Analog Diagnostic Results Register
Address: 0x15, Reset: 0x150000, Name: ANALOG_DIAG_RESULTS
This register contains an error flag corresponding to the four voltage nodes (VLDO, INT_AVCC, REFIN, and REFOUT) monitored in
the background by comparators, as well as a flag for each die temperature, which is also monitored by comparators. Voltage output short
circuit, current output open circuit and dc-to-dc error flags are also contained in this register. Like the DIGITAL_DIAG_RESULTS
register, all of the flags contained in this register require a 1 to be written to them to update or clear them. When the corresponding
diagnostic features are not enabled, the respective error flags are read as zero.
Table 45. Bit Descriptions for ANALOG_DIAG_RESULTS
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:14]
13
12
11
10
9
REGISTER_ADDRESS
Reserved
VIOUT_OV_ERR
Reserved
DCDC_P_SC_ERR
Reserved
DCDC_P_PWR_ERR
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R
R0
R/W-1-C
R/W-1-C
R/W-1-C
R/W-1-C
R/W-1-C
8
7
Reserved
IOUT_OC_ERR
0x0
0x0
R/W-1-C
R/W-1-C
6
5
4
3
VOUT_SC_ERR
DCDC_DIE_TEMP_ERR
MAIN_DIE_TEMP_ERR
REFOUT_ERR
0x0
0x0
0x0
0x0
R/W-1-C
R/W-1-C
R/W-1-C
R/W-1-C
2
1
REFIN_ERR
INT_AVCC_ERR
Register address.
Reserved.
This bit flags if the voltage at the VIOUT pin goes outside of the VDPC+ rail or AVSS rail.
Reserved.
This bit flags a dc-to-dc short-circuit error for the positive rail dc-to-dc circuit.
Reserved.
This bit flags a dc-to-dc regulation fault, that is, the dc-to-dc circuitry cannot reach
the target VDPC+ voltage due to an insufficient AVDD1 voltage.
Reserved.
This bit flags a current output open circuit error. This error bit is set in the case of a
current output open circuit and in the case where there is insufficient headroom
available to the internal current output driver circuitry to provide the programmed
output current.
This bit flags a voltage output short-circuit error.
This bit flags an overtemperature error for the dc-to-dc die.
This bit flags an overtemperature error for the main die.
This bit flags that the REFOUT node is outside of the comparator threshold levels
or if its short-circuit current limit occurs.
This bit flags that the REFIN node is outside of the comparator threshold levels.
This bit flags that the INT_AVCC node is outside of the comparator threshold
levels.
0x0
0x0
R/W-1-C
R/W-1-C
Rev. B | Page 64 of 69
Data Sheet
Bits
0
Bit Name
VLDO_ERR
AD5758
Description
This bit flags that the VLDO node is outside of the comparator threshold levels or if
its short-circuit current limit occurs.
Reset
0x0
Access
R/W-1-C
Status Register
Address: 0x16, Reset: 0x100000, Name: Status
This register contains ADC data and status bits, as well as the WDT, OR'd analog and digital diagnostics, and the FAULT pin status bits.
Table 46. Bit Descriptions for Status
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
20
DIG_DIAG_STATUS
0x1
R
19
ANA_DIAG_STATUS
0x0
R
18
17
[16:12]
[11:0]
WDT_STATUS
ADC_BUSY
ADC_CH
ADC_DATA
This bit represents the result of a logical OR of the contents of Bits[15:0] in the
DIGITAL_DIAG_RESULTS register, with the exception of the SLEW_BUSY bit. Therefore,
if any of these bits are high, the DIG_DIAG_STATUS bit is high. Note that this bit is high
on power-up due to the active RESET_OCCURRED flag. A quiet mode is also available
(SPI_DIAG_QUIET_EN in the GP_CONFIG1 register), such that the logical OR function
only incorporates Bits[D15:D3] of the DIGITAL_DIAG_RESULTS register (with the
exception of the SLEW_BUSY bit). If an SPI CRC, SPI slip bit, or SCLK count error occurs,
the DIG_DIAG_STATUS bit is not set high.
This bit represents the result of a logical OR of the contents of Bits[13:0] in the
ANALOG_DIAG_RESULTS register. Therefore, if any bit in this register is high, the
ANA_DIAG_STATUS bit is high.
WDT status bit.
ADC busy status bit.
Address of the ADC channel represented by the ADC_DATA bits in the status register.
12 bits of ADC data representing the converted signal addressed by the ADC_CH bits,
Bits[4:0].
0x0
0x0
0x0
0x0
R
R
R
R
Chip ID Register
Address: 0x17, Reset: 0x170101, Name: CHIP_ID
This register contains the silicon revision ID of both the main die and the dc-to-dc die.
Table 47. Bit Descriptions for CHIP_ID
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:11]
[10:8]
[7:0]
REGISTER_ADDRESS
Reserved
DCDC_DIE_CHIP_ID
MAIN_DIE_CHIP_ID
Register address.
Reserved.
These bits reflect the silicon revision number of the dc-to-dc die.
These bits reflect the silicon revision number of the main die.
0x0
0x0
0x2
0x2
R
R0
R
R
Frequency Monitor Register
Address: 0x18, Reset: 0x180000, Name: FREQ_MONITOR
An internal frequency monitor uses the internal oscillator (MCLK) to create a pulse at a frequency of 1 kHz (MCLK/10,000). This pulse
is used to increment a 16-bit counter. The value of the counter is available to read in the FREQ_MONITOR register. The user can poll
this register periodically and use it both as a diagnostic tool for the internal oscillator (to monitor that the oscillator is running) and to measure
the frequency. This feature is enabled by default via the FREQ_MON_EN bit in the DIGITAL_DIAG_CONFIG register.
Table 48. Bit Descriptions for FREQ_MONITOR
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:0]
REGISTER_ADDRESS
FREQ_MONITOR
Register address.
Internal clock counter value.
0x0
0x0
R
R
Rev. B | Page 65 of 69
AD5758
Data Sheet
Generic ID Register
Address: 0x1C, Reset: 0x1C0000, Name: DEVICE_ID_3
Table 49. Bit Descriptions for DEVICE_ID_3
Bits
21
Bit Name
FAULT_PIN_STATUS
Description
The FAULT_PIN_STATUS bit reflects the inverted current status of the FAULT pin.
Reset
0x0
Access
R
[20:16]
[15:8]
[7:3]
[2:0]
REGISTER_ADDRESS
Reserved
Reserved
Generic ID
Register address.
Reserved.
Reserved.
Generic ID.
000: reserved
001: reserved
010: AD5758
011: reserved
100: reserved
101: reserved
110: reserved
111: reserved
0x0
0x0
0x0
0x0
R
R
R
R
Rev. B | Page 66 of 69
Data Sheet
AD5758
APPLICATIONS INFORMATION
EXAMPLE MODULE POWER CALCULATION
Using the example module shown in Figure 91, the module
power dissipation (excluding the power dissipated in the load)
can be calculated using the methodology shown in the Power
Calculation Methodology (RLOAD = 1 kΩ) section. Assuming
a maximum IOUT value of 20 mA and RLOAD value of 1 kΩ, the
total module power is calculated as approximately 226 mW.
Note that power associated with the external digital isolation is
not included in the calculations because this power is dependent
on the choice of component used.
Replacing the 1 kΩ load with a short circuit, the power dissipation
calculation is shown in the Power Calculation Methodology
(RLOAD = 0 Ω) section, which shows that the total module power
becomes approximately 206 mW in a short-circuit load condition.
Power Calculation Methodology (RLOAD = 1 kΩ)
Current (mA)
AIDD1 = 0.05
AIDD2 = 2.9
AISS = 0.23
ILOGIC = 0.01
Assuming an 85% efficiency ADP1031, the total input power
becomes 625.5 mW (see Figure 91).
Total Module Power = Input Power − Load Power
Therefore,
625.5 mW − 400 mW = 225.5 mW
Power Calculation Methodology (RLOAD = 0 Ω)
Using the voltage and current values in Table 50, the total
quiescent current power is 19.18 mW.
Next,
Table 50. Quiescent Current Power Calculation
Voltage (V)
AVDD1 = 24
AVDD2 = 5
AVSS = −15
VLOGIC = 3.3
Assume the dc-to-dc converter is at 90% efficiency. Therefore,
VDPC+ power = 512.5 mW. The total input power at the AD5758
side of the ADP1031 PMU is therefore 512.5 mW + 19.18 mW =
531.68 mW. Subtracting the 400 mW load power from this
value gives the power associated only with the AD5758, which
is 131.68 mW.
(VDPC+) × (20 mA + IDPC+) = 4.95 V × 20.5 mA = 101.5 mW
Power (mW)
1.2
14.5
3.45
0.033
Assume the dc-to-dc converter at 65% efficiency. Therefore,
VDPC+ power = 156.2 mW. The total input power at the AD5758
side of the ADP1031 is therefore 156.2 mW + 19.18 mW =
175.38 mW. Subtracting the 0 mW load power from this value
gives the power associated only with the AD5758, which is
175.38 mW.
Using the voltage and current values in Table 50, the total
quiescent current power is 19.18 mW.
Next, perform the following calculation:
(VDPC+) × (20 mA + IDPC+) = 22.5 V × 20.5 mA = 461.25 mW
Assuming an 85% efficiency ADP1031, the total input power
becomes 206.33 mW (see Figure 91).
Total Module Power = Input Power − Load Power
Therefore,
206.33 mW − 0 mW = 206.33 mW
Rev. B | Page 67 of 69
AD5758
Data Sheet
1:1
D1
+24V
VINP
RFT1
CFLYBK
4.7µF
Tx1
RFB1
SWP
FB1
SGND2
VOUT1
VINP
SW2
EN
R6
PGNDP
VOUT3
GNDP
FB3
SLEW
SW3
MVDD
R3
PGOOD
FAULT
LDAC
RESET
ADuCM3029
L1
100µH
CBUCK
4.7µF
MGPO3
100kΩ
ADP1031
MGPI1
SGPI3
MGND
SGPO2
MOSI
MISO
GND
PGND
47µH
100nF
SGPO1
SVDD2
MVDD
SGND2
SVDD1
SGND1
CLK
L2
100µH
MGPI2
MVDD
CS
RFT3
CINV
4.7µF
SYNC
PWRGD
C2
100nF
VBAT
–12V
RFB3
MSS
SSS
SCK
MCK
SI
MO
C3
100nF
100kΩ
100kΩ
CLKOUT
100nF
C4
100nF
MGND
AVSS
100nF
AVDD2
AVDD1 SW+
VDPC+
VLDO
1kΩ
VLOGIC
+VSENSE
SYNC
SCLK
VIOUT
AD5758
10Ω
OUTPUT
SCREW
TERMINAL
SDI
CCOMP
SDO
SO
MI
100nF
2.2µF
100kΩ
FAULT
–VSENSE
LDAC
RESET
DGND AD1 AD0 REFOUT REFIN
MGND
RA
RB
13.7kΩ
DGND
CHART AGND
RLOAD
1kΩ
RETURN
SCREW
AGND TERMINAL
AGND
HART SIGNAL
11840-092
PGNDP
+5.15V
VOUT2
R5
CIN
4.7µF
Figure 91. Example Module Containing the ADP1031 and the AD5758
DRIVING INDUCTIVE LOADS
When driving large inductive loads or poorly defined loads, a
snubbing network may be required between VIOUT and AGND
to minimize ringing. An example of a snubbing network is a
series 300 Ω resistor and capacitor (with a value between 2.5 nF
and 10 nF) between VIOUT and AGND. In cases where a large
inductive load is present, the digital slew rate control of the
AD5758 can be used to minimize ringing when stepping the
output current by minimizing the dI/dt of the current step.
ELECTROMAGNETIC COMPATIBILITY (EMC)
CONSIDERATIONS
There are three minimum mandatory components for EMC
and electromagnetic interference (EMI).
•
•
•
A 10 Ω resistor on the trace between the VIOUT pin and the
output screw terminal limits the transient current to and
from the device.
A transient voltage suppression (TVS) diode directly
routed between the VIOUT and RETURN screw terminal
with short and heavy traces. The TVS diode is crucial to
clamp any electrical transient during EMC events.
A 10 nF, 50 V, X7R capacitor located in parallel to the TVS
diode diverts the small amount of high frequency transient
to the RETURN screw terminal.
Optional clamp diodes to AVDD1 and AVSS can be added to
the VIOUT line to further improve the robustness. Refer to the
AN-1599 Application Note for more information.
Rev. B | Page 68 of 69
Data Sheet
AD5758
OUTLINE DIMENSIONS
0.30
0.25
0.18
25
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
32
24
1
0.50
BSC
3.70
3.60 SQ
3.50
EXPOSED
PAD
17
TOP VIEW
1.00
0.95
0.85
END VIEW
PKG-004754/005209
SEATING
PLANE
0.50
0.40
0.30
8
9
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-5
09-12-2018-A
PIN 1
INDICATOR
AREA
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
Figure 92. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.95 mm Package Height
(CP-32-30)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
AD5758BCPZ-RL7
EVAL-AD5758SDZ
1
2
Temperature Range
−40°C to +115°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
USB interface board, EVAL-SDP-CS1Z, must be ordered separately when ordering the EVAL-AD5758SDZ.
©2018–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11840-3/20(B)
Rev. B | Page 69 of 69
Package Option
CP-32-30
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