AD7329

1 MSPS, 8-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC AD7329 FEATURES 12-bit plus sign SAR ADC True bipolar input ranges Software-selectable input ranges ±10 V, ±5 V, ±2.5 V, 0 V to +10 V 1 MSPS throughput rate Eight analog input channels with channel sequencer Single-ended true differential and pseudo differential analog input capability High analog input impedance MUXOUT and ADCIN pins allow separate access to mux and ADC Low power: 21 mW Temperature indicator Full power signal bandwidth: 20 MHz Internal 2.5 V reference High speed serial interface iCMOS™ process technology 24-lead TSSOP package Power-down modes FUNCTIONAL BLOCK DIAGRAM MUXOUT+ MUXOUT– ADC IN– ADC IN+ VDD REFIN/REFOUT VCC 2.5V VREF VIN0 VIN1 VIN2 VIN3 VIN4 VIN5 VIN6 VIN7 DOUT CHANNEL SEQUENCER CONTROL LOGIC AND REGISTERS SCLK CS DIN 05402-001 I/P MUX T/H 13-BIT SUCCESSIVE APPROXIMATION ADC AD7329 VSS AGND VDRIVE Figure 1. GENERAL DESCRIPTION The AD7329 1 is an 8-channel, 12-bit plus sign successive approximation ADC designed on the iCMOS (industrial CMOS) process. iCMOS is a process combining high voltage CMOS and low voltage CMOS. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage parts could achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can accept bipolar input signals while providing increased performance, dramatically reduced power consumption, and reduced package size. The AD7329 can accept true bipolar analog input signals. The AD7329 has four software-selectable input ranges, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V. Each analog input channel can be independently programmed to one of the four input ranges. The analog input channels on the AD7329 can be programmed to be single-ended, true differential, or pseudo differential. The ADC contains a 2.5 V internal reference. The AD7329 also allows for external reference operation. If a 3 V reference is applied to the REFIN/REFOUT pin, the AD7329 can accept a true bipolar ±12 V analog input. The ADC has a high speed serial interface that can operate at throughput rates up to 1 MSPS. PRODUCT HIGHLIGHTS 1. 2. The AD7329 can accept true bipolar analog input signals, ±10 V, ±5 V, ±2.5 V, and 0 V to +10 V unipolar signals. The eight analog inputs can be configured as eight singleended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. 1 MSPS serial interface. SPI®-/QSPI™-/DSP-/MICROWIRE™compatible interface. Low power, 21 mW, at 1 MSPS. MUXOUT and ADCIN pins allow for signal conditioning of the mux output prior to entering the ADC. 3. 4. 5. Table 1. Similar Devices Device Number AD7328 AD7327 AD7324 AD7323 AD7322 AD7321 1 Throughput Rate 1000 kSPS 500 kSPS 1000 kSPS 500 kSPS 1000 kSPS 500 kSPS Number of Channels 8 8 4 4 2 2 Protected by U.S. Patent No. 6,731,232. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD7329 TABLE OF CONTENTS Features .............................................................................................. 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 7 Absolute Maximum Ratings............................................................ 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 11 Terminology .................................................................................... 15 Theory of Operation ...................................................................... 17 Circuit Information.................................................................... 17 Converter Operation.................................................................. 17 Output Coding............................................................................ 18 Transfer Functions...................................................................... 18 Analog Input Structure.............................................................. 18 Track-and-Hold Section ............................................................ 19 Typical Connection Diagram ................................................... 20 Analog Input ............................................................................... 20 Driver Amplifier Choice............................................................ 23 Registers........................................................................................... 25 Addressing Registers.................................................................. 25 Control Register ......................................................................... 26 Sequence Register....................................................................... 28 Range Registers........................................................................... 28 Sequencer Operation ..................................................................... 29 Reference ..................................................................................... 31 VDRIVE ............................................................................................ 31 Temperature Indicator............................................................... 31 Modes of Operation ....................................................................... 32 Normal Mode.............................................................................. 32 Full Shutdown Mode.................................................................. 32 Autoshutdown Mode ................................................................. 33 Autostandby Mode..................................................................... 33 Power vs. Throughput Rate....................................................... 34 Serial Interface ................................................................................ 35 Microprocessor Interfacing........................................................... 36 AD7329 to ADSP-21xx.............................................................. 36 AD7329 to ADSP-BF53x ........................................................... 36 Outline Dimensions ....................................................................... 37 Ordering Guide .......................................................................... 37 REVISION HISTORY 4/06—Revision 0: Initial Version Rev. 0 | Page 2 of 40 AD7329 SPECIFICATIONS VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, fSCLK = 20 MHz, fS = 1 MSPS, TA = TMAX to TMIN, unless otherwise noted. MUXOUT+ is connected directly to ADCIN+ and MUXOUT −is connected directly to ADCIN−, which is connected to GND for single-ended mode. Table 2. Parameter 1 DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 2 Signal-to-Noise + Distortion (SINAD)2 Min 76 72.5 75 B Version Typ 77 74 76.5 76.5 73.5 73.5 Total Harmonic Distortion (THD)2 −87 −85 −82 −80 Peak Harmonic or Spurious Noise (SFDR)2 −88 −86 −84 −82 Intermodulation Distortion (IMD) 2 Second-Order Terms Third-Order Terms Aperture Delay 3 Aperture Jitter3 Common-Mode Rejection (CMRR)2 Channel-to-Channel Isolation2 Full Power Bandwidth −80 −80 −77 Max Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB Test Conditions/Comments fIN = 50 kHz sine wave Differential mode Single-ended/pseudo differential mode Differential mode; ±2.5 V and ±5 V ranges Differential mode; 0 V to +10 V and ±10 V ranges Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges Differential mode; ±2.5 V and ±5 V ranges Differential mode; 0 V to +10 V and ±10 V ranges Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges Differential mode; ±2.5 V and ±5 V ranges Differential mode; 0 V to +10 V and ±10 V ranges Single-ended/pseudo differential mode; ±2.5 V and ±5 V ranges Single-ended/pseudo differential mode; 0 V to +10 V and ±10 V ranges fa = 50 kHz, fb = 30 kHz 72 −78 −88 −90 7 50 −79 −75 20 1.5 dB dB ns ps dB dB MHz MHz Up to 100 kHz ripple frequency; see Figure 17 fIN on unselected channels up to 100 kHz; see Figure 14 At 3 dB At 0.1 dB Rev. 0 | Page 3 of 40 AD7329 Parameter 1 DC ACCURACY 4 Resolution No Missing Codes Min B Version Typ Max Unit Test Conditions/Comments All dc accuracy specifications are typical for 0 V to 10 V mode. Differential mode Single-ended/pseudo differential mode Differential mode Single-ended/pseudo differential mode Single-ended/pseudo differential mode (LSB = FSR/8192) Differential mode; guaranteed no missing codes to 13 bits Single-ended mode; guaranteed no missing codes to 12 bits Single-ended/psuedo differential mode (LSB = FSR/8192) Single-ended/pseudo differential mode Differential mode Single-ended/pseudo differential mode Differential mode Single-ended/pseudo differential mode Differential mode Single-ended/pseudo differential mode Differential mode Single-ended/pseudo differential mode Differential mode Single-ended/pseudo differential mode Differential mode Single-ended/pseudo differential mode Differential mode Single-ended/pseudo differential mode Differential mode Single-ended/pseudo differential mode Differential mode Single-ended/pseudo differential mode Differential mode 13 12-bit plus sign 11-bit plus sign ±1.1 ±1 −0.7/+1.2 Bits Bits Bits LSB LSB LSB LSB LSB LSB −4/+9 −7/+10 ±0.6 ±0.5 ±8.0 ±14 ±0.5 ±0.5 ±4 ±7 ±0.5 ±0.5 ±8.5 ±7.5 ±0.5 ±0.5 ±4 ±6 ±0.5 ±0.5 LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB Integral Nonlinearity2 Differential Nonlinearity2 −0.9/+1.5 ±0.9 −0.7/+1 Offset Error2, 5 Offset Error Match2, 5 Gain Error2, 5 Gain Error Match2, 5 Positive Full-Scale Error2, 6 Positive Full-Scale Error Match2, 6 Bipolar Zero Error2, 6 Bipolar Zero Error Match2, 6 Negative Full-Scale Error2, 6 Negative Full-Scale Error Match2, 6 Rev. 0 | Page 4 of 40 AD7329 Parameter 1 ANALOG INPUT Input Voltage Ranges (Programmed via Range Register) Min B Version Typ Max Unit Test Conditions/Comments Reference = 2.5 V; see Table 6 VDD = 10 V min, VSS = −10 V min, VCC = 2.7 V to 5.25 V VDD = 5 V min, VSS = −5 V min, VCC = 2.7 V to 5.25 V VDD = 5 V min, VSS = − 5 V min, VCC = 2.7 V to 5.25 V VDD = 10 V min, VSS = AGND min, VCC = 2.7 V to 5.25 V VDD = 16.5 V, VSS = −16.5 V, VCC = 5 V; see Figure 43 and Figure 44 Reference = 2.5 V; range = ±10 V Reference = 2.5 V; range = ±5 V Reference = 2.5 V; range = ±2.5 V Reference = 2.5 V; range = 0 V to +10 V VIN = VDD or VSS Per channel, VIN = VDD or VSS When in track, all ranges, single ended When in track, ±10 V range, single ended When in track, ±5 V range, single ended When in track, ±2.5 V range, single ended When in track, 0 V to +10 V range, single ended When in hold, all ranges, single ended All ranges, single ended All ranges, single ended ±10 ±5 ±2.5 0 to 10 V V V V Pseudo Differential VIN− Input Range ±3.5 ±6 ±5 +3/−5 DC Leakage Current Input Capacitance3 ADCIN± Capacitance3 3 16 7 10 14.5 10.5 4.0 7.5 13 2.5 10 2.5 ±5 ±10 25 3 7 2.4 0.8 0.4 ±1 10 VDRIVE − 0.2 V 0.4 ±1 5 Straight natural binary Twos complement 3 ±1 ±100 V V V V nA nA pF pF pF pF pF pF pF pF V μA pF V mV mV ppm/°C ppm/°C Ω V V V μA pF V V μA pF MUXOUT− Capacitance3 MUXOUT+ Capacitance3 REFERENCE INPUT/OUTPUT Input Voltage Range Input DC Leakage Current Input Capacitance Reference Output Voltage Reference Output Voltage Error @ 25°C Reference Output Voltage TMIN to TMAX Reference Temperature Coefficient Reference Output Impedance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN3 LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance3 Output Coding VCC = 4.75 V to 5.25 V VCC = 2.7 to 3.6 V VIN = 0 V or VDRIVE ISOURCE = 200 μA ISINK = 200 μA Coding bit set to 1 in control register Coding bit set to 0 in control register Rev. 0 | Page 5 of 40 AD7329 Parameter 1 CONVERSION RATE Conversion Time Track-and-Hold Acquisition Time2, 3 Throughput Rate POWER REQUIREMENTS VDD VSS VCC VDRIVE Normal Mode (Static) Normal Mode (Operational) IDD ISS ICC and IDRIVE Autostandby Mode (Dynamic) IDD ISS ICC and IDRIVE Autoshutdown Mode (Static) IDD ISS ICC and IDRIVE Full Shutdown Mode IDD ISS ICC and IDRIVE POWER DISSIPATION Normal Mode (Operational) Full Shutdown Mode 1 2 3 Min B Version Typ Max 800 300 1 770 Unit ns ns MSPS kSPS V V V V mA μA μA mA μA μA mA μA μA μA μA μA μA mW mW μW Test Conditions/Comments 16 SCLK cycles with SCLK = 20 MHz Full-scale step input; see the Terminology section See the Serial Interface section; VCC = 4.75 V to 5.25 V VCC < 4.75 V Digital inputs = 0 V or VDRIVE See Table 6 See Table 6 See Table 6; typical specifications for VCC < 4.75 V VDD= 16.5, VSS = −16.5 V, VCC = VDRIVE = 5.25 V fSAMPLE = 1 MSPS VDD = 16.5 V VSS = −16.5 V VCC = VDRIVE = 5.25 V fSAMPLE = 250 kSPS VDD = 16.5 V VSS = −16.5 V VCC = VDRIVE = 5.25 V SCLK on or off VDD = 16.5 V VSS = −16.5 V VCC = VDRIVE = 5.25 V SCLK on or off VDD = 16.5 V VSS = −16.5 V VCC = VDRIVE = 5.25 V VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V VDD = 12 V, VSS = −12 V, VCC = 5 V VDD = 16.5 V, VSS = −16.5 V, VCC = 5.25 V 12 −12 2.7 2.7 0.9 16.5 −16.5 5.25 5.25 360 410 3.2 200 210 1.3 1 1 1 1 1 1 30 21 38.25 Temperature range is −40°C to +85°C. See the Terminology section. Sample tested during initial release to ensure compliance. 4 For dc accuracy specifications, the LSB size for differential mode is FSR/8192. For single-ended mode/pseudo differential mode, the LSB size is FSR/4096, unless otherwise noted. 5 Unipolar 0 V to 10 V range with straight binary output coding. 6 Bipolar range with twos complement output coding. Rev. 0 | Page 6 of 40 AD7329 TIMING SPECIFICATIONS VDD = 12 V to 16.5 V, VSS = −12 V to −16.5 V, VCC = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, VREF = 2.5 V internal/external, TA = TMAX to TMIN. Timing specifications apply with a 32 pF load, unless otherwise noted. MUXOUT+ is connected directly to ADCIN+ and MUXOUT −is connected directly to ADCIN−, which is connected to GND for single-ended mode. Table 3. Parameter fSCLK tCONVERT tQUIET t1 t2 1 t3 t4 t5 t6 t7 t8 t9 t10 tPOWER-UP Limit at TMIN, TMAX VCC < 4.75 V VCC = 4.75 V to 5.25 V 50 50 14 20 16 × tSCLK 16 × tSCLK 75 60 12 5 25 20 45 35 26 14 57 43 0.4 × tSCLK 0.4 × tSCLK 0.4 × tSCLK 0.4 × tSCLK 13 8 40 22 10 9 4 4 2 2 750 750 500 500 25 1 Unit kHz min MHz max ns max ns min ns min ns min ns min ns max ns max ns min ns min ns min ns max ns min ns min ns min ns max μs max μs typ Description VDRIVE ≤ VCC 25 tSCLK = 1/fSCLK Minimum time between end of serial read and next falling edge of CS Minimum CS pulse width CS to SCLK set-up time; bipolar input ranges (±10 V, ±5 V, ±2.5 V) Unipolar input range (0 V to 10 V) Delay from CS until DOUT three-state disabled Data access time after SCLK falling edge SCLK low pulse width SCLK high pulse width SCLK to data valid hold time SCLK falling edge to DOUT high impedance SCLK falling edge to DOUT high impedance DIN set-up time prior to SCLK falling edge DIN hold time after SCLK falling edge Power-up from autostandby Power-up from full shutdown/autoshutdown mode, internal reference Power-up from full shutdown/autoshutdown mode, external reference When using VCC = 4.75 V to 5.25 V and the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t2 at 20 ns, the mark space ratio needs to be limited to 50:50. t1 CS t2 SCLK 1 2 3 4 3 IDENTIFICATION BITS t6 tCONVERT 5 13 14 15 16 t3 t4 DB11 t7 DB10 DB2 t5 DB1 DB0 t8 ADD1 DOUT THREE- ADD2 t9 STATE DIN WRITE REG SEL1 ADD0 SIGN tQUIET t10 REG SEL2 MSB LSB 0 THREE-STATE 05402-002 Figure 2. Serial Interface Timing Diagram Rev. 0 | Page 7 of 40 AD7329 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted Table 4. Parameter VDD to AGND, DGND VSS to AGND, DGND VDD to VCC VCC to AGND, DGND VDRIVE to AGND, DGND AGND to DGND Analog Input Voltage to AGND 1 Digital Input Voltage to DGND Digital Output Voltage to GND REFIN to AGND Input Current to Any Pin Except Supplies 2 Operating Temperature Range Storage Temperature Range Junction Temperature TSSOP Package θJA Thermal Impedance θJC Thermal Impedance Pb-Free Temperature, Soldering Reflow ESD 1 Rating −0.3 V to +16.5 V +0.3 V to −16.5 V VCC − 0.3 V to +16.5 V −0.3 V to +7 V −0.3 V to +7 V −0.3 V to +0.3 V VSS − 0.3 V to VDD + 0.3 V −0.3 V to +7 V −0.3 V to VDRIVE + 0.3 V −0.3 V to VCC + 0.3 V ±10 mA −40°C to +85°C −65°C to +150°C 150°C 128°C/W 42°C/W 260(0)°C 2.5 kV Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. If the analog inputs are being driven from alternative VDD and VSS supply circuitry, Schottky diodes should be placed in series with the AD7329’s VDD and VSS supplies. 2 Transient currents of up to 100 mA do not cause SCR latch-up. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 8 of 40 AD7329 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS CS 1 DIN 2 DGND 3 AGND 4 REFIN/REFOUT 5 VSS 6 ADCIN+ 7 MUXOUT+ 8 VIN0 9 VIN1 10 VIN4 11 VIN5 12 24 23 22 SCLK DGND DOUT VDRIVE VCC VDD ADCIN– MUXOUT– VIN2 VIN3 05402-003 AD7329 TOP VIEW (Not to Scale) 21 20 19 18 17 16 15 14 13 VIN6 VIN7 Figure 3. TSSOP Pin Configuration Table 5. Pin Function Descriptions Pin No. 24 22 Mnemonic SCLK DOUT Descriptions Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7329. This clock is also used as the clock source for the conversion process. Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The data stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data. The data is provided MSB first (see the Serial Interface section). Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7329 and frames the serial data transfer. Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register on the falling edge of SCLK (see the Registers section). Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates. This pin should be decoupled to DGND. The voltage at this pin can be different than that at VCC but should not exceed VCC by more than 0.3 V. Digital Ground. Ground reference point for all digital circuitry on the AD7329. The DGND and AGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Analog Ground. Ground reference point for all analog circuitry on the AD7329. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis. Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the AD7329. Alternatively, the internal reference can be disabled and an external reference applied to this input. On power up, this is the default condition. The nominal internal reference voltage is 2.5 V, which appears at this pin. A 680 nF capacitor should be placed on the reference pin (see the Reference section). Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7329. This supply should be decoupled to AGND. Positive Power Supply Voltage. This is the positive supply voltage for the analog input section. Negative Power Supply Voltage. This is the negative supply voltage for the analog input section. Positive ADC Input. This pin allows access to the on-chip track-and-hold. The voltage applied to this pin is still a high voltage signal (±10 V, ±5 V, ±2.5 V, or 0 V to +10 V). Positive Multiplexer Output. The output of the multiplexer appears at this pin. The voltage at this pin is still a high voltage signal equivalent to the voltage applied to the VIN+ input channel, as selected in the control register or sequence register. If no external filtering or buffering is required, this pin should be tied to the ADCIN+ pin. 1 2 21 CS DIN VDRIVE 3, 23 4 DGND AGND 5 REFIN/REFOUT 20 19 6 7 8 VCC VDD VSS ADCIN+ MUXOUT+ Rev. 0 | Page 9 of 40 AD7329 Pin No. 17 Mnemonic MUXOUT− Descriptions Negative Multiplexer Output. This pin allows access to the on-chip track-and-hold. The voltage applied to this pin is still a high voltage signal when the AD7329 is in differential mode. When the AD7329 is in single-ended mode, this signal is AGND, and MUXOUT− can be connected directly to the ADCIN− pin. When the AD7329 is in pseudo differential mode, a small dc voltage appears at this pin, and this pin should be tied to the ADCIN− pin. Negative ADC Input. This pin allows access to the track-and-hold. When the AD7329 is in single-ended mode, this pin can be tied to MUXOUT−, which is connected to AGND. When the AD7329 is in pseudo differential mode, this pin should be connected to MUXOUT−. When the AD7329 is in true differential mode, the voltage applied to this pin is a high voltage signal (±10 V, ±5 V, ±2.5 V, or 0 V to +10 V). Analog Input 0 Through Analog Input 7. The analog inputs are multiplexed into the on-chip track-and-hold. The analog input channel for conversion is selected by programming the channel address bits, ADD2 through ADD0, in the control register. The inputs can be configured as eight single-ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. The configuration of the analog inputs is selected by programming the mode bits, Mode 1 and Mode 0, in the control register. The input range on each input channel is controlled by programming the range registers. Input ranges of ±10 V, ±5 V, ±2.5 V, or 0 V to +10 V can be selected on each analog input channel (see the Range Registers section). On power up, VIN0 is automatically selected and the voltage on this pin appears on MUXOUT+. 18 ADCIN− 9 to 16 VIN0 to VIN7 Rev. 0 | Page 10 of 40 AD7329 TYPICAL PERFORMANCE CHARACTERISTICS 0 –20 –40 4096 POINT FFT VCC = VDRIVE = 5V VDD = 15V, VSS = –15V TA = 25°C INT/EXT 2.5V REFERENCE ±10V RANGE fIN = 50kHz SNR = 77.30dB SINAD = 76.85dB THD = –86.96dB SFDR = –88.22dB 1.0 VCC = VDRIVE = 5V 0.8 TA = 25°C VDD = 15V, VSS = –15V 0.6 INL ERROR (LSB) INT/EXT 2.5V REFERENCE ±10V RANGE +INL = +0.55LSB –INL = –0.68LSB 0.4 0.2 0 –0.2 –0.4 –0.6 SNR (dB) –60 –80 –100 –120 –140 –0.8 05402-004 05402-007 05402-009 05402-008 –1.0 0 50 100 150 200 250 300 350 400 450 500 0 FREQUENCY (kHz) 8192 1024 2048 3072 4096 5120 6144 7168 512 1536 2560 3584 4608 5632 6656 7680 CODE Figure 4. FFT True Differential Mode Figure 7. Typical INL True Differential Mode 0 –20 –40 4096 POINT FFT VCC = VDRIVE = 5V VDD = 15V, VSS = –15V TA = 25°C INT/EXT 2.5V REFERENCE ±10V RANGE fIN = 50kHz SNR = 74.67dB SINAD = 74.03dB THD = –82.68dB SFDR = –85.40dB 1.0 0.8 0.6 DNL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 VCC = VDRIVE = 5V ±10V RANGE TA = 25°C +DNL = +0.79LSB –DNL = –0.38LSB VDD = 15V, VSS = –15V INT/EXT 2.5V REFERENCE 0 8192 1024 2048 3072 4096 5120 6144 7168 512 1536 2560 3584 4608 5632 6656 7680 CODE SNR (dB) –60 –80 –100 –120 –140 –0.8 05402-005 –1.0 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (kHz) Figure 5. FFT Single-Ended Mode Figure 8. Typical DNL Single-Ended Mode 1.0 0.8 0.6 DNL ERROR (LSB) 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 VCC = VDRIVE = 5V TA = 25°C VDD = 15V, VSS = –15V INT/EXT 2.5V REFERENCE ±10V RANGE +DNL = +0.72LSB –DNL = –0.22LSB 05402-006 1.0 0.8 0.6 0.4 INL ERROR (LSB) 0.2 0 –0.2 VCC = VDRIVE = 5V TA = 25°C VDD = 15V, VSS = –15V –0.6 INT/EXT 2.5V REFERENCE ±10V RANGE –0.8 +INL = +0.87LSB –INL = –0.49LSB –1.0 0 8192 1024 2048 3072 4096 5120 6144 7168 512 1536 2560 3584 4608 5632 6656 7680 CODE –0.4 8192 1024 2048 3072 4096 5120 6144 7168 512 1536 2560 3584 4608 5632 6656 7680 CODE Figure 6. Typical DNL True Differential Mode Figure 9. Typical INL Single-Ended Mode Rev. 0 | Page 11 of 40 AD7329 –50 VCC = VDRIVE = 5V V = 12V, V = –12V –55 T DD 25°C SS A= fS = 1MSPS –60 INTERNAL REFERENCE AD8021 BETWEEN MUX OUT+ AND ADCIN+ PINS –65 –70 –75 –80 –85 05402-010 80 75 ±2.5V RANGE 70 ±10V RANGE SINAD (dB) ±10V RANGE ±5V RANGE THD (dB) 0V TO +10V RANGE ±5V RANGE 65 0V TO +10V RANGE –95 10 100 ANALOG INPUT FREQUENCY (kHz) 1000 1000 ANALOG INPUT FREQUENCY (kHz) Figure 10. THD vs. Analog Input Frequency for Single-Ended Mode (SE) at 5 V VCC Figure 13. SINAD vs. Analog Input Frequency for True Differential Mode (Diff) at 5 V VCC –50 CHANNEL-TO-CHANNEL ISOLATION (dB) VCC = VDRIVE = 5V V = 12V, V = –12V –55 T DD 25°C SS A= fS = 1MSPS –60 INTERNAL REFERENCE AD8021 BETWEEN MUX OUT AND ADCIN PINS –65 THD (dB) –50 ±10V RANGE ±5V RANGE –55 –60 –65 –70 –75 –80 –85 –90 –95 –100 0 100 200 VDD = 12V, VSS = –12V VCC = VDRIVE = 5V SINGLE-ENDED MODE 50kHz ON SELECTED CHANNEL fS = 1MSPS TA = 25°C 300 400 500 600 05402-014 05402-015 WIRE LINK WITH AD8021 –70 –75 –80 –85 05402-011 0V TO +10V RANGE ±2.5V RANGE –90 –95 10 100 ANALOG INPUT FREQUENCY (kHz) 1000 FREQUENCY OF INPUT NOISE (kHz) Figure 11. THD vs. Analog Input Frequency for True Differential Mode (Diff) at 5 V VCC Figure 14. Channel-to-Channel Isolation with and Without AD8021 Between the MUXOUT+ and ADCIN + Pins 74 73 72 71 0V TO +10V RANGE 70 69 VCC = VDRIVE = 5V VDD = 12V, VSS = –12V 68 TA = 25°C fS = 1MSPS 67 INTERNAL REFERENCE AD8021 BETWEEN MUX OUT+ AND ADCIN+ PINS 66 100 10 ANALOG INPUT FREQUENCY (kHz) ±10V RANGE ±5V RANGE 10k 9k 9469 NUMBER OF OCCURRENCES ±2.5V RANGE 8k 7k 6k 5k 4k 3k 2k 1k 0 0 –2 228 –1 0 CODE VCC = 5V VDD = 12V, VSS = –12V RANGE = ±10V 10k SAMPLES TA = 25°C SINAD (dB) 05402-012 303 1 0 2 1000 Figure 12. SINAD vs. Analog Input Frequency for Single-Ended Mode (SE) at 5 V VCC Figure 15. Histogram of Codes, True Differential Mode Rev. 0 | Page 12 of 40 05402-013 –90 ±2.5V RANGE 60 VCC = VDRIVE = 5V VDD = 12V, VSS = –12V TA = 25°C 55 fS = 1MSPS INTERNAL REFERENCE AD8021 BETWEEN MUX OUT AND ADCIN PINS 50 10 100 AD7329 8k 7k 7600 2.0 VCC = 5V VDD = 12V, VSS = –12V RANGE = ±10V 10k SAMPLES TA = 25°C 1.5 1.0 INL ERROR (LSB) INL = 1MSPS NUMBER OF OCCURRENCES 6k 5k 4k 3k 2k 1201 1k 0 0 –3 23 –2 –1 0 CODE 0.5 0 –0.5 –1.0 INL = 1MSPS INL = 500kSPS INL = 500kSPS 1165 11 1 2 0 3 05402-016 –1.5 –2.0 ±5 ±5V RANGE VCC = VDRIVE = 5V INTERNAL REFERENCE SINGLE-ENDED MODE AD8021 BETWEEN MUX OUT+ AND ADCIN+ PINS ±11 ±13 ±15 ±17 ±19 05402-019 ±7 ±9 SUPPLY VOLTAGE (V) (VDD = +, VSS = –) Figure 16. Histogram of Codes, Single-Ended Mode Figure 19. INL Error vs. Supply Voltage at 500 kSPS and 1 MSPS –50 –55 –60 –65 –50 –55 –60 –65 PSRR (dB) VCC = 5V 100mV p-p SINE WAVE ON EACH SUPPLY NO DECOUPLING SINGLE-ENDED MODE fS = 1MSPS VCC = 5V VCC = 3V CMRR (dB) –70 –75 –80 –85 –90 –95 –100 0 –70 –75 –80 –85 –90 –95 VCC = 3V DIFFERENTIAL MODE fIN = 50kHz VDD = 12V, VSS = –12V fS = 1MSPS TA = 25°C 05402-017 VDD = 12V VSS = –12V 200 400 600 800 1000 1200 0 200 400 600 800 1000 1200 RIPPLE FREQUENCY (kHz) SUPPLY RIPPLE FREQUENCY (kHz) Figure 17. CMRR vs. Common-Mode Ripple Frequency Figure 20. PSRR vs. Supply Ripple Frequency Without Supply Decoupling 2.0 1.5 1.0 DNL ERROR (LSB) –50 DNL = 500kSPS DIFFERENTIAL MODE –55 VDD = 12V, VSS = –12V VCC = VDRIVE = 5V INTERNAL REFERENCE –60 AD8021 BETWEEN MUX OUT AND ADCIN PINS –65 THD (dB) 0.5 0 –0.5 –1.0 –1.5 –2.0 ±5 DNL = 500kSPS ±5V RANGE VCC = VDRIVE = 5V INTERNAL REFERENCE SINGLE-ENDED MODE AD8021 BETWEEN MUX OUT+ AND ADCIN+ PINS ±13 ±15 ±17 ±19 05402-018 –70 –75 –80 –85 –90 –95 –100 10 100 DNL = 1MSPS DNL = 1MSPS ±10V RANGE RIN = 2000Ω RIN = 1000Ω RIN = 600Ω RIN = 100Ω RIN = 50Ω ±7 ±9 ±11 1000 SUPPLY VOLTAGE (V) (VDD = +, VSS = –) ANALOG INPUT FREQUENCY (kHz) Figure 18. DNL Error vs. Supply Voltage at 500 kSPS and 1 MSPS Figure 21. THD vs. Analog Input Frequency for Various Source Impedances, True Differential Mode Rev. 0 | Page 13 of 40 05402-021 ±2.5V RANGE RIN = 4000Ω RIN = 1000Ω RIN = 600Ω RIN = 100Ω RIN = 50Ω 05402-020 –100 AD7329 –50 SINGLE-ENDED MODE VDD = 12V, VSS = –12V –55 VCC = VDRIVE = 5V INTERNAL REFERENCE AD8021 BETWEEN MUX OUT+ –60 AND ADCIN+ PINS –65 THD (dB) –76 –78 ±10V RANGE RIN = 2000Ω RIN = 1000Ω RIN = 600Ω RIN = 100Ω RIN = 50Ω ±5V RANGE VCC = VDRIVE = 5V INTERNAL REFERENCE SINGLE-ENDED MODE AD8021 BETWEEN MUX OUT+ AND ADCIN+ PINS –80 THD (dB) –70 –75 –80 –85 –90 10 –82 30kHz/500kSPS –84 05402-022 100 ANALOG INPUT FREQUENCY (kHz) 1000 –88 ±5 10kHz/500kSPS ±7 ±9 ±11 10kHz/1MSPS ±13 ±15 ±17 SUPPLY VOLTAGE (V) (VDD = +, VSS = –) Figure 22. THD vs. Analog Input Frequency for Various Source Impedances, Single-Ended Mode Figure 23. THD vs. Supply Voltage at 500 kSPS and 1 MSPS with 10 kHz and 30 kHz Input Tone Rev. 0 | Page 14 of 40 05402-055 ±2.5V RANGE RIN = 2000Ω RIN = 1000Ω RIN = 600Ω RIN = 100Ω RIN = 50Ω 30kHz/1MSPS –86 AD7329 TERMINOLOGY Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale (a point 1 LSB below the first code transition) and full scale (a point 1 LSB above the last code transition). Offset Code Error This applies to straight binary output coding. It is the deviation of the first code transition (00 ... 000) to (00 ... 001) from the ideal, that is, AGND + 1 LSB. Offset Error Match This is the difference in offset error between any two input channels. Gain Error This applies to straight binary output coding. It is the deviation of the last code transition (111 ... 110) to (111 ... 111) from the ideal (that is, 4 × VREF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB) after adjusting for the offset error. Gain Error Match This is the difference in gain error between any two input channels. Bipolar Zero Code Error This applies when using twos complement output coding and a bipolar analog input. It is the deviation of the midscale transition (all 1s to all 0s) from the ideal input voltage, that is, AGND − 1 LSB. Bipolar Zero Code Error Match This refers to the difference in bipolar zero code error between any two input channels. Positive Full-Scale Error This applies when using twos complement output coding and any of the bipolar analog input ranges. It is the deviation of the last code transition (011 … 110) to (011 … 111) from the ideal (4 × VREF − 1 LSB, 2 × VREF − 1 LSB, VREF − 1 LSB) after adjusting for the bipolar zero code error. Positive Full-Scale Error Match This is the difference in positive full-scale error between any two input channels. Negative Full-Scale Error This applies when using twos complement output coding and any of the bipolar analog input ranges. This is the deviation of the first code transition (10 … 000) to (10 … 001) from the ideal (that is, −4 × VREF + 1 LSB, −2 × VREF + 1 LSB, −VREF + 1 LSB) after adjusting for the bipolar zero code error. Negative Full-Scale Error Match This is the difference in negative full-scale error between any two input channels. Track-and-Hold Acquisition Time The track-and-hold amplifier returns into track mode after the 14th SCLK rising edge. Track-and-hold acquisition time is the time required for the output of the track-and-hold amplifier to reach its final value, within ±½ LSB, after the end of a conversion. Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process. The more levels, the smaller the quantization noise. Theoretically, the signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB For a 13-bit converter, this is 80.02 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7329, it is defined as THD(dB) = 20 log V2 2 + V 3 2 + V 4 2 + V 5 2 + V 6 2 V1 where V1 is the rms amplitude of the fundamental, and V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, the largest harmonic could be a noise peak. Rev. 0 | Page 15 of 40 AD7329 Channel-to-Channel Isolation Channel-to-channel isolation is a measure of the level of crosstalk between any two channels. It is measured by applying a full-scale, 100 kHz sine wave signal to all unselected input channels and determining the degree to which the signal attenuates in the selected channel with a 50 kHz signal. Figure 14 shows the worst-case across all eight channels for the AD7329. The analog input range is programmed to be ±2.5 V on the selected channel and ±10 V on all other channels. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities creates distortion products at sum and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are those for which neither m nor n are equal to 0. For example, the second-order terms include (fa + fb) and (fa − fb), whereas the third-order terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb). terms are usually at a frequency close to the input frequencies. As a result, the second- and third-order terms are specified separately. The calculation of the intermodulation distortion is per the THD specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels. PSR (Power Supply Rejection) Variations in power supply affect the full-scale transition but not the linearity of the converter. Power supply rejection is the maximum change in the full-scale transition point due to a change in power supply voltage from the nominal value (see the Typical Performance Characteristics section). CMRR (Common-Mode Rejection Ratio) CMRR is defined as the ratio of the power in the ADC output at full-scale frequency, f, to the power of a 100 mV sine wave applied to the common-mode voltage of the VIN+ and VIN− frequency, fS, as The AD7329 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves, whereas the third-order CMRR (dB) = 10 log (Pf/PfS) where Pf is the power at frequency f in the ADC output, and PfS is the power at frequency fS in the ADC output (see Figure 17). Rev. 0 | Page 16 of 40 AD7329 THEORY OF OPERATION CIRCUIT INFORMATION The AD7329 is a fast, 8-channel, 12-bit plus sign, bipolar input, serial A/D converter. The AD7329 can accept bipolar input ranges that include ±10 V, ±5 V, and ±2.5 V; it can also accept a 0 V to +10 V unipolar input range. A different analog input range can be programmed on each analog input channel via the on-chip registers. The AD7329 has a high speed serial interface that can operate at throughput rates up to 1 MSPS. The AD7329 requires VDD and VSS dual supplies for the high voltage analog input structures. These supplies must be equal to or greater than the analog input range. See Table 6 for the requirements of these supplies for each analog input range. The AD7329 requires a low voltage 2.7 V to 5.25 V VCC supply to power the ADC core. Table 6. Reference and Supply Requirements for Each Analog Input Range Selected Analog Input Range (V) ±10 ±5 ±2.5 0 to +10 Full-Scale Input Range (V) ±10 ±12 ±5 ±6 ±2.5 ±3 0 to +10 0 to +12 external reference operation is the default option. If the internal reference is the preferred option, the user must write to the reference bit in the control register to select the internal reference operation. The AD7329 also features power-down options to allow power savings between conversions. The power-down modes are selected by programming the on-chip control register as described in the Modes of Operation section. CONVERTER OPERATION The AD7329 is a successive approximation analog-to-digital converter built around two capacitive DACs. Figure 24 and Figure 25 show simplified schematics of the ADC in singleended mode during the acquisition and conversion phases, respectively. Figure 26 and Figure 27 show simplified schematics of the ADC in differential mode during acquisition and conversion phases, respectively. In both examples, the MUXOUT+ pin is connected to the ADCIN+ pin, and the MUXOUT− pin is connected to the ADCIN− pin. The ADC is composed of control logic, a SAR, and capacitive DACs. In Figure 24 (the acquisition phase), SW2 is closed and SW1 is in Position A, the comparator is held in a balanced condition, and the sampling capacitor array acquires the signal on the input. CAPACITIVE DAC B CS SW2 COMPARATOR CONTROL LOGIC AGND In order to meet the specified performance specifications when the AD7329 is configured with the minimum VDD and VSS supplies for a chosen analog input range, the throughput rate should be decreased from the maximum throughput range (see the Typical Performance Characteristics section). The analog inputs can be configured as either eight single-ended inputs, four true differential input pairs, four pseudo differential inputs, or seven pseudo differential inputs. Selection can be made by programming the mode bits, Mode 0 and Mode 1, in the control register. The serial clock input accesses data from the part and provides the clock source for the successive approximation ADC. The AD7329 has an on-chip 2.5 V reference. However, the AD7329 can also work with an external reference. On power-up, the Figure 24. ADC Acquisition Phase (Single Ended) When the ADC starts a conversion (Figure 25), SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced. The control logic and the charge redistribution DAC are used to add and subtract fixed amounts of charge from the capacitive DAC to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code CAPACITIVE DAC B A CS SW1 SW2 COMPARATOR CONTROL LOGIC VIN0 AGND Figure 25. ADC Conversion Phase (Single Ended) Rev. 0 | Page 17 of 40 05402-024 05402-023 Reference Voltage (V) 2.5 3.0 2.5 3.0 2.5 3.0 2.5 3.0 AVCC (V) 3/5 3/5 3/5 3/5 3/5 3/5 3/5 3/5 Minimum VDD/VSS (V) ±10 ±12 ±5 ±6 ±5 ±5 +10/AGND +12/AGND VIN0 A SW1 AD7329 Figure 26 shows the differential configuration during the acquisition phase. For the conversion phase, SW3 opens and SW1 and SW2 move to Position B (see Figure 27). The output impedances of the source driving the VIN+ and VIN− pins must match; otherwise, the two inputs have different settling times, resulting in errors. CAPACITIVE DAC B CS SW3 COMPARATOR CONTROL LOGIC The ideal transfer characteristic for the AD7329 when twos complement coding is selected is shown in Figure 28. The ideal transfer characteristic for the AD7329 when straight binary coding is selected is shown in Figure 29. 011 ... 111 011 ... 110 ADC CODE 05402-025 VIN+ VIN– A SW1 A SW2 B VREF CS 000 ... 001 000 ... 000 111 ... 111 Figure 26. ADC Differential Configuration During Acquisition Phase Figure 28. Twos Complement Transfer Characteristic (Bipolar Ranges) CAPACITIVE DAC VIN+ VIN– A SW1 A SW2 B VREF CS ADC CODE B CS SW3 COMPARATOR CONTROL LOGIC 111 ... 111 111 ... 110 111 ... 000 011 ... 111 CAPACITIVE DAC 05402-026 Figure 27. ADC Differential Configuration During Conversion Phase 000 ... 010 000 ... 001 000 ... 000 05402-028 OUTPUT CODING The AD7329 default output coding is set to twos complement. The output coding is controlled by the coding bit in the control register. To change the output coding to straight binary coding, the coding bit in the control register must be set. When operating in sequence mode, the output coding for each channel in the sequence is the value written to the coding bit during the last write to the control register. –FSR/2 + 1LSB +FSR/2 – 1LSB BIPOLAR RANGES AGND + 1LSB +FSR – 1LSB UNIPOLAR RANGE ANALOG INPUT Figure 29. Straight Binary Transfer Characteristic (Bipolar Ranges) ANALOG INPUT STRUCTURE The analog inputs of the AD7329 can be configured as singleended, true differential, or pseudo differential via the control register mode bits, as shown in Table 4 of the Registers section. The AD7329 can accept true bipolar input signals. On powerup, the analog inputs operate as eight single-ended analog input channels. If true differential or pseudo differential is required, a write to the control register is necessary after power-up to change this configuration. Figure 30 shows the equivalent analog input circuit of the AD7329 in single-ended mode. Figure 31 shows the equivalent analog input structure in differential mode. The two diodes provide ESD protection for the analog inputs. VDD MUXOUT+ D VIN0 C1 D VSS C3 C4 05402-029 TRANSFER FUNCTIONS The designed code transitions occur at successive integer LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent on the analog input range selected. Table 7. LSB Sizes for Each Analog Input Range Input Range ±10 V ±5 V ±2.5 V 0 V to +10 V Full-Scale Range/8192 Codes 20 V 10 V 5V 10 V LSB Size 2.441 mV 1.22 mV 0.61 mV 1.22 mV ADCIN+ R1 C2 Figure 30. Equivalent Analog Input Circuit (Single Ended) Rev. 0 | Page 18 of 40 05402-027 CAPACITIVE DAC 100 ... 010 100 ... 001 100 ... 000 –FSR/2 + 1LSB AGND + 1LSB AGND – 1LSB +FSR/2 – 1LSB BIPOLAR RANGES +FSR – 1LSB UNIPOLAR RANGE ANALOG INPUT AD7329 VDD MUXOUT+ D VIN+ C1 D VSS VDD MUXOUT– D VIN– C1 D VSS C3 C4 05402-030 ADCIN+ R1 C3 C4 C2 For the AD7329, the value of R includes the on resistance of the input multiplexer. The value of R is typically 300 Ω. RSOURCE should include any extra source impedance on the analog input. The AD7329 enters track mode on the 14th SCLK rising edge. When the AD7329 is run at a throughput rate of 1 MSPS with a 20 MHz SCLK signal, the ADC has approximately 1.5 SCLK periods plus t8 plus the quiet time, tQUIET, to acquire the analog input signal. The ADC goes back into hold mode on the CS falling edge. The current required to drive the ADC is extremely small when using the external op amp between the MUXOUT and ADCIN pins. This is due to the high input impedance of the op amp placed between the MUXOUT and ADCIN pins. This can be seen in Figure 32, where the current required to drive the AD7329 input is