NCV7329D10R2G

NCV7329 Stand-alone LIN Transceiver Description The NCV7329 is a fully featured local interconnect network (LIN) transceiver designed to interface between a LIN protocol controller and the physical bus. The LIN bus is designed to communicate low rate data from control devices such as door locks, mirrors, car seats, and sunroofs at the lowest possible cost. The bus is designed to eliminate as much wiring as possible and is implemented using a single wire in each node. Each node has a slave MCU−state machine that recognizes and translates the instructions specific to that function. The main attraction of the LIN bus is that all the functions are not time critical and usually relate to passenger comfort. www.onsemi.com MARKING DIAGRAMS 8 SOIC−8 CASE 751AZ 8 1 Features 1 • LIN−Bus Transceiver 1 ♦ • • • Compliant to ISO 17987−4 (Backwards Compatible to LIN Specification rev. 2.x, 1.3) and SAE J2602 ♦ Bus Voltage $42 V ♦ Transmission Rate 1 kbps to 20 kbps ♦ TxD Timeout Function ♦ Integrated Slope Control Protection ♦ Thermal Shutdown ♦ Undervoltage Protection ♦ Bus Pins Protected Against Transients in an Automotive Environment Modes ♦ Normal Mode: LIN Transceiver Enabled, Communication via the Bus is Possible ♦ Sleep Mode: LIN Transceiver Disabled, the Consumption from VBB is Minimized ♦ Standby Mode: Transition Mode Reached after Wake−up Event on the LIN Bus Compatibility ♦ Pin−Compatible Subset with NCV7321 ♦ K−line Compatible 1 A L Y W G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) PIN CONNECTIONS RxD EN NC TxD 1 8 2 7 3 6 4 5 • NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Require− ments; AEC−Q100 Qualified and PPAP Capable These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant © Semiconductor Components Industries, LLC, 2018 May, 2018 − Rev. 0 1 NC VBB LIN GND SOIC−8 (Top View) RxD 1 8 NC EN 2 TxD 4 Quality NV73 29 ALYWG G DFN8 CASE 507AB NC 3 • NV7329 ALYW G EP 7 VBB 6 LIN 5 GND DFN8 (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 10 of this data sheet. Publication Order Number: NCV7329/D NCV7329 BLOCK DIAGRAM VBB POR Isleep EN State Thermal shutdown Control DS Osc RSLAVE COMP + RxD − TxD Filter LIN Slope Control time−out NCV7329 GND Figure 1. Block Diagram TYPICAL APPLICATION Slave Node Master Node 2 5 GND TxD EN 100 nF 10 μF LIN LIN GND 6 3 VCC 7 1 4 2 5 RxD TxD EN GND GND Microcontroller 3 4 8 NCV7329 6 RxD 220 pF 1 nF NCV7329 LIN LIN 1 3.3/5V VBB VCC 7 Microcontroller 1 kΩ VBB 8 10 kΩ VBAT 3.3/5V 100 nF 10 μF VBAT bat 10 kΩ bat GND GND LB20140619.0 LB20140619.0 KL30 KL30 LIN−BUS LIN−BUS KL31 KL31 Figure 2. Typical Application Diagram for a Master Node Table 1. PIN DESCRIPTION Pin Name Description 1 RxD Receive Data Output; Low in Dominant State; Open−Drain Output 2 EN Enable Input, Transceiver in Normal Operation Mode when High, Pull−down Resistor to GND 3 NC Not Connected 4 TxD Transmit Data Input, Low for Dominant State, Pull−down to GND 5 GND Ground 6 LIN LIN Bus Output/Input 7 VBB Battery Supply Input 8 NC Not Connected − EP Exposed Pad. Recommended to connect to GND or left floating in application (DFN8 package only). www.onsemi.com 2 NCV7329 Table 2. ABSOLUTE MAXIMUM RATINGS Min Max Unit VBB Symbol Voltage on Pin VBB Parameter −0.3 +42 V VLIN LIN Bus Voltage with respect to GND −42 +42 V LIN Bus Voltage with respect to VBB −42 +42 V V_Dig_IO DC Input Voltage on Pins (EN, RxD, TxD) −0.3 +7 V VESD Human Body Model (LIN Pin) (Note 1) −8 +8 kV Human Body Model (All Pins) (Note 1) −4 +4 kV Charged Device Model (All Pins) (Note 2) −750 +750 V Machine Model (All Pins) (Note 3) −200 +200 V VESDIEC Electrostatic Discharge Voltage (LIN Pin) System Human Body Model (Note 4) Conform to IEC 61000−4−2 −8 +8 kV TJ Junction Temperature Range −40 +150 °C TSTG Storage Temperature Range −55 +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Standardized human body model electrostatic discharge (ESD) pulses in accordance to EIA−JESD22. Equivalent to discharging a 100 pF capacitor through a 1.5 kW resistor. 2. Standardized charged device model ESD pulses when tested according to AEC−Q100−011. 3. In accordance to JEDEC JESD22−A115. Equivalent to discharging a 200 pF capacitor through a 10 W resistor and 0.75 mH coil. 4. Equivalent to discharging a 150 pF capacitor through a 330 W resistor. System HBM levels are verified by an external test−house. Table 3. THERMAL CHARACTERISTICS Parameter Symbol Value Unit Thermal characteristics, SOIC−8 (Note 5) Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 6) Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 7) RqJA RqJA 131 81 °C/W °C/W Thermal characteristics, DFN8 (Note 5) Thermal Resistance Junction−to−Air, Free air, 1S0P PCB (Note 6) Thermal Resistance Junction−to−Air, Free air, 2S2P PCB (Note 7) RqJA RqJA 125 58 °C/W °C/W 5. Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for Safe Operating parameters. 6. Values based on test board according to EIA/JEDEC Standard JESD51−3, signal layer with 10% trace coverage. 7. Values based on test board according to EIA/JEDEC Standard JESD51−7, signal layers with 10% trace coverage. www.onsemi.com 3 NCV7329 ELECTRICAL CHARACTERISTICS Definitions All voltages are referenced to GND (pin 5) unless otherwise specified. Positive currents flow into the IC. Sinking current means the current is flowing into the pin; sourcing current means the current is flowing out of the pin. Table 4. DC CHARACTERISTICS (VBB = 5 V to 18 V; TJ = −40°C to +150°C; Typical values are given at VBB = 12 V and TJ = 25°C Bus Load = 500 W (VBB to LIN); unless otherwise specified.) Parameter Symbol Conditions Min. Typ. Max. Unit 18 V SUPPY PIN (VBB) VBB Battery Supply 5 IBB Battery Supply Current Normal Mode; LIN recessive IBB Battery Supply Current Normal Mode; TxD = Low, LIN Dominant IBB Battery Supply Current IBB Battery Supply Current 0.2 0.55 1.2 mA 2 3.9 6.5 mA Sleep and Standby Mode; LIN recessive; VLIN = VBB; TJ tENABLE LIN, rising edge after t > tLIN_WAKE EN = Low for t > tDISABLE Standby Mode EN = High for t > tENABLE − LIN Transceiver: OFF − LIN Term: 30 kW pull−up − RxD: Low Normal Mode − LIN Transceiver: ON − LIN Term: 30 kW pull−up − RxD Receives LIN Data Figure 3. State Diagram www.onsemi.com 8 NCV7329 MEASUREMENT SETUPS AND DEFINITIONS TxD t BIT t BIT 50% t t BUS_DOM(max) LIN t BUS_REC(min) THREC(max) THDOM(max) Thresholds of receiving node 1 THREC(min) THDOM(min) Thresholds of receiving node 2 t t BUS_DOM(min) t BUS_REC(max) Figure 4. LIN Transmitter Duty Cycle LIN VBB 60% VBB 40% VBB t RxD t RX_PD t RX_PD 50% t Figure 5. LIN Receiver Timing LIN Detection of Remote Wake−Up VBB LIN recessive level tLIN_WAKE 60% VBB tTO_STB 40% VBB Sleep Mode Standby Mode Figure 6. Remote (LIN) Wake−up Detection www.onsemi.com 9 LIN dominant level t NCV7329 TxD tBIT tBIT 50% t LIN Vbb 60% Vbb 40% Vbb ttx_prop_down ttx_prop_up RB20180511 t Figure 7. LIN Transmitter Timing DEVICE ORDERING INFORMATION Part Number NCV7329D10R2G NCV7329MW0R2G Description Temperature Range Package Shipping† Stand−alone LIN Transceiver −40°C to +125°C SOIC−8 (Pb−Free) 3000 / Tape & Reel Stand−alone LIN Transceiver −40°C to +125°C DFN8 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 10 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DFNW8 3x3, 0.65P CASE 507AB ISSUE E 1 SCALE 2:1 DATE 02 JUL 2021 GENERIC MARKING DIAGRAM* 1 XXXXXX XXXXXX ALYWG G XXXXXX = Specific Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb−Free Package (Note: Microdot may be in either location) *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. DOCUMENT NUMBER: DESCRIPTION: 98AON14978G DFNW8 3x3, 0.65P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2018 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AK 8 1 SCALE 1:1 −X− DATE 16 FEB 2011 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 0.25 (0.010) M Y M 1 4 −Y− K G C N X 45 _ SEATING PLANE −Z− 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S 8 8 1 1 IC 4.0 0.155 XXXXX A L Y W G IC (Pb−Free) = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package XXXXXX AYWW 1 1 Discrete XXXXXX AYWW G Discrete (Pb−Free) XXXXXX = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. 1.270 0.050 SCALE 6:1 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 8 8 XXXXX ALYWX G XXXXX ALYWX 1.52 0.060 0.6 0.024 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 GENERIC MARKING DIAGRAM* SOLDERING FOOTPRINT* 7.0 0.275 DIM A B C D G H J K M N S mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 onsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves the right to make changes without further notice to any products herein. onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SOIC−8 NB CASE 751−07 ISSUE AK DATE 16 FEB 2011 STYLE 1: PIN 1. EMITTER 2. COLLECTOR 3. COLLECTOR 4. EMITTER 5. EMITTER 6. BASE 7. BASE 8. EMITTER STYLE 2: PIN 1. COLLECTOR, DIE, #1 2. COLLECTOR, #1 3. COLLECTOR, #2 4. COLLECTOR, #2 5. BASE, #2 6. EMITTER, #2 7. BASE, #1 8. EMITTER, #1 STYLE 3: PIN 1. DRAIN, DIE #1 2. DRAIN, #1 3. DRAIN, #2 4. DRAIN, #2 5. GATE, #2 6. SOURCE, #2 7. GATE, #1 8. SOURCE, #1 STYLE 4: PIN 1. ANODE 2. ANODE 3. ANODE 4. ANODE 5. ANODE 6. ANODE 7. ANODE 8. COMMON CATHODE STYLE 5: PIN 1. DRAIN 2. DRAIN 3. DRAIN 4. DRAIN 5. GATE 6. GATE 7. SOURCE 8. SOURCE STYLE 6: PIN 1. SOURCE 2. DRAIN 3. DRAIN 4. SOURCE 5. SOURCE 6. GATE 7. GATE 8. SOURCE STYLE 7: PIN 1. INPUT 2. EXTERNAL BYPASS 3. THIRD STAGE SOURCE 4. GROUND 5. DRAIN 6. GATE 3 7. SECOND STAGE Vd 8. FIRST STAGE Vd STYLE 8: PIN 1. COLLECTOR, DIE #1 2. BASE, #1 3. BASE, #2 4. COLLECTOR, #2 5. COLLECTOR, #2 6. EMITTER, #2 7. EMITTER, #1 8. COLLECTOR, #1 STYLE 9: PIN 1. EMITTER, COMMON 2. COLLECTOR, DIE #1 3. COLLECTOR, DIE #2 4. EMITTER, COMMON 5. EMITTER, COMMON 6. BASE, DIE #2 7. BASE, DIE #1 8. EMITTER, COMMON STYLE 10: PIN 1. GROUND 2. BIAS 1 3. OUTPUT 4. GROUND 5. GROUND 6. BIAS 2 7. INPUT 8. GROUND STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1 STYLE 12: PIN 1. SOURCE 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 13: PIN 1. N.C. 2. SOURCE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 14: PIN 1. N−SOURCE 2. N−GATE 3. P−SOURCE 4. P−GATE 5. P−DRAIN 6. P−DRAIN 7. N−DRAIN 8. N−DRAIN STYLE 15: PIN 1. ANODE 1 2. ANODE 1 3. ANODE 1 4. ANODE 1 5. CATHODE, COMMON 6. CATHODE, COMMON 7. CATHODE, COMMON 8. CATHODE, COMMON STYLE 16: PIN 1. EMITTER, DIE #1 2. BASE, DIE #1 3. EMITTER, DIE #2 4. BASE, DIE #2 5. COLLECTOR, DIE #2 6. COLLECTOR, DIE #2 7. COLLECTOR, DIE #1 8. COLLECTOR, DIE #1 STYLE 17: PIN 1. VCC 2. V2OUT 3. V1OUT 4. TXE 5. RXE 6. VEE 7. GND 8. ACC STYLE 18: PIN 1. ANODE 2. ANODE 3. SOURCE 4. GATE 5. DRAIN 6. DRAIN 7. CATHODE 8. CATHODE STYLE 19: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. MIRROR 2 7. DRAIN 1 8. MIRROR 1 STYLE 20: PIN 1. SOURCE (N) 2. GATE (N) 3. SOURCE (P) 4. GATE (P) 5. DRAIN 6. DRAIN 7. DRAIN 8. DRAIN STYLE 21: PIN 1. CATHODE 1 2. CATHODE 2 3. CATHODE 3 4. CATHODE 4 5. CATHODE 5 6. COMMON ANODE 7. COMMON ANODE 8. CATHODE 6 STYLE 22: PIN 1. I/O LINE 1 2. COMMON CATHODE/VCC 3. COMMON CATHODE/VCC 4. I/O LINE 3 5. COMMON ANODE/GND 6. I/O LINE 4 7. I/O LINE 5 8. COMMON ANODE/GND STYLE 23: PIN 1. LINE 1 IN 2. COMMON ANODE/GND 3. COMMON ANODE/GND 4. LINE 2 IN 5. LINE 2 OUT 6. COMMON ANODE/GND 7. COMMON ANODE/GND 8. LINE 1 OUT STYLE 24: PIN 1. BASE 2. EMITTER 3. COLLECTOR/ANODE 4. COLLECTOR/ANODE 5. CATHODE 6. CATHODE 7. COLLECTOR/ANODE 8. COLLECTOR/ANODE STYLE 25: PIN 1. VIN 2. N/C 3. REXT 4. GND 5. IOUT 6. IOUT 7. IOUT 8. IOUT STYLE 26: PIN 1. GND 2. dv/dt 3. ENABLE 4. ILIMIT 5. SOURCE 6. SOURCE 7. SOURCE 8. VCC STYLE 29: PIN 1. BASE, DIE #1 2. EMITTER, #1 3. BASE, #2 4. EMITTER, #2 5. COLLECTOR, #2 6. COLLECTOR, #2 7. COLLECTOR, #1 8. COLLECTOR, #1 STYLE 30: PIN 1. DRAIN 1 2. DRAIN 1 3. GATE 2 4. SOURCE 2 5. SOURCE 1/DRAIN 2 6. SOURCE 1/DRAIN 2 7. SOURCE 1/DRAIN 2 8. GATE 1 DOCUMENT NUMBER: DESCRIPTION: 98ASB42564B SOIC−8 NB STYLE 27: PIN 1. ILIMIT 2. OVLO 3. UVLO 4. INPUT+ 5. SOURCE 6. SOURCE 7. SOURCE 8. DRAIN STYLE 28: PIN 1. SW_TO_GND 2. DASIC_OFF 3. DASIC_SW_DET 4. GND 5. V_MON 6. VBULK 7. VBULK 8. VIN Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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