AD7537JR-REEL

a FEATURES Two 12-Bit DACs in One Package DAC Ladder Resistance Matching: 0.5% Space Saving Skinny DIP and Surface Mount Packages 4-Quadrant Multiplication Low Gain Error (1 LSB max Over Temperature) Byte Loading Structure Fast Interface Timing LC2MOS (8+4) Loading Dual 12-Bit DAC AD7537 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Automatic Test Equipment Programmable Filters Audio Applications Synchro Applications Process Control GENERAL DESCRIPTION The AD7537 contains two 12-bit current output DACs on one monolithic chip. A separate reference input is provided for each DAC. The dual DAC saves valuable board space, and the monolithic construction ensures excellent thermal tracking. Both DACs are guaranteed 12-bit monotonic over the full temperature range. The AD7537 has a 2-byte (8 LSBs, 4 MSBs) loading structure. It is designed for right-justified data format. The control signals for register loading are A0, A1, CS, WR and UPD. Data is loaded to the input registers when CS and WR are low. To transfer this data to the DAC registers, UPD must be taken low with WR. PRODUCT HIGHLIGHTS Added features on the AD7537 include an asynchronous CLR line which is very useful in calibration routines. When this is taken low, all registers are cleared. The double buffering of the data inputs allows simultaneous update of both DACs. Also, each DAC has a separate AGND line. This increases the device versatility; for instance one DAC may be operated with AGND biased while the other is connected in the standard configuration. 2. Small Package Size: The AD7537 is packaged in small 24-pin 0.3" DIPs and in 28-terminal surface mount packages. The AD7537 is manufactured using the Linear Compatible CMOS (LC2MOS) process. It is speed compatible with most microprocessors and accepts TTL, 74HC and 5 V CMOS logic level inputs. 1. DAC to DAC Matching: Since both DACs are fabricated on the same chip, precise matching and tracking is inherent. Many applications which are not practical using two discrete DACs are now possible. Typical matching: 0.5%. 3. Wide Power Supply Tolerance: The device operates on a +12 V to +15 V VDD, with ± 10% tolerance on this nominal figure. All specifications are guaranteed over this range. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 Fax: 781/461-3113 AD7537–SPECIFICATIONS (VDD = +12 V to +15 V, ⴞ10%, VREFA = VREFB = 10 V; IOUTA = AGND = 0 V, IOUTB = AGNDB = 0 V. All specifications TMIN to TMAX unless otherwise noted.) Parameter J, A Versions K, B Versions L, C Versions S Version T Version U Version Units ACCURACY Resolution Relative Accuracy Differential Nonlinearity 12 ±1 ±1 12 ± 1/2 ±1 12 ± 1/2 ±1 12 ±1 ±1 12 ± 1/2 ±1 12 ± 1/2 ±1 Bits LSB max LSB max ±6 ±3 ±1 ±6 ±3 ±2 LSB max ±5 ±5 ±5 ±5 ±5 ±5 ppm/°C max Typical value is 1 ppm/°C 10 150 10 150 10 150 10 250 10 250 10 250 nA max nA max DAC A Register loaded with all 0s 10 150 10 150 10 150 10 250 10 250 10 250 nA max nA max DAC B Register loaded with all 0s 9 20 9 20 9 20 9 20 9 20 9 20 kΩ min kΩ max Typical Input Resistance = 14 kΩ ±3 ±3 ±1 ±3 ±3 ±1 % max Typically ± 0.5% 2.4 0.8 2.4 0.8 2.4 0.8 2.4 0.8 2.4 0.8 2.4 0.8 V min V max ±1 ± 10 10 ±1 ± 10 10 ±1 ± 10 10 ±1 ± 10 10 ±1 ± 10 10 ±1 ± 10 10 μA max μA max pF max 10.8/16.5 2 10.8/16.5 2 10.8/16.5 2 10.8/16.5 2 10.8/16.5 2 10.8/16.5 2 V min/V max mA max Gain Error Gain Temperature Coefficient2; ΔGain/ΔTemperature Output Leakage Current IOUTA +25°C TMIN to TMAX IOUTB +25°C TMIN to TMAX REFERENCE INPUT Input Resistance VREFA, VREFB Input Resistance Match DIGITAL INPUTS VIH (lnput High Voltage) VIIL (Input Low Voltage) IIN (Input Current) +25°C TMIN to TMAX CIN (lnput Capacitance)2 POWER SUPPLY3 VDD IDD Test Conditions/Comments All grades guaranteed monotonic over temperature. Measured using RFBA, RFBB. Both DAC registers loaded with all 1s. VIN = VDD AC PERFORMANCE CHARACTERISTICS These characteristics are included for Design Guidance only and are not subject to test. (VDD = +12 V to +15 V; VREFA = VREFB = +10 V; IOUTA = AGNDA = 0 V, IOUTB = AGNDB = 0 V. Output Amplifiers are AD644 except where noted.) Parameter TA = +25ⴗC Units Test Conditions/Comments Output Current Settling Time 1.5 μs max To 0.01% of full-scale range. IOUT load = 100 Ω, CEXT = 13 pF. DAC output measured from falling edge of WR. Typical Value of Settling Time is 0.8 μs. Digital-to-Analog Glitch lmpulse 7 nV-s typ Measured with VREFA = VREFB = 0 V. IOUTA, IOUTB load = 100 Ω, CEXT = 13 pF. DAC registers alternately loaded with all 0s and all 1s. AC Feedthrough4 VREFA to IOUTA VREFB to IOUTB –70 –70 –65 –65 dB max dB max VREFA, VREFB = 20 V p-p 10 kHz sine wave. DAC registers loaded with all 0s. Power Supply Rejection ΔGain/ΔVDD ± 0.01 ± 0.02 % per % max ΔVDD = VDD max – VDD min Output Capacitance COUTA COUTB COUTA COUTB 70 70 140 140 70 70 140 140 pF max pF max pF max pF max Channel-to-Channel Isolation VREFA to IOUTB –84 dB typ –84 dB typ Digital Crosstalk 7 nV-s typ Measured for a Code Transition of all 0s to all 1s. IOUTA, IOUTB load = 100 Ω, CEXT = 13 pF. Output Noise Voltage Density (10 Hz–100 kHz) 25 nV/√Hz typ Measured between RFBA and IOUTA or RFBB and IOUTB. Frequency of measurement is 10 Hz–100 kHz. Total Harmonic Distortion –82 dB typ VIN = 6 V rms, 1 kHz. Both DACs loaded with all 1s. VREFB to IOUTA NOTES 1 Temperature range as follows: TA = TMIN, TMAX J, K, L Versions: –40°C to +85°C; A, B, C Versions: –40°C to +85°C; S, T, U Versions: –55°C to +125°C Specifications subject to change without notice. DAC A, DAC B loaded with all 0s DAC A, DAC B loaded with all 1s VREFA = 20 V p-p 10 kHz sine wave, VREFB = 0 V. Both DACs loaded with all 1s. VREFB = 20 V p-p 10 kHz sine wave, VREFA = 0 V. Both DACs loaded with all 1s. 2 Sample tested at +25°C to ensure compliance. Functional at VDD = 5 V, with degraded specifications. 4 Pin 12 (DGND) on ceramic DIPs is connected to lid. 3 –2– REV. A AD7537 TIMING CHARACTERISTICS (VDD = +10.8 V to +16.5 V, VREFA = VREFB = +10 V; IOUTA = AGNDA = 0 V, IOUTB = AGNDB = 0 V.) Parameter Limit at TA = +25ⴗC Limit at TA = –40ⴗC to +85ⴗC Limit at TA = +55ⴗC to +125ⴗC Units Test Conditions/Comments t1 t2 t3 t4 t5 t6 t7 t8 15 15 60 25 0 0 80 80 15 15 80 25 0 0 80 80 30 25 80 25 0 0 100 100 ns min ns min ns min ns min ns min ns min ns min ns min Address Valid to Write Setup Time Address Valid to Write Hold Time Data Setup Time Data Hold Time Chip Select or Update to Write Setup Time Chip Select or Update to Write Hold Time Write Pulse Width Clear Pulse Width Specifications subject to change without notice. Operating Temperature Range Commercial Plastic (J, K, L Versions) . . . . –40°C to +85°C Industrial Hermetic (A, B, C Versions) . . . –40°C to +85°C Extended Hermetic (S, T, U Versions) . . –55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C ABSOLUTE MAXIMUM RATINGS* (TA = +25°C unless otherwise stated) VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V VREFA, VREFB to AGNDA, AGNDB . . . . . . . . . . . . . . . . ± 25 V VRFBA, VRFBB to AGNDA, AGNDB . . . . . . . . . . . . . . . . ± 25 V Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD +0.3 V IOUTA, IOUTB to DGND . . . . . . . . . . . . . . –0.3 V, VDD +0.3 V AGNDA, AGNDB to DGND . . . . . . . . . –0.3 V, VDD +0.3 V Power Dissipation (Any Package) To +75°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW Derates Above +75°C . . . . . . . . . . . . . . . . . . . . . 6 mW/°C *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7537 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Figure 1. Timing Diagram REV. A –3– WARNING! ESD SENSITIVE DEVICE AD7537 PIN FUNCTION DESCRIPTION (PDIP) PIN MNEMONIC DESCRIPTION 1 2 3 4 5 6–14 12 15 16 17 AGNDA IOUTA RFBA VREFA CS DB0–DB7 DGND A0 A1 CLR 18 19 WR UPD 20 VDD 21 22 23 24 VREFB RFBB IOUTB AGNDB Analog Ground for DAC A. Current output terminal of DAC A. Feedback resistor for DAC A. Reference input to DAC A. Chip Select Input Active low. Eight data inputs, DB0–DB7. Digital Ground. Address Line 0. Address Line 1. Clear Input. Active low. Clears all registers. Write Input. Active low. Updates DAC Registers from inputs registers. Power supply input. Nominally +12 V to +15 V, with ± 10% tolerance. Reference input to DAC B. Feedback resistor for DAC B. Current output terminal of DAC B. Analog Ground for DAC B. PIN CONFIGURATIONS current flowing in each ladder leg is constant, irrespective of switch state. The feedback resistor RFBA is used with an op amp (see Figures 4 and 5) to convert the current flowing in IOUTA to a voltage output. Figure 2. Simplified Circuit Diagram for DAC A EQUIVALENT CIRCUIT ANALYSIS Figure 3 shows the equivalent circuit for one of the D/A converters (DAC A) in the AD7537. A similar equivalent circuit can be drawn for DAC B. COUT is the output capacitance due to the N-channel switches and varies from about 50 pF to 150 pF with digital input code. The current source ILKG is composed of surface and junction leakages and approximately doubles every 10°C. R0 is the equivalent output resistance of the device which varies with input code. PDIP and SOIC DIGITAL CIRCUIT INFORMATION The digital inputs are designed to be both TTL and 5 V CMOS compatible. All logic inputs are static protected MOS gates with typical input currents of less than 1 nA. Table I. AD7537 Truth Table CLR UPD CS WR A1 A0 FUNCTION PLCC 1 1 0 1 1 1 X 1 1 X X 0 X 1 X 0 X X X 0 X X X 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 0 X X 1 0 0 0 X X No Data Transfer No Data Transfer All Registers Cleared DAC A LS Input Register Loaded with DB7–DB0 (LSB) DAC A MS Input Register Loaded with DB3 (MSB)–DB0 DAC B LS Input Register Loaded with DB7–DB0 (LSB) DAC B MS Input Register Loaded with DB3 (MSB)–DB0 DAC A, DAC B Registers Updated Simultaneously from Input Registers DAC A, DAC B Registers are Transparent NOTES: X = Don’t care CIRCUIT INFORMATION – D/A SECTION The AD7537 contains two identical 12-bit multiplying D/A converters. Each DAC consists of a highly stable R-2R ladder and 12 N-channel current steering switches. Figure 2 shows a simplified D/A circuit for DAC A. In the R-2R ladder, binary weighted currents are steered between IOUTA and AGNDA. The Figure 3. Equivalent Analog Circuit for DAC A –4– REV. A Applications–AD7537 UNIPOLAR BINARY OPERATION (2-QUADRANT MULTIPLICATION) BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) Figure 4 shows the circuit diagram for unipolar binary operation. With an ac input, the circuit performs 2-quadrant multiplication. The code table for Figure 4 is given in Table II. The recommended circuit diagram for bipolar operation is shown in Figure 5. Offset binary coding is used. With the appropriate DAC register loaded to 1000 0000 0000, adjust R1 (R3) so that VOUTA (VOUTB) = 0 V. Alternatively, R1, R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, 10) varied for VOUTA (VOUTB) = 0 V. Full-scale trimming can be accomplished by adjusting the amplitude of VIN or by varying the value of R5 (R8). Operational amplifiers A1 and A2 can be in a single package (AD644, AD712) or separate packages (AD544, AD711, AD OP27). Capacitors C1 and C2 provide phase compensation to help prevent overshoot and ringing when high-speed op amps are used. For zero offset adjustment, the appropriate DAC register is loaded with all 0s and amplifier offset adjusted so that VOUTA or VOUTB is 0 V. Full-scale trimming is accomplished by loading the DAC register with all 1s and adjusting R1 (R3) so that VOUTA (VOUTB) = –VIN (4095/4096). For high temperature operation, resistors and potentiometers should have a low Temperature Coefficient. In many applications, because of the excellent Gain T.C. and Gain Error specifications of the AD7537, Gain Error trimming is not necessary. In fixed reference applications, full scale can also be adjusted by omitting R1, R2, R3, R4 and trimming the reference voltage magnitude. If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8, R9, R10) should be ratio matched to 0.01% to ensure gain error performance to the data sheet specification. When operating over a wide temperature range, it is important that the resistors be of the same type so that their temperature coefficients match. The code table for Figure 5 is given in Table III. Figure 5. Bipolar Operation (Offset Binary Coding) Table III. Bipolar Code Table for Offset Binary Circuit of Figure 5 Binary Number in DAC Register MSB LSB Figure 4. AD7537 Unipolar Binary Operation Table II. Unipolar Binary Code Table for Circuit of Figure 4 Binary Number in DAC Register MSB LSB 1111 1111 1111 1000 0000 0000 Analog Output, VOUTA or VOUTB ⎛ 4095 ⎞ −V IN ⎜ ⎟ ⎝ 4096 ⎠ ⎛ 2048 ⎞ −V IN ⎜ ⎟ = − 12 V IN ⎝ 4096 ⎠ 0000 0000 0001 ⎛ 1 ⎞ −V IN ⎜ ⎟ ⎝ 4096 ⎠ 0000 0000 0000 0V REV. A –5– Analog Output, VOUTA or VOUTB 1111 1111 1111 ⎛ 2047 ⎞ +V IN ⎜ ⎟ ⎝ 2048 ⎠ 1000 0000 0001 ⎛ 1 ⎞ +V IN ⎜ ⎟ ⎝ 2048 ⎠ 1000 0000 0000 0V 0111 1111 1111 ⎛ 1 ⎞ −V IN ⎜ ⎟ ⎝ 2048 ⎠ 0000 0000 0000 ⎛ 2048 ⎞ −V IN ⎜ ⎟ = −V IN ⎝ 2048 ⎠ AD7537 SEPARATE AGND PINS The DACs in the AD7537 have separate AGND lines taken to pins AGNDA and AGNDB on the package. This increases the applications versatility of the part. Figure 6 is an example of this. DAC A is connected in standard fashion as a programmable attenuator. AGNDA is at ground potential. DAC B is operating with AGND B biased to +5 V by the AD584. This gives an output range of +5 V to +10 V. the AD7537 controls the programmable integrators. The frequency of oscillation is given by: f= 1 2π R6 × 1 R5 C1× C2 × REQ1 × REQ2 where REQ1 and REQ2 are the equivalent resistances of the DACs. The same digital code is loaded into both DACs. If C1 = C2 and R5 = R6, the expression reduces to f= Since REQ = 1 REQ1 × REQ2 1 1 × 2π C 2n × RLAD , (RLAD = DAC ladder resistance). N f= (N / 2n )2 RLAD1 × RLAD2 1 1 × 2π C 1 = 1 D × 2π C = D 1 × 2 π C × RLAD RLAD1 × RLAD2 ⎛N⎞ D=⎜ n⎟ ⎝2 ⎠ m where m is the DAC ladder resistance mismatch ratio, typically 1.005. Figure 6. AD7537 DACs Used in Different Modes PROGRAMMABLE OSCILLATOR Figure 7 shows a conventional state variable oscillator in which With the values shown in Figure 7, the output frequency varies from 0 Hz to 1.38 kHz. The amplitude of the output signal at the A3 output is 10 V peak-to-peak and is constant over the entire frequency span. Figure 7. Programmable State Variable Oscillator –6– REV. A AD7537 other for the MC68008. Figure 11 shows how an AD7537 system can be easily expanded by tying all the UPD lines together and using a single decoder output to control these. This expanded system is shown using a Z80 microprocessor but it is just as easily configured using any other 8-bit microprocessor system. Note how the system shown in Figure 11 produces 4 analog outputs with a minimum amount of hardware. APPLICATION HINTS Output Offset: CMOS D/A converters in circuits such as Figures 4 and 5 exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the amplifier. The maximum amplitude of this error, which adds to the D/A converter nonlinearity, depends on VOS, where VOS is the amplifier input offset voltage. To maintain specified operation, it is recommended that VOS be no greater than (25 ⫻ 10–6) (VREF) over the temperature range of operation. Suitable op amps are the AD711C and its dual version, the AD712C. These op amps have a wide bandwidth and high slew rate and are recommended for wide bandwidth ac applications. AD711/AD712 settling time to 0.01% is typically 3 μs. Temperature Coefficients: The gain temperature coefficient of the AD7537 has a maximum value of 5 ppm/°C and typical value of 1 ppm/°C. This corresponds to worst case gain shifts of 2 LSBs and 0.4 LSBs respectively over a 100°C temperature range. When trim resistors R1 (R3) and R2 (R4) are used to adjust full scale range as in Figure 4, the temperature coefficient of R1 (R3) and R2 (R4) should also be taken into account. For further information see “Gain Error and Gain Temperature Coefficient of CMOS Multiplying DACs”, Application Note, Publication Number E630c-5-3/86 available from Analog Devices. Figure 9. AD7537–MC6809 Interface High Frequency Considerations: AD7537 output capacitance works in conjunction with the amplifier feedback resistance to add a pole to the open loop response. This can cause ringing or oscillation. Stability can be restored by adding a phase compensation capacitor in parallel with the feedback resistor. This is shown as C1 and C2 in Figures 4 and 5. Feedthrough: The dynamic performance of the AD7537 depends upon the gain and phase stability of the output amplifier, together with the optimum choice of PC board layout and decoupling components. A suggested printed circuit layout for Figure 4 is shown in Figure 8 which minimizes feedthrough from VREFA, VREFB to the output in multiplying applications. Figure 10. AD7537–MC68008 Interface Figure 8. Suggested Layout for AD7537 MICROPROCESSOR INTERFACING The byte loading structure of the AD7537 makes it very easy to interface the device to any 8-bit microprocessor system. Figures 9 and 10 show two interfaces: one for the MC6809 and the REV. A Figure 11. Expanded AD7537 System –7– AD7537 OUTLINE DIMENSIONS 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 24 13 1 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 12 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.015 (0.38) GAUGE PLANE SEATING PLANE 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.430 (10.92) MAX 0.005 (0.13) MIN 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 071006-A COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 12. 24-Lead Plastic Dual In-Line Package [PDIP] Narrow Body (N-24-1) Dimensions shown in inches and (millimeters) 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 4 0.048 (1.22) 0.042 (1.07) 5 PIN 1 IDENTIFIER 26 25 TOP VIEW 11 12 0.021 (0.53) 0.013 (0.33) 0.050 (1.27) BSC (PINS DOWN) 19 18 0.456 (11.582) SQ 0.450 (11.430) 0.495 (12.57) SQ 0.485 (12.32) 0.020 (0.51) MIN 0.120 (3.04) 0.090 (2.29) 0.032 (0.81) 0.026 (0.66) 0.430 (10.92) 0.390 (9.91) BOTTOM VIEW (PINS UP) 0.045 (1.14) R 0.025 (0.64) COMPLIANT TO JEDEC STANDARDS MO-047-AB CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 042508-A 0.048 (1.22) 0.042 (1.07) Figure 16. 28-Lead Plastic Leaded Chip Carrier [PLCC] (P-28) Dimensions shown in inches and (millimeters) –8– REV. A AD7537 15.60 (0.6142) 15.20 (0.5984) 13 24 7.60 (0.2992) 7.40 (0.2913) 12 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 10.65 (0.4193) 10.00 (0.3937) 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 0.75 (0.0295) 45° 0.25 (0.0098) 8° 0° 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-013-AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 12-09-2010-A 1 Figure 17. 24-Lead Standard Small Outline Package [SOIC-W] Wide Body (RW-24) Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1, 2, 3 AD7537JN AD7537JNZ AD7537KN AD7537KNZ AD7537LNZ AD7537JP AD7537JP-REEL AD7537JPZ AD7537JPZ-REEL AD7537KP AD7537KPZ AD7537KPZ-REEL AD7537LP-REEL AD7537LPZ AD7537LPZ-REEL AD7537JR AD7537JR-REEL AD7537JRZ AD7537JRZ-REEL AD7537KRZ AD7537KR-REEL AD7537BR AD7537BR-REEL AD7537BRZ Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Relative Accuracy ±1 LSB ±1 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1 LSB ±1 LSB ±1 LSB ±1 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB ±1/2 LSB Gain Error ±6 LSB ±6 LSB ±3 LSB ±3 LSB ±1 LSB ±6 LSB ±6 LSB ±6 LSB ±6 LSB ±3 LSB ±3 LSB ±3 LSB ±1 LSB ±1 LSB ±1 LSB ±6 LSB ±6 LSB ±6 LSB ±6 LSB ±3 LSB ±3 LSB ±3 LSB ±3 LSB ±3 LSB 1 Package Description 24-Lead PDIP 24-Lead PDIP 24-Lead PDIP 24-Lead PDIP 24-Lead PDIP 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 28-Lead PLCC 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W 24-Lead SOIC_W Z = RoHS Compliant Part. Analog Devices reserves the right to ship side-brazed CERDIP packages (D-24-1) in lieu of CERDIP packages (Q-24-1). 3 To order MIL-STD-883, Class B processed parts, add/883B to part number. Contact your local sales office for military data sheet. 2 REV. A –9– Package Option N-24-1 N-24-1 N-24-1 N-24-1 N-24-1 P-28 P-28 P-28 P-28 P-28 P-28 P-28 P-28 P-28 P-28 RW-24 RW-24 RW-24 RW-24 RW-24 RW-24 RW-24 RW-24 RW-24 AD7537 REVISION HISTORY 6/12—Rev. 0 to Rev. A Added SOIC Package ......................................................... Universal Removed LCCC Pin Configuration ................................................ 4 Updated Outline Dimensions .......................................................... 8 Changes to Ordering Guide ............................................................. 9 10/87—Revision 0: Initial Version ©1987–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01138-0-6/12(A) –10– REV. A