AD7679CB1

18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC AD7679 FEATURES 18-bit resolution with no missing codes No pipeline delay (SAR architecture) Differential input range: ±VREF (VREF up to 5 V) Throughput: 570 kSPS INL: ±2.5 LSB max (±9.5 ppm of full scale) Dynamic range : 103 dB typ (VREF = 5 V) S/(N+D): 100 dB typ @ 2 kHz (VREF = 5 V) Parallel (18-,16-, or 8-bit bus) and serial 5 V/3 V interface SPI®/QSPI™/MICROWIRE™/DSP compatible On-board reference buffer Single 5 V supply operation Power dissipation: 76 mW @ 500 kSPS 150 µW @ 1 kSPS 48-lead LQFP or 48-lead LFCSP package Pin-to-pin compatible upgrade of AD7674/AD7676/AD7678 FUNCTIONAL BLOCK DIAGRAM PDBUF AGND AVDD REFBUFIN IN+ IN– SWITCHED CAP DAC PARALLEL INTERFACE CLOCK PD RESET CONTROL LOGIC AND CALIBRATION CIRCUITRY REF REFGND DVDD DGND OVDD SERIAL PORT 18 OGND AD7679 D[17:0] BUSY RD CS MODE0 MODE1 CNVST 03085–0–001 Figure 1. Functional Block Diagram APPLICATIONS CT scanners High dynamic data acquisition Geophone and hydrophone sensors Σ-∆ replacement (low power, multichannel) Instrumentation Spectrum analysis Medical instruments Table 1. PulSAR Selection Type/kSPS PseudoDifferential True Bipolar True Differential 18-Bit Multichannel/ Simultaneous 100–250 AD7651 AD7660/AD7661 AD7663 AD7675 AD7678 500–570 AD7650/AD7652 AD7664/AD7666 AD7665 AD7676 AD7679 AD7654 AD7655 800– 1000 AD7653 AD7667 AD7671 AD7677 AD7674 GENERAL DESCRIPTION The AD7679 is an 18-bit, 570 kSPS, charge redistribution SAR, fully differential analog-to-digital converter that operates on a single 5 V power supply. The part contains a high speed 18-bit sampling ADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports. The part is available in a 48-lead LQFP or 48-lead LFCSP with operation specified from –40°C to +85°C. PRODUCT HIGHLIGHTS 1. High Resolution, Fast Throughput. The AD7679 is a 570 kSPS, charge redistribution, 18-bit SAR ADC (no latency). Excellent Accuracy. The AD7679 has a maximum integral nonlinearity of 2.5 LSB with no missing 18-bit codes. Serial or Parallel Interface. Versatile parallel (18-, 16-, or 8-bit bus) or 3-wire serial interface arrangement compatible with both 3 V and 5 V logic. 2. 3. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD7679 TABLE OF CONTENTS Specifications..................................................................................... 3 Timing Specifications....................................................................... 5 Absolute Maximum Ratings............................................................ 7 Pin Configuration and Functional Descriptions .......................... 8 Definition of Specifications ........................................................... 11 Typical Performance Characteristics ........................................... 12 Circuit Information ........................................................................ 15 Converter Operation.................................................................. 15 Typical Connection Diagram ................................................... 17 Power Dissipation versus Throughput .................................... 19 Conversion Control ................................................................... 19 Digital Interface .......................................................................... 20 Parallel Interface ......................................................................... 20 Serial Interface ............................................................................ 20 Master Serial Interface ............................................................... 21 Slave Serial Interface .................................................................. 22 Microprocessor Interfacing ...................................................... 24 Application Hints ........................................................................... 25 Layout .......................................................................................... 25 Evaluating the AD7679’s Performance .................................... 25 Outline Dimensions ....................................................................... 26 Ordering Guide ............................................................................... 26 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD7679 SPECIFICATIONS Table 2. –40°C to +85°C, VREF = 4.096 V, AVDD = DVDD= 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. Parameter RESOLUTION ANALOG INPUT Voltage Range Operating Input Voltage Analog Input CMRR Input Current Input Impedance1 THROUGHPUT SPEED Complete Cycle Throughput Rate DC ACCURACY Integral Linearity Error Differential Linearity Error No Missing Codes Transition Noise Zero Error, TMIN to TMAX3 Zero Error Temperature Drift Gain Error, TMIN to TMAX3 Gain Error Temperature Drift Power Supply Sensitivity AC ACCURACY Signal-to-Noise Conditions Min 18 –VREF –0.1 68 25 Typ Max Unit Bits V V dB µA VIN+ – VIN– VIN+, VIN– to AGND fIN = 100 kHz 570 kSPS Throughput +VREF AVDD+0.1 0 –2.5 –1 18 VREF = 5 V –40 –0.048 AVDD = 5 V ± 5% fIN = 2 kHz, VREF = 5 V VREF = 4.096 V fIN = 10 kHz, VREF = 4.096 V fIN = 100 kHz, VREF = 4.096 V VIN+ = VIN– = VREF/2 = 2.5 V fIN = 2 kHz fIN = 10 kHz fIN = 100 kHz fIN = 2 kHz fIN = 10 kHz fIN = 100 kHz fIN = 2 kHz, VREF = 4.096 V fIN = 2 kHz, –60 dB Input ±0.5 See Note 3 ±1.6 ±4 101 99 98 97 103 120 118 105 –115 –113 –98 98 40 26 2 5 Full-Scale Step 0.7 1.75 570 +2.5 +1.75 µs kSPS LSB2 LSB Bits LSB LSB ppm/°C % of FSR ppm/°C LSB dB4 dB dB dB dB dB dB dB dB dB dB dB dB MHz ns ps rms ns ns V V V µA µA +40 +0.048 97.5 Dynamic Range Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) –3 dB Input Bandwidth SAMPLING DYNAMICS Aperture Delay Aperture Jitter Transient Response Overvoltage Recovery REFERENCE External Reference Voltage Range REF Voltage with Reference Buffer Reference Buffer Input Voltage Range REFBUFIN Input Current REF Current Drain 250 250 3 4.05 1.8 –1 4.096 4.096 2.5 235 AVDD + 0.1 4.15 2.6 +1 REF REFBUFIN = 2.5 V REFBUFIN 570 kSPS Throughput Rev. 0 | Page 3 of 28 AD7679 Parameter DIGITAL INPUTS Logic Levels VIL VIH IIL IIH DIGITAL OUTPUTS Data Format5 Pipeline Delay6 VOL VOH POWER SUPPLIES Specified Performance AVDD DVDD OVDD Operating Current AVDD DVDD8 OVDD8 POWER DISSIPATION8 Conditions Min Typ Max Unit –0.3 2.0 –1 –1 +0.8 DVDD + 0.3 +1 +1 V V µA µA ISINK = 1.6 mA ISOURCE = –500 µA 0.4 OVDD – 0.6 V V 4.75 4.75 2.7 500 kSPS Throughput PDBUF High 5 5 5.25 5.25 DVDD + 0.37 V V V mA mA µA mW µW mW °C PDBUF High @ 500 kSPS PDBUF High @ 1 kSPS PDBUF Low @ 500 kSPS TMIN to TMAX –40 10.8 4.5 50 76 150 89 90 103 +85 TEMPERATURE RANGE9 Specified Performance 1 2 See Analog Inputs section. LSB means Least Significant Bit. With the ±4.096 V input range, 1 LSB is 31.25 µV. 3 See Definition of Specifications section. The nominal gain error is not centered at zero and is +0.273% of FSR. This specification is the deviation from this nominal value. These specifications do not include the error contribution from the external reference, but do include the error contribution from the reference buffer if used. 4 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale unless otherwise specified. 5 Parallel or Serial 18-Bit. 6 Conversion results are available immediately after completed conversion. 7 The max should be the minimum of 5.25 V and DVDD + 0.3 V. 8 Tested in Parallel Reading mode. 9 Contact factory for extended temperature range. Rev. 0 | Page 4 of 28 AD7679 TIMING SPECIFICATIONS Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted. Parameter Refer to Figure 32 and Figure 33 Convert Pulsewidth Time between Conversions CNVST LOW to BUSY HIGH Delay BUSY HIGH All Modes Except Master Serial Read after Convert Aperture Delay End of Conversion to BUSY LOW Delay Conversion Time Acquisition Time RESET Pulsewidth Refer to Figure 34, Figure 35, and Figure 36 (Parallel Interface Modes) CNVST LOW to Data Valid Delay Data Valid to BUSY LOW Delay Bus Access Request to Data Valid Bus Relinquish Time Refer to Figure 38 and Figure 39 (Master Serial Interface Modes) 1 CS LOW to SYNC Valid Delay CS LOW to Internal SCLK Valid Delay CS LOW to SDOUT Delay CNVST LOW to SYNC Delay SYNC Asserted to SCLK First Edge Delay2 Internal SCLK Period2 Internal SCLK HIGH2 Internal SCLK LOW2 SDOUT Valid Setup Time2 SDOUT Valid Hold Time2 SCLK Last Edge to SYNC Delay2 CS HIGH to SYNC HI-Z CS HIGH to Internal SCLK HI-Z CS HIGH to SDOUT HI-Z BUSY HIGH in Master Serial Read after Convert2 CNVST LOW to SYNC Asserted Delay SYNC Deasserted to BUSY LOW Delay Refer to Figure 40 and Figure 41 (Slave Serial Interface Modes) External SCLK Setup Time External SCLK Active Edge to SDOUT Delay SDIN Setup Time SDIN Hold Time External SCLK Period External SCLK HIGH External SCLK LOW Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 t33 t34 t35 t36 t37 Min 10 1.75 35 1.5 2 10 1.5 250 10 1.5 20 5 45 15 10 10 10 525 3 25 12 7 4 2 3 40 Typ Max Unit ns µs ns µs ns ns µs ns ns µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns ns ns ns ns ns ns ns 10 10 10 See Table 4 1.5 25 5 3 5 5 25 10 10 18 1 2 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum. In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode. Rev. 0 | Page 5 of 28 AD7679 Table 4. Serial Clock Timings in Master Read after Convert DIVSCLK[1] DIVSCLK[0] SYNC to SCLK First Edge Delay Minimum Internal SCLK Period Minimum Internal SCLK Period Maximum Internal SCLK HIGH Minimum Internal SCLK LOW Minimum SDOUT Valid Setup Time Minimum SDOUT Valid Hold Time Minimum SCLK Last Edge to SYNC Delay Minimum Busy High Width Maximum Symbol t18 t19 t19 t20 t21 t22 t23 t24 t28 0 0 3 25 40 12 7 4 2 3 2.25 0 1 17 60 80 22 21 18 4 60 3 1 0 17 120 160 50 49 18 30 140 4.5 1 1 17 240 320 100 99 18 89 300 7.5 Unit ns ns ns ns ns ns ns ns µs Rev. 0 | Page 6 of 28 AD7679 ABSOLUTE MAXIMUM RATINGS Table 5. AD7679 Absolute Maximum Ratings1 Parameter Analog Inputs IN+2, IN–2, REF, REFBUFIN, REFGND to AGND Ground Voltage Differences AGND, DGND, OGND Supply Voltages AVDD, DVDD, OVDD AVDD to DVDD, AVDD to OVDD DVDD to OVDD Digital Inputs Internal Power Dissipation3 Internal Power Dissipation4 Junction Temperature Storage Temperature Range Lead Temperature Range (Soldering 10 sec) Rating AVDD + 0.3 V to AGND – 0.3 V ±0.3 V 500µA IOH 1.6mA IOL TO OUTPUT PIN CL 60pF1 1.4V –0.3 V to +7 V ±7 V –0.3 V to +7 V –0.3 V to DVDD + 0.3 V 700 mW 2.5 W 150°C –65°C to +150°C 300°C 1 IN SERIAL INTERFACE MODES, THE SYNC, SCLK, AND SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM. 03085–0–002 Figure 2. Load Circuit for Digital Interface Timing SDOUT, SYNC, SCLK Outputs, CL = 10 pF 2V 0.8V tDEL AY 2V 0.8V tDELAY 2V 0.8V 03085–0–003 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 See Analog Inputs section. 3 Specification is for device in free air: 48-Lead LQFP: θJA = 91°C/W, θJC = 30°C/W. 4 Specification is for device in free air: 48-Lead LFCSP: θJA = 26°C/W. Figure 3. Voltage Reference Levels for Timing Rev. 0 | Page 7 of 28 AD7679 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS AVDD REFBUFIN 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 AVDD 2 MODE0 3 MODE1 4 D0/OB/2C 5 NC 6 NC 7 D1/A0 8 D2/A1 9 D3 10 D4/DIVSCLK[0] 11 D5/DIVSCLK[1] 12 NC = NO CONNECT REFGND REF PDBUF NC AGND IN+ NC NC NC IN– PIN 1 IDENTIFIER 36 35 34 AGND CNVST PD 33 RESET AD7679 TOP VIEW (Not to Scale) 32 31 30 CS RD DGND 29 BUSY 28 D17 27 26 25 D16 D15 D14 13 14 15 16 17 18 19 20 21 22 23 24 D6/EXT/INT D7/INVSYNC D8/INVSCLK D9/RDC/SDIN OGND D12/SYNC D13/RDERROR 03085–0–004 OVDD DVDD DGND D10/SDOUT Figure 4. 48-Lead LQFP(ST-48) and 48-Lead LFCSP (CP-48) Table 6. Pin Function Descriptions Pin No. 1, 44 2, 47 3 4 Mnemonic AGND AVDD MODE0 MODE1 Type1 P P DI DI Description Analog Power Ground Pin. Input Analog Power Pins. Nominally 5 V. Data Output Interface Mode Selection. Data Output Interface Mode Selection: Interface MODE MODE1 MODE0 Description 0 0 0 18-Bit Interface 1 0 1 16-Bit Interface 2 1 0 Byte Interface 3 1 1 Serial Interface When MODE = 0 (18-bit interface mode), this pin is Bit 0 of the parallel port data output bus and the data coding is straight binary. In all other modes, this pin allows choice of straight binary/binary twos complement. When OB/2C is HIGH, the digital output is straight binary; when LOW, the MSB is inverted, resulting in a twos complement output from its internal shift register. No Connect. When MODE = 0 (18-bit interface mode), this pin is Bit 1 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. When MODE = 0 or 1 (18-bit or 16-bit interface mode), this pin is Bit 2 of the parallel port data output bus. In all other modes, this input pin controls the form in which data is output, as shown in Table 7. In all modes except MODE = 3, this output is used as Bit 3 of the parallel port data output bus. This pin is always an output, regardless of the interface mode. In all modes except MODE = 3, these pins are Bit 4 and Bit 5 of the parallel port data output bus. When MODE = 3 (serial mode), EXT/INT is LOW, and RDC/SDIN is LOW (serial master read after convert), these inputs, part of the serial port, are used to slow down, if desired, the internal serial clock that clocks the data output. In other serial modes, these pins are not used. In all modes except MODE = 3, this output is used as Bit 6 of the parallel port data output bus. When MODE = 3 (serial mode), this input, part of the serial port, is used as a digital select input for choosing the internal data clock or an external data clock. With EXT/INT tied LOW, the internal clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is synchronized to an external clock signal connected to the SCLK input. Rev. 0 | Page 8 of 28 5 D0/OB/2C DI/O 6, 7, 40– 42, 45 8 9 10 11, 12 NC D1/A0 D2/A1 D3 D[4:5]or DIVSCLK[0:1] DI/O DI/O DO DI/O 13 D6 or EXT/INT DI/O D11/SCLK AD7679 Pin No. 14 Mnemonic D7 or INVSYNC D8 or INVSCLK D9 or RDC/SDIN Type1 DI/O Description In all modes except MODE = 3, this output is used as Bit 7 of the parallel port data output bus. When MODE = 3 (serial mode), this input, part of the serial port, is used to select the active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW. In all modes except MODE = 3, this output is used as Bit 8 of the parallel port data output bus. When MODE = 3 (serial mode), this input, part of the serial port, is used to invert the SCLK signal. It is active in both master and slave mode. In all modes except MODE = 3, this output is used as Bit 9 of the parallel port data output bus. When MODE = 3 (serial mode), this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of EXT/INT. When EXT/ INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT with a delay of 18 SCLK periods after the initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT only when the conversion is complete. Input/Output Interface Digital Power Ground. Output Interface Digital Power. Nominally at the same supply as the host interface (5 V or 3 V). Should not exceed DVDD by more than 0.3 V. Digital Power. Nominally at 5 V. Digital Power Ground. In all modes except MODE = 3, this output is used as Bit 10 of the parallel port data output bus. When MODE = 3 (serial mode), this output, part of the serial port, is used as a serial data output synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7679 provides the conversion result, MSB first, from its internal shift register. The data format is determined by the logic level of OB/2C. In serial mode when EXT/INT is LOW, SDOUT is valid on both edges of SCLK. In serial mode when EXT/INT is HIGH and INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and is valid on the next falling edge; if INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and is valid on the next rising edge. In all modes except MODE = 3, this output is used as Bit 11 of the parallel port data output bus. When MODE = 3 (serial mode), this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated depends upon the logic state of the INVSCLK pin. In all modes except MODE = 3, this output is used as Bit 12 of the parallel port data output bus. When MODE = 3 (serial mode), this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains HIGH while the SDOUT output is valid. When a read sequence is initiated and INVSYNC is HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. In all modes except MODE = 3, this output is used as Bit 13 of the parallel port data output bus. In MODE = 3 (serial mode) and when EXT/ INT is HIGH, this output, part of the serial port, is used as an incomplete read error flag. In slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and RDERROR is pulsed high. Bit 14 to Bit 17 of the Parallel Port Data Output Bus. These pins are always outputs regardless of the interface mode. Busy Output. Transitions HIGH when a conversion is started. Remains HIGH until the conversion is complete and the data is latched into the on-chip shift register. The falling edge of BUSY could be used as a data ready clock signal. Must Be Tied to Digital Ground. Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is also used to gate the external clock. Reset Input. When set to a logic HIGH, reset the AD7679. Current conversion, if any, is aborted. If not used, this pin could be tied to DGND. Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are inhibited after the current one is completed. 15 DI/O 16 DI/O 17 18 19 20 21 OGND OVDD DVDD DGND D10 or SDOUT P P P P DO 22 D11 or SCLK DI/O 23 D12 or SYNC DO 24 D13 or RDERROR DO 25–28 29 D[14:17] BUSY DO DO 30 31 32 33 34 DGND RD CS RESET PD P DI DI DI DI Rev. 0 | Page 9 of 28 AD7679 Pin No. 35 Mnemonic CNVST Type1 DI Description Start Conversion. If CNVST is held HIGH when the acquisition phase (t8) is complete, the next falling edge on CNVST puts the internal sample/hold into the hold state and initiates a conversion. If CNVST is held LOW when the acquisition phase is complete, the internal sample/hold is put into the hold state and a conversion is started immediately. Must Be Tied to Analog Ground. Reference Input Voltage and Internal Reference Buffer Output. Apply an external reference on this pin if the internal reference buffer is not used. Should be decoupled effectively with or without the internal buffer. Reference Input Analog Ground. Differential Negative Analog Input. Differential Positive Analog Input. Reference Buffer Input Voltage. The internal reference buffer has a fixed gain. It outputs 4.096 V typically when 2.5 V is applied on this pin. Allows Choice of Buffering Reference. When LOW, buffer is selected. When HIGH, buffer is switched off. 36 37 AGND REF P AI 38 39 43 46 48 REFGND IN– IN+ REFBUFIN PDBUF AI AI AI AI DI 1 AI = Analog Input; AO = Analog Output; DI = Digital Input; DI/O = Bidirectional Digital; DO = Digital Output; P = Power. Table 7. Data Bus Interface Definitions MODE 0 1 1 2 2 2 2 3 MODE1 0 0 0 1 1 1 1 1 MODE0 0 1 1 0 0 0 0 1 D0/OB/2C R[0] OB/2C OB/2C OB/2C OB/2C OB/2C OB/2C OB/2C D1/A0 R[1] A0:0 A0:1 A0:0 A0:0 A0:1 A0:1 D2/A1 R[2] R[2] R[0] A1:0 A1:1 A1:0 A1:1 All Hi-Z D[3] R[3] R[3] R[1] All Hi-Z All Hi-Z All Hi-Z All Hi-Z R[2:3] R[0:1] All Zeros Serial Interface D[4:9] R[4:9] R[4:9] D[10:11] R [ 10:11] R[10:11] R[10:11] D[12:15] R[12:15] R[12:15] R[12:15] R[4:7] D[16:17] R[16:17] R[16:17] R[16:17] R[8:9] All Zeros R[0:1] Description 18-Bit Parallel 16-Bit High Word 16-Bit Low Word 8-Bit HIGH Byte 8-Bit MID Byte 8-Bit LOW Byte 8-Bit LOW Byte Serial Interface All Zeros R[0:17] is the 18-bit ADC value stored in its output register. Rev. 0 | Page 10 of 28 AD7679 DEFINITION OF SPECIFICATIONS Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs ½ LSB before the first code transition. Positive full scale is defined as a level 1½ LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal, and is expressed in decibels. Dynamic Range Dynamic range is the ratio of the rms value of the full scale to the rms noise measured with the inputs shorted together. The value for dynamic range is expressed in decibels. Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. Differential nonlinearity is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Gain Error The first transition (from 000…00 to 000…01) should occur for an analog voltage ½ LSB above the nominal –full scale (–4.095991 V for the ±4.096 V range). The last transition (from 111…10 to 111…11) should occur for an analog voltage 1½ LSB below the nominal full scale (4.095977 V for the ±4.096 V range). The gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in decibels. Aperture Delay Aperture delay is a measure of the acquisition performance and is measured from the falling edge of the CNVST input to when the input signal is held for a conversion. Zero Error The zero error is the difference between the ideal midscale input voltage (0 V) from the actual voltage producing the midscale output code. Transient Response Transient response is the time required for the AD7679 to achieve its rated accuracy after a full-scale step function is applied to its input. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input, and is expressed in bits. It is related to S/(N+D) by the following formula: ENOB = (S/[N+D]dB – 1.76)/6.02 Rev. 0 | Page 11 of 28 AD7679 TYPICAL PERFORMANCE CHARACTERISTICS 2.5 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 –2.5 0 65536 131072 CODE 196608 262144 03085-0-005 2.0 1.5 DNL-LSB (18-Bit) INL-LSB (18-Bit) 1.0 0.5 0 –0.5 –1.0 0 65536 131072 CODE 196608 262144 03085-0-008 Figure 5. Integral Nonlinearity vs. Code 70000 60000 50000 60000 58510 59001 VREF = 5V 80000 70000 90000 Figure 8. Differential Nonlinearity vs. Code VREF = 5V COUNTS COUNTS 40000 30000 20000 10000 0 0 0 73 7584 50000 40000 30000 20000 23080 22496 4616 264 0 0 10000 0 0 2 799 3838 59 0 1FEBD 1FEBE 1FEC0 1FEC1 1FEC2 1FEC3 1FEC4 1FEC5 1FEC6 CODE IN HEX 03085-0-006 1FEBE 1FEBF 1FEC0 1FEC1 1FEC2 1FEC3 1FEC4 1FEC5 1FEC6 CODE IN HEX 03085-0-009 Figure 6. Histogram of 131,072 Conversions of a DC Input at the Code Transition 100 120 Figure 9. Histogram of 131,072 Conversions of a DC Input at the Code Center 80 NUMBER OF UNITS 100 NUMBER OF UNITS 0.5 1.0 1.5 POSITIVE INL (LSB) 2.0 80 60 60 40 40 20 20 0 0 2.5 03085-0-007 0 –2.5 –2.0 –1.5 –1.0 NEGATIVE INL (LSB) –0.5 0 03085-0-010 Figure 7. Typical Positive INL Distribution (424 Units) Figure 10. Typical Negative INL Distribution (424 Units) Rev. 0 | Page 12 of 28 AD7679 120 105 17.0 100 SNR AND S/[N+D] (dB) 100 SNR 95 16.5 NUMBER OF UNITS 80 16.0 ENOB (Bits) 60 90 S/(N+D) 85 ENOB 80 15.5 40 15.0 20 14.5 0 0 0.5 1.0 1.5 POSITIVE DNL (LSB) 2.0 03085-0-011 75 1 10 100 FREQUENCY (kHz) 14.0 1000 03085-0-015 Figure 11. Typical Positive DNL Distribution (424 Units) 180 160 140 120 100 80 60 40 20 0 –1.00 –0.75 –0.50 NEGATIVE DNL (LSB) –0.25 0 03085-0-014 Figure 14. SNR, S/(N+D), and ENOB vs. Frequency –60 –70 140 120 100 SFDR THD, HARMONICS (dB) NUMBER OF UNITS –80 –90 –100 THD –110 –120 –130 SECOND HARMONIC THIRD HARMONIC 60 40 20 0 1000 1 10 100 FREQUENCY (kHz) 03085-0-016 Figure 12. Typical Negative DNL Distribution (424 Units) 0 Figure 15. THD, SFDR, and Harmonics vs. Frequency 102 –40 –60 –80 –100 –120 –140 –160 –180 0 30 60 90 120 150 180 FREQUENCY (kHz) SNR REFERRED TO FULL SCALE (dB) –20 AMPLITUDE (dB of Full Scale) fS = 570kSPS fIN = 10kHz VREF = 4.096V SNR = 98.5dB THD = 115.8dB SFDR = 117.4dB S/(N+D) = 98.4dB VREF = 4.096V 100 S/(N+D) SNR 98 210 240 270 03085-0-012 96 –60 –50 –40 –30 –20 –10 0 03085-0-017 INPUT LEVEL (dB) Figure 13. FFT (10 kHz Tone) Figure 16. SNR and S/(N+D) vs. Input Level Rev. 0 | Page 13 of 28 SFDR (dB) 80 AD7679 100 SNR 99 16.0 S/(N+D) ENOB 98 15.5 16.5 1000 POWER-DOWN OPERATING CURRENTS (nA) 900 800 700 500 DVDD 500 400 300 200 100 0 –55 – 35 – 15 5 25 45 65 TEMPERATURE (°C) 85 105 125 AVDD SNR, S/[N+D] (dB) 97 15.0 OVDD 96 –55 –35 –15 5 25 45 65 85 105 14.5 125 TEMPERATURE (°C) 03085-0-018 03085-0-021 Figure 17. SNR, S/(N+D), and ENOB vs. Temperature –100 Figure 20. Power-Down Operating Currents vs. Temperature 25 20 ZERO ERROR,POSITIVE AND NEGATIVE FULL SCALE (LSB) THD 15 10 5 0 –5 –10 –15 –20 THD, HARMONICS (dB) –110 THIRD HARMONIC NEGATIVE FULL SCALE –120 SECOND HARMONIC –130 ZERO ERROR POSITIVE FULL SCALE –140 –55 –35 –15 5 25 45 65 85 105 125 –25 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) 03085-0-019 TEMPERATURE (°C) 03085-0-022 Figure 18. THD and Harmonics vs. Temperature 100000 10000 OPERATING CURRENTS (µA) Figure 21. Zero Error Positive and Negative Full Scale vs. Temperature 50 OVDD = 2.7V @ 85°C 40 1000 100 AVDD 10 DVDD 1 0.1 0.01 0.001 OVDD PDBUF HIGH 10 t12 DELAY (ns) 30 20 OVDD = 2.7V @ 25°C OVDD = 5V @ 85°C OVDD = 5V @ 25°C 1 10 100 1k 10k SAMPLING RATE (SPS) 100k 1M 03085-0-020 0 0 50 100 CL (pF) 150 200 03085-0-024 Figure 19. Operating Current vs. Sampling Rate Figure 22. Typical Delay vs. Load Capacitance CL Rev. 0 | Page 14 of 28 AD7679 CIRCUIT INFORMATION IN+ MSB 262,144C 131,072C REF REFGND 262,144C 131,072C MSB 4C 2C C C LSB SW– CNVST LSB 4C 2C C C BUSY COMP CONTROL LOGIC OUTPUT CODE SW+ SWITCHES CONTROL IN– 03085–0–025 Figure 23. ADC Simplified Schematic The AD7679 is a ver y fast, low power, single-supply, precise 18-bit analog-to-digital converter (ADC) using successive approximation architecture. The AD7679’s linearity and dynamic range are similar or better than many Σ-Δ ADCs. With the advantages of its successive architecture, which ease multiplexing and reduce power with throughput, it can be advantageous in applications that normally use Σ-Δ ADCs. The AD7679 provides the user with an on-chip track/hold, successive approximation ADC that does not exhibit any pipeline or latency, making it ideal for multiple multiplexed channel applications. The AD7679 can be operated from a single 5 V supply and can be interfaced to either 5 V or 3 V digital logic. It is housed in a 48-lead LQFP, or a tiny 48-lead LFCSP that offers space savings and allows for flexible configurations as either a serial or parallel interface. The AD7679 is pin-to-pin compatible with the AD7674, AD7676, and AD7678. CONVERTER OPERATION The AD7679 is a successive approximation ADC based on a charge redistribution DAC. Figure 23 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 18 binar y weighted capacitors that are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to AGND via SW+ and SW–. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on IN+ and IN– inputs. When the acquisition phase is complete and the CNVST input goes low, a conversion phase is initiated. When the conversion phase begins, SW+ and SW– are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the REFGND input. Therefore, the differential voltage between the IN+ and IN– inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between REFGND and REF, the comparator input varies by binar y weighted voltage steps (VREF/2, VREF/4...VREF/262144). The control logic toggles these switches, starting with the MSB first, to bring the comparator back into a balanced condition. After completing this process, the control logic generates the ADC output code and brings the BUSY output low. Rev. 0 | Page 15 of 28 AD7679 Transfer Functions Except in 18-bit interface mode, the AD7679 offers straight binar y and twos complement output coding when using OB/2C. See Figure 24 and Table 8 for the ideal transfer characteristic. Table 8. Output Codes and Ideal Input Voltages Analog Input VREF = 4.096 V 4.095962 V 4.095924 V 31.25 µV 0V –31.25 µV -4.095962 V -4.096 V Straight Binary (Hex) 3FFFF1 3FFFE 20001 20000 1FFFF 00001 000002 Twos Complement (Hex) 1FFFF1 1FFFE 00001 00000 3FFFF 20001 20000 2 ADC CODE (Straight Binary) 111...111 111...110 111...101 Description FSR –1 LSB FSR – 2 LSB Midscale + 1 LSB Midscale Midscale – 1 LSB –FSR + 1 LSB –FSR 000...010 000...001 000...000 –FS –FS + 1 LSB +FS – 1 LSB +FS – 1.5 LSB ANALOG INPUT 03085-0-026 1 2 –FS + 0.5 LSB This is also the code for overrange analog input (VIN+ – VIN– above VREF – VREFGND). This is also the code for underrange analog input (VIN+ – VIN– below –VREF + VREFGND). Figure 24. ADC Ideal Transfer Function DVDD ANALOG SUPPLY (5V) 20Ω + NOTE 5 DIGITAL SUPPLY (3.3V OR 5V) + 10µ F 100nF 100nF + 10µ F 10µF 100nF ADR421 2.5V REF NOTE 1 AVDD 1MΩ 100nF NOTE 2 AGND DGND DVDD OVDD OGND SCLK SDOUT SERIAL PORT REFBUFIN 50kΩ 100nF CREF 47µF NOTE 1 REF BUSY REFGND CNVST 50Ω µC/µP/DSP D NOTE 3 ANALOG INPUT+ – U1 + CC 30Ω NOTE 6 IN+ 2.7nF NOTE 4 AD7679 MODE1 MODE0 OB/2C DVDD AD8021 PDBUF CS NOTE 3 CLOCK ANALOG INPUT– – U2 + CC 30Ω RD IN– 2.7nF NOTE 4 RESET PD AD8021 NOTES 1. SEE VOLTAGE REFERENCE INPUT SECTION. 2. OPTIONAL CIRCUITRY FOR HARDWARE GAIN CALIBRATION. 3.THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION. 4. SEE ANALOG INPUTS SECTION. 5. OPTION, SEE POWER SUPPLY SECTION. 6. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION. 03085-0-027 Figure 25. Typical Connection Diagram (Internal Reference Buffer, Serial Interface) Rev. 0 | Page 16 of 28 AD7679 TYPICAL CONNECTION DIAGRAM Figure 25 shows a typical connection diagram for the AD7679. Different circuitr y shown on this diagram is optional and is discussed later in this data sheet. consists of the ADC sampling capacitor. This 1-pole filter with a –3 dB cutoff frequency of 26 MHz typ reduces any undesirable aliasing effect and limits the noise coming from the inputs. Because the input impedance of the AD7679 is ver y high, the part can be driven directly by a low impedance source without gain error. This allows the user to put an external 1-pole RC filter between the amplifier output and the ADC analog inputs, as shown in Figure 25, to even further improve the noise filtering done by the AD7679 analog input circuit. However, the source impedance has to be kept low because it affects the ac performance, especially the total harmonic distortion (THD). The maximum source impedance depends on the amount of THD that can be tolerated. The THD degrades as a function of source impedance and the maximum input frequency, as shown in Figure 28. –95 20kHz –100 Analog Inputs Figure 26 shows a simplified analog input section of the AD7679. The diodes shown in Figure 26 provide ESD protection for the inputs. Care must be taken to ensure that the analog input signal never exceeds the absolute ratings on these inputs. This will cause these diodes to become for ward biased and start conducting current. These diodes can handle a for ward-biased current of 120 mA max. This condition could eventually occur when the input buffer’s U1 or U2 supplies are different from AVDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part. AVDD IN+ R+ = 102Ω IN– CS R– = 102Ω THD (dB) CS –105 10kHz –110 2kHz AGND 03085-0-028 –115 Figure 26. Simplified Analog Input –120 15 This analog input structure is a true differential structure. By using these differential inputs, signals common to both inputs are rejected as shown in Figure 27, which represents typical CMRR over frequency. 80 45 75 INPUT RESISTANCE (Ω) 105 03085-0-030 Figure 28. THD vs. Analog Input Frequency and Source Resistance Driver Amplifier Choice Although the AD7679 is easy to drive, the driver amplifier needs to meet the following requirements: • The driver amplifier and the AD7679 analog input circuit have to be able to settle for a full-scale step of the capacitor array at an 18-bit level (0.0004%). In the amplifier’s data sheet, settling at 0.1% or 0.01% is more commonly specified. This could differ significantly from the settling time at an 18-bit level and, therefore, should be verified prior to driver selection. The tiny op amp AD8021, which combines ultralow noise and high gain-bandwidth, meets this settling time requirement. The noise generated by the driver amplifier needs to be kept as low as possible in order to preser ve the SNR and transition noise performance of the AD7679. The noise coming from the driver is filtered by the AD7679 analog input circuit 1-pole low-pass filter made by R+, R–, and CS. 75 70 CMRR (dB) 65 60 55 50 1 10 100 FREQUECY (kHz) 1000 10000 03085-0-029 • Figure 27. Analog Input CMRR vs. Frequency During the acquisition phase for ac signals, the AD7679 behaves like a 1-pole RC filter consisting of the equivalent resistance, R+, R–, and CS. Resistors R+ and R– are typically 102 Ω and are lumped components made up of a serial resistor and the on resistance of the switches. CS is typically 60 pF and mainly Rev. 0 | Page 17 of 28 AD7679 The SNR degradation due to the amplifier is    SNRLOSS = 20 log            ANALOG INPUT (UNIPOLAR 0V TO 4.096V) U1 AD8021 10pF 590Ω 590Ω 25 625 +π f –3dB (NeN )2 30Ω 2.7nF 30Ω IN+ where: f–3dB is the –3 dB input bandwidth in MHz of the AD7679 (26 MHz) or the cutoff frequency of the input filter, if used. N is the noise factor of the amplifiers (1 if in buffer configuration). eN is the equivalent input noise voltage of each op amp in nV/√Hz. For instance, for a driver with an equivalent input noise of 2 nV/√Hz (e.g., AD8021) configured as a buffer, thus with a noise gain of +1, the SNR degrades by only 0.34 dB with the filter in Figure 25, and by 1.8 dB without it. • The driver needs to have a THD performance suitable to that of the AD7679. AD7679 2.7nF IN– REF REFBUFIN 1.82kΩ 8.25kΩ U2 AD8021 100nF 10pF 10µF 2.5V 03085-0-031 Figure 29. Single-Ended-to-Differential Driver Circuit (Internal Reference Buffer Used) Voltage Reference The AD7679 allows the use of an external voltage reference either with or without the internal reference buffer. Using the internal reference buffer is recommended when sharing a common reference voltage between multiple ADCs is desired. However, the advantages of using the external reference voltage directly are • The SNR and dynamic range improvement (about 1.7 dB) resulting from the use of a reference voltage ver y close to the supply (5 V) instead of a typical 4.096 V reference when the internal buffer is used. The power saving when the internal reference buffer is powered down (PDBUF high). The AD8021 meets these requirements and is usually appropriate for almost all applications. The AD8021 needs a 10 pF external compensation capacitor, which should have good linearity as an NPO ceramic or mica type. The AD8022 could be used if a dual version is needed and gain of 1 is present. The AD829 is an alternative in applications where high frequency (above 100 kHz) performance is not required. In gain of 1 applications, it requires an 82 pF compensation capacitor. The AD8610 is another option when low bias current is needed in low frequency applications. • Single-to-Differential Driver For applications using unipolar analog signals, a single-endedto-differential driver will allow for a differential input into the part. The schematic is shown in Figure 29. When provided an input signal of 0 to VREF, this configuration will produce a differential ±VREF with midscale at VREF/2. If the application can tolerate more noise, the AD8138, differential driver can be used. To use the internal reference buffer, PDBUF should be LOW. A 2.5 V reference voltage applied on the REFBUFIN input will result in a 4.096 V reference on the REF pin. In both cases, the voltage reference input REF has a dynamic input impedance and therefore requires an efficient decoupling between REF and REFGND inputs. The decoupling consists of a low ESR 47 µF tantalum capacitor connected to the REF and REFGND inputs with minimum parasitic inductance. Care should also be taken with the reference temperature coefficient of the voltage reference, which directly affects the full-scale accuracy if this parameter matters. For instance, a ±4 ppm/°C temperature coefficient of the reference changes the full scale by ±1 LSB/°C. Rev. 0 | Page 18 of 28 AD7679 Power Supply The AD7679 uses three sets of power supply pins: an analog 5 V supply (AVDD), a digital 5 V core supply (DVDD), and a digital output interface supply (OVDD). The OVDD supply defines the output logic level and allows direct interface with any logic working between 2.7 V and DVDD + 0.3 V. To reduce the number of supplies needed, the digital core (DVDD) can be supplied through a simple RC filter from the analog supply, as shown in Figure 25. The AD7679 is independent of power supply sequencing once OVDD does not exceed DVDD by more than 0.3 V, and is therefore free from supply voltage induced latch-up. Additionally, it is ver y insensitive to power supply variations over a wide frequency range (see Figure 30). 65 1000000 100000 POWER DISSAPATION (µW) 10000 1000 100 10 1 PDBUF HIGH 0.1 1 10 100 1k 10k SAMPLING RATE (SPS) 100k 1M 03085-0-033 Figure 31. Power Dissipation vs. Sample Rate 60 CONVERSION CONTROL Figure 32 shows the detailed timing diagrams of the conversion process. The AD7679 is controlled by the CNVST signal, which initiates conversion. Once initiated, it cannot be restarted or aborted, even by PD, until the conversion is complete. The CNVST signal operates independently of CS and RD. t1 CNVST PSRR (dB) 55 50 45 t2 40 1 10 100 FREQUECY (kHz) 1000 10000 03085-0-032 BUSY Figure 30. PSRR vs. Frequency t4 t3 t5 t6 CONVERT ACQUIRE CONVERT POWER DISSIPATION VERSUS THROUGHPUT The AD7679 automatically reduces its power consumption at the end of each conversion phase. During the acquisition phase, the operating currents are ver y low, which allows for a significant power savings when the conversion rate is reduced, as shown in Figure 31. This feature makes the AD7679 ideal for ver y low power batter y applications. It should be noted that the digital interface remains active even during the acquisition phase. To reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (DVDD and DGND), and OVDD should not exceed DVDD by more than 0.3 V. MODE ACQUIRE t7 t8 03085-0-034 Figure 32. Basic Conversion Timing Although CNVST is a digital signal, it should be designed with special care with fast, clean edges and levels with minimum overshoot and undershoot or ringing. For applications where SNR is critical, the CNVST signal should have ver y low jitter. This may be achieved by using a dedicated oscillator for CNVST generation, or to clock it with a high frequency low jitter clock, as shown in Figure 25. For other applications, conversions can be automatically initiated. If CNVST is held low when BUSY is low, the AD7679 controls the acquisition phase and automatically initiates a new conversion. By keeping CNVST low, the AD7679 keeps the conversion process running by itself. It should be noted that the analog input has to be settled when BUSY goes low. Also, at power-up, CNVST should be brought low once to initiate the conversion process. In this mode, the AD7679 could sometimes run slightly faster than the guaranteed limits of 570 kSPS. Rev. 0 | Page 19 of 28 AD7679 DIGITAL INTERFACE The AD7679 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. The serial interface is multiplexed on the parallel data bus. The AD7679 digital interface also accommodates both 3 V and 5 V logic by simply connecting the AD7679’s OVDD supply pin to the host system interface digital supply. Finally, by using the OB/2C input pin in any mode but 18-bit interface mode, both twos complement and straight binar y coding can be used. The two signals, CS and RD, control the interface. When at least one of these signals is high, the interface outputs are in high impedance. Usually, CS allows the selection of each AD7679 in multicircuit applications, and is held low in a single AD7679 design. RD is generally used to enable the conversion result on the data bus. t9 RESET CS = 0 CNVST, RD that it is read only during the first half of the conversion phase. This avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitr y. Refer to Table 7 for a detailed description of the different options available. CS RD BUSY DATA BUS CURRENT CONVERSION t12 t13 03085-0-037 Figure 35. Slave Parallel Data Timing for Reading (Read after Convert) t1 BUSY BUSY t4 t3 DATA BUS t8 CNVST 03085-0-035 DATA BUS PREVIOUS CONVERSION t12 t13 03085-0-038 Figure 36. Slave Parallel Data Timing for Reading (Read during Convert) Figure 33. RESET Timing CS CS = RD = 0 t1 CNVST RD t10 BUSY t4 t3 t11 PREVIOUS CONVERSION DATA NEW DATA A0, A1 PINS D[15:8] HI-Z HIGH BYTE LOW BYTE HI-Z DATA BUS t12 PINS D[7:0] HI-Z LOW BYTE t12 HIGH BYTE t13 HI-Z 03085-0-039 03085-0-036 Figure 34. Master Parallel Data Timing for Reading (Continuous Read) Figure 37. 8-Bit and 16-Bit Parallel Interface PARALLEL INTERFACE The AD7679 is configured to use the parallel interface with an 18-bit, a 16-bit, or an 8-bit bus width, according to Table 7. The data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion, as shown in Figure 35 and Figure 36, respectively. When the data is read during the conversion, however, it is recommended SERIAL INTERFACE The AD7679 is configured to use the serial interface when MODE0 and MODE1 are held high. The AD7679 outputs 18 bits of data, MSB first, on the SDOUT pin. This data is synchronized with the 18 clock pulses provided on the SCLK pin. The output data is valid on both the rising and falling edge of the data clock. Rev. 0 | Page 20 of 28 AD7679 MASTER SERIAL INTERFACE Internal Clock The AD7679 is configured to generate and provide the serial data clock SCLK when the EXT/INT pin is held low. The AD7679 also generates a SYNC signal to indicate to the host when the serial data is valid. The serial clock SCLK and the SYNC signal can be inverted if desired. Depending on the RDC/SDIN input, the data can be read after each conversion or during the following conversion. Figure 38 and Figure 39 show the detailed timing diagrams of these two modes. Usually, because the AD7679 is used with a fast throughput, the mode master read during conversion is the most recommended serial mode. In Read during Conversion mode, the serial clock and data toggle at appropriate instants, minimizing potential feedthrough between digital activity and critical conversion decisions. In Read after Conversion mode, it should be noted that unlike in other modes, the BUSY signal returns low after the 18 data bits are pulsed out and not at the end of the conversion phase, which results in a longer BUSY width. To accommodate slow digital hosts, the serial clock can be slowed down by using DIVSCLK. CS, RD EXT/INT = 0 RDC/SDIN = 0 INVSCLK = INVSYNC = 0 t3 CNVST BUSY t28 t29 t30 t25 t18 t19 t20 t21 1 2 3 16 17 SYNC t14 t24 18 t26 SCLK t15 SDOUT X D17 D16 D2 D1 D0 t27 t16 t22 t23 03085-0-040 Figure 38. Master Serial Data Timing for Reading (Read after Convert) Rev. 0 | Page 21 of 28 AD7679 CS, RD EXT/INT = 0 RDC/SDIN = 1 INVSCLK = INVSYNC = 0 t1 CNVST t3 BUSY t17 SYNC t25 t19 t20 t21 1 2 3 16 17 18 t14 t24 SCLK t15 t18 t26 t27 D17 D16 D2 D1 D0 SDOUT X t16 t22 t23 03085-0-041 Figure 39. Master Serial Data Timing for Reading (Read Previous Conversion during Convert) SLAVE SERIAL INTERFACE External Clock The AD7679 is configured to accept an externally supplied serial data clock on the SCLK pin when the EXT/INT pin is held high. In this mode, several methods can be used to read the data. The external serial clock is gated by CS. When CS and RD are both low, the data can be read after each conversion or during the following conversion. The external clock can be either a continuous or a discontinuous clock. A discontinuous clock can be either normally high or normally low when inactive. Figure 40 and Figure 41 show the detailed timing diagrams of these methods. While the AD7679 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. This is particularly important during the second half of the conversion phase because the AD7679 provides error correction circuitr y that can correct for an improper bit decision made during the first half of the conversion phase. For this reason, it is recommended that when an external clock is being provided, it is a discontinuous clock that toggles only when BUSY is low or, more importantly, that it does not transition during the latter half of BUSY high. External Discontinuous Clock Data Read after Conversion This mode is the most recommended of the serial slave modes. Figure 40 shows the detailed timing diagrams of this method. After a conversion is complete, indicated by BUSY returning low, the result of this conversion can be read while both CS and RD are low. Data is shifted out MSB first with 18 clock pulses, and is valid on the rising and falling edge of the clock. Among the advantages of this method, the conversion performance is not degraded because there are no voltage transients on the digital interface during the conversion process. Also, data can be read at speeds up to 40 MHz, accommodating both slow digital host interface and the fastest serial reading. Finally, in this mode only, the AD7679 provides a daisy-chain feature using the RDC/SDIN input pin to cascade multiple converters together. This feature is useful for reducing component count and wiring connections when desired (for instance, in isolated multiconverter applications). An example of the concatenation of two devices is shown in Figure 42. Simultaneous sampling is possible by using a common CNVST signal. It should be noted that the RDC/SDIN input is latched on the edge of SCLK opposite the one used to shift out data on SDOUT. Thus, the MSB of the upstream converter follows the LSB of the downstream converter on the next SCLK cycle. Rev. 0 | Page 22 of 28 AD7679 CS EXT/INT = 1 INVSCLK = 0 RD = 0 BUSY t36 SCLK 1 t35 t37 2 3 17 18 19 20 t31 SDOUT X D17 t32 D16 D15 D1 D0 X17 X16 t16 t34 X17 X16 X15 X1 X0 Y17 Y16 SDIN t33 03085-0-042 Figure 40. Slave Serial Data Timing for Reading (Read after Convert) EXT/INT = 1 CS INVSCLK = 0 RD = 0 CNVST BUSY t3 t36 SCLK 1 t35 t37 2 3 17 18 t31 SDOUT X D17 t32 D16 D15 D1 D0 t16 03085-0-043 Figure 41. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert) Rev. 0 | Page 23 of 28 AD7679 BUSY OUT BUSY BUSY MICROPROCESSOR INTERFACING The AD7679 is ideally suited for traditional dc measurement applications supporting a microprocessor, and for ac signal processing applications interfacing to a digital signal processor. The AD7679 is designed to interface either with a parallel 8-bit or 16-bit wide interface, or with a general-purpose serial port or I/O ports on a microcontroller. A variety of external buffers can be used with the AD7679 to prevent digital noise from coupling into the ADC. The following section illustrates the use of the AD7679 with an SPI equipped DSP, the ADSP-219x. #2 (UPSTREAM) AD7679 #1 (DOWNSTREAM) AD7679 RDC/SDIN SDOUT CNVST CS SCLK RDC/SDIN SDOUT CNVST CS SCLK DATA OUT SCLK IN CS IN CNVST IN 03085-0-044 Figure 42. Two AD7679s in a Daisy-Chain Configuration SPI Interface (ADSP-219x) Figure 43 shows an interface diagram between the AD7679 and the SPI equipped ADSP-219x. To accommodate the slower speed of the DSP, the AD7679 acts as a slave device, and data must be read after conversion. This mode also allows the daisychain feature. The convert command could be initiated in response to an internal timer interrupt. The 18-bit output data are read with 3-byte SPI access. The reading process could be initiated in response to the end-of-conversion signal (BUSY going low) using an interrupt line of the DSP. The serial interface (SPI) on the ADSP-219x is configured for master mode (MSTR) = 1, Clock Polarity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00, by writing to the SPI Control register (SPICLTx). It should be noted that to meet all timing requirements, the SPI clock should be limited to 17 Mbits/s, which allow it to read an ADC result in about 1.1 µs. When a higher sampling rate is desired, use of one of the parallel interface modes is recommended. DVDD External Clock Data Read during Conversion Figure 41 shows the detailed timing diagrams of this method. During a conversion, while both CS and RD are low, the result of the previous conversion can be read. The data is shifted out MSB first with 18 clock pulses, and is valid on both the rising and falling edge of the clock. The 18 bits have to be read before the current conversion is complete. If that is not done, RDERROR is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. There is no daisychain feature in this mode, and the RDC/SDIN input should always be tied either high or low. To reduce performance degradation due to digital activity, a fast discontinuous clock is recommended to ensure that all bits are read during the first half of the conversion phase. It is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initiated. AD7679* SER/PAR EXT/INT BUSY CS RD INVSCLK SDOUT SCLK CNVST PFx ADSP-219x* SPIxSEL (PFx) MISOx SCKx PFx or TFSx * ADDITIONAL PINS OMITTED FOR CLARITY 03085-0-045 Figure 43. Interfacing the AD7679 to an SPI Interface Rev. 0 | Page 24 of 28 AD7679 APPLICATION HINTS LAYOUT The AD7679 has very good immunity to noise on the power supplies. However, care should still be taken with regard to grounding layout. The printed circuit board that houses the AD7679 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. Digital and analog ground planes should be joined in only one place, preferably underneath the AD7679, or at least as close to the AD7679 as possible. If the AD7679 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point that should be established as close to the AD7679 as possible. The user should avoid running digital lines under the device, as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD7679 to avoid noise coupling. Fast switching signals like CNVST or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. Crossover of digital and analog signals should be avoided. Traces on different but close layers of the board should run at right angles to each other. This will reduce the effect of feedthrough through the board. The power supply lines to the AD7679 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Good decoupling is also important to lower the supply’s impedance presented to the AD7679 and to reduce the magnitude of the supply spikes. Decoupling ceramic capacitors, typically 100 nF, should be placed close to and ideally right up against each power supply pin (AVDD, DVDD, and OVDD) and their corresponding ground pins. Additionally, low ESR 10 µF capacitors should be located near the ADC to further reduce low frequency ripple. The DVDD supply of the AD7679 can be a separate supply or can come from the analog supply, AVDD, or the digital interface supply, OVDD. When the system digital supply is noisy or when fast switching digital signals are present, and if no separate supply is available, the user should connect the DVDD digital supply to the analog supply AVDD through an RC filter, (see Figure 25), and connect the system supply to the interface digital supply OVDD and the remaining digital circuitry. When DVDD is powered from the system supply, it is useful to insert a bead to further reduce high frequency spikes. The AD7679 has four different ground pins: REFGND, AGND, DGND, and OGND. REFGND senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. AGND is the ground to which most internal ADC analog signals are referenced. This ground must be connected with the least resistance to the analog ground plane. DGND must be tied to the analog or digital ground plane depending on the configuration. OGND is connected to the digital system ground. The layout of the decoupling of the reference voltage is important. The decoupling capacitor should be close to the ADC and should be connected with short and large traces to minimize parasitic inductances. EVALUATING THE AD7679’S PERFORMANCE A recommended layout for the AD7679 is outlined in the documentation of the EVAL-AD7679CB evaluation board for the AD7679. The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVALCONTROL BRD2. Rev. 0 | Page 25 of 28 AD7679 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 48 1 PIN 1 9.00 BSC SQ 37 36 1.45 1.40 1.35 10 ° 6° 2° SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.10 MAX COPLANARITY (PINS DOWN ) TOP VIEW 7.00 BSC SQ VIEW A 12 13 24 25 0.15 0.05 SEATING PLANE VIEW A ROTATED 90° CCW 0.50 BSC 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026BBC Figure 44. 48-Lead Low Profile Quad Flatpack [LQFP] (ST-48) (Dimensions shown in millimeters) 7.00 BSC SQ 0.60 MAX 0.60 MAX 37 36 0.30 0.23 0.18 48 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 6.75 BSC SQ BOTTO M VIEW 5.25 5.10 SQ 4.95 0.50 0.40 0.30 0.80 MAX 0.65 NOM 0.05 MAX 0.02 NOM 0.50 BSC SEATING PLANE COPLANARITY 0.08 25 24 12 13 1.00 0.90 0.80 0.20 REF 5.50 REF PADDLE CONNECTED TO AGND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCE 12° MAX COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 Figure 45. 48-Lead Leadframe Chip Scale Package [LFCSP] (CP-48) (Dimensions shown in millimeters) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ORDERING GUIDE Model AD7679AST AD7679ASTRL AD7679ACP AD7679ACPRL EVAL-AD7679CB1 EVAL-CONTROL BRD22 1 2 Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C Package Description Quad Flatpack (LQFP) Quad Flatpack (LQFP) Lead Frame Chip Scale (LFCSP) Lead Frame Chip Scale (LFCSP) Evaluation Board Controller Board Package Option ST-48 ST-48 CP-48 CP-48 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes. This board allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. Rev. 0 | Page 26 of 28 AD7679 NOTES Rev. 0 | Page 27 of 28 AD7679 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies. C03085–0–7/03(0) Rev. 0 | Page 28 of 28