AD7827BRZ

a 3 V/5 V, 1 MSPS, 8-Bit, Serial Interface Sampling ADC AD7827 FEATURES 8-Bit Half-Flash ADC with 420 ns Conversion Time 200 ns Acquisition Time 8-Lead Package On-Chip Track-and-Hold On-Chip 2.5 V Reference with 2% Tolerance Operating Supply Range: 3 V 6 10% and 5 V 6 10% Specifications @ 3 V and 5 V DSP/Microcontroller Compatible Serial Interface Automatic Power-Down at End of Conversion Input Ranges 0 V to 2 V, VDD = 3 V 0 V to 2.5 V, VDD = 5 V FUNCTIONAL BLOCK DIAGRAM VDD VREFIN/VREFOUT 2.5V REF GND VDD DETECT COMP BUF AD7827 CONTROL LOGIC CONVST SCLK VIN T/H 8-BIT HALF-FLASH ADC SERIAL PORT DOUT RFS GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD7827 is a high speed, single channel, low power, analogto-digital converter with a maximum throughput of 1 MSPS that operates from a single 3 V or 5 V supply. The AD7827 contains a track/hold amplifier, an on-chip 2.5 V reference (2% tolerance), a 420 ns 8-bit half-flash ADC and a serial interface. The serial interface is compatible with the serial interfaces of most DSPs (Digital Signal Processors). The throughput rate of the AD7827 is dependent on the clock speed of the DSP serial interface. 1. Fast Conversion Time The AD7827 has a conversion time of 420 ns. Faster conversion times maximize the DSP processing time in a real time system. The AD7827 combines the Convert Start and Power Down signals at one pin, i.e., the CONVST pin. This allows a unique automatic power-down at the end of a conversion to be implemented. The logic level on the CONVST pin is sampled at the end of a conversion and, depending on its state, the AD7827 powers down. The AD7827 has one single-ended analog input with an input span determined by the supply voltage. With a VDD of 3 V, the input range of the AD7827 is 0 V to 2 V and with VDD equal to 5 V, the input range is 0 V to 2.5 V. 2. Built-In Track-and-Hold The analog input signal is held and a new conversion is initiated on the falling edge of the CONVST signal. The CONVST signal allows the sampling instant to be exactly controlled. This feature is a requirement in many DSP applications. 3. Automatic Power-Down The CONVST signal is sampled approximately 100 ns after the end of conversion and depending on its state the AD7827 is powered down. 4. An easy to use, fast serial interface allows direct interfacing to most popular DSPs with no external circuitry. The parts are available in a small, 8-lead, 0.3" wide, plastic dual-in-line package (DIP) and an 8-lead, small outline IC (SOIC). REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 (VDD = +3 V 6 10%, VDD = +5 V 6 10%, GND = 0 V, VREFIN/REFOUT = 2.5 V. All AD7827–SPECIFICATIONS specifications –408C to +1058C unless otherwise noted.) Parameter DYNAMIC PERFORMANCE Signal-to-(Noise + Distortion) Ratio1 Total Harmonic Distortion1 Peak Harmonic or Spurious Noise1 Intermodulation Distortion1 2nd Order Terms 3rd Order Terms DC ACCURACY Resolution Integral Nonlinearity (INL)1 Differential Nonlinearity (DNL)1 Offset Error1 Gain Error1 Minimum Resolution for Which No Missing Codes are Guaranteed Version B Units 48 –55 –55 dB min dB max dB max –65 –65 dB typ dB typ 8 ± 0.5 ± 0.5 ± 1.5 ±2 Bits LSB max LSB max LSB max LSB max 8 Bits 0 2.5 0 2 ±1 10 V min V max V min V max µA max pF max 2.55 2.45 ±1 ± 50 V max V min µA typ µA max 2.4 0.8 2.0 0.4 ±1 10 V min V max V min V max µA max pF max 4 2.4 V max V min 0.4 0.2 ±1 15 V max V min µA max pF max 420 200 ns max ns max Test Conditions/Comments fIN = 30 kHz; fSAMPLE = 1 MHz fa = 29.1 kHz; fb = 29.9 kHz 2 ANALOG INPUT Input Voltage Range Input Leakage Current Input Capacitance REFERENCE INPUT VREFIN/REFOUT Input Voltage Range Input Current LOGIC INPUTS CONVST, SCLK VINH, Input High Voltage VINL, Input Low Voltage VINH, Input High Voltage VINL, Input Low Voltage Input Current, IINH Input Capacitance LOGIC OUTPUTS DOUT, RFS VOH, Output High Voltage VOL, Output Low Voltage High Impedance Leakage Current High Impedance Capacitance CONVERSION RATE Conversion Time Track/Hold Acquisition Time –2– VDD = 5 V VDD = 3 V VDD = 5 V ± 10% VDD = 5 V ± 10% VDD = 3 V ± 10% VDD = 3 V ± 10% Typically 10 nA, VIN = 0 V or VDD ISOURCE = 200 µA VDD = 5 V ± 10% VDD = 3 V ± 10% ISINK = 200 µA VDD = 5 V ± 10% VDD = 3 V ± 10% REV. 0 AD7827 Parameter POWER SUPPLY VDD IDD Normal Operation Power-Down Power Dissipation Normal Operation Power-Down 200 kSPS 1 MSPS Version B Units Test Conditions/Comments 4.5 5.5 2.7 3.3 V min V max V min V max 5 V ± 10% For Specified Performance 10 1 mA max µA max 30 mW max 9.58 47.88 mW max mW max 3 V ± 10% For Specified Performance 8 mA Typically Logic Inputs = 0 V or VDD VDD = 3 V Typically 24 mW NOTES 1 See Terminology section of this data sheet. 2 Refer to the Analog Input section for an explanation of the Analog Input(s). Specifications subject to change without notice. TIMING CHARACTERISTICS1, 2 (V REFIN/REFOUT = 2.5 V, all specifications –408C to +1058C, unless otherwise noted) Parameter 5 V 6 10% 3 V 6 10% Units Conditions/Comments tCONVERT t1 t2 420 20 tCONVERT+t3 tCONVERT+t3+t7+t8 18 18 20 18 25 25 20 35 20 ns max ns min ns min ns max ns max ns max ns max ns max ns min ns min ns min ns max ns max Conversion Time. Minimum CONVST Pulsewidth. Falling edge of CONVST to falling edge of RFS. t10 420 20 tCONVERT+t3 tCONVERT+t3+t7+t8 14 14 20 14 25 25 20 35 20 t11 30 30 ns min tPOWER-UP 1 1 µs max tPOWER-UP 25 25 µs max t 33 t4 t 53 t 63 t7 t8 t 94 Rising edge of SCLK to falling edge of RFS. Rising edge of SCLK to rising edge of RFS. Rising edge of SCLK to high impedance disabled. Rising edge of SCLK to DOUT valid delay. Minimum high SCLK pulse duration. Minimum low SCLK pulse duration. Bus relinquish time after SCLK falling edge. Maximum delay from falling edge CONVST to rising edge RFS if RFS reset by CONVST. Minimum time between end of serial read and next falling edge of CONVST. Power-up time from rising edge of CONVST using external 2.5 V reference. Power-up time from rising edge of CONVST using on-chip reference. NOTES 1 Sample tested to ensure compliance. 2 See Figures 13, 14 and 15. 3 Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V with V DD = 5 V ± 10% and time required for an output to cross 0.4 V or 2.0 V with V DD = 3 V ± 10%. 4 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 9, quoted in the timing characteristics is the true bus relinquish time of the part and as such is independent of external bus loading capacitances. Specifications subject to change without notice. 200mA TO OUTPUT PIN IOL +2.1V CL 50pF 200mA IOH Figure 1. Load Circuit for Digital Output Timing Specifications REV. 0 –3– AD7827 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Digital Input Voltage to GND (CONVST, SCLK) . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V Digital Output Voltage to GND (DOUT, RFS) . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V Analog Input Voltage to AGND . . . . . . –0.3 V, VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . +300°C Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . +105°C/W Lead Temperature, (Soldering 10 sec) . . . . . . . . . . +260°C SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . +75°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . +215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . +220°C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 kV *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Pin No. Mnemonic Description 1 CONVST 2 3 VIN RFS 4 GND 5 6 VREF DOUT 7 SCLK 8 VDD Convert Start. Puts the track-andhold into hold mode and initiates a conversion. The state of this pin at the end of conversion also determines whether or not the part is powered down. Analog Input is applied here. Receive Frame Sync. This is an output. When this signal goes logic high at the end of a conversion, the DSP starts latching in data on the next cycle of SCLK. Ground reference for analog and digital circuitry. Reference Input. Serial Data is shifted out on this pin. Data is clocked out by the rising edges of SCLK. Serial Clock. An external serial clock is applied here. The clock must be continuous so the RFS (frame SYNC) can be synchronized to the clock for high speed data transfers. (See Microprocessor Interfacing section.) Positive Supply Voltage 3 V/5 V ± 10%. ORDERING GUIDE Model Linearity Error (LSB) Package Description Package Option AD7827BN AD7827BR ± 0.5 LSB ± 0.5 LSB Plastic DIP Small Outline IC N-8 SO-8 PIN CONFIGURATION CONVST 1 8 AD7827 VDD SCLK TOP VIEW RFS 3 (Not to Scale) 6 DOUT VIN 2 GND 4 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7827 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– 7 5 VREF WARNING! ESD SENSITIVE DEVICE REV. 0 AD7827 TERMINOLOGY Signal-to-(Noise + Distortion) Ratio order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the fundamental expressed in dBs. This is the measured ratio of signal-to-(noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Relative Accuracy Relative accuracy or endpoint nonlinearity is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB Differential Nonlinearity Thus for an 8-bit converter, this is 50 dB. This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7827 it is defined as: 2 THD (dB) = 20 log 2 2 2 Offset Error This is the deviation of the 128th code transition (01111111) to (10000000) from the ideal, i.e., VREF/2 (VDD = 5 V), 0.8 VREF/2 (VDD = 3 V). 2 V 2 +V 3 +V 4 +V 5 +V 6 V1 Zero Scale Error where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics. This is the deviation of the first code transition (00000000) to (00000001) from the ideal, i.e., VREF/2 –1.25 V + 1 LSB (VDD = 5 V ± 10%), or 0.8 VREF/2 –1.0 V + 1 LSB (VDD = 3 V ± 10%). Peak Harmonic or Spurious Noise Full-Scale Error Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts where the harmonics are buried in the noise floor, it will be a noise peak. This is the deviation of the last code transition (11111110) to (11111111) from the ideal, i.e., VMID + 1.25 V – 1 LSB (VDD = 5 V ± 10%), or VMID + 1.0 V – 1 LSB (VDD = 3 V ± 10%). Gain Error Intermodulation Distortion Track/Hold Acquisition Time With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which neither m nor n are equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). Track/hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ± 1/2 LSB, after the point at which the track/hold returns to track mode. This happens approximately 120 ns after the falling edge of CONVST. This is the deviation of the last code transition (1111 . . . 110) to (1111 . . . 111) from the ideal, i.e., VREF – 1 LSB, after the offset error has been adjusted out. It also applies when there is a step input change on the input voltage applied to the VIN input of the AD7827. It means that the user must wait for the duration of the track/hold acquisition time after the end of conversion or after a step input change to VIN before starting another conversion, to ensure that the part operates to specification. The AD7827 is tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second and third order terms are of different significance. The second order terms are usually distanced in frequency from the original sine waves while the third REV. 0 –5– AD7827 CIRCUIT DESCRIPTION of the second flash, and hence the 8-bit conversion result, is available at 330 ns. As shown in Figure 4 the track-and-hold returns to track mode after 120 ns, and so starts the next acquisition before the end of the current conversion. Figure 6 shows the ADC transfer function. The AD7827 consists of a track-and-hold amplifier followed by a half-flash analog-to-digital converter. This device uses a halfflash conversion technique where one 4-bit flash ADC is used to achieve an 8-bit result. The 4-bit flash ADC contains a sampling capacitor followed by 15 comparators that compare the unknown input to a reference ladder to get a 4-bit result. This first flash, i.e., coarse conversion, provides the 4 MSBs. For a full 8-bit reading to be realized, a second flash, i.e., a fine conversion, must be performed to provide the 4 LSBs. The 8-bit word is then placed in the serial shift register. 120ns TRACK B HOLD R14 13 R13 . . . . OUTPUT DRIVER SW2 OUTPUT REGISTER 14 T/H t10 RFS t7 t3 t4 t8 SCLK 1 DOUT DB7 DB6 2 3 4 DB5 5 DB4 6 DB3 DB2 7 DB1 8 DB0 Figure 4. Track-and-Hold Timing TYPICAL CONNECTION DIAGRAM Figure 5 shows a typical connection diagram for the AD7827. The serial interface is implemented using three wires; the RFS is a logic output and the serial clock is continuous. The Receive Frame Sync signal (RFS) idles high, the falling edge of CONVST initiates a conversion and the first rising edge of the serial clock after the end of conversion causes the RFS signal to go low. This falling edge of RFS is used to drive the RFS on a microprocessor—see Serial Interface section for more details. VREF is connected to a voltage source such as the AD780, while VDD is connected to a voltage source of 3 V ± 10% or 5 V ± 10%. Due to the proximity of the CONVST and VIN pins, it is recommended to use a 10 nF decoupling capacitor on VIN. When VDD is first connected the AD7827 powers up in a low current mode, i.e., power-down. A rising edge on the CONVST pin will cause the AD7827 to fully power up. For applications where power consumption is of concern, the automatic power-down at the end of a conversion should be used to improve power performance. See the Power-Down Options section of this data sheet. 15 DECODE LOGIC A VIN HOLD t2 REFERENCE SAMPLING CAPACITOR R15 TRACK CONVST Figures 2 and 3 below show simplified schematics of the ADC. When the ADC starts a conversion, the track-and-hold goes into hold mode and holds the analog input for 120 ns. This is the acquisition phase as shown in Figure 2 when Switch 2 is in Position A. At the point when the track-and-hold returns to its track mode, this signal is sampled by the sampling capacitor as Switch 2 moves into Position B. The first flash occurs at this instant and is then followed by the second flash. Typically the first flash is complete after 100 ns, i.e., at 220 ns, while the end R16 HOLD t1 DOUT 1 R1 TIMING AND CONTROL LOGIC Figure 2. ADC Acquisition Phase 2.5V AD780 SUPPLY +3V 610% OR +5V 610% REFERENCE SW2 HOLD B R14 13 R13 . . . . OUTPUT DRIVER 14 T/H DECODE LOGIC VIN THREE-WIRE SERIAL INTERFACE 0.1mF VDD SAMPLING CAPACITOR R15 A 10mF 15 OUTPUT REGISTER R16 VREF SCLK 0V TO 2.5V (VDD = 5V) 0V TO 2V (VDD = 3V) INPUT DOUT VIN AD7827 DOUT mC/mP RFS GND CONVST Figure 5. Typical Connection Diagram 1 R1 TIMING AND CONTROL LOGIC Figure 3. ADC Conversion Phase –6– REV. 0 AD7827 that of the multiplexer and the track-and-hold. This resistor is typically about 310 Ω. The capacitor C1 is the track-and-hold capacitor and has a capacitance of 0.5 pF. Switch 1 is the trackand-hold switch, while Switch 2 is that of the sampling capacitor as shown in Figures 2 and 3. ADC TRANSFER FUNCTION The output coding of the AD7827 is straight binary. The designed code transitions occur at successive integer LSB values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size is = VREF/256 (VDD = 5 V) or the LSB size = (0.8 VREF)/256 (VDD = 3 V). The ideal transfer characteristic for the AD7827 is shown in Figure 6 below. ADC CODE 11111111 111....110 When in track phase, Switch 1 is closed and Switch 2 is in Position A. When in hold mode, Switch 1 opens while Switch 2 remains in Position A. The track-and-hold remains in hold mode for 120 ns—see Circuit Description, after which it returns to track mode and the ADC enters its conversion phase. At this point Switch 1 opens and Switch 2 moves to Position B. At the end of the conversion Switch 2 moves back to Position A. (VDD = 5V) 1LSB = VREF/256 111....000 (VDD = 3V) 1LSB = 0.8VREF/256 10000000 VDD 000....111 D1 000....010 000....001 00000000 VIN C2 4pF 1LSB (VDD = 5V) VREF/2 (VDD = 3V) 0.8VREF/2 (VDD = 5V) VREF/2 – 1.25V (VDD = 3V) 0.8VREF/2 – 1V A SW2 SW1 B D2 VREF/2+1.25V – 1LSB 0.8VREF/2+1V – 1LSB Figure 7. Equivalent Analog Input Circuit Figure 6. Transfer Characteristic The on-chip track-and-hold can accommodate input frequencies to 10 MHz, making the AD7827 ideal for subsampling applications. When the AD7827 is converting a 10 MHz input signal at a sampling rate of 1 MSPS, the effective number of bits typically remains above seven corresponding to a signal-tonoise ratio of 42 dBs as shown in Figure 8. ANALOG INPUT The AD7827 has a single input channel with an input range of 0 V to 2.5 V or 0 V to 2.0 V, depending on the supply voltage (VDD). This input range is automatically set up by an on-chip “VDD detector” circuit. 5 V operation of the ADC is detected when VDD exceeds 4.1 V and 3 V operation is detected when VDD falls below 3.8 V. This circuit also possesses a degree of glitch rejection; for example, a glitch from 5.5 V to 2.7 V up to 60 ns wide will not trip the VDD detector. 50 FSAMPLE = 1MHz 48 46 SNR – dB Note: Although there is a VREF pin from which a voltage reference of 2.5 V may be sourced, or to which an external reference may be applied, this does not provide an option of varying the value of the voltage reference. As stated in the specifications for the AD7827, the input voltage range at this pin is 2.5 V ± 2%. 44 42 Analog Input Structure Figure 7 shows an equivalent circuit of the analog input structure of the AD7827. The two diodes, D1 and D2, provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV. This will cause these diodes to become forward biased and start conducting current into the substrate. The maximum current these diodes can conduct without causing irreversible damage to the part is 20 mA. The capacitor C2 in Figure 7 is typically about 4 pF and can mostly be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of several components including REV. 0 C1 0.5pF R1 310V 40 38 0.2 1 3 4 5 6 INPUT FREQUENCY – MHz 8 10 Figure 8. SNR vs. Input Frequency On the AD7827 –7– AD7827 POWER-UP TIMES For example, if the AD7827 is operated in a continuous sampling mode, with a throughput rate of 100 kSPS and using an external reference, the power consumption is calculated as follows. The power dissipation during normal operation is 30 mW, VDD = 3 V. The AD7827 has a 1 µs power-up time when using an external reference and a 25 µs power-up time when using the on-chip reference. When VDD is first connected, the AD7827 is in a low current mode of operation. In order to carry out a conversion the AD7827 must first be powered up. The AD7827 is powered up by a rising edge on the CONVST pin and a conversion is initiated on the falling edge of CONVST. Figure 9 shows how to power up the AD7827 when VDD is first connected or after the ADC has been powered down using the CONVST pin when using either the on-chip, or an external, reference. When using an external reference the falling edge of CONVST may occur before the required power-up time has elapsed; however, the conversion will not be initiated on the falling edge of CONVST but rather at the moment when the part has completely powered up, i.e., after 1 µs. If the falling edge of CONVST occurs after the required power-up time has elapsed, it is upon this falling edge that a conversion is initiated. When using the on-chip reference, it is necessary to wait the required power-up time of approximately 25 µs before initiating a conversion, i.e., a falling edge on CONVST may not occur before the required power-up time has elapsed, when VDD is first connected or after the AD7827 has been powered down using the CONVST pin as shown in Figure 9. tPOWER-UP tCONVERT 1ms 330ns POWER-DOWN CONVST tCYCLE 10ms @ 100kSPS Figure 10. Automatic Power-Down If the power-up time is 1 µs and the conversion time is 330 ns (@ 25°C), the AD7827 can be said to dissipate 30 mW for 1.33 µs (worst case) during each conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 µs and the average power dissipated during each cycle is (1.33/10) × (30 mW) = 3.99 mW. Figure 11 shows the Power vs. Throughput rate for automatic full power-down. 100 EXTERNAL REFERENCE VDD tPOWER-UP 10 POWER – mW 1ms CONVST CONVERSION INITIATED HERE 1 ON-CHIP REFERENCE VDD tPOWER-UP 25ms 0.1 0 CONVST 50 100 150 200 250 300 350 THROUGHPUT – kSPS 400 450 500 Figure 11. Power vs. Throughput CONVERSION INITIATED HERE Figure 9. Power-Up Time 0 2048 POINT FFT SAMPLING 1MSPS FIN = 30kHz –10 POWER VS. THROUGHPUT Superior power performance can be achieved by using the automatic power-down (Mode 2) at the end of a conversion (see Operating Modes section of this data sheet). –20 –30 dB Figure 10 shows how the automatic power-down is implemented using the CONVST signal to achieve the optimum power performance for the AD7827. The duration of the CONVST pulse is set to be equal to or less than the power-up time of the devices (see Operating Modes section). As the throughput rate is reduced, the device remains in its power-down state for longer and the average power consumption over time drops accordingly. –40 –50 –60 –70 –80 0 50 100 150 200 250 300 350 FREQUENCY – Hz 400 450 500 Figure 12. AD7827 SNR –8– REV. 0 AD7827 OPERATING MODES Mode 2 Operation (Automatic Power-Down) The AD7827 has two possible modes of operation depending on the state of the CONVST pulse at the end of a conversion. When the AD7827 is operated in Mode 2 (see Figure 14) it automatically powers down 530 ns after the falling edge of CONVST. The CONVST signal is brought low to initiate a conversion and is left logic low until 530 ns has elapsed after the falling edge of the CONVST pulse, i.e., before Point A or Point B in Figure 14, depending on the actual value of t2 (see Timing Characteristics). The state of the CONVST signal is sampled at this point (i.e., 530 ns after CONVST falling edge) and the AD7827 will power down as long as the CONVST is low. The ADC is powered up again on the rising edge of the CONVST signal. The CONVST pulse width does not have to be as long as the power-up time if an external reference is used (see Power-Up Times section). Superior power performance can be achieved in this mode of operation by powering up the AD7827 to only carry out a conversion. The serial interface of the AD7827 is still fully operational while the device is powered down. Mode 1 Operation (High Speed Sampling) When the AD7827 is operated in Mode 1 the device is not powered down between conversions. This mode of operation allows high throughput rates to be achieved. Figure 13 shows how this optimum throughput rate is achieved by bringing CONVST high before the end of the conversion. When operating in this mode, a new conversion should not be initiated until 30 ns after the end of a read operation. This is to allow the track/hold to acquire the analog signal to 0.5 LSB accuracy. t2 CONVST t1 RFS SCLK CURRENT CONVERSION RESULT DOUT Figure 13. Mode 1 Operation Timing Diagram tPOWER-UP t2 CONVST A B RFS SCLK DOUT CURRENT CONVERSION RESULT Figure 14. Mode 2 Operation Timing Diagram REV. 0 –9– AD7827 synchronize the data with a continuous serial clock. The data output pin (DOUT) is a logic output and serial data is shifted out onto this pin on the rising edge of the serial clock. The first rising edge of the serial clock after the end of a conversion causes the RFS pin to go logic low. (See Figure 15 below.) The DOUT pin leaves its high impedance state and the first MSB is shifted out on the first SCLK rising edge after the end of conversion. The remaining seven data bits are shifted out on subsequent SCLK rising edges. The DOUT pin enters its high impedance state again on the falling edge of the eighth SCLK after RFS goes low. The RFS output goes high again on the rising edge of the ninth SCLK. If the AD7827 does not receive a ninth SCLK, the RFS will be reset logic high by the next falling edge of CONVST. AD7827 SERIAL INTERFACE In order to achieve a high throughput rate, the serial port of the AD7827 has been optimized for high speed serial protocols. Many high speed serial protocols use a continuous serial clock to transfer data, e.g., the serial ports of many popular DSPs like the TMS320C5x, ADSP-21xx and DSP560xx. The serial interface of the AD7827 is optimized for communication with such devices. The serial interface of the AD7827 uses a three-wire interface to communicate with a Master. The serial clock pin (SCLK) is a logic input and determines the bit transfer rate. The Receive Frame Synchronization pin (RFS) is a logic output and used to t1 CONVST t2 t10 RFS t7 t3 SCLK 1 2 t5 DOUT DB7 3 t8 t4 4 5 DB4 DB3 6 7 8 DB2 DB1 DB0 t6 DB6 DB5 t11 t9 Figure 15. Serial Timing –10– REV. 0 AD7827 MICROPROCESSOR INTERFACING AD7827 to DSP56xxx The Serial Interface on the AD7827 allows the part to be connected directly to a range of many different microprocessors and microcontrollers. This section explains how to interface the AD7827 with some of the more common DSP serial interface protocols. The connection diagram in Figure 18 shows how the AD7827 can be connected to the SSI (Synchronous Serial Interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in Synchronous Mode (SYN bit in CRB = 1) with internally generated 1-bit clock period frame sync for both TX and RX (FSL1 and FSL0 bits in CRB = 1 and 0 respectively). AD7827 to TMS320C5x The serial interface on the TMS320C5x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices such as the AD7827. A receive frame synchronization output has been supplied on the AD7827 to allow easy interfacing with no extra gluing logic. The serial port of the TMS320C5x is set up to operate in Burst Mode with internal CLKX (TX serial clock) and FSR (RX frame sync). The Serial Port Control register (SPC) must have the following setup: F0 = 1, FSM = 1, MCM = 1. The connection diagram is shown in Figure 16. AD7827* SCLK TMS320C5x* CLKX CLKR DOUT DR RFS FSR AD7827* TFSW = RFSW = 1, Alternate Framing INVRFS = INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data SLEN = 0111, 8-Bit Data Words ISCLK = 1, Internal Serial Clock TFSR = RFSR = 1, Frame Every Word IRFS = 0, External Framing Signal ITFS = 1, Internal Framing Signal The 8-bit data words will be right justified in the 16-bit serial data registers when using this configuration. Figure 17 shows the connection diagram. ADSP-21xx* SCLK DR RFS *ADDITIONAL PINS OMITTED FOR CLARITY Figure 17. Interfacing to the ADSP-21xx REV. 0 SC2 The AD7827 may also be interfaced to many microcontrollers, as a continuous serial clock is not essential. However, enough time must be left for the conversion to be complete before applying a burst of serial clocks to read out the data. The ADSP-21xx family of DSPs are easily interfaced to the AD7827 without the need for any extra gluing logic. The SPORT is operated in alternate framing mode. The SPORT control register should be set up as follows: RFS SRD RFS Microcontrollers AD7827 to ADSP-21xx DOUT DOUT Figure 18. Interfacing to the DSP56xxx Figure 16. Interfacing to the TMS320C5x SCLK SCLK *ADDITIONAL PINS OMITTED FOR CLARITY *ADDITIONAL PINS OMITTED FOR CLARITY AD7827* DSP56xxx* SCLK –11– AD7827 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3215–8–1/98 8-Lead Plastic DIP (N-8) 0.430 (10.92) 0.348 (8.84) 8 5 0.280 (7.11) 0.240 (6.10) 1 4 0.060 (1.52) 0.015 (0.38) PIN 1 0.210 (5.33) MAX 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.100 0.070 (1.77) 0.014 (0.356) (2.54) 0.045 (1.15) BSC 0.015 (0.381) 0.008 (0.204) SEATING PLANE 8-Lead Small Outline Package (SO-8) 0.1968 (5.00) 0.1890 (4.80) 0.1574 (4.00) 0.1497 (3.80) PIN 1 SEATING PLANE 5 1 4 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC 0.0196 (0.50) x 45° 0.0099 (0.25) 0.0098 (0.25) 0.0075 (0.19) 8° 0° 0.0500 (1.27) 0.0160 (0.41) PRINTED IN U.S.A. 0.0098 (0.25) 0.0040 (0.10) 8 –12– REV. 0