LC2MOS
Quad 14-Bit DACs
AD7834/AD7835
into one via DIN, SCLK, and FSYNC. The AD7834 has five
dedicated package address pins, PA0 to PA4, that can be wired
to AGND or VCC to permit up to 32 AD7834s to be individually
addressed in a multipackage application.
FEATURES
Four 14-bit DACs in one package
AD7834—serial loading
AD7835—parallel 8-bit/14-bit loading
Voltage outputs
Power-on reset function
Maximum/minimum output voltage range of ±8.192 V
Maximum output voltage span of 14 V
Common voltage reference inputs
User-assigned device addressing
Clear function to user-defined voltage
Surface-mount packages
AD7834—28-lead SOIC and PDIP
AD7835—44-lead MQFP and PLCC
The AD7835 can accept either 14-bit parallel loading or doublebyte loading, where right-justified data is loaded in one 8-bit
byte and one 6-bit byte. Data is loaded from the external bus
into one of the input latches under the control of the WR, CS,
BYSHF, and DAC channel address pins, A0 to A2.
GENERAL DESCRIPTION
With each device, the LDAC signal is used to update all four
DAC outputs simultaneously, or individually, on reception of
new data. In addition, for each device, the asynchronous CLR
input can be used to set all signal outputs, VOUT1 to VOUT4, to
the user-defined voltage level on the device sense ground pin,
DSG. On power-on, before the power supplies have stabilized,
internal circuitry holds the DAC output voltage levels to within
±2 V of the DSG potential. As the supplies stabilize, the DAC
output levels move to the exact DSG potential (assuming CLR is
exercised).
The AD7834 and AD7835 contain four 14-bit DACs on one
monolithic chip. The AD7834 and AD7835 have output
voltages in the range ±8.192 V with a maximum span of 14 V.
The AD7834 is available in a 28-lead 0.3" SOIC package and a
28-lead 0.6" PDIP package, and the AD7835 is available in a
44-lead MQFP package and a 44-lead PLCC package.
APPLICATIONS
Process control
Automatic test equipment
General-purpose instrumentation
The AD7834 is a serial input device. Data is loaded in 16-bit
format from the external serial bus, MSB first after two leading 0s,
FUNCTIONAL BLOCK DIAGRAMS
AD7834
PAEN
PA3
DAC 1
LATCH
AD7835
DAC 1
BYSHF
×1
CONTROL
LOGIC
AND
ADDRESS
DECODE
PA4
INPUT
REGISTER
2
DAC 2
LATCH
DB0
DAC 2
×1
INPUT
REGISTER
3
DAC 3
LATCH
SERIAL-TOPARALLEL
CONVERTER
INPUT
REGISTER
4
VOUT 3
A1
AGND
DGND
LDAC
DSG
Figure 1. AD7834
ADDRESS
DECODE
A2
VOUT 4
CLR
SCLK
VREF (–)A VREF (+)A DSGA
INPUT
REGISTER
1
DAC 1
LATCH
INPUT
REGISTER
2
DAC 2
LATCH
INPUT
REGISTER
3
DAC 3
LATCH
INPUT
REGISTER
4
DAC 4
LATCH
DAC 1
×1
VOUT1
×1
VOUT2
×1
VOUT3
DAC 2
DAC 3
A0
DAC 4
×1
VSS
WR
CS
×1
DAC 4
LATCH
VOUT 2
VDD
14
INPUT
BUFFER
DAC 3
FSYNC
DIN
VOUT 1
01006-001
PA2
INPUT
REGISTER
1
VCC
VREF (–) VREF (+)
VSS
DB13
PA0
PA1
VDD
DAC 4
×1
VOUT4
CLR
AGND
DGND
LDAC VREF (–)B VREF (+)B DSGB
01006-002
VCC
Figure 2. AD7835
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2007 Analog Devices, Inc. All rights reserved.
AD7834/AD7835
TABLE OF CONTENTS
Features .............................................................................................. 1
Power-On with CLR Low, LDAC High ................................... 17
Applications....................................................................................... 1
Power-On with LDAC Low, CLR High ................................... 17
General Description ......................................................................... 1
Loading the DAC and Using the CLR Input .......................... 17
Functional Block Diagrams............................................................. 1
DSG Voltage Range .................................................................... 18
Revision History ............................................................................... 2
Power-On of the AD7834/AD7835.............................................. 19
Specifications..................................................................................... 3
Microprocessor Interfacing........................................................... 20
AC Performance Characteristics ................................................ 5
AD7834 to 80C51 Interface ...................................................... 20
Timing Specifications .................................................................. 6
AD7834 to 68HC11 Interface ................................................... 20
Absolute Maximum Ratings............................................................ 7
AD7834 to ADSP-2101 Interface ............................................. 20
Thermal Resistance ...................................................................... 7
AD7834 to DSP56000/DSP56001 Interface............................ 21
ESD Caution.................................................................................. 7
AD7834 to TMS32020/TMS320C25 Interface....................... 21
Pin Configurations and Function Descriptions ........................... 8
Interfacing the AD7835—16-Bit Interface.............................. 21
Typical Performance Characteristics ........................................... 11
Interfacing the AD7835—8-Bit Interface................................ 22
Terminology .................................................................................... 13
Applications Information .............................................................. 23
Theory of Operation ...................................................................... 14
Serial Interface to Multiple AD7834s ...................................... 23
DAC Architecture....................................................................... 14
Opto-Isolated Interface ............................................................. 23
Data Loading—AD7834 Serial Input Device ......................... 14
Automated Test Equipment ...................................................... 23
Data Loading—AD7835 Parallel Loading Device ................. 14
Power Supply Bypassing and Grounding................................ 24
Unipolar Configuration............................................................. 15
Outline Dimensions ....................................................................... 25
Bipolar Configuration................................................................ 16
Ordering Guide .......................................................................... 27
Controlled Power-On of the Output Stage.................................. 17
REVISION HISTORY
8/07—Rev. C to Rev. D
Changes to Table 5 ........................................................................... 7
Added Table 6.................................................................................... 7
Changes to Table 8............................................................................ 9
Updated Outline Dimensions ....................................................... 25
Changes to Ordering Guide .......................................................... 27
7/05—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Figure 40...................................................................... 25
Changes to Ordering Guide .......................................................... 27
7/03—Rev. A to Rev. B
Revision 0: Initial Version
Rev. D | Page 2 of 28
AD7834/AD7835
SPECIFICATIONS
VCC = 5 V ± 5%; VDD = 15 V ± 5%; VSS = −15 V ± 5%; AGND = DGND = 0 V; TA 1 = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
TMIN to TMAX
Zero-Scale Error
Gain Error
Gain Temperature
Coefficient 2
A
B
S
Unit
14
±2
±0.9
14
±1
±0.9
14
±2
±0.9
Bits
LSB max
LSB max
±5
±4
±0.5
4
±5
±4
±0.5
4
±8
±5
±0.5
4
mV max
mV max
mV typ
ppm FSR/°C typ
20
50
20
50
20
50
ppm FSR/°C max
μV max
30
±1
0/8.192
−8.192/0
5/14
30
±1
0/8.192
−8.192/0
7/14
30
±1
0/8.192
−8.192/0
5/14
MΩ typ
μA max
V min/max
V min/max
V min/max
±2
±2
±2
μA max
2.4
2.4
2.4
V min
VINL, Input Low Voltage
0.8
0.8
0.8
V max
IINH, Input Current
±10
±10
±10
μA max
CIN, Input Capacitance
10
10
10
pF max
5.0
15.0
−15.0
5.0
15.0
−15.0
5.0
15.0
−15.0
V nom
V nom
V nom
±5% for specified performance.
±5% for specified performance.
±5% for specified performance.
110
100
0.2
3
6
13
15
13
110
100
0.2
3
6
13
15
13
110
100
0.5
3
6
15
15
15
dB typ
dB typ
mA max
mA max
mA max
mA max
mA max
mA max
VINH = VCC, VINL = DGND.
AD7834: VINH = 2.4 V min, VINL = 0.8 V max.
AD7835: VINH = 2.4 V min, VINL = 0.8 V max.
AD7834: outputs unloaded.
AD7835: outputs unloaded.
Outputs unloaded.
DC Crosstalk2
REFERENCE INPUTS
DC Input Resistance
Input Current
VREF(+) Range
VREF(−) Range
VREF(+) − VREF(−)
Test Conditions/Comments
Guaranteed monotonic over temperature.
VREF(+) = +7 V, VREF(−) = −7 V.
VREF(+) = +7 V, VREF(−) = −7 V.
VREF(+) = +7 V, VREF(−) = −7 V.
See the Terminology section. RL = 10 kΩ.
Per input.
For specified performance. Can go as low as
0 V, but performance is not guaranteed.
DEVICE SENSE GROUND INPUTS
Input Current
DIGITAL INPUTS
VINH, Input High Voltage
POWER REQUIREMENTS
VCC
VDD
VSS
Power Supply Sensitivity
ΔFull Scale/ΔVDD
ΔFull Scale/ΔVSS
ICC
IDD
ISS
1
2
Temperature range for A, B, and C versions is −40°C to +85°C.
Guaranteed by design.
Rev. D | Page 3 of 28
Per input. VDSG = −2 V to +2 V.
AD7834/AD7835
VCC = 5 V ± 5%; VDD = 12 V ± 5%; VSS = −12 V ± 5%; AGND = DGND = 0 V; TA 1 = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
ACCURACY
Resolution
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
TMIN to TMAX
Zero-Scale Error
Gain Error
Gain Temperature Coefficient 2
A
B
S
Unit
14
±2
±0.9
14
±1
±0.9
14
±2
±0.9
Bits
LSB max
LSB max
±5
±4
±0.5
4
20
50
±5
±4
±0.5
4
20
50
±8
±5
±0.5
4
20
50
mV max
mV max
mV typ
ppm FSR/°C typ
ppm FSR/°C max
μV max
30
±1
0/8.192
−5/0
5/13.192
30
±1
0/8.192
−5/0
7/13.192
30
±1
0/8.192
−5/0
5/13.192
MΩ typ
μA max
V min/max
V min/max
V min/max
±2
±2
±2
μA max
2.4
2.4
2.4
V min
VINL, Input Low Voltage
0.8
0.8
0.8
V max
IINH, Input Current
±10
±10
±10
μA max
CIN, Input Capacitance
10
10
10
pF max
5.0
15.0
−15.0
5.0
15.0
−15.0
5.0
15.0
−15.0
V nom
V nom
V nom
±5% for specified performance.
±5% for specified performance.
±5% for specified performance.
110
100
0.2
3
6
13
15
13
110
100
0.2
3
6
13
15
13
110
100
0.5
3
6
15
15
15
dB typ
dB typ
mA max
mA max
mA max
mA max
mA max
mA max
VINH = VCC, VINL = DGND.
AD7834: VINH = 2.4 V min, VINL = 0.8 V max.
AD7835: VINH = 2.4 V min, VINL = 0.8 V max.
AD7834: outputs unloaded.
AD7835: outputs unloaded.
Outputs unloaded.
DC Crosstalk2
REFERENCE INPUTS
DC Input Resistance
Input Current
VREF(+) Range
VREF(−) Range
VREF(+) − VREF(−)
Test Conditions/Comments
Guaranteed monotonic over temperature.
VREF(+) = +5 V, VREF(−) = –5 V.
VREF(+) = +5 V, VREF(−) = −5 V.
VREF(+) = +5 V, VREF(−) = −5 V.
See the Terminology section. RL = 10 kΩ.
Per input.
For specified performance. Can go as low as
0 V, but performance is not guaranteed.
DEVICE SENSE GROUND INPUTS
Input Current
DIGITAL INPUTS
VINH, Input High Voltage
POWER REQUIREMENTS
VCC
VDD
VSS
Power Supply Sensitivity
ΔFull Scale/ΔVDD
ΔFull Scale/ΔVSS
ICC
IDD
ISS
1
2
Temperature range for A, B, and C versions is −40°C to +85°C.
Guaranteed by design.
Rev. D | Page 4 of 28
Per input. VDSG = −2 V to +2 V.
AD7834/AD7835
AC PERFORMANCE CHARACTERISTICS
These characteristics are included for design guidance and are not subject to production testing.
Table 3.
Parameter
DYNAMIC PERFORMANCE
Output Voltage Settling Time
A
B
S
Unit (typ)
Test Conditions/Comments
10
10
10
μs
Digital-to-Analog Glitch Impulse
120
120
120
nV-s
DC Output Impedance
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
0.5
100
25
3
0.5
100
25
3
0.5
100
25
3
Ω
dB
nV-s
nV-s
Digital Feedthrough—AD7834
Digital Feedthrough—AD7835
Output Noise Spectral Density at 1 kHz
0.2
1.0
40
0.2
1.0
40
0.2
1.0
40
nV-s
nV-s
nV/√Hz
Full-scale change to ±1/2 LSB. DAC latch contents
alternately loaded with all 0s and all 1s.
Measured with VREF(+) = VREF(−) = 0 V. DAC latch
alternately loaded with all 0s and all 1s.
See the Terminology section.
See the Terminology section; applies to the AD7835 only.
See the Terminology section.
Feedthrough to DAC output under test due to change in
digital input code to another converter.
Effect of input bus activity on DAC output under test.
Rev. D | Page 5 of 28
All 1s loaded to DAC. VREF(+) = VREF(−) = 0 V.
AD7834/AD7835
TIMING SPECIFICATIONS
VCC = 5 V ± 5%; VDD = 11.4 V to 15.75 V; VSS = −11.4 V to −15.75 V; AGND = DGND = 0 V 1 .
Table 4.
Parameter
AD7834-SPECIFIC
t1 2
t22
t32
t4
t5
t6
t7
t8
t9
t21
AD7835-SPECIFIC
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
GENERAL
t10
1
2
Limit at TMIN, TMAX
Unit
Description
100
50
30
30
40
30
10
0
40
20
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK cycle time
SCLK low
SCLK high time
FSYNC, PAEN setup time
FSYNC, PAEN hold time
Data setup time
Data hold time
LDAC to FSYNC setup time
LDAC to FSYNC hold time
Delay between write operations
15
15
0
0
40
40
10
0
0
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
A0, A1, A2, BYSHF to CS setup time
A0, A1, A2, BYSHF to CS hold time
CS to WR setup time
CS to WR hold time
WR pulse width
Data setup time
Data hold time
LDAC to CS setup time
CS to LDAC setup time
LDAC to CS hold time
40
ns min
LDAC, CLR pulse width
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and time from a voltage level of 1.6 V.
Rise and fall times should be no longer than 50 ns.
1ST 2ND
CLK CLK
t1
24TH
CLK
A0 A1 A2
BYSHF
SCLK
t4
t2
t 11
t5
t3
CS
FSYNC
t 21
MSB
LDAC
(PER-CHANNEL
UPDATE)
D23
t13
D22
D1
WR
D0
t 10
t8
t 14
t 15
LSB
t16
t17
DB0 TO DB13
t9
01006-003
LDAC
(SIMULTANEOUS
UPDATE)
t7
t10
LDAC
(SIMULTANEOUS
UPDATE)
t19
t 18
LDAC
(PER-CHANNEL
UPDATE)
Figure 3. AD7834 Timing Diagram
t 20
Figure 4. AD7835 Timing Diagram
Rev. D | Page 6 of 28
01006-004
t6
DIN
t 12
AD7834/AD7835
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up. VCC must not exceed VDD by more than
0.3 V. If it is possible for this to happen during power supply sequencing, the diode protection scheme shown in Figure 5 can be used to
provide protection.
VDD
Table 5.
VDD to AGND
VSS to AGND
AGND to DGND
Digital Inputs to DGND
VREF(+) to VREF(–)
VREF(+) to AGND
VREF(–) to AGND
DSG to AGND
VOUT (1–4) to AGND
Operating Temperature Range, TA
Industrial (A Version)
Storage Temperature Range
Junction Temperature, TJ (max)
Power Dissipation, PD (max)
Lead Temperature
Soldering
Rating
−0.3 V to +7 V, or VDD + 0.3 V
(whichever is lower)
−0.3 V to +17 V
+0.3 V to –17 V
−0.3 V to +0.3 V
−0.3 V to VCC + 0.3 V
−0.3 V to +18 V
VSS – 0.3 V to VDD + 0.3 V
VSS – 0.3 V to VDD + 0.3 V
VSS – 0.3 V to VDD + 0.3 V
VSS – 0.3 V to VDD + 0.3 V
−40°C to +85°C
−65°C to +150°C
150°C
(TJ − TA)/θJA
JEDEC Industry Standard
J-STD-020
SD103C
VDD
VCC
AD7834/
AD7835
01006-005
Parameter
VCC to DGND
VCC
IN4148
Figure 5. Diode Protection
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 6. Thermal Resistance
Package Type
PDIP
SOIC
MQFP
PLCC
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. D | Page 7 of 28
θJA
75
75
95
55
Unit
°C/W
°C/W
°C/W
°C/W
AD7834/AD7835
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VSS 1
28
AGND
DSG 2
27
NC
VREF(–) 3
26
NC
VREF(+) 4
25
NC
NC 5
24
NC
VOUT2 6
23
VDD
DGND 8
21
VOUT3
VCC 9
20
CLR
SCLK 10
19
LDAC
DIN 11
18
FSYNC
PA0 12
17
PAEN
PA1 13
16
PA4
PA2 14
15
PA3
AD7834
NC = NO CONNECT
01006-006
TOP VIEW
VOUT4 7 (Not to Scale) 22 VOUT1
Figure 6. AD7834 PDIP and SOIC Pin Configuration
Table 7. AD7834 Pin Function Descriptions
Pin No.
1
2
Pin Mnemonic
VSS
DSG
3
4
5, 24, 25, 26, 27
22, 6, 21, 7
8
9
10
VREF(−)
VREF(+)
NC
VOUT1 to VOUT4
DGND
VCC
SCLK
11
12,13,14,15,16
DIN
PA0 to PA4
17
PAEN
18
FSYNC
19
LDAC
20
CLR
23
28
VDD
AGND
Description
Negative Analog Power Supply: −15 V ± 5% or −12 V ± 5%.
Device Sense Ground Input. Used in conjunction with the CLR input for power-on protection of
the DACs. When CLR is low, the DAC outputs are forced to the potential on the DSG pin.
Negative Reference Input. The negative reference voltage is referred to AGND.
Positive Reference Input. The positive reference voltage is referred to AGND.
No Connect.
DAC Outputs.
Digital Ground.
Logic Power Supply: 5 V ± 5%.
Clock Input. Used for writing data to the device; data is clocked into the input register on the
falling edge of SCLK.
Serial Data Input.
Package Address Inputs. These inputs are hardwired high (VCC) or low (DGND) to assign dedicated
package addresses in a multipackage environment.
Package Address Enable Input. When low, this input allows normal operation of the device. When
high, the device ignores the package address, but not the channel address, in the serial data
stream and loads the serial data into the input registers. This feature is useful in a multipackage
application where it can be used to load the same data into the same channel in each package.
Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to
the device with serial data expected after the falling edge of this signal. The contents of the 24-bit
serial-to-parallel input register are transferred on the rising edge of this signal.
Load DAC Input (Level Sensitive). This input signal, in conjunction with the FSYNC input signal,
determines how the analog outputs are updated. If LDAC is maintained high while new data is
being loaded into the device’s input registers, no change occurs on the analog outputs.
Subsequently, when LDAC is brought low, the contents of all four input registers are transferred
into their respective DAC latches, updating all of the analog outputs simultaneously.
Asynchronous Clear Input (Level Sensitive, Active Low). When this input is brought low, all analog
outputs are switched to the externally set potential on the DSG pin. When CLR is brought high, the
signal outputs remain at the DSG potential until LDAC is brought low. When LDAC is brought low,
the analog outputs are switched back to reflect their individual DAC output levels. As long as CLR
remains low, the LDAC signals are ignored, and the signal outputs remain switched to the
potential on the DSG pin.
Positive Analog Power Supply: 15 V ± 5% or 12 V ± 5%.
Analog Ground.
Rev. D | Page 8 of 28
NC
VREF(–)B
1
VREF(+)B
VSS
VDD
2
AGND
NC
3
NC
VREF(–)A
4
44 43 42 41 40
PIN 1
IDENTIFIER
NC 7
33 NC
PIN 1
IDENTIFIER
5
39 NC
32 DSGB
DSGA 8
38 DSGB
VOUT1 3
31 VOUT3
VOUT1 9
37 VOUT3
VOUT2 4
30 VOUT4
VOUT2 10
DSGA 2
NC 5
AD7835
A2 6
TOP VIEW
(Not to Scale)
A1 7
A0 8
29 DB13
NC 11
28 DB12
A2 12
27 DB11
A1 13
26 DB10
A0 14
36 VOUT4
35 DB13
AD7835
34 DB12
TOP VIEW
(Not to Scale)
33 DB11
32 DB10
CLR 9
25 DB9
CLR 15
31 DB9
LDAC 10
24 DB8
LDAC 16
30 DB8
BYSHF 11
23 DB7
BYSHF 17
29 DB7
Figure 7. AD7835 MQFP Pin Configuration
DB6
DB4
DB5
DB3
DB2
DB1
DB0
DGND
VCC
CS
NC = NO CONNECT
WR
18 19 20 21 22 23 24 25 26 27 28
01006-007
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VCC
DGND
CS
NC = NO CONNECT
WR
12 13 14 15 16 17 18 19 20 21 22
01006-008
NC 1
6
VREF(+)A
44 43 42 41 40 39 38 37 36 35 34
NC
NC
VREF(+)B
VREF(–)B
NC
AGND
VDD
VSS
VREF(+)A
NC
NC
VREF(–)A
AD7834/AD7835
Figure 8. AD7835 PLCC Pin Configuration
Table 8. AD7835 Pin Function Descriptions
Pin No.
MQFP
1, 5, 33, 34,
37, 41, 44
Pin No. PLCC
3, 6, 7, 11, 39,
40, 43
Pin Mnemonic
NC
Description
No Connect.
2
8
DSGA
3, 4, 31, 30
8, 7, 6
9, 10, 37, 36
14, 13, 12
VOUT1 to VOUT4
A0, A1, A2
9
15
CLR
10
16
LDAC
11
17
BYSHF
12
18
CS
13
19
WR
14
15
20
21
VCC
DGND
Device Sense Ground A Input. Used in conjunction with the CLR input for power-on
protection of the DACs. When CLR is low, DAC outputs VOUT1 and VOUT2 are forced to the
potential on the DSGA pin.
DAC Outputs.
Address Inputs. A0 and A1 are decoded to select one of the four input latches for a data
transfer. A2 is used to select all four DACs simultaneously.
Asynchronous Clear Input (Level Sensitive, Active Low). When this input is brought low,
all analog outputs are switched to the externally set potentials on the DSG pins (VOUT1
and VOUT2 follow DSGA, and VOUT3 and VOUT4 follow DSGB). When CLR is brought high, the
signal outputs remain at the DSG potentials until LDAC is brought low. When LDAC is
brought low, the analog outputs are switched back to reflect their individual DAC output
levels. As long as CLR remains low, the LDAC signals are ignored, and the signal outputs
remain switched to the potential on the DSG pins.
Load DAC Input (Level Sensitive). This input signal, in conjunction with the WR and CS
input signals, determines how the analog outputs are updated. If LDAC is maintained
high while new data is being loaded into the device’s input registers, no change occurs
on the analog outputs. Subsequently, when LDAC is brought low, the contents of all four
input registers are transferred into their respective DAC latches, updating the analog
outputs simultaneously. Alternatively, if LDAC is brought low while new data is being
entered, the addressed DAC latch and corresponding analog output are updated
immediately on the rising edge of WR.
Byte Shift Input. When low, it shifts the data on DB0 to DB7 into the DB8 to DB13 half of
the input register.
Level-Triggered Chip Select Input (Active Low). The device is selected when this input is
low.
Level-Triggered Write Input (Active Low). When active, it is used in conjunction with CS
to write data over the input databus.
Logic Power Supply: 5 V ± 5%.
Digital Ground.
Rev. D | Page 9 of 28
AD7834/AD7835
Pin No.
MQFP
16 to 29
Pin No. PLCC
22 to 35
Pin Mnemonic
DB0 to DB13
32
38
DSGB
36, 35
42, 41
VREF(+)B, VREF(−)B
Description
Parallel Data Inputs. The AD7835 can accept a straight 14-bit parallel word on DB0 to
DB13, where DB13 is the MSB and the BYSHF input is hardwired to a logic high.
Alternatively for byte loading, the bottom eight data inputs, DB0 to DB7, are used for
data loading, and the top six data inputs, DB8 to DB13, should be hardwired to a logic
low. The BYSHF control input selects whether 8 LSBs or 6 MSBs of data are being loaded
into the device.
Device Sense Ground B Input. Used in conjunction with the CLR input for power-on
protection of the DACs. When CLR is low, DAC outputs VOUT3 and VOUT4 are forced to the
potential on the DSGB pin.
Reference Inputs for DACs 3 and 4. These reference voltages are referred to AGND.
38
39
40
42, 43
44
1
2
4, 5
AGND
VDD
VSS
VREF(+)A, VREF(−)A
Analog Ground.
Positive Analog Power Supply: 15 V ± 5% or 12 V ± 5%.
Negative Analog Power Supply: −15 V ± 5% or −12 V ± 5%.
Reference Inputs for DAC 1 and DAC 2. These reference voltages are referred to AGND.
Rev. D | Page 10 of 28
AD7834/AD7835
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.50
0.8
0.45
0.6
0.40
0.4
0.35
0.2
0.30
0.15
0.10
0
2
4
6
8
10
CODE/1000
12
14
DAC 2
0.20
–0.6
–1.0
DAC 4
0.25
–0.4
–0.8
DAC 3
TEMP = 25°C
ALL DACs FROM 1 DEVICE
0.05
0
16
01006-012
INL (LSB)
0
–0.2
01006-009
INL (LSB)
DAC 1
0
2.5
5.0
8.0
VREF(+) (V)
Figure 9. Typical INL Plot
Figure 12. Typical INL vs. VREF(+), VREF(+) – VREF(−) = 5 V
0.5
0.8
0.4
ALL DACs FROM ONE DEVICE
0.7
0.3
0.6
DAC 1
DAC 3
0.5
0.1
INL (LSB)
DNL (LSB)
0.2
0
–0.1
DAC 4
0.4
DAC 2
0.3
–0.2
0.2
–0.5
0.1
01006-010
–0.4
0
2
4
6
8
10
CODE/1000
12
14
01006-013
–0.3
0
–40
16
Figure 13. Typical INL vs. Temperature
Figure 10. Typical DNL Plot
1.0
0.9
0.8
0.8
0.6
0.7
0.4
DAC (LSB)
0.6
0.5
0.4
0.3
0.2
0
–0.2
–0.4
0.2
0.1
0
0
1
2
3
4
5
6
7
01006-014
–0.6
01006-011
INL (LSB)
85
25
TEMPERATURE (°C)
–0.8
–1.0
8
VREF(+) (V)
Figure 11. Typical INL vs. VREF(+), VREF(−) = −6 V
0
2
4
6
8
10
CODE/1000
12
Figure 14. Typical DAC-to-DAC Matching
Rev. D | Page 11 of 28
14
16
AD7834/AD7835
0.7
0.6
–2.985
8
VERT = 100mV/DIV
HORIZ = 1μs/DIV
VERT = 10mV/DIV
HORIZ = 1µs/DIV
6
–3.005
4
–3.025
0.3
VOLTS
VOLTS
0.4
0.2
2
VREF (+) = +7V
VREF (–) = –3V
–3.065
0
0.1
–3.045
VOLTS
0.5
0
01006-015
VERT = 2V/DIV
HORIZ = 1µs/DIV
–0.2
Figure 15. Typical Digital/Analog Glitch Impulse
6
7.225
4
7.200
2
VREF(+) = +7V
VREF(–) = –3V
7.175
VOLTS
VERT = 2V/DIV
HORIZ = 1.2μs/DIV
7.150
0
7.125
–2
VERT = 25mV/DIV
HORIZ = 2.5μs/DIV
7.100
–4
01006-016
VOLTS
Figure 17. Settling Time(−)
7.250
8
–3.105
–4
Figure 16. Settling Time(+)
Rev. D | Page 12 of 28
01006-017
–3.085
–2
–0.1
AD7834/AD7835
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error. It is normally
expressed in LSBs or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
DC Crosstalk
Although the common input reference (IR) voltage signals are
internally buffered, small IR drops in individual DAC reference
inputs across the die mean that an update to one channel
produces a dc output change in one or more channel outputs.
The four DAC outputs are buffered by op amps sharing
common VDD and VSS power supplies. If the dc load current
changes in one channel due to an update, a further dc change
occurs in one or more of the channel outputs. This effect is
most obvious at high load currents and is reduced as the load
currents are reduced. With high impedance loads, the effect is
virtually unmeasurable.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV-secs. It is measured with the reference inputs
connected to 0 V and the digital inputs toggled between all
1s and all 0s.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is defined as the glitch impulse that
appears at the output of one converter due to both the digital
change and the subsequent analog output (O/P) change at
another converter. It is specified in nV-secs.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the digital crosstalk and is specified in nV-secs.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on its digital inputs can be capacitively coupled both across and
through the device to show up as noise on the VOUT pins. This
noise is digital feedthrough.
DC Output Impedance
DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.
Full-Scale Error
Full-scale error is the error in DAC output voltage when all 1s
are loaded into the DAC latch. Ideally, the output voltage, with
all 1s loaded into the DAC latch, should be VREF(+) – 1 LSB.
Full-scale error does not include zero-scale error.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when
all 0s are loaded into the DAC latch. Ideally, the output voltage,
with all 0s in the DAC latch, is equal to VREF(−). Zero-scale
error is due mainly to offsets in the output amplifier.
Gain Error
Gain error is defined as (full-scale error) − (zero-scale error).
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from the reference input of one DAC that appears at the
output of the other DAC. It is expressed in decibels (dB). The
AD7834 has no specification for channel-to-channel isolation
because it has one reference for all DACs. Channel-to-channel
isolation is specified for the AD7835.
Rev. D | Page 13 of 28
AD7834/AD7835
THEORY OF OPERATION
DAC ARCHITECTURE
Table 9. D23 Control
Each channel consists of a segmented 14-bit R-2R voltage-mode
DAC. The full-scale output voltage range is equal to the entire
reference span of VREF(+) – VREF(−). The DAC coding is straight
binary; all 0s produce an output of VREF(−); all 1s produce an
output of VREF(+) − 1 LSB.
D23
0
1
Control Function
Ignore the following 23 bits of information.
Use the following 23 bits of address and data as normal.
D22 and D21
D22 and D21 are decoded to select one of the four DAC channels within a device, as shown in Table 10.
The analog output voltage of each DAC channel reflects the
contents of its own DAC latch. Data is transferred from the
external bus to the input register of each DAC latch on a per
channel basis. The AD7835 has a feature whereby the A2 pin
data can be transferred from the input databus to all four input
registers simultaneously.
Table 10. D22, D21 Control
Bringing the CLR line low switches all the signal outputs, VOUT1
to VOUT4, to the voltage level on the DSG pin. The signal
outputs are held at this level after the removal of the CLR signal
and do not switch back to the DAC outputs until the LDAC
signal is exercised.
D20 to D16
DATA LOADING—AD7834 SERIAL INPUT DEVICE
A write operation transfers 24 bits of data to the AD7834. The
first 8 bits are control data and the remaining 16 bits are DAC
data (see Figure 18). The control data identifies the DAC channel to be updated with new data and which of 32 possible
packages the DAC resides in. In any communication with the
device, the first 8 bits must always be control data.
The DAC output voltages, VOUT1 to VOUT4, can be updated to
reflect new data in the DAC input registers in one of two ways.
The first method normally keeps LDAC high and only pulses
LDAC low momentarily to update all DAC latches simultaneously with the contents of their respective input registers. The
second method ties LDAC low and channel updating occurs on
a per channel basis after new data has been clocked into the
AD7834. With LDAC low, the rising edge of FSYNC transfers
the new data directly into the DAC latch, updating the analog
output voltage.
Data being shifted into the AD7834 enters a 24-bit long shift
register. If more than 24 bits are clocked in before FSYNC goes
high, the last 24 bits transmitted are used as the control data
and DAC data.
Individual bit functions are shown in Figure 18.
D23
D22
0
0
1
1
D21
0
1
0
1
Control Function
Select Channel 1
Select Channel 2
Select Channel 3
Select Channel 4
D20 and D16 determine the package address. The five address
bits allow up to 32 separate packages to be individually decoded.
Successful decoding is accomplished when these five bits match
up with the five hardwired pins on the physical package.
D15 to D0
D15 and D0 provide DAC data to be loaded into the identified
DAC input register. This data must have two leading 0s followed
by 14 bits of data, MSB first. The MSB is in location D13 of the
24-bit data stream.
DATA LOADING—AD7835 PARALLEL LOADING
DEVICE
Data is loaded into the AD7835 in either straight 14-bit wide
words or in two 8-bit bytes.
In systems that transfer 14-bit wide data, the BYSHF input
should be hardwired to VCC. This sets up the AD7835 as a
straight 14-bit parallel-loading DAC.
In 8-bit bus systems where it is required to transfer data in two
bytes, it is necessary to have the BYSHF input under logic control.
In such a system, the top six pins of the device databus, DB8 to
DB13, must be hardwired to DGND. New low byte data is
loaded into the lower eight places of the selected input register
by carrying out a write operation while holding BYSHF high.
A second write operation is subsequently executed with BYSHF
low and the 6 MSBs on the DB0 to DB5 inputs (DB5 = MSB).
D23 determines whether the following 23 bits of address and
data should be used or ignored. This is effectively a software
chip select bit. D23 is the first bit to be transmitted in the 24-bit
long word.
Rev. D | Page 14 of 28
AD7834/AD7835
NOTE: D23 IS THE FIRST BIT TRANSMITTED IN THE SERIAL WORD.
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LSB, DB0
SECOND LSB, DB1
THIRD LSB, DB2
CONTROL BIT TO USE/IGNORE
FOLLOWING 23 BITS OF INFORMATION
DB3
CHANNEL ADDRESS MSB, D1
DB4
CHANNEL ADDRESS LSB, D2
DB5
DB6
PACKAGE ADDRESS MSB, PA4
DB7
PACKAGE ADDRESS, PA2
PACKAGE ADDRESS, PA1
PACKAGE ADDRESS LSB, PA0
01006-018
DB8
DB9
DB10
THIRD MSB, DB11
SECOND MSB, DB12
MSB, DB13
SECOND LEADING ZERO
FIRST LEADING ZERO
PACKAGE ADDRESS, PA3
Figure 18. Bit Assignments for 24-Bit Data Stream of AD7834
To avoid the DAC output going to an intermediate value during
a 2-byte transfer, LDAC should not be tied low permanently but
should be held high until the two bytes are written to the input
register. When the selected input register has been loaded with
the two bytes, LDAC should then be pulsed low to update the
DAC latch and, consequently, perform the digital-to-analog
conversion.
In many applications, it may be acceptable to allow the DAC
output to go to an intermediate value during a 2-byte transfer.
In such applications, LDAC can be tied low, thus using one less
control line.
The actual DAC input register that is being written to is determined by the logic levels present on the device address lines, as
shown in Table 11.
Table 11. AD7835—Address Line Truth Table
A2
0
0
0
0
1
A1
0
0
1
1
X
A0
0
1
0
1
X
DAC Selected
DAC 1
DAC 2
DAC 3
DAC 4
All DACs selected
gives the code table for unipolar operation of the AD7834/
AD7835.
2
6
8
AD586
C1
1nF
5
+15V
+5V
VDD
VCC
VREF(+)
VOUT
(0V TO 5V)
VOUT
AD7834/
AD78351
R1
10kΩ
AGND
4
VREF(–)
DGND
VSS
SIGNAL
GND
SIGNAL
GND
–15V
1ADDITIONAL
PINS OMITTED FOR CLARITY
01006-019
When 14-bit transfers are being used, the DAC output voltages,
VOUT1 to VOUT4, can be updated to reflect new data in the DAC
input registers in one of two ways. The first method normally
keeps LDAC high and only pulses LDAC low momentarily to
update all DAC latches simultaneously with the contents of
their respective input registers. The second method ties LDAC
low, and channel updating occurs on a per channel basis after
new data is loaded to an input register.
Figure 19. Unipolar 5 V Operation
Offset and gain can be adjusted in Figure 19 as follows:
•
•
To adjust offset, disconnect the VREF(−) input from 0 V,
load the DAC with all 0s, and adjust the VREF(−) voltage
until VOUT = 0 V.
To adjust gain, load the AD7834/AD7835 with all 1s and
adjust R1 until VOUT = 5 V(16383/16384) = 4.999695 V.
Many circuits do not require these offset and gain adjustments.
In these circuits, R1 can be omitted. Pin 5 of the AD586 can be
left open circuit, and Pin 2 (VREF(−)) of the AD7834/AD7835 is
tied to 0 V.
Table 12. Code Table for Unipolar Operation 1 , 2
UNIPOLAR CONFIGURATION
Figure 19 shows the AD7834/AD7835 in the unipolar binary
circuit configuration. The VREF(+) input of the DAC is driven by
the AD586, a 5 V reference. VREF(−) is tied to ground. Table 12
Binary Number in DAC Latch
MSB
LSB
11
1111
1111
1111
Analog Output (VOUT)
VREF (16383/16384) V
10
01
00
00
VREF (8192/16384) V
VREF (8191/16384) V
VREF (1/16384) V
0V
1
2
0000
1111
0000
0000
0000
1111
0000
0000
0000
1111
0001
0000
VREF = VREF(+); VREF(−) = 0 V for unipolar operation.
For VREF(+) = 5 V, 1 LSB = 5 V/214 = 5 V/16384 = 305 μV.
Rev. D | Page 15 of 28
AD7834/AD7835
BIPOLAR CONFIGURATION
+15V
+5V
VDD
VCC
In Figure 20, full-scale and bipolar zero adjustments are
provided by varying the gain and balance on the AD588. R2
varies the gain on the AD588 while R3 adjusts the offset of both
the +5 V and –5 V outputs together with respect to ground.
R1
39kΩ
4
6
7
C1
1μF
2
3
9
AD588
R2
100kΩ
1
5
14
10
11
15
16
VREF(+)
VOUT
AD7834/
AD78351
VOUT
(–5V TO +5V)
AGND
VREF(–)
DGND
VSS
1ADDITIONAL
8
13
SIGNAL
GND
PINS OMITTED FOR CLARITY
01006-020
R3
100kΩ
12
–15V
For bipolar-zero adjustment, the DAC is loaded with
1000 . . . 0000 and R3 is adjusted until VOUT = 0 V. Full scale
is adjusted by loading the DAC with all 1s and adjusting R2
until VOUT = 5(8191/8192) V = 4.99939 V.
When bipolar zero and full-scale adjustment are not needed, R2
and R3 are omitted. Pin 12 on the AD588 should be connected to
Pin 11, and Pin 5 should be left floating.
Figure 20. Bipolar ±5 V Operation
Figure 20 shows the AD7834/AD7835 setup for ±5 V operation.
The AD588 provides precision ±5 V tracking outputs that are
fed to the VREF(+) and VREF(−) inputs of the AD7834/AD7835.
The code table for bipolar operation of the AD7834/AD7835 is
shown in Table 13.
Table 13. Code Table for Bipolar Operation 1, 2
Binary Number in DAC Latch
MSB
LSB
11
1111 1111 1111
10
0000 0000 0001
10
0000 0000 0000
01
1111 1111 1111
00
0000 0000 0001
00
0000 0000 0000
1
2
Analog Output (VOUT)
VREF(−) + VREF (16383/16384) V
VREF(−) + VREF (8193/16384) V
VREF(−) + VREF (8192/16384) V
VREF(−) + VREF (8191/16384) V
VREF(−) + VREF (1/16384) V
VREF(−) V
VREF = VREF(+) – VREF(−).
For VREF(+) = +5 V and VREF(−) = –5 V, 1 LSB = 10 V/214 = 10 V/16384 = 610 μV.
Rev. D | Page 16 of 28
AD7834/AD7835
CONTROLLED POWER-ON OF THE OUTPUT STAGE
G1
A block diagram of the output stage of the AD7834/AD7835 is
shown in Figure 21. It is capable of driving a load of 10 kΩ in
parallel with 200 pF. G1 to G6 are transmission gates used to
control the power-on voltage present at VOUT. G1 and G2 are also
used in conjunction with the CLR input to set VOUT to the userdefined voltage present at the DSG pin.
G6
DAC
VOUT
G3
G4
G2
R
01006-023
G5
G1
G6
DAC
DSG
VOUT
Figure 23. Output Stage with VDD > 10 V and CLR Low
G3
VOUT is disconnected from the DSG pin by the opening of G5
but tracks the voltage present at DSG via the unity gain buffer.
G4
G2
R
POWER-ON WITH LDAC LOW, CLR HIGH
01006-021
DSG
Figure 21. Block Diagram of AD7834/AD7835 Output Stage
POWER-ON WITH CLR LOW, LDAC HIGH
The output stage of the AD7834/AD7835 is designed to allow
output stability during power-on. If CLR is kept low during
power-on, and power is applied to the part, G1, G4, and G6 are
open while G2, G3, and G5 are closed (see Figure 22).
G1
G6
DAC
VOUT
In many applications of the AD7834/AD7835, LDAC is kept
continuously low, updating the DAC after each valid data
transfer. If LDAC is low when power is applied, G1 is closed and
G2 is open, connecting the output of the DAC to the input of the
output amplifier. G3 and G5 are closed and G4 and G6 are open,
connecting the amplifier as a unity gain buffer, as before. VOUT is
connected to DSG via G5 and R (a thin-film resistance between
DSG and VOUT) until VDD and VSS reach approximately ±10 V.
Then, the internal power-on circuitry opens G3 and G5 and
closes G4 and G6. This is the situation shown in Figure 24. At
this point, VOUT is at the same voltage as the DAC output.
G3
G1
G4
VOUT
R
DSG
G3
01006-022
G5
G6
DAC
G2
G4
G2
G5
Figure 22. Output Stage with VDD < 10 V
VOUT is kept within a few hundred millivolts of DSG via G5
and R. R is a thin-film resistor between DSG and VOUT. The
output amplifier is connected as a unity gain buffer via G3, and
the DSG voltage is applied to the buffer input via G2. The
amplifier output is thus at the same voltage as the DSG pin. The
output stage remains configured as in Figure 22 until the
voltage at VDD and VSS reaches approximately ±10 V. At this
point, the output amplifier has enough headroom to handle
signals at its input and has also had time to settle. The internal
power-on circuitry opens G3 and G5 and closes G4 and G6 (see
Figure 23). As a result, the output amplifier is connected in
unity gain mode via G4 and G6. The DSG voltage is still applied
to the noninverting input via G2. This voltage appears at VOUT.
R
DSG
01006-024
G5
Figure 24. Output Stage with LDAC Low
LOADING THE DAC AND USING THE CLR INPUT
When LDAC goes low, it closes G1 and opens G2 as in Figure 24.
The voltage at VOUT now follows the voltage present at the output of the DAC. The output stage remains connected in this
manner until a CLR signal is applied. Then, the situation reverts
(see Figure 23). Once again, VOUT remains at the same voltage as
DSG until LDAC goes low. This reconnects the DAC output to
the unity gain buffer.
Rev. D | Page 17 of 28
AD7834/AD7835
DSG VOLTAGE RANGE
During power-on, the VOUT pins of the AD7834/AD7835 are
connected to the relevant DSG pins via G6 and the thin-film
resistor, R. The DSG potential must obey the maximum ratings
at all times. Thus, the voltage at DSG must always be within the
range VSS – 0.3 V to VDD + 0.3 V. However, to keep the voltages
at the VOUT pins of the AD7834/AD7835 within ±2 V of the
relevant DSG potential during power-on, the voltage applied to
DSG should also be kept within the range AGND – 2 V to
AGND + 2 V.
Once the AD7834/AD7835 have powered on and the on-chip
amplifiers have settled, the situation is as shown in Figure 23.
Any voltage subsequently applied to the DSG pin is buffered by
the same amplifier that buffers the DAC output voltage in
normal operation. Thus, for specified operations, the maximum
voltage applied to the DSG pin increases to the maximum
allowable VREF(+) voltage, and the minimum voltage applied to
DSG is the minimum VREF(−) voltage. After the AD7834 or
AD7835 has fully powered on, the outputs can track any DSG
voltage within this minimum/maximum range.
Rev. D | Page 18 of 28
AD7834/AD7835
POWER-ON OF THE AD7834/AD7835
In some systems, it is necessary to introduce one or more
Schottky diodes between pins to prevent the above situations
arising at power-on. These diodes are shown in Figure 25.
However, in most systems, with careful consideration given to
power supply sequencing, the above rules are adhered to, and
protection diodes are not necessary.
Rev. D | Page 19 of 28
VREF(+)
AD78341
SD103C
1N5711
1N5712
VREF(–)
1ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. Power-On Protection
01006-025
Power is normally applied to the AD7834/AD7835 in the
following sequence: first VDD and VSS, then VCC, and then
VREF(+) and VREF(−). The VREF pins are not allowed to float when
power is applied to the part. VREF(+) is not allowed to go below
VREF(−) − 0.3 V. VREF(−) is not allowed to go below VSS − 0.3 V.
VDD is not allowed to go below VCC − 0.3 V.
AD7834/AD7835
MICROPROCESSOR INTERFACING
A serial interface between the AD7834 and the 80C51 microcontroller is shown in Figure 26. TXD of the 80C51 drives SCLK
of the AD7834, while RXD drives the serial data line of the part.
The 80C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. The AD7834 expects the MSB of the
24-bit write first. Therefore, the user has to ensure that data in
the SBUF register is arranged correctly so the data is received
MSB first by the AD7834/AD7835. When data is to be transmitted to the part, P3.3 is taken low. Data on RXD is valid on
the falling edge of TXD. The 80C51 transmits its data in 8-bit
bytes with only eight falling clock edges occurring in the transmit cycle. To load data to the AD7834, P3.3 is left low after the
first 8 bits are transferred. A second byte is then transferred,
with P3.3 still kept low. After the third byte has been transferred, the P3.3 line is taken high.
AD78341
CLR
P3.4
LDAC
P3.3
FSYNC
TXD
SCLK
RXD
DIN
1ADDITIONAL PINS OMITTED FOR CLARITY
AD78341
68HC11 1
PC5
CLR
PC6
LDAC
PC7
FSYNC
SCK
SCLK
MOSI
1ADDITIONAL PINS
DIN
OMITTED FOR CLARITY
Figure 27. AD7834 to 68HC11 Interface
In Figure 27, LDAC and CLR are controlled by the PC6 and PC5
port outputs, respectively. As with the 80C51, each DAC of the
AD7834 can be updated after each 3-byte transfer, or all DACs
can be simultaneously updated after 12 bytes are transferred.
AD7834 TO ADSP-2101 INTERFACE
Figure 26. AD7834 to 80C51 Interface
LDAC and CLR on the AD7834 are also controlled by 80C51
port outputs. The user can bring LDAC low after every three
bytes have been transmitted to update the DAC, which has been
programmed. Alternatively, it is possible to wait until all the
input registers have been loaded (12-byte transmits) and then
update the DAC outputs.
An interface between the AD7834 and the ADSP-2101 is shown
in Figure 28. In the interface shown, SPORT0 is used to transfer
data to the part. SPORT1 is configured for alternate functions.
FO, the flag output on SPORT0, is connected to LDAC and is
used to load the DAC latches. In this way, data is transferred
from the ADSP-2101 to all the input registers in the DAC, and
the DAC latches are updated simultaneously. In the application
shown, the CLR pin on the AD7834 is controlled by circuitry
that monitors the power in the system.
POWER
MONITOR
CLR
FO
AD7834 TO 68HC11 INTERFACE
Figure 27 shows a serial interface between the AD7834 and the
68HC11 microcontroller. SCK of the 68HC11 drives SCLK of
the AD7834, while the MOSI output drives the serial data line,
DIN, of the AD7834. The FSYNC signal is derived from Port
Line PC7.
For correct operation of this interface, the 68HC11 should be
configured so that its CPOL bit is 0 and its CPHA bit is 1. When
data is to be transferred to the part, PC7 is taken low. When the
68HC11 is configured like this, data on MOSI is valid on the
falling edge of SCK. The 68HC11 transmits its serial data in 8-bit
bytes, MSB first. The AD7834 also expects the MSB of the 24-bit
write first. Eight falling clock edges occur in the transmit cycle.
AD78341
ADSP-21011
LDAC
TFS
FSYNC
SCK
SCLK
DT
1ADDITIONAL PINS
DIN
OMITTED FOR CLARITY
01006-028
P3.5
01006-026
80C51 1
To load data to the AD7834, PC7 is left low after the first eight
bits are transferred. A second byte of data is then transmitted
serially to the AD7834. Then, a third byte is transmitted and,
when this transfer is complete, the PC7 line is taken high.
01006-027
AD7834 TO 80C51 INTERFACE
Figure 28. AD7834 to ADSP-2101 Interface
The AD7834 requires 24 bits of serial data framed by a single
FSYNC pulse. It is necessary that this FSYNC pulse stay low until
all the data is transferred. This can be provided by the ADSP-2101
in one of two ways. Both require setting the serial word length of
the SPORT to 12 bits, with the following conditions: internal
SCLK, alternate framing mode, and active low framing signal.
Rev. D | Page 20 of 28
AD7834/AD7835
CLOCK/
TIMER
TMS32020/
TMS320C251
DSP56000/
DSP560011
SC0
CLR
SC1
LDAC
SC2
FSYNC
SCK
SCLK
STD
DIN
PINS OMITTED FOR CLARITY
SCLK
CLKX
DIN
DX
PINS OMITTED FOR CLARITY
Figure 30. AD7834 to TMS32020/TMS320C25 Interface
INTERFACING THE AD7835—16-BIT INTERFACE
The AD7835 can be interfaced to a variety of microcontrollers
or DSP processors, both 8-bit and 16-bit. Figure 31 shows the
AD7835 interfaced to a generic 16-bit microcontroller/DSP
processor. BYSHF is tied to VCC in this interface. The lower
address lines from the processor are connected to A0, A1, and
A2 on the AD7835 as shown. The upper address lines are
decoded to provide a chip select signal for the AD7835. They
are also decoded, in conjunction with the lower address lines if
need be, to provide an LDAC signal. Alternatively, LDAC can be
driven by an external timing circuit or just tied low. The data
lines of the processor are connected to the data lines of the
AD7835. Selection options available for the DACs are provided
in Table 11.
MICROCONTROLLER/
DSP
PROCESSOR1
01006-029
1ADDITIONAL
AD78341
FSYNC
FSX
1ADDITIONAL
Figure 29 shows a serial interface between the AD7834 and the
DSP56000/DSP56001. The serial port is configured for a word
length of 24 bits, gated clock, and FSL0 and FSL1 control bits
each set to 0. Normal mode synchronous operation is selected,
which allows the use of SC0 and SC1 as outputs controlling
CLR and LDAC, respectively. The framing signal on SC2 has to
be inverted before being applied to FSYNC. SCK is internally
generated on the DSP56000/DSP56001 and is applied to SCLK
on the AD7834. Data from the DSP56000/DSP56001 is valid on
the falling edge of SCK.
LDAC
CLR
XF
AD7834 TO DSP56000/DSP56001 INTERFACE
AD78341
01006-030
First, data can be transferred using the autobuffering feature of
the ADSP-2101, sending two 12-bit words directly after each
other. This ensures a continuous transmit frame synchronization (TFS ) pulse. Second, the first data word is loaded to the
serial port, the subsequent generated interrupt is trapped, and
then the second data word is sent immediately after the first.
Again, this produces a continuous TFS pulse that frames the
24 data bits.
Figure 29. AD7834 to DSP56000/DSP56001 Interface
AD78351
VCC
BYSHF
D13
D13
D0
D0
DATABUS
A serial interface between the AD7834 and the TMS32020/
TMS320C25 DSP processor is shown in Figure 30. The
CLKX and FSX signals for the TMS32020/TMS32025 are
generated using an external clock/timer circuit. The CLKX and
FSX pins are configured as inputs. The TMS32020/ TMS320C25
are set up for an 8-bit serial data length. Data can then be written
to the AD7834 by writing three bytes to the serial port of the
TMS32020/TMS320C25. In the configuration shown in Figure
30, the CLR input on the AD7834 is controlled by the XF output
on the TMS32020/TMS320C25. The clock/timer circuit controls
the LDAC input on the AD7834. Alternatively, LDAC can also be
tied to ground to allow automatic update of the DAC latches after
each transfer.
UPPER BITS OF
ADDRESS BUS
ADDRESS
DECODE
A2
A1
A0
R/W
1ADDITIONAL
Rev. D | Page 21 of 28
CS
LDAC
A2
A1
A0
WR
PINS OMITTED FOR CLARITY
Figure 31. AD7835 16-Bit Interface
01006-031
AD7834 TO TMS32020/TMS320C25 INTERFACE
AD7834/AD7835
INTERFACING THE AD7835—8-BIT INTERFACE
Figure 32 shows an 8-bit interface between the AD7835 and
a generic 8-bit microcontroller/DSP processor. Pin D13 to
Pin D8 of the AD7835 are tied to DGND. Pin D7 to Pin D0 of the
processor are connected to Pin D7 to Pin D0 of the AD7835.
BYSHF is driven by the A0 line of the processor. This maps the
DAC upper bits and lower bits into adjacent bytes in the processor address space. Table 14 shows the truth table for addressing
the DACs in the AD7835. For example, if the base address for the
DACs in the processor address space is decoded by the upper
address bits to location HC000, then the upper and lower bits of
the first DAC are at locations HC000 and HC001, respectively.
D13
MICROCONTROLLER/
DSP
PROCESSOR1
D8
AD78351
DGND
D7
D7
D0
D0
DATABUS
ADDRESS
DECODE
LDAC
A3
A2
A2
A1
A1
A0
BYSHF
WR
A0
R/W
1ADDITIONAL
CS
PINS OMITTED FOR CLARITY
Table 14. DAC Channel Decoding, 8-Bit Interface
A3
x
1
0
0
0
0
0
0
0
0
Processor Address Lines
A2
A1
A0
X
X
0
X
X
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
01006-032
UPPER BITS OF
ADDRESS BUS
When writing to the DACs, the lower eight bits must be written
first, followed by the upper six bits. The upper six bits should be
output on data lines D0 to D5. Once again, the upper address
lines of the processor are decoded to provide a CS signal. They
are also decoded in conjunction with lines A3 to A0 to provide
an LDAC signal. Alternatively, LDAC can be driven by an external timing circuit or, if it is acceptable to allow the DAC output
to go to an intermediate value between 8-bit writes, LDAC can
be tied low.
Figure 32. AD7835 8-Bit Interface
Rev. D | Page 22 of 28
DAC Selected
Upper 6 bits of all DACs
Lower 8 bits of all DACs
Upper 6 bits, DAC 1
Lower 8 bits, DAC 1
Upper 6 bits, DAC 2
Lower 8 bits, DAC 2
Upper 6 bits, DAC 3
Lower 8 bits, DAC 3
Upper 6 bits, DAC 4
Lower 8-bits, DAC 4
AD7834/AD7835
APPLICATIONS INFORMATION
Figure 33 shows how the package address pins of the AD7834
are used to address multiple AD7834s. This figure shows only
10 devices, but up to 32 AD7834s can each be assigned a unique
address by hardwiring each of the package address pins to VCC
or DGND. Normal operation of the device occurs when PAEN
is low. When serial data is being written to the AD7834s, only
the device with the same package address as the package address
contained in the serial data accepts data into the input registers.
Conversely, if PAEN is high, the package address is ignored, and
the data is loaded into the same channel on each package.
Figure 34 shows a 5-channel isolated interface to the AD7834.
Multiple devices are connected to the outputs of the opto-coupler
and controlled as for serial interfacing. To reduce the number of
opto-isolators, the PAEN line doesn’t need to be controlled if it
is not used. If the PAEN line is not controlled by the microcontroller, it should be tied low at each device. If simultaneous updating of the DACs is not required, the LDAC pin on each part can
be tied permanently low and another opto-isolator is not needed.
VCC
MICROCONTROLLER
The primary limitation with multiple packages is the output
update rate. For example, if an output update rate of 10 kHz is
required, 100 μs are available to load all DACs. Assuming a
serial clock frequency of 10 MHz, it takes 2.5 μs to load data to
one DAC. Thus, 40 DACs or 10 packages can be updated in this
time. As the update rate requirement decreases, the number of
possible packages increases.
MICROCONTROLLER
CONTROL OUT
SYNC OUT
SERIAL CLOCK OUT
SERIAL DATA OUT
PAEN
LDAC
FSYNC
SCLK
DIN
DIN
VCC
PA0
PA1
PA2
PA3
PA4
DIN
PA0
PA1
PA2
PA3
PA4
1ADDITIONAL PINS OMITTED FOR CLARITY
VCC
01006-033
DEVICE 9
TO FSYNCs
TO SCLKs
SERIAL CLOCK OUT
TO DINs
SERIAL DATA OUT
OPTO-COUPLER
The AD7834/AD7835 are particularly suited for use in an
automated test environment. Figure 35 shows the AD7835
providing the necessary voltages for the pin driver and the
window comparator in a typical ATE pin electronics configuration. Two AD588s are used to provide reference voltages for
the AD7835. In the configuration shown, the AD588s are
configured so that the voltage at Pin 1 is 5 V greater than the
voltage at Pin 9 and the voltage at Pin 15 is 5 V less than the
voltage at Pin 9.
AD78341
PAEN
LDAC
FSYNC
SCLK
TO LDACs
AUTOMATED TEST EQUIPMENT
PA0
PA1
PA2
PA3
PA4
DEVICE 1
CONTROL OUT
Figure 34. Opto-Isolated Interface
AD78341
PAEN
LDAC
FSYNC
SCLK
TO PAENs
SYNC OUT
AD78341
DEVICE 0
CONTROL OUT
CONTROL OUT
01006-034
SERIAL INTERFACE TO MULTIPLE AD7834S
Figure 33. Serial Interface to Multiple AD7834s
OPTO-ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD7834
makes it ideal for opto-isolated interfaces because the number
of interface lines is kept to a minimum.
One AD588 is used as a reference for DAC 1 and DAC 2. These
DACs are used to provide high and low levels for the pin driver.
The pin driver can have an associated offset. This can be nulled
by applying an offset voltage to Pin 9 of the AD588. First, the
code 1000 . . . 0000 is loaded into the DAC 1 latch, and the pin
driver output is set to the DAC 1 output. The VOFFSET voltage is
adjusted until 0 V appears between the pin driver output and
DUT GND. This causes both VREF(+)A and VREF(−)A to be offset with respect to AGND by an amount equal to VOFFSET.
However, the output of the pin driver varies from −5 V to +5 V
with respect to DUT GND as the DAC input code varies from
000 . . . 000 to 111 . . . 111. The VOFFSET voltage is also applied to
the DSGA pin. When a clear is performed on the AD7835, the
output of the pin driver is 0 V with respect to DUT GND.
Rev. D | Page 23 of 28
AD7834/AD7835
VOFFSET
+15V –15V
2
3
1
+15V
VREF(+)A
15
14
AD588
VOUT2
DSG A
0.1µF
10 11 12
DSG B
16
4
6
8
13
10
11
12
1µF
3
1
AD588
15
14
–15V
AD78351
+15V –15V
2
PIN
DRIVER
VREF(–)A
9
1µF
VOUT1
DUT
GND
VDUT
VOUT3
VREF(+)B
DUT
GND
VOUT4
VREF (–)B
AGND
7
1ADDITIONAL
9
DUT
GND
WINDOW
COMPARATOR
TO TESTER
PINS OMITTED FOR CLARITY
01006-035
4
6
8
13
7
If the AD7834/AD7835 are the only devices requiring an AGND
to DGND connection, then the ground planes should be connected
at the AGND and DGND pins of the AD7834/ AD7835. If the
AD7834/AD7835 are in a system where multiple devices require
an AGND to DGND connection, the connection can still be made
at one point only, a star ground point, which can be established as
close as possible to the AD7834/AD7835.
16
Figure 35. ATE Application
The other AD588 provides a reference voltage for DAC 3 and
DAC 4. These provide the reference voltages for the window
comparator shown in Figure 35. Pin 9 of this AD588 is connected to DUT GND. This causes VREF(+)B and VREF(−)B to be
referenced to DUT GND. As DAC 3 and DAC 4 input codes vary
from 000 . . . 000 to 111 . . . 111, VOUT3 and VOUT4 vary from −5 V
to +5 V with respect to DUT GND. DUT GND is also connected
to DSGB. When the AD7835 is cleared, VOUT3 and VOUT4 are
cleared to 0 V with respect to DUT GND.
Care must be taken to ensure that the maximum and minimum
voltage specifications for the AD7835 reference voltages are
followed as shown in Figure 35.
Digital lines running under the device must be avoided because
they couple noise onto the die. The analog ground plane can run
under the AD7834/AD7835 to avoid noise coupling. The power
supply lines of the AD7834/AD7835 can use as large a trace as
possible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals, such as
clocks, should be shielded with digital ground to avoid radiating
noise to other parts of the board. These signals should never be
run near the analog inputs. Avoid crossover of digital and analog
signals. Traces on opposite sides of the board should run at right
angles to each other. This reduces the effects of feedthrough
through the board. A microstrip method is best but not always
possible with a double-sided board. With this method, the
component side of the board is dedicated to ground plane while
signal traces are placed on the solder side.
The AD7834/AD7835 must have ample supply bypassing located
as close as possible to the package, ideally right up against the
device. Figure 36 shows the recommended capacitor values of
10 μF in parallel with 0.1 μF on each of the supplies. The 10 μF
capacitors are the tantalum bead type. The 0.1 μF capacitor can
have low effective series resistance (ESR) and effective series
inductance (ESI), such as the common ceramic types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
POWER SUPPLY BYPASSING AND GROUNDING
Rev. D | Page 24 of 28
VCC
10μF
DGND
0.1μF
VDD
AD7834/
AD78351
0.1μF
10μF
AGND
VSS
0.1μF
1ADDITIONAL PINS OMITTED FOR CLARITY
Figure 36. Power Supply Decoupling
10μF
01006-036
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit boards on
which the AD7834/AD7835 are mounted should be designed so
the analog and digital sections are separated and confined to
certain areas of the boards. This facilitates the use of ground
planes that can be easily separated. A minimum etch technique
is generally best for ground planes because it gives the best
shielding. Digital and analog ground planes should be joined at
only one place.
AD7834/AD7835
OUTLINE DIMENSIONS
18.10 (0.7126)
17.70 (0.6969)
15
28
7.60 (0.2992)
7.40 (0.2913)
1
14
10.65 (0.4193)
10.00 (0.3937)
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.75 (0.0295)
0.25 (0.0098)
45°
8°
0°
0.33 (0.0130)
0.20 (0.0079)
1.27 (0.0500)
0.40 (0.0157)
060706-A
COMPLIANT TO JEDEC STANDARDS MS-013-AE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 37. 28-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)
1.565 (39.75)
1.380 (35.05)
28
15
0.580 (14.73)
0.485 (12.31)
1
14
0.625 (15.88)
0.600 (15.24)
0.100 (2.54)
BSC
0.250 (6.35)
MAX
0.195 (4.95)
0.125 (3.17)
0.015 (0.38)
GAUGE
PLANE
0.015
(0.38)
MIN
0.200 (5.08)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.014 (0.36)
0.005 (0.13)
MIN
0.700 (17.78)
MAX
0.015 (0.38)
0.008 (0.20)
COMPLIANT TO JEDEC STANDARDS MS-011
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE LEADS.
Figure 38. 28-Lead Plastic Dual In-Line Package [PDIP]
Wide Body
(N-28-2)
Dimensions shown in inches and (millimeters)
Rev. D | Page 25 of 28
071006-A
0.070 (1.78)
0.050 (1.27)
AD7834/AD7835
0.180 (4.57)
0.165 (4.19)
0.048 (1.22)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
6
40
39
7
0.021 (0.53)
0.013 (0.33)
PIN 1
IDENTIFIER
17
0.630 (16.00)
0.590 (14.99)
0.050
(1.27)
BSC
TOP VIEW
(PINS DOWN)
(PINS UP)
0.032 (0.81)
0.026 (0.66)
29
28
18
BOTTOM VIEW
0.656 (16.66)
SQ
0.650 (16.51)
0.045 (1.14)
R
0.025 (0.64)
0.120 (3.05)
0.090 (2.29)
0.695 (17.65)
SQ
0.685 (17.40)
COMPLIANT TO JEDEC STANDARDS MO-047-AC
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 39. 44-Lead Plastic Leaded Chip Carrier [PLCC}
(P-44A)
Dimensions shown in inches and (millimeters)
1.03
0.88
0.73
14.15
13.90 SQ
13.65
2.45
MAX
34
44
1.95 REF
1
33
PIN 1
SEATING
PLANE
10.20
10.00 SQ
9.80
TOP VIEW
(PINS DOWN)
2.20
2.00
1.80
0.23
0.11
23
11
0.25 MIN
0.10
COPLANARITY
7°
0°
VIEW A
VIEW A
22
12
0.80 BSC
LEAD PITCH
0.45
0.30
LEAD WIDTH
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MO-112-AA-1
Figure 40. 44-Lead Metric Quad Flat Package [MQFP]
(S-44-2)
Dimensions show in millimeters
Rev. D | Page 26 of 28
041807-A
0.048 (1.22)
0.042 (1.07)
0.020 (0.51)
MIN
AD7834/AD7835
ORDERING GUIDE
Model
AD7834AR
AD7834AR-REEL
AD7834ARZ 1
AD7834ARZ-REEL1
AD7834BR
AD7834BR-REEL
AD7834BRZ1
AD7834BRZ-REEL1
AD7834AN
AD7834ANZ1
AD7834BN
AD7834BNZ1
AD7835AP
AD7835AP-REEL
AD7835APZ1
AD7835APZ-REEL1
AD7835AS
AD7835AS-REEL
AD7835ASZ1
AD7835ASZ-REEL1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Linearity Error (LSBs)
±2
±2
±2
±2
±1
±1
±1
±1
±2
±2
±1
±1
±2
±2
±2
±2
±2
±2
±2
±2
DNL (LSBs)
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
±0.9
Z = RoHS Compliant Part.
Rev. D | Page 27 of 28
Package Description
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead SOIC_W
28-Lead PDIP
28-Lead PDIP
28-Lead PDIP
28-Lead PDIP
44-Lead PLCC
44-Lead PLCC
44-Lead PLCC
44-Lead PLCC
44-Lead-MQFP
44-Lead-MQFP
44-Lead-MQFP
44-Lead-MQFP
Package Option
RW-28
RW-28
RW-28
RW-28
RW-28
RW-28
RW-28
RW-28
N-28-2
N-28-2
N-28-2
N-28-2
P-44A
P-44A
P-44A
P-44A
S-44-2
S-44-2
S-44-2
S-44-2
AD7834/AD7835
NOTES
©2003–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01006-0-8/07(D)
Rev. D | Page 28 of 28
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