AD8260

High Current Driver Amplifier and Digital VGA/Preamplifier with 3 dB Steps AD8260 FEATURES High current driver Differential input—direct drive from DAC Preset gain: 1.5× −3 dB bandwidth: 195 MHz Large output drive: >±300 mA VGA/preamplifier Low noise Voltage noise: 2.4 nV/√Hz Current noise: 5 pA/√Hz −3 dB bandwidth: 230 MHz Gain range: 30 dB in 3 dB steps −6 dB to +24 dB (for preamplifier gain of 6 dB) Single-ended preamplifier input and differential VGA output Supplies: 3.3 V to 10 V (with VMID enabled) ±3.3 V to ±5 V (with VMID disabled) Power: 93 mW with 3.3 V supplies Power-down for VGA, driver amplifier, and system FUNCTIONAL BLOCK DIAGRAM VOCM INPP INRP INRN INPN TXFB VNEG 32 31 30 29 28 27 26 VNEG 25 1.5kΩ VMDO 1 TXEN 2 1kΩ 1kΩ 1.5kΩ 24 TXOP + GM – ×1 23 TXOP 22 VPOS HIGH CURRENT DRIVER VMDI 3 VMID VNCM 4 BIAS VPSB 5 VGA/PREAMPLIFIER ENBL 6 VGAP 7 GM STAGES VGAN 8 LOGIC ATTENUATOR AD8260 21 VPOS 20 VPSR 19 VMDO 18 PRAI 17 FDBK 9 10 11 12 13 14 15 16 APPLICATIONS Digital AGC systems Tx/Rx signal processing Power line transceivers VNGR VPSR GNS3 GNS2 GNS1 GNS0 PRAO VNGR Figure 1. Functional Block Diagram GENERAL DESCRIPTION The AD8260 includes a high current driver, usable as a transmitter, and a low noise digitally programmable variable gain amplifier (DGA), useable as a receiver. The receiver section consists of a single-ended input preamplifier, and linear-in-dB, differential-output DGA. The receiver has a small signal –3 dB bandwidth of 230 MHz; the driver small signal bandwidth is 195 MHz. The driver delivers ±300 mA, well suited for driving low impedance loads, even when connected to a 3.3 V supply. The AD8260 DGA is ideal for trim applications and has a gain span of 30 dB, in 3 dB steps. Excellent bandwidth uniformity is maintained across the entire frequency range. The low outputreferred noise of the DGA is advantageous in driving high speed ADCs. The differential output facilitates the interface to modern low voltage high speed ADCs. Single-supply and dual-supply operation makes the part versatile and enables gain control of negative-going pulses, such as those generated by photodiodes or photo-multiplier tubes, as well as processing band-pass signals on a single supply. For maximum dynamic range, it is essential that the part be ac-coupled when operating on a single supply. The AD8260 preamplifier (PrA) is configured with external resistors for gains greater than 6 dB and can be inverting or noninverting. The DGA is characterized with a noninverting preamplifier gain of 2×. The attenuator has a range of 30 dB and the output amplifier has a gain of 8× (18.06 dB). The lowest noninverting gain range is −6 dB to +24 dB and shifts up with increased preamplifier gain. The gain is controlled via a parallel port (Pin GNS0 to Pin GNS3) with 10 gain steps of 3 dB per code. The preamplifier and DGA are disabled for any code that is not assigned a gain step. The AD8260 can operate with single or dual supplies from 3.3 V to ±5 V. An internal buffer normally provides a split supply reference for single-supply operation; an external reference can also be used when the VMID buffer is shut down. The operating temperature range is −40°C to +105°C. The AD8260 is available in a 5 mm × 5 mm, 32-lead LFCSP. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. 07192-001 AD8260 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  Functional Block Diagram .............................................................. 1  General Description ......................................................................... 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Absolute Maximum Ratings............................................................ 6  ESD Caution .................................................................................. 6  Pin Configuration and Function Descriptions ............................. 7  Typical Performance Characteristics ............................................. 8  Test Circuits ..................................................................................... 16  Theory of Operation ...................................................................... 20  Overview...................................................................................... 20  High Current Driver Amplifier ................................................ 21  Precautions to Be Observed During Half-Duplex Operation..................................................................................... 22  VMID Buffer ............................................................................... 22  Preamplifier................................................................................. 22  Preamplifier Noise...................................................................... 22  DGA ............................................................................................. 23  Gain Control ............................................................................... 23  Output Stage................................................................................ 23  Attenuator.................................................................................... 23  Single-Supply Operation and AC Coupling ........................... 24  Power-Up/Power-Down Sequence .......................................... 24  Logic Interfaces........................................................................... 24  Applications Information .............................................................. 25  Evaluation Board ............................................................................ 26  Connecting the Evaluation Board ............................................ 27  Outline Dimensions ....................................................................... 32  Ordering Guide .......................................................................... 32  REVISION HISTORY 5/08—Revision 0: Initial Version Rev. 0 | Page 2 of 32 AD8260 SPECIFICATIONS VS (supply voltage) = 3.3 V, TA = 25°C, preamplifier gain = 2× (RFB1 = RFB2 = 100 Ω), VVMDO = VS/2, f = 10 MHz, CL = 5 pF, RLOAD = 500 Ω, DGA differential output. All dBm values are referenced to 50 Ω, gain code 1011, unless otherwise specified. Table 1. Parameter DRIVER AMPLIFIER—GENERAL PARAMETERS –3 dB Small Signal Bandwidth Conditions VOUT = 10 mV p-p, RLOAD = 500 Ω VOUT = 10 mV p-p, RLOAD = 50 Ω VOUT = 10 mV p-p, RLOAD = 10 Ω VOUT = 1 V p-p VOUT = 2 V p-p VOUT = 2 V p-p, RLOAD = 50 Ω VOUT = 1 V p-p VOUT = 2 V p-p VOUT = 2 V p-p, RLOAD = 50 Ω Nominal gain with internal gain setting resistors f = 10 MHz RS = 100 Ω (differential, 2 × 50 Ω that convert differential DAC output currents to differential voltage) Gain = 3.52 dB (1.5×), includes internal gain setting resistors DC to 10 MHz, VS = ±3.3 V RLOAD = 1 Ω, VIN = ±0.5 V RLOAD ≥ 500 Ω VS = +5 V VS = ±5 V Differential input signal Gain = 3.52 dB (1.5×), max and min limits are 3σ VOUT = 1 V p-p f = 1 MHz f = 10 MHz VOUT = 2 V p-p f = 1 MHz f = 10 MHz Min Typ 195 120 85 195 190 180 730 725 620 3.52 9.5 17.6 14.3 ≤1.7 ±310 VMDO ± 1.5 VMDO ± 2.3 ±4.7 −20 2 ±5 +20 Max Unit MHz MHz MHz MHz MHz MHz V/μs V/μs V/μs dB nV/√Hz dB nV/√Hz Ω mA V V V V p-p mV –3 dB Large Signal Bandwidth Slew Rate Gain Input Voltage Noise Noise Figure Output-Referred Noise Output Impedance Output Current Output Signal Range 3.0 Input Signal Range Output Offset Voltage DRIVER AMPLIFIER—DYNAMIC PERFORMANCE Harmonic Distortion HD2 HD3 HD2 HD3 Harmonic Distortion HD2 HD3 HD2 HD3 Input 1 dB Compression Point Multitone Power Ratio (MTPR, In-Band) −84 −85 −83 −70 −78 −76 −70 −58 13 −49 −43 dBc dBc dBc dBc dBc dBc dBc dBc dBm dBc dBc Two-Tone Intermodulation Distortion (IMD3) Output Third-Order Intercept Two-Tone Intermodulation Distortion (IMD3), RLOAD = 50 Ω RLOAD = 50 Ω, VOUT = 1.4 V p-p max, 10 tones, 2 MHz to 22 MHz with missing tone at 12 MHz (spacing 2 MHz) RLOAD = 50 Ω, VOUT = 1.4 V p-p max, 16 tones, 2 MHz to 38 MHz with missing tones at 10 MHz, 20 MHz, 30 MHz, and 40 MHz (spacing 2 MHz) VOUT = 1 V p-p, f1 = 10 MHz, f2 = 11 MHz VOUT = 2 V p-p, f1 = 10 MHz, f2 = 11 MHz VOUT = 1 V p-p, f1 = 45 MHz, f2 = 46 MHz VOUT = 2 V p-p, f1 = 45 MHz, f2 = 46 MHz VOUT = 1 V p-p, f = 10 MHz VOUT = 2 V p-p, f = 10 MHz VOUT = 1 V p-p, f = 45 MHz VOUT = 2 V p-p, f = 45 MHz VOUT = 1 V p-p, f1 = 10 MHz, f2 = 11 MHz VOUT = 2 V p-p, f1 = 10 MHz, f2 = 11 MHz VOUT = 1 V p-p, f1 = 45 MHz, f2 = 46 MHz VOUT = 2 V p-p, f1 = 45 MHz, f2 = 46 MHz Rev. 0 | Page 3 of 32 −90 −71 −60 −48 43 40 28 28 −69 −72 −51 −48 dBc dBc dBc dBc dBm dBm dBm dBm dBc dBc dBc dBc AD8260 Parameter Output Third-Order Intercept, RLOAD = 50 Ω Conditions VOUT = 1 V p-p, f = 10 MHz VOUT = 2 V p-p, f = 10 MHz VOUT = 1 V p-p, f = 45 MHz VOUT = 2 V p-p, f = 45 MHz VOUT = 10 mV p-p, gain code = 0110 VOUT = 1 V p-p, gain code = 0110 VOUT = 2 V p-p, gain code = 0110 VOUT = 1 V p-p, gain code = 0110 VOUT = 1.6 V p-p, gain code = 0110 f = 10 MHz (shorted input) f = 10 MHz (input open) Max gain (gain code = 1011), RS = 50 Ω, unterminated Max gain (gain code = 1011), RS = 50 Ω, shunt terminated with 50 Ω Max gain (gain code = 1011), gain = 24 dB (input short) Max gain (gain code = 1011), gain = 24 dB (input open) Min gain (gain code = 0001), gain = −6 dB DC to 10 MHz RLOAD ≥ 500 Ω VS = +5 V VS = ±5 V Preamplifier input Max gain (gain code = 1011), gain = 24 dB, 3 σ limits Gain code = 0110, gain = 9 dB, VOUT = 1 V p-p f = 1 MHz f = 10 MHz Gain code = 1011, gain = 24 dB, VOUT = 2 V p-p f = 1 MHz f = 10 MHz Min gain (gain code = 0001), gain = −6 dB (preamplifier limited) Max gain (gain code = 1011), gain = 24 dB (VGA limited) VOUT = 1.4 V p-p-max, 10 tones, 2 MHz to 22 MHz with missing tone at 12 MHz (spacing 2 MHz), gain code = 1011, gain = 24 dB VOUT = 1.4 V p-p-max, 16 tones, 2 MHz to 38 MHz with missing tones at 10 MHz, 20 MHz, 30 MHz, and 40 MHz (spacing 2 MHz) Gain code = 1011, gain = 24 dB VOUT = 1 V p-p, f1 = 10 MHz, f2 = 11 MHz VOUT = 2 V p-p, f1 = 10 MHz, f2 = 11 MHz VOUT = 1 V p-p, f1 = 45 MHz, f2 = 46 MHz VOUT = 2 V p-p, f1 = 45 MHz, f2 = 46 MHz Gain code = 1011, gain = 24 dB VOUT = 1 V p-p, f = 10 MHz VOUT = 2 V p-p, f = 10 MHz VOUT = 1 V p-p, f = 45 MHz VOUT = 2 V p-p, f = 45 MHz Max gain (gain code = 1011), gain = 24 dB, VIN = 50 mV p-p to 500 mV p-p 1 MHz < f < 50 MHz, full gain range Min Typ 33 40 23 28 230 165 135 330 335 2.4 6.2 10.2 15.5 38 98.1 25 ≤3 VMDO ± 0.7 VMDO ± 1.4 ±3.6 VMDO ± 0.3 ±20 Max Unit dBm dBm dBm dBm MHz MHz MHz V/μs V/μs nV/√Hz nV/√Hz dB dB nV/√Hz nV/√Hz nV/√Hz Ω V V V V mV PREAMPLFIER AND VGA—GENERAL PARAMETERS −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Slew Rate Input Voltage Noise Noise Figure Output-Referred Noise Output Impedance Output Signal Range (per Pin) Input Signal Range Output Offset Voltage PREAMPLIFIER AND VGA—DYNAMIC PERFORMANCE Harmonic Distortion HD2 HD3 HD2 HD3 Harmonic Distortion HD2 HD3 HD2 HD3 Input 1 dB Compression Point −50 +50 −90 −87 −75 −58 −94 −90 −61 −84 1.9 −9.2 −68 dBc dBc dBc dBc dBc dBc dBc dBc dBm dBm dBc MTPR (In-Band) −61 dBc Two-Tone Intermodulation Distortion (IMD3) −92 −77 −50 −36 44 43 27 22 50 2 dBc dBc dBc dBc dBm dBm dBm dBm ns ns Output Third-Order Intercept Overload Recovery Group Delay Variation Rev. 0 | Page 4 of 32 AD8260 Parameter ACCURACY Absolute Gain Error Gain Law Conformance (DNL) GAIN CONTROL Gain Step per Code Gain Range Response Time LOGIC INTERFACES High Level Input Voltage Low Level Input Voltage Logic Input Bias Current POWER SUPPLY Supply Voltage Quiescent Current Conditions All gain codes, limits are 3σ Differential gain error code-to-code Min −0.5 −0.3 Typ ±0.15 ±0.15 3.0 30 50 1.4 0 Logic high, VLOGIC = 3.3 V Logic low Single supply Dual supply Full chip enabled (TXEN = 1, ENBL = 1, gain code = 0001) TXEN = 0, ENBL = 1, gain code = 0001, driver off, DGA on TXEN = 1, ENBL = 1, gain code = 0000, driver on, DGA off Chip disabled (TXEN = 0, ENBL = 0, gain code = 0000) VS = ±5 V, no signal Max gain (gain code = 1011), gain = 24 dB, 1 MHz Driver amplifier, 1 MHz No signal No signal, VPOS − VNEG = 10 V Bias only, TXEN = 0, gain code = 0000, ENBL = 0 to 1 All at once, TXEN = 0 to 1, gain code = 0000 to 0001, ENBL = 0 to 1 ENBL = 1, TXEN = 0, gain code = 0000 to 0001 ENBL = 1, gain code = 0001, TXEN stepped from 0 to 1 TXEN = 1 to 0, gain code = 0001 to 0000, ENBL = 1 to 0, ISUPPLY = 100 μA All at once, TXEN = 1 to 0, gain code = 0001 to 0000, ENBL = 1 to 0, ISUPPLY = 35 μA ENBL = 1, TXEN = 0, gain code = 0001 to 0000 ENBL = 1, gain code = 0000, TXEN = 1 to 0 3.3 ±3.3 28.3 19.1 10.8 35 34.2 −30 −48 93 342 0.4 0.3 0.3 0.2 20 50 0.4 2.2 0.2 18 10 ±5 VS 0.8 Max +0.5 +0.3 Unit dB dB dB dB ns V V μA nA V V mA mA mA μA mA dB dB mW mW μs μs μs μs μs μs μs μs Default = −6dB to +24 dB 30 dB gain change (gain code stepped from 0001 to 1011) PSRR Power Dissipation ENABLE TIMES Chip Enable Time Preamplifier and DGA Enable Time Driver Enable Time DISABLE TIMES Chip Disable Time Preamplifier and DGA Disable Time Driver Disable Time Rev. 0 | Page 5 of 32 AD8260 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Voltage Supply Voltage (VPOS, VNEG) Input Voltage (INxx, PRAI, FDBK, VMDI, VOCM) Logic Voltages Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering, 60 sec) Thermal Data1 Maximum Junction Temperature θJA θJC θJB ΨJT ΨJB 1 Rating ±6 V VPOS, VNEG VPOS, ground –40°C to +105°C –65°C to +150°C 300°C 125°C 47.3°C/W 6.9°C/W 28.6°C/W 0.6°C/W 27.4°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Thermal data at zero airflow with exposed pad soldered to four-layer JEDEC board with vias per JESD51-5. Rev. 0 | Page 6 of 32 AD8260 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VOCM INPP 32 31 30 29 28 27 26 25 VNEG VNEG INPN TXFB INRP INRN VMDO 1 TXEN 2 VMDI 3 VNCM 4 VPSB 5 ENBL 6 VGAP 7 VGAN 8 PIN 1 INDICATOR 24 TXOP 23 TXOP 22 VPOS 21 VPOS 20 VPSR 19 VMDO 18 PRAI 17 FDBK AD8260 TOP VIEW (Not to Scale) Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 191 2 3 4 5 6 7 8 9, 161 10, 201 11 12 13 14 15 17 18 21, 221 23, 241 25, 261 27 28 29 30 31 32 1 Mnemonic VMDO TXEN VMDI VNCM VPSB ENBL VGAP VGAN VNGR VPSR GNS3 GNS2 GNS1 GNS0 PRAO FDBK PRAI VPOS TXOP VNEG TXFB INPN INRN INRP INPP VOCM Description VMID Buffer Output. Requires robust ac decoupling with a capacitance of 0.1 μF capacitor or greater. Driver Enable. Logic threshold = 1.1 V with ±0.2 V hysteresis. VMID Input Voltage. Normally decoupled with a 0.1 μF capacitor. When pulled to VNCM, the VMID buffer shuts down. This can be useful when using the part with dual supplies or when an external midpoint generator is used. Negative Supply for Bias Cell, VMID Cell, and Logic Inputs. (Ground this pin in applications.) Positive Supply for Bias Cell and VMID Cell. Enable. Logic threshold = 1.1 V. When low, the AD8260 is disabled and the supply current is 35 μA when TXEN and all GNSx pins are also low. Positive VGA Output (Needs to Be Ac-Coupled for Single Supply). Negative VGA Output (Needs to Be Ac-Coupled for Single Supply). Negative Supply for Preamplifier and DGA (Set to −VPOS for Dual Supply; GND for Single Supply). Positive Supply for Preamplifier, DGA, and GNSx Logic Decoder. MSB for Gain Control. Logic threshold = 1.1 V. Gain Control Bit. Logic threshold = 1.1 V. Gain Control Bit. Logic threshold = 1.1 V. LSB for Gain Control. Logic threshold = 1.1 V. Preamplifier Output. Negative Input of Preamplifier. Positive Input of Preamplifier. Positive Supply for Driver Amplifier. Driver Output. Negative Supply for Driver Amplifier (Set to −VPOS for Dual Supply; GND for Single Supply). Feedback for Driver Amplifier. Negative Driver Amplifier Input. Negative Gain Resistor Input for Driver Amplifier. Positive Gain Resistor Input for Driver Amplifier. Positive Driver Amplifier Input. Output Common Mode Pin. Normally connected to Pin VMDO. Pins with the same name are connected internally. Rev. 0 | Page 7 of 32 07192-002 9 10 11 12 13 14 15 16 VNGR VPSR PRAO VNGR GNS3 GNS2 GNS1 GNS0 AD8260 TYPICAL PERFORMANCE CHARACTERISTICS VS (supply voltage) = 3.3 V, TA = 25°C, CL = 5 pF, f = 10 MHz, preamplifier gain = 2×, RFB1 and RFB2 of the preamplifier = 100 Ω, RLOAD of the driver amplifier = 500 Ω, TX and RX enabled, unless otherwise specified. 5 VOUT = 200mV p-p 20 T = +25°C T = –40°C 15 RTO 4 GAIN (dB) 3 T = +105°C NOISE (nV/√Hz) 10 RTI 2 5 1 07192-003 1M 10M FREQUENCY (Hz) 100M 200M 1M FREQUENCY (Hz) 10M 50M Figure 3. Small-Signal Frequency Response at Three Temperatures of the High Current Driver—See Figure 51 5 VOUT = 200mV p-p Figure 6. Input-Referred and Output-Referred Noise of the High Current Driver—See Figure 52 100 VS = +3.3V 4 OUTPUT IMPEDANCE (Ω) 10 GAIN (dB) 3 VS = +5V VS = ±5V 2 1 1 07192-004 1M 10M FREQUENCY (Hz) 100M 200M 1M 10M FREQUENCY (Hz) 100M Figure 4. Small-Signal Frequency Response of the High Current Driver for Three Supply Voltages—See Figure 51 5 VLOAD = VLOAD = VLOAD = VLOAD = 1V p-p; 1V p-p; 2V p-p; 2V p-p; RLOAD = RLOAD = RLOAD = RLOAD = 50Ω 500Ω 50Ω 500Ω Figure 7. Output Impedance of the High Current Driver See Figure 53 –20 –30 HARMONIC DISTORTION (dBc) 4 –40 –50 –60 HD3 –70 –80 –90 GAIN (dB) 3 2V p-p HD2 2 1 1V p-p 07192-005 Figure 5. Large-Signal Frequency Response of the High Current Driver for Two Values of Output Voltage and Two Values of Load Resistance—See Figure 51 Figure 8. Harmonic Distortion (HD2, HD3) vs. Load Resistance for the High Current Driver—See Figure 54 Rev. 0 | Page 8 of 32 07192-008 0 100k 1M 10M FREQUENCY (Hz) 100M 200M – 100 10 100 LOAD RESISTANCE (Ω) 1k 07192-007 0 100k 0 .1 100k 07192-006 0 100k 0 100k AD8260 –20 f = 10MHz –30 0 HARMONIC DISTORTION (dBc) –40 –50 –60 –70 –80 –90 HD2, HD3, HD2, HD3, VOUT = 1V p-p VOUT = 1V p-p VOUT = 2V p-p VOUT = 2V p-p –20 RLOAD = 50Ω, VOUT = 1V p-p RLOAD = 50Ω, VOUT = 2V p-p RLOAD = 500Ω, VOUT = 1V p-p RLOAD = 500Ω, VOUT = 2V p-p IMD3 (dBc) 07192-009 –40 –60 –80 0 10 20 60 40 30 50 70 LOAD CAPACITANCE (pF) 80 90 100 10M FREQUENCY (Hz) 100M Figure 9. Harmonic Distortion (HD2, HD3) vs. Load Capacitance at Two Values of Output Voltage for the High Current Driver—See Figure 54 0 f = 10MHz –20 HARMONIC DISTORTION (dBc) Figure 12. IMD3 vs. Frequency for Two Values of Output Voltage and Two Values of Load Resistance for the High Current Driver—See Figure 55 50 40 –40 OIP3 (dBm) 30 RLOAD = 50Ω, VOUT = 1V p-p RLOAD = 50Ω, VOUT = 2V p-p RLOAD = 500Ω, VOUT = 1V p-p RLOAD = 500Ω, VOUT = 2V p-p –60 HD3 –80 HD2 20 –100 10 07192-010 0 0.5 1.0 2.0 1.5 OUTPUT VOLTAGE (V p-p) 2.5 3.0 10M FREQUENCY (Hz) 100M Figure 10. Harmonic Distortion (HD2, HD3) vs. Output Voltage for the High Current Driver—See Figure 54 –20 –30 HARMONIC DISTORTION (dBc) Figure 13. Third-Order Intercept (OIP3) vs. Frequency for the High Current Driver See Figure 55 20 RLOAD = 50Ω RLOAD = 500Ω 15 –40 IP1dB (dBm) –50 –60 –70 –80 –90 –100 1M 1V p-p 2V p-p HD2 HD3 10 5 07192-011 10M FREQUENCY (Hz) 100M 0 1M 10M FREQUENCY (Hz) 100M Figure 11. Harmonic Distortion (HD2, HD3) vs. Frequency of the High Current Driver at Two Values of Output Voltage—See Figure 54 Figure 14. Input-Referred 1 dB Compression (IP1dB) vs. Frequency for Two Values of Load Resistance for the High Current Driver Rev. 0 | Page 9 of 32 07192-014 07192-013 –120 0 2M 07192-012 –100 –100 2M AD8260 0 –10 OUTPUT VOLTAGE (V) 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 RLOAD = 50Ω NONINVERTING –20 –10 0 10 20 30 TIME (ns) 40 50 60 70 80 07192-018 07192-020 07192-019 CLOAD = 5pF CLOAD = 10pF CLOAD = 47pF –20 –30 –40 –50 –60 –70 –80 –90 0 2 4 6 8 10 12 14 16 FREQUENCY (MHz) 18 20 22 24 07192-015 OUTPUT (dBm) –0.20 –30 Figure 15. Missing Tone Power Ratio for the High Current Driver Figure 18. Small-Signal Pulse Response of the High Current Driver for Various Values of Load Capacitance, CLOAD, and 50 Ω Load—See Figure 56 2.0 CLOAD = 5pF NONINVERTING 0.20 0.15 0.10 OUTPUT VOLTAGE (V) CLOAD = 5pF NONINVERTING 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 07192-016 0 .05 0 –0.05 –0.10 –0.15 –0.20 –30 OUTPUT VOLTAGE (V) RLOAD = 10Ω RLOAD = 50Ω RLOAD = 100Ω RLOAD = 500Ω –20 –10 0 10 20 30 40 TIME (ns) 50 60 70 80 RLOAD = RLOAD = RLOAD = RLOAD = 30 20 10 0 10 10Ω 50Ω 100Ω 500Ω 40 50 60 70 80 –2.0 20 30 TIME (ns) Figure 16. Small-Signal Pulse Response of the High Current Driver for Various Values of Load Resistance, RLOAD—See Figure 56 0.20 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 –30 CLOAD = 5pF CLOAD = 10pF CLOAD = 47pF Figure 19. Large-Signal Pulse Response of the High Current Driver for Various Values of Load Resistance, RLOAD—See Figure 56 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 RLOAD = 500Ω NONINVERTING –20 –10 0 10 20 30 TIME (ns) 40 50 60 70 80 CLOAD = 5pF CLOAD = 10pF CLOAD = 47pF OUTPUT VOLTAGE (V) RLOAD = 500Ω NONINVERTING OUTPUT VOLTAGE (V) –20 –10 0 10 20 30 TIME (ns) 40 50 60 70 80 Figure 17. Small-Signal Pulse Response of the High Current Driver for Various Values of Load Capacitance, CLOAD, and RLOAD = 500 Ω—See Figure 56 07192-017 –2.0 –30 Figure 20. Large-Signal Pulse Response of the High Current Driver for Various Values of Load Capacitance, CLOAD, and RLOAD = 500 Ω—See Figure 56 Rev. 0 | Page 10 of 32 AD8260 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 07192-021 RLOAD = 50Ω NONINVERTING 1.00 ABSOLUTE GAIN ERROR (dB) CLOAD = 5pF CLOAD = 10pF CLOAD = 47pF 0.75 0.50 0.25 0 –0.25 –0.50 –0.75 07192-024 07192-026 07192-025 OUTPUT VOLTAGE (V) AVERAGE OF 3 SAMPLES f = 1MHz, 10MHz, AND 40MHz –2.0 –30 –20 –10 0 10 20 30 TIME (ns) 40 50 60 70 80 –1.00 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 GAIN SELECT CODE Figure 21. Large-Signal Pulse Response of the High Current Driver for Various Values of Load Capacitance, CLOAD, and 50 Ω Load—See Figure 56 27 24 21 18 15 AVERAGE OF 3 SAMPLES f = 1MHz, 10MHz, AND 40MHz Figure 24. Absolute Gain Error vs. Gain Select Code for Three Samples for the VGA/Preamplifier at Three Frequencies Normalized to 1 MHz and Code 0110 See Figure 57 1.00 0.75 0.50 T = +105°C T = +25°C T = –40°C GAIN ERROR (dB) GAIN (dB) 12 9 6 3 0 –3 –6 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 GAIN SELECT CODE 07192-022 0.25 0 –0.25 –0.50 –0.75 –1.00 AVERAGE OF 3 SAMPLES AT EACH TEMPERATURE 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 GAIN SELECT CODE –9 Figure 22. Gain vs. Gain Select Code for Three Samples for the VGA/Preamplifier at Three Frequencies—See Figure 57 4.00 3.75 3.50 GAIN STEP (dB) Figure 25. Gain Error vs. Gain Select Code at Three Temperatures for the VGA/Preamplifier—See Figure 57 50 40 30 T = +105°C T = +25°C T = –40°C 3.25 3.00 2.75 2.50 2.25 AVERAGE OF 3 SAMPLES f = 1MHz, 10MHz, AND 40MHz OFFSET VOLTAGE (mV) 20 10 0 –10 –20 –30 –40 AVERAGE OF 3 SAMPLES AT EACH TEMPERATURE 07192-023 2.00 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 GAIN SELECT CODE –50 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 GAIN SELECT CODE Figure 23. Gain Step vs. Gain Select Code for Three Samples for the VGA/Preamplifier at Three Frequencies—See Figure 57 Figure 26. Output Offset Voltage vs. Gain Select Code at Three Temperatures for the VGA/Preamplifier—See Figure 58 Rev. 0 | Page 11 of 32 AD8260 27 24 21 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 2 8 10 DIFFERENTIAL GAIN (dB) 18 15 12 9 6 3 0 –3 –6 –9 GROUP DELAY (ns) 07192-027 6 4 1M 10M FREQUENCY (Hz) 100M 200M 10M FREQUENCY (Hz) 100M Figure 27. Frequency Response for a Supply Voltage (VS) of 3.3 V for all Codes of the VGA/Preamplifier—See Figure 59 27 24 21 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 OUTPUT RESISTANCE (Ω) Figure 30. Group Delay vs. Frequency for the VGA/Preamplifier See Figure 59 100 DIFFERENTIAL GAIN (dB) 18 15 12 9 6 3 0 –3 –6 –9 VS = 5V –12 100k 10 VGAN VGAP 1 07192-028 1M 10M FREQUENCY (Hz) 100M 200M 1M 10M FREQUENCY (Hz) 100M Figure 28. Frequency Response for a Supply Voltage (VS) of 5 V for All Codes for the VGA/Preamplifier—See Figure 59 27 24 21 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 Figure 31. Output Resistance vs. Frequency for the VGA/Preamplifier See Figure 60 50 DIFFERENTIAL GAIN (dB) 18 15 12 9 6 3 0 –3 –6 –9 VS = ±5V –12 100k OUTPUT-REFERRED NOISE (nV/√Hz) 40 30 20 07192-029 1M 10M FREQUENCY (Hz) 100M 200M 10 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 GAIN SELECT CODE Figure 29. Frequency Response for a Dual Supply (VS) = ±5 V for All Codes for the VGA/Preamplifier—See Figure 59 Figure 32. Output-Referred Noise vs. Gain Select Code for the VGA/Preamplifier—See Figure 61 Rev. 0 | Page 12 of 32 07192-032 07192-031 0 .1 100k 07192-030 –12 100k 0 1M AD8260 100 GAIN CODE = 1011 30 VOUT = 1V p-p GAIN CODE = 0110 HARMONIC DISTORTION (dBc) OUTPUT-REFERRED NOISE (nV/√Hz) 40 50 60 70 HD2 HD3 07192-033 1M FREQUENCY (Hz) 10M 50M 0 200 400 600 800 1000 1200 1400 1600 1800 2000 LOAD RESISTANCE (Ω) Figure 33. Output-Referred Noise vs. Frequency for the VGA/Preamplifier at Maximum Gain—See Figure 61 100 Figure 36. Harmonic Distortion (HD2, HD3) vs. Load Resistance for the VGA/Preamplifier—See Figure 62 –30 VOUT = 1V p-p GAIN CODE = 0110 INPUT-REFERRED NOISE (nV/√Hz) HARMONIC DISTORTION (dBc) –40 –50 10 –60 HD2 HD3 –70 07192-034 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 GAIN SELECT CODE 0 10 20 30 LOAD CAPACITANCE (pF) 40 50 Figure 34. Input-Referred Noise vs. Gain Select Code for the VGA/Preamplifier See Figure 61 10 Figure 37. Harmonic Distortion (HD2, HD3) vs. Load Capacitance for the VGA/Preamplifier—See Figure 62 0 SHORT-CIRCUIT INPUT-REFERRED NOISE (nV/√Hz) GAIN CODE = 1011 HARMONIC DISTORTION (dBc) –20 VOUT = 1V p-p –40 HD2, HD3, HD2, HD3, fC = 1MHz fC = 1MHz fC = 10MHz fC = 10MHz –60 –80 MEASUREMENT OF DISTORTION IS LIMITED BY THE MAXIMUM DYNAMIC INPUT RANGE OF THE PREAMPLIFIER –100 07192-035 1M FREQUENCY (Hz) 10M 50M 0101 0110 0111 1000 1001 1010 1011 GAIN SELECT CODE Figure 35. Short-Circuit Input Noise vs. Frequency for the VGA/Preamplifier See Figure 61 Figure 38. Harmonic Distortion (HD2, HD3) vs. Gain Select Code at 1 MHz and 10 MHz for the VGA/Preamplifier—See Figure 62 Rev. 0 | Page 13 of 32 07192-038 1 100k –120 07192-037 1 –80 07192-036 10 100k 80 AD8260 0 GAIN CODE = 1011 VOUT = 1V p-p 10 5 0 HD2 HD3 –60 INPUT IP1dB (dBm) HARMONIC DISTORTION (dBc) –20 IP1dB LIMITED AT LOW GAIN BY THE DYNAMIC RANGE OF THE PREAMPLIFIER –40 –5 –10 –15 –20 –80 –100 –25 07192-039 1MHz 10MHz 10M FREQUENCY (Hz) 100M –30 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 GAIN SELECT CODE Figure 39. Harmonic Distortion (HD2, HD3) vs. Frequency for the VGA/Preamplifier—See Figure 62 0 Figure 42. Input 1 dB Compression (IP1dB) vs. Gain Select Code at 1 MHz and 10 MHz for the VGA/Preamplifier T INPUT –20 VOUT = 1V p-p TONES 1MHz APART EACH TONE 0.5V p-p GAIN CODE = 1011 LOWER UPPER –80 M 1 2mV/DIV 0V –40 IMD3 (dBc) –60 50mV/DIV 0V OUTPUT –100 –120 1M 07192-040 10M FREQUENCY (Hz) 100M CH1 2.00VΩ MATH 5.00mV M10.0ns 10.0ns T A CH4 180µV 27.2000ns Figure 40. Third-Order Intermodulation Distortion (IMD3) vs. Frequency for the VGA/Preamplifier 60 Figure 43. Small-Signal Pulse Response for the VGA/Preamplifier T INPUT 50 3 20mV/DIV 0V 40 OIP3 (dBm) 30 20 LOWER UPPER GAIN CODE = 1011 TONES 1MHz APART 07192-041 M 500mV/DIV 0V OUTPUT 10 0 1M 10M FREQUENCY (Hz) 100M CH3 20.0mVΩ MATH 50.0mV M10.0ns 10.0ns T A CH4 200µV 27.2000ns Figure 41. OIP3 vs. Frequency for the VGA/Preamplifier Figure 44. Large-Signal Pulse Response for the VGA/Preamplifier Rev. 0 | Page 14 of 32 07192-044 07192-043 07192-042 –120 1M AD8260 1.5 –10 +SUPPLY VGA/PREAMPLIFIER +SUPPLY HIGH CURRENT DRIVER –SUPPLY VGA PREAMPLIFIER –SUPPLY HIGH CURRENT DRIVER 1.0 OUTPUT VOLTAGE (V) VS = +3V, +5V, AND ±5V 0.5 PSRR (dB) –20 –30 0 –40 –0.5 –50 VS = ±3.3V GAIN CODE = 1011 –1.0 –60 07192-045 –2 –1 0 1 2 3 TIME (ns) 4 5 6 7 8 1M FREQUENCY (Hz) 5M Figure 45. Large-Signal Pulse Response for Various Values of Supply Voltage for the VGA/Preamplifier Figure 48. PSRR vs. Frequency for Dual Supplies for the High Current Driver and the VGA/Preamplifier 40 QUIESCENT SUPPLY CURRENT (mA) 35 30 25 20 15 10 5 0 –55 FULLY ENABLED VGA/PREAMPLIFIER ENABLED HIGH CURRENT DRIVER ENABLED –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 T M CH1 AMPL 3.28V CH2 AMPL 1.20mV MATH AMPL 117mV 1 4 CH1 1.00VΩ CH2 20.0mVΩ CH2 20.0mVΩ MATH 100mV 200nV M200ns A CH1 T 595.200ns 760mV Figure 46. Gain Response for the VGA/Preamplifier, Yellow: Gain Code Select, Red: VGA Differential Output, Blue/Green: VGAP and VGAN 2 07192-046 Figure 49. Quiescent Supply Current vs. Temperature for Three Operating States 80 STANDBY QUIESCENT SUPPLY CURRENT (µA) 70 60 50 40 30 20 10 07192-050 1 OUTPUT VOLTAGE (V) 0 –1 0 100 200 300 400 TIME (ns) 500 600 700 800 07192-047 –2 –200 –100 0 –55 –35 –15 5 25 45 65 TEMPERATURE (°C) 85 105 125 Figure 47. Overdrive Recovery of the VGA/Preamplifier—Gain Code = 1011 Figure 50. Standby Quiescent Supply Current vs. Temperature Rev. 0 | Page 15 of 32 07192-049 07192-048 –1.5 –3 –70 100k AD8260 TEST CIRCUITS NETWORK ANALYZER OUT 50Ω 50Ω IN AD8260—HIGH CURRENT DRIVER 0.1µF 50Ω INRP 0.1µF VOCM 07192-151 INRN TXFB + VMDO Figure 51. Test Circuit for Frequency Response of the High Current Driver AD8260—HIGH CURRENT DRIVER INRN 0.1µF INRP 0.1µF – – + VOCM VMDO TXFB TXOP 0.1µF Figure 52. Test Circuit for Input-Referred and Output-Referred Noise of the High Current Driver AD8260—HIGH CURRENT DRIVER INRN 0.1µF INRP 0.1µF – + VOCM +3.3V NETWORK ANALYZER WITH S-PARAMETER MODE IN TXFB TXOP –3.3V Figure 53. Test Circuit for Output Impedance of the High Current Driver LP FILTER 1:1 SIGNAL GENERATOR 50Ω 07192-153 50Ω 07192-152 AD8260—HIGH CURRENT DRIVER 0.1µF 50Ω – 50Ω 0.1µF VOCM VMDO TXOP INRP + 0.1µF INRN TXFB RLOAD Figure 54. Test Circuit for Harmonic Distortion of the High Current Driver Rev. 0 | Page 16 of 32 07192-154 – – TXOP 0.1µF 453Ω 5pF + IN SPECTRUM ANALYZER 50Ω SPECTRUM ANALYZER IN 50Ω CLOAD AD8260 SIGNAL GENERATORS 50Ω AD8260—HIGH CURRENT DRIVER 1kΩ 1kΩ INRP 0.1µF VOCM VMDO 07192-155 1:1 0.1µF INRN – TXFB SPECTRUM ANALYZER TXOP 50Ω + 0.1µF 453Ω IN 50Ω Figure 55. Test Circuit for IMD3 and OIP3 of the High Current Driver AD8260—HIGH CURRENT DRIVER 0.1µF INRN TXFB RLOAD CLOAD 12.5Ω OSCILLOSCOPE 50Ω 0.1µF INRP – + VOCM VMDO TXOP 0.1µF IN 50Ω 50Ω Figure 56. Test Circuit for Pulse Response of the High Current Driver SIGNAL GENERATOR 50Ω AD8260—VGA/PREAMPLIFIER 0.1µF + 50Ω PREAMP – 0.1µF OSCILLOSCOPE 453Ω 0.1µF 453Ω 100Ω IN 50Ω VMDO Figure 57. Test Circuit for Gain Step Size and Error of the VGA/Preamplifier AD8260—VGA/PREAMPLIFIER 0.1µF + PREAMP – DMM 100Ω VMDO Figure 58. Test Circuit for Output-Referred Offset Voltage of the VGA/Preamplifier Rev. 0 | Page 17 of 32 07192-158 100Ω 07192-157 100Ω 07192-156 AD8260 NETWORK ANALYZER 50Ω IN AD8260—VGA/PREAMPLIFIER 0.1µF + 50Ω PREAMP – 0.1µF 453Ω 0.1µF 100Ω 453Ω VMDO Figure 59. Test Circuit for Frequency Response and Group Delay of the VGA/Preamplifier NETWORK ANALYZER WITH S-PARAMETER CAPABILITY 50Ω IN AD8260—VGA/ PREAMPLIFIER 0.1µF + PREAMP – +3.3V 100Ω –3.3V 07192-160 100Ω Figure 60. Test Circuit for Output Resistance of the VGA/Preamplifier 07192-159 100Ω AD8260—VGA/PREAMPLIFIER 0.1µF 0.1µF SPECTRUM ANALYZER AD8129 0.1µF ×10 50Ω + PREAMP VMDO VGA – 1kΩ 0.1µF 1kΩ 100Ω VMDO Figure 61. Test Circuit for Input-Referred and Output-Referred Noise Measurements of the VGA/Preamplifier Rev. 0 | Page 18 of 32 07192-051 100Ω AD8260 SPECTRUM ANALYZER LP FILTER AD8260—VGA/PREAMPLIFIER 0.1µF 0.1µF 475Ω 1:1 50Ω IN 0.1µF 475Ω + 50Ω SIGNAL GENERATOR 50Ω PREAMP – 100Ω VMDO Figure 62. Test Circuit for Harmonic Distortion Measurements of the VGA/Preamplifier AD8260—VGA/PREAMPLIFIER 0.1µF + 50Ω 50Ω 100Ω PREAMP – IN OSCILLOSCOPE 50Ω VMDO Figure 63. Test Circuit for IP1dB, Pulse Response, Overdrive Recovery, and Gain Response of the VGA/Preamplifier Rev. 0 | Page 19 of 32 07192-163 100Ω 07192-052 100Ω AD8260 THEORY OF OPERATION OVERVIEW The AD8260 is a self-contained transceiver intended for analog communications using a power line as the media. Operating on supplies as low as 3.3 V, it includes a high current driver usable as a transmitter and a low noise digitally programmable variable gain amplifier (DGA), usable as a receiver (see Figure 64). An uncommitted current-feedback high frequency op amp acts as a preamplifier and interface to the DGA and is user configured for gains greater than 6 dB. Combined, the VGA and preamplifier are usable at high signal levels from dc to 100 MHz, with a small-signal −3 dB bandwidth of 230 MHz. To implement a high current-output VGA, the VGA output can be connected to the driver-amplifier differential input. The small-signal −3 dB bandwidth of the driver amplifier is 195 MHz and the large-signal bandwidth is >115 MHz, even when driving a 50 Ω load. The device is fabricated on the Analog Devices, Inc., high speed (eXtra Fast Complementary Bipolar) XFCB process. The preamplifier and DGA feature low dc offset voltage, and a nominal gain range of −6 dB to +24 dB, a 30 dB gain span, and a differential output for ADC driving. The power consumption is 93 mW with a single 3.3 V supply. The supply current is typically about 28 mA when all circuits in the device are active. During normal usage, either the driver amplifier is on or the preamplifier and DGA are on and, therefore, the supply current in general is less than 28 mA. The gain of the AD8260 VGA is programmed via a 4-bit parallel interface. Figure 64 shows the circuit block diagram and basic application connections, and illustrates the envisioned external DAC, ADC, and power-line bus interface connections. The diagram shows the connections for single 3.3 V supply operation; if a dual supply is available, the VMID generator can be shut down and Pin VMDI, Pin VMDO, and Pin VOCM need to be grounded. Note that Pin VNCM functions as the negative supply for the bias and VMID cells, plus the logic interfaces, and should always be tied to ground. For optimal dynamic range, it is important that the inputs and outputs to both the driver amplifier and the preamplifier and the DGA output amplifier be ac-coupled in a single-supply application. In Figure 64, the DAC and ADC are presumed to operate on a 1.8 V or 3.3 V supply with a corresponding limited output and input swing. The DAC outputs are currents that point down and generate a voltage in the 50 Ω resistors that are connected to ground. The maximum voltage with a peak DAC output current of 15 mA is 0.75 V; if a DAC with a 20 mA peak current is used, then the maximum voltage is 1 V per side for a differential input signal of 2 V p-p. The driver amplifier supports a 3 V p-p output swing on a 3.3 V supply. Because of its gain of 1.5, the maximum input swing is 2 V p-p. The corresponding maximum output swing for the DGA is 2.4 V p-p differential; the input to the preamplifier can be a maximum of 0.6 V p-p. Rev. 0 | Page 20 of 32 AD8260 1.8V OR 3.3V 20mA DAC 50Ω 50Ω 0.1µF 0.1µF CFB VOCM 32 1V MAX WITH 200mA pk OPTIONAL USER SELECTED CFB REDUCES HF PEAKING WITH CAPACITIVE LOADING VNEG 26 INPP 31 30 29 28 27 25 1.5kΩ VMDO 0.1µF TXEN 0V, 1.8V/3.3V 0.1µF VMDI VNCM VPSB ENBL VGAP VGAN 1 1kΩ + 1kΩ 1.5kΩ – 24 VNEG TXFB INRN INPN INRP TXOP TXOP VPOS VPOS VPSR VMDO OPTIONAL CLAMP DIODES AND SNUBBING RESISTORS GM ×1 23 2 0.1µF 0.1µF 3 AD8260 VMID BIAS 22 4 21 POWERLINE CABLE, ETC. 3.3V 3.3V 1.8V OR 3.3V 0V, 1.8V/3.3V LOW-PASS AA FILTER 0.1µF 0.1µF INN 5 20 6 ATTENUATOR 19 0.1µF 18 ADC FS INPUT 2V p-p INP 7 PRAI FDBK RFB1 100Ω RFB2 100Ω GM STAGES 8 LOGIC 9 10 11 12 13 14 15 16 17 VNGR VPSR VNGR GNS3 GNS2 GNS1 GNS0 PRAO 3.3V Figure 64. Block Diagram and Basic Application Connections HIGH CURRENT DRIVER AMPLIFIER The high current driver amplifier can deliver very large output currents suitable for driving complex impedances, such as a power line, a 50 Ω line, or a coaxial cable. The input of the amplifier is fully differential and intended to be driven by a differential current-output DAC, as shown in Figure 64. The differential input signal is amplified by 1.5× and produces a 2.25 V p-p single-ended output signal from a 1.5 V p-p input signal. A DAC with 15 mA maximum output current into a 50 Ω load provides 1.5 V p-p of input voltage and results in 2.25 V p-p at the output. A DAC whose output is 20 mA produces an output swing of 3 V p-p (neglecting a small gain error when driving the parallel combination of the 50 Ω load-resistor and the internal 1 kΩ gain resistor of the AD8260). For a 3.3 V supply rail, the maximum limit of the output voltage is 3 V p-p and distorts severely if exceeded. The recommended output for optimum distortion is 2 V p-p for a 3.3 V supply. Correspondingly, larger output swings are accommodated for higher supply voltages such as +5 V or ±5 V. For optimum distortion, the input drive must be controlled such that the output swing is well within saturation levels established by the supply rail. The output swing can be reduced by using load resistors with values less than 50 Ω or by reducing the amplifier gain by connecting external resistors in parallel with the internal 1 kΩ and 1.5 kΩ resistors between Pin 27, Pin 28, and Pin 29, and between Pin 30, Pin 31, and Pin 32. Coincidently, noise is reduced because the gain setting resistors are the primary noise sources of the high current driver amplifier. The output-referred noise is 14 nV/√Hz, of which 11 nV/√Hz is due to the gain setting resistors. Matching of the gain setting resistors is important for good common-mode rejection and the accuracy of the differential gain. If external resistors are used, their accuracy should be at least ±1%. How low the resistor values can be is primarily determined by the quality of the ac ground at Pin VOCM; as the gain setting resistors decrease in value, the dynamic current increases, and the quality of the decoupling capacitors needs to increase correspondingly. Rev. 0 | Page 21 of 32 07192-053 AD8260 PRECAUTIONS TO BE OBSERVED DURING HALFDUPLEX OPERATION During receive, when the high current driver-amplifier is disabled, its gain setting resistors provide a signal path from input to output. To prevent inadvertent DAC signals from being transmitted while receiving via the preamplifier and DGA, the DAC in Figure 64 must have no output signal. During transmit, the preamplifier and VGA should be disabled through any of the nongain-setting codes (see Table 4). determine the −3 dB bandwidth of the amplifier. Smaller resistor values may compromise preamplifier stability. Because the AD8260 is internally dc-coupled, larger preamplifier gains increase its offset voltage. The circuit contains an internal bias resistor and some offset compensation; however, if a lower value of offset voltage is required, it can be compensated by connecting a resistor between the FDBK pin and the supply voltage. If the offset is negative, the resistor value connects to the negative supply; otherwise, it connects to the positive supply. For larger gains, the overall noise is reduced if a low value of RFB1 is selected. For values of RFB1 = 20 Ω and RFB2 = 301 Ω, the preamplifier gain is 16× (24.1 dB) and the input-referred noise is about 1.5 nV/√Hz. For this value of gain, the overall gain range increases by 18 dB so that the absolute gain range is 12 dB to 42 dB. VMID BUFFER The VMID buffer is a dc bias source that generates the voltage on Pin 1 and Pin 19, VMDO. Node VMDO cannot accommodate large dynamic currents and requires excellent ac decoupling to ground. A high quality 0.1μF capacitor located as close as possible to Pin 1 and Pin 19 (see Figure 64) is normally sufficient to decouple the high values of current from Node VMDO. When operating with dual power supplies, the buffer is disabled by connecting Pin VMDI, Pin VOCM, and Pin VMDO to ground. Because the logic decoder in the DGA (GNSx inputs) requires 3.3 V of headroom, the positive supply rails must be 3.3 V or greater whether single-ended or dual. If a dual supply is used, the negative rails are the same magnitude (opposite polarity) as the positive, that is, −3.3 V when VPOS, VPSB, and VPSR are +3.3 V. PREAMPLIFIER NOISE The total input-referred voltage and current noise of the positive input of the preamplifier is about 2.4 nV/√Hz and 5 pA/√Hz, respectively. The DGA output referred noise is about 25 nV/√Hz at low gains and 39 nV/√Hz at the highest gain. The 25 nV/√Hz divided by the DGA fixed gain of 8× results in 3.12 nV/√Hz referred to the DGA input. Note that this value includes the noise of the DGA gain setting resistors as well. If this voltage is divided by the preamplifier gain of 2×, the DGA noise referred all the way to the preamplifier input is about 1.56 nV/√Hz. From this, it can be determined that the preamplifier, including the 100 Ω gain setting resistors, contributes about 1.8 nV/√Hz. The two 100 Ω resistors each contribute 1.29 nV/√Hz at the output of the preamplifier and 0.9 nV/√Hz referred to the input. With the gain resistor noise subtracted, the preamplifier noise alone is about 1.6 nV/√Hz. Equation 1 shows the calculation that determines the outputreferred noise at maximum gain (24 dB or 16×). PREAMPLIFIER The AD8260 includes an uncommitted current feedback op amp to buffer the resistive attenuator of the DGA. External resistors are used to adjust the gain. The preamplifier is characterized with a noninverting gain of 6 dB (2×) and both gain resistor values of 100 Ω. The preamplifier gain can be increased using different gain ratios of RFB1 and RFB2, trading off bandwidth and offset voltage. The sum of the values of RFB1 and RFB2 should be ≥200 Ω to maintain low distortion. RFB2 should be ≥100 Ω because it and an internal compensation capacitor en−out = (en,RS × At )2 + (en,PrA × At )2 + (in,PrA × RS )2 + (en,RFB1 × RFB2 × AVGA )2 + (en,RFB2 × AVGA )2 + (en,VGA × AVGA )2 R FB1 (1) where: At is the total gain from preamplifier input to the VGA output. en,RS is the noise of the source resistance. en,PrA is the input-referred voltage noise of the preamplifier. in,PrA is the current noise of the preamplifier at the PRAI pin. RS is the source resistance. AVGA is the VGA gain. en,RFB1 is the voltage noise of RFB1. en,RFB2 is the voltage noise of RFB2. en,VGA is the input-referred voltage noise of DGA (low gain output-referred noise divided by a fixed gain of 8×). Rev. 0 | Page 22 of 32 AD8260 Assuming RS = 0, RFB1 = RFB2 = 100 Ω, At = 16, and AVGA = 8, the noise simplifies to Table 4. Gain Control Logic Table D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Disable −6 −3 0 3 6 9 12 15 18 21 24 Disable Disable Disable Disable Comments PrA and DGA powered down The numbers in the function column are composite gain values in dB for the corresponding code, when the preamplifier gain is 6 dB. For other values of preamplifier gain, the gain is amended accordingly; for example, if the preamplifier gain is 12 dB, the gain values increase by 6 dB. When using the DGA single ended, the composite gain decreases by 6 dB. PrA and DGA powered down PrA and DGA powered down PrA and DGA powered down PrA and DGA powered down e n −out = (1.6 × 16) + 2 (1.29 × 8) + (3.12 × 8) = 2 2 2 (2) 39 nV / Hz Taking this result and dividing by 16 gives the total input-referred noise with a short-circuited input as 2.4 nV/√Hz. When the preamplifier is used in the inverting configuration with the same RFB1 = RFB2 = 100 Ω as in the previous example, then en-out does not change; however, because the gain decreases by 6 dB, the input-referred noise increases by a factor of 2 to about 4.8 nV/√Hz. The reason for this is that the noise gain to the DGA output of all the noise generators stays the same, but the preamp inverting gain is (−1×) compared to the (+2×) in the noninverting configuration. This doubles the input-referred noise. DGA Referring to Figure 64, the signal path consists of a 30 dB programmable attenuator followed by a fixed gain amplifier of 18 dB for a total DGA gain range of −12 dB to +18 dB. With the preamplifier configured for a gain of 6 dB, the composite gain range is −6 dB to +24 dB from single-ended preamplifier input to differential DGA output. The DGA plus preamplifier with 6 dB of gain implements the following gain law: dB ⎡ ⎤ Gain(dB) = ⎢3.01 × Code ⎥ + ICPT (dB) Code ⎣ ⎦ where: ICPT is the nominal intercept, −9 dB. Code values are decimal from 1 to 11. The ICPT increases as the gain of the preamplifier is increased. For example, if the gain of the preamplifier is increased by 6 dB, then ICPT increases to −3 dB. OUTPUT STAGE The gain of the voltage feedback output stage is fixed at 18 dB and inaccessible to the user. Otherwise, it is similar to the preamplifier in speed and bandwidth. The overall −3 dB bandwidth of the preamplifier and DGA combination is 230 MHz. ATTENUATOR The input resistance of the VGA attenuator is nominally 265 Ω. Assuming that the default preamplifier feedback network of RFB1 and RFB2 is 200 Ω, the effective preamplifier load is about 114 Ω. The attenuator is composed of ten 3.01 dB sections for a total attenuation span of −30.10 dB. Following the attenuator is a fixed gain amplifier with 18 dB (8×) gain. Because of this relatively low gain, the output offset is less than 20 mV over the operating temperature range; the offset is largest at maximum gain because the preamplifier offset is amplified. The VMDO pin defines the common-mode reference for the input and output. The voltage at VMID is half the supply voltage for single-supply operation and 0 V when dual supplies are used. GAIN CONTROL To change the gain, the desired four bits are programmed on Pin GNS0 to Pin GNS3, where GNS0 is the LSB (D0) and GNS3 is the MSB (D3). The states of Decimal 0 and Decimal 12 through Decimal 15 disable the preamplifier (PrA) and DGA (see Table 4). Rev. 0 | Page 23 of 32 AD8260 SINGLE-SUPPLY OPERATION AND AC COUPLING When operating the AD8260 from a single supply, there are two bias options for VMDO. • Use an external low impedance midpoint reference at Pin VMDO and pull VMDI to VNCM to shut down the VMID buffer. Use the internal VMID buffer as shown in Figure 64. active first to listen to any signals, and the driver needs to be off. Therefore, the gain code should be set to 0001 (−6 dB of gain) first and then the gain adjusted as needed. Note that any code besides 1 to 11 (binary) disables the receive section (see Table 4). During receive, it is also important that the DAC that provides the signal for the high current driver be disabled to avoid interfering with the received signal. After receive, presumably data needs to be transmitted via the high current driver amplifier. At this point, the DAC should still be off. Pull Pin TXEN high and allow the high current driver to settle. Enable the DAC. Although the preamplifier and DGA can remain enabled during the previous sequence, there may be significant preamplifier overdrive, and it is best that the receiver be disabled while transmitting. Pull Pin ENBL low to disable the chip. To achieve the specified sleep current of 35 μA, all logic pins must be pulled low as well. • 3. In both cases, decoupling capacitors are needed on Pin VMDO to absorb the dynamic currents. During single-supply operation, the preamplifier input is normally ac-coupled. An internal bias resistor (nominally 1 k Ω) connected between PRAI and VMDO provides bias to the preamplifier input pin. A 50 Ω resistor connected between Pin PRAI and Pin VMDO, in parallel with the internal 1 kΩ, serves as a termination resistor and at the same time reduces the offset; the result is a composite value of about 48 Ω. The VGA input is biased through the attenuator network and the voltage at Pin VMDO. When active, the VMID buffer provides the needed bias currents. When the buffer is disabled, an external voltage is required at Pin VMDO to provide the bias currents. For example, for a single 5 V application, a reference such as the ADR43 and a stable op amp provide an adequate 2.5 V VMDO source. 4. LOGIC INTERFACES All logic pins use the same interfaces and, therefore, have the same behavior and thresholds. The interface contains a Schmitt trigger type input with a threshold at about 1.1 V and a hysteresis of ±0.2 V. Therefore, the logic low is between ground and 0.8 V, and logic high is from 1.4 V to VPOS. Because the threshold is so low, the logic interfaces can be driven directly from 1.8 V or 3.3 V CMOS. The input bias current is nominally 0.2 μA when the applied voltage is 3.3 V and 18 nA when grounded. POWER-UP/POWER-DOWN SEQUENCE For glitch-free power-up operation, the following power-up and power-down sequence is recommended: 1. 2. Enable the bias by pulling the ENBL pin high. Maintain GNS0 to GNS3 and TXEN at ground. It is assumed that after the part wakes up from sleep mode, the receive section (preamplifier and DGA) needs to be Rev. 0 | Page 24 of 32 AD8260 APPLICATIONS INFORMATION The AD8260 is ideally suited for compact applications requiring high frequency and large current drive of complex modulation products. Because the driver is capable of providing up to 300 mA (using a 3.3 V supply rail) to very low impedance loads, undefined network impedances are of little consequence. Such applications can include, but are not limited to, local power line wiring found in homes or in automobiles, or low impedance complex filters used in communications. Pulse response performance with loading effects are illustrated by various curves in the Typical Performance Characteristics section. Figure 65 is an application block diagram showing AD8260 devices configured as transceivers in a small local network. In this figure, consider a small security system consisting of a master controller and four satellite cameras. For example, the master can be a processor-controlled switch that routes data to and from local satellite cameras. The cameras video signals are modulated for transmission over an existing power system such as the wiring found in homes or small businesses. Using the existing power network in this way eliminates the need to install additional cabling, thereby saving cost. Portability is also achieved because the system can be moved to other locations should the need arise, simply by unplugging a satellite and moving it elsewhere. The AD8260 transceivers perform the same function at the master and slave locations; a high frequency current-output DAC converts digital-to-analog data for the high current driver for transmission over a low impedance load. The input of the VGA/preamplifier connects to the same load, functioning as the receiver. In such a system, multiple AD8260 devices are connected to form a network, much like a LAN, except using the power-line wiring in a home or automobile in lieu of a CAT-5 cable, for example. CONTROLLER MICROPROCESSOR + MODULATOR DAC ADC AD8260 COUPLING LOCAL POWER WIRING COUPLING COUPLING AD8260 DAC ADC SATELLITE CAMERAS AD8260 DAC ADC MICROPROCESSOR + MODULATOR MICROPROCESSOR + MODULATOR 07192-065 CAMERA CAMERA Figure 65. AD8260 Transceiver Application Figure 66 shows the AD8260 as a low distortion, high power driver. The VGA and high current driver are combined by simply connecting the differential output of the VGA directly to the input of the driver. AD8260 VGA/ HIGH CURRENT PREAMPLIFIER DRIVER COMPLEX LOW Z FILTER ≥10Ω Figure 66. AD8260 Used as a VGA Driving a Low Impedance Load Rev. 0 | Page 25 of 32 07192-066 DAC AD8260 EVALUATION BOARD Analog Devices provides evaluation boards to customers as a support service so that the circuit designer can become familiar with the device in the most efficient way possible. The AD8260 evaluation board provides a fast, easy, and convenient means to assess the performance of the AD8260 before going through the inconvenience and expense of design and layout of a custom board. The board is shipped fully assembled and tested and provides basic functionality as shipped. Connectors enable the user to connect standard types of lab test equipment without having to wait for the rest of the design to be completed. Figure 67 shows a digital image of the top view and Figure 70 shows the schematic. PCB artwork for all conductor and silkscreen layers is shown in Figure 71 through Figure 76. A description of a typical test setup is explained in the Connecting the Evaluation Board section. The artwork can be used as a guide in circuit layout and parts placement. This is particularly useful for multiple function circuits with many pins, requiring multiple passive components. The board is shipped with the device fully enabled. Moving the ENABLE jumper to its upper position on the board disables the device. When the TX_EN jumper is in its upper position, the high current driver is disabled. Figure 67. Top View of the AD8260-EVALZ Rev. 0 | Page 26 of 32 07192-067 AD8260 CONNECTING THE EVALUATION BOARD Figure 69 shows an evaluation board with typical test connections. The various pieces of test equipment are representative, and equivalent equipment may be substituted. The AD8260 includes two amplifier channels: a high current driver and a digitally controlled VGA that is independently enabled. The slide switch labeled ENABLE functions as the chip enable, the GNSx switches permit the preamplifier/VGA to operate, and the TX_EN switch enables the high current driver. These independent enable functions permit the device to operate in a send or listen mode when used as a transceiver. The high current driver features differential inputs and is optimally driven by a differential signal source. The input signal is monitored at the 2-pin header labeled INP, using a differential probe such as the Tektronix P6247 (not shown). Two 49.9 Ω resistors are provided (R12 and R13), either for terminating coaxial cables from a signal generator or to be used as load resistors for a DAC with a current source output. An optional external load resistor is connected at the SMA connector TXOP and the output signal monitored at the 2-pin header labeled TXOP_1. As shipped, the gain of the high current driver is 1.5×, its default value. The internal differential network with resistor values of 1 kΩ and 1.5 kΩ establishes this value. Other values of gain are realized by connecting external resistors to the device at Pin 23, Pin 24, Pin 27, Pin 28, and Pin 31, as shown in Figure 68, which shows the internal structure for the default gain and how the gain can be modified. DEFAULT GAIN SETTING COMPONENTS ARE SHOWN IN BLACK, OPTIONAL COMPONENTS ARE SHOWN IN GRAY. VMDO 1 1.5kΩ VOCM INPP 32 31 INRP 30 1kΩ + TXOP 24 23 1.5kΩ 27 TXOP – INRN INPN 29 28 1kΩ TXFB CCOMP Figure 68. Gain-Setting Resistors of the High Current Driver The VGA/preamplifier is completely independent of the high current driver and features a single-ended input at the SMA connector PRAI. The input signal is monitored at the header VPRE_IN. The output is monitored at the 2-pin header VGA_OUT. The gain bits, GNS0 through GNS3, must be set before the VGA/preamplifier can operate. Table 4 lists the binary gain codes. The board is shipped with both enables (ENBL and TXEN) engaged and the gain-code switches adjusted for maximum DGA gain (1011). Resistor R5 and Resistor R6 establish the preamplifier gain and are 100 Ω as shipped for a noninverting preamplifier gain of 2×. Rev. 0 | Page 27 of 32 07192-068 AD8260 PULSE GENERATOR WITH DIFFERENTIAL OUTPUT HIGH CURRENT DRIVER INPUTS +5 V -5 V VGA OUTPUT (TO SCOPE) RLOAD HIGH CURRENT DRIVER OUTPUT SINGLEENDED VGA INPUT POWER SUPPLY Figure 69. Typical Evaluation Board Connections Rev. 0 | Page 28 of 32 07192-057 FUNCTION GENERATOR FOR VGA INPUT AD8260 INRP R12 49.9Ω INRN R13 49.9Ω C8 0.1µF C3 + 10µF +VS GND –VS C4 10µF C9 0.1µF +VS –VS + C19 0.1µF INR INP C18 0.1µF GND1 GND2 GND3 GND4 GND5 GND6 R 18 R17 R 15 R14 OR CCOMP R7 0Ω C14 0.1µF R21 0Ω 31 IN PP L7 120nH FB C1 0.1µF C2 0.1µF –VS R9 0Ω C17 0.1µF TXOP VMDO R 16 TX _ OP 32 VPSB EN TX_EN DIS L1 120 nH FB VPS EN ENABLE DIS VGAP R1 453Ω C23 0.1µF 8 VMDI VPSB C13 0.1µF TXEN 1 2 3 4 5 ENBL C15 0.1µF 6 7 30 I NR P 29 IN R N 28 I NP N 27 TXFB 26 VN EG 25 VNEG TXOP TXOP VPOS 24 23 22 21 20 19 PRAI 18 17 R6 100Ω R5 100Ω C10 0.1µF C7 0.1µF C11 0.1µF R10 49.9Ω C12 0.1µF PREAMP_IN C6 0.1µF C5 0.1µF L6 120nH FB L5 120nH FB VOCM VMDO TXEN VMDI VNCM VPSB ENBL VGAP + VS U1 AD8260 VPOS VPSR VMDO PRAI PR AO VPS R GN S3 GN S2 GN S1 VNGR C10 0.1µF VGA _ OUT 9 GN S0 VGAN FDBK VNGR 16 10 11 12 13 14 15 R2 453Ω VGAN L2 120nH FB L3 120nH FB PRAO R11 453Ω PRAO H R19 0Ω R4 C16 0.1µF GNS1 GNS0 L R20 0Ω R3 C20 0.1µF –VS +VS GNS2 L4 120nH FB C22 0.1µF GNS3 Figure 70. AD8260 Evaluation Board—Schematic Diagram Rev. 0 | Page 29 of 32 07192-070 –VS AD8260 Figure 71. AD8260-EVALZ Component Side Assembly 07192-071 Figure 73. AD8260-EVALZ Secondary Side Copper 07192-060 Figure 72. AD8260-EVALZ Component Side Copper Figure 74. AD8260-EVALZ Power Plane Rev. 0 | Page 30 of 32 07192-062 07192-061 AD8260 Figure 75. AD8260-EVALZ Ground Plane 07192-063 Figure 76. Component Side Silkscreen Rev. 0 | Page 31 of 32 07192-064 AD8260 OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 24 32 1 PIN 1 INDICATOR 2.85 2.70 SQ 2.55 PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 EXPOSED PAD (BOT TOM VIEW) 17 16 98 0.20 MIN 3.50 REF THE EXPOSED PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. THE GROUND PLANE PATTERN SHOULD INCLUDE A PATTERN OF VIAS TO INNER LAYERS. 032807-A 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.25 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 77. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-8) Dimensions shown in millimeters ORDERING GUIDE Model AD8260ACPZ-R71 AD8260ACPZ-RL1 AD8260ACPZ-WP1 AD8260-EVALZ1 1 Temperature −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Package Option CP-32-8 CP-32-8 CP-32-8 Z = RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07192-0-5/08(0) Rev. 0 | Page 32 of 32