AD8306AR-REEL7

a 5 MHz–400 MHz 100 dB High Precision Limiting-Logarithmic Amplifier AD8306 FEATURES Complete, Fully Calibrated Log-Limiting IF Amplifier 100 dB Dynamic Range: –91 dBV to +9 dBV Stable RSSI Scaling Over Temperature and Supplies: 20 mV/dB Slope, –95 dBm Intercept ⴞ0.4 dB RSSI Linearity up to 200 MHz Programmable Limiter Gain and Output Current Differential Outputs to 10 mA, 2.4 V p-p Overall Gain 90 dB, Bandwidth 400 MHz Constant Phase (Typical ⴞ56 ps Delay Skew) Single Supply of +2.7 V to +6.5 V at 16 mA Typical Fully Differential Inputs, RIN = 1 k⍀, C IN = 2.5 pF 500 ns Power-Up Time, 4.5 V. For frequencies in the range 10 MHz to 200 MHz these high drive levels are easily achieved using a matching network. Using such a network, having an inductor at the input, the input transient is eliminated. voltage sensitivity. Most interfaces have additional small junction capacitances associated with them, due to active devices or ESD protection; these may be neither accurate nor stable. Component numbering in each of these interface diagrams is local. Enable Interface The chip-enable interface is shown in Figure 20. The current in R1 controls the turn-on and turn-off states of the band-gap reference and the bias generator, and is a maximum of 100 µA when Pin 8 is taken to 5 V. Left unconnected, or at any voltage below 1 V, the AD8306 will be disabled, when it consumes a sleep current of much less than 1 µA (leakage currents only); when tied to the supply, or any voltage above 2 V, it will be fully enabled. The internal bias circuitry requires approximately 300 ns for either OFF or ON, while a delay of some 6 µs is required for the supply current to fall below 10 µA. Limiter Output Interface The simplified limiter output stage is shown in Figure 22. The bias for this stage is provided by a temperature-stable reference voltage of nominally 400 mV which is forced across the external resistor RLIM connected from Pin 9 (LMDR, or limiter drive) by a special op amp buffer stage. The biasing scheme also introduces a slight “lift” to this voltage to compensate for the finite current gain of the current source Q3 and the output transistors Q1 and Q2. A maximum current of 10 mA is permissible (RLIM = 40 Ω). In special applications, it may be desirable to modulate the bias current; an example of this is provided in the Applications section. Note that while the bias currents are temperature stable, the ac gain of this stage will vary with temperature, by –6 dB over a 120°C range. ENBL R1 60kV TO BIAS ENABLE 1.3kV 50kV A pair of supply and temperature stable complementary currents is generated at the differential output LMHI and LMLO (Pins 12 and 13), having a square wave form with rise and fall times of typically 0.6 ns, when load resistors of 50 Ω are used. The voltage at these output pins may swing to 1.2 V below the supply voltage applied to VPS2 (Pin 15). 4kV COMM Figure 20. Enable Interface Because of the very high gain bandwidth product of this amplifier considerable care must be exercised in using the limiter outputs. The minimum necessary bias current and voltage swings should be used. These outputs are best utilized in a fully-differential mode. A flux-coupled transformer, a balun, or an output matching network can be selected to transform these voltages to a single-sided form. Equal load resistors are recommended, even when only one output pin is used, and these should always be returned to the same well decoupled node on the PC board. When the AD8306 is used only to generate an RSSI output, the limiter should be completely disabled by omitting RLIM and strapping LMHI and LMLO to VPS2. Input Interface Figure 21 shows the essentials of the signal input interface. The parasitic capacitances to ground are labeled CP; the differential input capacitance, CD, mainly due to the diffusion capacitance of Q1 and Q2. In most applications both input pins are accoupled. The switch S closes when Enable is asserted. When disabled, the inputs float, bias current IE is shut off, and the coupling capacitors remain charged. If the log amp is disabled for long periods, small leakage currents will discharge these capacitors. If they are poorly matched, charging currents at power-up can generate a transient input voltage which may block the lower reaches of the dynamic range until it has become much less than the signal. VPS1 3.65kV CC INHI SIGNAL INPUT CC INLO 1.725V RIN = 1kV 67V 3.65kV IB = 15mA CD 2.5pF 1.3kV TO STAGES 1 THRU 5 67V S 1.78V VPS2 Q1 RIN = 3kV 1.725V Q1 4e Q2 4e 400mV Q2 20e OA ZERO-TC Q3 2.6kV 2.6kV GAIN BIAS 1.26V (TOP-END DETECTORS) CP LMLO 1.3kV FROM FINAL LIMITER STAGE TO 2ND STAGE 20e LMHI CP 130V 1.3kV 1.3kV COM1 3.4mA PTAT LMDR COMM RLIM Figure 22. Limiter Output Interface Figure 21. Signal Input Interface RSSI Output Interface In most applications, the input signal will be single-sided, and may be applied to either Pin 4 or 5, with the remaining pin accoupled to ground. Under these conditions, the largest input signal that can be handled is –3 dBV (sine amplitude of 1 V) when operating from a 3 V supply; a +3 dBV input may be The outputs from the ten detectors are differential currents, having an average value that is dependent on the signal input level, plus a fluctuation at twice the input frequency. The currents are summed at the internal nodes LGP and LGN shown in Figure 23. A further current IT is added to LGP, to position –8– REV. A AD8306 range: a 60 Hz hum, picked up due to poor grounding techniques; spurious coupling from digital logic on the same PC board; a strong EMI source; etc. the intercept to –108 dBV, by raising the RSSI output voltage for zero input, and to provide temperature compensation, resulting in a stable intercept. For zero signal conditions, all the detector output currents are equal. For a finite input, of either polarity, their difference is converted by the output interface to a singlesided voltage nominally scaled 20 mV/dB (400 mV per decade), at the output VLOG (Pin 16). This scaling is controlled by a separate feedback stage, having a tightly controlled transconductance. A small uncertainty in the log slope and intercept remains (see Specifications); the intercept may be adjusted (see Applications). Very careful shielding is essential to guard against such unwanted signals, and also to minimize the likelihood of instability due to HF feedback from the limiter outputs to the input. With this in mind, the minimum possible limiter gain should be used. Where only the logarithmic amplifier (RSSI) function is required, the limiter should be disabled by omitting RLIM and tying the outputs LMHI and LMLO directly to VPS2. A good ground plane should be used to provide a low impedance connection to the common pins, for the decoupling capacitor(s) used at VPS1 and VPS2, and at the output ground. Note that COM2 is a special ground pin serving just the RSSI output. VPS2 SUMMED 1.3kV DETECTOR OUTPUTS LGP 1.3kV CURRENT MIRROR ISOURCE >50mA ON DEMAND The four pins labeled PADL tie down directly to the metallic lead frame, and are thus connected to the back of the chip. The process on which the AD8306 is fabricated uses a bonded-wafer technique to provide a silicon-on-insulator isolation, and there is no junction or other dc path from the back side to the circuitry on the surface. These paddle pins must be connected directly to the ground plane using the shortest possible lead lengths to minimize inductance. FLTR C1 3.5pF LGN IT 3.3kV VLOG 250ms 3.3kV ISINK FIXED 1mA CF VLOG 20mV/dB 125mA COMM TRANSCONDUCTANCE DETERMINES SLOPE Figure 23. Simplified RSSI Output Interface The RSSI output bandwidth, fLP, is nominally 3.5 MHz. This is controlled by the compensation capacitor C1, which may be increased by adding an external capacitor, CF, between FLTR (Pin 10) and VLOG (Pin 16). An external 33 pF will reduce fLP to 350 kHz, while 360 pF will set it to 35 kHz, in each case with an essentially one-pole response. In general, the relationships (for fLP in MHz) are: CF = 12.7 × 10–10 – 3.5 pF ; f LP f LP = 12.7 × 10−6 C F + 3.5 pF (1) Using a load resistance of 50 Ω or greater, and at any temperature, the peak output voltage may be at least 2.4 V when using a supply of 4.5 V, and at least 2.1 V for a 3 V supply, which is consistent with the maximum permissible input levels. The incremental output resistance is approximately 0.3 Ω at low frequencies, rising to 1 Ω at 150 kHz and 18 Ω at very high frequencies. Basic Connections for Log (RSSI) Output Figure 24 shows the connections required for most applications. The AD8306 is enabled by connecting ENBL to VPS1. The device is put into the sleep mode by grounding this pin. The inputs are ac-coupled by C1 and C2, which normally should have the same value (CC). The input is, in this case, terminated with a 52.3 Ω resistor that combines with the AD8306’s input resistance of 1000 Ω to give a broadband input impedance of 50 Ω. Alternatively an input matching network can be used (see Input Matching section). R1 10V The output is unconditionally stable with load capacitance, but it should be noted that while the peak sourcing current is over 100 mA, and able to rapidly charge even large capacitances, the internally provided sinking current is only 1 mA. Thus, the fall time from the 2 V level will be as long as 2 µs for a 1 nF load. This may be reduced by adding a grounded load resistance. 1 COM2 VLOG 16 2 VPS1 VPS2 15 3 PADL PADL 14 0.1mF C1 0.01mF C2 0.01mF The AD8306 exhibits very high gain from 1 MHz to over 1 GHz, at which frequency the gain of the main path is still over 65 dB. Consequently, it is susceptible to all signals, within this very broad frequency range, that find their way to the input terminals. It is important to remember that these are quite indistinguishable from the “wanted” signal, and will have the effect of raising the apparent noise floor (that is, lowering the useful dynamic range). Therefore, while the signal of interest may be an IF of, say, 200 MHz, any of the following could easily be larger than this signal at the lower extremities of its dynamic VS (2.7V TO 6.5V) R2 10V RSSI 0.1mF AD8306 RT 52.3V SIGNAL INPUTS USING THE AD8306 REV. A The voltages at the two supply pins should not be allowed to differ greatly; up to 500 mV is permissible. It is desirable to allow VPS1 to be slightly more negative than VPS2. When the primary supply is greater than 2.7 V, the decoupling resistors R1 and R2 (Figure 24) may be increased to improve the isolation and lower the dissipation in the IC. However, since VPS2 supports the RSSI load current, which may be large, the value of R2 should take this into account. ENABLE 4 INHI LMHI 13 5 INLO LMLO 12 6 PADL PADL 11 7 COM1 FLTR 10 8 ENBL LMDR 9 CF (OPTIONAL SEE TEXT) Figure 24. Basic Connections for RSSI (Log) Output The 0.01 µF coupling capacitors and the resulting 50 Ω input impedance give a high-pass corner frequency of around 600 kHz. (1/(2 π RC)), where C = (C1)/2. In high frequency applications, this corner frequency should be placed as high as possible, to minimize the coupling of unwanted low frequency signals. In –9– AD8306 low frequency applications, a simple RC network forming a lowpass filter should be added at the input for the same reason. If the limiter output is not required, Pin 9 (LMDR) should be left open and Pins 12 and 13 (LMHI, LMLO) should be tied to VPS2 as shown in Figure 24. Figure 25 shows the output versus the input level in dBV, for sine inputs at 10 MHz, 50 MHz and 100 MHz (add 13 to the dBV number to get dBm Re 50 Ω. Figure 26 shows the typical logarithmic linearity (log conformance) under the same conditions. For example, for an input level of –33 dBV (–20 dBm), the output voltage will be VOUT = 0.02 V/dB × (–33 dBV – (–108 dBV)) = 1.5 V 100MHz 2 RSSI OUTPUT – V 50MHz 10MHz 1.5 1 0.5 Output Response Time and CF –100 –80 –60 –40 –20 INPUT LEVEL – dBV 0 20 The RSSI output has a low-pass corner frequency of 3.5 MHz, which results in a 10% to 90% rise time of 73 ns. For low frequency applications, the corner frequency can be reduced by adding an external capacitor, CF, between FLTR (Pin 10) and VLOG (Pin 16) as shown in Figure 24. For example, an external 33 pF will reduce the corner frequency to 350 kHz, while 360 pF will set it to 35 kHz, in each case with an essentially one-pole response. Figure 25. RSSI Output vs. Input Level at TA = +25 °C for Frequencies of 10 MHz, 50 MHz and 100 MHz 5 DYNAMIC RANGE 61dB 63dB 10MHz 86 93 50MHz 90 97 100MHz 96 100 4 3 Using the Limiter ERROR – dB 2 Figure 27 shows the basic connections for operating the limiter and the log output concurrently. The limiter output is a pair of differential currents of magnitude, IOUT, from high impedance (open-collector) sources. These are converted to equal-amplitude voltages by supply-referenced load resistors, RLOAD. The limiter output current is set by RLIM, the resistor connected between Pin 9 (LMDR) and ground. The limiter output current is set according the equation: 1 100MHz 0 10MHz –1 50MHz –2 –3 –4 –5 –120 (3) The most widely used convention in RF systems is to specify power in dBm, that is, decibels above 1 mW in 50 Ω. Specification of log amp input level in terms of power is strictly a concession to popular convention; they do not respond to power (tacitly “power absorbed at the input”), but to the input voltage. The use of dBV, defined as decibels with respect to a 1 V rms sine wave, is more precise, although this is still not unambiguous because waveform is also involved in the response of a log amp, which, for a complex input (such as a CDMA signal) will not follow the rms value exactly. Since most users specify RF signals in terms of power—more specifically, in dBm/50 Ω—we use both dBV and dBm in specifying the performance of the AD8306, showing equivalent dBm levels for the special case of a 50 Ω environment. Values in dBV are converted to dBm re 50 Ω by adding 13. 2.5 0 –120 where VOUT is the demodulated and filtered RSSI output, VSLOPE is the logarithmic slope, expressed in V/dB, PIN is the input signal, expressed in decibels relative to some reference level (either dBm or dBV in this case) and PO is the logarithmic intercept, expressed in decibels relative to the same reference level. IOUT = –400 mV/RLIM –100 –80 –60 –40 –20 INPUT LEVEL – dBV 0 20 (5) and has an absolute accuracy of ± 5%. Figure 26. Log Linearity vs. Input Level at TA = +25 °C, for Frequencies of 10 MHz, 50 MHz and 100 MHz The supply referenced voltage on each of the limiter pins will thus be given by: VLIM = VS –400 mV × RLOAD/RLIM Transfer Function in Terms of Slope and Intercept (6) The transfer function of the AD8306 is characterized in terms of its Slope and Intercept. The logarithmic slope is defined as the change in the RSSI output voltage for a 1 dB change at the input. For the AD8306 the slope is calibrated to be 20 mV/dB. The intercept is the point at which the extrapolated linear response would intersect the horizontal axis. For the AD8306 the intercept is calibrated to be –108 dBV (–95 dBm). Using the slope and intercept, the output voltage can be calculated for any input level within the specified input range using the equation: VOUT = VSLOPE × (PIN – PO) (2) –10– REV. A AD8306 R1 10V 1 COM2 VLOG 16 0.1mF C1 0.01mF C2 0.01mF ENABLE RSSI 0.1mF 2 VPS1 VPS2 15 3 PADL PADL 14 AD8306 RT 52.3V SIGNAL INPUTS VS (2.7V TO 6.5V) R2 10V 0.01mF RLOAD 4 INHI LMHI 13 5 INLO LMLO 12 6 PADL PADL 11 7 COM1 FLTR 10 NC RLIM (SEE TEXT) LMDR 9 8 ENBL RL 0.01mF LIMITER OUTPUT NC = NO CONNECT Figure 27. Basic Connections for Operating the Limiter will be a contribution from the input noise current. Thus, the total noise will be reduced by a smaller factor. The intercept at the primary input will be lowered to –121 dBV (–108 dBm). Impedance matching and drive balancing using a flux-coupled transformer is useful whenever broadband coupling is required. However, this may not always be convenient. At high frequencies, it will often be preferable to use a narrow-band matching network, as shown in Figure 28, which has several advantages. First, the same voltage gain can be achieved, providing increased sensitivity, but now a measure of selectively is simultaneously introduced. Second, the component count is low: two capacitors and an inexpensive chip inductor are needed. Third, the network also serves as a balun. Analysis of this network shows that the amplitude of the voltages at INHI and INLO are quite similar when the impedance ratio is fairly high (i.e., 50 Ω to 1000 Ω). Depending on the application, the resulting voltage may be used in a fully balanced or unbalanced manner. It is good practice to retain both load resistors, even when only one output pin is used. These should always be returned to the same well decoupled node on the PC board (see layout of evaluation board). The unbalanced, or single-sided mode, is more inclined to result in instabilities caused by the very high gain of the signal path. The limiter current may be set as high as 10 mA (which requires RLIM to be 40 Ω) and can be optionally increased somewhat beyond this level. It is generally inadvisable, however, to use a high bias current, since the gain of this wide bandwidth signal path is proportional to the bias current, and the risk of instability is elevated as RLIM is reduced (recommended value is 400 Ω). However, as the size of RLOAD is increased, the bandwidth of the limiter output decreases from 585 MHz for RLOAD = RLIM = 50 Ω to 50 MHz for RLOAD = RLIM = 400 Ω (bandwidth = 210 MHz for RLOAD = RLIM = 100 Ω and 100 MHz for RLOAD = RLIM = 200 Ω). As a result, the minimum necessary limiter output level should be chosen while maintaining the required limiter bandwidth. For RLIM = RLOAD = 50 Ω, the limiter output is specified for input levels between –78 dBV (–65 dBm) and +9 dBV (+22 dBm). The output of the limiter may be unstable for levels below –78 dBV (–65 dBm). However, keeping RLIM above 100 Ω will make instabilities on the output less likely for input levels below –78 dBV. A transformer or a balun (e.g., MACOM part number ETC1-1-13) can be used to convert the differential limiter output voltages to a single-ended signal. VS 10V VLOG 16 1 COM2 0.1mF ZIN RSSI 0.1mF C1 = CM 2 VPS1 VPS2 15 3 PADL PADL 14 AD8306 4 INHI LMHI 13 5 INLO LMLO 12 6 PADL PADL 11 7 COM1 FLTR 10 NC RLIM LMDR 9 LIMITER OUTPUT LM C2 = CM 8 ENBL NC = NO CONNECT Figure 28. High Frequency Input Matching Network Figure 29 shows the response for a center frequency of 100 MHz. The response is down by 50 dB at one-tenth the center frequency, falling by 40 dB per decade below this. The very high frequency attenuation is relatively small, however, since in the limiting case it is determined simply by the ratio of the AD8306’s input capacitance to the coupling capacitors. Table I provides solutions for a variety of center frequencies fC and matching from impedances ZIN of nominally 50 Ω and 100 Ω. Exact values are shown, and some judgment is needed in utilizing the nearest standard values. 14 13 Input Matching The choice of turns ratio will depend somewhat on the frequency. At frequencies below 30 MHz, the reactance of the input capacitance is much higher than the real part of the input impedance. In this frequency range, a turns ratio of 2:9 will lower the effective input impedance to 50 Ω while raising the input voltage by 13 dB. However, this does not lower the effect of the short circuit noise voltage by the same factor, since there 12 11 GAIN 10 DECIBELS Where either a higher sensitivity or a better high frequency match is required, an input matching network is valuable. Using a flux-coupled transformer to achieve the impedance transformation also eliminates the need for coupling capacitors, lowers any dc offset voltages generated directly at the input, and usefully balances the drives to INHI and INLO, permitting full utilization of the unusually large input voltage capacity of the AD8306. REV. A 10V 9 8 7 6 5 4 INPUT AT TERMINATION 3 2 1 0 –1 60 70 80 90 100 110 120 FREQUENCY – MHz 130 140 150 Figure 29. Response of 100 MHz Matching Network –11– AD8306 Step 2: Calculate CO and LO Table I. Match to 50 ⍀ (Gain = 13 dB) CM LM pF nH fC MHz 10 10.7 15 20 21.4 25 30 35 40 45 50 60 80 100 120 150 200 250 300 350 400 450 500 140 133 95.0 71.0 66.5 57.0 47.5 40.7 35.6 31.6 28.5 23.7 17.8 14.2 11.9 9.5 7.1 5.7 4.75 4.07 3.57 3.16 2.85 Now having a purely resistive input impedance, we can calculate the nominal coupling elements CO and LO, using Match to 100 ⍀ (Gain = 10 dB) CM LM pF nH 3500 3200 2250 1660 1550 1310 1070 904 779 682 604 489 346 262 208 155 104 75.3 57.4 45.3 36.7 30.4 25.6 100.7 94.1 67.1 50.3 47.0 40.3 33.5 28.8 25.2 22.4 20.1 16.8 12.6 10.1 8.4 6.7 5.03 4.03 3.36 2.87 2.52 2.24 2.01 CO = 4790 4460 3120 2290 2120 1790 1460 1220 1047 912 804 644 448 335 261 191 125 89.1 66.8 52.1 41.8 34.3 28.6 (R IN RM ) (R IN RM ) 2 πfC (8) Step 3: Split CO Into Two Parts Since we wish to provide the fully-balanced form of network shown in Figure 28, two capacitors C1 = C2 each of nominally twice CO, shown as CM in the figure, can be used. This requires a value of 14.24 pF in this example. Under these conditions, the voltage amplitudes at INHI and INLO will be similar. A somewhat better balance in the two drives may be achieved when C1 is made slightly larger than C2, which also allows a wider range of choices in selecting from standard values. For example, capacitors of C1 = 15 pF and C2 = 13 pF may be used (making CO = 6.96 pF). Step 4: Calculate LM The matching inductor required to provide both LIN and LO is just the parallel combination of these: LM = LINLO/(LIN + LO) (9) With LIN = 1 µH and LO = 356 nH, the value of LM to complete this example of a match of 50 Ω at 100 MHz is 262.5 nH. The nearest standard value of 270 nH may be used with only a slight loss of matching accuracy. The voltage gain at resonance depends only on the ratio of impedances, as is given by For other center frequencies and source impedances, the following method can be used to calculate the basic matching parameters.  R  R  GAIN = 20 log  IN  = 10 log  IN   R   RS   S  Step 1: Tune Out CIN At a center frequency fC, the shunt impedance of the input capacitance CIN can be made to disappear by resonating with a temporary inductor LIN, whose value is given by (7) when CIN = 2.5 pF. For example, at fC = 100 MHz, LIN = 1 µH. 2 πfC ; LO = For the AD8306, RIN is 1 kΩ. Thus, if a match to 50 Ω is needed, at fC = 100 MHz, CO must be 7.12 pF and LO must be 356 nH. General Matching Procedure LIN = 1/{(2 π fC)2CIN} = 1010/fC2 1 Altering the Logarithmic Slope Simple schemes can be used to increase and decrease the logarithmic slope as shown in Figure 30. For the AD8306, only power, ground and logarithmic output connections are shown; refer to Figure 24 for complete circuitry. In Figure 30(a), the op amp’s gain of +2 increases the slope to 40 mV/dB. In Figure 30(b), the AD8031 buffers a resistive divider to give a slope of +5V 0.1mF 10V 10V 0.1mF (10) +5V 0.1mF 10V 10V 10V 0.1mF 0.1mF VPS1 VPS2 VPS1 VPS2 10V VLOG VLOG AD8031 AD8306 PADL, COM1, COM2 40mV/dB 5kV 0.1mF AD8306 5kV PADL, COM1, COM2 5kV AD8031 10mV/dB 5kV (a) (b) Figure 30. Altering the Logarithmic Slope –12– REV. A AD8306 10 mV/dB The AD8031 rail-to-rail op amp, used in both examples, can swing from 50 mV to 4.95 mV on a single +5 V supply. If high output current is required (> 10 mA), the AD8051, which also has rail-to-rail capability but can deliver up to 45 mA of output current, can be used. VS 10V 10V 1 COM2 VLOG 16 RSSI 0.1mF 2 VPS1 VPS2 15 3 PADL PADL 14 0.1mF 0V TO +1V AD8306 APPLICATIONS The AD8306 is a versatile and easily applied log-limiting amplifier. Being complete, it can be used with very few external components, and most applications can be accommodated using the simple connections shown in the preceding section. A few examples of more specialized applications are provided here. 4 INHI LMHI 13 5 INLO LMLO 12 6 PADL PADL 11 7 COM1 FLTR 10 8 ENBL LMDR 9 The AD8306 can generate a fairly large output power at its differential limiter output interface. This may be coupled into a 50 Ω grounded load using the narrow-band coupling network following similar lines to those provided for input matching. Alternatively, a flux-linked transformer, having a center-tapped primary, may be used. Even higher output powers can be obtained using emitter-followers. In Figure 31, the supply voltage to the AD8306 is dropped from 5 V to about 4.2 V, by the diode. This increases the available swing at each output to about 2 V. Taking both outputs differentially, a square wave output of 4 V p-p can be generated. IN914 +5V APPROX. 4.2V RLOAD 10V 1 COM2 RSSI VLOG 16 0.1mF 0.1mF 2 VPS1 VPS2 15 3 PADL PADL 14 RLOAD SET RL = 5*RLIM AD8306 4 INHI LMHI 13 5 INLO LMLO 12 5V TO 3V 6 PADL PADL 11 DIFFERENTIAL OUTPUT = 4V pk-pk 7 COM1 FLTR 10 8 ENBL LMDR 9 3V TO 5V RLIM 2N3904 AD8031 1.8kV 18V Figure 32. Variable Limiter Output Programming Effect of Waveform Type on Intercept The AD8306 fundamentally responds to voltage and not to power. A direct consequence of this characteristic is that input signals of equal rms power, but differing crest factors, will produce different results at the log amp’s output. The effect of differing signal waveforms is to shift the effective value of the log amp’s intercept. Graphically, this looks like a vertical shift in the log amp’s transfer function. The device’s logarithmic slope however is not affected. For example, consider the case of the AD8306 being alternately fed by an unmodulated sine wave and by a single CDMA channel of the same rms power. The AD8306’s output voltage will differ by the equivalent of 3.55 dB (71 mV) over the complete dynamic range of the device (the output for a CDMA input being lower). Table II shows the correction factors that should be applied to measure the rms signal strength of a various signal types. A sine wave input is used as a reference. To measure the rms power of a square wave, for example, the mV equivalent of the dB value given in the table (20 mV/dB times 3.01 dB) should be subtracted from the output voltage of the AD8306. Table II. Shift in AD8306 Output for Signals with Differing Crest Factors Figure 31. Increasing Limiter Output Voltage When operating at high output power levels and high frequencies, very careful attention must be paid to the issue of stability. Oscillation is likely to be observed when the input signal level is low, due to the extremely high gain-bandwidth product of the AD8306 under such conditions. These oscillations will be less evident when signal-balancing networks are used, operating at frequencies below 200 MHz, and they will generally be fully quenched by the signal at input levels of a few dB above the noise floor. Signal Type Sine Wave Square Wave or DC Triangular Wave GSM Channel (All Time Slots On) CDMA Channel (Forward Link, 9 Channels On) CDMA Channel (Reverse Link) PDC Channel (All Time Slots On) Gaussian Noise Modulated Limiter Output The limiter output stage of the AD8306 also provides an analog multiplication capability: the amplitude of the output square wave can be controlled by the current withdrawn from LMDR (Pin 9). An analog control input of 0 V to +1 V is used to generate an exactly-proportional current of 0 mA to 10 mA in the npn transistor, whose collector is held at a fixed voltage of ∼400 mV by the internal bias in the AD8306. When the input signal is above the limiting threshold, the output will then be a squarewave whose amplitude is proportional to the control bias. REV. A 8.2kV VARIABLE OUTPUT 0mA TO 10mA High Output Limiter Loading 10V 0.1mF Correction Factor (Add to Output Reading) 0 dB –3.01 dB +0.9 dB +0.55 dB +3.55 dB +0.5 dB +0.58 dB +2.51 dB Evaluation Board An evaluation board, carefully laid out and tested to demonstrate the specified high speed performance of the AD8306 is available. Figure 33 shows the schematic of the evaluation board, which fairly closely follows the basic connections schematic shown in Figure 27. For ordering information, please refer to the Ordering Guide. Links, switches and component settings for different setups are described in Table III. –13– AD8306 R3 0V R2 10V +VS C1 0.01mF SIG INHI C3 0.1mF R1 0V 2 VPS1 VPS2 15 PADL 14 AD8306 C2 0.01mF B 4 INHI LMHI 13 5 INLO LMLO 12 6 PADL PADL 11 7 COM1 FLTR 10 8 ENBL LMDR 9 R5 10V R6 50V C4 0.1mF C7 (OPEN) R7 50V +VS C5 0.01mF L1 (OPEN) R12 0V R11 0V C6 0.01mF LK1 A EXT ENABLE VLOG 16 3 PADL R10 52.3V SIG INLO 1 COM2 VRSSI R4 (OPEN) R8 402V R9 (OPEN) SW1 Figure 33. Evaluation Board Schematic Table III. Evaluation Board Setup Options Component Function Default Condition SW1 Device Enable. When in Position A, the ENBL pin is connected to +VS and the AD8306 is in normal operating mode. In Position B, the ENBL pin is connected to an SMA connector labeled Ext Enable. A signal can be applied to this connector to enable/disable the AD8306. SW1 = A R1 This pad is used to ac-couple INLO to ground for single-ended input drive. To drive the AD8306 differentially, R1 should be removed. R1 = 0 Ω R/L, C1, C2 Input Interface. The 52.3 Ω resistor in position R10, along with C1 and C2, create a high-pass input filter whose corner frequency (640 kHz) is equal to 1/(2πRC), where C = (C1)/2 and R is the parallel combination of 52.3 Ω and the AD8306’s input impedance of 1000 Ω. Alternatively, the 52.3 Ω resistor can be replaced by an inductor to form an input matching network. See Input Matching Network section for more details. R10 = 52.3 Ω C1 = C2 = 0.01 µF R3/R4 Slope Adjust. A simple slope adjustment can be implemented by adding a resistive divider at the VLOG output. R3 and R4, whose sum should be about 1 kΩ, and never less than 40 Ω (see specs), set the slope according to the equation: Slope = 20 mV/dB × R4/(R3 + R4). R3 = 0 Ω R4 = ⬁ L1, C5, C6 Limiter Output Coupling. C5 and C6 ac-couple the limiter’s differential outputs. By adjusting these values and installing an inductor in L1, an output matching network can be implemented. To convert the limiter’s differential output to singleended, R11 and R12 (nominally 0 Ω) can be replaced with a surface mount balun such as the ETC1-1-13 (Macom). The balun can be grounded by soldering a 0 Ω into Position R9 (nominally open). L1 = Open C5 = 0.01 µF C6 = 0.01 µF R9 = Open R10 = R11 = 0 Ω R8, LK1 Limiter Output Current. With LK1 installed, R8 enables and sets the limiter output current. The limiter’s output current is set according to the equation (IOUT = 400 mV/R8). The limiter current can be as high as 10 mA (R8 = 40 Ω). To disable the limiter (recommended if the limiter is not being used), LK1 should be removed. LK1 Installed. R8 = 402 Ω R6, R7 (Limited Load Resistors) = 50 Ω C7 RSSI Bandwidth Adjust. The addition of C7 (farads) will lower the RSSI bandwidth of C7 = Open the VLOG output according to the equation: fCORNER (Hz) = 12.7 × 10–6/(C7 + 3.5 × 10–12). –14– REV. A AD8306 Figure 34. Layout of Signal Layer Figure 36. Signal Layer Silkscreen Figure 35. Layout of Power Layer REV. A Figure 37. Power Layer Silkscreen –15– AD8306 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3592a–9–8/99 16-Lead Narrow Body SO (SO-16) 0.3937 (10.00) 0.3859 (9.80) PIN 1 16 9 1 8 0.050 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) 3 458 0.0099 (0.25) 88 0.0192 (0.49) SEATING 0.0099 (0.25) 08 0.0500 (1.27) 0.0138 (0.35) PLANE 0.0160 (0.41) 0.0075 (0.19) PRINTED IN U.S.A. 0.1574 (4.00) 0.1497 (3.80) –16– REV. A