AD8392AACPZ-RL

Low Power, High Output Current, Quad Op Amp, Dual-Channel ADSL/ADSL2+ Line Driver AD8392A Data Sheet VEE 1 28 GND PD0 1, 2 2 27 NIC PD1 1, 2 3 26 NIC +VIN1 4 25 +VIN2 –VIN1 5 24 –VIN2 VOUT1 6 23 VOUT2 VCC 7 AD8392A 22 NIC NIC 8 21 VCC VOUT3 TOP VIEW (Not To Scale) 9 20 VOUT4 19 –VIN4 1 –VIN3 10 2 3 +VIN3 11 4 18 +VIN4 NIC 12 17 PD1 3, 4 NIC 13 16 PD0 3, 4 GND 14 15 VEE NOTES 1. NIC = NO INTERNAL CONNECTION. 2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GROUND PLANE. 06477-001 PIN CONFIGURATIONS +VIN2 VCOM1, 2 NIC ADSL/ADSL2+ CO line drivers XDSL line drivers GND +VIN1 APPLICATIONS VEE Figure 1. AD8392AARE, 28-Lead TSSOP_EP PD0 1, 2 Four current feedback, high current amplifiers Ideal for use as ADSL/ADSL2+ dual-channel central office (CO) line drivers Low power operation Power supply operation from ±5 V (+10 V) up to ±12 V (+24 V) Less than 3 mA/amp quiescent supply current for full power ADSL/ADSL2+ CO applications (20.4 dBm line power, 5.5 CF) Three active power modes plus shutdown High output voltage and current drive 500 mA peak output drive current 42.6 V p-p differential output voltage Low distortion −93 dBc @1 MHz second harmonic −103 dBc @ 1 MHz third harmonic High speed: 515 V/μs differential slew rate Additional functionality of AD8392AACP On-chip, common-mode voltage generation PD1 1, 2 FEATURES 32 31 30 29 28 27 26 25 NIC 1 1 –VIN1 2 22 VOUT2 VOUT1 3 The AD8392A is available in two thermally enhanced packages, a 28-lead TSSOP_EP (AD8392AARE) and a 5 mm × 5 mm, 32-lead LFCSP (AD8392AACP). Four bias modes are available via the use of two digital bits (PD1, PD0). AD8392A VCC 4 21 NIC TOP VIEW (Not to Scale) NIC 5 20 VCC 19 VOUT4 VOUT3 6 –VIN3 7 3 4 NIC 8 18 –VIN4 17 NIC +VIN4 PD1 3, 4 PD0 3, 4 VEE GND VCOM3, 4 10 11 12 13 14 15 16 NIC 9 +VIN3 The AD8392A is comprised of four high output current, low power consumption, operational amplifiers. It is particularly well suited for the CO driver interface in digital subscriber line systems, such as ADSL and ADSL2+. The driver is capable of providing enough power to deliver 20.4 dBm to a line, while compensating for losses due to hybrid insertion and back termination resistors. NIC 23 –VIN2 NOTES 1. NIC = NO INTERNAL CONNECTION. 2. EXPOSED PAD. CONNECT THE EXPOSED PAD TO GROUND PLANE. 06477-002 GENERAL DESCRIPTION 24 2 Figure 2. AD8392AACP, 5 mm × 5 mm, 32-Lead LFCSP Additionally, the AD8392AACP provides VCOM pins for on-chip, common-mode voltage generation. The low power consumption, high output current, high output voltage swing, and robust thermal packaging enable the AD8392A to be used as the CO line drivers in ADSL and other xDSL systems. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8392A Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Applications........................................................................................8  Applications ....................................................................................... 1  Supplies, Grounding, and Layout ................................................8  General Description ......................................................................... 1  Power Management ......................................................................8  Pin Configurations ........................................................................... 1  Thermal Considerations...............................................................8  Revision History ............................................................................... 2  Typical ADSL/ADSL2+ Application ...........................................9  Specifications..................................................................................... 3  Multitone Power Ratio ............................................................... 10  Absolute Maximum Ratings............................................................ 4  Outline Dimensions ....................................................................... 11  Thermal Resistance ...................................................................... 4  Ordering Guide .......................................................................... 11  ESD Caution .................................................................................. 4  Notes................................................................................................. 12  Typical Performance Characteristics ............................................. 5  Theory of Operation ........................................................................ 7  REVISION HISTORY 6/2016—Rev. 0 to Rev. A Changed CP-32-2 to CP-32-7 ...................................... Throughout Change to Applications Section, Figure 1, and Figure 2 ............. 1 Updated Outline Dimensions ....................................................... 12 Changes to Ordering Guide .......................................................... 12 10/2006—Revision 0: Initial Version Rev. A | Page 2 of 12 Data Sheet AD8392A SPECIFICATIONS VS = ±12 V or +24 V, RL = 100 Ω, G = +5, PD = (0, 0), T = 25°C, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Peaking Slew Rate NOISE/DISTORTION PERFORMANCE Second Harmonic Distortion Third Harmonic Distortion Multitone Input Power Ratio Voltage Noise (RTI) +Input Current Noise −Input Current Noise INPUT CHARACTERISTICS RTI Offset Voltage +Input Bias Current −Input Bias Current Input Resistance Input Capacitance Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Differential Output Voltage Swing Single-Ended Output Voltage Swing Linear Output Current POWER SUPPLY Operating Range (Dual Supply) Operating Range (Single Supply) Total Quiescent Current PD1, PD0 = (0, 0) PD1, PD0 = (0, 1) PD1, PD0 = (1, 0) PD1, PD0 = (1, 1) (Shutdown State) PD = 0 Threshold PD = 1 Threshold +Power Supply Rejection Ratio −Power Supply Rejection Ratio Min Typ 25 23 −4 63 41.2 20.6 Unit Test Conditions/Comments 37 30 0.06 515 MHz MHz dB V/µs VOUT = 0.1 V p-p, RF = 2 kΩ VOUT = 4 V p-p, RF = 2 kΩ VOUT = 0.1 V p-p, RF = 2 kΩ VOUT = 20 V p-p, RF = 2 kΩ −93 −103 70 2.5 7.6 12.5 dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz fC = 1 MHz, VOUT = 2 V p-p fC = 1 MHz, VOUT = 2 V p-p 26 kHz to 2.2 MHz, ZLINE = 100 Ω differential load f = 10 kHz f = 10 kHz f = 10 kHz mV µA µA MΩ pF dB V+IN − V−IN V p-p V p-p mA ΔVOUT ΔVOUT, RL = 50 Ω RL = 10 Ω, fC = 100 kHz ±2 2 3 8 1 66 +4 7 10 42.6 21.3 500 ±5 10 5.8 3.0 2.6 0.4 1.8 72 65 Max 74 69 ±12 24 V V 6.5 3.5 3.0 0.08 0.8 mA/amp mA/amp mA/amp mA/amp V V dB dB Rev. A | Page 3 of 12 (ΔVOS, DM (RTI))/(ΔVIN, CM) ΔVOS, DM (RTI)/ΔVCC, ΔVCC = ±1 V ΔVOS, DM (RTI)/ΔVEE, ΔVEE = ±1 V AD8392A Data Sheet ABSOLUTE MAXIMUM RATINGS Rating ±13 V (+26 V) See Figure 3 −65°C to +150°C −40°C to +85°C 300°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. In single supply with RL to VS−, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing θJA. In addition, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the LFCSP-32 and TSSOP_EP packages on a JEDEC standard 4-layer board. θJA values are approximations. 7 TJ = 150°C THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, θJA is specified for the device soldered in the circuit board for surface-mount packages. Table 3. Package Type LFCSP-32 (CP) TSSOP_EP (RE) θJA 27.27 35.33 Unit °C/W °C/W 6 5 LFCSP-32 4 TSSOP-28/EP 3 2 1 0 –40 –30 –20 –10 Maximum Power Dissipation 0 10 20 30 40 50 TEMPERATURE (°C) 60 70 80 90 06477-003 Parameter Supply Voltage Power Dissipation Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering 10 sec) Junction Temperature RMS output voltages should be considered. If RL is referenced to VS− as in single-supply operation, the total power is VS × IOUT. MAXIMUM POWER DISSIPATION (W) Table 2. Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming that the load (RL) is midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). See the Thermal Considerations section for additional thermal design guidance. ESD CAUTION Rev. A | Page 4 of 12 Data Sheet AD8392A TYPICAL PERFORMANCE CHARACTERISTICS 0 900 850 SIGNAL FEEDTHROUGH (dB) POWER CONSUMPTION (mW) –20 800 PD (0, 0) 750 700 PD (0, 1) 650 PD (1, 0) 600 550 –40 –60 –80 –100 16 17 19 18 20 21 OUTPUT POWER (dBm) –120 100k 1M 10M 100M 1G FREQUENCY (Hz) Figure 4. Power Consumption vs. Output Power (138 kHz to 2.2 MHz), ADSL/ADSL2+ Circuit (Figure 15), VS = ±12 V, RLOAD = 100 Ω, CF = 5.5 Figure 7. Signal Feedthrough vs. Frequency VS = ±12 V, G = +5, VIN = 800 mV p-p, PD (1, 1), RF = 2 kΩ 15 10 PD (0, 0) GAIN (dB) 5 PD (0, 1) 0 2 –5 PD (1, 0) –10 1 100k 1M 10M 1G 100M FREQUENCY (Hz) CH1 500mV CH2 500mV 100ns 06477-042 –20 10k 06477-049 –15 Figure 8. Power-Up Time: PD (1, 1) to PD (0, 0) VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 1 V p-p, RF = 2 kΩ Figure 5. Small Signal Frequency Response VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 100 mV p-p, RF = 2 kΩ 15 10 PD (0, 0) 0 2 –5 PD (0, 1) –10 1 PD (1, 0) –20 10k 100k 1M 10M 100M FREQUENCY (Hz) 1G CH1 500mV CH2 500mV 400ns Figure 9. Power-Down Time: PD (0, 0) to PD (1, 1) VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 1 V p-p, RF = 2 kΩ Figure 6. Large Signal Frequency Response VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 4 V p-p, RF = 2 kΩ Rev. A | Page 5 of 12 06477-041 –15 06477-045 GAIN (dB) 5 06477-048 450 15 06477-046 500 AD8392A Data Sheet 100 OUTPUT IMPEDANCE (Ω) OUTPUT CHANNEL 2 CH1 200mV CH2 2V 06477-040 2 400ns 10 PD (0, 0) 1 PD (0, 1) PD (1, 0) 0.1 0.01 10k 100k 1M 10M 1G 100M FREQUENCY (Hz) Figure 13. Output Impedance vs. Frequency VS = ±12 V, G = +5, RF = 2 kΩ Figure 10. Output Overdrive Recovery, ADSL/ADSL2+ Circuit (Figure 15), DMT Waveform, VS = ±12 V 0 –10 –20 CROSSTALK (dB) –30 49.9Ω DIFF CHANNEL 1, 2 –40 –50 2kΩ DIFF CHANNEL 3, 4 –60 100Ω 499Ω 2kΩ –70 –80 1M 100M 10M FREQUENCY (Hz) 49.9Ω 06477-025 –100 100k 06477-053 –90 Figure 14. Dual Differential Driver Circuit Figure 11. Crosstalk vs. Frequency, Dual Differential Driver Circuit (Figure 14), VS = ±12 V, VIN = 800 mV p-p 45 1.78kΩ 35 0.01µF 634Ω 4.99Ω 30 77Ω VCM 1µF 20 77Ω 15 87Ω 100Ω 2kΩ 4.99Ω 0.01µF 634Ω 0 10 20 30 40 50 60 70 80 LOAD RESISTANCE (Ω) 90 100 Figure 12. Differential Output Swing vs. RLOAD Dual Differential Driver Circuit (Figure 14) 1.78kΩ Figure 15. ADSL/ADSL2+ Circuit Rev. A | Page 6 of 12 06477-021 10 87Ω 2kΩ 25 06477-054 DIFFERENTIAL OUTPUT (V p-p) 40 06477-047 INPUT CHANNEL 1 Data Sheet AD8392A THEORY OF OPERATION Of course, for a real amplifier there are additional poles that contribute excess phase, and there is a value for RF below which the amplifier is unstable. Tolerance for peaking and desired flatness determines the optimum RF in each application. RF The open-loop transimpedance is analogous to the open-loop voltage gain of a voltage feedback amplifier. Figure 16 shows a simplified model of a current feedback amplifier. Because RIN is proportional to 1/gm, the equivalent voltage gain is TZ × gm, where gm is the transconductance of the input stage. Basic analysis of the follower with gain circuit yields RG RIN IIN VIN Figure 16. Simplified Block Diagram The AD8392A is capable of delivering 500 mA of output current while swinging to within 2 V of either power supply rail. The AD8392A also has a power management system included on-chip. It features four user-programmable power levels (three active power modes as well as the provision for complete shutdown). where: RIN = VOUT RN VO TZ (S ) = G× VIN TZ (S ) + G × RIN + RF G =1+ TZ 06477-022 The AD8392A is a current feedback amplifier with high (500 mA) output current capability. With a current feedback amplifier, the current into the inverting input is the feedback signal, and the open-loop behavior is that of a transimpedance, dVO/dIIN or TZ. RF RG 1 ≈ 50 Ω gm Because G ×  RIN