AD8512ARZ

Precision, Very Low Noise, Low Input Bias Current, Wide Bandwidth JFET Operational Amplifiers AD8510/AD8512/AD8513 Date Sheet PIN CONFIGURATIONS 8 NC NULL 1 7 V+ –IN 2 TOP VIEW 6 OUT (Not to Scale) V– 4 5 NULL NC = NO CONNECT Figure 1. 8-Lead MSOP (RM Suffix) OUT A 1 –IN A 2 V– 4 AD8512 8 V+ 7 OUT B TOP VIEW 6 –IN B (Not to Scale) 5 +IN B NC 7 +IN 3 02729-003 NC = NO CONNECT 8 AD8510 V+ TOP VIEW 6 OUT (Not to Scale) V– 4 5 NULL +IN 3 +IN A 3 Instrumentation Multipole filters Precision current measurement Photodiode amplifiers Sensors Audio AD8510 Figure 2. 8-Lead SOIC_N (R Suffix) OUT A 1 –IN A 2 Figure 3. 8-Lead MSOP (RM Suffix) +IN A 3 V– 4 AD8512 8 V+ 7 OUT B TOP VIEW 6 –IN B (Not to Scale) 5 +IN B Figure 4. 8-Lead SOIC_N (R Suffix) OUT A 1 14 OUT D OUT A 1 14 OUT D –IN A 2 13 –IN D –IN A 2 13 –IN D +IN A 3 12 +IN D +IN A 3 12 +IN D AD8513 9 –IN C 8 OUT C V+ 4 02729-005 –IN B 6 OUT B 7 AD8513 11 V– TOP VIEW +IN B 5 (Not to Scale) 10 +IN C 11 V– TOP VIEW +IN B 5 (Not to Scale) 10 +IN C V+ 4 02729-004 –IN 2 02729-002 APPLICATIONS NULL 1 02729-001 Fast settling time: 500 ns to 0.1% Low offset voltage: 400 μV maximum Low TCVOS: 1 μV/°C typical Low input bias current: 25 pA typical at VS = ±15 V Dual-supply operation: ±5 V to ±15 V Low noise: 8 nV/√Hz typical at f = 1 kHz Low distortion: 0.0005% No phase reversal Unity-gain stable Figure 5. 14-Lead SOIC_N (R Suffix) –IN B 6 9 –IN C OUT B 7 8 OUT C 02729-006 FEATURES Figure 6. 14-Lead TSSOP (RU Suffix) GENERAL DESCRIPTION The AD8510/AD8512/AD8513 are single-, dual-, and quadprecision JFET amplifiers that feature low offset voltage, input bias current, input voltage noise, and input current noise. The combination of low offsets, low noise, and very low input bias currents makes these amplifiers especially suitable for high impedance sensor amplification and precise current measurements using shunts. The combination of dc precision, low noise, and fast settling time results in superior accuracy in medical instruments, electronic measurement, and automated test equipment. Unlike many competitive amplifiers, the AD8510/ AD8512/AD8513 maintain their fast settling performance even with substantial capacitive loads. Unlike many older JFET amplifiers, the AD8510/AD8512/AD8513 do not suffer from output phase reversal when input voltages exceed the maximum common-mode voltage range. Rev. K Fast slew rate and great stability with capacitive loads make the AD8510/AD8512/AD8513 a perfect fit for high performance filters. Low input bias currents, low offset, and low noise result in a wide dynamic range of photodiode amplifier circuits. Low noise and distortion, high output current, and excellent speed make the AD8510/AD8512/AD8513 great choices for audio applications. The AD8510/AD8512 are both available in 8-lead narrow SOIC_N and 8-lead MSOP packages. MSOP-packaged devices are only available in tape and reel. The AD8513 is available in 14-lead SOIC_N and TSSOP packages. The AD8510/AD8512/AD8513 are specified over the −40°C to +125°C extended industrial temperature range. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2002–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD8510/AD8512/AD8513 Date Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Output Phase Reversal ............................................................... 14 Applications ....................................................................................... 1 Total Harmonic Distortion (THD) + Noise .............................. 14 Pin Configurations ........................................................................... 1 Total Noise Including Source Resistors ................................... 14 General Description ......................................................................... 1 Settling Time ............................................................................... 15 Revision History ............................................................................... 2 Overload Recovery Time .......................................................... 15 Specifications..................................................................................... 4 Capacitive Load Drive ............................................................... 15 Electrical Characteristics ............................................................. 5 Open-Loop Gain and Phase Response .................................... 16 Absolute Maximum Ratings............................................................ 7 Precision Rectifiers..................................................................... 17 ESD Caution .................................................................................. 7 I-V Conversion Applications .................................................... 18 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 20 General Application Information ................................................. 14 Ordering Guide .......................................................................... 21 Input Overvoltage Protection ................................................... 14 REVISION HISTORY 12/2018—Rev. J to Rev. K Change to 8-Lead SOIC_N (R) Parameter, Table 4 ..................... 7 6/2017—Rev. I to Rev. J Changes to Figure 14 Caption......................................................... 8 Deleted Figure 39; Renumbered Sequentially ............................ 12 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 2/2009—Rev. H to Rev. I Changes to Figure 25 ...................................................................... 10 Changes to Ordering Guide .......................................................... 20 10/2007—Rev. G to Rev. H Changes to Crosstalk Section........................................................ 18 Added Figure 58.............................................................................. 18 6/2007—Rev. F to Rev. G Changes to Figure 1 and Figure 2 ................................................... 1 Changes to Table 1 and Table 2 ....................................................... 3 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 6/2006—Rev. E to Rev. F Changes to Figure 23 ........................................................................ 9 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 6/2004—Rev. D to Rev. E Changes to Format ............................................................. Universal Changes to Specifications .................................................................3 Updated Outline Dimensions ....................................................... 19 10/2003—Rev. C to Rev. D Added AD8513 Model ....................................................... Universal Changes to Specifications .................................................................3 Added Figure 36 through Figure 40 ............................................. 10 Added Figure 55 and Figure 57 .................................................... 17 Changes to Ordering Guide .......................................................... 20 9/2003—Rev. B to Rev. C Changes to Ordering Guide ............................................................4 Updated Figure 2 ............................................................................ 10 Changes to Input Overvoltage Protection Section .................... 10 Changes to Figure 10 and Figure 11............................................. 12 Changes to Photodiode Circuits Section .................................... 13 Changes to Figure 13 and Figure 14............................................. 13 Deleted Precision Current Monitoring Section ......................... 14 Updated Outline Dimensions ....................................................... 15 3/2003—Rev. A to Rev. B Updated Figure 5 ............................................................................ 11 Updated Outline Dimensions ....................................................... 15 Rev. K | Page 2 of 21 Date Sheet AD8510/AD8512/AD8513 8/2002—Rev. 0 to Rev. A Added AD8510 Model ....................................................... Universal Added Pin Configurations ............................................................... 1 Changes to Specifications ................................................................. 2 Changes to Ordering Guide ............................................................. 4 Changes to TPC 2 and TPC 3 .......................................................... 5 Added TPC 10 and TPC 12 ............................................................. 6 Replaced TPC 20 ............................................................................... 8 Replaced TPC 27 ............................................................................... 9 Changes to General Application Information Section ...............10 Changes to Figure 5.........................................................................11 Changes to I-V Conversion Applications Section ......................13 Changes to Figure 13 and Figure 14 .............................................13 Changes to Figure 17 ......................................................................14 Rev. K | Page 3 of 21 AD8510/AD8512/AD8513 Date Sheet SPECIFICATIONS At VS = ±5 V, VCM = 0 V, TA = 25°C, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage (B Grade)1 Symbol Conditions Min VOS Typ Max Unit 0.08 0.4 0.8 0.9 1.8 75 0.7 7.5 50 0.3 0.5 mV mV mV mV pA nA nA pA nA nA −40°C < TA < +125°C Offset Voltage (A Grade) VOS 0.1 −40°C < TA < +125°C Input Bias Current IB 21 −40°C < TA < +85°C −40°C < TA < +125°C Input Offset Current IOS 5 −40°C < TA < +85°C −40°C < TA < +125°C Input Capacitance Differential Common Mode Input Voltage Range Common-Mode Rejection Ratio Large-Signal Voltage Gain Offset Voltage Drift (B Grade)1 Offset Voltage Drift (A Grade) OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Voltage High Output Voltage Low Output Voltage High Output Voltage Low Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier AD8510/AD8512/AD8513 AD8510/AD8512 AD8513 DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Settling Time Total Harmonic Distortion (THD) + Noise Phase Margin NOISE PERFORMANCE Voltage Noise Density Peak-to-Peak Voltage Noise 1 12.5 11.5 CMRR AVO ΔVOS/ΔT ΔVOS/ΔT VCM = −2.0 V to +2.5 V RL = 2 kΩ, VO = −3 V to +3 V VOH VOL VOH VOL VOH VOL IOUT RL = 10 kΩ RL = 10 kΩ, −40°C < TA < +125°C RL = 2 kΩ RL = 2 kΩ, −40°C < TA < +125°C RL = 600 Ω RL = 600 Ω, −40°C < TA < +125°C PSRR ISY VS = ±4.5 V to ±18 V SR GBP tS THD + N φM en en p-p −2.0 86 65 4.1 +2.5 100 107 0.9 1.7 ±40 4.3 −4.9 4.2 −4.9 4.1 −4.8 ±54 86 130 3.9 3.7 5 12 −4.7 −4.5 −4.2 pF pF V dB V/mV μV/°C μV/°C V V V V V V mA dB VO = 0 V −40°C < TA < +125°C −40°C < TA < +125°C 2.0 RL = 2 kΩ 20 8 0.4 0.0005 44.5 V/μs MHz μs % Degrees 34 12 8.0 7.6 2.4 nV/√Hz nV/√Hz nV/√Hz nV/√Hz μV p-p To 0.1%, 0 V to 4 V step, G = +1 1 kHz, G = +1, RL = 2 kΩ f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz 0.1 Hz to 10 Hz bandwidth AD8510/AD8512 only. Rev. K | Page 4 of 21 2.3 2.5 2.75 10 5.2 mA mA mA Date Sheet AD8510/AD8512/AD8513 ELECTRICAL CHARACTERISTICS At VS = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage (B Grade)1 Symbol Conditions Min VOS Typ Max Unit 0.08 0.4 0.8 mV mV 0.1 1.0 1.8 80 0.7 10 75 0.3 0.5 mV mV pA nA nA pA nA nA +13.0 pF pF V dB V/mV 5 12 μV/°C μV/°C −40°C < TA < +125°C Offset Voltage (A Grade) VOS −40°C < TA < +125°C Input Bias Current IB 25 −40°C < TA < +85°C −40°C < TA < +125°C Input Offset Current IOS 6 −40°C < TA < +85°C −40°C < TA < +125°C Input Capacitance Differential Common Mode Input Voltage Range Common-Mode Rejection Ratio Large-Signal Voltage Gain Offset Voltage Drift (B Grade)1 Offset Voltage Drift (A Grade) OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Voltage High Output Voltage Low Output Voltage High Output Voltage Low Output Current POWER SUPPLY Power Supply Rejection Ratio Supply Current/Amplifier AD8510/AD8512/AD8513 AD8510/AD8512 AD8513 DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product Settling Time Total Harmonic Distortion (THD) + Noise Phase Margin 12.5 11.5 CMRR AVO VCM = −12.5 V to +12.5 V RL = 2 kΩ, VCM = 0 V, VO = −13.5 V to +13.5 V −13.5 86 115 ΔVOS/ΔT ΔVOS/ΔT VOH VOL VOH VOL VOH VOL 1.0 1.7 RL = 10 kΩ RL = 10 kΩ, −40°C < TA < +125°C RL = 2 kΩ RL = 2 kΩ, −40°C < TA < +125°C RL = 600 Ω RL = 600 Ω, −40°C < TA < +125°C RL = 600 Ω RL = 600 Ω, −40°C < TA < +125°C +14.0 +13.8 +13.5 +11.4 SR GBP tS THD + N φM +14.2 −14.9 +14.1 –14.8 +13.9 −14.3 IOUT PSRR ISY 108 196 −14.6 −14.5 −13.8 −12.1 ±70 VS = ±4.5 V to ±18 V 86 dB VO = 0 V −40°C < TA < +125°C −40°C < TA < +125°C 2.2 RL = 2 kΩ 20 8 0.5 0.9 0.0005 52 To 0.1%, 0 V to 10 V step, G = +1 To 0.01%, 0 V to 10 V step, G = +1 1 kHz, G = +1, RL = 2 kΩ Rev. K | Page 5 of 21 V V V V V V V V mA 2.5 2.6 3.0 mA mA mA V/μs MHz μs μs % Degrees AD8510/AD8512/AD8513 Parameter NOISE PERFORMANCE Voltage Noise Density Peak-to-Peak Voltage Noise 1 Date Sheet Symbol Conditions en f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz 0.1 Hz to 10 Hz bandwidth en p-p AD8510/AD8512 only. Rev. K | Page 6 of 21 Min Typ 34 12 8.0 7.6 2.4 Max Unit 10 nV/√Hz nV/√Hz nV/√Hz nV/√Hz μV p-p 5.2 Date Sheet AD8510/AD8512/AD8513 ABSOLUTE MAXIMUM RATINGS Table 4. Thermal Resistance Table 3. Parameter Supply Voltage Input Voltage Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 10 sec) Electrostatic Discharge (Human Body Model) Rating ±18 V ±VS Observe derating curves −65°C to +150°C −40°C to +125°C −65°C to +150°C 300°C 2000 V Package Type 8-Lead MSOP (RM) 8-Lead SOIC_N (R) 14-Lead SOIC_N (R) 14-Lead TSSOP (RU) 1 θJA1 210 120 120 180 θJC 45 43 36 35 Unit °C/W °C/W °C/W °C/W θJA is specified for worst case conditions, that is, θJA is specified for device soldered in circuit board for surface-mount packages. ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. K | Page 7 of 21 AD8510/AD8512/AD8513 Date Sheet TYPICAL PERFORMANCE CHARACTERISTICS 120 100k VSY = ±15V TA = 25°C VSY = ±5V, ±15V INPUT BIAS CURRENT (pA) 80 60 40 10k 1k 100 20 02729-007 10 0 –0.5 –0.4 –0.3 –0.2 –0.1 0 0.1 0.2 0.3 0.4 1 –40 0.5 INPUT OFFSET VOLTAGE (mV) Figure 7. Input Offset Voltage Distribution 02729-010 NUMBER OF AMPLIFIERS 100 –25 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 125 Figure 10. Input Bias Current vs. Temperature 30 1000 VSY = ±15V B GRADE 20 15 10 02729-008 5 0 0 1 2 3 TCVOS (µV/°C) 4 5 100 ±15V 10 ±5V 1 0.1 –40 6 Figure 8. AD8510/AD8512 TCVOS Distribution 02729-011 INPUT OFFSET CURRENT (pA) NUMBER OF AMPLIFIERS 25 –25 –10 5 65 20 35 50 TEMPERATURE (°C) 80 95 110 125 Figure 11. Input Offset Current vs. Temperature 40 30 TA = 25°C VSY = ±15V A GRADE 35 INPUT BIAS CURRENT (pA) 15 10 5 0 0 1 2 3 TCVOS (µV/°C) 4 5 30 25 20 15 10 5 0 6 Figure 9. AD8510/AD8512 TCVOS Distribution 02729-012 20 02729-009 NUMBER OF AMPLIFIERS 25 8 13 18 23 SUPPLY VOLTAGE (V+ – V– ) 28 Figure 12. Input Bias Current vs. Supply Voltage Rev. K | Page 8 of 21 30 Date Sheet AD8510/AD8512/AD8513 2.8 TA = 25°C TA = 25°C 1.9 2.6 1.8 SUPPLY CURRENT (mA) 2.4 1.7 1.6 1.5 1.4 1.3 2.2 2.0 1.8 1.6 8 13 18 23 SUPPLY VOLTAGE (V+ – V–) 28 1.2 1.0 30 8 Figure 13. AD8512 Supply Current per Amplifier vs. Supply Voltage 28 33 70 VOL VSY = ±15V 315 VSY = ±15V RL = 2.5kΩ CSCOPE = 20pF ΦM = 52° 60 14 50 VOH 270 225 12 10 GAIN (dB) 8 40 180 30 135 20 90 10 45 6 VOL VSY = ±5V VOH 02729-039 2 0 0 20 10 30 40 50 LOAD CURRENT (mA) 0 0 4 60 70 –10 –45 –20 –90 –30 10k 80 2.50 2.25 2.25 SUPPLY CURRENT (mA) 2.50 ±15V 1.75 ±5V 1.50 1.25 –10 5 35 50 20 65 TEMPERATURE (°C) 80 95 ±15V 2.00 ±5V 1.75 1.50 1.25 02729-015 1.00 –40 –25 –135 50M 10M Figure 17. Open-Loop Gain and Phase vs. Frequency Figure 14. Output Voltage vs. Load Current 2.00 1M FREQUENCY (Hz) 100k 1.00 –40 –25 110 125 Figure 15. AD8512 Supply Current per Amplifier vs. Temperature 02729-018 OUTPUT VOLTAGE (V) 18 23 SUPPLY VOLTAGE (V+ – V–) Figure 16. AD8510 Supply Current vs. Supply Voltage 16 SUPPLY CURRENT PER AMPLIFIER (mA) 13 PHASE (Degrees) 1.0 –10 5 20 35 50 65 TEMPERATURE (°C) 80 95 110 Figure 18. AD8510 Supply Current vs. Temperature Rev. K | Page 9 of 21 125 02729-017 1.1 02729-016 1.4 1.2 02729-013 SUPPLY CURRENT PER AMPLIFIER (mA) 2.0 AD8510/AD8512/AD8513 Date Sheet 300 70 240 OUTPUT IMPEDANCE (Ω) 40 AV = 100 30 20 AV = 10 10 0 AV = 1 210 180 150 AV = 1 120 AV = 100 90 60 02729-019 –10 –20 10k 100k 1M FREQUENCY (Hz) 10M AV = 10 02729-022 CLOSED-LOOP GAIN (dB) 50 –30 1k VSY = ±15V VIN = 50mV 270 VSY = ±15V, ±5V 60 30 0 100 50M 1k 10k 1M 100k FREQUENCY (Hz) 10M 100M Figure 22. Output Impedance vs. Frequency Figure 19. Closed-Loop Gain vs. Frequency 1k 120 VSY = ±5V TO ±15V 100 CMRR (dB) 80 60 40 0 100 02729-020 20 1k 10k 100k 1M FREQUENCY (Hz) 10M 100 10 02729-023 VOLTAGE NOISE DENSITY (nV/ Hz) VSY = ±15V 1 1 100M 10 100 1k 10k FREQUENCY (Hz) Figure 20. CMRR vs. Frequency Figure 23. Voltage Noise Density vs. Frequency 120 VSY = ±15V VSY = ±5V, ±15V 100 VOLTAGE (1µV/DIV) 80 40 +PSRR 0 –20 100 02729-024 20 02729-021 PSRR (dB) –PSRR 60 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M TIME (1s/DIV) Figure 21. PSRR vs. Frequency Figure 24. 0.1 Hz to 10 Hz Input Voltage Noise Rev. K | Page 10 of 21 Date Sheet AD8510/AD8512/AD8513 280 90 VSY = ±5V TO ±15V SMALL-SIGNAL OVERSHOOT (%) 175 140 105 70 70 60 50 35 0 20 2 3 4 5 6 7 8 9 10 0 10 10 1 FREQUENCY (Hz) Figure 25. Voltage Noise Density vs. Frequency 10k 100 1k LOAD CAPACITANCE (pF) Figure 28. Small-Signal Overshoot vs. Load Capacitance 315 70 VSY = ±15V RL = 2kΩ CL = 100pF AV = 1 VSY = ±5V RL = 2.5kΩ CSCOPE = 20pF ΦM = 44.5° 60 VOLTAGE (5V/DIV) OPEN-LOOP GAIN (dB) 50 40 225 180 30 135 20 90 10 45 0 0 –10 02729-026 270 PHASE (Degrees) 1 –OS 30 –45 –90 –20 –30 10k 1M 100k TIME (1µs/DIV) 10M –135 50M FREQUENCY (Hz) Figure 26. Large-Signal Transient Response Figure 29. Open-Loop Gain and Phase vs. Frequency 120 VSY = ±5V VSY = ±15V RL = 2kΩ CL = 100pF AV = 1 100 CMRR (dB) VOLTAGE (50mV/DIV) 80 60 40 0 100 TIME (100ns/DIV) Figure 27. Small-Signal Transient Response 02729-030 02729-027 20 1k 10k 100k 1M FREQUENCY (Hz) Figure 30. CMRR vs. Frequency Rev. K | Page 11 of 21 10M 100M 02729-029 0 +OS 40 02729-028 210 02729-025 VOLTAGE NOISE DENSITY (nV Hz) VSY = ±15V RL = 2kΩ 80 245 AD8510/AD8512/AD8513 Date Sheet 300 VSY = ±5V RL = 2kΩ CL = 100pF AV = 1 VSY = ±5V VIN = 50mV 270 VOLTAGE (50mV/DIV) OUTPUT IMPEDANCE (Ω) 240 210 AV = 1 180 150 120 AV = 100 90 02729-031 AV = 10 30 0 100 1k 10k 100k 1M FREQUENCY (Hz) 02729-034 60 10M TIME (100ns/DIV) 100M Figure 31. Output Impedance vs. Frequency Figure 34. Small-Signal Transient Response 100 VSY = ±5V VSY = ±5V RL = 2kΩ 80 70 60 +OS 50 –OS 40 30 20 02729-035 02729-032 VOLTAGE (1µV/DIV) SMALL-SIGNAL OVERSHOOT (%) 90 10 0 TIME (1s/DIV) Figure 32. 0.1 Hz to 10 Hz Input Voltage Noise 10 1 10k 100 1k LOAD CAPACITANCE (pF) Figure 35. Small-Signal Overshoot vs. Load Capacitance 100 VSY = ±5V RL = 2kΩ CL = 100pF AV = 1 VS = ±15V 90 VOLTAGE (2V/DIV) NUMBER OF AMPLIFIERS 80 70 60 50 40 30 02729-036 02729-033 20 10 0 TIME (1µs/DIV) 0 1 2 3 4 TCVOS (µV/°C) Figure 33. Large-Signal Transient Response Figure 36. AD8513 TCVOS Distribution Rev. K | Page 12 of 21 5 6 Date Sheet AD8510/AD8512/AD8513 3.0 SUPPLY CURRENT PER AMPLIFIER (mA) VS = ±5V NUMBER OF AMPLIFIERS 100 80 60 40 02729-037 20 0 0 1 4 3 2 5 2.3 2.2 2.1 2.0 1.9 1.8 1.7 02729-038 SUPPLY CURRENT PER AMPLIFIER (mA) TA = 25°C 1.6 1.5 18 23 ±5V 1.5 1.0 0.5 –25 –10 5 20 35 50 65 80 95 110 125 Figure 39. AD8513 Supply Current per Amplifier vs. Temperature 2.5 13 2.0 TEMPERATURE (°C) Figure 37. AD8513 TCVOS Distribution 8 ±15V 0 –40 6 TCVOS (µV/°C) 2.4 2.5 02729-040 120 28 33 SUPPLY VOLTAGE (V+ – V–) Figure 38. AD8513 Supply Current per Amplifier vs. Supply Voltage Rev. K | Page 13 of 21 AD8510/AD8512/AD8513 Date Sheet GENERAL APPLICATION INFORMATION INPUT OVERVOLTAGE PROTECTION 0.01 VSY = ±5V RL = 100kΩ BW = 22kHz RS  5 mA With a very low offset current of > R2, the circuit behavior is not impacted by the effect of the junction resistance. The maximum signal bandwidth is f MAX  ft 2R2Ct where ft is the unity-gain frequency of the amplifier. Cf can be calculated by Cf  Ct 2R2 ft where ft is the unity-gain frequency of the op amp, and it achieves a phase margin, φM, of approximately 45°. A higher phase margin can be obtained by increasing the value of Cf. Setting Cf to twice the previous value yields approximately φM = 65° and a maximal flat frequency response, but it reduces the maximum signal bandwidth by 50%. Using the previous parameters with a Cf ≈ 1 pF, the signal bandwidth is approximately 2.6 MHz. VEE Signal Transmission Applications 4 Rd Ct 3 One popular signal transmission method uses pulse-width modulation. High data rates can require a fast comparator rather than an op amp. However, the need for sharp, undistorted signals can favor using a linear amplifier. 6 7 VCC Figure 52. Equivalent Preamplifier Photodiode Circuit A larger signal bandwidth can be attained at the expense of additional output noise. The total input capacitance (Ct) consists of the sum of the diode capacitance (typically 3 pF to 4 pF) and the amplifier’s input capacitance (12 pF), which includes external parasitic capacitance. Ct creates a pole in the frequency response that can lead to an unstable system. To ensure stability and optimize the bandwidth of the signal, a capacitor is placed in the feedback loop of the circuit shown in Figure 52. It creates a zero and yields a bandwidth whose corner frequency is 1/(2π(R2Cf)). The value of R2 can be determined by the ratio The AD8510/AD8512/AD8513 make excellent voltage comparators. In addition to a high slew rate, the AD8510/ AD8512/AD8513 have a very fast saturation recovery time. In the absence of feedback, the amplifiers are in open-loop mode (very high gain). In this mode of operation, they spend much of their time in saturation. The circuit shown in Figure 53 was used to compare two signals of different frequencies, namely a 100 Hz sine wave and a 1 kHz triangular wave. Figure 54 shows a scope plot of the resulting output waveforms. A pull-up resistor (typically 5 kΩ) can be connected from the output to VCC if the output voltage needs to reach the positive rail. The trade-off is that power consumption is higher. +15V V/ID where: V is the desired output voltage of the op amp. ID is the diode current. 3 2 For example, if ID is 100 μA and a 10 V output voltage is desired, R2 can be 100 kΩ. Rd (see Figure 52) is a junction resistance that drops typically by a factor of 2 for every 10°C increase in temperature. Rev. K | Page 18 of 21 V1 7 VOUT 4 –15V V2 6 02729-049 AD8510 02729-048 2 Figure 53. Pulse-Width Modulator Date Sheet AD8510/AD8512/AD8513 02729-050 VOLTAGE (5V/DIV) The AD8510 single has two additional active terminals that are not present on the AD8512 dual or AD8513 quad devices. These pins are labeled null and are used for fine adjustment of the input offset voltage. Although the guaranteed maximum offset voltage at room temperature is 400 μV and over the −40°C to +125°C range is 800 mV maximum, this offset voltage can be reduced by adding a potentiometer to the null pins as shown in Figure 57. With the 20 kΩ potentiometer shown, the adjustment range is approximately ±3.5 mV. The potentiometer parallels low value resistors in the drain circuit of the JFET differential input pair and allows unbalancing of the drain currents to change the offset voltage. If offset adjustment is not required, these pins must be left unconnected. TIME (2ms/DIV) Figure 54. Pulse-Width Modulation Crosstalk Crosstalk, also known as channel separation, is a measure of signal feedthrough from one channel to another on the same IC. The AD8512/AD8513 have a channel separation of better than −90 dB for frequencies up to 10 kHz and of better than −50 dB for frequencies up to 10 MHz. Figure 56 shows the typical channel separation behavior between Amplifier A (driving amplifier) and each of the following: Amplifier B, Amplifier C, and Amplifier D. VOUT Caution must be used when adding adjusting potentiometers to any op amp with this capability for several reasons. First, there is gain from these nodes to the output; therefore, capacitive coupling from noisy traces to these nodes injects noise into the signal path. Second, the temperature coefficient of the potentiometer does not match the temperature coefficient of the internal resistors, so the offset voltage drift with temperature is slightly affected. Third, this provision is for adjusting the offset voltage of the op amp, not for adjusting the offset of the overall system. Although it is tempting to decrease the value of the potentiometer to attain more range, this adversely affects the dc and ac parameters. Instead, increase the potentiometer to 50 kΩ to decrease the range if needed. 2.2kΩ 20kΩ 18V p-p 8 1 7 3 VIN CROSSTALK = 20 log – 5 5kΩ VOUT 10VIN 5kΩ + –VS 5 AD8510 3 4 7 6 OUTPUT VOS TRIM RANGE IS TYPICALLY ±3.5mV V– Figure 57. Optional Offset Nulling Circuit 0 –20 –40 –60 CH B CH D –80 CH C –100 –120 –140 02729-051 CHANNEL SEPARATION (dB) 2 INPUT 4 Figure 55. Crosstalk Test Circuit –160 100 V+ 1 6 02729-052 2 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 56. Channel Separation Rev. K | Page 19 of 21 02729-058 20kΩ +VS AD8510/AD8512/AD8513 Date Sheet OUTLINE DIMENSIONS 5.10 5.00 4.90 5.00 (0.1968) 4.80 (0.1890) 5 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 14 0.50 (0.0196) 0.25 (0.0099) 8 4.50 4.40 4.30 6.40 BSC 45° 1 8° 0° 7 PIN 1 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 0.65 BSC 1.05 1.00 0.80 1.20 MAX 0.15 0.05 012407-A 8 4.00 (0.1574) 3.80 (0.1497) 0.30 0.19 0.20 0.09 SEATING COPLANARITY PLANE 0.10 0.75 0.60 0.45 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB-1 Figure 58. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) Figure 60. 14-Lead Thin Shrink Small Outline Package [TSSOP] (RU-14) Dimensions shown in millimeters 3.20 3.00 2.80 3.20 3.00 2.80 8 1 5 8.75 (0.3445) 8.55 (0.3366) 5.15 4.90 4.65 4 4.00 (0.1575) 3.80 (0.1496) 8 14 1 7 6.20 (0.2441) 5.80 (0.2283) PIN 1 IDENTIFIER 0.95 0.85 0.75 0.25 (0.0098) 0.10 (0.0039) 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 COPLANARITY 0.10 0.80 0.55 0.40 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 0.25 (0.0098) 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) COMPLIANT TO JEDEC STANDARDS MS-012-AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 61. 14-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-14) Dimensions shown in millimeters and (inches) Figure 59. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. K | Page 20 of 21 45° 8° 0° 060606-A 1.27 (0.0500) BSC 0.65 BSC Date Sheet AD8510/AD8512/AD8513 ORDERING GUIDE Model1 AD8510ARMZ-REEL AD8510ARMZ AD8510ARZ AD8510ARZ-REEL AD8510ARZ-REEL7 AD8510BRZ AD8510BRZ-REEL AD8510BRZ-REEL7 AD8512ARMZ-REEL AD8512ARMZ AD8512ARZ AD8512ARZ-REEL AD8512ARZ-REEL7 AD8512BRZ AD8512BRZ-REEL AD8512BRZ-REEL7 AD8513ARZ AD8513ARZ-REEL AD8513ARZ-REEL7 AD8513ARUZ AD8513ARUZ-REEL 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead MSOP 8-Lead MSOP 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead SOIC_N 14-Lead TSSOP 14-Lead TSSOP Z = RoHS Compliant Part, # denotes RoHS compliant product may be top or bottom marked. ©2002–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02729-0-12/18(K) Rev. K | Page 21 of 21 Package Option RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 R-14 R-14 R-14 RU-14 RU-14 Marking Code B7A# B7A# B8A# B8A#