AD8570ACP-REEL

a 16 V Rail-to-Rail Buffer Amplifiers AD8568/AD8569/AD8570 FEATURES Single-Supply Operation: 4.5 V to 16 V Input Capability Beyond the Rails Rail-to-Rail Output Swing Continuous Output Current: 35 mA Peak Output Current: 250 mA Offset Voltage: 10 mV Max Slew Rate: 6 V/
s Stable with 1
F Loads Supply Current PIN CONFIGURATIONS 6-Lead SOT-23 (RT Suffix) OUT A 1 6 OUT B IN A 2 5 V+ GND 3 4 IN B TE 10-Lead MSOP (RM Suffix) APPLICATIONS LCD Reference Drivers Portable Electronics Communications Equipment OUT A 1 LE IN A B SO The AD8568, AD8569, and AD8570 are low-cost, single-supply buffer amplifiers with rail-to-rail input and output capability. They are optimized for LCD monitor applications and built on an advanced high voltage CBCMOS process. The AD8568 includes two buffers, the AD8569 includes four buffers, and the AD8570 includes eight buffers. O 2 AD8569 8 GND IN B 4 7 IN C OUT B 5 6 OUT C V+ 1 NC 2 IN C 3 IN D 4 IN E 5 IN F 6 NC 7 V+ 8 32-Lead LFCSP (CP Suffix) 24 GND 23 NC 22 OUT C 21 OUT D 20 OUT E 19 OUT F 18 NC 17 GND PIN 1 INDICATOR AD8570 NC 9 IN G 10 IN H 11 NC 12 NC 13 OUT H 14 OUT G 15 NC 16 TOP VIEW NC = NO CONNECT 20-Lead TSSOP 1 20 OUT 1 IN 2 2 19 OUT 2 IN 1 18 V– IN 3 4 AD8570-ARU 17 OUT 3 IN 4 5 TOP VIEW 16 OUT 4 IN 5 6 15 OUT 5 IN 6 7 14 OUT 6 V+ 8 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. IN D 3 V+ 3 REV. C 9 V+ These LCD buffers have high slew rates, 35 mA continuous output drive, and high capacitive load drive capability. They have a wide supply range and offset voltages below 10 mV. The AD8568, AD8569, and AD8570 are specified over the –40°C to +85°C temperature range. They are available on tape and reel, with the AD8568 packaged in a 6-lead SOT-23, the AD8569 in a 10-lead MSOP, and the AD8570 in a 32-lead LFCSP and 20-lead TSSOP. 10 OUT D 32 NC 31 IN B 30 IN A 29 NC 28 NC 27 OUT A 26 OUT B 25 NC GENERAL DESCRIPTION AD8568 13 V– IN 7 9 12 OUT 7 IN 8 10 11 OUT 8 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD8568/AD8569/AD8570–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (4.5 V ≤ V ≤ 16 V, V S CM = VS/2, TA = 25C, unless otherwise noted.) Parameter Symbol Conditions INPUT CHARACTERISTICS Offset Voltage Offset Voltage Drift Input Bias Current VOS ∆VOS/∆T IB –40°C ≤ TA ≤ +85°C Output Voltage Low Continuous Output Current Peak Output Current TRANSFER CHARACTERISTICS Gain VOH VOL IOUT IPK AVCL NL POWER SUPPLY Supply Voltage Power Supply Rejection Ratio Supply Current/Amplifier DYNAMIC PERFORMANCE Slew Rate Bandwidth Phase Margin Channel Separation O NOISE PERFORMANCE Voltage Noise Density Current Noise Density 2 5 80 10 –0.5 400 1 ZIN CIN IL = 100 µA VS = 16 V, IL = 5 mA –40°C ≤ TA ≤ +85°C VS = 4.5 V, IL = 5 mA –40°C ≤ TA ≤ +85°C IL = 100 µA VS = 16 V, IL = 5 mA –40°C ≤ TA ≤ +85°C VS = 4.5 V, IL = 5 mA –40°C ≤ TA ≤ +85°C VS PSRR ISY 15.85 15.75 4.2 4.1 RL = 2 kΩ –40°C ≤ TA ≤ +85°C RL = 2 kΩ, VO = 0.5 to (VS – 0.5 V) VS = 4 V to 17 V –40°C ≤ TA ≤ +85°C VO = VS/2, No Load –40°C ≤ TA ≤ +85°C SR BW Øo RL = 10 kΩ, CL = 200 pF –3 dB, RL = 10 kΩ, CL = 10 pF RL = 10 kΩ, CL = 10 pF en en in f = 1 kHz f = 10 kHz f = 10 kHz 4.38 95 0.995 0.995 4.5 70 4 150 250 300 400 35 250 0.9985 0.9980 0.01 90 700 Unit mV µV/°C 600 nA 800 nA –VS + 0.5 V kΩ pF VS – 0.005 15.95 5 42 VS = 16 V B SO Gain Linearity Max TE OUTPUT CHARACTERISTICS Output Voltage High Typ –40°C ≤ TA ≤ +85°C LE Input Voltage Range Input Impedance Input Capacitance Min V V V V V mV mV mV mV mV mA mA 1.005 1.005 V/V V/V % 16 V 850 1 dB µA mA 6 6 65 75 V/µs MHz Degrees dB 26 25 0.8 nV/√Hz nV/√Hz pA/√Hz Specifications subject to change without notice. –2– REV. C AD8568/AD8569/AD8570 ABSOLUTE MAXIMUM RATINGS* Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input Voltage . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VS + 0.5 V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Junction Temperature Range . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300°C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Package Type JA1 JC 6-Lead SOT-23 (RT) 10-Lead MSOP (RM) 20-Lead TSSOP (RU) 32-Lead LFCSP (CP) 250 200 72 35 140 44 45 JB2 Unit 13 °C/W °C/W °C/W °C/W NOTES 1 θJA is specified for worst-case conditions, i.e., θJA is specified for a device soldered onto a circuit board for surface-mount packages. 2 ⌿JB is applied for calculating the junction temperature by reference to the board temperature. TE ORDERING GUIDE Temperature Range Package Description Package Option Branding Information AD8568ART-R2 AD8568ART-REEL AD8568ART-REEL7 AD8569ARM-R2 AD8569ARM-REEL AD8569ARMZ-REEL* AD8570ACP-R2 AD8570ACP-REEL AD8570ACP-REEL7 AD8570ARU AD8570ARU-REEL –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 32-Lead LFCSP 32-Lead LFCSP 32-Lead LFCSP 20-Lead TSSOP 20-Lead TSSOP RT-6 RT-6 RT-6 RM-10 RM-10 RM-10 CP-32-2 CP-32-2 CP-32-2 RU-20 RU-20 AWA AWA AWA AXA AXA AXA B SO LE Model *Z = Pb-free part. O CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8568/AD8569/AD8570 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. C –3– WARNING! ESD SENSITIVE DEVICE AD8568/AD8569/AD8570 –Typical Performance Characteristics 0 100 TA = 25C 4.5V < VS < 16V 90 VCM = VS/2 50 VS = 16V INPUT BIAS CURRENT (nA) QUANTITY (Amplifiers) 80 70 60 50 40 30 100 150 VS = 4.5V 200 250 20 300 10 9 0 3 6 6 3 INPUT OFFSET VOLTAGE (mV) 9 350 12 TPC 1. Input Offset Voltage Distribution 4 200 150 100 0 0 10 B SO 50 20 30 40 50 60 TCVOS (
V/C) 70 80 90 100 TPC 2. Input Offset Voltage Drift Distribution OUTPUT VOLTAGE SWING (V) O INPUT OFFSET VOLTAGE (mV) VCM = VS /2 VS = 16V 0.75 1.00 VS = 4.5V 1.25 1.50 3 LE INPUT OFFSET CURRENT (nA) QUANTITY (Amplifiers) 250 0.50 85 5 4.5V < VS < 16V 0.25 25 TEMPERATURE (C) TPC 4. Input Bias Current vs. Temperature 300 0 40 TE 0 12 40 25 TEMPERATURE (C) 85 TPC 3. Input Offset Voltage vs. Temperature 2 1 VS = 4.5V 0 1 VS = 16V 2 3 4 5 40 25 TEMPERATURE (C) 85 TPC 5. Input Offset Current vs. Temperature 15.96 4.46 ILOAD = 5mA 15.95 4.45 VS = 16V 15.94 4.44 15.93 4.43 15.92 4.42 15.91 4.41 15.90 4.40 15.89 4.39 VS = 4.5V 4.38 15.88 15.87 4.37 15.86 4.36 40 25 TEMPERATURE (C) 85 TPC 6. Output Voltage Swing vs. Temperature –4– REV. C AD8568/AD8569/AD8570 150 0.80 ILOAD = 5mA VCM = VS /2 SUPPLY CURRENT/AMPLIFIER (mA) OUTPUT VOLTAGE SWING (mV) 135 120 105 90 VS = 4.5V 75 60 45 VS = 16V 30 0.75 VS = 16V 0.70 0.65 0.60 VS = 4.5V 0.55 15 40 25 TEMPERATURE (C) 0.50 85 TPC 7. Output Voltage Swing vs. Temperature 25 TEMPERATURE (C) 85 TPC 10. Supply Current/Amplifier vs. Temperature 0.9999 7 4.5V < VS < 16V VOUT = 0.5V TO 15V RL = 2k 6 VS = 16V 5 SLEW RATE (V/
s) LE GAIN ERROR (V/V) 40 TE 0 0.9997 VS = 4.5V 4 3 B SO 2 1 RL = 10k CL = 200pF RL = 600 0.9995 40 25 TEMPERATURE (C) 0 85 40 TPC 8. Voltage Gain vs. Temperature 1k 1.0 10 VS = 16V 1 TA = 25C AV = +1 VO = VS /2 0.9 SUPPLY CURRENT/AMPLIFIER (mA) O OUTPUT VOLTAGE (mV) VS = 4.5V 85 TPC 11. Slew Rate vs. Temperature TA = 25C 100 25 TEMPERATURE (C) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.1 0.001 0 0.01 0.1 1 LOAD CURRENT (mA) 10 100 2 4 6 8 10 12 SUPPLY VOLTAGE (V) 14 16 18 TPC 12. Supply Current/Amplifier vs. Supply Voltage TPC 9. Output Voltage to Supply Rail vs. Load Current REV. C 0 –5– AD8568/AD8569/AD8570 10 18 5 16 1k 0 14 OUTPUT SWING (V p-p) 10k 10 560 15 20 35 40 100k 0 1M 10M FREQUENCY (Hz) 10 100M 1k 10k 100k 1M 10M FREQUENCY (Hz) TPC 16. Closed-Loop Output Swing vs. Frequency 160 TA = 25C VS = 8V VIN = 50mV rms RL = 10k AV = +1 5 0 50pF 5 1040pF 10 100pF 20 25 100k B SO 15 540pF 1M 10M FREQUENCY (Hz) 500 450 400 350 O 300 VS = 4.5V 200 150 100 0 100 VS = 16V 1k 10k 100k FREQUENCY (Hz) 1M TA = 25C VS = 16V 120 100 80 +PSRR 60 40 PSRR 20 0 20 1k 10k 100k FREQUENCY (Hz) 1M 10M TPC 17. Power Supply Rejection Ratio vs. Frequency 250 50 140 40 100 100M TPC 14. Frequency Response vs. Capacitive Loading IMPEDANCE () 100 LE GAIN (dB) 10 TA = 25C VS = 16V AV = +1 RL = 10k DISTORTION < 1% 2 25 15 6 4 TPC 13. Frequency Response vs. Resistive Loading 20 8 TE 30 TA = 25C VS = 8V VIN = 50mV rms CL = 40pF AV = +1 10 POWER SUPPLY REJECTION RATIO (dB) 25 150 12 160 POWER SUPPLY REJECTION RATIO (dB) GAIN (dB) 5 140 TA = 25C VS = 4.5V 120 100 +PSRR 80 60 40 20 0 20 40 100 10M PSRR 1k 10k 100k FREQUENCY (Hz) 1M 10M TPC 18. Power Supply Rejection Ratio vs. Frequency TPC 15. Closed-Loop Output Impedance vs. Frequency –6– REV. C AD8568/AD8569/AD8570 1,000 100 16V TA = 25C VS = 4.5V VCM = 2.25V VIN = 100mV p-p AV = +1 RL = 10k 90 80 70 100 OVERSHOOT (%) VOLTAGE NOISE DENSITY (nV/ Hz) TA = 25C 4.5V VS 10 60 50 40 OS 30 +OS 20 10 1k 100 FREQUENCY (Hz) 0 10 10k TPC 19. Voltage Noise Density vs. Frequency 15 OUTPUT SWING FROM 0V TO V TA = 25C VS = 8V RL = 10k 10 LE 40 60 80 100 120 140 160 180 100 B SO CHANNEL SEPARATION (dB) TA = 25C 4.5V < VS < 16V 20 1k 10k 100k 1M FREQUENCY (Hz) 10M 5 5 UNDERSHOOT SETTLING TO 0.1% 10 15 0 100M 80 60 O OVERSHOOT (%) 70 50 40 30 OS 100 LOAD CAPACITANCE (pF) 0 TA = 25C VS = 16V AV = +1 RL = 10k CL = 300pF 0 0 0 0 0 0 0 1k 0 0 0 0 0 TIME (2
s/DIV) 0 0 TPC 24. Large Signal Transient Response TPC 21. Small Signal Overshoot vs. Load Capacitance REV. C 2.0 1.5 0 10 0 10 1.0 SETTLING TIME (
s) 0 +OS 20 0.5 TPC 23. Settling Time vs. Step Size VOLTAGE (3V/DIV) 90 TA = 25C VS = 16V VCM = 8V VIN = 100mV p-p AV = +1 RL = 10k OVERSHOOT SETTLING TO 0.1% 0 TPC 20. Channel Separation vs. Frequency 100 1k TPC 22. Small Signal Overshoot vs. Load Capacitance 20 0 100 LOAD CAPACITANCE (pF) TE 1 10 –7– 0 AD8568/AD8569/AD8570 0 0 TA = 25C VS = 4.5V AV = +1 RL = 10k CL = 300pF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIME (2
s/DIV) 0 0 0 0 0 TPC 25. Large Signal Transient Response 0 0 0 0 0 TIME (1
s/DIV) 0 0 0 TPC 27. Small Signal Transient Response 0 0 TA = 25C VS = 16V AV = +1 RL = 10k CL = 100pF 0 0 0 0 0 0 0 0 0 B SO 0 0 0 VOLTAGE (3V/DIV) 0 0 TA = 25C VS = 16V AV = +1 RL = 10k 0 LE 0 VOLTAGE (50mV/DIV) 0 TE VOLTAGE (1V/DIV) 0 TA = 25C VS = 4.5V AV = +1 RL = 10k CL = 100pF 0 VOLTAGE (50mV/DIV) 0 0 0 0 0 TIME (1
s/DIV) 0 0 0 0 0 0 0 0 0 0 TIME (40
s/DIV) 0 0 0 TPC 28. No Phase Reversal O TPC 26. Small Signal Transient Response 0 –8– REV. C AD8568/AD8569/AD8570 This family of buffers is designed to drive large capacitive loads in LCD applications. Each has high output current drive and railto-rail input/output operation and can be powered from a single 16 V supply. They are also intended for other applications where low distortion and high output current drive are needed. Figure 1 shows the maximum power dissipation versus temperature. To achieve proper operation, use the previous equation to calculate PDISS for a specific package at any given temperature, or see Figure 1. 1.00 MAXIMUM POWER DISSIPATION – W APPLICATIONS Theory of Operation Input Overvoltage Protection Output Phase Reversal 10-LEAD MSOP 6-LEAD SOT-23 0.50 0.25 0 35 85 The buffer family features low THD+N. The total harmonic distortion plus noise for the buffer over the entire supply range is below 0.08%. When the device is powered from a 16 V supply, the THD+N stays below 0.03%. Figure 2 shows the AD8568 THD+N versus frequency performance. 10 O The maximum safe junction temperature, TJMAX, is 150°C. Using the following formula, we can obtain the maximum power that the buffer family can safely dissipate as a function of temperature. The power dissipated by the device can be calculated as  0.1 VS = 2.5V VS = 8V 0.01 PDISS = (TJMAX − TA ) / θ JA where: PDISS = the power dissipation. TJMAX = the maximum allowable junction temperature (150°C). TA = the ambient temperature of the circuit. θJA = the AD856x package thermal resistance, junction-to-ambient. 1 THD + N – % The maximum allowable internal junction temperature of 150°C limits the device’s maximum power dissipation. As the ambient temperature increases, the maximum power dissipated by the device must decrease linearly to maintain the maximum junction temperature. If this maximum junction temperature is exceeded momentarily, the device will still operate properly once the junction temperature is reduced below 150°C. If the maximum junction temperature is exceeded for an extended period of time, overheating could lead to permanent damage of the device. REV. C 65 Total Harmonic Distortion + Noise (THD+N) Power Dissipation where: VS = the supply voltage. VOUT = the output voltage. ILOAD = the output load current. 5 25 45 AMBIENT TEMPERATURE – C Figure 1. Maximum Power Dissipation vs. Temperature for 6- and 10-Lead Packages B SO The buffer family is immune to phase reversal. Although the device’s output will not change phase, large currents due to input overvoltage could damage the device. In applications where the possibility exists of an input voltage exceeding the supply voltage, overvoltage protection should be used as described in the previous section. PDISS = (VS − VOUT ) × I LOAD 15 LE This input current is not inherently damaging to the device as long as it is limited to 5 mA or less. If a condition exists using the buffers where the input exceeds the supply by more than 0.6 V, an external series resistor should be added. The size of the resistor can be calculated by using the maximum overvoltage divided by 5 mA. This resistance should be placed in series with the input exposed to an overvoltage. 0.75 TE As with any semiconductor device, whenever the input exceeds either supply voltage, attention needs to be paid to the input overvoltage characteristics. As an overvoltage occurs, the amplifier could be damaged, depending on the voltage level and the magnitude of the fault current. When the input voltage exceeds either supply by more than 0.6 V, the internal pn junctions will allow current to flow from the input to the supplies. 20 100 1k FREQUENCY – Hz 10k 30k Figure 2. AD8568 THD+N vs. Frequency Short-Circuit Output Conditions The buffer family does not have internal short-circuit protection circuitry. As a precautionary measure, do not short the output directly to the positive power supply or to ground. It is not recommended to operate the AD856x with more than 35 mA of continuous output current. The output current can be limited by placing a series resistor at the output of the amplifier whose value can be derived using the following equation. RX ≥ VS 35 mA For a 5 V single-supply operation, RX should have a minimum value of 143 Ω. –9– AD8568/AD8569/AD8570 OUTLINE DIMENSIONS 6-Lead Small Outline Transistor Package [SOT-23] (RT-6) 10-Lead Micro Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters Dimensions shown in millimeters 2.90 BSC 6 5 3.00 BSC 4 1 2 4.90 BSC 3.00 BSC 3 1 PIN 1 TE 0.50 BSC 1.90 BSC 0.95 0.85 0.75 0.50 0.30 0.22 0.08 1.10 MAX 0.15 0.00 10 4 0 SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-178AB 0.60 0.45 0.30 0.27 0.17 SEATING PLANE 0.23 0.08 8 0 0.80 0.60 0.40 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA LE 1.45 MAX 0.15 MAX 5 PIN 1 0.95 BSC 1.30 1.15 0.90 6 10 2.80 BSC 1.60 BSC 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 x 5 mm Body (CP-32-2) B SO Dimensions shown in millimeters 5.00 BSC SQ PIN 1 INDICATOR 0.50 0.40 0.30 12 MAX O 1.00 0.85 0.80 SEATING PLANE PIN 1 INDICATOR 25 24 32 1 0.50 BSC 4.75 BSC SQ TOP VIEW 0.60 MAX 0.60 MAX 3.25 3.10 SQ 2.95 BOTTOM VIEW 17 16 0.80 MAX 0.65 TYP 9 8 0.25 MIN 3.50 REF 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 –10– REV. C AD8568/AD8569/AD8570 OUTLINE DIMENSIONS 20-Lead Thin Shrink Small Outline Package [TSSOP] (RU-20) Dimensions shown in millimeters 6.60 6.50 6.40 20 11 1 10 PIN 1 0.65 BSC 0.15 0.05 1.20 MAX 6.40 BSC TE 4.50 4.40 4.30 0.20 0.09 0.30 COPLANARITY 0.19 0.10 SEATING PLANE 8 0 0.75 0.60 0.45 Location B SO Revision History LE COMPLIANT TO JEDEC STANDARDS MO-153AC Page 12/03—Data Sheet changed from REV. B to REV. C. Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5/02—Data Sheet changed from REV. A to REV. B. Added 20-Lead TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Added Package Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 O Added TSSOP Package to OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 REV. C –11– –12– TE LE B SO O C02612–0–12/03(C)