AD8582AR-REEL

a +5 Volt, Parallel Input Complete Dual 12-Bit DAC AD8582 FEATURES Complete Dual 12-Bit DAC No External Components Single +5 Volt Operation 1 mV/Bit with 4.095 V Full Scale True Voltage Output, ±5 mA Drive Very Low Power: 5 mW FUNCTIONAL BLOCK DIAGRAM AD8582 APPLICATIONS Digitally Controlled Calibration Portable Equipment Servo Controls Process Control Equipment PC Peripherals DAC A REGISTER CS A/B INPUT A REGISTER 12 DATA VDD 12 LDA 2 12-BIT DAC A VOUTA VREF REFERENCE INPUT B REGISTER 12 DAC B REGISTER LDB 12-BIT DAC B VOUTB AGND RST MSB DGND GENERAL DESCRIPTION The AD8582 is a complete, parallel input, dual 12-bit, voltage output DAC designed to operate from a single +5 volt supply. Built using a CBCMOS process, this monolithic DAC offers the user low cost, and ease-of-use in +5 volt only systems. Included on the chip, in addition to the DACs, are a rail-to-rail amplifier, latch and reference. The reference (VREF) is trimmed to 2.5 volts output, and the on-chip amplifier gains up the DAC output to 4.095 volts full scale. The user needs only supply a +5 volt supply. The AD8582 is coded natural binary. The op amp output swings from 0 volt to +4.095 volts for a one-millivolt-per-bit resolution, and is capable of driving ± 5 mA. Operation down to 4.3 V is possible with output load currents less than 1 mA. The high speed parallel data interface connects to the fastest processors without wait states. The double-buffered input structure allows the user to load the input registers one at a time, then a single load strobe tied to both LDA + LDB inputs will update both DAC outputs simultaneously. LDA and LDB can also be activated independently to immediately update their respective DAC registers. An address input decodes DAC A or DAC B when the chip select CS input is strobed. An asynchronous reset input sets the output to zero scale. The MSB bit can be used to establish a preset to midscale when the reset input is strobed. The AD8582 is available in the 24-pin plastic DIP and the surface mount SOIC-24. Each part is fully specified for operation over –40°C to +85°C, and the full +5 V ± 5% power supply range. 5.0 4.6 4.4 VDD = +5V T = –55°C, +25°C, +85°C 1.5 LINEARITY ERROR – LSB VDD MIN – Volts 4.8 2.0 ∆∆VFS ≤ 1 LSB DATA = FFFH TA = +25°C PROPER OPERATION WHEN VDD SUPPLY VOLTAGE ABOVE CURVE 4.2 A 1.0 0.5 0.0 –0.5 –1.0 = +25°C & +85°C = –55°C –1.5 4.0 0.01 0.1 1.0 10 OUTPUT LOAD CURRENT – mA 100 Figure 1. Minimum Supply Voltage vs. Load –2.0 0 1024 2048 3072 4096 DIGITAL INPUT CODE – Decimal Figure 2. Linearity Error vs. Digital Code and Temperature REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD8582–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V DD = +5.0 V ± 5%, RL = No Load, –40°C ≤ TA ≤ +85°C, unless otherwise noted) Parameter Symbol Condition Min STATIC PERFORMANCE Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Voltage Full-Scale Tempco N INL DNL VZSE VFS TCVFS Note 1 12 –2 –1 MATCHING PERFORMANCE Linearity Matching Error ∆VFSA/B REFERENCE OUTPUT Output Voltage Output Source Current Line Rejection Load Regulation VREF IREF LNREJ LDREG ANALOG OUTPUT Output Current Load Regulation at Half Scale Capacitive Load IOUT LDREG CL DYNAMIC CHARACTERISTICS3 Crosstalk Voltage Output Settling Time5 Digital Feedthrough CT tS FT LOGIC INPUTS Logic Input Low Voltage Logic Input High Voltage Input Leakage Current Input Capacitance VIL VIH IIL CIL TIMING SPECIFICATIONS3, 6 Chip Select Pulse Width DAC Select Setup DAC Select Hold Data Setup Data Hold Load Setup Load Hold Load Pulse Width Reset Pulse Width tCSW tAS tAH tDS tDH tLS tLH tLDW tRSW SUPPLY CHARACTERISTICS Positive Supply Current IDD Power Dissipation7 PDISS Power Supply Sensitivity PSS Monotonic Data = 000H Data = FFFH,2 Notes 2 and 3 4.079 Typ Max Units ± 3/4 ± 3/4 +0.2 4.095 ± 16 +2 +1 +3 4.111 Bits LSB LSB mV V ppm/°C ±1 2.484 2.500 Note 4 IREF = 0 mA to 5 mA Data = 800H RL = 402 Ω to ∞, Data = 800H No Oscillation3 1 500 LSB 2.516 –5 0.08 0.1 V mA %/V %/mA ±5 3 mA LSB pF >64 16 35 To ± 1 LSB of Final Value Signal Measured at DAC Output, While Changing Data (LDA = LDB = “1”) dB µs nV s 0.8 2.4 10 10 Note 3 30 30 0 30 10 20 10 20 30 VIH = 2.4 V, VIL = 0.8 V VIL = 0 V, VDD = +5 V VIH = 2.4 V, VIL = 0.8 V VIL = 0 V, VDD = +5 V ∆VDD = ± 5% V V µA pF ns ns ns ns ns ns ns ns ns 4 1 20 5 0.002 7 2 35 10 0.004 mA mA mW mW %/% NOTES 1 1 LSB = 1 mV for 0 V to +4.095 V output range. 2 Includes internal voltage reference error. 3 These parameters are guaranteed by design and not subject to production testing. 4 Very little sink current is available at the V REF pin. Use external buffer if setting up a virtual ground. 5 Settling time is not guaranteed for the first six codes 0 through 5. 6 All input control signals are specified with t R = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V. 7 Power dissipation is a calculated value I DD × 5 V. Specifications subject to change without notice. –2– REV. 0 AD8582 PIN DESCRIPTION ABSOLUTE MAXIMUM RATINGS* VDD to DGND & AGND . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V Logic Inputs to DGND . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V VOUT to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V VREF to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD IOUT Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 50 mA Package Power Dissipation . . . . . . . . . . . . . . . (TJ max–TA)/θJA Thermal Resistance, θJA 24-Pin Plastic DIP Package (N-24) . . . . . . . . . . . . . 62°C/W 24-Lead SOIC Package (SOL-24) . . . . . . . . . . . . . . 73°C/W Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Pin No. Name 1, 24 VOUTA VOUTB Voltage outputs from the DACs. Fixed output voltage range of 0 V to 4.095 V with 1 mV/LSB. An internal temperature stabilized reference maintains a fixed full-scale voltage independent of time, temperature and power supply variations. AGND Analog Ground. Ground reference for the internal bandgap reference voltage, the DAC, and the output buffer. DGND Digital ground for input logic. LDA, Load DAC register strobes. Transfers LDB input register data to the DAC registers. Active low inputs, Level sensitive latch. May be connected together to doublebuffer load DAC registers. MSB Digital Input: High presets DAC registers to half scale (800H), Low clears DAC registers to zero (000H) upon RST assertion. RST Active low digital input that clears the DAC register to zero, setting the DAC to minimum scale when MSB pin = 0, or half-scale when MSB pin = 1. DB0–11 Twelve Binary Data Bit Inputs. DB11 is the MSB and DB0 is the LSB. CS Chip Select. Active low input. A/B Select DAC A = 0 or DAC B = 1. VDD Positive Supply. Nominal value +5 V, ± 5%. Nominal 2.5 V reference output VREF voltage. This node must be buffered if required to drive external loads. 2 3 4, 21 *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5 tCSW CS tAH tAS 6 A/B tDH tDS D0–D11 tLDW tLH tLS LDA, LDB 7–18 tRSW 19 20 22 23 RST tS tS VOUT ± 1LSB ERROR BAND Timing Diagram PIN CONFIGURATIONS N-24 SOL-24 24-Pin Plastic DIP 24-Pin SOIC ORDERING INFORMATION* Model Temperature Range Package Description Description Package Option 1 VOUTA AD8582AN –40°C to +85°C 24-Pin Plastic DIP N-24 AD8582AR –40°C to +85°C 24-Lead SOIC SOL-24 AD8582Chips +25°C Die *For die specifications contact your local Analog Devices sales office. The AD8582 contains 1270 transistors. 1 AGND 2 23 VREF DGND 3 22 VDD LDA 4 21 LDB MSB 5 RST 6 DB0 7 DB1 8 DB2 9 20 AD8582 12 13 16 DB9 15 DB8 DB4 11 14 DB7 DB5 12 13 DB6 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8582 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –3– A/B AD8582 TOP VIEW (Not to Scale) 19 CS TOP VIEW (Not to Scale) 18 DB11 17 DB10 DB3 10 REV. 0 24 24 VOUTB WARNING! ESD SENSITIVE DEVICE AD8582 Table I. Control Logic Truth Table CS A/B LDA LDB RST MSB Input Register DAC Register L L L L H H X X H L H L H X X X X X H H L H L ^ X X X H H H L L ^ X X X H H H H H H L L ^ X X X X X X L H X Write to A Write to B Write to A Write to B Latched Latched Reset to Zero Scale Reset to Midscale Latch Reset Value Latched Latched A Transparent B Transparent A & B Transparent Latched Reset to Zero Scale Reset to Midscale Latch Reset Value ^Denotes positive edge triggered. OPERATION BANDGAP REFERENCE The AD8582 is a complete, ready-to-use dual 12-bit digital-toanalog converter. Only one +5 V power supply is necessary for operation. It contains two voltage-switched, 12-bit, lasertrimmed digital-to-analog converters, a curvature-corrected bandgap reference, rail-to-rail output op amps, input registers, and DAC registers. The parallel data interface consists of twelve data bits, DB0–DB11, an address select pin A/B, two load strobe pins (LDA, LDB) and an active low CS strobe. In addition an asynchronous RST pin will set all DAC register bits to zero causing the VOUT to become zero volts, or to midscale for trimming applications when the MSB pin is programmed to Logic 1. This function is useful for power on reset or system failure recovery to a known state. AMPLIFIER SECTION The internal DAC’s output is buffered by a low power consumption precision amplifier. This low power amplifier contains a differential PNP pair input stage which provides low offset voltage and low noise, as well as the ability to amplify the zeroscale DAC output voltages. The rail-to-rail amplifier is configured in a gain of 1.6384 (= 4.095 V/2.5 V) in order to set the 4.095 volt full-scale output (1 mV/LSB). See Figure 3 for an equivalent circuit schematic of the analog section. VOLTAGE SWITCHED 12-BIT R-2R D/A CONVERTER RAIL-TO-RAIL OUTPUT AMPLIFIER 2R VOUT R BUFFER R2 2R R 2R R1 AV = 4.095/2.5 = 1.638V/V 2R SPDT N CH FET SWITCHES D/A CONVERTER SECTION The internal DAC is a 12-bit voltage-mode device with an output that swings from AGND potential to the 2.5 volt internal bandgap voltage. It uses a laser trimmed R-2R ladder which is switched by N channel MOSFETs. The output voltage of the DAC has a constant resistance independent of digital input code. The DAC output (not available to the user) is internally connected to the rail-to-rail output op amp. VREF 2.5V 2R Figure 3. Equivalent Schematic of Analog Portion OUTPUT SECTION The rail-to-rail output stage of this amplifier has been designed to provide precision performance while operating near either power supply. Figure 4 shows an equivalent output schematic of the rail-to-rail amplifier with its N channel pull-down FETs that will pull an output load directly to GND. The output sourcing current is provided by a P channel pull-up device that can supply GND terminated loads, especially important at the –5% supply tolerance value of 4.75 volts. VDD P-CH N-CH The op amp has a 16 µs typical settling time to 0.01%. There are slight differences in settling time for negative slewing signals versus positive. See the oscilloscope photos in the Typical Performances section of this data sheet. VOUT AGND Figure 4. Equivalent Analog Output Circuit –4– REV. 0 AD8582 Figures 5 and 6 in the typical performance characteristics section provide information on output swing performance near ground and full-scale as a function of load. In addition to resistive load driving capability, the amplifier has also been carefully designed and characterized for up to 500 pF capacitive load driving capability. One advantage of the rail-to-rail output amplifiers used in the AD8582 is the wide range of usable supply voltage. The part is fully specified and tested over temperature for operation from +4.75 V to +5.25 V. If reduced linearity and source current capability near full scale can be tolerated, operation of the AD8582 is possible down to +4.3 volts. The minimum operating supply voltage versus load current plot, in Figure 1, provides information for operation below VDD = +4.75 V. REFERENCE SECTION The internal 2.5 V curvature-corrected bandgap voltage reference is laser trimmed for both initial accuracy and low temperature coefficient. The voltage generated by the reference is available at the VREF pin. Since VREF is not intended to drive external loads, it must be buffered. The equivalent emitter follower output circuit of the VREF pin is shown in Figure 3. TIMING AND CONTROL The input registers are level triggered and acquire data from the data bus during the time period when CS is low. The input register selected is determined by the A/B select pin, see Table I. for a complete description. When CS goes high, the data is latched into the register and held until CS returns low. The minimum time required for the data to be present on the bus before CS returns high is called the data setup time (tDS) as seen in Timing Diagram. The data hold time (tDH) is the amount of time that the data has to remain on the bus after CS goes high. The high speed timing offered by the AD8582 provides for direct interface with no wait states in all but the fastest microprocessors. Bypassing the VREF pin will improve noise performance; however, bypassing is not required for proper operation. Figure 8 shows broadband noise performance. POWER SUPPLY The very low power consumption of the AD8582 is a direct result of a circuit design optimizing use of the CBCMOS process. By using the low power characteristics of the CMOS for the logic, and the low noise, tight matching of the complementary bipolar transistors good analog accuracy is achieved. The data from the input registers is transferred to the DAC registers by the active low LDA and LDB pins. If these inputs are tied together, a single logic input can perform a double buffer update of the DAC registers, which in turn simultaneously changes the analog output voltages to a new value. If the LDA and LDB pins are wired low, they become transparent. In this mode the input register data will directly control the output voltages. Refer to the Control Logic Truth Table for a com- For power-consumption sensitive applications it is important to note that the internal power consumption of the AD8582 is strongly dependent on the actual logic-input voltage levels present on the DB0–DB11, CS, A/B, MSB, LDA, LDB and RST pins. Since these inputs are standard CMOS logic structures they contribute static power dissipation dependent on the actual driving logic VOH and VOL voltage levels. The graph in Figure 9 shows the effect on total AD8582 supply current as a function of the actual value of input logic voltage. Consequently, for optimum dissipation use of CMOS logic versus TTL provides minimal dissipation in the static state. A VINL = 0 V on the DB0–11 pins provides the lowest standby dissipation of 1 mA typical with a +5 V power supply. plete description. Unipolar Output Operation This is the basic mode of operation for the AD8582. The AD8582 has been designed to drive loads as low as 820Ω in parallel with 500 pF. The code table for this operation is shown in Table II. As with any analog system, it is recommended that the AD8582 power supply be bypassed on the same PC card that contains the chip. Figure 10 shows the power supply rejection versus frequency performance. This should be taken into account when using higher frequency switched-mode power supplies with ripple frequencies of 100 kHz and higher. REV. 0 Table II. Unipolar Code Table –5– Hexadecimal Number in DAC Register Decimal Number in DAC Register Analog Output Voltage (V) FFF 801 800 7FF 000 4095 2049 2048 2047 0 + 4.095 + 2.049 + 2.048 + 2.047 0 AD8582–Typical Performance Characteristics OUTPUT PULL-DOWN VOLTAGE – mV RL TIED TO AGND DATA = FFFH 3 2 RL TIED TO +5V DATA = 000H 1 0 10 1 TA = +85°C TA = –40°C 0.1 100 1k 10k LOAD RESISTANCE – Ω 10 100 POWER SUPPLY REJECTION – dB OUTPUT NOISE VOLTAGE – 200µV/DIV TA = +25°C SUPPLY CURRENT – mA VDD = +4.75V VDD = +5V 3 2 0 5 204810 TO 204710 OUTPUT 2.048 VOUT – Volts 1 2 3 4 LOGIC VOLTAGE VALUE – Volts 5 0 LDB 90 VDD = +5V 3 TA = +25°C 2 10 0% 0 20µs 1V Figure 11. Midscale Transition Performance 40 20 0 10 100 1k 10k FREQUENCY – Hz 100k Figure 10. Power Supply Rejection vs. Frequency 5 0 15µs 4 1 TA = +25°C DATA = FFFH 60 DATA 5V 5 100 3 VDD = +5V ±200mV AC 80 Figure 9. Supply Current vs. Logic Input Voltage INPUT LD Figure 8. Broadband Noise 2 Figure 7. IOUT vs. VOUT 0 TIME – 500ns/DIV 1 100 4 TIME = 100µs/DIV 2.008 NEGATIVE CURRENT LIMIT OUTPUT VOLTAGE – Volts 1 2.018 –40 Figure 6. Pull-Down Voltage vs. Output Sink Current Capability TA = +25°C NBW = 630kHz 2.028 –20 1000 5 2.038 DATA = 800H RL TIED TO +2V 0 OUTPUT SINK CURRENT – µA Figure 5. Output Swing vs. Load 0 20 –80 1 100k 40 –60 TA = +25°C 0.01 10 POSITIVE0 CURRENT0 LIMIT0 60 OUTPUT CURRENT – mA 4 VDD = +5V DATA = 000H TIME = 20µs/DIV Figure 12. Large Signal Settling Time –6– OUTPUT VOLTAGE 1mV/DIV VDD = +5V TA = +25°C OUTPUT VOLTAGE – Volts 80 100 5 VDD = +5V TA = +25°C TIME – 5µs/DIV Figure 13. Output Voltage Rise Time Detail REV. 0 AD8582 TUE = ΣINL+ZS+FS SS = 297 UNITS V = +4.75V DD T = +25°C A 40 35 0 FREQUENCY 30 15µs 25 20 15 10 4.115 FULL-SCALE OUTPUT – Volts 5 OUTPUT VOLTAGE 1mV/DIV DATA 45 VDD = +5V TA = +25°C 0 4.105 4.100 σAVG +1σ 4.095 4.090 4.085 σAVG –1σ 4.080 5 TIME – 5µs/DIV VDD = +4.75V NO LOAD SS = 298 UNITS 4.110 –8 –7 –6 –5 –4 –3 –2 –1 0 4.075 –50 1 –25 TOTAL UNADJUSTED ERROR – mV Figure 14. Output Voltage Fall Time Detail 1 0 –1 –50 0 25 50 75 TEMPERATURE – °C 100 H 10 1.0 125 1 σAVG +2σ 0 AVG –1 –2 σAVG –2σ 125 –3 10 Figure 17. Zero-Scale Voltage vs. Temperature 100 VDD = +5V SS = 135 UNITS DATA = FFFH 2 0.1 –25 75 3 VDD = +5V TA = +25°C DATA = FFF NOMINAL FULL-SCALE VOLTAGE CHANGE – mV OUTPUT NOISE DENSITY – µV/ Hz ZERO-SCALE OUTPUT – Volts 2 50 Figure 16. Full-Scale Voltage vs. Temperature 100 VDD = +4.75V NO LOAD SS = 298 UNITS 25 TEMPERATURE – °C Figure 15. Total Unadjusted Error Histogram 3 0 AVG 100 1k 10k FREQUENCY – Hz 0 100k 100 200 300 400 500 HOURS OF OPERATION AT +150°C 600 Figure 19. Long-Term Drift Accelerated by Burn-In Figure 18. Output Voltage Noise Density vs. Frequency 8 6 VDD = +5.25V ∞ TA = +25°C RL = ∞ VDD 5 VDD = +5.00V 4 0V 3 VREF 0V VDD = +4.75V 2 10 –25 0 25 50 75 100 125 0 5µs CS = HIGH 100 90 10 0% 10mV 2V 0 –50 1 VDD = +5V 0% 1 5V 1µs VOUT 10mV/DIV SUPPLY CURRENT – mA 2V 100 90 DATA VDATA = +2.4V NO LOAD 7 TIME – 1µs/DIV TIME – 5µs/DIV TEMPERATURE – °C Figure 20. Supply Current vs. Temperature REV. 0 Figure 21. Reference Startup vs. Time –7– Figure 22. Digital Feedthrough vs. Time AD8582 6 4 σAVG +1σ AVG –2 –4 –6 –8 –10 –50 σAVG –1σ –25 25 50 75 0 TEMPERATURE – °C 100 σAVG +1σ AVG –0.002 –0.003 –0.004 σAVG –1σ –0.005 –50 125 ∆VDD = +4.75V ∆IL = 5mA –0.001 –25 0 25 50 75 100 ∆ VDD = +4.75 TO +5.25V 0.08 0.06 AVG 0.04 0.02 σAVG – 1σ 0.00 –50 125 –25 0 25 50 75 100 125 TEMPERATURE – °C TEMPERATURE – °C Figure 23. Reference Error vs. Temperature σAVG +1σ Figure 24. Reference Load Regulation vs. Temperature Figure 25. Reference Line Regulation vs. Temperature OUTLINE DIMENSIONS Dimensions shown in inches and (mm). N-24 24-Pin Narrow Body Plastic DIP PIN 1 24 13 1 12 0.280 (7.11) 0.240 (6.10) 1.275 (32.30) 1.125 (28.60) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.150 (3.81) MIN 0.200 (5.05) 0.125 (3.18) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 0.070 (1.77) 0.045 (1.15) SEATING PLANE 0.015 (0.381) 0.008 (0.204) SOL-24 24-Lead Wide Body SOIC 13 24 0.2992 (7.60) 0.2914 (7.40) PIN 1 1 12 0.0118 (0.30) 0.0040 (0.10) 0.0500 (1.27) BSC 0.4193 (10.65) 0.3937 (10.00) 0.1043 (2.65) 0.0926 (2.35) 0.6141 (15.60) 0.5985 (15.20) 0.0192 (0.49) 0.0138 (0.35) –8– PRINTED IN U.S.A. 0 REF LINE REGULATION – %/Volt REF LOAD REGULATION – %/mA REFERENCE ERROR – mV 8 2 0.10 0.000 VDD = +4.75V C1869–18–12/93 10 0.0125 (0.32) 0.0091 (0.23) 0.0291 (0.74) x 45° 0.0098 (0.25) 8° 0° 0.0500 (1.27) 0.0157 (0.40) REV. 0