a
FEATURES
Low Cost
Replaces Eight Potentiometers
Eight Individually Programmable Outputs
Three-Wire Serial Input
Power Shutdown ≤ 25 mW Including IDD and IREF
Midscale Preset, AD8801
Separate V REFL Range Setting, AD8803
+3 V to +5 V Single Supply Operation
Octal 8-Bit TrimDAC
with Power Shutdown
AD8801/AD8803
FUNCTIONAL BLOCK DIAGRAM
(DACs 2–7 Omitted for Clarity)
VREFH
AD8801/AD8803
8
VDD
8-BIT
LATCH
GND
CK RS
DAC
SELECT
APPLICATIONS
Automatic Adjustment
Trimmer Potentiometer Replacement
Video and Audio Equipment Gain and Offset Adjustment
Portable and Battery Operated Equipment
DAC 1 VOUT
VREFL
.
.
.
.
.
.
3
CS
O1
8
1
11-BIT
SERIAL 8
LATCH
SDI
D
CK RS
8
GENERAL DESCRIPTION
Easily programmed by serial interfaced microcontroller ports,
the AD8801 with its midscale preset is ideal for potentiometer
replacement where adjustments start at a nominal value. Applications such as gain control of video amplifiers, voltage controlled frequencies and bandwidths in video equipment,
geometric correction and automatic adjustment in CRT computer graphic displays are a few of the many applications ideally
suited for these parts. The AD8803 provides independent control of both the top and bottom end of the potentiometer divider
allowing a separate zero-scale voltage setting determined by the
VREFL pin. This is helpful for maximizing the resolution of devices with a limited allowable voltage control range.
VREFH
8
ADDRESS
CLK
The AD8801/AD8803 provides eight digitally controlled dc
voltage outputs. This potentiometer divider TrimDAC® allows
replacement of the mechanical trimmer function in new designs.
The AD8801/AD8803 is ideal for dc voltage adjustment
applications.
VREFL
8-BIT 8
LATCH
CK RS
RS
VREFH
DAC 8 VOUT
VREFL
O8
8
SHDN
Internally the AD8801/AD8803 contain eight voltage output
digital-to-analog converters, sharing a common reference voltage input.
Each DAC has its own DAC register that holds its output state.
These DAC registers are updated from an internal serial-to-parallel shift register that is loaded from a standard three-wire serial
input digital interface. Eleven data bits make up the data word
clocked into the serial input register. This data word is decoded
where the first 3 bits determine the address of the DAC register
to be loaded with the last 8 bits of data. The AD8801/AD8803
consumes only 5 µA from 5 V power supplies. In addition, in
shutdown mode reference input current consumption is also reduced to 5 µA while saving the DAC latch settings for use after
return to normal operation.
The AD8801/AD8803 is available in 16-pin plastic DIP and the
1.5 mm height SO-16 surface mount packages.
See the AD8802/AD8804 for a twelve channel version of this product.
TrimDAC is a registered trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
(VDD = +3 V 6 10% or +5 V 6 10%, VREFH = +VDD, VREFL = 0 V, –408C
AD8801/AD8803–SPECIFICATIONS ≤ T ≤ +858C unless otherwise noted)
A
Parameter
Symbol
STATIC ACCURACY
Specifications Apply to All DACs
Resolution
Integral Nonlinearity Error
Differential Nonlinearity
Full-Scale Error
Zero-Code Error
DAC Output Resistance
Output Resistance Match
N
INL
DNL
GFSE
VZSE
ROUT
∆R/RO
REFERENCE INPUT
Voltage Range2
Input Resistance
Reference Input Capacitance 3
VREFH
VREFL
RREFH
CREF0
CREF1
Conditions
Guaranteed Monotonic
Pin Available on AD8803 Only
Digital Inputs = 55 H, VREFH = VDD
Digital Inputs All Zeros
Digital Inputs All Ones
Min
8
–1.5
–1
–4
–0.5
3
Typ1
Max
Units
± 1/2
± 1/4
–2.8
± 0.1
5
1
+1.5
+1
+0.5
+0.5
8
Bits
LSB
LSB
LSB
LSB
kΩ
%
0
0
VDD
VDD
2
25
25
DIGITAL INPUTS
Logic High
Logic Low
Logic High
Logic Low
Input Current
Input Capacitance3
VIH
VIL
VIH
VIL
IIL
CIL
POWER SUPPLIES4
Power Supply Range
Supply Current (CMOS)
Supply Current (TTL)
Shutdown Current
Power Dissipation
Power Supply Sensitivity
Power Supply Sensitivity
VDD Range
IDD
IDD
IREFH
PDISS
PSRR
PSRR
VIH = VDD or VIL = 0 V
VIH = 2.4 V or VIL = 0.8 V, VDD= +5.5 V
SHDN = 0
VIH = VDD or VIL = 0 V, VDD = +5.5 V
VDD = 5 V ± 10%, VREFH = +4.5 V
VDD = 3 V ± 10%, VREFH = +2.7 V
0.01
1
0.01
DYNAMIC PERFORMANCE 3
VOUT Settling Time (Positive or Negative)
Crosstalk
tS
CT
± 1/2 LSB Error Band
See Note 5, f = 100 kHz
0.6
50
SWITCHING CHARACTERISTICS 3, 6
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Rise to CS Rise Hold Time
CS Rise to Next Rising Clock
tCH, tCL
tDS
tDH
tCSS
tCSW
tRS
tCSH
tCS1
Clock Level High or Low
VDD = +5 V
VDD = +5 V
VDD = +3 V
VDD = +3 V
VIN = 0 V or +5 V
V
V
kΩ
pF
pF
2.4
V
V
V
V
µA
pF
0.8
2.1
0.6
±1
5
2.7
0.001
0.01
5.5
5
4
5
27.5
0.002
V
µA
mA
µA
µW
%/%
%/%
µs
dB
15
5
5
10
10
60
15
10
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1
Typical values represent average readings measured at +25 °C.
2
VREFH can be any value between GND and V DD, for the AD8803 V REFL can be any value between GND and V DD.
3
Guaranteed by design and not subject to production test.
4
Digital Input voltages V IN = 0 V or VDD for CMOS condition. DAC outputs unloaded. PDISS is calculated from (I DD × VDD).
5
Measured at a V OUT pin where an adjacent V OUT pin is making a full-scale voltage change.
6
See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of V DD) and timed from a voltage
level of 1.6 V.
Specifications subject to change without notice.
–2–
REV. A
AD8801/AD8803
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3, +8 V
VREFX to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Outputs (Ox) to GND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . 0 V, VDD
Operating Temperature Range . . . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (TJ MAX) . . . . . . . . +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . (TJ MAX – TA)/θJA
Thermal Resistance θJA,
SOIC (SO-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
P-DIP (N-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57°C/W
AD8801 PIN DESCRIPTIONS
VREFH
O1
O2
O3
O4
SHDN
7
CS
8
9
10
11
12
13
14
15
GND
CLK
SDI
O5
O6
O7
O8
RS
16
VDD
FTN
Temperature
Package
Package
Description Option
AD8801AN
AD8801AR
AD8803AN
AD8803AR
RS
RS
REFL
REFL
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
PDIP-16
SO-16
PDIP-16
SO-16
Common DAC Reference Input
DAC Output #1, Addr = 0002
DAC Output #2, Addr = 0012
DAC Output #3, Addr = 0102
DAC Output #4, Addr = 0112
Reference input open circuit, active low, all
DAC outputs open circuit. DAC latch settings
maintained.
Chip Select Input, active low. When CS returns
high, data in the serial input register is decoded
based on the address bits and loaded into the target DAC register.
Ground
Serial Clock Input, Positive Edge Triggered
Serial Data Input
DAC Output #5, Addr = 1002
DAC Output #6, Addr = 1012
DAC Output #7, Addr = 1102
DAC Output #8, Addr = 1112
Asynchronous preset to midscale output setting,
active low. Loads all DAC latches with 80H.
Positive power supply, specified for operation at
both +3 V and +5 V.
Pin Name
Description
1
2
3
4
5
6
VREFH
O1
O2
O3
O4
SHDN
7
CS
8
9
10
11
12
13
14
15
16
GND
VREFL
CLK
SDI
O5
O6
O7
O8
VDD
Common High-Side DAC Reference Input
DAC Output #1, Addr = 0002
DAC Output #2, Addr = 0012
DAC Output #3, Addr = 0102
DAC Output #4, Addr = 0112
Reference inputs open circuit, active low, all
DAC outputs open circuit. DAC latch settings
maintained.
Chip Select Input, active low. When CS returns
high, data in the serial input register is decoded
based on the address bits and loaded into the target DAC register.
Ground
Common Low-Side DAC Reference Input
Serial Clock Input, Positive Edge Triggered
Serial Data Input
DAC Output #5, Addr = 1002
DAC Output #6, Addr = 1012
DAC Output #7, Addr = 1102
DAC Output #8, Addr = 1112
Positive power supply, specified for operation at
both +3 V and +5 V.
PIN CONFIGURATIONS
VREFH
1
16 VDD
VREFH
1
16 VDD
O1
2
15 RS
O1
2
15 O8
O2
3
14 O8
O2
3
O3
4
AD8801
13 O7
O3
4
AD8803
13 O6
O4
5
TOP VIEW
(Not to Scale)
12 O6
O4
5
TOP VIEW
(Not to Scale)
12 O5
SHDN
6
11 O5
SHDN
6
11 SDI
CS
7
10 SDI
CS
7
10 CLK
GND
8
GND
8
9
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
N-16
R-16A
N-16
R-16A
AD8803 PIN DESCRIPTIONS
Pin Name Description
1
2
3
4
5
6
Model
–3–
CLK
14 O7
9
VREFL
WARNING!
ESD SENSITIVE DEVICE
AD8801/AD8803
following address assignments for the ADDR decode which determines the location of DAC register receiving the serial register data in bits B7 through B0:
OCTAL 8-BIT TRIMDAC, WITH SHUTDOWN
1
SDI
A2 A1 A0
D7 D6 D5
D4 D3 D2 D1
D0
0
DAC # = A2 × 4 + A1 × 2 + A0 + 1
1
CLK
0
1
DAC outputs can be changed one at a time in random sequence. The fast serial-data loading of 33 MHz makes it possible
to load all eight DACs in as little time as 3 µs (12 × 8 × 30 ns).
The exact timing requirements are shown in Figure 2.
DAC REGISTER LOAD
CS
0
+5V
VOUT
The AD8801 offers a midscale preset activated by the RS pin
simplifying initial setting conditions at first power up. The
AD8803 has both a VREFH and a VREFL pin to establish independent positive full-scale and zero-scale settings to optimize resolution. Both parts offer a power shutdown SHDN that places
the DAC structure in a zero power consumption state resulting
in only leakage currents being consumed from the power supply,
VREF inputs, and all 8 outputs. In shutdown mode the DACx
latch settings are maintained. When returning to operational
mode from power shutdown the DAC outputs return to their
previous voltage settings.
0V
Figure 2a. Timing Diagram
DETAIL SERIAL DATA INPUT TIMING (RS = "1")
SDI
1
(DATA
IN)
0
AX OR DX
AX OR DX
tDS
tDH
tCH
1
tCS1
CLK
0
tCL
tCSS
1
tCSH
TO OTHER DACS
tCSW
CS
0
tS
P CH
+5V
VREFH
±1 LSB
VOUT
0V
N CH
MSB
OX
2R
±1 LSB ERROR BAND
R
Figure 2b. Detail Timing Diagram
DAC
REGISTER
RESET TIMING
D7
tRS
1
2R
D6
RS
tS
.. ..
..
+5V
±1 LSB
VOUT
2.5V
R
D0
0
±1 LSB ERROR BAND
..
.
LSB
2R
Figure 2c. Reset Timing Diagram
Table I. Serial-Data Word Format
ADDR
B10 B9
B8
DATA
B7 B6
A2 A1
MSB
210 29
A0 D7 D6
LSB MSB
28
27
26
GND
VREFL
B5
B4
B3
B2
B1
B0
D5
D4
D3
D2
D1
25
24
23
22
21
D0
LSB
20
2R
Figure 3. AD8801/AD8803 Equivalent TrimDAC Circuit
PROGRAMMING THE OUTPUT VOLTAGE
The output voltage range is determined by the external reference connected to VREFH and VREFL pins. See Figure 3 for a
simplified diagram of the equivalent DAC circuit. In the case of
the AD8801, its VREFL is internally connected to GND and
therefore cannot be offset. VREFH can be tied to VDD and VREFL
can be tied to GND establishing a basic rail-to-rail voltage output programming range. Other output ranges are established by
the use of different external voltage references. The general
transfer equation that determines the programmed output
voltage is:
OPERATION
The AD8801/AD8803 provides eight channels of programmable
voltage output adjustment capability. Changing the programmed
output voltage of each TrimDAC is accomplished by clocking in
an 11-bit serial data word into the SDI (Serial Data Input) pin.
The format of this data word is three address bits, MSB first,
followed by eight data bits, MSB first. Table I provides the serial register data word format. The AD8801/AD8803 has the
VO (Dx) = (Dx)/256 × (VREFH – VREFL) + VREFL
(1)
where Dx is the data contained in the 8-bit DACx latch.
–4–
REV. A
AD8801/AD8803
For example, when VREFH = +5 V and VREFL = 0 V the following output voltages will be generated for the following codes:
D
VOX
Output State
(VREFH = +5 V, VREFL = 0 V)
255
128
1
0
4.98 V
2.50 V
0.02 V
0.00 V
Full-Scale
Half-Scale (Midscale Reset Value)
1 LSB
Zero-Scale
DIGITAL INTERFACING
The AD8801/AD8803 contains a standard three-wire serial input control interface. The three inputs are clock (CLK), CS and
serial data input (SDI). The positive-edge sensitive CLK input
requires clean transitions to avoid clocking incorrect data into
the serial input register. Standard logic families work well. If
mechanical switches are used for product evaluation, they
should be debounced by a flip-flop or other suitable means. Figure 4 block diagram shows more detail of the internal digital circuitry. When CS is taken active low, the clock can load data into
the serial register on each positive clock edge, see Table II.
REFERENCE INPUTS (V REFH, VREFL)
The reference input pins set the output voltage range of all eight
DACs. In the case of the AD8801 only the VREFH pin is available to establish a user designed full-scale output voltage. The
external reference voltage can be any value between 0 and VDD
but must not exceed the VDD supply voltage. In the case of the
AD8803, which has access to the VREFL which establishes the
zero-scale output voltage, any voltage can be applied between
0 V and VDD. VREFL can be smaller or larger in voltage than
VREFH since the DAC design uses fully bidirectional switches as
shown in Figure 3. The input resistance to the DAC has a code
dependent variation that has a nominal worst case measured at
55H, which is approximately 2 kΩ. When VREFH is greater than
VREFL, the REFL reference must be able to sink current out of
the DAC ladder, while the REFH reference is sourcing current
into the DAC ladder. The DAC design minimizes reference
glitch current maintaining minimum interference between DAC
channels during code changes.
Table II. Input Logic Control Truth Table
DAC
DAC
1
D7
DAC
REG
#1
EN
ADDR
DEC
D10
D9
D8
D7
SER
REG
SDI
D
..
.
D0
8
D0
RS
(AD8801 ONLY)
ADDR
DECODE
..
.
SERIAL
REGISTER
The target DAC register is loaded with the last eight bits of the serial data word completing one DAC update. Eight separate 11-bit
data words must be clocked in to change all eight output settings.
VDD
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 6. This applies to
digital input pins CS, SDI, RS, SHDN, CLK.
O1
100Ω
LOGIC
O5
O6
DAC
8
O7
Figure 6. Equivalent ESD Protection Circuit
O8
Digital inputs can be driven by voltages exceeding the AD8801/
AD8803 VDD value. This allows 5 V logic to interface directly to
the part when it is operated at 3 V.
R
VREFL
(AD8803 ONLY)
Figure 4. Block Diagram
REV. A
DAC 1
DAC 2
Figure 5. Equivalent Control Logic
SHDN
GND
X
CLK
SDI
O4
.. ..
..
DAC
REG
#8
P
No effect.
Shifts Serial Register one bit loading the
next bit in from the SDI pin.
Data is transferred from the serial register
to the decoded DAC register. See Figure 5.
O3
D7
D0
X
P
DAC 8
O2
R
.. .. ..
...
1
0
CS
VREFH
CLK
Register Activity
The data setup and data hold times in the specification table
determine the data valid time requirements. The last 11 bits of
the data word entered into the serial register are held when CS
returns high. At the same time CS goes high it gates the address
decoder which enables one of the eight positive edge triggered
DAC registers, see Figure 5 detail.
The eight DAC outputs present a constant output resistance of
approximately 5 kΩ independent of code setting. The distribution of ROUT from DAC to DAC typically matches within ± 1%.
However, device to device matching is process lot dependent
having a ± 20% variation. The change in ROUT with temperature
has a 500 ppm/°C temperature coefficient. During power shutdown all eight outputs are open circuited.
AD8801/AD8803
CLK
NOTE: P = positive edge, X = don’t care.
DAC OUTPUTS (O1–O8)
CS
CS
–5–
AD8801/AD8803–Typical Performance Characteristics
1
200
VDD = +5V
VREFH = +5V
VREFL = 0V
0.75
150
IREF CURRENT – µA
0.5
0.25
INL – LSB
VDD = +5V
VREFH = +2V
VREFL = 0V
ALL OTHER DACS SET
TO ZERO SCALE
TA = +25°C
TA = +85°C
TA = +25°C
TA = –40°C
0
–0.25
100
50
–0.5
–0.75
–1
0
32
64
96
128
160
CODE – Decimal
192
224
0
256
Figure 7. INL vs. Code
32
64
96
128
160
CODE – Decimal
192
224
256
Figure 10. Input Reference Current vs. Code
1
10k
VDD = +5V
VREFH = +5V
VREFL = 0V
VDD = +5.5V
VREF = 0V
IREF SHUTDOWN CURRENT – nA
0.75
TA = –40°C, +25°C, +85°C
0.5
0.25
DNL – LSB
0
0
–0.25
–0.5
1k
VDD = +5.5V
VREF = +5.5V
100
10
–0.75
–1
0
64
128
CODE – Decimal
192
0
–55
256
25
45
65
85
105
125
100k
VDD = +4.5V
VREF = +4.5V
VREFL = 0V
TA = +25°C
SS = 2446 PCS
VDD = +5.5V
LOGIC = +2.4V
ALL DIGITAL PINS
TIED TOGETHER
10k
IDD SUPPLY CURRENT – µA
FREQUENCY
840
5
Figure 11. Shutdown Current vs. Temperature
1200
960
–15
TEMPERATURE – °C
Figure 8. Differential Nonlinearity Error vs. Code
1080
–35
720
600
480
260
240
1k
100
10
VDD = +5.5V
LOGIC = +5.5V
ALL DIGITAL PINS
TIED TOGETHER
1
0.1
0.01
120
0.001
–55
0
–3.4
–3.3
–3.2
–3.1
–3.0
–2.9
–2.8
–2.7 –2.6
–2.5
TOTAL UNADJUSTED ERROR – LSB
–35
–15
5
25
45
65
TEMPERATURE – °C
85
105
125
Figure 12. Supply Current vs. Temperature
Figure 9. Total Unadjusted Error Histogram
–6–
REV. A
AD8801/AD8803
TA = +25°C
ALL DIGITAL INPUTS
TIED TOGETHER
10
1.0
OUTPUT2 – 10mV/DIV
IDD SUPPLY CURRENT – mA
100
VDD = +5V
0.1
0.01
OUTPUT1: OOH → FFH
VDD = +5V
VREF = +2V
f = 500kHz
100
90
10
0%
VDD = +3V
0.001
TIME – 0.2µs/DIV
0.0001
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
LOGIC INPUT VOLTAGE – Volts
Figure 13. Supply Current vs. Logic Input Voltage
Figure 16. Adjacent Channel Clock Feedthrough
80
VDD = +5V ±0.5V P
VREFH = +2V
CODE = 80H
TA = +25°C
PSRR – dB
60
100
90
OUTPUT1: 7FH → 80H
VDD = +5V
VREF = +2V
OUT1
10mV/DIV
40
CS
5V/DIV
10
0%
20
TIME – 0.2µs/DIV
0
10
100
1k
10k
100k
FREQUENCY – Hz
Figure 17. Midscale Transition
Figure 14. Power Supply Rejection vs. Frequency
CHANGE IN ZERO-SCALE ERROR – LSB
0.01
VDD = +5V
VREF = +2V
2V
100
90
OUT1
0V
5V
CS
10
0%
0V
TIME – 1µs/DIV
VDD = +4.5V
VREF = +4.5V
SS = 162 PCS
VREFL = 0V
0.005
0
–0.005
–0.01
0
150
300
450
600
HOURS OF OPERATION AT 150°C
Figure 18. Zero-Scale Error Accelerated by Burn-In
Figure 15. Large-Signal Settling Time
REV. A
–7–
AD8801/AD8803
1.0
VDD = +4.5V
VREF = +4.5V
SS = 162 PCS
x + 2σ
INPUT RESISTANCE DRIFT – kΩ
CHANGE IN FULL-SCALE ERROR – LSB
0.04
0.02
x
0
x – 2σ
–0.02
–0.04
0.5
x + 2σ
x
0
x – 2σ
–0.5
–1.0
0
150
300
450
600
VDD = +4.5V
VREF = +4.5V
CODE = 55H
SS = 162 PCS
0
150
300
450
600
HOURS OF OPERATION AT 150°C
HOURS OF OPERATION AT 150°C
Figure 20. REF Input Resistance Accelerated by Burn-In
Figure 19. Full-Scale Error Accelerated by Burn-In
+5V
APPLICATIONS
Supply Bypassing
Precision analog products, such as the AD8801/AD8803, require a well filtered power source. Since the AD8801/AD8803
operate from a single +3 V to +5 V supply, it seems convenient
to simply tap into the digital logic power supply. Unfortunately,
the logic supply is often a switch-mode design, which generates
noise in the 20 kHz to 1 MHz range. In addition, fast logic gates
can generate glitches hundred of millivolts in amplitude due to
wiring resistances and inductances.
VDD
+
10µF
Figure 22. Recommended Supply Bypassing for the
AD8801/AD8803
Buffering the AD8801/AD8803 Output
In many cases, the nominal 5 kΩ output impedance of the
AD8801/AD8803 is sufficient to drive succeeding circuitry. If a
lower output impedance is required, an external amplifier can
be added. Several examples are shown in Figure 23. One amplifier of an OP291 is used as a simple buffer to reduce the output
resistance of DAC A. The OP291 was chosen primarily for its
rail-to-rail input and output operation, but it also offers operation to less than 3 V, low offset voltage, and low supply current.
TTL/CMOS
LOGIC
CIRCUITS
10µF
TANT
0.1µF
AD8801/
AD8803
DGND
If possible, the AD8801/AD8803 should be powered directly
from the system power supply. This arrangement, shown in Figure 21, will isolate the analog section from the logic switching
transients. Even if a separate power supply trace is not available,
however, generous supply bypassing will reduce supply-line induced errors. Local supply bypassing consisting of a 10 µF tantalum electrolytic in parallel with a 0.1 µF ceramic capacitor is
recommended (Figure 22).
+
0.1µF
AD8801/
AD8803
The next two DACs, B and C, are configured in a summing arrangement where DAC C provides the coarse output voltage
setting and DAC B can be used for fine adjustment. The insertion of R1 in series with DAC B attenuates its contribution to
the voltage sum node at the DAC C output.
+5V
POWER SUPPLY
Figure 21. Use Separate Traces to Reduce Power Supply
Noise
–8–
REV. A
AD8801/AD8803
+5V
Microcomputer Interfaces
VREFH VDD
The AD8801/AD8803 serial data input provides an easy interface to a variety of single-chip microcomputers (µCs). Many µCs
have a built-in serial data capability that can be used for communicating with the DAC. In cases where no serial port is provided, or it is being used for some other purpose (such as an
RS-232 communications interface), the AD8801/AD8803 can
easily be addressed in software.
OP291
VH
SIMPLE BUFFER
0V TO 5V
VL
VH
VL
R1
100kΩ
VH
Eleven data bits are required to load a value into the AD8801/
AD8803 (3 bits for the DAC address and 8 bits for the DAC
value). If more than 11 bits are transmitted before the Chip Select input goes high, the extra (i.e., the most-significant) bits are
ignored. This feature is valuable because most µCs only transmit
data in 8-bit increments. Thus, the µC will send 16 bits to the
DAC instead of 11 bits. The AD8801/AD8803 will only respond to the last 11 bits clocked into the SDI input, however, so
the serial data interface is not affected.
SUMMER CIRCUIT
WITH FINE TRIM
ADJUSTMENT
VL
AD8801/
AD8803
VREFL GND
DIGITAL INTERFACING
OMITTED FOR CLARITY
Figure 23. Buffering the AD8801/AD8803 Output
An 8051 µC Interface
A typical interface between the AD8801/AD8803 and an 8051
µC is shown in Figure 25. This interface uses the 8051’s internal
serial port. The serial port is programmed for Mode 0 operation, which functions as a simple 8-bit shift register. The 8051’s
Port3.0 pin functions as the serial data output, while Port3.1
serves as the serial clock.
Increasing Output Voltage Swing
An external amplifier can also be used to extend the output voltage swing beyond the power supply rails of the AD8801/AD8803.
This technique permits an easy digital interface for the DAC,
while expanding the output swing to take advantage of higher
voltage external power supplies. For example, DAC A of Figure 24 is configured to swing from –5 V to +5 V. The actual
output voltage is given by:
VOUT
(
+5V
+
)
0.1µF
R
= 1 + F × D × 5 V – 5 V
RS
256
10µF
VDD VREFH
Where D is the DAC input value (i.e., 0 to 255). This circuit
can be combined with the “fine/coarse” circuit of Figure 23 if,
for example, a very accurate adjustment around 0 V is desired.
SBUF
SERIAL DATA SHIFT REGISTER
SHIFT CLOCK
RxD
P3.0
TxD
P3.1
AD8801
SDI
O1
SCLK
O2
O3
P1.3
8051 µC
+5V
RS
100kΩ
RF
100kΩ
P1.2
P1.1
+5V
RESET
O5
SHDN
O6
O7
CS
O8
VREFH
VDD
O4
PORT 1
1.3 1.2 1.1
–5V TO +4.98V
A
GND
OP191
–5V
AD8801/
AD8803
Figure 25. Interfacing the 8051 µ C to an AD8801/AD8803,
Using the Serial Port
+12V
OP193
When data is written to the Serial Buffer Register (SBUF, at
Special Function Register location 99H), the data is automatically converted to serial format and clocked out via Port3.0 and
Port3.1. After 8 bits have been transmitted, the Transmit Interrupt flag (SCON.1) is set and the next 8 bits can be transmitted.
B
0V TO +10V
GND
VREFL
100kΩ
100kΩ
The AD8801 and AD8803 require the Chip Select to go low at
the beginning of the serial data transfer. In addition, the SCLK
input must be high when the Chip Select input goes high at the
end of the transfer. The 8051’s serial clock meets this requirement, since Port3.1 both begins and ends the serial data in the
high state.
Figure 24. Increasing Output Voltage Swing
DAC B of Figure 24 is in a noninverting gain of two configuration, which increases the available output swing to +10 V. The
feedback resistors can be adjusted to provide any scaling of the
output voltage, within the limits of the external op amp power
supplies.
REV. A
Software for the 8051 Interface
A software routine for the AD8801/AD8803 to 8051 interface is
shown in Listing 1. The routine transfers the 8-bit data stored at
data memory location DAC_VALUE to the AD8801/AD8803
DAC addressed by the contents of location DAC_ADDR.
–9–
AD8801/AD8803
;
; This subroutine loads an AD8801/AD8803 DAC from an 8051 microcomputer,
; using the 8051’s serial port in MODE 0 (Shift Register Mode).
; The DAC value is stored at location DAC_VAL
; The DAC address is stored at location DAC_ADDR
;
; Variable declarations
;
PORT1
DATA
90H
DAC_VALUE
DATA
40H
DAC_ADDR
DATA
41H
SHIFT1
DATA
042H
SHIFT2
DATA
043H
SHIFT_COUNT
DATA
44H
;
ORG
100H
DO_8801:
CLR
SCON.7
CLR
SCON.6
CLR
SCON.5
CLR
SCON.1
ORL
PORT1.1,#00001110B
CLR
PORT1.1
MOV
SHIFT1,DAC_ADDR
ACALL
BYTESWAP
MOV
SBUF,SHIFT2
ADDR_WAIT:
JNB
SCON.1,ADDR_WAIT
CLR
SCON.1
MOV
SHIFT1,DAC_VALUE
ACALL
BYTESWAP
MOV
SBUF,SHIFT2
VALU_WAIT:
JNB
SCON.1,VALU_WAIT
CLR
SCON.1
SETB
PORT1.1
RET
;
BYTESWAP:
MOV
SHIFT_COUNT,#8
SWAP_LOOP:
MOV
A,SHIFT1
RLC
A
MOV
SHIFT1,A
MOV
A,SHIFT2
RRC
A
MOV
SHIFT2,A
DJNZ
SHIFT_COUNT,SWAP_LOOP
RET
END
;SFR register for port 1
;DAC Value
;DAC Address
;high byte of 16-bit answer
;low byte of answer
;
;arbitrary start
;set serial
; data mode 0
;clr transmit flag
;/RS, /SHDN, /CS high
;set the /CS low
;put DAC value in shift register
;
;send the address byte
;wait until 8 bits are sent
;clear the serial transmit flag
;send the DAC value
;
;
;wait again
;clear serial flag
;/CS high, latch data
; into AD8801
;Shift 8 bits
;Get source byte
;Rotate MSB to carry
;Save new source byte
;Get destination byte
;Move carry to MSB
;Save
;Done?
Listing 1. Software for the 8051 to AD8801/AD8803 Serial Port Interface
–10–
REV. A
AD8801/AD8803
The subroutine begins by setting appropriate bits in the Serial
Control register to configure the serial port for Mode 0 operation. Next the DAC’s Chip Select input is set low to enable the
AD8801/AD8803. The DAC address is obtained from memory
location DAC_ADDR, adjusted to compensate for the 8051’s
serial data format, and moved to the serial buffer register. At
this point, serial data transmission begins automatically. When
all 8 bits have been sent, the Transmit Interrupt bit is set, and
the subroutine then proceeds to send the DAC value stored at
location DAC_VALUE. Finally the Chip Select input is returned high, causing the appropriate AD8801/AD8803 output
voltage to change, and the subroutine ends.
The BYTESWAP routine in Listing 1 is convenient because the
DAC data can be calculated in normal LSB form. For example,
producing a ramp voltage on a DAC is simply a matter of repeatedly incrementing the DAC_VALUE location and calling
the LD_8801 subroutine.
If the µC’s hardware serial port is being used for other purposes,
the AD8801/AD8803 can be loaded by using the parallel port.
A typical parallel interface is shown in Figure 26. The serial data
is transmitted to the DAC via the 8051’s Port1.7 output, while
Port1.6 acts as the serial clock.
The 8051 sends data out of its shift register LSB first, while the
AD8801/AD8803 require data MSB first. The subroutine therefore includes a BYTESWAP subroutine to reformat the data.
This routine transfers the MSB-first byte at location SHIFT1 to
an LSB-first byte at location SHIFT2. The routine rotates the
MSB of the first byte into the carry with a Rotate Left Carry instruction, then rotates the carry into the MSB of the second byte
with a Rotate Right Carry instruction. After 8 loops, SHIFT2
contains the data in the proper format.
Software for the interface of Figure 26 is contained in Listing 2. The
subroutine will send the value stored at location DAC_VALUE to
the AD8801/AD8803 DAC addressed by location DAC_ADDR.
The program begins by setting the AD8801/AD8803’s Serial
Clock and Chip Select inputs high, then setting Chip Select low
to start the serial interface process. The DAC address is loaded
into the accumulator and three Rotate Right shifts are performed. This places the DAC address in the 3 MSBs of the accumulator. The address is then sent to the AD8801/AD8803 via
the SEND_SERIAL subroutine. Next, the DAC value is loaded
into the accumulator and sent to the AD8801/AD8803. Finally,
the Chip Select input is set high to complete the data transfer.
; This 8051 µC subroutine loads an AD8801 or AD8803 DAC with an 8-bit value,
; using the 8051’s parallel port #1.
; The DAC value is stored at location DAC_VALUE
; The DAC address is stored at location DAC_ADDR
;
; Variable declarations
PORT1
DATA
90H
DAC_VALUE
DATA
40H
DAC_ADDR
DATA
41H
LOOPCOUNT
DATA
43H
;
ORG
100H
LD_8803:
ORL
PORT1,#11110000B
CLR
PORT1.5
MOV
LOOPCOUNT,#3
MOV
A,DAC_ADDR
RR
A
RR
A
RR
A
ACALL
SEND_SERIAL
MOV
LOOPCOUNT,#8
MOV
A,DAC_VALUE
ACALL
SEND_SERIAL
SETB
PORT1.5
RET
SEND_SERIAL:
RLC
MOV
CLR
SETB
DJNZ
RET;
END
A
PORT1.7,C
PORT1.6
PORT1.6
LOOPCOUNT,SEND_SERIAL
;SFR register for port 1
;DAC Value
;DAC Address (0 through 7)
;COUNT LOOPS
;arbitrary start
;set CLK, /CS and /SHDN high,
;Set Chip Select low
;Address is 3 bits
; Get DAC address
; Rotate the DAC
;address to the Most
;Significant Bits (MSBs)
;Send the address
;Do 8 bits of data
;Send the data
;Set /CS high
;DONE
;Move next bit to carry
;Move data to SDI
;Pulse the
; CLK input
;Loop if not done
Listing 2. Software for the 8051 to AD8801/AD8803 Parallel Port Interface
REV. A
–11–
AD8801/AD8803
+5V
VDD
8051 µC
MC68HC11*
VREFH
AD8803
SDI
P1.6
P1.5
P1.4
PORT 1 1.7 1.6 1.5 1.4
(PD3) MOSI
SDI
(PD4) SCK
CLK
O1
P1.7
CLK
(PD5) SS
O2
O3
AD8801/
AD8803*
CS
PC0
SHDN
PC1
RS (AD8801 ONLY)
O4
CS
O5
O6
SHDN
O7
*ADDITIONAL PINS OMITTED FOR CLARITY
O8
GND VREFL
Figure 27. An AD8801/AD8803-to-MC68HC11 Interface
Figure 26. An AD8801/AD8803-8051 µ C Interface Using
Parallel Port 1
Unlike the serial port interface of Figure 25, the parallel port interface only transmits 11 bits to the AD8801/AD8803. Also, the
BYTESWAP subroutine is not required for the parallel interface, because data can be shifted out MSB first. However, the
results of the two interface methods are exactly identical. In
most cases, the decision on which method to use will be determined by whether or not the serial data port is available for
communication with the AD8801/AD8803.
An MC68HC11-to-AD8801/AD8803 Interface
Like the 8051, the MC68HC11 includes a dedicated serial data
port (labeled SPI). The SPI port provides an easy interface to
the AD8801/AD8803 (Figure 27). The interface uses three lines
of Port D for the serial data, and one or two lines from Port C
to control the SHDN and RS (AD8801 only) inputs.
A software routine for loading the AD8801/AD8803 from a
68HC11 evaluation board is shown in Listing 3. First, the
MC68HC11 is configured for SPI operation. Bits CPHA and
CPOL define the SPI mode wherein the serial clock (SCK) is
high at the beginning and end of transmission, and data is valid
on the rising edge of SCK. This mode matches the requirements
of the AD8801/AD8803. After the registers are saved on the
stack, the DAC value and address are transferred to RAM and
the AD8801/AD8803’s CS is driven low. Next, the DAC’s address byte is transferred to the SPDR register, which automatically initiates the SPI data transfer. The program tests the SPIF
bit and loops until the data transfer is complete. Then the DAC
value is sent to the SPI. When transmission of the second byte is
complete, CS is driven high to load the new data and address
into the AD8801/AD8803.
–12–
REV. A
AD8801/AD8803
*
* AD8801/AD8803 to M68HC11 Interface Assembly Program
*
* M68HC11 Register definitions
*
PORTC
EQU
$1003
Port C control register
*
“0,0,0,0;0,0,RS/, SHDN/”
DDRC
EQU
$1007
Port C data direction
PORTD
EQU
$1008
Port D data register
*
“0,0,/CS,CLK;SDI,0,0,0”
DDRD
EQU
$1009
Port D data direction
SPCR
EQU
$1028
SPI control register
*
“SPIE,SPE,DWOM,MSTR;CPOL,CPHA,SPR1,SPR0”
SPSR
EQU
$1029
SPI status register
*
“SPIF,WCOL,0,MODF;0,0,0,0”
SPDR
EQU
$102A
SPI data register; Read-Buffer; Write-Shifter
*
* SDI RAM variables:
SDI1 is encoded from 0 (Hex) to 7 (Hex)
*
SDI2 is encoded from 00 (Hex) to FF (Hex)
*
AD8801/3 requires two 8-bit loads; upper 5 bits
*
of SDI1 are ignored. AD8801/3 address bits in last
*
three LSBs of SDI1.
*
SDI1
EQU
$00
SDI packed byte 1 “0,0,0,0;0,A2,A1,A0”
SDI2
EQU
$01
SDI packed byte 2 “DB7,DB6,DB5,DB4;DB3,DB2,DB1,DB0”
*
* Main Program
*
ORG
$C000
Start of user’s RAM in EVB
INIT
LDS
#$CFFF
Top of C page RAM
*
* Initialize Port C Outputs
*
LDAA
#$03
0,0,0,0;0,0,1,1
*
/RS-Hi, /SHDN-Hi
STAA
PORTC
Initialize Port C Outputs
LDAA
#$03
0,0,0,0;0,0,1,1
STAA
DDRC
/RS and /SHDN are now enabled as outputs
*
* Initialize Port D Outputs
*
LDAA
#$20
0,0,1,0;0,0,0,0
*
/CS-Hi,/CLK-Lo,SDI-Lo
STAA
PORTD
Initialize Port D Outputs
LDAA
#$38
0,0,1,1;1,0,0,0
STAA
DDRD
/CS,CLK, and SDI are now enabled as outputs
*
* Initialize SPI Interface
*
LDAA
#$53
STAA
SPCR
SPI is Master,CPHA=0,CPOL=0,Clk rate=E/32
*
* Call update subroutine
*
BSR
UPDATE
Xfer 2 8-bit words to AD8402
JMP
$E000
Restart BUFFALO
*
* Subroutine UPDATE
*
UPDATE
PSHX
Save registers X, Y, and A
REV. A
–13–
AD8801/AD8803
PSHY
PSHA
*
* Enter Contents of SDI1 Data Register
*
LDAA
$0000
Hi-byte data loaded from memory
STAA
SDI1
SDI1 = data in location 0000H
*
* Enter Contents of SDI2 Data Register
*
LDAA
$0001
Low-byte data loaded from memory
STAA
SDI2
SDI2 = Data in location 0001H
*
LDX
#SDI1
Stack pointer at 1st byte to send via SDI
LDY
#$1000
Stack pointer at on-chip registers
*
* Reset AD8801 to one-half scale (AD8803 does not have a Reset input)
*
BCLR
PORTC,Y $02
Assert /RS
BSET
PORTC,Y $02
De-assert /RS
*
* Get AD8801/03 ready for data input
*
BCLR
PORTD,Y $20
Assert /CS
*
TFRLP
LDAA
0,X
Get a byte to transfer via SPI
STAA
SPDR
Write SDI data reg to start xfer
*
WAIT
LDAA
SPSR
Loop to wait for SPIF
BPL
WAIT
SPIF is the MSB of SPSR
*
(when SPIF is set, SPSR is negated)
INX
Increment counter to next byte for xfer
CPX
#SDI2+1
Are we done yet ?
BNE
TFRLP
If not, xfer the second byte
*
* Update AD8801 output
*
BSET
PORTD,Y $20
Latch register & update AD8801
*
PULA
When done, restore registers X, Y & A
PULY
PULX
RTS
** Return to Main Program **
Listing 3. AD8801/AD8803 to MC68HC11 Interface Program Source Code
–14–
REV. A
AD8801/AD8803
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Plastic DIP Package (N-16)
0.840 (21.33)
0.745 (18.93)
16
9
1
8
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
0.325 (8.25)
0.300 (7.62)
0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.070 (1.77)
0.045 (1.15)
0.100
(2.54)
BSC
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
16-Pin Narrow Body SOIC Package (R-16A)
16
9
0.1574 (4.00)
0.1497 (3.80)
PIN 1
8
1
0.2440 (6.20)
0.2284 (5.80)
0.3937 (10.00)
0.3859 (9.80)
0.0196 (0.50)
x 45 °
0.0099 (0.25)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
REV. A
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0099 (0.25)
0.0075 (0.19)
–15–
8°
0°
0.0500 (1.27)
0.0160 (0.41)
–16–
PRINTED IN U.S.A.
C2026–18–4/95
工商网监
湘ICP备2023018690号
