Data Sheet
AD9114/AD9115/AD9116/AD9117
Dual Low Power, 8-/10-/12-/14-Bit TxDAC Digital-to-Analog Converters
FEATURES
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GENERAL DESCRIPTION
Power dissipation @ 3.3 V, 20 mA output
► 191 mW @ 10 MSPS
► 232 mW @ 125 MSPS
Sleep mode: 1.8 V, bypass DVDD with a 1.0 µF
capacitor. Do not connect external loads to DVDD.
Digital Inputs
Digital Input (LSB).
No Connect. These pins are not connected to the chip.
Data Input/Output Clock. Clock used to qualify input data.
Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
LVCMOS Sampling Clock Input.
Sampling Clock Supply Voltage Common.
Q DAC Output Common-Mode Level. When the internal on-chip (QRCML) is enabled, this pin is connected to the on-chip QRCML resistor.
It is recommended to leave this pin unconnected. When the internal on-chip (QRCML) is disabled, this pin is the common-mode load for Q
DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value
for this external resistor is 0 Ω.
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally.
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally.
25
AVSS
Analog Common.
26
AVDD
27
RLIP
Analog Supply Voltage Input (1.8 V to 3.3 V).
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally.
28
IOUTP
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29
30
31
IOUTN
RLIN
CMLI
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally.
I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is
recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common-mode load for I DAC
and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this
external resistor is 0 Ω.
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Rev. E | 11 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 7. AD9114 Pin Function Descriptions
Pin No.
Mnemonic
Description
32
FSADJQ/AUXQ
33
FSADJI/AUXI
34
REFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMAT
38
CS/PWRDN
39
40
DB7 (MSB)
DB6
EP (EPAD)
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-scale current output adjust
for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external
resistor is 4 kΩ for 8 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output.
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale current output adjust for
I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is
4 kΩ for 8 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output.
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in
internal reference mode (a 0.1 µF capacitor to AVSS is required).
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset
the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When
DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retimer, see the Retimer section.
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the
binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format.
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port.
Digital Input (MSB).
Digital Input.
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected
to this pad.
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Rev. E | 12 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. AD9115 Pin Configuration
Table 8. AD9115 Pin Function Description
Pin No.
Mnemonic
Description
1 to 4
DB[7:4]
Digital Inputs.
5
DVDDIO
Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6
DVSS
7
DVDD
8 to 10
DB[3:1]
Digital Common.
Digital Core Supply Voltage Output (1.8 V). If DVDDIO is 1.8 V, strap DVDD to DVDDIO. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 µF
capacitor. Do not connect external loads to DVDD.
Digital Inputs.
11
DB0 (LSB)
Digital Input (LSB).
12 to 15
NC
No Connect. These pins are not connected to the chip.
16
DCLKIO
Data Input/Output Clock. Clock used to qualify input data.
17
CVDD
Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18
CLKIN
LVCMOS Sampling Clock Input.
19
CVSS
20
CMLQ
21
RLQN
Sampling Clock Supply Voltage Common.
Q DAC Output Common-Mode Level. When the internal on-chip (QRCML) is enabled, this pin is connected to the on-chip QRCML resistor.
It is recommended to leave this pin unconnected. When the internal on-chip (QRCML) is disabled, this pin is the common-mode load for Q
DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value
for this external resistor is 0 Ω.
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally.
22
QOUTN
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23
QOUTP
24
RLQP
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally.
25
AVSS
Analog Common.
26
AVDD
27
RLIP
Analog Supply Voltage Input (1.8 V to 3.3 V).
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally.
28
IOUTP
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29
IOUTN
30
RLIN
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally.
31
CMLI
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I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It is
recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common-mode load for I DAC
Rev. E | 13 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 8. AD9115 Pin Function Description
Pin No.
Mnemonic
32
FSADJQ/AUXQ
33
FSADJI/AUXI
34
REFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMAT
38
CS/PWRDN
39
40
DB9 (MSB)
DB82
EP (EPAD)
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Description
and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value for this
external resistor is 0 Ω.
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-scale current output adjust
for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external
resistor is 4 kΩ for 8 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output.
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale current output adjust for
I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external resistor is
4 kΩ for 8 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output.
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in
internal reference mode (a 0.1 µF capacitor to AVSS is required).
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset
the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0. When
DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see the Retimer section.
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the
binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format.
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port.
Digital Input (MSB).
Digital Input.
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected
to this pad.
Rev. E | 14 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. AD9116 Pin Configuration
Table 9. AD9116 Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 4
DB[9:6]
Digital Inputs.
5
DVDDIO
Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6
DVSS
7
DVDD
8 to 12
DB[5:1]
Digital Common.
Digital Core Supply Voltage Output (1.8 V). If DVDDIO is 1.8 V, strap DVDD to DVDDIO. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 µF
capacitor. Do not connect external loads to DVDD.
Digital Inputs.
13
DB0 (LSB)
Digital Input (LSB).
14, 15
NC
No Connect. These pins are not connected to the chip.
16
DCLKIO
Data Input/Output Clock. Clock used to qualify input data.
17
CVDD
Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18
CLKIN
LVCMOS Sampling Clock Input.
19
CVSS
20
CMLQ
21
RLQN
Sampling Clock Supply Voltage Common.
Q DAC Output Common-Mode Level. When the internal on-chip (QRCML) is enabled, this pin is connected to the on-chip QRCML resistor.
It is recommended to leave this pin unconnected. When the internal on-chip (QRCML) is disabled, this pin is the common-mode load for Q
DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value
for this external resistor is 0 Ω.
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally.
22
QOUTN
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23
QOUTP
24
RLQP
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally.
25
AVSS
Analog Common.
26
AVDD
27
RLIP
Analog Supply Voltage Input (1.8 V to 3.3 V).
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally.
28
IOUTP
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29
IOUTN
30
RLIN
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally.
31
CMLI
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I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It
is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common mode load for I
Rev. E | 15 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 9. AD9116 Pin Function Descriptions
Pin No.
Mnemonic
32
FSADJQ/AUXQ
33
FSADJI/AUXI
34
REFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMAT
38
CS/PWRDN
39
40
DB11 (MSB)
DB10
EP (EPAD)
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Description
DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value
for this external resistor is 0 Ω.
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-scale current output adjust
for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external
resistor is 4 kΩ for 8 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output.
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale current output adjust
for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external
resistor is 4 kΩ for 8 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output.
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in
internal reference mode (a 0.1 µF capacitor to AVSS is required).
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset
the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0.
When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see the Retimer section.
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the
binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format.
Active Low Chip Select (). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port.
Digital Input (MSB).
Digital Input.
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected
to this pad.
Rev. E | 16 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. AD9117 Pin Configuration
Table 10. AD9117 Pin Function Descriptions
Pin No.
Mnemonic
Description
1 to 4
DB[11:8]
Digital Inputs.
5
DVDDIO
Digital I/O Supply Voltage Input (1.8 V to 3.3 V Nominal).
6
DVSS
7
DVDD
8 to 14
DB[7:1]
Digital Common.
Digital Core Supply Voltage Output (1.8 V). If DVDDIO is 1.8 V, strap DVDD to DVDDIO. If DVDDIO > 1.8 V, bypass DVDD with a 1.0 µF
capacitor. Do not connect external loads to DVDD.
Digital Inputs.
15
DB0 (LSB)
Digital Input (LSB).
16
DCLKIO
Data Input/Output Clock. Clock used to qualify input data.
17
CVDD
Sampling Clock Supply Voltage Input (1.8 V to 3.3 V). CVDD must be ≥ DVDD.
18
CLKIN
LVCMOS Sampling Clock Input.
19
CVSS
20
CMLQ
21
RLQN
Sampling Clock Supply Voltage Common.
Q DAC Output Common-Mode Level. When the internal on-chip (QRCML) is enabled, this pin is connected to the on-chip QRCML resistor.
It is recommended to leave this pin unconnected. When the internal on-chip (QRCML) is disabled, this pin is the common-mode load for Q
DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value
for this external resistor is 0 Ω.
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTN externally.
22
QOUTN
Complementary Q DAC Current Output. Full-scale current is sourced when all data bits are 0s.
23
QOUTP
24
RLQP
Q DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Load Resistor (62.5 Ω) to the CMLQ Pin. For the internal load resistor to be used, this pin should be tied to QOUTP externally.
25
AVSS
Analog Common.
26
AVDD
27
RLIP
Analog Supply Voltage Input (1.8 V to 3.3 V).
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTP externally.
28
IOUTP
I DAC Current Output. Full-scale current is sourced when all data bits are 1s.
29
IOUTN
30
RLIN
Complementary I DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Load Resistor (62.5 Ω) to the CMLI Pin. For the internal load resistor to be used, this pin should be tied to IOUTN externally.
31
CMLI
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I DAC Output Common-Mode Level. When the internal on-chip (IRCML) is enabled, this pin is connected to the on-chip IRCML resistor. It
is recommended to leave this pin unconnected. When the internal on-chip (IRCML) is disabled, this pin is the common-mode load for I
DAC and must be connected to AVSS through a resistor, see the Using the Internal Termination Resistors section. Recommended value
for this external resistor is 0 Ω.
Rev. E | 17 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 10. AD9117 Pin Function Descriptions
Pin No.
Mnemonic
Description
32
FSADJQ/AUXQ
33
FSADJI/AUXI
34
REFIO
35
RESET/PINMD
36
SCLK/CLKMD
37
SDIO/FORMAT
38
CS/PWRDN
39
40
DB13 (MSB)
DB12
EP (EPAD)
Full-Scale Current Output Adjust (FSADJQ). When the internal on chip (QRSET) is disabled, this pin is the full-scale current output adjust
for Q DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external
resistor is 4 kΩ for 8 mA output current.
Auxiliary Q DAC Output (AUXQ). When the internal on-chip (QRSET) is enabled, this pin is the auxiliary Q DAC output.
Full-Scale Current Output Adjust (FSADJI). When the internal on-chip (IRSET) is disabled, this pin is the full-scale current output adjust
for I DAC and must be connected to AVSS through a resistor, see the Theory of Operation section. Nominal value for this external
resistor is 4 kΩ for 8 mA output current.
Auxiliary I DAC Output (AUXI). When the internal on-chip (IRSET) is enabled, it is the auxiliary I DAC output.
Reference Input/Output. Serves as a reference input when the internal reference is disabled. Provides a 1.0 V reference output when in
internal reference mode (a 0.1 µF capacitor to AVSS is required).
This pin defines the operation mode of the part. A logic low (pull-down to DVSS) sets the part in SPI mode. Pulse RESET high to reset
the SPI registers to their default values.
A logic high (pull-up to DVDDIO) puts the device into pin mode (PINMD).
Clock Input for Serial Port (SCLK). In SPI mode, this pin is the clock input for the serial port.
Clock Mode (CLKMD). In pin mode, CLKMD determines the phase of the internal retiming clock. When DCLKIO = CLKIN, tie it to 0.
When DCLKIO ≠ CLKIN, pulse 0 to 1 to edge trigger the internal retime, see the Retimer section.
Serial Port Input/Output (SDIO). In SPI mode, this pin is the bidirectional data line for the serial port.
Format Pin (FORMAT). In pin mode, FORMAT determines the data format of digital data. A logic low (pull-down to DVSS) selects the
binary input data format. A logic high (pull-up to DVDDIO) selects the twos complement input data format.
Active Low Chip Select (CS). In SPI mode, this pin serves as the active low chip select.
Power-Down (PWRDN). In pin mode, a logic high (pull-up to DVDDIO) powers down the device, except for the SPI port.
Digital Input (MSB).
Digital Input.
The exposed pad is connected to AVSS and must be soldered to the ground plane. Exposed metal at the package corners is connected
to this pad.
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Rev. E | 18 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
IxOUTFS = 8 mA, maximum sample rate (125 MSPS), unless otherwise noted. DVDD is always at 1.8 V.
Figure 6. AD9117 Precalibration INL at 1.8 V, 8 mA (DVDD = 1.8 V)
Figure 9. AD9117 Postcalibration INL at 1.8 V, 8 mA (DVDD = 1.8 V)
Figure 7. AD9117 Precalibration DNL at 1.8 V, 8 mA (DVDD = 1.8 V)
Figure 10. AD9117 Postcalibration DNL at 1.8 V, 8 mA (DVDD = 1.8 V)
Figure 8. AD9117 Precalibration INL at 3.3 V, 20 mA (DVDD = 1.8 V)
Figure 11. AD9117 Postcalibration INL at 3.3 V, 20 mA (DVDD = 1.8 V)
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Rev. E | 19 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 12. AD9117 Precalibration DNL at 3.3 V, 20 mA
Figure 15. AD9117 Postcalibration DNL at 3.3 V, 20 mA
Figure 13. AD9116 Precalibration INL at 1.8 V, 8 mA
Figure 16. AD9116 Postcalibration INL at 1.8 V, 8 mA
Figure 14. AD9116 Precalibration DNL at 1.8 V, 8 mA
Figure 17. AD9116 Postcalibration DNL at 1.8 V, 8 mA
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Rev. E | 20 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 18. AD9116 Precalibration INL at 3.3 V, 20 mA
Figure 21. AD9116 Postcalibration INL at 3.3 V, 20 mA
Figure 19. AD9116 Precalibration DNL at 3.3 V, 20 mA
Figure 22. AD9116 Postcalibration DNL at 3.3 V, 20 mA
Figure 20. AD9115 Precalibration INL at 1.8 V, 8 mA
Figure 23. AD9115 Postcalibration INL at 1.8 V, 8 mA
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Rev. E | 21 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 24. AD9115 Precalibration DNL at 1.8 V, 8 mA
Figure 27. AD9115 Postcalibration DNL at 1.8 V, 8 mA
Figure 25. AD9115 Precalibration INL at 3.3 V, 20 mA
Figure 28. AD9115 Postcalibration INL at 3.3 V, 20 mA
Figure 26. AD9115 Precalibration DNL at 3.3 V, 20 mA
Figure 29. AD9115 Postcalibration DNL at 3.3 V, 20 mA
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Rev. E | 22 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 30. AD9114 Precalibration INL at 1.8 V, 8 mA
Figure 33. AD9114 Postcalibration INL at 1.8 V, 8 mA
Figure 31. AD9114 Precalibration DNL at 1.8 V, 8 mA
Figure 34. AD9114 Postcalibration DNL at 1.8 V, 8 mA
Figure 32. AD9114 Precalibration INL at 3.3 V, 20 mA
Figure 35. AD9114 Postcalibration INL at 3.3 V, 20 mA
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Rev. E | 23 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 36. AD9114 Precalibration DNL at 3.3 V, 20 mA
Figure 39. AD9114 Postcalibration DNL at 3.3 V, 20 mA
Figure 37. NSD at 8 mA vs. fOUT, 1.8 V
Figure 40. NSD at 20 mA vs. fOUT, 3.3 V
Figure 38. AD9117 NSD at Three Temperatures 8 mA vs. fOUT, 1.8 V
Figure 41. AD9117 NSD at Three Temperatures 8 mA vs. fOUT, 3.3 V
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Rev. E | 24 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 42. AD9117 NSD at Two Output Currents vs. fOUT, 1.8 V
Figure 45. AD9117 NSD at Three Output Currents vs. fOUT, 3.3 V
Figure 43. AD9117 Two Tone Spectrum at 1.8 V
Figure 46. AD9117 Two Tone Spectrum at 3.3 V
Figure 44. All IMD 8 mA vs. fOUT, 1.8 V
Figure 47. All IMD 20 mA vs. fOUT, 3.3 V
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Rev. E | 25 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 48. AD9117 IMD at Three Temperatures 8 mA vs. fOUT, 1.8 V
Figure 51. AD9117 IMD at Three Temperatures 20 mA vs. fOUT, 3.3 V
Figure 49. AD9117 IMD at Three Digital Signal Levels vs. fOUT, 1.8 V
Figure 52. AD9117 IMD at Three Digital Signal Levels vs. fOUT, 3.3 V
Figure 50. AD9117 IMD at Two Output Currents vs. fOUT, 1.8 V
Figure 53. AD9117 IMD at Three Output Currents vs. fOUT, 3.3 V
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Rev. E | 26 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 54. AD9117 Singe Tone Spectrum, 1.8 V
Figure 57. AD9117 Singe Tone Spectrum, 3.3 V
Figure 55. SFDR at 8 mA vs. fOUT, 1.8 V
Figure 58. AD9117 SFDR at 20 mA vs. fOUT, 3.3 V
Figure 56. AD9117 SFDR at Three Temperatures 8 mA vs. fOUT, 1.8 V
Figure 59. AD9117 SFDR at Three Temperatures 8 mA vs. fOUT, 3.3 V
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Rev. E | 27 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 60. AD9117 SFDR at Three Digital Signal Levels vs. fOUT, 1.8 V
Figure 63. AD9117 SFDR at Three Digital Signal Levels vs. fOUT., 3.3 V
Figure 61. AD9117 SFDR at Two Currents vs. fOUT, 1.8 V
Figure 64. AD9117 SFDR at Three Currents vs. fOUT, 3.3V
Figure 62. AD9117 ACLR One-Carrier, 1.8 V
Figure 65. AD9117 ACLR One-Carrier, 3.3 V
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Rev. E | 28 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 66. AD9117 One-Carrier W-CDMA First ACLR vs. fOUT, 1.8 V
Figure 69. AD9117 One-Carrier W-CDMA First ACLR vs. fOUT, 3.3 V
Figure 67. AD9117 One-Carrier W-CDMA Second ACLR vs. fOUT, 1.8 V
Figure 70. AD9117 One-Carrier W-CDMA Second ACLR vs. fOUT, 3.3 V
Figure 68. AD9117 One-Carrier W-CDMA Third ACLR vs. fOUT, 1.8 V
Figure 71. AD9117 One-Carrier W-CDMA Third ACLR vs. fOUT, 3.3 V
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Rev. E | 29 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 72. AD9117 ACLR Two-Carrier, 1.8 V
Figure 75. AD9117 ACLR Two-Carrier, 3.3 V
Figure 73. AD9117 Two-Carrier W-CDMA First ACLR vs. fOUT, 1.8 V
Figure 76. AD9117 Two-Carrier W-CDMA First ACLR vs. fOUT, 3.3 V
Figure 74. AD9117 Two-Carrier W-CDMA Second ACLR vs. fOUT, 1.8 V
Figure 77. AD9117 Two-Carrier W-CDMA Second ACLR vs. fOUT, 3.3 V
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Rev. E | 30 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 78. AD9117 Two-Carrier W-CDMA Third ACLR vs. fOUT, 1.8 V
Figure 81. AD9117 Two-Carrier W-CDMA Third ACLR vs. fOUT, 3.3 V
Figure 79. AD9114/AD9115/AD9116/AD9117 AUXDAC DNL
Figure 82. AD9114/AD9115/AD9116/AD9117 AUXDAC INL
Figure 80. AD9114/AD9115/AD9116/AD9117 Supply Current vs. fDAC, 1.8 V
Figure 83. AD9114/AD9115/AD9116/AD9117Supply Current vs. fDAC, 3.3 V
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Rev. E | 31 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
TERMINOLOGY
Linearity Error or Integral Nonlinearity (INL)
Settling Time
Linearity error is defined as the maximum deviation of the actual
analog output from the ideal output, determined by a straight line
drawn from zero scale to full scale.
Settling time is the time required for the output to reach and remain
within a specified error band around its final value, measured from
the start of the output transition.
Differential Nonlinearity (DNL)
Spurious Free Dynamic Range (SFDR)
DNL is the measure of the variation in analog value, normalized to
full scale, associated with a 1 LSB change in digital input code.
SFDR is the difference, in decibels (dB), between the peak amplitude of the output signal and the peak spurious signal between dc
and the frequency equal to half the input data rate.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
Offset error is the deviation of the output current from the ideal of
zero. For IOUTP, the 0 mA output is expected when the inputs are all
0. For IOUTN, the 0 mA output is expected when all inputs are set to
1.
Gain Error
Gain error is the difference between the actual and the ideal output
span. The actual span is determined by the difference between the
output when all inputs are set to 1 and the output when all inputs
are set to 0.
Output Compliance Range
The output compliance range is the range of allowable voltage at
the output of a current output DAC. Operation beyond the maximum
compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient value (25°C) to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale range
per degree Celsius (ppm FSR/°C). For reference drift, the drift is
reported in parts per million per degree Celsius (ppm/°C).
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is
expressed as a percentage (%) or in decibels (dB).
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value for
SNR is expressed in decibels (dB).
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in decibels relative to the carrier (dBc) between
the measured power within a channel relative to its adjacent channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect of
wasting transmitter power and system bandwidth. By placing the
real part of a second complex modulator in series with the first
complex modulator, either the upper or lower frequency image near
the second IF can be rejected.
Power Supply Rejection
Power supply rejection is the maximum change in the full-scale
output as the supplies are varied from minimum to maximum
specified voltages.
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Rev. E | 32 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
THEORY OF OPERATION
Figure 84. Simplified Block Diagram
Figure 84 shows a simplified block diagram of the AD9114/AD9115/
AD9116/AD9117 that consists of two DACs, digital control logic,
and a full-scale output current control. Each DAC contains a PMOS
current source array capable of providing a maximum of 20 mA.
The arrays are divided into 31 equal currents that make up the
five most significant bits (MSBs). The next four bits, or middle bits,
consist of 15 equal current sources whose value is 1/16 of an MSB
current source. The remaining LSBs are binary weighted fractions
of the current sources of the middle bits. Implementing the middle
and lower bits with current sources, instead of an R-2R ladder,
enhances its dynamic performance for multitone or low amplitude
signals and helps maintain the high output impedance of the main
DACs (that is, >200 MΩ).
The current sources are switched to one or the other of the two output nodes (IOUTP or IOUTN) via PMOS differential current switches.
The switches are based on the architecture that was pioneered
in the AD976x family, with further refinements to reduce distortion
contributed by the switching transient. This switch architecture also
reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches.
The analog and digital I/O sections of the AD9114/AD9115/AD9116/
AD9117 have separate power supply inputs (AVDD, DVDDIO, and
CVDD) that can operate independently over a 1.8 V to 3.3 V range.
The core digital section (DVDD) requires 1.8 V. For an operating
supply voltage of 1.8 V at DVDDIO, DVDD can be strapped to
DVDDIO. Otherwise, for an operating supply voltage of >1.8 V at
DVDDIO, the on-chip LDO for the digital block must be enabled and
DVDD pin must be bypassed with a 0.1 μF capacitor. To ensure
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proper operation of the device, the RESET/PINMD pin must be
pulsed high after applying power to all supplies. If operating the
device in SPI mode, the minimum duration before setting the pin
low is 50 ns. If operating the device in pin mode, there is no need
to set RESET/PINMD low after pulsing it high and, alternatively, the
pin can be pulled up to DVDDIO.
The core is capable of operating at a rate of up to 125 MSPS. It
consists of edge-triggered latches and the segment decoding logic
circuitry. The analog section includes PMOS current sources, associated differential switches, a 1.0 V band gap voltage reference, and
a reference control amplifier.
Each DAC full-scale output current is regulated by the reference
control amplifier and can be set from 4 mA to 20 mA via an external
resistor, xRSET, connected to its full-scale adjust pin (FSADJx).
The external resistor, in combination with both the reference control
amplifier and voltage reference, VREFIO, sets the reference current,
IxREF, which is replicated to the segmented current sources with the
proper scaling factor. The full-scale current, IxOUTFS, is 32 × IxREF.
Optional on-chip xRSET resistors are provided that can be programmed between a nominal value of 1.6 kΩ to 8 kΩ (20 mA to 4 mA
IxOUTFS, respectively).
The AD9114/AD9115/AD9116/AD9117 provide the option of setting
the output common mode to a value other than AGND via the output common-mode pin (CMLI and CMLQ). This facilitates directly
interfacing the output of the AD9114/AD9115/AD9116/AD9117 to
components that require common-mode levels greater than 0 V.
Rev. E | 33 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
SERIAL PERIPHERAL INTERFACE (SPI)
The serial port of the AD9114/AD9115/AD9116/AD9117 is a flexible, synchronous serial communications port that allows easy
interfacing to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous
transfer formats, including both the Motorola SPI and Intel® SSR
protocols. The interface allows read/write access to all registers that
configure the AD9114/AD9115/AD9116/AD9117. Single or multiple
byte transfers are supported, as well as MSB first or LSB first
transfer formats. The serial interface port of the AD9114/AD9115/
AD9116/AD9117 is configured as a single I/O pin on the SDIO pin.
R/W (Bit 7 of the instruction byte) determines whether a read or a
write data transfer occurs after the instruction byte write. Logic 1
indicates a read operation. Logic 0 indicates a write operation.
N1 and N0 (Bit 6 and Bit 5 of the instruction byte) determine the
number of bytes to be transferred during the data transfer cycle.
The bit decodes are shown in Table 12.
Table 12. Byte Transfer Count
N1
N0
Description
0
0
Transfer 1 byte
GENERAL OPERATION OF THE SERIAL
INTERFACE
0
1
Transfer 2 bytes
1
0
Transfer 3 bytes
There are two phases to a communication cycle on the AD9114/
AD9115/AD9116/AD9117. Phase 1 is the instruction cycle, which is
the writing of an instruction byte into the AD9114/AD9115/AD9116/
AD9117, coinciding with the first eight SCLK rising edges. In Phase
2, the instruction byte provides the serial port controller of the
AD9114/AD9115/AD9116/AD9117 with information regarding the
data transfer cycle. The Phase 1 instruction byte defines whether
the upcoming data transfer is a read or write, the number of bytes
in the data transfer, and the starting register address for the first
byte of the data transfer. The first eight SCLK rising edges of each
communication cycle are used to write the instruction byte into the
AD9114/AD9115/AD9116/AD9117.
1
1
Transfer 4 bytes
To ensure that SPI registers are set to default after power-up, a
Logic 1 with a minimum pulse width of 50 ns, followed by a Logic
0, must be applied on Pin 35 (RESET/PINMD). This also resets the
SPI port timing to the initial state of the instruction cycle. This is true
regardless of the present state of the internal registers or the other
signal levels present at the inputs to the SPI port. If the SPI port is
in the midst of an instruction cycle or a data transfer cycle, none of
the present data is written.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9114/
AD9115/AD9116/AD9117 and the system controller. Phase 2 of the
communication cycle is a transfer of one, two, three, or four data
bytes, as determined by the instruction byte. Using a multibyte
transfer is the preferred method. Single byte data transfers are
useful to reduce CPU overhead when register access requires one
byte only. Registers change immediately upon writing to the last bit
of each transfer byte.
A4, A3, A2, A1, and A0 (Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of
the instruction byte) determine which register is accessed during
the data transfer portion of the communications cycle. For multibyte
transfers, this address is the starting byte address. The following
register addresses are generated internally by the AD9114/AD9115/
AD9116/AD9117 based on the LSBFIRST bit (Register 0x00, Bit 6).
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from
the AD9114/AD9115/AD9116/AD9117 and to run the internal state
machines. The SCLK maximum frequency is 25 MHz. All data input
to the AD9114/AD9115/AD9116/AD9117 is registered on the rising
edge of SCLK. This is shown in Figure 85 and Figure 87 for write
instructions where the SCLK rising edges are lined up in the middle
of the data. All data is driven out of the AD9114/AD9115/AD9116/
AD9117 on the falling edge of SCLK. This is shown in Figure 86
and Figure 88 for read cycles where the SCLK falling edges are
lined up with the change in data in the data transfer cycle.
CS—Chip Select
An active low input starts and gates a communications cycle. It
allows more than one device to be used on the same serial communications lines. The SDIO/FORMAT pin reaches a high impedance
state when this input is high. Chip select should stay low during the
entire communication cycle.
INSTRUCTION BYTE
SDIO—Serial Data I/O
The instruction byte contains the information shown in Table 11.
The SDIO pin is used as a bidirectional data line to transmit and
receive data.
Table 11.
MSB
LSB
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
R/W
N1
N0
A4
A3
A2
A1
A0
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MSB/LSB TRANSFERS
The serial port of the AD9114/AD9115/AD9116/AD9117 can support
both most significant bit (MSB) first or least significant bit (LSB) first
data formats. This functionality is controlled by the LSBFIRST bit
(Register 0x00, Bit 6). The default is MSB first (LSBFIRST = 0).
Rev. E | 34 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
SERIAL PERIPHERAL INTERFACE (SPI)
When LSBFIRST = 0 (MSB first), the instruction and data bytes
must be written from the most significant bit to the least significant
bit. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant
data byte. Subsequent data bytes should follow in order from a
high address to a low address. In MSB first mode, the serial port
internal byte address generator decrements for each data byte of
the multibyte communications cycle.
When LSBFIRST = 1 (LSB first), the instruction and data bytes
must be written from the least significant bit to the most significant
bit. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant
data byte followed by multiple data bytes. The serial port internal
byte address generator increments for each byte of the multibyte
communication cycle.
If the MSB first mode is active, the serial port controller data
address of the AD9114/AD9115/AD9116/AD9117 decrements from
the data address written toward 0x00 for multibyte I/O operations.
If the LSB first mode is active, the serial port controller address
increments from the data address written toward 0x1F for multibyte
I/O operations.
SERIAL PORT OPERATION
The serial port configuration of the AD9114/AD9115/AD9116/
AD9117 is controlled by Register 0x00. It is important to note that
the configuration changes immediately upon writing to the last bit
of the register. For multibyte transfers, writing to this register can
occur during the middle of the communications cycle. Care must be
taken to compensate for this new configuration for the remaining
bytes of the current communications cycle.
The same considerations apply to setting the software reset bit
(Register 0x00, Bit 5). All registers are set to their default values
except Register 0x00, which remains unchanged.
Use of single-byte transfers or initiating a software reset is recommended when changing serial port configurations to prevent
unexpected device behavior.
Figure 87. Serial Register Interface Timing, LSB First Write
Figure 88. Serial Register Interface Timing, LSB First Read
PIN MODE
The AD9114/AD9115/AD9116/AD9117 can also be operated without ever writing to the serial port. With RESET/PINMD (Pin 35) tied
high, the SCLK pin becomes CLKMD to provide for clock mode
control (see the Retimer section), the SDIO pin becomes FORMAT
and selects the input data format, and the CS/PWRDN pin serves
to power down the device. The pins are not latched at power-up. If
the data format is changed, it is required to wait 1μs after power-up
to ensure proper function.
Operation is otherwise exactly as defined by the default register
values in Table 13; therefore, external resistors at FSADJI and
FSADJQ are needed to set the DAC currents, and both DACs
are active. This is also a convenient quick checkout mode. DAC
currents can be externally adjusted in pin mode by sourcing or
sinking currents at the FSADJI/AUXI and FSADJQ/AUXQ pins, as
desired, with the fixed resistors installed. An op amp output with
appropriate series resistance is one of many possibilities. This has
the same effect as changing the resistor value. Place at least 10
kΩ resistors in series right at the DAC to guard against accidental
short circuits and noise modulation. The REFIO pin can be adjusted
±25% in a similar manner, if desired.
Figure 85. Serial Register Interface Timing, MSB First Write
Figure 86. Serial Register Interface Timing, MSB First Read
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Rev. E | 35 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
SPI REGISTER MAP
Table 13.
Name
Addr
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
SPI Control
0x00
0x00
Reserved
LSBFIRST
Reset
LNGINS
Bit 2
Bit 1
Bit 0
Reserved
Power-Down
0x01
0x40
LDOOFF
LDOSTAT
PWRDN
Q DACOFF
I DACOFF
QCLKOFF
ICLKOFF
EXTREF
Data Control
0x02
0x34
TWOS
Reserved
IFIRST
IRISING
SIMULBIT
DCI_EN
DCOSGL
DCODBL
I DAC Gain
0x03
0x00
IRSET
0x04
0x00
IRSETEN
Reserved
Reserved
I DACGAIN[5:0]
IRSET[5:0]
IRCML
0x05
0x00
IRCMLEN
Reserved
IRCML[5:0]
Q DAC Gain
0x06
0x00
QRSET
0x07
0x00
QRSETEN
Reserved
QRSET[5:0]
QRCML
0x08
0x00
QRCMLEN
Reserved
QRCML[5:0]
AUXDAC I
0x09
0x00
AUX CTL I
0x0A
0x00
AUXDAC Q
0x0B
0x00
AUX CTL Q
0x0C
0x00
Reference Resistor
0x0D
0x00
Reserved
Q DACGAIN[5:0]
IAUXDAC[7:0]
IAUXEN
IAUXRNG[1:0]
QAUXEN
QAUXRNG[1:0]
IAUXDAC[9:8]
QAUXDAC[7:0]
QAUXOFS[2:0]
Reserved
Cal Control
0x0E
0x00
PRELDQ
PRELDI
Cal Memory
0x0F
0x00
CALSTATQ
CALSTATI
Memory Address
0x10
0x00
Memory Data
0x11
0x3F
Memory R/W
0x12
0x00
CLKMODE
0x14
0x00
Version
0x1F
0x0A
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IAUXOFS[2:0]
RREF[5:0]
CALSELQ
CALSELI
CALCLK
Reserved
CLKMODEQ[1:0]
CALMEMI[1:0]
MEMADDR[5:0]
Reserved
CALRSTI
DIVSEL[2:0]
CALMEMQ[1:0]
Reserved
CALRSTQ
QAUXDAC[9:8]
MEMDATA[5:0]
CALEN
Searching
SMEMWR
SMEMRD
Reacquire
CLKMODEN
UNCALQ
UNCALI
CLKMODEI[1:0]
Version[7:0]
Rev. E | 36 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
SPI REGISTER DESCRIPTIONS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 14.
Register
Address
Bit
Name
Description
SPI Control
0x00
6
LSBFIRST
0 (default): MSB first per SPI standard.
Reset
1: LSB first per SPI standard.
Note that the user must always change the LSB/MSB order in single-byte instructions to avoid erratic behavior
due to bit order errors.
Executes software reset of SPI and controllers, reloads default register values, except Register 0x00.
5
1: set software reset; write 0 on the next (or any following) cycle to release reset.
4
LNGINS
0 (default): the SPI instruction word uses a 5-bit address.
1: the SPI instruction word uses a 13-bit address.
Power-Down
0x01
7
LDOOFF
0 (default): LDO voltage regulator on.
1: turns core LDO voltage regulator off.
6
LDOSTAT
0: indicates that the core LDO voltage regulator is off.
1 (default): indicates that the core LDO voltage regulator is on.
5
PWRDN
0 (default): all analog, digital circuitry and SPI logic are powered on.
1: powers down all analog and digital circuitry, except for SPI logic.
4
Q DACOFF
0 (default): turns on Q DAC output current.
1: turns off Q DAC output current.
3
I DACOFF
0 (default): turns on I DAC output current.
1: turns off I DAC output current.
2
QCLKOFF
0 (default): turns on Q DAC clock.
1: turns off Q DAC clock.
1
ICLKOFF
0 (default): turns on I DAC clock.
1: turns off I DAC clock.
0
EXTREF
0 (default): turns on internal voltage reference.
1: powers down the internal voltage reference (external reference required).
Data Control
0x02
7
TWOS
0 (default): Unsigned binary input data format.
1: twos complement input data format.
5
IFIRST
0: pairing of data—Q first of pair on data input pads.
1 (default): pairing of data—I first of pair on data input pads (default).
4
IRISING
0: Q data latched on DCLKIO rising edge.
1 (default): I data latched on DCLKIO rising edge (default).
3
SIMULBIT
0 (default): allows simultaneous input and output enable on DCLKIO.
1: disallows simultaneous input and output enable on DCLKIO.
2
DCI_EN
Controls the use of the DCLKIO pad for the data clock input.
0: data clock input disabled.
1 (default): data clock input enabled.
1
DCOSGL
Controls the use of the DCLKIO pad for the data clock output.
0 (default): data clock output disabled.
1: data clock output enabled; regular strength driver.
0
DCODBL
Controls the use of the DCLKIO pad for the data clock output.
0 (default): DCODBL data clock output disabled.
1: DCODBL data clock output enabled; paralleled with DCOSGL for 2× drive current.
I DAC Gain
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0x03
5:0
I DACGAIN[5:0]
DAC I fine gain adjustment; alters the full-scale current, as shown in Figure 100. Default IDACGAIN = 0x00.
Rev. E | 37 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
SPI REGISTER DESCRIPTIONS
Table 14.
Register
Address
Bit
Name
Description
IRSET
0x04
7
IRSETEN
5:0
IRSET[5:0]
0 (default): disables on-chip IRSET resistor value for I channel. IRSET is set by an external resistor connected to
the FSADJI/AUXI pin. Nominal value for this external resistor is 4 kΩ.
1: enables the on-chip IRSETand allows its value to be changed for I channel.
Changes the value of the on-chip IRSET resistor; this scales the full-scale current of the DAC in ~0.25 dB steps
twos complement (nonlinear), see Figure 99.
000000 (default): IRSET = 2 kΩ.
011111: IRSET = 8 kΩ.
100000: IRSET = 1.6 kΩ.
111111: IRSET = 2 kΩ.
IRCML
0x05
7
IRCMLEN
5:0
IRCML[5:0]
0 (default): disables the on-chip IRCML resistor value for the I channel. IRCML is set by an external resistor
connected to CMLI pin. Recommended value for this external resistor is 0 Ω.
1: enables on-chip IRCML and allows adjustment for I channel.
Changes the value of the on-chip IRCML resistor for I channel; this adjusts the common-mode level of the DAC
output stage.
000000 (default): IRCML = 60 Ω.
100000: IRCML = 160 Ω.
111111: IRCML = 260 Ω.
Q DAC Gain
0x06
5:0
QRSET
0x07
7
5:0
Q DACGAIN[5:0] DAC Q fine gain adjustment; alters the full-scale current, as shown in Figure 100. Default QDACGAIN = 0x00.
0 (default): disables on-chip QRSET resistor for Q channel. QRSET is set by an external resistor connected to the
QRSETEN
FSADJI/AUXI pin. Nominal value for this external resistor is 4 kΩ.
1: enables the on-chip QRSET and allows its value to be changed for Q channel.
Changes the value of the on-chip QRSET resistor; this scales the full-scale current of the DAC in ~0.25 dB steps
QRSET[5:0]
twos complement (nonlinear).
000000 (default): QRSET = 2 kΩ.
011111: QRSET = 8 kΩ.
100000: QRSET = 1.6 kΩ.
111111: QRSET = 2 kΩ.
QRCML
0x08
7
QRCMLEN
5:0
QRCML[5:0]
0 (default): disables on-chip QRCML resistor for the Q channel. QRCML is set by an external resistor connected to
CMLQ pin. Recommended value for this external resistor is 0 Ω.
1: enables on-chip QRCML and allows adjustment for the Q channel.
Changes the value of the on-chip QRCML resistor for Q channel; this adjusts the common-mode level of the DAC
output stage.
000000 (default): QRCML = 60 Ω.
100000: QRCML = 160 Ω.
111111: QRCML = 260 Ω.
AUXDAC I
0x09
7:0
IAUXDAC[7:0]
8 LSBs for the 10-bit AUXDAC I output voltage adjustment word. Set MSBs in Register 0x0A, Bits[1:0].
0x3FF: sets AUXDAC I output to full scale.
0x200: sets AUXDAC I output to midscale.
0x000 (default): sets AUXDAC I output to bottom of scale.
AUX CTL I
0x0A
7
IAUXEN
6:5
IAUXRNG[1:0]
0 (default): AUXDAC I output disabled.
1: enables AUXDAC I output.
00 (default): sets AUXDAC I output voltage range to 2 V.
01: sets AUXDAC I output voltage range to 1.5 V.
10: sets AUXDAC I output voltage range to 1.0 V.
11: sets AUXDAC I output voltage range to 0.5 V.
4:2
IAUXOFS[2:0]
000 (default): sets AUXDAC I top of range to 1.0 V.
001: sets AUXDAC I top of range to 1.5 V.
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Rev. E | 38 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
SPI REGISTER DESCRIPTIONS
Table 14.
Register
Address
Bit
Name
Description
010: sets AUXDAC I top of range to 2.0 V.
011: sets AUXDAC I top of range to 2.5 V.
100: sets AUXDAC I top of range to 2.9 V.
AUXDAC Q
0x0B
1:0
IAUXDAC[9:8]
2 MSBs for 10-bit AUXDAC I output voltage adjustment word (default = 00). Set LSBs in Register 0x09, Bits[7:0].
7:0
QAUXDAC[7:0]
8 LSBs for 10-bit AUXDAC Q output voltage adjustment word. Set MSBs in Register 0x0C, Bits[1:0]
0x3FF: sets AUXDAC Q output to full scale.
0x200: sets AUXDAC Q output to midscale.
0x000 (default): sets AUXDAC Q output to bottom of scale.
AUX CTLQ
0x0C
7
QAUXEN
6:5
QAUXRNG[1:0]
0 (default): AUXDAC Q output disabled.
1: enables AUXDAC Q output.
00 (default): sets AUXDAC Q output voltage range to 2 V.
01: sets AUXDAC Q output voltage range to 1.5 V.
10: sets AUXDAC Q output voltage range to 1.0 V.
11: sets AUXDAC Q output voltage range to 0.5 V.
4:2
QAUXOFS[2:0]
000 (default): sets AUXDAC Q top of range to 1.0 V.
001: sets AUXDAC Q top of range to 1.5 V.
010: sets AUXDAC Q top of range to 2.0 V.
011: sets AUXDAC Q top of range to 2.5 V.
100: sets AUXDAC Q top of range to 2.9 V.
Reference
Resistor
0x0D
1:0
QAUXDAC[9:8]
2 MSBs for 10-bit AUX DAC Q output voltage adjustment word (default = 00). Set LSBs in Register 0x0B,
Bits[7:0].
5:0
RREF[5:0]
Permits an adjustment of the on-chip reference voltage and output at REFIO (see Figure 98) twos complement.
000000 (default): sets the value of RREF to 10 kΩ, VREF = 1.0 V.
011111: sets the value of RREF to 12 kΩ, VREF = 1.2 V.
100000: sets the value of RREF to 8 kΩ, VREF = 0.8 V.
111111: sets the value of RREF to 10 kΩ, VREF = 1.0 V.
Cal Control
0x0E
7
PRELDQ
0 (default): preloads Q DAC calibration reference set to 32.
1: preloads Q DAC calibration reference set by user (Cal Address 1).
6
PRELDI
0 (default): preloads I DAC calibration reference set to 32.
1: preloads I DAC calibration reference set by user (Cal Address 1).
5
CALSELQ
0 (default): Q DAC self-calibration done.
1: selects Q DAC self-calibration.
4
CALSELI
0 (default): I DAC self-calibration done.
1: selects I DAC self-calibration.
3
CALCLK
0 (default): calibration clock disabled.
1: calibrates clock enabled.
2:0
DIVSEL[2:0]
Calibration clock divide ratio from DAC clock rate.
000 (default): divide by 256.
001: divide by 128.
…
110: divide by 4.
111: divide by 2.
Cal Memory
0x0F
7
CALSTATQ
0 (default): Q DAC calibration in progress.
1: calibration of Q DAC complete.
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Rev. E | 39 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
SPI REGISTER DESCRIPTIONS
Table 14.
Register
Address
Bit
Name
Description
6
CALSTATI
0 (default): I DAC calibration in progress.
1: calibration of I DAC complete.
3:2
CALMEMQ[1:0]
Status of Q DAC calibration memory.
00 (default): uncalibrated.
01: self-calibrated.
10: user-calibrated.
1:0
CALMEMI[1:0]
Status of I DAC calibration memory.
00 (default): uncalibrated.
01: self-calibrated.
10: user-calibrated.
Memory Address
0x10
5:0
MEMADDR[5:0]
Address of static memory to be accessed.
Memory Data
0x11
5:0
MEMDATA[5:0]
Data for static memory access.
Memory R/W
0x12
7
CALRSTQ
0 (default): no action.
6
CALRSTI
4
CALEN
3
SMEMWR
2
SMEMRD
1
UNCALQ
0
UNCALI
7:6
CLKMODEQ[1:0]
Depending on CLKMODEN bit setting, these two bits reflect the phase relationship between DCLKIO and CLKIN,
as described in Table 16.
Searching
If CLKMODEN = 0, read only; reports the clock phase chosen by the retime.
If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if needed to better synchronize
the DACs (see the Retimer section).
Datapath retimer status bit.
3
Reacquire
0 (default): clock relationship established.
1: indicates that the internal datapath retimer is searching for clock relationship(device output is not usable while
this bit is high).
Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship.
2
CLKMODEN
1: clears CALSTATQ.
0 (default): no action.
1: clears CALSTATI.
0 (default): no action.
1: initiates device self-calibration.
0 (default): no action.
1: writes to static memory (calibration coefficients).
0 (default): no action.
1: reads from static memory (calibration coefficients).
0 (default): no action.
1: resets Q DAC calibration coefficients to default (uncalibrated).
0 (default): no action.
1: resets I DAC calibration coefficients to default (uncalibrated).
CLKMODE
0x14
4
Version
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0x1F
1:0
CLKMODEI[1:0]
7:0
Version[7:0]
0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and read back in CLKMODEI[1:0] and
CLKMODEQ[1:0].
1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers.
Depending on CLKMODEN bit setting, these two bits reflect the phase relationship between DCLKIO and CLKIN,
as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
Hardware version of the device. This register is set to 0x0A for the latest version of the device.
Rev. E | 40 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
DIGITAL INTERFACE OPERATION
Digital data for the I and Q DACs is supplied over a single parallel
bus (DB[n:0], where n is 7 for the AD9114, is 9 for the AD9115,
is 11 for the AD9116, and 13 for the AD9117) accompanied by
a qualifying clock (DCLKIO). The I and Q data are provided to
the chip in an interleaved double data rate (DDR) format. The
maximum guaranteed data rate is 250 MSPS with a 125 MHz clock.
The order of data pairing and the sampling edge selection is user
programmable using the IFIRST and IRISING data control bits,
resulting in four possible timing diagrams. These timing diagrams
are shown in Figure 89, Figure 90, Figure 91, and Figure 92.
Figure 92. Timing Diagram with IFIRST = 1, IRISING = 1
Ideally, the rising and falling edges of the clock fall in the center of
the keep-in window formed by the setup and hold times, tS and tH.
Refer to Table 2 for setup and hold times. A detailed timing diagram
is shown in Figure 93.
Figure 89. Timing Diagram with IFIRST = 0, IRISING = 0
Figure 93. Setup and Hold Times for All Input Modes
Figure 90. Timing Diagram with IFIRST = 0, IRISING = 1
In addition to the different timing modes listed in Table 2, the input
data can also be presented to the device in either unsigned binary
or twos complement format. The format type is chosen via the
TWOS data control bit.
Figure 91. Timing Diagram with IFIRST = 1, IRISING = 0
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Rev. E | 41 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
DIGITAL INTERFACE OPERATION
Figure 94. Simplified Diagram of AD9114/AD9115/AD9116/AD9117 Timing
DIGITAL DATA LATCHING AND RETIMER
SECTION
DCI_EN, to logic low causes the CLKIN to be used as the DCLKIO
also.
The AD9114/AD9115/AD9116/AD9117 have two clock inputs,
DCLKIO and CLKIN. The CLKIN is the analog clock whose jitter
affects DAC performance, and the DCLKIO is a digital clock from
an FPGA that needs to have a fixed relationship with the input data
to ensure that the data is sampled correctly by the flip-flops on the
pads.
Setting Bit 1 or Bit 0 of SPI Address 0x02, DCOSGL or DCODBL, to
logic high allows the user to get a DCLKIO output from the CLKIN
input for use in the user’s PCB system.
Figure 94 is a simplified diagram of the entire data capture system
in the AD9114/AD9115/AD9116/AD9117. The double data rate input
data (DB[n:0], where n is 7 for the AD9114, is 9 for the AD9115,
is 11 for the AD9116, and 13 for the AD9117) is latched at the pads/
pins either on the rising edge or the falling edge of the DCLKIO-INT
clock, as determined by IRISING, Bit 4 of SPI Address 0x02. Bit
5 of SPI Address 0x02, IFIRST, determines which channel data is
latched first (that is, I or Q). The captured data is then retimed
to the internal clock (CLKIN-INT) in the retimer block before being
sent to the final analog DAC core (D-FF 4), which controls the
current steering output switches. All delay blocks depicted in Figure
94 are non-inverting, and any wires without an explicit delay block
can be assumed to have no delay.
It is strongly recommended that DCI_EN = DCOSGL = high, or
DCI_EN = DCODBL = high not be used, even though the device
may appear to function correctly. Similarly, DCOSGL and DCODBL
should not be set to logic high simultaneously.
Retimer
The AD9114/AD9115/AD9116/AD9117 have an internal data retimer
circuit that compares the CLKIN-INT and DCLKIO-INT clocks and,
depending on their phase relationship, selects a retimer clock
(RETIMER-CLK) to safely transfer data from the DCLKIO used at
the chip’s input interface to the CLKIN used to clock the analog
DAC cores (D-FF 4).
The retimer selects one of the three phases shown in Figure 95.
The retimer is controlled by the CLKMODE SPI bits as is shown in
Table 15.
Only one channel is shown in Figure 94 with the data pads
(DB[n:0], where n is 7 for the AD9114, is 9 for the AD9115, is
11 for the AD9116, and 13 for the AD9117) serving as double data
rate pads for both channels.
The default PINMD and SPI settings are IE = high (closed) and OE
= low (open). These settings are enabled when RESET/PINMD (Pin
35) is held high. In this mode, the user has to supply both DCLKIO
and CLKIN. In PINMD, it is also recommended that the DCLKIO
and the CLKIN be in phase for proper functioning of the DAC, which
can easily be ensured by tying the pins together on the PCB. If
the user can access the SPI, setting Bit 2 of SPI Address 0x02,
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Figure 95. RETIMER-CLK Phases
Rev. E | 42 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
DIGITAL INTERFACE OPERATION
Note that, in most cases, more than one retimer phase works
and, in such cases, the retimer arbitrarily picks one phase that
works. The retimer cannot pick the best or safest phase. If the
user has a working knowledge of the exact phase relationship between DCLKIO and CLKIN (and thus DCLKIO-INT and CLKIN‑INT
because the delay is approximately the same for both clocks and
equal to DELAY1), then the retimer can be forced to this phase
with CLKMODEN = 1, as described in Table 15 and the following
paragraphs.
Table 15. Timer Register List
Bit Name
Description
CLKMODEQ[1:0]
Q datapath retimer clock selected output. Valid after the searching bit goes low.
Searching
High indicates that the internal datapath retimer is searching for the clock relationship (DAC is not usable until it is low again).
Reacquire
Changing this bit from 0 to 1 causes the datapath retimer circuit to reacquire the clock relationship.
CLKMODEN
0: Uses the CLKMODEI/CLKMODEQ values (as computed by the two internal retimers) for I and Q clocking.
CLKMODEI[1:0]
1: Uses the CLKMODE value set in CLKMODEI[1:0] to override the bits for both the I and Q retimers (that is, force the retimer).
I datapath retimer clock selected output. Valid after searching goes low. If CLKMODEN = 1, a value written to this register overrides both I and Q
automatic retimer values.
Table 16. CLKMODEI/CLKMODEQ Details
CLKMODEI[1:0]/CLKMODEQ[1:0]
DCLKIO-to-CLKIN Phase Relationship
RETIMER-CLK Selected
00
0° to 90°
Phase 2
01
90° to 180°
Phase 3
10
180° to 270°
Phase 3
11
270° to 360°
Phase 1
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Rev. E | 43 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
DIGITAL INTERFACE OPERATION
When RESET is pulsed high and then returns low (the part is in
SPI mode), the retimer runs and automatically selects a suitable
clock phase for the RETIMER-CLK within 128 clock cycles. The SPI
searching bit, Bit 4 of SPI Address 0x14, returns to low, indicating
that the retimer has locked and the part is ready for use. The reacquire bit, Bit 3 of SPI Address 0x14, can be used to reinitiate phase
detection in the I and Q retimers at any time. CLKMODEQ[1:0] and
CLKMODEI[1:0] bits of SPI Address 0x14 provide readback for the
values picked by the internal phase detectors in the retimer (see
Table 16).
To force the two retimers (I and Q) to pick a particular phase for
the retimer clock (they must both be forced to the same value),
CLKMODEN, Bit 2 of the SPI Address 0x14, should be set high
and the required phase value is written into CLKMODEI[1:0]. For
example, if the DCLKIO and the CLKIN are in phase to first order,
the user could safely force the retimers to pick Phase 2 for the RETIMER-CLK. This forcing function may be useful for synchronizing
multiple devices.
In pin mode, it is expected that the user tie CLKIN and DCLKIO
together. The device has a small amount of programmable functionality using the now unused SPI pins (SCLK, SDIO, and CS). If
the two chip clocks are tied together, the SCLK pin can be tied to
ground, and the chip uses a clock for the retimer that is 180° out
of phase with the two input clocks (that is, Phase 2, which is the
safest and best option). The chip has an additional option in pin
mode when the redefined SCLK pin is high. Use this mode if using
pin mode, but CLKIN and DCLKIO are not tied together (that is,
not in phase). Holding SCLK high causes the internal clock detector
to use the phase detector output to determine which clock to use
in the retimer (that is, select a suitable RETIMER‑CLK phase).
The action of taking SCLK high causes the internal phase detector
to reexamine the two clocks and determine the relative phase.
Whenever the user wants to reevaluate the relative phase of the
two clocks, the SCLK pin can be taken low and then high again.
ESTIMATING THE OVERALL DAC PIPELINE
DELAY
DAC pipeline latency is affected by the phase of the RETIMER-CLK
that is selected. If latency is critical to the system and must be
constant, the retimer should be forced to a particular phase and not
be allowed to automatically select a phase each time.
Consider the case in which DCLKIO = CLKIN (that is, in phase),
and the RETIMER-CLK is forced to Phase 2. Assume that IRISING
is 1 (that is, I data is latched on the rising edge and Q data is
latched on the falling edge). Then the latency to the output for the
I channel is four clock cycles total; one clock cycle from the input
interface (D-FF 1, not D-FF0 as it latches data on either edge and
does not cause any delay), two clock cycles from the retimer (D-FF
2 and D-FF 4, but not D-FF 3 because it is latched on the half
clock cycle or 180°), and one clock cycle going through the analog
core (D-FF 5). The latency to the output for the Q channel from the
time the falling edge latches it at the pads in D-FF 0 is 3.5 clock
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cycles (no delay due to D-FF0, 1 clock cycle due to D-FF 1, ½ clock
cycle to D-FF 2, 1 clock cycle to D-FF 4, and 1 clock cycle to D-FF
5). This latency for the AD9114/AD9115/AD9116/AD9117 is case
specific and needs to be calculated based on the RETIMER-CLK
phase that is automatically selected or manually forced.
REFERENCE OPERATION
The AD9114/AD9115/AD9116/AD9117 contain an internal 1.0 V
band gap reference. The internal reference can be disabled by
setting Bit 0 (EXTREF) of the power-down register (Address 0x01)
through the SPI interface. To use the internal reference, decouple
the REFIO pin to AVSS with a 0.1 μF capacitor, enable the internal
reference, and clear Bit 0 of the power-down register (Address
0x01) through the SPI interface. Note that this is the default configuration. The internal reference voltage is present at REFIO and
ramps up for around 2 ms when the proper power-up conditions in
the Power Supply section are followed. If the voltage at REFIO is
to be used anywhere else in the circuit, an external buffer amplifier
with an input bias current of less than 100 nA must be used to
avoid loading the reference. An example of the use of the internal
reference is shown in Figure 96.
Figure 96. Internal Reference Configuration
REFIO serves as either an input or an output, depending on
whether the internal or an external reference is used. Table 17
summarizes the reference operation.
Table 17. Reference Operation
Reference Mode
REFIO Pin
Register Setting
Internal
Connect 0.1 µF
capacitor
Apply external
reference
Register 0x01, Bit 0 = 0
(default)
Register 0x01, Bit 0 = 1 (for
power saving)
External
An external reference is required in applications needing gain tolerances with minimal variation or lower temperature drift. In addition,
a variable external voltage reference can be used to implement a
method for gain control of the DAC output.
Recommendations When Using an External
Reference
Apply the external reference to the REFIO pin. The internal reference can be directly overdriven by the external reference, or the
Rev. E | 44 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
DIGITAL INTERFACE OPERATION
internal reference can be powered down to save power consumption.
The external 0.1 µF compensation capacitor on REFIO is not
required unless specified by the external voltage reference manufacturer. The input impedance of REFIO is 10 kΩ when the internal
reference is powered up and 1 MΩ when it is powered down.
The ADR130 precision voltage reference or equivalent is recommended with the analog supply connected to AVDD, as shown in
Figure 97.
current. The current outputs appearing at the positive DAC outputs,
IOUTP and QOUTP, and at the negative DAC outputs, IOUTN and
QOUTN, are a function of both the input code and IxOUTFS and can
be expressed as follows:
IOUTP = (IDAC CODE/2N) × IIOUTFS
(1)
QOUTP = (QDAC CODE/2N) × IQOUTFS
IOUTN = ((2N − 1) − IDAC CODE)/2N × IIOUTFS
QOUTN = ((2N − 1) − QDAC CODE)/2N × I
(2)
QOUTFS
where:IDAC CODE and QDAC CODE = 0 to 2N − 1 (that is, decimal
representation).
IIOUTFS and IQOUTFS are functions of the reference currents, IIREF
and IQREF, respectively, which are nominally set by a reference voltage, VREFIO, and external resistors, IRSET and QRSET, respectively.
IIOUTFS and IQOUTFS can be expressed as follows:
Figure 97. External Reference Configuration
REFERENCE CONTROL AMPLIFIER
The AD9114/AD9115/AD9116/AD9117 contain a control amplifier
that regulates the full-scale output current, IxOUTFS. The control
amplifier is configured as a V-I converter, as shown in Figure 96.
The output current, IxREF, is determined by the ratio of the VREFIO
and an external resistor, xRSET, as stated in Equation 4 (see the
DAC Transfer Function section). IxREF is mirrored to the segmented
current sources with the proper scale factor to set IxOUTFS, as stated
in Equation 3 (see the DAC Transfer Function section).
The control amplifier allows a 10:1 adjustment span of IxOUTFS from
2 mA to 20 mA by setting IxREF between 62.5 µA and 625 µA
(xRSET between 1.6 kΩ and 16 kΩ). When using a resistor larger
than 4 kΩ, split the resistor with 4 kΩ plus the additional resistance
needed, for example, 16 kΩ made of a 4 kΩ + 12 kΩ combination,
and add a 1 µF capacitor from 4 kΩ to ground. The wide adjustment
span of IxOUTFS provides several benefits. The first relates directly
to the power dissipation of the AD9114/AD9115/AD9116/AD9117,
which is proportional to IxOUTFS (see the DAC Transfer Function
section). The second benefit relates to the ability to adjust the
output over a 8 dB range with 0.25 dB steps, which is useful for
controlling the transmitted power. The small signal bandwidth of the
reference control amplifier is approximately 500 kHz. This allows
the device to be used for low frequency, small signal multiplying
applications.
DAC TRANSFER FUNCTION
The AD9114/AD9115/AD9116/AD9117 provides two differential current outputs, IOUTP/IOUTN and QOUTP/ QOUTN. IOUTP and
QOUTP provide a near full-scale current output, IxOUTFS, when all
bits are high (that is, DAC CODE = 2N − 1, where N = 8, 10, 12,
or 14 for the AD9114, AD9115, AD9116, and AD9117, respectively),
while IOUTN and QOUTN, the complementary outputs, provide no
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IIOUTFS = 32 × IIREF
(3)
IQOUTFS = 32 × IQREF
where:
IIREF = VREFIO/IRSET
(4)
IQREF = VREFIO/QRSET
or
IIOUTFS = 32 × VREFIO/IRSET
(5)
IQOUTFS = 32 × VREFIO/QRSET
A differential pair (IOUTP/IOUTN or QOUTP/QOUTN) typically
drives a resistive load directly or via a transformer. If dc coupling
is required, the differential pair (IOUTP/IOUTN or QOUTP/QOUTN)
should be connected to matching resistive loads, xRLOAD, that are
tied to analog common, AVSS. The single-ended voltage output
appearing at the positive and negative nodes is
VIOUTP = IOUTP × IRLOAD
(6)
VQOUTP = QOUTP × QRLOAD
VIOUTN = IOUTN × IRLOAD
(7)
VQOUTN = QOUTN × QRLOAD
To achieve 1 V p-p output at the nominal 20 mA output current,
IRLOAD = QRLOAD must be set to 50 Ω.
Substituting the values of IOUTP, IOUTN, IxREF, and VIDIFF can be
expressed as
VIDIFF = {(2 × IDAC CODE − (2N − 1))/2N} × (32 × VREFIO/
IRSET) × IRLOAD
(8)
Equation 8 highlights some of the advantages of operating the
AD9114/AD9115/AD9116/AD9117 differentially. First, the differential
operation helps cancel common-mode error sources associated
Rev. E | 45 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
DIGITAL INTERFACE OPERATION
with IOUTP and IOUTN, such as noise, distortion, and dc offsets.
Second, the differential code-dependent current and subsequent
voltage, VIDIFF, is twice the value of the single-ended voltage output
(that is, VIOUTP or VIOUTB), thus providing twice the signal power
to the load. Note that the gain drift temperature performance for a
single-ended output (VIOUTP and VIOUTN) or differential output of the
AD9114/AD9115/AD9116/AD9117 can be enhanced by selecting
temperature tracking resistors for xRLOAD and xRSET because of
their ratiometric relationship, as shown in Equation 8.
ANALOG OUTPUT
The complementary current outputs in each DAC, IOUTP/ IOUTN
and QOUTP/QOUTN, can be configured for single-ended or differential operation. IOUTP/IOUTN and QOUTP/ QOUTN can be
converted into complementary single-ended voltage outputs, VIOUTP
and VIOUTN as well as VQOUTP and VQOUTN, via a load resistor,
xRLOAD, as described in the DAC Transfer Function section by
Equation 6 through Equation 8. The differential voltages, VIDIFF
and VQDIFF, existing between VIOUTP and VIOUTN, and VQOUTP
and VQOUTN, can also be converted to a single-ended voltage
via a transformer or a differential amplifier configuration. The ac
performance of the AD9114/AD9115/AD9116/AD9117 is optimum
and is specified using a differential transformer-coupled output in
which the voltage swing at IOUTP and IOUTN is limited to ±0.5
V. The distortion and noise performance of the AD9114/AD9115/
AD9116/AD9117 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTP/
IOUTN and QOUTP/QOUTN can be significantly reduced by the
common-mode rejection of a transformer or differential amplifier.
These common-mode error sources include even-order distortion
products and noise.
The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform
increases and/or its amplitude increases. This is due to the firstorder cancellation of various dynamic common-mode distortion
mechanisms, digital feedthrough, and noise. Performing a differential-to-single-ended conversion via a transformer also provides the
ability to deliver twice the reconstructed signal power to the load
(assuming no source termination). Because the output currents
of IOUTP/IOUTN and QOUTP/QOUTN are complementary, they
become additive when processed differentially.
SELF-CALIBRATION
The AD9114/AD9115/AD9116/AD9117 have a self-calibration feature that improves the DNL of the device. Performing a self-calibration on the device improves device performance in low frequency
applications. The device performance in applications where the analog output frequencies are above 5 MHz are generally influenced
more by dynamic device behavior than by DNL and, in these
cases, self-calibration is unlikely to produce measurable benefits.
The calibration clock frequency is equal to the DAC clock divided
by the division factor chosen by the DIVSEL value. There is a
fixed pre-divider of 16 and it is multiplied by the DIVSEL, which
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has a range of divide by 2 -256. Each calibration clock cycle is
between 32 and 2048 DAC input clock cycles, depending on the
value of DIVSEL[2:0] (Register 0x0E, Bits[2:0]). The frequency of
the calibration clock should be between 0.5 MHz and 4 MHz for reliable calibrations. Best results are obtained by setting DIVSEL[2:0]
to produce a calibration clock frequency between these values.
Separate self-calibration hardware is included for each DAC. The
DACs can be self-calibrated individually or simultaneously.
To perform a device self-calibration, use the following procedure:
1. Write 0x00 to Register 0x12. This ensures that the UNCALI and
UNCALQ bits (Bit 1 and Bit 0) are reset.
2. Set up a calibration clock between 0.5 MHz and 4 MHz using
DIVSEL[2:0], and then enable the calibration clock by setting
the CALCLK bit (Register 0x0E, Bit 3).
3. Select the DAC(s) to self-calibrate by setting either Bit 4 (CALSELI) for the I DAC and/or Bit 5 (CALSELQ) for the Q DAC in
Register 0x0E. Note that each DAC contains independent calibration hardware so that they can be calibrated simultaneously.
4. Start self-calibration by setting Bit 4 (CALEN) in Register 0x12.
Wait approximately 300 calibration clock cycles.
5. Check if the self-calibration has completed by reading Bit 6
(CALSTATI) and Bit 7 (CALSTATQ) in Register 0x0F. Logic 1
indicates that the calibration has completed.
6. When the self-calibration has completed, write 0x00 to Register
0x12.
7. Disable the calibration clock by clearing Bit 3 (CALCLK) in
Register 0x0E.
The AD9114/AD9115/AD9116/AD9117 allow reading and writing of
the calibration coefficients. There are 32 coefficients in total. The
read/write feature of the coefficients can be useful for improving
the results of the self-calibration routine by averaging the results
of several self-calibration cycles and loading the averaged results
back into the device.
To read the calibration coefficients, use the following steps:
1. Select which DAC core to read by setting either Bit 4 (CALSELI)
for the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register
0x0E. Write the address of the first coefficient (0x01) to Register
0x10.
2. Set Bit 2 (SMEMRD) in Register 0x12 by writing 0x04 to
Register 0x12.
3. Read the 6-bit value of the first coefficient by reading the
contents of Register 0x11.
4. Clear the SMEMRD bit by writing 0x00 to Register 0x12.
5. Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by 1 for each read.
6. Deselect the DAC core by clearing either Bit 4 (CALSELI) for
the I DAC and/or Bit 5 (CALSELQ) for the Q DAC in Register
0x0E.
Rev. E | 46 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
DIGITAL INTERFACE OPERATION
To write the calibration coefficients to the device, use the following
steps:
mal variation or lower temperature drift, external temperature tracking resistors for FSADJx, xRLOAD and xRSET are recommended.
1. Select which DAC core to write to by setting either Bit 4
(CALSELI) for the I DAC or Bit 5 (CALSELQ) for the Q DAC in
Register 0x0E.
2. Set Bit 3 (SMEMWR) in Register 0x12 by writing 0x08 to
Register 0x12.
3. Write the address of the first coefficient (0x01) to Register 0x10.
4. Write the value of the first coefficient to Register 0x11.
5. Repeat Step 2 through Step 4 for each of the remaining 31
coefficients by incrementing the address by one for each write.
6. Clear the SMEMWR bit by writing 0x00 to Register 0x12.
7. Deselect the DAC core by clearing either Bit 4 (CALSELI) for
the I DAC or Bit 5 (CALSELQ) for the Q DAC in Register 0x0E.
COARSE GAIN ADJUSTMENT
Figure 99. Effect of xRSET Code
Option 1
A coarse full-scale output current adjustment can be achieved using
the lower six bits in Register 0x0D. This adds or subtracts up to
20% from the band gap voltage on Pin 34 (REFIO), and the voltage
on the FSADJx resistors tracks this change. As a result, the DAC
full-scale current varies by the same amount. A secondary effect
to changing the REFIO voltage is that the full-scale voltage in the
AUXDAC also changes by the same magnitude. The register uses
twos complement format, in which 011111 maximizes the voltage on
the REFIO node and 100000 minimizes the voltage.
Option 3
Even when the device is in pin mode, full-scale values can be
adjusted by sourcing or sinking current from the FSADJx pins. Any
noise injected here appears as amplitude modulation of the output.
Thus, a portion of the required series resistance (at least 20 kΩ)
must be installed right at the pin. A range of ±10% is quite practical
using this method.
Option 4
As in Option 3, when the device is in pin mode, both full-scale
values can be adjusted by sourcing or sinking current from the
REFIO pin. Noise injected here appears as amplitude modulation of
the output; therefore, a portion of the required series resistance (at
least 10 kΩ) must be installed at the pin. A range of ±25% is quite
practical when using this method.
Fine Gain
Figure 98. Typical VREF Voltage vs. Code
Option 2
Each main DAC has independent fine gain control using the lower
six bits in Register 0x03 (I DACGAIN[5:0]) and Register 0x06 (Q
DACGAIN[5:0]). Unlike Coarse Gain Option 1, this impacts only the
main DAC full-scale output current. These registers use straight
binary format. One application in which straight binary format is
critical is for side-band suppression while using a quadrature modulator. This is described in more detail in the Applications Information
section.
While using the internal FSADJx resistors, each main DAC can
achieve independently controlled coarse gain using the lower six
bits of Register 0x04 (IRSET[5:0]) and Register 0x07 (QRSET[5:0]).
Unlike Coarse Gain Option 1, this impacts only the main DAC
full-scale output current. The register uses twos complement format
and allows the output current to be changed in approximately
0.25 dB steps. For applications requiring gain tolerances with minianalog.com
Rev. E | 47 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
DIGITAL INTERFACE OPERATION
By default, the common-mode resistor is not connected. When
enabled, it can be adjusted from ~60 Ω to ~260 Ω. Each main DAC
has an independent adjustment using the lower six bits in Register
0x05 (IRCML[5:0]) and Register 0x08 (QRCML[5:0]).
Figure 100. Typical DAC Gain Characteristics
USING THE INTERNAL TERMINATION
RESISTORS
The AD9114/AD9115/AD9116/AD9117 have four 62.5 Ω termination
internal resistors (two for each DAC output). To use these resistors
to convert the DAC output current to a voltage, connect each DAC
output pin to the adjacent load pin. For example, on the I DAC,
IOUTP must be shorted to RLIP and IOUTN must be shorted to
RLIN. In addition, the CMLI or CMLQ pin must be connected to
ground directly or through a resistor. If the output current is at
the nominal 20 mA and the CMLI or CMLQ pin is tied directly
to ground, this produces a dc common-mode bias voltage on the
DAC output equal to 0.625 V. If the DAC dc bias must be higher
than 0.625 V, an external resistor can be connected between the
CMLI or CMLQ pin and ground. This part also has an internal
common-mode resistor that can be enabled. This is explained in the
Using the Internal Common-Mode Resistor section.
Figure 102. Typical CML Resistor Value vs. Register Code
Using the CMLx Pins for Optimal Performance
The CMLx pins also serve to change the DAC bias voltages in the
parts allowing them to run at higher dc output bias voltages. When
running the bias voltage below 0.9 V and an AVDD of 3.3 V, the
parts perform optimally when the CMLx pins are tied to ground.
When the dc bias increases above 0.9 V, set the CMLx pins at
0.5 V for optimal performance. The maximum dc bias on the DAC
output should be kept at or below 1.2 V when the supply is 3.3 V.
When the supply is 1.8 V, keep the dc bias close to 0 V and connect
the CMLx pins directly to ground.
Figure 101. Simplified Internal Load Options
Using the Internal Common-Mode Resistor
These devices contain an adjustable internal common-mode resistor that can be used to increase the dc bias of the DAC outputs.
analog.com
Rev. E | 48 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
APPLICATIONS INFORMATION
OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configurations
for the AD9114/AD9115/AD9116/AD9117. Unless otherwise noted,
it is assumed that IxOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential
output configuration is suggested.
A differential output configuration can consist of either an RF
transformer or a differential op amp configuration. The transformer
configuration provides the optimum high frequency performance
and is recommended for any application that allows ac coupling.
The differential op amp configuration is suitable for applications
requiring dc coupling, signal gain, and/or a low output impedance.
A single-ended output is suitable for applications in which low cost
and low power consumption are primary concerns.
DIFFERENTIAL COUPLING USING A
TRANSFORMER
An RF transformer can be used to perform a differential-to-singleended signal conversion, as shown in Figure 103. The distortion
performance of a transformer typically exceeds that available from
standard op amps, particularly at higher frequencies. Transformer
coupling provides excellent rejection of common-mode distortion
(that is, even-order harmonics) over a wide frequency range. It also
provides electrical isolation and can deliver voltage gain without
adding noise. Transformers with different impedance ratios can also
be used for impedance matching purposes. The main disadvantages of transformer coupling are low frequency roll-off, lack of power
gain, and high output impedance.
via a passive reconstruction filter or cable. RDIFF, as reflected by
the transformer, is chosen to provide a source termination that
results in a low voltage standing wave ratio (VSWR). Note that
approximately half the signal power is dissipated across RDIFF.
SINGLE-ENDED BUFFERED OUTPUT USING
AN OP AMP
Figure 104 shows a buffered single-ended output configuration in
which the ADA4899-1 op amp performs a current to voltage (I-V)
conversion on the AD9114/AD9115/AD9116/AD9117 output current.
The ADA4899-1 maintains IOUTN (or IOUTP) at a virtual ground,
minimizing the nonlinear output impedance effect on the INL performance of the DAC as described in the Analog Output section.
Although this single-ended configuration typically provides optimal
dc linearity performance, its ac distortion performance at higher
DAC update rates may be limited by the slew rate capabilities of
the op amp. The ADA4899-1 provides a negative unipolar output
voltage, and its full-scale output voltage is simply the product of
RFB (49.9 Ω) and IOUTFS. Set the full-scale output within the voltage
output swing capabilities of the AD9114/AD9115/AD9116/AD9117
by scaling IOUTFS and/or the feedback resistor, RFB. An improvement in ac distortion performance may result with a reduced IOUTFS
because the signal current at the op amp is required to sink less
signal current.
Figure 104. Unipolar Buffered Voltage Output
Figure 103. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be connected to a voltage that keeps the voltages on IOUTP and IOUTN
within the output common-mode voltage range of the device. Note
that the dc component of the DAC output current is equal to IIOUTFS
and flows out of both IOUTP and IOUTN. The center tap of the
transformer should provide a path for this dc current. In most
applications, AGND provides the most convenient voltage for the
transformer center tap. The complementary voltages appearing at
IOUTP and IOUTN (that is, VIOUTP and VIOUTN) swing symmetrically
around AGND and should be maintained with the specified output
compliance range of the AD9114/AD9115/AD9116/AD9117.
A differential resistor, RDIFF, can be inserted in applications in which
the output of the transformer is connected to the load, RLOAD,
analog.com
DIFFERENTIAL BUFFERED OUTPUT USING AN
OP AMP
An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 105. The AD9114/AD9115/
AD9116/AD9117 are configured with two equal load resistors,
RLOAD, of 50 Ω. The differential voltage developed across IOUTN
and IOUTP is converted to a single-ended signal via the differential
op amp configuration. An optional capacitor can be installed across
IOUTN and IOUTP, forming a real pole in a low-pass filter. The
addition of this capacitor also enhances the distortion performance
of the op amp by preventing the high slewing output of the DAC
from overloading the op amp input.
The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op
Rev. E | 49 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
APPLICATIONS INFORMATION
amp circuit using the ADA4899-1 is configured to provide some
additional signal gain. The op amp must operate from a dual
supply because its output is approximately ±1 V. A high speed
amplifier capable of preserving the differential performance of the
AD9114/AD9115/AD9116/AD9117 while meeting other system level
objectives (such as cost or power) must be selected. The differential gain, gain setting resistor values, and full-scale output swing
capabilities of the op amp must all be considered when optimizing
this circuit.
Figure 106. AUXDAC Simplified Circuit Diagram
The SPI speed limits the update rate of the auxiliary DACs. The
data is inverted such that IAUXDAC is full scale at 0x000 and zero at
0x1FF, as shown in Figure 107.
Figure 105. Differential Buffered Voltage Output
AUXILIARY DACS
The DACs of the AD9114/AD9115/AD9116/AD9117 feature two
versatile and independent 10-bit auxiliary DACs suitable for dc
offset correction and similar tasks.
Because the AUXDACs are driven through the SPI port, they
should never be used in timing-critical applications, such as inside
analog feedback loops.
To keep the pin count reasonable, these auxiliary DACs each share
a pin with the corresponding FSADJx resistor. They are, therefore,
usable only when enabled and when that DAC is operated on its internal full-scale resistors. A simple I-to-V converter is implemented
on-chip with selectable shunt resistors (3.2 kΩ to 16 kΩ) such that if
REFIO is set to exactly 1 V, REFIO/2 equals 0.5 V and the following
equation describes the no load output voltage:
VOUT = 0.5 V −
IDAC −
1.5
RS
16 kΩ
Figure 106 illustrates the function of all the SPI bits controlling
these DACs with the exception of the QAUXEN (Register 0x0C)
and IAUXEN (Register 0x0A) bits and gating to prohibit RS < 3.2
kΩ.
Figure 107. AUXDAC Op Amp Output vs. Current, AVDD = 3.3 V No Load,
AUXDAC 0x1FF to 0x000
Two registers are assigned to each DAC with 10 bits for the actual
DAC current to be generated, a 3-bit offset (and gain) adjustment,
a 2-bit current range adjustment, and an enable/disable bit. Setting
the QAUXOFS (Register 0x0C) and IAUXOFS (Register 0x0A) bits
to all 1s disables the respective op amp and routes the DAC current
directly to the respective FSADJI/AUXI or FSADJQ/AUXQ pins.
This is especially useful when the loads to be driven are beyond the
limited capability of the on-chip amplifier.
When not enabled (QAUXEN or IAUXEN = 0), the respective DAC
output is in open circuit.
DAC-TO-MODULATOR INTERFACING
The auxiliary DACs can be used for local oscillator (LO) cancellation when the DAC output is followed by a quadrature modulator.
This LO feedthrough is caused by the input referred dc offset
voltage of the quadrature modulator (and the DAC output offset
voltage mismatch) and can degrade system performance. Typical
analog.com
Rev. E | 50 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
APPLICATIONS INFORMATION
DAC-to-quadrature modulator interfaces are shown in Figure 108
and Figure 109, with the series resistor value chosen to give an
appropriate adjustment range. Figure 108 also shows external load
resistors in use. Often, the input common-mode voltage for the
modulator is much higher than the output compliance range of the
DAC, so that ac coupling or a dc level shift is necessary. If the
required common-mode input voltage on the quadrature modulator
matches that of the DAC, the dc blocking capacitors in Figure 108
can be removed and the on-chip resistors can be connected.
Figure 108. Typical Use of Auxiliary DACs
Figure 109 shows a greatly simplified circuit that takes full advantage of the internal components supplied in the DAC. A low-pass
or band-pass passive filter is recommended when spurious signals
from the DAC (distortion and DAC images) at the quadrature modulator inputs can affect the system performance. In the example
shown in Figure 109, the filter must be able to pass dc to properly
bias the modulator. Placing the filter at the location shown in Figure
108 and Figure 109 allows easy design of the filter, because the
source and load impedances can easily be designed close to 50 Ω
for a 20 mA full-scale output. When the resistance at the modulator
inputs is known, an optimum value for the series resistor can be
calculated from the modulator input offset voltage ratings.
Figure 109. Typical Use of Auxiliary DACs When DC Coupling to Quadrature
Modulator ADL537x Family
CORRECTING FOR NONIDEAL
PERFORMANCE OF QUADRATURE
MODULATORS ON THE IF-TO-RF
CONVERSION
Analog quadrature modulators make it very easy to realize single
sideband radios. These DACs are most often used to make radio
transmitters, such as in cell phone towers. However, there are several nonideal aspects of quadrature modulator performance. Among
these analog degradations are gain mismatch and LO feedthrough.
analog.com
Gain Mismatch
The gain in the real and imaginary signal paths of the quadrature
modulator may not be matched perfectly. This leads to less than
optimal image rejection because the cancellation of the negative
frequency image is less than perfect.
LO Feedthrough
The quadrature modulator has a finite dc referred offset, as well
as coupling from its LO port to the signal inputs. These can lead
to a significant spectral spur at the frequency of the quadrature
modulator LO.
The AD9114/AD9115/AD9116/AD9117 have the capability to correct
for both of these analog degradations. However, understand that
these degradations drift over temperature; therefore, if close to
optimal single sideband performance is desired, a scheme for
sensing these degradations over temperature and correcting them
may be necessary.
I/Q CHANNEL GAIN MATCHING
Fine gain matching is achieved by adjusting the values in the DAC
fine gain adjustment registers. For the I DAC, these values are in
the I DAC Gain register (Register 0x03, I DACGAIN[5:0]). For the Q
DAC, these values are in the Q DAC gain register (Register 0x06,
Q DACGAIN[5:0]). These are 6-bit values that cover ±2% of full
scale. To perform gain compensation by starting from the default
values of zero, raise the value of one of these registers a few
steps until it can be determined if the amplitude of the unwanted
image is increased or decreased. If the unwanted image increases
in amplitude, remove the step and try the same adjustment on
the other DAC control register. Iterate register changes until the
rejection cannot be improved further. If the fine gain adjustment
range is not sufficient to find a null (that is, the register goes full
scale with no null apparent), adjust the course gain settings of
the two DACs accordingly and try again. Variations on this simple
method are possible.
Note that LO feedthrough compensation is independent of phase
compensation. However, gain compensation can affect the LO
compensation because the gain compensation may change the
common-mode level of the signal. The dc offset of some modulators
is common-mode level dependent. Therefore, it is recommended
that the gain adjustment be performed prior to LO compensation.
LO FEEDTHROUGH COMPENSATION
To achieve LO feedthrough compensation in a circuit, each output
of the two AUXDACs must be connected through a 10 kΩ resistor
to one side of the differential DAC output. See the Auxiliary DACs
section for details of how to use AUXDACs. The purpose of these
connections is to drive a very small amount of current into the
nodes at the quadrature modulator inputs, thereby adding a slight
dc bias to one or the other of the quadrature modulator signal
inputs.
Rev. E | 51 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
APPLICATIONS INFORMATION
To achieve LO feedthrough compensation, the user should start
with the default conditions of the AUXDAC registers and then increment the magnitude of one or the other AUXDAC output voltages.
While this is being done, the amplitude of the LO feedthrough
at the quadrature modulator output should be sensed. If the LO
feedthrough amplitude increases, try either decreasing the output
voltage of the AUXDAC being adjusted or try adjusting the output
voltage of the other AUXDAC. It may take practice before an effective algorithm is achieved. The AD9114/AD9115/AD9116/AD9117
evaluation board can be used to adjust the LO feedthrough down to
the noise floor, although this is not stable over temperature.
RESULTS OF GAIN AND OFFSET
CORRECTION
The results of gain and offset correction can be seen in Figure 110
and Figure 111. Figure 110 shows the output spectrum of the quadrature demodulator before gain and offset correction. Figure 111
shows the output spectrum after correction. The LO feedthrough
spur at 450 MHz has been suppressed to the noise level. This
result can be achieved by applying the correction, but the correction
must be repeated after a large change in temperature.
Note that gain matching improves the negative frequency image
rejection, but it is also related to the phase mismatch in the quadrature modulator. It can be improved by adjusting the relative phase
between the two quadrature signals at the digital side or properly
designing the low-pass filter between the DACs and quadrature
modulators. Phase mismatch is frequency dependent; therefore,
routines must be developed to adjust it if wideband signals are
desired.
Figure 111. AD9114/AD9115/AD9116/AD9117 and ADL5370 with a Single-Tone
Signal at 450 MHz, Gain and LO Compensation Optimized
POWER SUPPLY
Requirements
The analog and digital I/O sections of the AD9114/AD9115/AD9116/
AD9117 have separate power supply inputs (AVDD, DVDDIO, and
CLKVDD) that can operate over the 1.8 V to 3.3 V range. The core
digital section (DVDD) requires 1.8 V.
To ensure proper operation of the device, the RESET/PINMD pin
must be pulsed high after applying power to all supplies. If operating the device in SPI mode, the minimum duration before setting
the pin low is 50 ns. If operating the device in pin mode, there
is no need to set RESET/PINMD low after pulsing it high and,
alternatively, the pin can be pulled up to DVDDIO.
Recommendations
The user can employ several different decoupling capacitors to cover both high and low frequencies. These capacitors must be located
close to the point of entry at the PCB level and close to the devices,
with minimal trace lengths. Recommended decoupling capacitor
values for each supply pin are one of each of the following: 10 nF,
0.1 μF, and 10 μF. The smallest value capacitor must be placed
nearest to the supply pin.
Figure 110. AD9114/AD9115/AD9116/AD9117 and ADL5370 with a Single-Tone
Signal at 450 MHz, No Gain or LO Compensation
analog.com
Rev. E | 52 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.60 MAX
0.60 MAX
31
30
0.50
BSC
1.00
0.85
0.80
SEATING
PLANE
12° MAX
4.25
4.10 SQ
3.95
(BOTTOM VIEW)
10
0.50
0.40
0.30
11
0.20 MIN
4.50 REF
0.80 MAX
0.65 TYP
0.30
0.23
0.18
1
EXPOSED
PAD
21
20
TOP VIEW
PIN 1
INDICATOR
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARIT Y
0.08
0.20 REF
06-01-2012-D
5.85
5.75 SQ
5.65
PI N 1
INDICATOR
40
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
Figure 112. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm and 0.85 mm Package Height
(CP-40-1)
Dimensions shown in millimeters
D ETAIL A
(JED EC 95)
0.30
0.23
0.18
31
40
30
0.50
BSC
4.25
4.10 SQ
3.95
EXPO SED
PAD
21
TOP VIEW
0.80
0.75
0.70
PK G-00 43 54
SEATING
PLANE
SIDE VIEW
0.45
0.40
0.35
10
11
20
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PIN 1
IN D IC A T OR A R EA OPTION S
(SEE D ETA IL A )
1
BOTTO M VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220- WJJD-5 .
10-23-2017-B
PI N 1
INDICATOR
6.10
6.00 SQ
5.90
Figure 113. 40-Lead Lead Frame Chip Scale Package [LFCSP]
6 mm × 6 mm and 0.75 mm Package Height
(CP-40-9)
Dimensions shown in millimeters
analog.com
Rev. E | 53 of 54
Data Sheet
AD9114/AD9115/AD9116/AD9117
OUTLINE DIMENSIONS
Updated: June 29, 2022
ORDERING GUIDE
Model1
Temperature Range
Package Description
AD9114BCPZ
AD9114BCPZRL7
AD9115BCPZ
AD9115BCPZRL7
AD9116BCPZ
AD9116BCPZRL7
AD9117BCPZ
AD9117BCPZN
AD9117BCPZNRL7
AD9117BCPZRL7
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
40-Lead LFCSP (6mm x 6mm w/ EP)
40-Lead LFCSP (6mm x 6mm w/ EP)
40-Lead LFCSP (6mm x 6mm w/ EP)
40-Lead LFCSP (6mm x 6mm w/ EP)
40-Lead LFCSP (6mm x 6mm w/ EP)
40-Lead LFCSP (6mm x 6mm w/ EP)
40-Lead LFCSP (6mm x 6mm w/ EP)
40-Lead LFCSP (6mm x 6mm w/ EP)
40-Lead LFCSP (6mm x 6mm w/ EP)
40-Lead LFCSP (6mm x 6mm w/ EP)
1
Packing Quantity
Reel, 750
Reel, 750
Reel, 750
Reel, 750
Reel, 750
Package Option
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-1
CP-40-9
CP-40-9
CP-40-1
Z = RoHS Compliant Part.
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