AD9121BCPZRL

Dual, 14-Bit, 1230 MSPS, TxDAC+ Digital-to-Analog Converter AD9121 Data Sheet The AD9121 TxDAC+® includes features optimized for direct conversion transmit applications, including complex digital modulation, and gain and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series from Analog Devices, Inc. A 4-wire serial port interface provides for programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 8.7 mA to 31.7 mA. The AD9121 comes in a 72-lead LFCSP. FEATURES Flexible LVDS interface allows word or byte load Single-carrier W-CDMA ACLR = 82 dBc at 122.88 MHz IF Analog output: adjustable 8.7 mA to 31.7 mA, RL = 25 Ω to 50 Ω Integrated 2×/4×/8× interpolator/complex modulator allows carrier placement anywhere in the DAC bandwidth Gain, dc offset, and phase adjustment for sideband suppression Multiple chip synchronization interfaces High performance, low noise PLL clock multiplier Digital inverse sinc filter Low power: 1.5 W at 1.2 GSPS, 800 mW at 500 MSPS, full operating conditions 72-lead, exposed paddle LFCSP PRODUCT HIGHLIGHTS 1. 2. APPLICATIONS 3. Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX, GSM, LTE Digital high or low IF synthesis Transmit diversity Wideband communications: LMDS/MMDS, point-to-point 4. Ultralow noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals from baseband to high intermediate frequencies (IF). Proprietary DAC output switching technique enhances dynamic performance. Current outputs are easily configured for various singleended or differential circuit topologies. Flexible LVDS digital interface allows the standard 28-wire bus to be reduced to one-half of the width. COMPANION PRODUCTS IQ Modulators: ADL5370, ADL537x family IQ Modulators with PLL and VCO: ADRF6701, ADRF670x family Clock Drivers: AD9516, AD951x family Voltage Regulator Design Tool: ADIsimPower GENERAL DESCRIPTION The AD9121 is a dual, 14-bit, high dynamic range digital-toanalog converter (DAC) that provides a sample rate of 1230 MSPS, permitting multicarrier generation up to the Nyquist frequency. TYPICAL SIGNAL CHAIN COMPLEX BASEBAND COMPLEX IF RF DC fIF LO – fIF 2 2/4 I DAC SIN DIGITAL BASEBAND PROCESSOR ANTIALIASING FILTER AQM PA COS 2 2/4 Q DAC LO 09988-001 AD9121 NOTES 1. AQM = ANALOG QUADRATURE MODULATOR. Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arethe property of their respectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9121 Data Sheet TABLE OF CONTENTS Features .....................................................................................1 Coarse Modulation Mixing Sequences ................................ 42 Applications...............................................................................1 Quadrature Phase Correction.............................................. 43 General Description ..................................................................1 DC Offset Correction .......................................................... 43 Product Highlights ....................................................................1 Inverse Sinc Filter ................................................................ 43 Companion Products.................................................................1 DAC Input Clock Configurations............................................ 44 Typical Signal Chain..................................................................1 Driving the DACCLK and REFCLK Inputs ......................... 44 Revision History ........................................................................3 Direct Clocking ................................................................... 44 Functional Block Diagram.........................................................4 Clock Multiplication............................................................ 44 Specifications.............................................................................5 PLL Settings......................................................................... 45 DC Specifications...................................................................5 Configuring the VCO Tuning Band..................................... 45 Digital Specifications .............................................................6 Analog Outputs ....................................................................... 46 Digital Input Data Timing Specifications...............................6 Transmit DAC Operation .................................................... 46 AC Specifications...................................................................7 Auxiliary DAC Operation.................................................... 47 Absolute Maximum Ratings ......................................................8 Interfacing to Modulators.................................................... 48 Thermal Resistance................................................................8 Baseband Filter Implementation.......................................... 48 ESD Caution ..........................................................................8 Driving the ADL5375-15..................................................... 48 Pin Configuration and Function Descriptions...........................9 Reducing LO Leakage and Unwanted Sidebands................. 49 Typical Performance Characteristics .......................................11 Device Power Management ..................................................... 50 Terminology ............................................................................17 Power Dissipation................................................................ 50 Theory of Operation................................................................18 Temperature Sensor............................................................. 51 Serial Port Operation ...........................................................18 Multichip Synchronization...................................................... 52 Data Format.........................................................................18 Synchronization with Clock Multiplication ............................ 52 Serial Port Pin Descriptions.................................................18 Synchronization with Direct Clocking................................. 53 Serial Port Options...............................................................19 Data Rate Mode Synchronization ........................................ 53 Device Configuration Register Map and Descriptions.........20 FIFO Rate Mode Synchronization ....................................... 54 LVDS Input Data Ports ............................................................31 Additional Synchronization Features................................... 55 Word Interface Mode...........................................................31 Interrupt Request Operation ................................................... 56 Byte Interface Mode.............................................................31 Interrupt Service Routine .................................................... 56 Interface Timing ..................................................................31 Interface Timing Validation .................................................... 57 Recommended Frame Input Bias Circuitry .........................32 SED Operation .................................................................... 57 FIFO Operation ...................................................................32 SED Example ....................................................................... 58 Digital Datapath ......................................................................36 Example Start-Up Routine....................................................... 59 Premodulation .....................................................................36 Device Configuration .......................................................... 59 Interpolation Filters .............................................................36 Derived PLL Settings ........................................................... 59 NCO Modulation.................................................................39 Derived NCO Settings ......................................................... 59 Datapath Configuration.......................................................39 Start-Up Sequence ............................................................... 59 Determining Interpolation Filter Modes..............................40 Outline Dimensions ................................................................ 60 Datapath Configuration Examples.......................................41 Ordering Guide ................................................................... 60 Data Rates vs. Interpolation Modes .....................................42 Rev. B | Page 2 of 60 Data Sheet AD9121 REVISION HISTORY 10/12—Rev. 0 to Rev. B Updated Outline Dimensions ........................................................60 Rev. B | Page 3 of 60 AD9121 Data Sheet FUNCTIONAL BLOCK DIAGRAM AD9121 14 IOUT1P DAC 1 AUX 14-BIT IOUT1N 14 fDATA /2 PRE MOD NCO AND MOD HB1 HB2 I OFFSET 10 HB3 Q OFFSET INV SINC DAC_CLK 14 14 INVSINC_CLK INTP FACTOR HB3_CLK HB2_CLK MODE HB1_CLK FRAME PHASE CORRECTION DCI 10 1.2G IOUT2P DAC 2 AUX 14-BIT IOUT2N GAIN 2 FIFO GAIN 1 DATA RECEIVER D13P/D13N D0P/D0N 1.2G 10 REF AND BIAS REFIO FSADJ INTERNAL CLOCK TIMING AND CONTROL LOGIC DAC CLK_SEL PLL CONTROL POWER-ON RESET MULTICHIP SYNCHRONIZATION DAC_CLK 1 CLOCK MULTIPLIER (2× TO 16×) CLK RCVR DACCLKP DACCLKN CLK RCVR REFCLKP REFCLKN 09988-002 IRQ RESET CS SCLK SDO 0 SYNC PLL_LOCK SDIO PROGRAMMING REGISTERS SERIAL INPUT/OUTPUT PORT Figure 2. Rev. B | Page 4 of 60 Data Sheet AD9121 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current 1 Output Compliance Range Power Supply Rejection Ratio, AVDD33 Output Resistance Gain DAC Monotonicity Settling Time to Within ±0.5 LSB MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES AVDD33 CVDD18 DIGITAL SUPPLY VOLTAGES DVDD18 IOVDD POWER CONSUMPTION 2× Mode, fDAC = 491.22 MSPS, IF = 10 MHz, PLL Off 2× Mode, fDAC = 491.22 MSPS, IF = 10 MHz, PLL On 8× Mode, fDAC = 800 MSPS, IF = 10 MHz, PLL Off AVDD33 CVDD18 DVDD18 Power-Down Mode (Register 0x01 = 0xF0) POWER-UP TIME OPERATING RANGE 1 Min Typ 14 Max ±0.5 ±1.0 −0.001 −3.6 8.66 −1.0 −0.3 0 ±2 19.6 Unit Bits LSB LSB +0.001 +3.6 31.66 +1.0 +0.3 10 Guaranteed 20 % FSR % FSR mA V % FSR/V MΩ ns 0.04 100 30 ppm/°C ppm/°C ppm/°C 1.2 5 V kΩ 3.13 1.71 3.3 1.8 3.47 1.89 V V 1.71 1.71 1.8 1.8/3.3 1.89 3.47 V V 1241 57 90 495 18.8 −40 834 913 1135 55 85 444 6.5 260 +25 mW mW mW mA mA mA mW ms °C Based on a 10 kΩ external resistor between FSADJ and AVSS. Rev. B | Page 5 of 60 +85 AD9121 Data Sheet DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, IOVDD = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 2. Parameter CMOS INPUT LOGIC LEVEL Input VIN Logic High Input VIN Logic Low CMOS OUTPUT LOGIC LEVEL Output VOUT Logic High Output VOUT Logic Low LVDS RECEIVER INPUTS 1 Input Voltage Range, VIA or VIB Input Differential Threshold, VIDTH Input Differential Hysteresis, VIDTHH to VIDTHL Receiver Differential Input Impedance, RIN LVDS Input Rate DAC CLOCK INPUT (DACCLKP, DACCLKN) Differential Peak-to-Peak Voltage Common-Mode Voltage Maximum Clock Rate REFCLK INPUT (REFCLKP, REFCLKN) Differential Peak-to-Peak Voltage Common-Mode Voltage REFCLK Frequency (PLL Mode) REFCLK Frequency (SYNC Mode) Test Conditions/Comments Min IOVDD = 1.8 V IOVDD = 2.5 V IOVDD = 3.3 V IOVDD = 1.8 V IOVDD = 2.5 V, 3.3 V 1.2 1.6 2.0 IOVDD = 1.8 V IOVDD = 2.5 V IOVDD = 3.3 V IOVDD = 1.8 V, 2.5 V, 3.3 V Applies to data, DCI, and FRAME inputs 1.4 1.8 2.4 825 −100 Unit 0.6 0.8 V V V V V 0.4 V V V V 20 120 mV mV mV Ω See Table 5 100 Self-biased input, ac-coupled 500 1.25 2000 mV V MHz 500 1.25 2000 mV V MHz MHz 1230 100 1 GHz ≤ fVCO ≤ 2.1 GHz See the Multichip Synchronization section for conditions 15.625 0 600 600 40 12.5 12.5 1.9 0.2 2.3 1.4 LVDS receiver is compliant with the IEEE 1596 reduced range link, unless otherwise noted. DIGITAL INPUT DATA TIMING SPECIFICATIONS Table 3. Parameter LATENCY (DACCLK CYCLES) 1× Interpolation (With or Without Modulation) 2× Interpolation (With or Without Modulation) 4× Interpolation (With or Without Modulation) 8× Interpolation (With or Without Modulation) Inverse Sinc Fine Modulation Max 1675 +100 80 SERIAL PORT INTERFACE Maximum Clock Rate (SCLK) Minimum Pulse Width High (tPWH) Minimum Pulse Width Low (tPWL) Setup Time, SDIO to SCLK (tDS) Hold Time, SDIO to SCLK (tDH) Data Valid, SDO to SCLK (tDV) Setup Time, CS to SCLK (tDCSB) 1 Typ Value Unit 64 135 292 608 20 8 Cycles Cycles Cycles Cycles Cycles Cycles Rev. B | Page 6 of 60 MHz ns ns ns ns ns ns Data Sheet AD9121 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IFS = 20 mA, maximum sample rate, unless otherwise noted. Table 4. Parameter SPURIOUS-FREE DYNAMIC RANGE (SFDR) fDAC = 100 MSPS, fOUT = 20 MHz fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 70 MHz fDAC = 800 MSPS, fOUT = 70 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 200 MSPS, fOUT = 50 MHz fDAC = 400 MSPS, fOUT = 60 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 100 MHz NOISE SPECTRAL DENSITY (NSD), EIGHT-TONE, 500 kHz TONE SPACING fDAC = 200 MSPS, fOUT = 80 MHz fDAC = 400 MSPS, fOUT = 80 MHz fDAC = 800 MSPS, fOUT = 80 MHz W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE-CARRIER fDAC = 491.52 MSPS, fOUT = 10 MHz fDAC = 491.52 MSPS, fOUT = 122.88 MHz fDAC = 983.04 MSPS, fOUT = 122.88 MHz W-CDMA SECOND ACLR, SINGLE-CARRIER fDAC = 491.52 MSPS, fOUT = 10 MHz fDAC = 491.52 MSPS, fOUT = 122.88 MHz fDAC = 983.04 MSPS, fOUT = 122.88 MHz Min Typ Max Unit 78 80 69 72 dBc dBc dBc dBc 84 86 84 81 dBc dBc dBc dBc −162 −163 −164 dBm/Hz dBm/Hz dBm/Hz 84 82 83 dBc dBc dBc 88 86 88 dBc dBc dBc Table 5. Maximum Rate (MSPS) with DVDD and CVDD Supply Regulation Bus Width Byte (7 Bits) Word (14 Bits) Interpolation Factor 1× 2× 4× 8× 1× 2× (HB1) 2× (HB2) 4× 8× 1.8 V ± 5% 1100 1100 1100 550 1100 900 1100 550 275 fINTERFACE (MSPS) DVDD18, CVDD18 = 1.8 V ± 2% 1.9 V ± 2% 1200 1230 1200 1230 1200 1230 600 615 1200 1230 1000 1000 1200 1230 600 615 300 307.5 Rev. B | Page 7 of 60 1.8 V ± 5% 275 550 1100 1100 550 900 1100 1100 1100 fDAC (MSPS) DVDD18, CVDD18 = 1.8 V ± 2% 1.9 V ± 2% 300 307.5 600 615 1200 1230 1200 1230 600 615 1000 1000 1200 1230 1200 1230 1200 1230 AD9121 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 6. Parameter AVDD33 to AVSS, EPAD, CVSS, DVSS IOVDD to AVSS, EPAD, CVSS, DVSS DVDD18, CVDD18 to AVSS, EPAD, CVSS, DVSS AVSS to EPAD, CVSS, DVSS EPAD to AVSS, CVSS, DVSS CVSS to AVSS, EPAD, DVSS DVSS to AVSS, EPAD, CVSS FSADJ, REFIO, IOUT1P, IOUT1N, IOUT2P, IOUT2N to AVSS D[15:0]P, D[15:0]N, FRAMEP, FRAMEN, DCIP, DCIN to EPAD, DVSS DACCLKP, DACCLKN, REFCLKP, REFCLKN to CVSS RESET , IRQ, CS, SCLK, SDIO, SDO to EPAD, DVSS Junction Temperature Storage Temperature Range The exposed pad (EPAD) of the 72-lead LFCSP must be soldered to the ground plane (AVSS). The EPAD provides an electrical, thermal, and mechanical connection to the board. Rating −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +2.1 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to AVDD33 + 0.3 V Typical θJA, θJB, and θJC values are specified for a 4-layer board in still air. Airflow increases heat dissipation, effectively reducing θJA and θJB. Table 7. Thermal Resistance Package 72-Lead LFCSP −0.3 V to DVDD18 + 0.3 V −0.3 V to CVDD18 + 0.3 V ESD CAUTION −0.3 V to IOVDD + 0.3 V 125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 8 of 60 θ JA 20.7 θJB 10.9 θJC 1.1 Unit °C/W Conditions EPAD soldered to ground plane Data Sheet AD9121 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 CVDD18 CVDD18 REFCLKP REFCLKN AVDD33 IOUT1P IOUT1N AVDD33 AVSS FSADJ REFIO AVSS AVDD33 IOUT2N IOUT2P AVDD33 AVSS NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9121 TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 RESET CS SCLK SDIO SDO DVDD18 NC NC NC/BYTELSBN NC/BYTELSBP DVSS DVDD18 D0N D0P D1N D1P D2N D2P NOTES 1. EXPOSED PAD (EPAD) MUST BE SOLDERED TO THE GROUND PLANE (AVSS). THE EPAD PROVIDES AN ELECTRICAL, THERMAL, AND MECHANICAL CONNECTION TO THE BOARD. 2. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND. AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT. 09988-003 D9P D9N D8P D8N D7P D7N D6P D6N DCIP DCIN DVDD18 DVSS D5P D5N D4P D4N D3P D3N 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 CVDD18 DACCLKP DACCLKN CVSS FRAMEP FRAMEN IRQ D13P D13N NC IOVDD DVDD18 D12P D12N D11P D11N D10P D10N Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 Mnemonic CVDD18 DACCLKP DACCLKN CVSS FRAMEP FRAMEN IRQ 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 D13P D13N NC IOVDD DVDD18 D12P D12N D11P D11N D10P D10N D9P D9N D8P D8N Description 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. DAC Clock Input, Positive. DAC Clock Input, Negative. Clock Supply Common. Frame Input, Positive. This pin must be tied to DVSS if not used. Frame Input, Negative. This pin must be tied to DVDD18 if not used. Interrupt Request. Open-drain, active low output. Connect an external pull-up to IOVDD through a 10 kΩ resistor. Data Bit 13 (MSB), Positive. Data Bit 13 (MSB), Negative. This pin is not connected internally (see Figure 3). Supply Pin for Serial Port I/O Pins, RESET , and IRQ. 1.8 V to 3.3 V can be supplied to this pin. 1.8 V Digital Supply. Supplies power to digital core and digital data ports. Data Bit 12, Positive. Data Bit 12, Negative. Data Bit 11, Positive. Data Bit 11, Negative. Data Bit 10, Positive. Data Bit 10, Negative. Data Bit 9, Positive. Data Bit 9, Negative. Data Bit 8, Positive. Data Bit 8, Negative. Rev. B | Page 9 of 60 AD9121 Pin No. 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Data Sheet Mnemonic D7P D7N D6P D6N DCIP DCIN DVDD18 DVSS D5P D5N D4P D4N D3P D3N D2P D2N D1P D1N D0P D0N DVDD18 DVSS NC/ByteLSBP NC/ByteLSBN NC NC DVDD18 SDO SDIO SCLK CS RESET NC AVSS AVDD33 IOUT2P IOUT2N AVDD33 AVSS REFIO FSADJ AVSS AVDD33 IOUT1N IOUT1P AVDD33 REFCLKN REFCLKP CVDD18 CVDD18 EPAD Description Data Bit 7, Positive. Data Bit 7, Negative. Data Bit 6, Positive. Data Bit 6, Negative. Data Clock Input, Positive. Data Clock Input, Negative. 1.8 V Digital Supply. Supplies power to digital core and digital data ports. Digital Common. Data Bit 5, Positive. Data Bit 5, Negative. Data Bit 4, Positive. Data Bit 4, Negative. Data Bit 3, Positive. Data Bit 3, Negative. Data Bit 2, Positive. Data Bit 2, Negative. Data Bit 1, Positive. Data Bit 1, Negative. Data Bit 0, Positive. Data Bit 0, Negative. 1.8 V Digital Supply. Supplies power to digital core and digital data ports. Digital Common. This pin is not connected internally (see Figure 3) in word mode. LSB Positive (Data Bit 0) in byte mode. This pin is not connected internally (see Figure 3) in word mode. LSB Negative (Data Bit 0) in byte mode. This pin is not connected internally (see Figure 3). This pin is not connected internally (see Figure 3). 1.8 V Digital Supply. Supplies power to digital core and digital data ports. Serial Port Data Output (CMOS Levels with Respect to IOVDD). Serial Port Data Input/Output (CMOS Levels with Respect to IOVDD). Serial Port Clock Input (CMOS Levels with Respect to IOVDD). Serial Port Chip Select, Active Low (CMOS Levels with Respect to IOVDD). Reset, Active Low (CMOS Levels with Respect to IOVDD). This pin is not connected internally (see Figure 3). Analog Supply Common. 3.3 V Analog Supply. Q DAC Positive Current Output. Q DAC Negative Current Output. 3.3 V Analog Supply. Analog Supply Common. Voltage Reference. Nominally 1.2 V output. Should be decoupled to AVSS. Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to AVSS. Analog Supply Common. 3.3 V Analog Supply. I DAC Negative Current Output. I DAC Positive Current Output. 3.3 V Analog Supply. PLL Reference Clock Input, Negative. This pin has a secondary function as a synchronization input. PLL Reference Clock Input, Positive. This pin has a secondary function as a synchronization input. 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. 1.8 V Clock Supply. Supplies clock receivers, clock distribution, and PLL circuitry. The exposed pad (EPAD) must be soldered to the ground plane (AVSS). The EPAD provides an electrical, thermal, and mechanical connection to the board. Rev. B | Page 10 of 60 Data Sheet AD9121 TYPICAL PERFORMANCE CHARACTERISTICS fDATA fDATA fDATA fDATA –20 –30 –40 –50 –60 –70 –40 –50 –60 –70 50 100 150 200 250 300 350 400 450 fOUT (MHz) Figure 4. Harmonics vs. fOUT over fDATA, 2× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA 0 fDATA fDATA fDATA fDATA –10 50 100 150 200 250 300 350 400 450 fOUT (MHz) Figure 7. Second Harmonic vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 400 MSPS, IFS = 20 mA 0 = 100MSPS, SECOND HARMONIC = 100MSPS, THIRD HARMONIC = 200MSPS, SECOND HARMONIC = 200MSPS, THIRD HARMONIC 0dBFS –6dBFS –12dBFS –18dBFS –10 –20 THIRD HARMONIC (dBc) –20 0 09988-104 –90 –100 09988-101 –90 –100 0 –30 –40 –50 –60 –70 –80 –30 –40 –50 –60 –70 –80 –90 –100 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) 09988-102 –90 –100 Figure 5. Harmonics vs. fOUT over fDATA, 4× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA 0 fDATA fDATA fDATA fDATA –10 –20 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) 09988-105 HARMONICS (dBc) –30 –80 –80 Figure 8. Third Harmonic vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 400 MSPS, IFS = 20 mA 0 = 100MSPS, SECOND HARMONIC = 100MSPS, THIRD HARMONIC = 150MSPS, SECOND HARMONIC = 150MSPS, THIRD HARMONIC IFS IFS IFS IFS IFS IFS –10 –20 HARMONICS (dBc) –30 –40 –50 –60 –70 –80 –30 = 10mA, = 20mA, = 30mA, = 10mA, = 20mA, = 30mA, SECOND HARMONIC SECOND HARMONIC SECOND HARMONIC THIRD HARMONIC THIRD HARMONIC THIRD HARMONIC –40 –50 –60 –70 –80 –90 –90 –100 –100 0 100 200 300 400 500 600 fOUT (MHz) 700 09988-103 HARMONICS (dBc) 0dBFS –6dBFS –12dBFS –18dBFS –10 Figure 6. Harmonics vs. fOUT over fDATA, 8× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA 0 50 100 150 200 250 300 350 400 fOUT (MHz) Figure 9. Harmonics vs. fOUT over IFS, 2× Interpolation, fDATA = 400 MSPS, Digital Scale = 0 dBFS Rev. B | Page 11 of 61 450 09988-106 HARMONICS (dBc) –20 0 = 250MSPS, SECOND HARMONIC = 250MSPS, THIRD HARMONIC = 400MSPS, SECOND HARMONIC = 400MSPS, THIRD HARMONIC SECOND HARMONIC (dBc) 0 –10 AD9121 –69 fDATA = 250MSPS fDATA = 400MSPS –70 HIGHEST DIGITAL SPUR (dBc) Data Sheet 2× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 250MSPS, fOUT = 101MHz –71 –72 –73 –74 –75 –76 –77 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) STOP 500.0MHz SWEEP 6.017s (601 PTS) 4× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 200MSPS, fOUT = 151MHz –65 –70 –75 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) fDATA = 100MSPS fDATA = 150MSPS –65 VBW 10kHz STOP 800.0MHz SWEEP 9.634s (601 PTS) Figure 14. Single-Tone Spectrum, 4× Interpolation, fDATA = 200 MSPS, fOUT = 151 MHz Figure 11. Highest Digital Spur vs. fOUT over fDATA , 4× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA –60 START 1.0MHz #RES BW 10kHz 09988-111 –80 09988-108 8× INTERPOLATION, SINGLE-TONE SPECTRUM, fDATA = 100MSPS, fOUT = 131MHz –70 –75 –80 –85 –95 0 100 200 300 400 500 600 700 fOUT (MHz) 09988-109 –90 START 1.0MHz #RES BW 10kHz VBW 10kHz STOP 800.0MHz SWEEP 9.634s (601 PTS) Figure 15. Single-Tone Spectrum, 8× Interpolation, fDATA = 100 MSPS, fOUT = 131 MHz Figure 12. Highest Digital Spur vs. fOUT over fDATA , 8× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA Rev. B | Page 12 of 60 09988-112 HIGHEST DIGITAL SPUR (dBc) fDATA = 100MSPS fDATA = 200MSPS –85 HIGHEST DIGITAL SPUR (dBc) VBW 10kHz Figure 13. Single-Tone Spectrum, 2× Interpolation, fDATA = 250 MSPS, fOUT = 101 MHz Figure 10. Highest Digital Spur vs. fOUT over fDATA , 2× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA –60 START 1.0MHz #RES BW 10kHz 09988-110 –79 09988-107 –78 Data Sheet –10 –20 –30 –30 IMD (dBc) –20 –40 –50 –40 –50 –60 –60 –70 –70 –80 –80 –90 0 50 100 150 200 250 300 350 400 450 fOUT (MHz) –90 0 100 150 200 250 300 350 400 450 Figure 19. IMD vs. fOUT over Digital Scale, 2× Interpolation, fDATA = 400 MSPS, IFS = 20 mA –50 fDATA = 100MSPS fDATA = 200MSPS –10 50 fOUT (MHz) Figure 16. IMD vs. fOUT over fDATA , 2× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA 0 0dBFS –6dBFS –12dBFS –18dBFS –10 09988-113 IMD (dBc) 0 fDATA = 250MSPS fDATA = 400MSPS 09988-116 0 AD9121 IFS = 10mA IFS = 20mA IFS = 30mA –55 –20 –60 IMD (dBc) IMD (dBc) –30 –40 –50 –65 –70 –60 –75 –70 50 100 150 200 250 300 350 400 450 fOUT (MHz) –85 0 –50 –30 –55 –40 –60 IMD (dBc) –20 –50 –60 300 350 400 450 PLL OFF –75 –80 –90 –85 –100 200 250 300 350 400 fOUT (MHz) 450 Figure 18. IMD vs. fOUT, 8× Interpolation, fDATA = 100 MSPS, Digital Scale = 0 dBFS, IFS = 20 mA PLL ON –70 –80 150 250 –65 –70 09988-115 IMD (dBc) –45 100 200 –40 fDATA = 100MSPS 50 150 Figure 20. IMD vs. fOUT over IFS, 2× Interpolation, fDATA = 400 MSPS, Digital Scale = 0 dBFS –10 0 100 fOUT (MHz) Figure 17. IMD vs. fOUT over fDATA , 4× Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA 0 50 –90 0 50 100 150 200 250 300 350 400 fOUT (MHz) Figure 21. IMD vs. fOUT, 4× Interpolation, fDATA = 200 MSPS, Digital Scale = 0 dBFS, IFS = 20 mA, PLL On and PLL Off Rev. B | Page 13 of 60 450 09988-118 0 09988-114 –90 09988-117 –80 –80 AD9121 –152 Data Sheet 1×, fDATA 2×, fDATA 4×, fDATA 8×, fDATA –154 –161.0 = 200MSPS = 200MSPS = 200MSPS = 100MSPS 1×, fDATA 2×, fDATA 4×, fDATA 8×, fDATA –161.5 –162.0 = 200MSPS = 200MSPS = 200MSPS = 100MSPS –156 NSD (dBm/Hz) NSD (dBm/Hz) –162.5 –158 –160 –163.0 –163.5 –164.0 –162 –164.5 –164 0 50 100 150 200 250 300 350 400 –165.5 09988-119 –166 450 fOUT (MHz) 0 –161.0 200 250 300 350 400 450 0dBFS –6dBFS –12dBFS –18dBFS –161.5 –162.0 –162.5 NSD (dBm/Hz) –158 NSD (dBm/Hz) 150 Figure 25. Eight-Tone NSD vs. fOUT over Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA, PLL Off 0dBFS –6dBFS –12dBFS –18dBFS –156 100 fOUT (MHz) Figure 22. One-Tone NSD vs. fOUT over Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA, PLL Off –154 50 09988-122 –165.0 –160 –162 –164 –163.0 –163.5 –164.0 –164.5 –165.0 –165.5 –166 50 100 150 200 250 300 350 400 450 fOUT (MHz) Figure 23. One-Tone NSD vs. fOUT over Digital Scale, 4× Interpolation, fDATA = 200 MSPS, IFS = 20 mA, PLL Off –158 –166.5 09988-120 0 0 100 150 200 250 300 350 400 450 fOUT (MHz) Figure 26. Eight-Tone NSD vs. fOUT over Digital Scale, 4× Interpolation, fDATA = 200 MSPS, IFS = 20 mA, PLL Off –160 2×, fDATA = 200MSPS 4×, fDATA = 200MSPS 8×, fDATA = 100MSPS –159 50 09988-123 –166.0 –168 2×, fDATA = 200MSPS 4×, fDATA = 200MSPS 8×, fDATA = 100MSPS –161 –160 NSD (dBm/Hz) –162 –163 –163 –164 –164 –165 –166 0 50 100 150 200 250 300 350 400 fOUT (MHz) 450 Figure 24. One-Tone NSD vs. fOUT over Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA, PLL On –166 0 50 100 150 200 250 300 350 400 fOUT (MHz) Figure 27. Eight-Tone NSD vs. fOUT over Interpolation, Digital Scale = 0 dBFS, IFS = 20 mA, PLL On Rev. B | Page 14 of 60 450 09988-124 –165 09988-121 NSD (dBm/Hz) –162 –161 Data Sheet AD9121 –70 0dBFS –3dBFS –6dBFS –151 –153 –75 NSD (dBm/Hz) –155 ACLR (dBc) AD9121 NSD –157 –159 AD9122 NSD –80 –85 –161 –90 0 100 200 300 400 500 fOUT (MHz) –95 09988-200 –165 0 150 200 250 Figure 31. One-Carrier W-CDMA ACLR vs. fOUT over Digital Scale, Second Alternate Channel, PLL Off –77 –50 0dBFS –3dBFS –6dBFS –78 INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, –55 PLL OFF PLL OFF PLL ON PLL ON –60 ACLR (dBc) –79 –80 –81 –82 –65 –70 –75 –80 –83 0 50 100 150 200 250 fOUT (MHz) –90 09988-125 –84 0 100 200 300 400 500 fOUT (MHz) Figure 29. One-Carrier W-CDMA ACLR vs. fOUT over Digital Scale, Adjacent Channel, PLL Off 09988-128 –85 Figure 32. One-Carrier W-CDMA ACLR vs. fOUT over Interpolation, Adjacent Channel, PLL On and PLL Off –78 –70 0dBFS –3dBFS –6dBFS –80 INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, –72 –74 PLL OFF PLL OFF PLL ON PLL ON –76 ACLR (dBc) –82 –84 –86 –78 –80 –82 –84 –86 –88 0 50 100 150 200 250 fOUT (MHz) 09988-126 –88 –90 Figure 30. One-Carrier W-CDMA ACLR vs. fOUT over Digital Scale, First Alternate Channel, PLL Off –90 0 100 200 300 400 500 fOUT (MHz) Figure 33. One-Carrier W-CDMA ACLR vs. fOUT over Interpolation, First Alternate Channel, PLL On and PLL Off Rev. B | Page 15 of 60 09988-129 ACLR (dBc) 100 fOUT (MHz) Figure 28. One-Tone NSD vs. fOUT, fDATA = 400 MSPS, 2× Interpolation, PLL Off (Comparison of AD9121 vs. AD9122) ACLR (dBc) 50 09988-127 –163 AD9121 Data Sheet –70 INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, INTERPOLATION FACTOR = 2×, INTERPOLATION FACTOR = 4×, ACLR (dBc) –75 PLL OFF PLL OFF PLL ON PLL ON –80 –85 –90 0 100 200 300 400 09988-130 –95 500 fOUT (MHz) START 125.88MHz #RES BW 30kHz VBW 30kHz STOP 174.42MHz SWEEP 206.9ms (601 PTS) 1 2 3 4 Figure 34. One-Carrier W-CDMA ACLR vs. fOUT over Interpolation, Second Alternate Channel, PLL On and PLL Off RMS RESULTS CARRIER POWER –10.00dBm/ 3.840MHz FREQ OFFSET 5.00MHz 10.00MHz 15.00MHz VBW 30kHz STOP 166.94MHz SWEEP 143.6ms (601 PTS) REF BW 3.840MHz 3.840MHz 2.888MHz LOWER dBc dBm –75.96 –85.96 –85.33 –95.33 –95.81 –95.81 UPPER dBc dBm –77.13 –87.13 –85.24 –95.25 –85.43 –95.43 OFFSET FREQ 5.000MHz 10.00MHz 15.00MHz INTEG BW 3.840MHz 3.840MHz 3.840MHz LOWER dBc dBm –65.88 –82.76 –68.17 –85.05 –70.42 –87.31 UPPER dBc dBm –67.52 –84.40 –69.91 –86.79 –71.40 –88.28 Figure 36. Four-Carrier W-CDMA ACLR Performance, IF = ~150 MHz 09988-131 START 133.06MHz #RES BW 30kHz –16.92dBm –16.89dBm –17.43dBm –17.64dBm 09988-132 TOTAL CARRIER POWER –11.19dBm/15.3600MHz RRC FILTER: OFF FILTER ALPHA 0.22 REF CARRIER POWER –16.89dBm/3.84000MHz Figure 35. One-Carrier W-CDMA ACLR Performance, IF = ~150 MHz Rev. B | Page 16 of 60 Data Sheet AD9121 TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal within the dc to Nyquist frequency of the DAC. Typically, energy in this band is rejected by the interpolation filters. This specification, therefore, defines how well the interpolation filters work and the effect of other parasitic coupling paths on the DAC output. Offset Error Offset error is the deviation of the output current from the ideal of 0 mA. For IOUT1P, 0 mA output is expected when all inputs are set to 0. For IOUT1N, 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The output compliance range is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree Celsius. For reference voltage drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection (PSR) PSR is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Interpolation Filter If the digital inputs to the DAC are sampled at a multiple rate of fDATA (interpolation rate), a digital filter can be constructed that has a sharp transition band near fDATA/2. Images that typically appear around fDAC (output data rate) can be greatly suppressed. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio, in decibels relative to the carrier (dBc), between the measured power within a channel and that of its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. B | Page 17 of 60 AD9121 Data Sheet THEORY OF OPERATION The AD9121 combines many features that make it a very attractive DAC for wired and wireless communications systems. The dual digital signal path and dual DAC structure allow an easy interface to common quadrature modulators when designing single sideband (SSB) transmitters. The speed and performance of the AD9121 allow wider bandwidths and more carriers to be synthesized than in previously available DACs. In addition, the AD9121 includes an innovative low power, 32-bit, complex NCO that greatly increases the ease of frequency placement. The remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the device and the system controller. Phase 2 of the communication cycle is a transfer of one or more data bytes. Registers change immediately upon writing to the last bit of each transfer byte, except for the frequency tuning word and NCO phase offsets, which change only when the frequency tuning word (FTW) update bit (Register 0x36, Bit 0) is set. The AD9121 offers features that allow simplified synchronization with incoming data and between multiple devices. Auxiliary DACs are also provided on chip. The auxiliary DACs can be used for output dc offset compensation (for LO compensation in SSB transmitters) and for gain matching (for image rejection optimization in SSB transmitters). The instruction byte contains the information shown in Table 9. SERIAL PORT OPERATION The serial port is a flexible, synchronous serial communications port that allows easy interfacing to many industry-standard microcontrollers and microprocessors. The serial I/O is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel® SSR protocols. The interface allows read/write access to all registers that configure the AD9121. Single-byte or multiple-byte transfers are supported, as well as MSB first or LSB first transfer formats. The serial port interface can be configured as a single-pin I/O (SDIO) or as two unidirectional pins for input and output (SDIO and SDO). CS 53 SPI PORT 09988-010 SDIO 51 Table 9. Serial Port Instruction Byte I7 (MSB) R/W I6 A6 I5 A5 I4 A4 I3 A3 I2 A2 I1 A1 I0 (LSB) A0 R/W, Bit 7 of the instruction byte, determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation, and Logic 0 indicates a write operation. A6 to A0, Bit 6 to Bit 0 of the instruction byte, determine the register that is accessed during the data transfer portion of the communication cycle. For multibyte transfers, A6 is the starting byte address. The remaining register addresses are generated by the device based on the LSB_FIRST bit (Register 0x00, Bit 6). SERIAL PORT PIN DESCRIPTIONS Serial Clock (SCLK) The serial clock pin synchronizes data to and from the device and runs the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. SDO 50 SCLK 52 DATA FORMAT Chip Select (CS) Figure 37. Serial Port Interface Pins A communication cycle with the AD9121 has two phases. Phase 1 is the instruction cycle (the writing of an instruction byte into the device), coincident with the first eight SCLK rising edges. The instruction byte provides the serial port controller with information regarding the data transfer cycle—Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, along with the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the device. A logic high on the CS pin followed by a logic low resets the serial port timing to the initial state of the instruction cycle. From this state, the next eight rising SCLK edges represent the instruction bits of the current I/O operation. An active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communications lines. When the CS pin is high, the SDO and SDIO pins go to a high impedance state. During the communication cycle, the CS pin should stay low. Serial Data I/O (SDIO) Data is always written into the device on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, configuring the SDIO pin as unidirectional. Serial Data Output (SDO) Data is read from this pin for protocols that use separate lines for transmitting and receiving data. If the device operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. Rev. B | Page 18 of 60 Data Sheet AD9121 SERIAL PORT OPTIONS INSTRUCTION CYCLE When LSB_FIRST = 1 (LSB first), the instruction and data bits must be written from LSB to MSB. Multibyte data transfers in LSB first format start with an instruction byte that includes the register address of the least significant data byte. Subsequent data bytes should follow from low address to high address. In LSB first mode, the serial port internal byte address generator increments for each data byte of the multibyte communication cycle. If the MSB first mode is active, the serial port controller data address decrements from the data address written toward 0x00 for multibyte I/O operations. If the LSB first mode is active, the serial port controller data address increments from the data address written toward 0x7F for multibyte I/O operations. INSTRUCTION CYCLE A3 A4 tDCSB A5 A6 R/W D00 D10 D20 D4N D5N D6N D7N D00 D10 D20 D4N D5N D6N D7N tSCLK CS tPWH tPWL SCLK tDS SDIO tDH INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 40. Timing Diagram for Serial Port Register Write CS SCLK tDV DATA BIT n DATA BIT n – 1 Figure 41. Timing Diagram for Serial Port Register Read R/W A6 A5 A4 A3 A2 A1 A0 D7N D6N D5N D30 D20 D10 D00 D7N D6N D5N D30 D20 D10 D00 09988-011 SCLK SDO A2 Figure 39. Serial Port Interface Timing, LSB First CS SDIO A1 SDO SDIO, SDO DATA TRANSFER CYCLE A0 09988-012 SDIO 09988-013 When LSB_FIRST = 0 (MSB first), the instruction and data bits must be written from MSB to LSB. Multibyte data transfers in MSB first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes should follow from high address to low address. In MSB first mode, the serial port internal byte address generator decrements for each data byte of the multibyte communication cycle. SCLK Figure 38. Serial Port Interface Timing, MSB First Rev. B | Page 19 of 60 09988-014 The serial port can support both MSB first and LSB first data formats. This functionality is controlled by the LSB_FIRST bit (Register 0x00, Bit 6). The default is MSB first (LSB_FIRST = 0). DATA TRANSFER CYCLE CS AD9121 Data Sheet DEVICE CONFIGURATION REGISTER MAP AND DESCRIPTIONS Table 10. Device Configuration Register Map Addr (Hex) 0x00 0x01 Register Name Comm Power control 0x03 Data format 0x04 Interrupt enable 0x05 Bit 7 SDIO Power down I DAC Binary data format Enable PLL lock lost Bit 6 LSB_FIRST Power down Q DAC Q data first Bit 5 Reset Power down data receiver MSB swap Bit 4 Enable PLL locked Enable sync signal lost Interrupt enable 0 0 0 0x06 Event flag PLL lock lost PLL locked Sync signal lost 0x07 Event flag 0x08 Clock receiver control Enable sync signal locked Enable AED compare pass Sync signal locked AED compare pass REFCLK crosscorrection 0x0A PLL control 0x0C PLL control 0x0D PLL control 0x0E 0x0F 0x10 PLL status PLL status Sync control 0x11 0x12 Sync control Sync status 0x13 0x15 Sync status Data receiver status 0x16 0x17 0x18 DCI delay FIFO control FIFO status 0x19 0x1B FIFO status Datapath control REFCLK duty correction PLL manual enable PLL Loop Bandwidth[1:0] N2[1:0] DACCLK duty correction PLL enable DACCLK crosscorrection Data/FIFO rate toggle Sync lost Sync locked Bit 2 FIFO Warning 2 Bypass premod Bypass sinc−1 Bit 0 Power down aux ADC Data Bus Width[1:0] Enable AED compare fail AED compare fail 1 Enable SED compare fail SED compare fail 1 PLL crosscontrol enable N0[1:0] 0x00 Enable FIFO Warning 2 0x00 0 0 0x00 FIFO Warning 1 FIFO Warning 2 N/A N/A 1 1 0x3F 0x40 0xD1 N1[1:0] 0xD9 VCO Control Voltage[3:0] VCO Band Readback[5:0] Rising Sync Averaging[2:0] edge sync Sync Phase Request[5:0] N/A N/A 0x48 LVDS data level high LVDS data level low DCI Delay[1:0] FIFO Phase Offset[2:0] FIFO soft FIFO soft align ack align request Bypass NCO Default 0x00 0x10 Enable FIFO Warning 1 PLL Charge Pump Current[4:0] Sync Phase Readback[7:0] (6.2 format) LVDS LVDS LVDS DCI LVDS DCI FRAME FRAME level high level low level high level low FIFO Warning 1 Bit 1 Manual VCO Band[5:0] PLL locked Sync enable Bit 3 FIFO Level[7:0] NCO gain Rev. B | Page 20 of 60 Bypass phase comp and dc offset Select sideband Send I data to Q data 0x00 N/A N/A N/A 0x00 0x04 N/A N/A 0xE4 Data Sheet Addr (Hex) 0x1C 0x1D 0x1E 0x1F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 Register Name HB1 control HB2 control HB3 control Chip ID FTW LSB FTW FTW FTW MSB NCO phase offset LSB NCO phase offset MSB NCO FTW update I phase adj LSB I phase adj MSB Q phase adj LSB Q phase adj MSB I DAC offset LSB I DAC offset MSB Q DAC offset LSB Q DAC offset MSB I DAC FS adjust I DAC control 0x42 0x43 I aux DAC data I aux DAC control 0x44 0x45 Q DAC FS adjust Q DAC control 0x46 0x47 Q aux DAC data Q aux DAC control 0x48 Die temp range control Die temp LSB Die temp MSB SED control 0x49 0x4A 0x67 0x68 0x69 0x6A 0x6B Compare I0 LSBs Compare I0 MSBs Compare Q0 LSBs Compare Q0 MSBs AD9121 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 HB1[1:0] Bit 0 Bypass HB1 Bypass HB2 Bypass HB3 HB2[5:0] HB3[5:0] Chip ID[7:0] FTW[7:0] FTW[15:8] FTW[23:16] FTW[31:24] NCO Phase Offset[7:0] NCO Phase Offset[15:8] FRAME FTW ack FRAME FTW request I Phase Adj[7:0] 0x00 Update FTW ack Update FTW request I DAC Offset[7:0] I DAC Offset[15:8] Q DAC Offset[7:0] Q DAC Offset[15:8] 0x00 Q Phase Adj[7:0] Q Phase Adj[9:8] I DAC FS Adj[7:0] I DAC FS Adj[9:8] 0xF9 0x01 I Aux DAC[9:8] 0x00 0x00 Q DAC FS Adj[9:8] 0xF9 0x01 Q Aux DAC[9:8] 0x00 0x00 I DAC sleep I Aux DAC[7:0] I aux DAC current direction I aux DAC sleep Q DAC FS Adj[7:0] Q DAC sleep Q Aux DAC[7:0] Q aux DAC sign SED compare enable Q aux DAC current direction Q aux DAC sleep FS Current[2:0] Sample error detected 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 I Phase Adj[9:8] I aux DAC sign Default 0x00 0x00 0x00 0x08 0x00 0x00 0x00 0x00 0x00 Reference Current[2:0] Die Temp[7:0] Die Temp[15:8] Autoclear enable Compare fail Capacitor value Compare pass 0x02 N/A N/A 0x00 Compare Value I0[7:0] Compare Value I0[15:8] 0xB6 0x7A Compare Value Q0[7:0] 0x45 Compare Value Q0[15:8] 0xEA Rev. B | Page 21 of 60 AD9121 Addr (Hex) 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x7F Data Sheet Register Name Compare I1 LSBs Compare I1 MSBs Compare Q1 LSBs Compare Q1 MSBs SED I LSBs SED I MSBs SED Q LSBs SED Q MSBs Revision Bit 7 Bit 6 0 Bit 5 0 Bit 4 Bit 3 Bit 2 Compare Value I1[7:0] Compare Value I1[15:8] Bit 1 Bit 0 Default 0x16 0x1A Compare Value Q1[7:0] 0xC6 Compare Value Q1[15:8] 0xAA Errors Detected I_BITS[7:0] Errors Detected I_BITS[15:8] Errors Detected Q_BITS[7:0] Errors Detected Q_BITS[15:8] Revision[3:0] 0x00 0x00 0x00 0x00 N/A 0 0 Table 11. Device Configuration Register Descriptions Register Name Comm Power Control Address (Hex) 0x00 0x01 Bits 7 Name SDIO 6 LSB_FIRST 5 Reset 7 6 5 7 Power down I DAC Power down Q DAC Power down data receiver Power down auxiliary ADC Binary data format 6 Q data first 5 MSB swap [1:0] Data Bus Width[1:0] 7 6 5 4 1 0 Enable PLL lock lost Enable PLL locked Enable sync signal lost Enable sync signal locked Enable FIFO Warning 1 Enable FIFO Warning 2 4 Data Format Interrupt Enable 0x03 0x04 Description SDIO pin operation. 0 = SDIO operates as an input only. 1 = SDIO operates as a bidirectional input/output. Serial port communication, LSB or MSB first. 0 = MSB first. 1 = LSB first. The device is placed in reset when this bit is written high and remains in reset until the bit is written low. 1 = power down I DAC. 1 = power down Q DAC. 1 = power down the input data receiver. 0 0 0 1 = power down the auxiliary ADC for temperature sensor. 1 0 = input data is in twos complement format. 1 = input data is in binary format. Indicates I/Q data pairing on data input. 0 = I data sent to data receiver first. 1 = Q data sent to data receiver first. Swaps the bit order of the data input port. 0 = order of the data bits corresponds to the pin descriptions. 1 = bit designations are swapped; most significant bits become the least significant bits. Data receiver interface mode. See the LVDS Input Data Ports section for information about the operation of the different interface modes. 00 = word mode; 14-bit interface bus width. 01 = byte mode; 7-bit interface bus width. 10 = invalid. 11 = invalid. 1 = enable interrupt for PLL lock lost. 1 = enable interrupt for PLL locked. 1 = enable interrupt for sync signal lost. 1 = enable interrupt for sync signal locked. 1 = enable interrupt for FIFO Warning 1. 1 = enable interrupt for FIFO Warning 2. 0 Rev. B | Page 22 of 60 Default 0 0 0 0 0 00 0 0 0 0 0 0 Data Sheet Register Name Interrupt Enable Address (Hex) 0x05 Event Flag 0x06 AD9121 Bits [7:5] 4 3 2 [1:0] 7 6 5 4 1 0 0x07 4 3 2 Clock Receiver Control 0x08 7 6 5 4 PLL Control 0x0A 7 6 0x0C [5:0] [7:6] [4:0] Name Set to 0 Enable AED compare pass Enable AED compare fail Enable SED compare fail Set to 0 PLL lock lost Description Set these bits to 0. 1 = enable interrupt for AED comparison pass. 1 = enable interrupt for AED comparison fail. 1 = enable interrupt for SED comparison fail. Set these bits to 0. 1 = indicates that the PLL, which had been previously locked, has unlocked from the reference signal. This is a latched signal. PLL locked 1 = indicates that the PLL has locked to the reference clock input. Sync signal lost 1 = indicates that the sync logic, which had been previously locked, has lost alignment. This is a latched signal. Sync signal locked 1 = indicates that the sync logic has achieved sync alignment. This is indicated when no phase changes were requested for at least a few full averaging cycles. FIFO Warning 1 1 = indicates that the difference between the FIFO read and write pointers is 1. FIFO Warning 2 1 = indicates that the difference between the FIFO read and write pointers is 2. Note that all event flags are cleared by writing the respective bit high. AED compare pass 1 = indicates that the SED logic detected a valid input data pattern compared against the preprogrammed expected values. This is a latched signal. AED compare fail 1 = indicates that the SED logic detected an invalid input data pattern compared against the preprogrammed expected values. This latched signal is automatically cleared when eight valid I/Q data pairs are received. SED compare fail 1 = indicates that the SED logic detected an invalid input data pattern compared against the preprogrammed expected values. This is a latched signal. Note that all event flags are cleared by writing the respective bit high. DACCLK duty correction 1 = enable duty cycle correction on the DACCLK input. REFCLK duty correction 1 = enable duty cycle correction on the REFCLK input. DACCLK cross-correction 1 = enable differential crossing correction on the DACCLK input. REFCLK cross-correction 1 = enable differential crossing correction on the REFCLK input. PLL enable 1 = enable the PLL clock multiplier. The REFCLK input is used as the PLL reference clock signal. PLL manual enable 1 = enable manual selection of the VCO band. The correct VCO band must be determined by the user and written to Bits[5:0]. Manual VCO Band[5:0] Selects the VCO band to be used. PLL Loop Bandwidth[1:0] Selects the PLL loop filter bandwidth. 00 = widest bandwidth. … 11 = narrowest bandwidth. PLL Charge Pump Sets the nominal PLL charge pump current. Current[4:0] 00000 = lowest current setting. … 11111 = highest current setting. Rev. B | Page 23 of 60 Default 000 0 0 0 00 N/A N/A N/A N/A N/A N/A N/A N/A N/A 0 0 1 1 0 1 000000 11 10001 AD9121 Register Name PLL Control PLL Status Sync Control Data Sheet Address (Hex) 0x0D Bits [7:6] Name N2[1:0] 4 [3:2] PLL cross-control enable N0[1:0] [1:0] N1[1:0] 0x0E 7 PLL locked 0x0F 0x10 [3:0] [5:0] 7 6 VCO Control Voltage[3:0] VCO Band Readback[5:0] Sync enable Data/FIFO rate toggle 3 Rising edge sync [2:0] Sync Averaging[2:0] [5:0] Sync Phase Request[5:0] 0x11 Description PLL control clock divider. This divider determines the ratio of the REFCLK frequency to the PLL controller clock frequency. fPC_CLK must always be less than 75 MHz. 00 = fREFCLK/fPC_CLK = 2. 01 = fREFCLK/fPC_CLK = 4. 10 = fREFCLK/fPC_CLK = 8. 11 = fREFCLK/fPC_CLK = 16. 1 = enable PLL cross-point controller. PLL VCO divider. This divider determines the ratio of the VCO frequency to the DACCLK frequency. 00 = fVCO/fDACCLK = 1. 01 = fVCO/fDACCLK = 2. 10 = fVCO/fDACCLK = 4. 11 = fVCO/fDACCLK = 4. PLL loop divider. This divider determines the ratio of the DACCLK frequency to the REFCLK frequency. 00 = fDACCLK/fREFCLK = 2. 01 = fDACCLK/fREFCLK = 4. 10 = fDACCLK/fREFCLK = 8. 11 = fDACCLK/fREFCLK = 16. 1 = the PLL-generated clock is tracking the REFCLK input signal. VCO control voltage readback. See Table 24. Indicates the VCO band currently selected. 1 = enable the synchronization logic. 0 = operate the synchronization at the FIFO reset rate. 1 = operate the synchronization at the data rate. 0 = sync is initiated on the falling edge of the sync input. 1 = sync is initiated on the rising edge of the sync input. Sets the number of input samples that are averaged in determining the sync phase. 000 = 1. 001 = 2. 010 = 4. 011 = 8. 100 = 16. 101 = 32. 110 = 64. 111 = 128. This register sets the requested clock phase offset after sync. The offset unit is in DACCLK cycles. This register enables repositioning of the DAC output with respect to the sync input. The offset can also be used to skew the DAC outputs between the synchronized DACs. 000000 = 0 DACCLK cycles. 000001 = 1 DACCLK cycle. … 111111 = 63 DACCLK cycles. Rev. B | Page 24 of 60 Default 11 1 10 01 N/A N/A N/A 0 1 1 000 000000 Data Sheet Register Name Sync Status Address (Hex) 0x12 0x13 Data Receiver Status 0x15 AD9121 Bits 7 6 [7:0] Name Sync lost Sync locked Sync Phase Readback[7:0] 5 4 LVDS FRAME level high LVDS FRAME level low 3 2 LVDS DCI level high LVDS DCI level low LVDS data level high LVDS data level low DCI Delay[1:0] DCI Delay 0x16 1 0 [1:0] FIFO Control 0x17 [2:0] FIFO Phase Offset[2:0] FIFO Status 0x18 7 6 2 1 FIFO Warning 1 FIFO Warning 2 FIFO soft align acknowledge FIFO soft align request [7:0] FIFO Level[7:0] 0x19 Description 1 = synchronization was attained but has been lost. 1 = synchronization has been attained. Indicates the averaged sync phase offset (6.2 format). If this value differs from the Sync Phase Request[5:0] value in Register 0x11, a sync timing error has occurred. For more information, see the Sync Status Bits section. 00000000 = 0.0. 00000001 = 0.25. … 11111110 = 63.50. 11111111 = 63.75. One or both LVDS FRAME input signals have exceeded 1.7 V. One or both LVDS FRAME input signals have crossed below 0.7 V. One or both LVDS DCI input signals have exceeded 1.7 V. One or both LVDS DCI input signals have crossed below 0.7 V. One or more LVDS Dx input signals have exceeded 1.7 V. One or more LVDS Dx input signals have crossed below 0.7 V. This option is available for the Revision 2 silicon only. The DCI delay bits control the delay applied to the DCI signal. The DCI delay affects the sampling interval of the DCI with respect to the Dx inputs. See Table 13. 00 = 350 ps delay of DCI signal. 01 = 590 ps delay of DCI signal. 10 = 800 ps delay of DCI signal. 11 = 925 ps delay of DCI signal. FIFO write pointer phase offset following FIFO reset. This is the difference between the read pointer and the write pointer values upon FIFO reset. The optimal value is nominally 4 (100). 000 = 0. 001 = 1. … 111 = 7. 1 = FIFO read and write pointers are within ±1. 1 = FIFO read and write pointers are within ±2. 1 = FIFO read and write pointers are aligned after a serial port initiated FIFO reset. 1 = request FIFO read and write pointer alignment via the serial port. Thermometer encoded measure of the FIFO level. Rev. B | Page 25 of 60 Default N/A N/A N/A N/A N/A N/A N/A N/A N/A 00 100 N/A N/A N/A 0 N/A AD9121 Register Name Datapath Control Data Sheet Address (Hex) 0x1B Bits 7 6 5 3 Name Bypass premod Bypass sinc−1 Bypass NCO NCO gain 2 1 Bypass phase compensation and dc offset Select sideband 0 Send I data to Q data HB1 Control 0x1C [2:1] HB1[1:0] HB2 Control 0x1D 0 [6:1] Bypass HB1 HB2[5:0] 0 Bypass HB2 Description 1 = bypass the fS/2 premodulator. 1 = bypass the inverse sinc filter. 1 = bypass the NCO. 0 = no gain scaling is applied to the NCO input to the internal digital modulator (default). 1 = gain scaling of 0.5 is applied to the NCO input to the internal digital modulator. Gain scaling can eliminate saturation of the modulator output for some combinations of data inputs and NCO signals. 1 = bypass phase compensation and dc offset. Default 1 1 1 0 0 = the modulator outputs the high-side image. 1 = the modulator outputs the low-side image. The image is spectrally inverted compared to the input data. 1 = ignore Q data from the interface and disable the clocks to the Q datapath. Send I data to both the I and Q DACs. Modulation mode for I Side Half-Band Filter 1. 00 = input signal not modulated; filter pass band is from −0.4 to +0.4 of fIN1. 01 = input signal not modulated; filter pass band is from 0.1 to 0.9 of fIN1. 10 = input signal modulated by fIN1; filter pass band is from 0.6 to 1.4 of fIN1. 11 = input signal modulated by fIN1; filter pass band is from 1.1 to 1.9 of fIN1. 1 = bypass the first-stage interpolation filter. Modulation mode for I Side Half-Band Filter 2. 000000 = input signal not modulated; filter pass band is from −0.25 to +0.25 of fIN2. 001001 = input signal not modulated; filter pass band is from 0.0 to 0.5 of fIN2. 010010 = input signal not modulated; filter pass band is from 0.25 to 0.75 of fIN2. 011011 = input signal not modulated; filter pass band is from 0.5 to 1.0 of fIN2. 100100 = input signal modulated by fIN2; filter pass band is from 0.75 to 1.25 of fIN2. 101101 = input signal modulated by fIN2; filter pass band is from 1.0 to 1.5 of fIN2. 110110 = input signal modulated by fIN2; filter pass band is from 1.25 to 1.75 of fIN2. 111111 = input signal modulated by fIN2; filter pass band is from 1.5 to 2.0 of fIN2. 1 = bypass the second-stage interpolation filter. 0 Rev. B | Page 26 of 60 1 0 00 0 000000 0 Data Sheet AD9121 Register Name HB3 Control Address (Hex) 0x1E Bits [6:1] Name HB3[5:0] Chip ID FTW LSB FTW FTW FTW MSB 0x1F 0x30 0x31 0x32 0x33 0 [7:0] [7:0] [7:0] [7:0] [7:0] Bypass HB3 Chip ID[7:0] FTW[7:0] FTW[15:8] FTW[23:16] FTW[31:24] NCO Phase Offset LSB NCO Phase Offset MSB 0x34 [7:0] NCO Phase Offset[7:0] 0x35 [7:0] NCO Phase Offset[15:8] 0x36 5 FRAME FTW acknowledge 4 FRAME FTW request 0x38 1 0 [7:0] Update FTW acknowledge Update FTW request I Phase Adj[7:0] 0x39 [1:0] I Phase Adj[9:8] Q Phase Adj LSB Q Phase Adj MSB 0x3A [7:0] Q Phase Adj[7:0] 0x3B [1:0] Q Phase Adj[9:8] I DAC Offset LSB I DAC Offset MSB 0x3C [7:0] I DAC Offset[7:0] 0x3D [7:0] I DAC Offset[15:8] NCO FTW Update I Phase Adj LSB I Phase Adj MSB Description Modulation mode for I Side Half-Band Filter 3. 000000 = input signal not modulated; filter pass band is from −0.2 to +0.2 of fIN3. 001001 = input signal not modulated; filter pass band is from 0.05 to 0.45 of fIN3. 010010 = input signal not modulated; filter pass band is from 0.3 to 0.7 of fIN3. 011011 = input signal not modulated; filter pass band is from 0.55 to 0.95 of fIN3. 100100 = input signal modulated by fIN3; filter pass band is from 0.8 to 1.2 of fIN3. 101101 = input signal modulated by fIN3; filter pass band is from 1.05 to 1.45 of fIN3. 110110 = input signal modulated by fIN3; filter pass band is from 1.3 to 1.7 of fIN3. 111111 = input signal modulated by fIN3; filter pass band is from 1.55 to 1.95 of fIN3. 1 = bypass the third-stage interpolation filter. This register identifies the device as an AD9121. See Register 0x33. See Register 0x33. See Register 0x33. FTW[31:0] is the 32-bit frequency tuning word that determines the frequency of the complex carrier generated by the on-chip NCO. The frequency is not updated when the FTW registers are written. The values are only updated when Bit 0 of Register 0x36 transitions from 0 to 1. See Register 0x35. Default 000000 The NCO sets the phase of the complex carrier signal when the NCO is reset. The phase offset spans from 0° to 360°. Each bit represents an offset of 0.0055°. This value is in twos complement format. 1 = the NCO has been reset due to an extended FRAME pulse signal. 0 = the NCO is reset on the first extended FRAME pulse after this bit is set to 1. 1 = the FTW has been updated. The FTW is updated on the 0-to-1 transition of this bit. See Register 0x39. 00000000 0 00001000 00000000 00000000 00000000 00000000 00000000 0 0 0 0 00000000 I Phase Adj[9:0] is used to insert a phase offset between the I and Q datapaths. This offset can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for more information. See Register 0x3B. 00 Q Phase Adj[9:0] is used to insert a phase offset between the I and Q datapaths. This offset can be used to correct for phase imbalance in a quadrature modulator. See the Quadrature Phase Correction section for more information. See Register 0x3D. 00 I DAC Offset[15:0] is a value that is added directly to the samples written to the I DAC. 00000000 Rev. B | Page 27 of 60 00000000 00000000 AD9121 Data Sheet Register Name Q DAC Offset LSB Q DAC Offset MSB I DAC FS Adjust I DAC Control Address (Hex) 0x3E Bits [7:0] Name Q DAC Offset[7:0] Description See Register 0x3F. Default 00000000 0x3F [7:0] Q DAC Offset[15:8] 00000000 0x40 [7:0] I DAC FS Adj[7:0] Q DAC Offset[15:0] is a value that is added directly to the samples written to the Q DAC. See Register 0x41, Bits[1:0]. 0x41 7 [1:0] I DAC sleep I DAC FS Adj[9:8] 0 01 I Aux DAC Data I Aux DAC Control 0x42 [7:0] I Aux DAC[7:0] 1 = puts the I DAC into sleep mode (fast wake-up mode). I DAC FS Adj[9:0] sets the full-scale current of the I DAC. The full-scale current can be adjusted from 8.64 mA to 31.68 mA in step sizes of approximately 22.5 µA. 0x000 = 8.64 mA. … 0x200 = 20.16 mA. … 0x3FF = 31.68 mA. See Register 0x43, Bits[1:0]. 0x43 7 I aux DAC sign 0 6 I aux DAC current direction 5 [1:0] I aux DAC sleep I Aux DAC[9:8] 0x44 [7:0] Q DAC FS Adj[7:0] 0 = the I auxiliary DAC sign is positive, and the current is directed to the IOUT1P pin (Pin 67). 1 = the I auxiliary DAC sign is negative, and the current is directed to the IOUT1N pin (Pin 66). 0 = the I auxiliary DAC sources current. 1 = the I auxiliary DAC sinks current. 1 = puts the I auxiliary DAC into sleep mode. I Aux DAC[9:0] sets the magnitude of the auxiliary DAC current. The range is 0 mA to 2 mA, and the step size is 2 µA. 0x000 = 0.000 mA. 0x001 = 0.002 mA. … 0x3FF = 2.046 mA. See Register 0x45, Bits[1:0]. 0x45 7 [1:0] Q DAC sleep Q DAC FS Adj[9:8] 0x46 [7:0] Q Aux DAC[7:0] Q DAC FS Adjust Q DAC Control Q Aux DAC Data 1 = puts the Q DAC into sleep mode (fast wake-up mode). Q DAC FS Adj[9:0] sets the full-scale current of the Q DAC. The full-scale current can be adjusted from 8.64 mA to 31.68 mA in step sizes of approximately 22.5 µA. 0x000 = 8.64 mA. … 0x200 = 20.16 mA. … 0x3FF = 31.68 mA. See Register 0x47, Bits[1:0]. Rev. B | Page 28 of 60 11111001 00000000 0 0 00 11111001 0 01 00000000 Data Sheet Register Name Q Aux DAC Control Die Temp Range Control Die Temp LSB Die Temp MSB SED Control Compare I0 LSBs Compare I0 MSBs Compare Q0 LSBs Compare Q0 MSBs Compare I1 LSBs Compare I1 MSBs Address (Hex) 0x47 AD9121 Bits 7 Name Q aux DAC sign 6 Q aux DAC current direction 5 [1:0] Q aux DAC sleep Q Aux DAC[9:8] [6:4] FS Current[2:0] [3:1] Reference Current[2:0] 0 Capacitor value 0x49 [7:0] Die Temp[7:0] 0x4A [7:0] Die Temp[15:8] 0x67 7 SED compare enable 5 Sample error detected 3 Autoclear enable 1 Compare fail 0x68 0 [7:0] Compare pass Compare Value I0[7:0] 0x69 [7:0] Compare Value I0[15:8] 0x6A [7:0] Compare Value Q0[7:0] 0x6B [7:0] Compare Value Q0[15:8] 0x6C [7:0] Compare Value I1[7:0] 0x6D [7:0] Compare Value I1[15:8] 0x48 Description 0 = the Q auxiliary DAC sign is positive, and the current is directed to the IOUT2P pin (Pin 58). 1 = the Q auxiliary DAC sign is negative, and the current is directed to the IOUT2N pin (Pin 59). 0 = the Q auxiliary DAC sources current. 1 = the Q auxiliary DAC sinks current. 1 = puts the Q auxiliary DAC into sleep mode. Q Aux DAC[9:0] sets the magnitude of the auxiliary DAC current. The range is 0 mA to 2 mA, and the step size is 2 µA. 0x000 = 0.000 mA. 0x001 = 0.002 mA. … 0x3FF = 2.046 mA. Auxiliary ADC full-scale current. 000 = lowest current. … 111 = highest current. Auxiliary ADC reference current. 000 = lowest current. … 111 = highest current. Auxiliary ADC internal capacitor value. 0 = 5 pF. 1 = 10 pF. See Register 0x4A. Default 0 Die Temp[15:0] indicates the approximate die temperature. For more information, see the Temperature Sensor section. 1 = enable the SED circuitry. None of the flags in this register or the values in Register 0x70 through Register 0x73 are significant if the SED is not enabled. 1 = indicates that an error was detected. The bit remains set until cleared. Any write to this register clears this bit to 0. 1 = enable autoclear mode. This activates Bit 1 and Bit 0 of this register and causes Register 0x70 through Register 0x73 to be autocleared when eight consecutive sample data sets are received error free. 1 = indicates that an error was detected. This bit remains set until it is autocleared by the reception of eight consecutive error-free comparisons or is cleared by a write to this register. 1 = indicates that the last sample comparison was error free. See Register 0x69. N/A 0 0 00 000 001 0 N/A 0 0 0 0 0 10110110 Compare Value I0[15:0] is the word that is compared with the I0 input sample captured at the input interface. See Register 0x6B. 01111010 Compare Value Q0[15:0] is the word that is compared with the Q0 input sample captured at the input interface. See Register 0x6D. 11101010 Compare Value I1[15:0] is the word that is compared with the I1 input sample captured at the input interface. Rev. B | Page 29 of 60 01000101 00010110 00011010 AD9121 Register Name Compare Q1 LSBs Compare Q1 MSBs SED I LSBs SED I MSBs SED Q LSBs SED Q MSBs Revision Data Sheet Address (Hex) 0x6E Bits [7:0] Name Compare Value Q1[7:0] Description See Register 0x6F. Default 11000110 0x6F [7:0] Compare Value Q1[15:8] 10101010 0x70 [7:0] 0x71 [7:0] [7:0] Errors Detected I_BITS[15:0] indicates which bits were received in error. See Register 0x73. 00000000 0x72 0x73 [7:0] 0x7F [5:2] Errors Detected I_BITS[7:0] Errors Detected I_BITS[15:8] Errors Detected Q_BITS[7:0] Errors Detected Q_BITS[15:8] Revision[3:0] Compare Value Q1[15:0] is the word that is compared with the Q1 input sample captured at the input interface. See Register 0x71. Errors Detected Q_BITS[15:0] indicates which bits were received in error. This value corresponds to the die revision number. Rev. B | Page 30 of 60 00000000 00000000 00000000 0011 Data Sheet AD9121 LVDS INPUT DATA PORTS Table 12. Data Bit Pair Assignments for Data Input Modes Mode Word Byte 1 1 MSB to LSB D13, D12, …, D0 D12, D10, D8, D6, D5, D3, D1, ByteLSB In byte mode, the unused pins can be left floating. The data is accompanied by a reference bit (DCI) that is used to generate a double data rate (DDR) clock. In byte mode, a FRAME signal is required for controlling to which DAC the data is sent. All of the interface signals are time aligned, so there is a maximum skew requirement on the bus. WORD INTERFACE MODE In word mode, the DCI signal is a reference bit used to generate the data sampling clock. The DCI signal should be time aligned with the data. The I DAC data should correspond to DCI high, and the Q DAC data should correspond to DCI low, as shown in Figure 42. DCI DATA[13:0] Q0 I1 Q1 I1LSB Q1MSB I3 Q3 BYTE INTERFACE MODE In byte mode, the DCI signal is a reference bit used to generate the data sampling clock. The DCI signal should be time aligned with the data. The most significant byte of the data should correspond to DCI high, and the least significant byte of the data should correspond to DCI low. The FRAME signal indicates to which DAC the data is sent. When FRAME is high, data is sent to the I DAC; when FRAME is low, data is sent to the Q DAC. The complete timing diagram is shown in Figure 43. INTERFACE TIMING The timing diagram for the digital interface port is shown in Figure 44. The sampling point of the data bus nominally occurs 350 ps after each edge of the DCI signal and has an uncertainty of ±300 ps, as illustrated by the sampling interval shown in Figure 44. The data and FRAME signals must be valid throughout this sampling interval. The data and FRAME signals may change at any time between sampling intervals. Q1LSB I2MSB I2LSB Q2MSB Q2LSB 09988-016 I1MSB Q2 Figure 42. Timing Diagram for Word Mode DCI DATA[13:0] Q0LSB I2 09988-015 The AD9121 has one LVDS data port that receives data for both the I and Q transmit paths. The device can accept data in word and byte formats. In word mode, the data is sent over a 14-bit LVDS data bus. In byte mode, the data is sent over an 8-bit LVDS data bus in the format of MSB[D13:D6] + LSB[D5:D0]. The 14-bit word is split into an 8-bit MSB portion and a 6-bit LSB portion. The LSB portion should be MSB aligned with the 8-bit LVDS data bus. The pin assignments of the bus in each mode are shown in Table 12. FRAME Figure 43. Timing Diagram for Byte Mode Rev. B | Page 31 of 60 AD9121 Data Sheet The setup (tS) and hold (tH) times, with respect to the edges, are shown in Figure 44. The minimum setup and hold times are shown in Table 13. tDATA FIFO OPERATION The AD9121 contains a 2-channel, 14-bit wide, eight-word deep FIFO designed to relax the timing relationship between the data arriving at the DAC input ports and the internal DAC data rate clock. The FIFO acts as a buffer that absorbs timing variations between the data source and the DAC, such as the clock-to-data variation of an FPGA or ASIC, which significantly increases the timing budget of the interface. tDATA DCI SAMPLING INTERVAL SAMPLING INTERVAL DATA tS 09988-146 tS tH tH Figure 44. Timing Diagram for Input Data Port Table 13. Data to DCI Setup and Hold Times DCI Delay Register 0x16, Bits[1:0] 00 01 10 11 Minimum Hold Time, tH (ns) 0.65 0.95 1.22 1.38 Minimum Setup Time, tS (ns) −0.05 −0.23 −0.38 −0.47 Sampling Interval (ns) 0.6 0.72 0.84 0.91 The data interface timing can be verified by using the sample error detection (SED) circuitry. See the Interface Timing Validation section for more information. RECOMMENDED FRAME INPUT BIAS CIRCUITRY Because the frame signal can be used as a reference clock in the byte mode or as a trigger to reset the FIFO, it is recommended that the frame input be tied to LVDS logic low when it is not used (that is, when it is not driven by an ASIC or FPGA). The external bias circuit shown in Figure 45 is recommended for this purpose. Figure 46 shows the block diagram of the datapath through the FIFO. The data is latched into the device, is formatted, and is then written into the FIFO register determined by the FIFO write pointer. The value of the write pointer is incremented every time a new word is loaded into the FIFO. Meanwhile, data is read from the FIFO register determined by the read pointer and fed into the digital datapath. The value of the read pointer is incremented every time data is read into the datapath from the FIFO. The FIFO pointers are incremented at the data rate (DACCLK rate divided by the interpolation ratio). Valid data is transmitted through the FIFO as long as the FIFO does not overflow or become empty. An overflow or empty condition of the FIFO occurs when the write pointer and read pointer point to the same FIFO location. This simultaneous access of data leads to unreliable data transfer through the FIFO and must be avoided. Nominally, data is written to and read from the FIFO at the same rate. This keeps the FIFO depth constant. If data is written to the FIFO faster than data is read out, the FIFO depth increases. If data is read out of the FIFO faster than data is written to it, the FIFO depth decreases. For optimum timing margin, the FIFO depth should be maintained near half full (a difference of 4 between the write pointer and read pointer values). The FIFO depth represents the FIFO pipeline delay and is part of the overall latency of the AD9121. AD9122 150Ω FRAMEP FRAMEN 5 100Ω 6 DVDD18 (1.8V) 09988-145 51Ω Figure 45. External Bias Circuit Rev. B | Page 32 of 61 Data Sheet AD9121 28 BITS WRITE POINTER READ POINTER REG 0 REG 1 REG 2 DATA INPUT LATCH DATA FORMAT 28 28 REG 3 REG 4 I AND Q DATA PATHS 28 I AND Q DACS REG 5 REG 6 ÷ INT RESET LOGIC FIFO SOFT ALIGN REQUEST REG 0x18[1] DATA/FIFO RATE REG 0x10[6] DACCLK SYNC FIFO PHASE OFFSET REG 0x17[2:0] Figure 46. Block Diagram of FIFO Rev. B | Page 33 of 60 09988-018 FRAME READ POINTER RESET DCI WRITE POINTER RESET REG 7 AD9121 Data Sheet When the AD9121 is powered on, the FIFO depth is unknown. To avoid a concurrent read and write to the same FIFO address and to ensure a fixed pipeline delay, it is important to reset the FIFO pointers to known states. The FIFO pointers can be initialized in two ways: via a write sequence to the serial port or by strobing the FRAME input. There are two types of FIFO resets: a relative reset and an absolute reset. A relative reset enforces a defined FIFO depth. An absolute reset enforces a particular write pointer value when the reset is initiated. A serial port initiated FIFO reset is always a relative reset. A FRAME strobe initiated reset can be either a relative or an absolute reset. If the FRAME differential inputs are not used for FIFO reset or for framing the word width, they must be tied to logic low. FRAMEP must be tied to DVSS, and FRAMEN must be tied to DVDD18 to avoid accidental reset of the FIFO due to noise. The recommended procedure for a serial port FIFO data level initialization is as follows: 1. 2. 3. 4. 5. 6. 7. 8. The operation of the FRAME initiated FIFO reset depends on the synchronization mode chosen.   When synchronization is disabled or when it is configured for data rate mode synchronization, the FRAME strobe initiates a relative FIFO reset. The reference point of the relative reset is the position of the read pointer. When FIFO mode synchronization is chosen, the FRAME strobe initiates an absolute FIFO reset. For more information about the synchronization function, see the Multichip Synchronization section. A summary of the synchronization modes and the types of FIFO reset used is provided in Table 14. Table 14. Summary of FIFO Resets FIFO Reset Signal Serial Port FRAME Synchronization Mode Disabled Data Rate FIFO Reset Relative Relative Relative Relative Relative Absolute Program Register 0x17 to 0x05. Request FIFO level reset by setting Register 0x18, Bit 1, to 1. Verify that the part acknowledges the request by ensuring that Register 0x18, Bit 2, is set to 1. Remove the request by setting Register 0x18, Bit 1, to 0. Verify that the part drops the acknowledge signal by ensuring that Register 0x18, Bit 2, is set to 0. Read back Register 0x19 to verify that the pointer spacing is set to 3 (0x07) or 4 (0x0F). If the readback of Register 0x19 shows a pointer spacing of 2 (0x03), increment Register 0x17 to a spacing of 0x06 and repeat Step 2 through Step 5. Read back Register 0x19 again to verify that the pointer spacing is now set to 3 (0x07). If the readback of Register 0x19 shows a pointer spacing of 5 (0x1F) after Step 6, decrement Register 0x17 to a spacing of 0x04 and repeat Step 2 through Step 5. Read back Register 0x19 again to verify that the pointer spacing is now set to 4 (0x0F). FRAME Initiated Relative FIFO Reset The primary function of the FRAME input is to indicate to which DAC the input data is written. Another function of the FRAME input is to initialize the FIFO data level value. This is done by asserting the FRAME signal high for at least the time interval required to load complete data to the I and Q DACs. This corresponds to one DCI period in word mode and two DCI periods in byte mode. To initiate a relative FIFO reset with the FRAME signal, the device must be configured in data rate mode (Register 0x10, Bit 6 = 1). When FRAME is asserted in data rate mode, the write pointer is set to 4 by default (or to the FIFO start level) the next time that the read pointer becomes 0 (see Figure 47). READ POINTER 0 1 2 3 A serial port initiated FIFO reset can be issued in any synchronization mode and always results in a relative FIFO reset. To initialize the FIFO data level through the serial port, Bit 1 of Register 0x18 should be toggled from 0 to 1 and back. When the write to this register is complete, the FIFO data level is initialized. When the initialization is triggered, the next time that the read pointer becomes 0, the write pointer is set to the value of the FIFO start level variable (Register 0x17, Bits[2:0]) upon initialization. By default, this value is 4, but it can be programmed to a value from 0 to 7. It is recommended that a value of 5 (0x05) be programmed in Register 0x17. WRITE POINTER Rev. B | Page 34 of 60 5 6 7 0 1 2 3 3 4 5 6 FIFO WRITE RESETS FRAME Serial Port Initiated FIFO Reset 4 3 4 5 6 7 0 1 2 Figure 47. FRAME Input vs. Write Pointer Value, Data Rate Mode 09988-019 Resetting the FIFO Data Sheet AD9121 FRAME Initiated Absolute FIFO Reset Monitoring the FIFO Status In FIFO rate synchronization mode, the write pointer of the FIFO is reset in an absolute manner. The synchronization signal aligns the internal clocks on the part to a common reference clock so that the pipeline delay in the digital circuit stays the same during power cycles. The synchronization signal is sampled by the DAC clock in the AD9121. The edge of the DAC clock used to sample the synchronization signal is selected by Bit 3 of Register 0x10. The FIFO initialization and status can be read from Register 0x18. This register provides information about the FIFO status and whether the initialization was successful. The MSB of Register 0x18 is a FIFO warning flag that can optionally trigger a device IRQ. This flag indicates that the FIFO is close to emptying (FIFO level is 1) or overflowing (FIFO level is 7). In this case, data may soon be corrupted, and action should be taken. The FRAME signal is used to reset the FIFO write pointer. In the FIFO rate synchronization mode, the FIFO write pointer is reset immediately after the FRAME signal is asserted high for at least the time interval required to load complete data to the I and Q DACs. The FIFO write pointer is reset to the value of the FIFO Phase Offset[2:0] bits in Register 0x17. FIFO rate synchronization is selected by setting Bit 6 of Register 0x10 to 0. The FIFO data level can be read from Register 0x19 at any time. The serial port reported FIFO data level is denoted as a 7-bit thermometer code (Base 1 code) of the write counter state relative to the absolute read counter being at 0. The optimum FIFO data level of 4 is therefore reported as a value of 00001111 in the status register. READ POINTER FIFO READ RESET 0 FRAME WRITE POINTER 1 2 FIFO WRITE RESET 6 5 6 3 4 5 6 7 0 1 2 3 3 4 5 6 7 FIFO PHASE OFFSET[2:0] REG 0x17[2:0] = 101 7 0 1 2 09988-148 SYNC Note that, depending on the timing relationship between the DCI and the main DACCLK, the FIFO level value can be off by a ±1 count, that is, the readback of Register 0x19 can be 00011111 in the case of a +1 count and 00000111 in the case of a −1 count. Therefore, it is important to keep the difference between the read and write pointers to a value of at least 2. Figure 48. FRAME Input vs. Write Pointer Value, FIFO Rate Mode Rev. B | Page 35 of 60 AD9121 Data Sheet DIGITAL DATAPATH HB1 HB2 HB3 SINC–1 Figure 49. Block Diagram of Digital Datapath The half-band filters operate in several modes, providing programmable pass-band center frequencies as well as signal modulation. The HB1 filter has four modes of operation, and the HB2 and HB3 filters each have eight modes of operation. Half-Band Filter 1 (HB1) HB1 has four modes of operation, as shown in Figure 50. The shape of the filter response is identical in each of the four modes. The four modes are distinguished by two factors: the filter center frequency and whether the input signal is modulated by the filter. MODE 0 The digital datapath accepts I and Q data streams and processes them as a quadrature data stream. The signal processing blocks can be used when the input data stream is represented as complex data. –40 –60 –80 PREMODULATION –100 The half-band interpolation filters have selectable pass bands that allow the center frequencies to be moved in increments of one-half their input data rate. The premodulation block provides a digital upconversion of the incoming waveform by one-half the incoming data rate, fDATA. This can be used to frequency-shift baseband input data to the center of the interpolation filter pass band. INTERPOLATION FILTERS The transmit path contains three interpolation filters. Each of the three interpolation filters provides a 2× increase in output data rate. The half-band (HB) filters can be individually bypassed or cascaded to provide 1×, 2×, 4×, or 8× interpolation ratios. Each half-band filter stage offers a different combination of bandwidths and operating modes. The bandwidth of the three half-band filters with respect to the data rate at the filter input is as follows: • • • MODE 3 –20 MAGNITUDE (dB) The digital datapath can also be used to process an input data stream representing two independent real data streams, but the functionality is somewhat restricted. The premodulation block and any of the nonshifted interpolation filter modes can be used for an input data stream representing two independent real data streams. See the Coarse Modulation Mixing Sequences section for more information. MODE 2 MODE 1 0 Bandwidth of HB1 = 0.8 × fIN1 Bandwidth of HB2 = 0.5 × fIN2 Bandwidth of HB3 = 0.4 × fIN3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 FREQUENCY (× fIN1) (Hz) 09988-021 PREMOD PHASE AND OFFSET ADJUST 09988-020 The block diagram in Figure 49 shows the functionality of the digital datapath. The digital processing includes a premodulation block, three half-band (HB) interpolation filters, a quadrature modulator with a fine resolution NCO, phase and offset adjustment blocks, and an inverse sinc filter. Figure 50. HB1 Filter Modes As shown in Figure 50, the center frequency in each mode is offset by one-half the input data rate (fIN1) of the filter. Mode 0 and Mode 1 do not modulate the input signal. Mode 2 and Mode 3 modulate the input signal by fIN1. When operating in Mode 0 and Mode 2, the I and Q paths operate independently and no mixing of the data between channels occurs. When operating in Mode 1 and Mode 3, mixing of the data between the I and Q paths occurs; therefore, the data input into the filter is assumed to be complex. Table 15 summarizes the HB1 modes. Table 15. HB1 Filter Modes Mode 0 1 2 3 The usable bandwidth is defined as the frequency over which the filters have a pass-band ripple of less than ±0.001 dB and an image rejection of greater than +85 dB. As described in the Half-Band Filter 1 (HB1) section, the image rejection usually sets the usable bandwidth of the filter, not the pass-band flatness. Rev. B | Page 36 of 60 fCENTER DC fIN/2 fIN 3fIN/2 fMOD None None fIN fIN Input Data Real or complex Complex Real or complex Complex Data Sheet AD9121 Figure 51 shows the pass-band filter response for HB1. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 16 shows the pass-band flatness and stop-band rejection supported by the HB1 filter at different bandwidths. Half-Band Filter 2 (HB2) HB2 has eight modes of operation, as shown in Figure 52 and Figure 53. The shape of the filter response is identical in each of the eight modes. The eight modes are distinguished by two factors: the filter center frequency and whether the input signal is modulated by the filter. 0.02 MODE 0 MODE 4 MODE 2 MODE 6 0 0 MAGNITUDE (dB) –0.04 –0.06 –40 –60 –80 –0.08 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 FREQUENCY (× fIN1) (Hz) 0 0.2 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.8 2.0 Figure 52. HB2, Even Filter Modes Table 16. HB1 Pass-Band and Stop-Band Performance by Bandwidth Stop-Band Rejection (dB) 85 80 70 60 50 40 MODE 1 MODE 3 MODE 5 MODE 7 0 –20 MAGNITUDE (dB) Pass-Band Flatness (dB) 0.001 0.0012 0.0033 0.0076 0.0271 0.1096 0.6 FREQUENCY (× fIN2) (Hz) Figure 51. Pass-Band Detail of HB1 Bandwidth (% of fIN1) 80 80.4 81.2 82 83.6 85.6 0.4 09988-023 0 09988-022 –100 –0.10 09988-024 MAGNITUDE (dB) –20 –0.02 –40 –60 –80 –100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 FREQUENCY (× fIN2) (Hz) 1.6 Figure 53. HB2, Odd Filter Modes As shown in Figure 52 and Figure 53, the center frequency in each mode is offset by one-fourth the input data rate (fIN2) of the filter. Mode 0 through Mode 3 do not modulate the input signal. Mode 4 through Mode 7 modulate the input signal by fIN2. When operating in Mode 0 and Mode 4, the I and Q paths operate independently and no mixing of the data between channels occurs. When operating in the other six modes, mixing of the data between the I and Q paths occurs; therefore, the data input to the filter is assumed to be complex. Rev. B | Page 37 of 60 AD9121 Data Sheet Table 17 summarizes the HB2 and HB3 modes. Half-Band Filter 3 (HB3) Table 17. HB2 and HB3 Filter Modes HB3 has eight modes of operation that function the same as HB2. The primary difference between HB2 and HB3 is the filter bandwidths. fCENTER DC fIN/4 fIN/2 3fIN/4 fIN 5fIN/4 3fIN/2 7fIN/4 fMOD None None None None fIN fIN fIN fIN Input Data Real or complex Complex Complex Complex Real or complex Complex Complex Complex Figure 55 shows the pass-band filter response for HB3. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 19 shows the pass-band flatness and stop-band rejection supported by the HB3 filter at different bandwidths. 0.02 Figure 54 shows the pass-band filter response for HB2. In most applications, the usable bandwidth of the filter is limited by the image suppression provided by the stop-band rejection and not by the pass-band flatness. Table 18 shows the pass-band flatness and stop-band rejection supported by the HB2 filter at different bandwidths. 0 MAGNITUDE (dB) Mode 0 1 2 3 4 5 6 7 –0.02 –0.04 –0.06 0.02 –0.08 MAGNITUDE (dB) –0.10 0 –0.02 0.04 0.08 0.12 0.16 0.20 FREQUENCY (× fIN3) (Hz) 0.24 0.28 09988-026 0 Figure 55. Pass-Band Detail of HB3 –0.04 Table 19. HB3 Pass-Band and Stop-Band Performance by Bandwidth –0.06 –0.10 0 0.04 0.08 0.12 0.16 0.20 0.24 FREQUENCY (× fIN2) (Hz) 0.28 0.32 09988-025 –0.08 Figure 54. Pass-Band Detail of HB2 Table 18. HB2 Pass-Band and Stop-Band Performance by Bandwidth Bandwidth (% of fIN2) 50 50.8 52.8 56 60 64.8 Pass-Band Flatness (dB) 0.001 0.0012 0.0028 0.0089 0.0287 0.1877 Bandwidth (% of fIN3) 40 40.8 42.4 45.6 49.8 55.6 Stop-Band Rejection (dB) 85 80 70 60 50 40 Rev. B | Page 38 of 60 Pass-Band Flatness (dB) 0.001 0.0014 0.002 0.0093 0.03 0.1 Stop-Band Rejection (dB) 85 80 70 60 50 40 Data Sheet AD9121 I DATA INTERPOLATION COSINE FTW[31:0] NCO NCO PHASE OFFSET [15:0] OUT_I SINE OUT_Q – + –1 Q DATA 0 1 09988-027 SPECTRAL INVERSION INTERPOLATION Figure 56. Digital Quadrature Modulator Block Diagram NCO MODULATION The digital quadrature modulator makes use of a numerically controlled oscillator (NCO), a phase shifter, and a complex modulator to provide a means for modulating the signal by a programmable carrier signal. A block diagram of the digital modulator is shown in Figure 56. The fine modulation provided by the digital modulator, in conjunction with the coarse modulation of the interpolation filters and premodulation block, allows the signal to be placed anywhere in the output spectrum with very fine frequency resolution. The quadrature modulator is used to mix the carrier signal generated by the NCO with the I and Q signal. The NCO produces a quadrature carrier signal to translate the input signal to a new center frequency. A complex carrier signal is a pair of sinusoidal waveforms of the same frequency, offset 90° from each other. The frequency of the complex carrier signal is set via FTW[31:0] in Register 0x30 through Register 0x33. The NCO operating frequency, fNCO, is at either fDATA (HB1 bypassed) or 2× fDATA (HB1 enabled). The frequency of the complex carrier signal can be set from dc up to fNCO. The frequency tuning word (FTW) is calculated as Given these four parameters, the first step in configuring the datapath is to verify that the device supports the bandwidth requirements. The modes of the interpolation filters are then chosen. Finally, any additional frequency offset requirements are determined and applied with premodulation and NCO modulation. Determining the Datapath Signal Bandwidth The available signal bandwidth of the datapath is dependent on the center frequency of the output signal in relation to the center frequency of the interpolation filters used. Signal center frequencies offset from the center frequencies of the half-band filters lower the available signal bandwidth. When correctly configured, the available complex signal bandwidth for 2× interpolation is always 80% of the input data rate. The available signal bandwidth for 4× interpolation vs. output frequency varies between 50% and 80% of the input data rate, as shown in Figure 57. Note that in 4× interpolation mode, fDAC = 4 × fDATA; therefore, the data shown in Figure 57 repeats four times from dc to fDAC. HB1 AND HB2 FTW  f CARRIER  2 32 f NCO The generated quadrature carrier signal is mixed with the I and Q data. The quadrature products are then summed into the I and Q datapaths, as shown in Figure 56. BANDWIDTH/ fDATA 0.8 0.5 HB2 AND HB3 0.3 The frequency tuning word registers are not updated immediately upon writing, as other configuration registers are. After loading the FTW registers with the desired values, Bit 0 of Register 0x36 must transition from 0 to 1 for the new FTW to take effect. DATAPATH CONFIGURATION Configuring the AD9121 datapath starts with the application requirements of the input data rate, the interpolation ratio, the output signal bandwidth, and the output signal center frequency. 0.2 0.4 0.6 fOUT/fDATA 0.8 1.0 09988-028 Updating the Frequency Tuning Word Figure 57. Signal Bandwidth vs. Center Frequency of the Output Signal, 4× Interpolation Configuring 4× interpolation using the HB2 and HB3 filters can lower the power consumption of the device at the expense of bandwidth. The lower curve in Figure 57 shows that the supported bandwidth in this mode varies from 30% to 50% of fDATA. Rev. B | Page 39 of 60 AD9121 Data Sheet The available signal bandwidth for 8× interpolation vs. output frequency varies between 50% and 80% of the input data rate, as shown in Figure 58. Note that in 8× interpolation mode, fDAC = 8 × fDATA; therefore, the data shown in Figure 58 repeats eight times from dc to fDAC. HB1, HB2, AND HB3 0.6 Table 20 shows the recommended interpolation filter settings for a variety of filter interpolation factors, filter center frequencies, and signal modulation. The interpolation modes were chosen based on the final center frequency of the signal and by determining the frequency shift of the signal required. When these parameters are known and put in terms of the input data rate (fDATA), the filter configuration that comes closest to matching is selected from Table 20. 0.5 0.1 0.25 0.4 0.50 0.6 0.75 fOUT/fDATA 0.9 1.00 09988-029 BANDWIDTH/ fDATA 0.8 DETERMINING INTERPOLATION FILTER MODES Figure 58. Signal Bandwidth vs. Center Frequency of the Output Signal, 8× Interpolation Table 20. Recommended Interpolation Filter Modes (Register 0x1C Through Register 0x1E) Interpolation Factor 8 8 82 8 8 8 8 8 8 8 8 8 8 8 8 8 4 43 4 4 4 4 4 4 2 2 2 2 HB1[1:0] 00 (Mode 0) 01 (Mode 1) 10 (Mode 2) 11 (Mode 3) 00 (Mode 0) 01 (Mode 1) 10 (Mode 2) 11 (Mode 3) 00 (Mode 0) 01 (Mode 1) 10 (Mode 2) 11 (Mode 3) 00 (Mode 0) 01 (Mode 1) 10 (Mode 2) 11 (Mode 3) 00 (Mode 0) 01 (Mode 1) 10 (Mode 2) 11 (Mode 3) 00 (Mode 0) 01 (Mode 1) 10 (Mode 2) 11 (Mode 3) 00 (Mode 0) 01 (Mode 1) 10 (Mode 2) 11 (Mode 3) Filter Modes HB2[5:0] 000000 001001 010010 011011 100100 101101 110110 111111 000000 001001 010010 011011 100100 101101 110110 111111 000000 001001 010010 011011 100100 101101 110110 111111 Bypass Bypass Bypass Bypass HB3[5:0] 000000 000000 001001 001001 010010 010010 011011 011011 100100 100100 101101 101101 110110 110110 111111 111111 Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass Bypass 1 fSIGNAL Modulation DC DC1 fDATA fDATA1 2fDATA 2fDATA1 3fDATA 3fDATA1 4fDATA 4fDATA1 5fDATA 5fDATA1 6fDATA 6fDATA1 7fDATA 7fDATA1 DC DC1 fDATA fDATA1 2fDATA 2fDATA1 3fDATA 3fDATA1 DC DC1 fDATA fDATA1 fCENTER Shift 0 fDATA/2 fDATA 3fDATA/2 2fDATA 5fDATA/2 3fDATA 7fDATA/2 4fDATA 9fDATA/2 5fDATA 11fDATA/2 6fDATA 13fDATA/2 7fDATA 15fDATA/2 0 fDATA/2 fDATA 3fDATA/2 2fDATA 5fDATA/2 3fDATA 7fDATA/2 0 fDATA/2 fDATA 3fDATA/2 When HB1 Mode 1 or Mode 3 is used, enabling premodulation provides an additional frequency translation of the input signal by fDATA/2, which centers a baseband input signal in the filter pass band. This configuration was used in the 8× interpolation without NCO example (see the 8× Interpolation Without NCO section). 3 This configuration was used in the 4× interpolation with NCO example (see the 4× Interpolation with NCO section). 2 Rev. B | Page 40 of 60 Data Sheet AD9121 DATAPATH CONFIGURATION EXAMPLES 4× Interpolation with NCO 8× Interpolation Without NCO For this example, the following parameters are given: For this example, the following parameters are given:     fDATA = 100 MSPS 8× interpolation fBW = 75 MHz fCENTER = 100 MHz The desired 140 MHz of bandwidth is 56% of fDATA. As shown in Figure 57, the value at 0.7 × fDATA is 0.6. This is calculated as 0.8 − 2(0.7 − 0.6) = 0.6. This verifies that the AD9121 supports a bandwidth of 60% of fDATA, which exceeds the required 56%. The desired 75 MHz of bandwidth is 75% of fDATA. In this case, the ratio of fOUT/fDATA = 100/100 = 1.0. From Figure 58, the bandwidth supported at fDATA is 0.8, which verifies that the AD9121 supports the bandwidth required in this configuration. The signal center frequency is 0.7 × fDATA and, assuming the input signal is at baseband, the frequency shift required is also 0.7 × fDATA. Choosing the second row in the Interpolation Factor column in the 4× interpolation section of Table 20 selects the filter modes that give a center frequency of fDATA/2 with no frequency translation. The selected modes for the three half-band filters are HB1, Mode 1; HB2, Mode 1; and HB3, bypassed. The signal center frequency is fDATA and, assuming the input signal is at baseband, the frequency shift required is also fDATA. Choosing the third row (highlighted by the superscripted number 2) of the Interpolation Factor column from Table 20 selects filter modes that give a center frequency of fDATA and a frequency translation of fDATA. The selected modes for the three half-band filters are HB1, Mode 2; HB2, Mode 2; and HB3, Mode 1. Figure 59 shows how the signal propagates through the interpolation filters. Because Mode 1 of HB1 was selected, the premodulation block should be enabled. This provides fDATA/2 modulation, which centers the baseband input data at the center frequency of HB1. The digital modulator can be used to provide the final frequency translation of 0.2 × fDATA to place the output signal at 0.7 × fDATA, as desired. Because 2 × fIN1 = fIN2 and 2 × fIN2 = fIN3, the signal appears frequency scaled by one-half into each consecutive stage. The output signal band spans 0.15 to 0.35 of fIN3 (400 MHz). Therefore, the output frequency supported is 60 MHz to 140 MHz, which covers the 75 MHz bandwidth centered at 100 MHz, as desired. The formula for calculating the FTW of the NCO is as follows: f CARRIER  2 32 f NCO FTW  where: fCARRIER = 0.2 × fDATA. fNCO = 2 × fDATA. Therefore, FTW = 232/10. 0 2 1 0 3 HB1 0.1 –0.5 0.4 0 3 2 0.25 –0.5 0 3 0.2 0.3 0 1.75 1.5 4 5 2.0 × fIN2 7 6 0.7 0.5 0.15 1.25 1.0 2 –0.2 –0.5 7 6 0.7 1 HB3 2.0 × fIN1 1.5 5 4 0.75 0.5 0.3 0 1.0 1 0 HB2 0.6 0.5 1.0 0.35 1.5 2.0 × fIN3 09988-030     fDATA = 250 MSPS 4× interpolation fBW = 140 MHz fCENTER = 175 MHz Figure 59. Signal Propagation for 8× Interpolation (fDATA Modulation) Rev. B | Page 41 of 60 AD9121 Data Sheet DATA RATES vs. INTERPOLATION MODES Table 22 summarizes the maximum bus speed (fBUS), supported input data rates, and signal bandwidths with the various combinations of bus width modes and interpolation rates. The real signal bandwidth supported is a fraction of the input data rate, which depends on the interpolation filters (HB1, HB2, or HB3) selected. The complex signal bandwidth supported is twice the real signal bandwidth. In general, 2× interpolation is best supported by enabling HB1, and 4× interpolation is best supported by enabling HB1 and HB2. However, in some cases, power dissipation can be lowered by not using HB1. If the bandwidth required is low enough, 2× interpolation can be supported by using HB2, and 4× interpolation can be supported by using HB2 and HB3. COARSE MODULATION MIXING SEQUENCES The coarse digital quadrature modulation occurs within the interpolation filters. The modulation shifts the frequency spectrum of the incoming data by the frequency offset selected. The frequency offsets available are multiples of the input data rate. The modulation is equivalent to multiplying the quadrature input signal by a complex carrier signal, C(t), of the form In practice, this modulation results in the mixing functions shown in Table 21. Table 21. Modulation Mixing Sequences Modulation fS/2 fS/4 3fS/4 fS/8 Note that r = Mixing Sequence I = I, −I, I, −I, … Q = Q, −Q, Q, −Q, … I = I, Q, −I, −Q, … Q = Q, −I, −Q, I, … I = I, −Q, −I, Q, … Q = Q, I, −Q, −I, … I = I, r(I + Q), Q, r(−I + Q), −I, −r(I + Q), −Q, r(I − Q), … Q = Q, r(Q − I), −I, −r(Q + I), −Q, r(−Q + I), I, r(Q + I), … 2 2 As shown in Table 21, the mixing functions of most of the modes cross-couple samples between the I and Q channels. The I and Q channels operate independently only in fS/2 mode. This means that real modulation using both the I and Q DAC outputs can only be done in fS/2 mode. All other modulation modes require complex input data and produce complex output signals. C(t) = cos(ωct) + j sin(ωct) Table 22. Summary of Data Rates and Bandwidths vs. Interpolation Modes (DVDD18, CVDD18 = 1.9 V ± 2%) Bus Width Byte (8 Bits) Word (14 Bits) Filter Modes HB3 HB2 HB1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 1 1 fBUS (Mbps) 1230 1230 1230 1230 1230 615 1230 1000 1230 615 615 307.5 fDATA (Mbps) 307.5 307.5 307.5 307.5 307.5 153.75 615 500 615 307.5 307.5 153.75 Rev. B | Page 42 of 60 Real Signal Bandwidth (MHz) 150 120 75 120 75 60 300 200 150 120 75 60 fDAC (MHz) 307.5 615 615 1230 1230 1230 615 1000 1230 1230 1230 1230 AD9121 Q Phase Adj[9:0] (Register 0x3A and Register 0x3B) works in a similar fashion. When Q Phase Adj[9:0] is set to 1000000000, the Q DAC output moves approximately 1.75° away from the I DAC output, creating an angle of 91.75° between the channels. When Q Phase Adj[9:0] is set to 0111111111, the Q DAC output moves approximately 1.75° toward the I DAC output, creating an angle of 88.25° between the channels. Based on these two endpoints, the combined resolution of the phase compensation register is approximately 3.5°/1024 or 0.00342° per code. DC OFFSET CORRECTION The dc value of the I datapath and the Q datapath can be independently controlled by adjusting the I DAC Offset[15:0] and Q DAC Offset[15:0] values in Register 0x3C through Register 0x3F. These values are added directly to the datapath values. Care should be taken not to overrange the transmitted values. Figure 60 shows how the DAC offset current varies as a function of the I DAC Offset[15:0] and Q DAC Offset[15:0] values. With the digital inputs fixed at midscale (0x0000, twos complement data format), Figure 60 shows the nominal IOUTxP and IOUTxN currents as the DAC offset value is swept from 0 to 65,535. Because IOUTxP and IOUTxN are complementary current outputs, the sum of IOUTxP and IOUTxN is always 20 mA. 0 15 5 10 10 5 15 0x4000 0x8000 20 0xFFFF 0xC000 09988-031 0 0x0000 DAC OFFSET VALUE Figure 60. DAC Output Currents vs. DAC Offset Value INVERSE SINC FILTER The inverse sinc (sinc−1) filter is a nine-tap FIR filter. The composite response of the sinc−1 filter and the sin(x)/x response of the DAC is shown in Figure 61. The composite response has a pass-band ripple of less than ±0.05 dB up to a frequency of 0.4 × fDACCLK. To provide the necessary peaking at the upper end of the pass band, the inverse sinc filters shown have an intrinsic insertion loss of about 3.2 dB. Figure 61 shows the composite frequency response. –3.0 –3.2 –3.4 –3.6 –3.8 –4.0 0 0.1 0.2 0.3 0.4 0.5 fOUT/fDAC 09988-032 Ordinarily, the I and Q channels have an angle of precisely 90° between them. The quadrature phase adjustment is used to change the angle between the I and Q channels. When I Phase Adj[9:0] (Register 0x38 and Register 0x39) is set to 1000000000, the I DAC output moves approximately 1.75° away from the Q DAC output, creating an angle of 91.75° between the channels. When I Phase Adj[9:0] is set to 0111111111, the I DAC output moves approximately 1.75° toward the Q DAC output, creating an angle of 88.25° between the channels. 20 MAGNITUDE (dB) The purpose of the quadrature phase correction block is to enable compensation of the phase imbalance of the analog quadrature modulator following the DAC. If the quadrature modulator has a phase imbalance, the unwanted sideband appears with significant energy. Tuning the quadrature phase adjust value can optimize image rejection in single sideband radios. IOUTxP (mA) QUADRATURE PHASE CORRECTION IOUTxN (mA) Data Sheet Figure 61. Sample Composite Responses of the Sinc−1 Filter with sin(x)/x Roll-Off The sinc−1 filter is disabled by default. It can be enabled by setting the bypass sinc−1 bit to 0 (Register 0x1B, Bit 6). Rev. B | Page 43 of 60 AD9121 Data Sheet DAC INPUT CLOCK CONFIGURATIONS The AD9121 DAC sampling clock (DACCLK) can be sourced directly or by clock multiplying. Clock multiplying uses the on-chip phase-locked loop (PLL), which accepts a reference clock operating at a submultiple of the desired DACCLK rate, most commonly the data input frequency. The PLL then multiplies the reference clock up to the desired DACCLK frequency, which can then be used to generate all the internal clocks required by the DAC. The clock multiplier provides a high quality clock that meets the performance requirements of most applications. Using the on-chip clock multiplier eliminates the need to generate and distribute the high speed DACCLK. when the clock input signal is between 800 mV p-p differential and 1.6 V p-p differential. Whether using the on-chip clock multiplier or sourcing the DACCLK directly, it is necessary that the input clock signal to the device have low jitter and fast edge rates to optimize the DAC noise performance. DIRECT CLOCKING Direct clocking with a low noise clock produces the lowest noise spectral density at the DAC outputs. To select the differential CLK inputs as the source for the DAC sampling clock, set the PLL enable bit (Register 0x0A, Bit 7) to 0. This powers down the internal PLL clock multiplier and selects the input from the DACCLKP and DACCLKN pins as the source for the internal DAC sampling clock. The second mode bypasses the clock multiplier circuitry and allows the DACCLK to be sourced directly to the DAC core. This mode enables the user to source a very high quality clock directly to the DAC core. Sourcing the DACCLK directly through the REFCLKP, REFCLKN, DACCLKP, and DACCLKN pins may be necessary in demanding applications that require the lowest possible DAC output noise, particularly when directly synthesizing signals above 150 MHz. The device also has duty cycle correction circuitry and differential input level correction circuitry. Enabling these circuits can provide improved performance in some cases. The control bits for these functions are in Register 0x08 (see Table 11). CLOCK MULTIPLICATION The on-chip PLL clock multiplication circuit can be used to generate the DAC sampling clock from a lower frequency reference clock. When the PLL enable bit (Register 0x0A, Bit 7) is set to 1, the clock multiplication circuit generates the DAC sampling clock from the lower rate REFCLK input. The functional diagram of the clock multiplier is shown in Figure 63. DRIVING THE DACCLK AND REFCLK INPUTS The differential DACCLK and REFCLK inputs share similar clock receiver input circuitry. Figure 62 shows a simplified circuit diagram of the inputs. The on-chip clock receiver has a differential input impedance of about 10 kΩ. It is self-biased to a commonmode voltage of about 1.25 V. The inputs can be driven by direct coupling differential PECL or LVDS drivers. The inputs can also be ac-coupled if the driving source cannot meet the input compliance voltage of the receiver. The clock multiplication circuit operates such that the VCO outputs a frequency, fVCO, equal to the REFCLK input signal frequency multiplied by N1 × N0. fVCO = fREFCLK × (N1 × N0) DACCLKP, REFCLKP The DAC sampling clock frequency, fDACCLK, is equal to 5kΩ The output frequency of the VCO must be chosen to keep f VCO in the optimal operating range of 1.0 GHz to 2.1 GHz. The frequency of the reference clock and the values of N1 and N0 must be chosen so that the desired DACCLK frequency can be synthesized and the VCO output frequency is in the correct range. Figure 62. Clock Receiver Input Simplified Equivalent Circuit The minimum input drive level to either of the clock inputs is 100 mV p-p differential. The optimal performance is achieved REG 0x06[7:6] PLL LOCK LOST PLL LOCKED REFCLKP/REFCLKN (PIN 69 AND PIN 70) PHASE DETECTION ADC LOOP FILTER REG 0x0E[3:0] VCO CONTROL VOLTAGE VCO ÷N1 ÷N0 REG 0x0D[1:0] N1 REG 0x0D[3:2] N0 DACCLK DACCLKP/DACCLKN (PIN 2 AND PIN 3) REG 0x0A[7] PLL ENABLE REG 0x0D[7:6] ÷N2 N2 PC_CLK Figure 63. PLL Clock Multiplication Circuit Rev. B | Page 44 of 60 09988-034 DACCLKN, REFCLKN fDACCLK = fREFCLK × N1 1.25V 09988-033 5kΩ Data Sheet AD9121 PLL SETTINGS Manual VCO Band Select Three settings for the PLL circuitry should be programmed to their nominal values. The PLL values shown in Table 23 are the recommended settings for these parameters. The device also has a manual band select mode (PLL manual enable, Register 0x0A, Bit 6 = 1) that allows the user to select the VCO tuning band. In manual mode, the VCO band is set directly with the value written to the manual VCO band bits (Register 0x0A, Bits[5:0]). To properly select the VCO band, follow these steps: Table 23. PLL Settings Register Address 0x0C 0x0C 0x0D PLL Control Register PLL Loop Bandwidth[1:0] PLL Charge Pump Current[4:0] PLL Cross-Control Enable Bits [7:6] [4:0] 4 Optimal Setting 11 10001 1 1. 2. 3. CONFIGURING THE VCO TUNING BAND The PLL VCO has a valid operating range from approximately 1.0 GHz to 2.1 GHz covered in 63 overlapping frequency bands. For any desired VCO output frequency, there may be several valid PLL band select values. The frequency bands of a typical device are shown in Figure 64. Device-to-device variations and operating temperature affect the actual band frequency range. Therefore, it is required that the optimal PLL band select value be determined for each individual device. 4. 5. 0 Put the device in manual band select mode by setting Register 0x0A, Bit 6 = 1. Sweep the VCO band over a range of bands that results in the PLL being locked. For each band, verify that the PLL is locked and read the PLL using the VCO control voltage bits (Register 0x0E, Bits[3:0]). Select the band that results in the control voltage being closest to the center of the range, that is, 1001 or 1000 (see Table 24). The resulting VCO band should be the optimal setting for the device. Write this value to the manual VCO band bits (Register 0x0A, Bits[5:0]). If desired, an indication of where the VCO is within the operating frequency band can be determined by querying the VCO control voltage. Table 24 shows how to interpret the PLL VCO control voltage value (Register 0x0E, Bits[3:0]). 4 Table 24. VCO Control Voltage Range Indications 8 12 16 PLL BAND 20 24 28 32 36 40 44 48 52 56 1000 1200 1400 1600 1800 2000 2200 VCO FREQUENCY (MHz) 09988-035 60 Figure 64. PLL Lock Range over Temperature for a Typical Device Automatic VCO Band Select The device has an automatic VCO band select feature on chip. Using the automatic VCO band select feature is a simple and reliable method of configuring the VCO frequency band. This feature is enabled by starting the PLL in manual mode, and then placing the PLL in auto band select mode. This is done by setting Register 0x0A to a value of 0xCF, and then to a value of 0xA0. When these values are written, the device executes an automated routine that determines the optimal VCO band setting for the device. The setting selected by the device ensures that the PLL remains locked over the full −40°C to +85°C operating temperature range of the device without further adjustment. (The PLL remains locked over the full temperature range even if the temperature during initialization is at one of the temperature extremes.) VCO Control Voltage (Register 0x0E, Bits[3:0]) 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000 Rev. B | Page 45 of 60 Indication Move to higher VCO band VCO is operating in the higher end of the frequency band VCO is operating within an optimal region of the frequency band VCO is operating in the lower end of the frequency band Move to lower VCO band AD9121 Data Sheet ANALOG OUTPUTS TRANSMIT DAC OPERATION I DAC FS ADJUST REGISTER 0x40 IOUT1P 15 10 CURRENT SCALING 10kΩ RSET 5 IOUT2N IOUT2P 0 0 400 600 800 DAC GAIN CODE Figure 65. Simplified Block Diagram of DAC Core 1000 Figure 66. DAC Full-Scale Current vs. DAC Gain Code The DAC has a 1.2 V band gap reference with an output impedance of 5 kΩ. The reference output voltage appears on the REFIO pin. When using the internal reference, decouple the REFIO pin to AVSS with a 0.1 µF capacitor. Use the internal reference only for external circuits that draw dc currents of 2 µA or less. For dynamic loads or static loads greater than 2 µA, buffer the REFIO pin. If desired, the internal reference can be overdriven by applying an external reference (from 1.10 V to 1.30 V) to the REFIO pin. A 10 kΩ external resistor, RSET, must be connected from the FSADJ pin to AVSS. This resistor, along with the reference control amplifier, sets up the correct internal bias currents for the DAC. Because the full-scale current is inversely proportional to this resistor, the tolerance of RSET is reflected in the full-scale output amplitude. The full-scale current equation, where the DAC gain is set individually for the I and Q DACs in Register 0x40 and Register 0x44, respectively, is as follows: VREF  3  ×  72 +  × DAC gain   RSET   16  200 09988-036 Q DAC Q DAC FS ADJUST REGISTER 0x44 I FS = 20 IOUT1N REFIO FSADJ 25 I DAC 5kΩ 0.1µF 30 09988-037 1.2V 35 IFS (mA) Figure 65 shows a simplified block diagram of the transmit path DACs. The DAC core consists of a current source array, a switch core, digital control logic, and full-scale output current control. The DAC full-scale output current (IFS) is nominally 20 mA. The output currents from the IOUT1P/IOUT2P and IOUT1N/ IOUT2N pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the DAC. The digital input code to the DAC determines the effective differential current delivered to the load. For the nominal values of VREF (1.2 V), RSET (10 kΩ), and DAC gain (512), the full-scale current of the DAC is typically 20.16 mA. The DAC full-scale current can be adjusted from 8.64 mA to 31.68 mA by setting the DAC gain parameter, as shown in Figure 66. Transmit DAC Transfer Function The output currents from the IOUT1P/IOUT2P and IOUT1N/ IOUT2N pins are complementary, meaning that the sum of the two currents always equals the full-scale current of the DAC. The digital input code to the DAC determines the effective differential current delivered to the load. IOUT1P/IOUT2P provide maximum output current when all bits are high. The output currents vs. DACCODE for the DAC outputs are expressed as DACCODE  I OUTxP =   × I FS 2N  (1) I OUTxN = I FS − I OUTxP (2) N where DACCODE = 0 to 2 − 1. Transmit DAC Output Configurations The optimum noise and distortion performance of the AD9121 is realized when it is configured for differential operation. The common-mode error sources of the DAC outputs are significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases and/or its amplitude increases. This is due to the first-order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough, and noise. Rev. B | Page 46 of 60 Data Sheet AD9121 –60 –70 VIP + IOUT1P IFS = 10mA IFS = 20mA IFS = 30mA –65 IMD (dBc) Figure 67 shows the most basic transmit DAC output circuitry. A pair of resistors, RO, is used to convert each of the complementary output currents to a differential voltage output, VOUT. Because the current outputs of the DAC are high impedance, the differential driving point impedance of the DAC outputs, ROUT, is equal to 2 × RO. Figure 68 illustrates the output voltage waveforms. –75 –80 RO VOUTI –85 VIN – IOUT1N –90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VCM (V) VQP + IOUT2P Figure 69. IMD vs. Output Common-Mode Voltage (fOUT = 61 MHz, RLOAD = 50 Ω Differential, IFS = 10 mA, 20 mA, and 30 mA) RO VOUTQ VQN – IOUT2N –50 09988-038 RO 09988-168 RO IFS = 10mA IFS = 20mA IFS = 30mA –55 Figure 67. Basic Transmit DAC Output Circuit IMD (dBc) –60 +VPEAK VCM –65 –70 –75 VN VP –80 –85 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VCM (V) Figure 70. IMD vs. Output Common-Mode Voltage (fOUT = 161 MHz, RLOAD = 50 Ω Differential, IFS = 10 mA, 20 mA, and 30 mA) 09988-039 VOUT –VPEAK 09988-169 0 Figure 68. Output Voltage Waveforms The common-mode signal voltage, VCM, is calculated as I FS × RO 2 The peak output voltage, VPEAK, is calculated as VCM = VPEAK = IFS × RO AUXILIARY DAC OPERATION The AD9121 has two auxiliary DACs: one associated with the I path and one associated with the Q path. These auxiliary DACs can be used to compensate for dc offsets in the transmitted signal. Each auxiliary DAC has a single-ended current that can sink or source current into either the positive (P) or negative (N) output of the associated transmit DAC. The auxiliary DAC structure is shown in Figure 71. VB With this circuit configuration, the single-ended peak voltage is the same as the peak differential output voltage. I AUX DAC[9:0] Transmit DAC Linear Output Signal Swing I AUX DAC CURRENT DIRECTION I AUX DAC SIGN IOUT1P I DAC IOUT1N Figure 71. Auxiliary DAC Structure Rev. B | Page 47 of 60 09988-040 To achieve optimum performance, the DAC outputs have a linear output compliance voltage range that must be adhered to. The linear output signal swing is dependent on the full-scale output current, IFS, and the common-mode level of the output. Figure 69 and Figure 70 show the IMD performance vs. the output common-mode voltage at different full-scale currents and output frequencies. AD9121 Data Sheet The control registers for the I and Q auxiliary DACs are Register 0x42, Register 0x43, Register 0x46, and Register 0x47. Figure 74 shows a fifth-order, low-pass filter. A common-mode choke is used between the I-V resistors and the remainder of the filter. This removes the common-mode signal produced by the DAC and prevents the common-mode signal from being converted to a differential signal, which can appear as unwanted spurious signals in the output spectrum. Splitting the first filter capacitor into two and grounding the center point creates a common-mode low-pass filter, providing additional commonmode rejection of high frequency signals. A purely differential filter can pass common-mode signals. INTERFACING TO MODULATORS The AD9121 interfaces to the ADL537x family of modulators with a minimal number of components. An example of the recommended interface circuitry is shown in Figure 72. AD9121 ADL537x 67 IBBP 66 RLI 100Ω RBIN 50Ω DRIVING THE ADL5375-15 The ADL5375-15 requires a 1500 mV dc bias and, therefore, requires a slightly more complex interface than most other Analog Devices modulators. It is necessary to level-shift the DAC output from a 500 mV dc bias to the 1500 mV dc bias required by the ADL5375-15. Level-shifting can be achieved with a purely passive network, as shown in Figure 73. In this network, the dc bias of the DAC remains at 500 mV, whereas the input to the ADL5375-15 is 1500 mV. This passive, levelshifting network introduces approximately 2 dB of loss in the ac signal. IBBN IOUT1N 59 IOUT2N QBBN RBQP 50Ω 58 RLQ 100Ω 09988-041 RBQN 50Ω QBBP IOUT2P Figure 72. Typical Interface Circuitry Between the AD9121 and the ADL537x Family of Modulators The baseband inputs of the ADL537x family require a dc bias of 500 mV. The nominal midscale output current on each output of the DAC is 10 mA (one-half the full-scale current). Therefore, a single 50 Ω resistor to ground from each of the DAC outputs results in the desired 500 mV dc common-mode bias for the inputs to the ADL537x. The signal level can be reduced through the addition of the load resistor in parallel with the modulator inputs. The peak-to-peak voltage swing of the transmitted signal is VSIGNAL = I FS × AD9121 BASEBAND FILTER IMPLEMENTATION RBIN 66 45.3Ω RLIN RSIN 1kΩ 3480Ω 59 RSQN 1kΩ 50Ω AD9121 22 IBBN QBBN RLQN 3480Ω RBQP 58 45.3Ω RSQP RLQP 1kΩ 3480Ω 5V 10 QBBP Figure 73. Passive, Level-Shifting Network for Biasing the ADL5375-15 22pF 33nH 56nH 33nH 56nH 2pF 50Ω 5V 9 RBQN 45.3Ω IOUT2P Most applications require a baseband anti-imaging filter between the DAC and the modulator to filter out Nyquist images and broadband DAC noise. The filter can be inserted between the I-V resistors at the DAC output and the signal level setting resistor across the modulator input. This establishes the input and output impedances for the filter. IBBP RLIP 3480Ω IOUT2N (2 × R B + R L ) 21 RBIP 45.3Ω IOUT1N (2 × R B × R L ) ADL5375-15 RSIP 1kΩ 67 IOUT1P 09988-043 RBIP 50Ω 3pF 6pF 22pF 140Ω ADL537x 3pF Figure 74. DAC Modulator Interface with Fifth-Order, Low-Pass Filter Rev. B | Page 48 of 60 09988-042 IOUT1P Data Sheet AD9121 REDUCING LO LEAKAGE AND UNWANTED SIDEBANDS Analog quadrature modulators can introduce unwanted signals at the LO frequency due to dc offset voltages in the I and Q baseband inputs, as well as feedthrough paths from the LO input to the output. The LO feedthrough can be nulled by applying the correct dc offset voltages at the DAC output. This can be done using the auxiliary DACs (Register 0x42, Register 0x43, Register 0x46, and Register 0x47) or by using the digital dc offset adjustments (Register 0x3C through Register 0x3F). The advantage of using the auxiliary DACs is that none of the main DAC dynamic range is used to perform the dc offset adjustment. The disadvantage is that the common-mode level of the output signal changes as a function of the auxiliary DAC current. The opposite is true when the digital offset adjustment is used. Good sideband suppression requires both gain and phase matching of the I and Q signals. The I/Q phase adjust registers (Register 0x38 through Register 0x3B) and the DAC FS adjust registers (Register 0x40 and Register 0x44) can be used to calibrate the I and Q transmit paths to optimize sideband suppression. Rev. B | Page 49 of 60 AD9121 Data Sheet DEVICE POWER MANAGEMENT POWER DISSIPATION 1700 The AD9121 has four supply rails: AVDD33, IOVDD, DVDD18, and CVDD18. 1500 1300 POWER (mW) 900 700 500 300 0 50 100 150 200 250 300 fDATA (MHz) 09988-044 100 The IOVDD voltage supplies the serial port I/O pins, the RESET pin, and the IRQ pin. The voltage applied to the IOVDD pin can range from 1.8 V to 3.3 V. The current drawn by the IOVDD supply pin is typically 3 mA. Figure 75. Total Power Dissipation vs. fDATA Without PLL, Fine NCO, or Inverse Sinc 1200 The DVDD18 supply powers all of the digital signal processing blocks of the device. The power consumption from this supply is a function of which digital blocks are enabled and the frequency at which the device is operating. 1× INTERPOLATION 2× INTERPOLATION 4× INTERPOLATION 8× INTERPOLATION 1000 800 POWER (mW) The CVDD18 supply powers the clock receiver and clock distribution circuitry. The power consumption from this supply varies directly with the operating frequency of the device. CVDD18 also powers the PLL. The power dissipation of the PLL is typically 80 mW when enabled. 1100 600 400 200 Figure 75 through Figure 79 show the power dissipation of the AD9121 under a variety of operating conditions. All of the graphs were taken with data being supplied to both the I and Q DACs. The power consumption of the device does not vary significantly with changes in the coarse modulation mode selected or the analog output frequency. Figure 75 through Figure 79 show the total power dissipation, as well as the power dissipation of the DVDD18 and CVDD18 supplies. 0 0 50 100 150 200 250 300 fDATA (MHz) 09988-045 The AVDD33 supply powers the DAC core circuitry. The power dissipation of the AVDD33 supply rail is independent of the digital operating mode and sample rate. The current drawn from the AVDD33 supply rail is typically 55 mA (182 mW) when the fullscale current of the I and Q DACs is set to the nominal value of 20 mA. Changing the full-scale current directly affects the supply current drawn from the AVDD33 rail. For example, if the full-scale current of the I DAC and the Q DAC is changed to 10 mA, the AVDD33 supply current drops by 20 mA to 35 mA. 1× INTERPOLATION 2× INTERPOLATION 4× INTERPOLATION 8× INTERPOLATION Figure 76. DVDD18 Power Dissipation vs. fDATA Without Fine NCO or Inverse Sinc 250 Maximum power dissipation can be estimated to be 20% higher than the typical power dissipation. 1× INTERPOLATION 2× INTERPOLATION 4× INTERPOLATION 8× INTERPOLATION POWER (mW) 200 150 100 50 0 50 100 150 200 250 300 fDATA (MHz) Figure 77. CVDD18 Power Dissipation vs. fDATA with PLL Disabled Rev. B | Page 50 of 60 09988-046 0 Data Sheet AD9121 300 TEMPERATURE SENSOR The AD9121 has a band gap temperature sensor for monitoring the temperature change of the AD9121. The temperature must be calibrated against a known temperature to remove the partto-part variation on the band gap circuit used to sense the temperature. The DACCLK must be running at a minimum of 100 MHz to obtain a reliable temperature measurement. 250 POWER (mW) 200 150 To monitor temperature change, the user must take a reading at a known ambient temperature for a single-point calibration of each AD9121 device. 100 50 Tx = TREF + 7.7 × (Code_x − Code_ref)/1000 + 1 0 200 400 600 800 1000 1200 fDAC (MHz) 09988-047 0 Figure 78. DVDD18 Power Dissipation vs. fDAC Due to Inverse Sinc Filter where: Code_x is the readback code at the unknown temperature, Tx. Code_ref is the readback code at the calibrated temperature, TREF. To use the temperature sensor, it must be enabled by setting Register 0x01, Bit 4, to 0. In addition, to obtain accurate readings, the die temperature range control register (Register 0x48) should be set to 0x02. 300 1× INTERPOLATION 2×, 4×, 8× INTERPOLATION 250 150 100 50 0 50 100 150 200 250 300 fDATA (MHz) 09988-048 POWER (mW) 200 Figure 79. DVDD18 Power Dissipation vs. fDATA Due to Fine NCO Rev. B | Page 51 of 60 AD9121 Data Sheet MULTICHIP SYNCHRONIZATION Multiple devices are considered synchronized to each other when the state of the clock generation state machines is identical for all parts and when time-aligned data is being read from the FIFOs of all parts simultaneously. Devices are considered synchronized to a system clock when there is a fixed and known relationship between the clock generation state machine and the data being read from the FIFO and a particular clock edge of the system clock. The AD9121 has provisions for enabling multiple devices to be synchronized to each other or to a system clock. The AD9121 supports synchronization in two different modes: data rate mode and FIFO rate mode. In data rate mode, the input data rate represents the lowest synchronized clock rate. In FIFO rate mode, the FIFO rate, which is the data rate divided by the FIFO depth of 8, represents the lowest rate clock. The advantage of FIFO rate synchronization is increased time between the setup and hold time windows for DCI changes relative to the DACCLK or REFCLK input. When the synchronization state machine is on in data rate mode, the elasticity of the FIFO is not used to absorb timing variations between the data source and the DAC, resulting in setup and hold time windows repeating at the input data rate. The method chosen for providing the DAC sampling clock directly affects the synchronization methods available. When the device clock multiplier is used, only data rate mode is available. When the DAC sampling clock is sourced directly, both data rate mode and FIFO rate mode synchronization are available. The following sections describe the synchronization methods for enabling both clocking modes and querying the status of the synchronization logic. The full synchronization methods described are used to align multiple dual DACs within one DACCLK cycle. To achieve synchronization within one DACCLK cycle, both the REFCLK and FRAME signals are required to perform back-end and front-end alignment. If synchronization does not need to be this accurate, other options can be used. In data rate mode or in FIFO rate mode, using soft alignment of the FIFO for multiple DACs synchronizes the DAC outputs within two data clock cycles (see the Serial Port Initiated FIFO Reset section). For more information about synchronization, see the AN-1093 Application Note, Synchronization of Multiple AD9122 TxDAC+ Converters. SYNCHRONIZATION WITH CLOCK MULTIPLICATION When using the clock multiplier to generate the DAC sample rate clock, the REFCLK input signal acts as both the reference clock for the PLL-based clock multiplier and the synchronization signal. To synchronize devices, distribute the REFCLK signal with low skew to all the devices that need to be synchronized. Skew between the REFCLK signals of the different devices shows up directly as a timing mismatch at the DAC outputs. Because two clocks are shared on the same signal, an appropriate frequency must be chosen for the synchronization and REFCLK signals. The FRAME and DCI signals can be created in the FPGA along with the data. A circuit diagram of a typical configuration is shown in Figure 80. MATCHED LENGTH TRACES SYSTEM CLOCK REFCLKP/ REFCLKN FRAMEP/ FRAMEN DCIP/ DCIN IOUT1P/ IOUT1N LOW SKEW CLOCK DRIVER REFCLKP/ REFCLKN FPGA FRAMEP/ FRAMEN DCIP/ DCIN IOUT2P/ IOUT2N 09988-049 System demands may require that the outputs of multiple DACs be synchronized with each other or with a system clock. Systems that support transmit diversity or beamforming, where multiple antennas are used to transmit a correlated signal, require multiple DAC outputs to be phase aligned with each other. Systems with a time division multiplexing transmit chain may require one or more DACs to be synchronized with a system-level reference clock. Figure 80. Typical Circuit Diagram for Synchronizing Devices The Procedure for Synchronization When Using the PLL section outlines the steps required to synchronize multiple devices. The procedure assumes that the REFCLK signal is applied to all the devices and that the PLL of each device is phase locked to it. The procedure must be carried out on each individual device. Procedure for Synchronization When Using the PLL In the initialization of the AD9121, all the clock signals (DACCLK, DCI, FRAME, synchronization, and REFCLK) must be present and stable before the synchronization feature is turned on. Configure the AD9121 for periodic data rate synchronization by writing 0xC8 to the sync control register (Register 0x10). Additional synchronization options are available (see the Additional Synchronization Features section). Read the sync status register (Register 0x12) to verify that the sync locked bit (Bit 6) is set high, indicating that the device achieved back-end synchronization, and that the sync lost bit (Bit 7) is low. These levels indicate that the clocks are running with a constant and known phase relative to the synchronization signal. Reset the FIFO by strobing the FRAME signal high for the time interval required to write two complete input data words. Resetting the FIFO ensures that the correct data is being read from the FIFO. This completes the synchronization procedure; all devices should now be synchronized. Rev. B | Page 52 of 60 Data Sheet AD9121 tSKEW REFCLKP(1)/ REFCLKN(1) REFCLKP(2)/ REFCLKN(2) tSDCI tHDCI 09988-050 DCIP(2)/ DCIN(2) FRAMEP(2)/ FRAMEN(2) Figure 81. Timing Diagram Required for Synchronizing Devices SAMPLE RATE CLOCK SYNC CLOCK LOW SKEW CLOCK DRIVER DACCLKP/ DACCLKN REFCLKP/ REFCLKN FRAMEP/ FRAMEN DCIP/ DCIN IOUT1P/ IOUT1N MATCHED LENGTH TRACES DACCLKP/ DACCLKN REFCLKP/ REFCLKN FRAMEP/ FRAMEN DCIP/ DCIN LOW SKEW CLOCK DRIVER IOUT2P/ IOUT2N 09988-051 FPGA Figure 82. Typical Circuit Diagram for Synchronizing Devices to a System Clock To maintain synchronization, the skew between the REFCLK signals of the devices must be less than tSKEW ns. When resetting the FIFO, the FRAME signal must be held high for the time interval required to write two complete input data words. A timing diagram of the input signals is shown in Figure 81. Figure 81 shows a REFCLK frequency equal to the data rate. Although this is the most common situation, it is not strictly required for proper synchronization. Any REFCLK frequency that satisfies the following equation is acceptable. (This equation is valid only when the PLL is used because only data rate mode is available with the PLL on.) fSYNC_I = fDACCLK/2N and fSYNC_I ≤ fDATA where N = 0, 1, 2, or 3. As an example, a configuration with 4× interpolation and clock frequencies of fVCO = 1600 MHz, fDACCLK = 800 MHz, fDATA = 200 MHz, and fSYNC_I = 100 MHz is a viable solution. SYNCHRONIZATION WITH DIRECT CLOCKING When directly sourcing the DAC sample rate clock, a separate REFCLK input signal is required for synchronization. To synchronize devices, the DACCLK signal and the REFCLK signal must be distributed with low skew to all the devices being synchronized. If the devices need to be synchronized to a master clock, use the master clock directly for generating the REFCLK input (see Figure 82). DATA RATE MODE SYNCHRONIZATION The Procedure for Data Rate Synchronization When Directly Sourcing the DAC Sampling Clock section outlines the steps required to synchronize multiple devices in data rate mode. The procedure assumes that the DACCLK and REFCLK signals are applied to all the devices. The procedure must be carried out on each individual device. Procedure for Data Rate Synchronization When Directly Sourcing the DAC Sampling Clock Configure the AD9121 for periodic data rate synchronization by writing 0xC8 to the sync control register (Register 0x10). Additional synchronization options are available (see the Additional Synchronization Features section). Read the sync locked bit (Register 0x12, Bit 6) to verify that the device is back-end synchronized. A high level on this bit indicates that the clocks are running with a constant and known phase relative to the synchronization signal. Reset the FIFO by strobing the FRAME signal high for one complete DCI period. Resetting the FIFO ensures that the correct data is being read from the FIFO of each of the devices simultaneously. Rev. B | Page 53 of 60 AD9121 Data Sheet tDATA correct data is being read from the FIFO of each of the devices simultaneously. DACCLK/ REFCLK This completes the synchronization procedure; all devices should now be synchronized. SAMPLING INTERVAL To ensure that each DAC is updated with the correct data on the same CLK edge, two timing relationships must be met on each DAC. FIFO RATE MODE SYNCHRONIZATION The Procedure for FIFO Rate Synchronization When Directly Sourcing the DAC Sampling Clock section outlines the steps required to synchronize multiple devices in FIFO rate mode. The procedure assumes that the DACCLK and REFCLK signals are applied to all the devices. The procedure must be carried out on each individual device. tSKEW DACCLKP(1)/ DACCLKN(1) DACCLKP(2)/ DACCLKN(2) tSUSYNC tHSYNC Procedure for FIFO Rate Synchronization When Directly Sourcing the DAC Sampling Clock REFCLKP(2)/ REFCLKN(2) tSDCI tHDCI 09988-052 DCIP(2)/ DCIN(2) FRAMEP(2)/ FRAMEN(2) Figure 83. Data Rate Synchronization Signal Timing Requirements, 2× Interpolation Figure 83 shows the synchronization signal timing with 2× interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is shown to be equal to the data rate. The maximum frequency at which the device can be resynchronized in data rate mode can be expressed as fSYNC_I = fDATA/2N Generally, for values of N greater than or equal to 3, select the FIFO rate synchronization mode. When synchronization is used in data rate mode, the timing constraint between the DCI and DACCLK must be met according to Table 25. In data rate mode, the allowed phase drift between the DCI and DACCLK is limited to one DCI cycle. The DCI to DACCLK timing restriction is required to prevent corruption of the data transfer when the FIFO is constantly reset. The required timing between the DCI and DACCLK is shown in Figure 84. Read the sync locked bit (Register 0x12, Bit 6) to verify that the device is back-end synchronized. A high level on this bit indicates that the clocks are running with a constant and known phase relative to the synchronization signal. Reset the FIFO by strobing the FRAME signal high for one complete DCI period. Resetting the FIFO ensures that the correct data is being read from the FIFO of each of the devices simultaneously. When these conditions are met, the outputs of the DACs are updated within one DAC clock cycle of each other. The timing requirements of the input signals are shown in Figure 85. tSKEW DACCLKP(1)/ DACCLKN(1) DACCLKP(2)/ DACCLKN(2) tSUSYNC tHSYNC REFCLKP(2)/ REFCLKN(2) Table 25. DCI to DACCLK Setup and Hold Times Minimum Hold Time, tHDCI (ns) 0.82 1.13 1.40 1.55 Configure the AD9121 for periodic FIFO rate synchronization by writing 0x88 to the sync control register (Register 0x10). Additional synchronization options are available (see the Additional Synchronization Features section). This completes the synchronization procedure; all devices should now be synchronized. where N is any non-negative integer. Minimum Setup Time, tSDCI (ns) −0.07 −0.24 −0.39 −0.49 tHDCI Figure 84. Timing Diagram for Input Data Port (Data Rate Mode) When these conditions are met, the outputs of the DACs are updated within one DAC clock cycle of each other. The timing requirements of the input signals are shown in Figure 83. DCI Delay Register 0x16, Bits[1:0] 00 01 10 11 tSDCI 09988-147  DCI DCIP/DCIN and D[15:0]P/D[15:0]N must meet the setup and hold times with respect to the rising edge of DACCLK. Synchronization (REFCLK) must also meet the setup and hold times with respect to the rising edge of DACCLK. Sampling Interval (ns) 0.75 0.89 1.01 1.06 Rev. B | Page 54 of 60 DCIP(2)/ DCIN(2) FRAMEP(2)/ FRAMEN(2) Figure 85. FIFO Rate Synchronization Signal Timing Requirements, 2× Interpolation 09988-053  Data Sheet AD9121 Figure 85 shows the synchronization signal timing with 2× interpolation; therefore, fDCI = ½ × fCLK. The REFCLK input is shown to be equal to the FIFO rate. The maximum frequency at which the device can be resynchronized in FIFO rate mode can be expressed as fSYNC_I = fDATA/(8 × 2N) where N is any non-negative integer. Timing Optimization ADDITIONAL SYNCHRONIZATION FEATURES Table 26 shows the required timing between the DACCLK and the synchronization clock when synchronization is used. This timing restriction applies to both data rate mode and FIFO rate mode. Table 26. Synchronization Setup and Hold Times Parameter tSKEW tSUSYNC tHSYNC Min −tDACCLK/2 100 330 Max +tDACCLK/2 The sync phase readback bits (Register 0x13, Bits[7:0]) report the current clock phase in a 6.2 format. Bits[7:2] report which of the 64 states (0 to 63) the clock is currently in. When averaging is enabled, Bits[1:0] provide ¼ state accuracy (for 0, ¼, ½, ¾). The lower two bits give an indication of the timing margin issues that may exist. If the synchronization sampling is error free, the fractional clock state should be 00. Unit ps ps ps One-Time Synchronization When implementing the full multichip synchronization feature (with the REFCLK and FRAME signals aligned within one DACCLK cycle), the user may experience difficulty meeting the DACCLK to synchronization clock timing. In this case, a one-time synchronization method can be used. Before implementing the one-time synchronization, make sure that the synchronization signal is locked by checking both the sync signal locked and the sync signal lost flags (Bit 4 and Bit 5 in Register 0x06). It is also important that synchronization not be enabled before stable REFCLK signals are present from the FPGA or ASIC. For more information and a detailed flowchart of the one-time synchronization feature, see the AN-1093 Application Note, Synchronization of Multiple AD9122 TxDAC+ Converters. Sync Status Bits When the sync locked bit (Register 0x12, Bit 6) is set, it indicates that the synchronization logic has reached alignment. This alignment is determined when the clock generation state machine phase is constant. Alignment takes from (11 + averaging) × 64 to (11 + averaging) × 128 DACCLK cycles. The sync locked bit can also trigger an IRQ, as described in the Interrupt Request Operation section. The synchronization signal (REFCLK) is sampled by a version of the DACCLK. If sampling errors are detected, the opposite sampling edge can be selected to improve the sampling point. The sampling edge can be selected by setting Register 0x10, Bit 3 (1 = rising and 0 = falling). The synchronization logic resynchronizes when a phase change between the synchronization signal (REFCLK) and the state of the clock generation state machine exceeds a threshold. To mitigate the effects of jitter and prevent erroneous resynchronizations, the relative phase can be averaged. The amount of averaging is set by the sync averaging bits (Register 0x10, Bits[2:0]) and can be set from 1 to 128. The higher the number of averages, the more slowly the device recognizes and resynchronizes to a legitimate phase correction. Generally, the averaging should be made as large as possible while still meeting the allotted resynchronization time interval. Note that, if the average synchronization sampling result is in approximately the middle of the probability curve, the synchronization engine can be unstable, resulting in corrupted output. The value of the Sync Phase Request[5:0] bits (Register 0x11, Bits[5:0]) is the state to which the clock generation state machine resets upon initialization. By varying this value, the timing of the internal clocks, with respect to the synchronization signal (REFCLK), can be adjusted. Every increment of the Sync Phase Request[5:0] value advances the internal clocks by one DACCLK cycle. This offset can be used for two purposes: to skew the outputs of two synchronized DAC outputs in increments of the DACCLK cycle, and to change the relative timing between the DAC output and the SYNC input (REFCLK). This may allow for a more optimal placement of the DCI sampling point in data rate synchronization mode. When the sync lost bit (Register 0x12, Bit 7) is set, it indicates that a previously synchronized device has lost alignment. This bit is latched and remains set until cleared by overwriting the register. This bit can also trigger an IRQ, as described in the Interrupt Request Operation section. Rev. B | Page 55 of 60 AD9121 Data Sheet INTERRUPT REQUEST OPERATION The AD9121 provides an interrupt request output signal on Pin 7 (IRQ) that can be used to notify an external host processor of significant device events. Upon assertion of the interrupt, the device should be queried to determine the precise event that occurred. The IRQ pin is an open-drain, active low output. Pull the IRQ pin high external to the device. This pin can be tied to the interrupt pins of other devices with open-drain outputs to wire-OR these pins together. When an interrupt enable bit is set low, the event flag bit reflects the current status of the EVENT_FLAG_SOURCE signal, and the event flag has no effect on the external IRQ pin. The latched version of an event flag (the INTERRUPT_SOURCE signal) can be cleared in two ways. The recommended way is by writing 1 to the corresponding event flag bit. A hardware or software reset also clears the INTERRUPT_SOURCE signal. INTERRUPT SERVICE ROUTINE The event flags provide visibility into the device. These flags are located in the two event flag registers, Register 0x06 and Register 0x07. The behavior of each event flag is independently selected in the interrupt enable registers, Register 0x04 and Register 0x05. When the flag interrupt enable is active, the event flag latches and triggers an external interrupt. When the flag interrupt is disabled, the event flag monitors the source signal, but the IRQ pin remains inactive. Interrupt request management starts by selecting the set of event flags that require host intervention or monitoring. The events that require host action should be enabled so that the host is notified when they occur. For events requiring host intervention upon IRQ activation, run the following routine to clear an interrupt request: 1. Figure 86 shows the IRQ-related circuitry and how the event flag signals propagate to the IRQ output. The INTERRUPT_ENABLE signal represents one bit from the interrupt enable register. The EVENT_FLAG_SOURCE signal represents one bit from the event flag register. The EVENT_FLAG_SOURCE signal represents one of the device signals that can be monitored, such as the PLL_LOCKED signal from the PLL phase detector or the FIFO_WARNING_1 signal from the FIFO controller. 2. 3. 4. 5. 6. When an interrupt enable bit is set high, the corresponding event flag bit reflects a positively tripped version of the EVENT_FLAG_SOURCE signal; that is, the event flag bit is latched on the rising edge of the EVENT_FLAG_SOURCE signal. This signal also asserts the external IRQ pin. Read the status of the event flag bits that are being monitored. Set the interrupt enable bit low so that the unlatched EVENT_FLAG_SOURCE signal can be monitored directly. Perform any actions that may be required to clear the EVENT_FLAG_SOURCE. In many cases, no specific actions may be required. Read the event flag to verify that the actions taken have cleared the EVENT_FLAG_SOURCE. Clear the interrupt by writing 1 to the event flag bit. Set the interrupt enable bits of the events to be monitored. Note that some EVENT_FLAG_SOURCE signals are latched signals. These signals are cleared by writing to the corresponding event flag bit. For more information about each event flag, see Register 0x06 and Register 0x07 in Table 11. 0 1 EVENT_FLAG IRQ INTERRUPT_ENABLE EVENT_FLAG_SOURCE INTERRUPT_ SOURCE OTHER INTERRUPT SOURCES 09988-054 WRITE_1_TO_EVENT_FLAG DEVICE_RESET Figure 86. Simplified Schematic of IRQ Circuitry Rev. B | Page 56 of 60 Data Sheet AD9121 INTERFACE TIMING VALIDATION The AD9121 provides on-chip sample error detection (SED) circuitry that simplifies verification of the input data interface. The SED circuitry compares the input data samples captured at the digital input pins with a set of comparison values. The comparison values are loaded into registers through the SPI port. Differences between the captured values and the comparison values are detected and stored. Options are available for customizing SED test sequencing and error handling. The SED has three flag bits (Register 0x67, Bit 5, Bit 1, and Bit 0) that indicate the results of the input sample comparisons. The sample error detected bit (Register 0x67, Bit 5) is set when an error is detected and remains set until cleared. The SED also provides registers that indicate which input data bits experienced errors (Register 0x70 through Register 0x73). These bits are latched and indicate the accumulated errors detected until cleared. Autosample error detection (AED) is an autoclear function in the SED. The autoclear mode has two effects: it activates the compare fail bit and the compare pass bit (Register 0x67, Bit 1 and Bit 0) and changes the behavior of Register 0x70 through Register 0x73. The compare pass bit is set if the last comparison indicated that the sample was error free. The compare fail bit is set if an error is detected. The compare fail bit is automatically cleared by the reception of eight consecutive error-free comparisons. When autoclear mode is enabled, Register 0x70 through Register 0x73 accumulate errors as previously described but are reset to all 0s after eight consecutive error-free sample comparisons are made. SED OPERATION The SED circuitry operates on a data set made up of four 14-bit input words, denoted as I0, Q0, I1, and Q1. To properly align the input samples, the first I data-word (that is, I0) is indicated by asserting FRAME for at least one complete input sample. Figure 87 shows the input timing of the interface in word mode. The FRAME signal can be issued once at the start of the data transmission, or it can be asserted repeatedly at intervals coinciding with the I0 and Q0 data-words. FRAME I0 Q0 I1 Q1 I0 Q0 If desired, the sample error detected, compare pass, and compare fail flags can be configured to trigger the IRQ pin when active. This is done by enabling the appropriate bits in the event flag register (Register 0x07). 09988-056 DATA[13:0] Figure 87. Timing Diagram of Extended FRAME Signal Required to Align Input Data for SED Table 27 shows a progression of the input sample comparison results and the corresponding states of the error flags. Table 27. Progression of Input Sample Comparison Results and the Resulting SED Register Values Compare Results (Pass/Fail) Register 0x67, Bit 5 (Sample Error Detected) Register 0x67, Bit 1 (Compare Fail) Register 0x67, Bit 0 (Compare Pass) Register 0x70 to Register 0x73 (Errors Detected x_BITS[15:0]) 1 2 P 0 0 1 Z1 F 1 1 0 N2 F 1 1 0 N2 F 1 1 0 N2 P 1 1 1 N2 Z = all 0s. N = nonzero. Rev. B | Page 57 of 60 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 1 1 N2 P 1 0 1 Z1 F 1 1 0 N2 P 1 1 1 N2 F 1 1 0 N2 AD9121 Data Sheet 4. SED EXAMPLE Normal Operation The following example illustrates the SED configuration for continuously monitoring the input data and assertion of the IRQ pin when a single error is detected. 1. 2. 3. Load the following comparison values. (Comparison values can be chosen arbitrarily; however, choosing values that require frequent bit toggling provides the most robust test.) Register 0x68: I0[7:0] Register 0x69: I0[15:8] Register 0x6A: Q0[7:0] Register 0x6B: Q0[15:8] Register 0x6C: I1[7:0] Register 0x6D: I1[15:8] Register 0x6E: Q1[7:0] Register 0x6F: Q1[15:8] Enable the SED error detect flag to assert the IRQ pin. (Set Register 0x05 to 0x04.) Begin transmitting the input data pattern. 5. Write to Register 0x67 to enable the SED. (Set Register 0x67 to 0x80.) Clear the SED errors in Register 0x67 and Register 0x07. When the SED is first turned on, the FRAME signal may be detected immediately; therefore, the SED failure bit may be asserted due to the unknown initial FRAME status. For this reason, the SED compare fail status bit must be cleared at least once immediately after enabling the SED. If IRQ is asserted, read Register 0x67 and Register 0x70 through Register 0x73 to verify that a SED error was detected and to determine which input bits were in error. The bits in Register 0x70 through Register 0x73 are latched; therefore, the bits indicate any errors that occurred on those bits throughout the test (not only the errors that caused the error detected flag to be set). Note that the FRAME signal is not required during normal operation when the device is configured for word mode. Enabling the alignment of the I0 sample as described in the SED Operation section requires the use of the FRAME signal. The timing diagram for byte mode is the same as during normal operation and is shown in Figure 43. Rev. B | Page 58 of 60 Data Sheet AD9121 EXAMPLE START-UP ROUTINE To ensure reliable start-up of the AD9121, certain sequences should be followed. This section shows an example start-up routine. This example uses the configuration described in the Device Configuration section. Device Configuration Register Write Sequence: 0x00  0x20 /* Issue Software Reset */ 0x00  0x00 DEVICE CONFIGURATION /* Start PLL */ The following device configuration is used for this example: 0x0D  0xD9 • • • • • • • • • • 0x0A  0xC0 fDATA = 122.88 MSPS Interpolation is 4×, using HB1 = 10 and HB2 = 010010 Input data is baseband data fOUT = 140 MHz fREFCLK = 122.88 MHz PLL is enabled Fine NCO is enabled Inverse sinc filter is enabled Synchronization is enabled Silicon revision is R2 0x0A  0x80 /* Verify PLL is Locked */ Read 0x0E /* Expect bit 7 = 1 */ /* Configure Interpolation Filters */ 0x1B  0x84 0x1C  0x04 0x1D  0x24 DERIVED PLL SETTINGS The following PLL settings can be derived from the device configuration: /* Configure NCO */ • • • • 0x30  0x55 0x1E  0x01 fDACCLK = fDATA × interpolation = 491.52 MHz fVCO = 4 × fDACCLK = 1966.08 MHz (1 GHz < fVCO < 2 GHz) N1 = fDACCLK/fREFCLK = 4 N2 = fVCO/fDACCLK = 4 DERIVED NCO SETTINGS 0x32  0xD5 0x33  0x11 /* Update Frequency Tuning Word */ The following NCO settings can be derived from the device configuration: • • • 0x31  0x55 0x36  0x01 0x36  0x00 fNCO = 2 × fDATA fCARRIER = fOUT − fMODHB1 = 140 − 122.88 = 17.12 MHz FTW = 17.12/(2 × 122.8) × 232 = 0x11D55555 /* Choose Data Rate Mode */ 0x10  0x48 START-UP SEQUENCE The following sequence configures the power clock and register write sequencing for reliable device start-up in PLL on mode: /* Issue Software FIFO Reset */ Power up Device (no specific power supply sequence is required) 0x18  0x02 0x17  0x04 Apply stable REFCLK input signal. /* Verify FIFO Reset */ Apply stable DCI input signal. Read 0x18 Issue H/W RESET (Optional). 0x18  0x00 Read 0x19 Rev. B | Page 59 of 60 /* Expect 0x07 */ /* Expect 0x1F or 0x0F or 0x07 */ AD9121 Data Sheet OUTLINE DIMENSIONS 10.10 10.00 SQ 9.90 0.60 0.42 0.24 0.60 0.42 0.24 0.30 0.23 0.18 55 54 72 1 PIN 1 INDICATOR PIN 1 INDICATOR 9.85 9.75 SQ 9.65 0.50 BSC 0.50 0.40 0.30 18 37 BOTTOM VIEW 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 0.25 MIN 8.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 06-25-2012-A 1.00 0.85 0.80 19 36 TOP VIEW 12° MAX 6.15 6.00 SQ 5.85 EXPOSED PAD Figure 88. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm Body, Very Thin Quad (CP-72-7) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9121BCPZ AD9121BCPZRL AD9121-M5372-EBZ AD9121-M5375-EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 72-lead LFCSP_VQ 72-lead LFCSP_VQ Evaluation Board Connected to ADL5372 Modulator Evaluation Board Connected to ADL5375 Modulator Z = RoHS Compliant Part. ©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D09988-0-10/12(B) Rev. B | Page 60 of 60 Package Option CP-72-7 CP-72-7