16-Bit, 1600 MSPS, TxDAC+ Digital-toAnalog Converter
AD9139
Data Sheet
FEATURES
GENERAL DESCRIPTION
Selectable 1× or 2× interpolation filter
Support input signal bandwidth up to 575 MHz
Very small inherent latency variation: 85 dBc (bandwidth = 300 MHz) at zero IF
Flexible 16-bit LVDS interface
Supports word and byte load
Multiple chip synchronization
Fixed latency and data generator latency compensation
FIFO eases system timing and includes error detection
High performance, low noise PLL clock multiplier
Digital inverse sinc filter
Low power: 700 mW at 1230 MSPS
72-lead LFCSP
The AD9139 is an 16-bit, high dynamic range digital-to-analog
converter (DAC) that provides a sample rate of 1600 MSPS,
permitting a multicarrier generation up to the Nyquist frequency.
The AD9139 TxDAC+® includes features optimized for wideband
communication applications, including 1× and 2× interpolation, a
delay locked loop (DLL) powered high speed interface, sample
error detection, and parity detection. A 3-wire serial port interface
provides for the programming/readback of many internal
parameters. A full-scale output current can be programmed
over a range of 9 mA up to 33 mA. The AD9139 is available
in a 72-lead LFCSP.
PRODUCT HIGHLIGHTS
1.
2.
APPLICATIONS
Wireless communications: 3G/4G and MC-GSM base stations,
wideband repeaters, software defined radios
Wideband communications: point-to-point, LMDS/MMDS
Transmit diversity/MIMO
Instrumentation
Automated test equipment
3.
4.
575 MHz achievable input signal bandwidth.
Advanced low spurious and distortion design techniques
provide high quality synthesis of wideband signals from
baseband to high intermediate frequencies.
Very small inherent latency variation simplifies both software
and hardware design in the system. It allows easy multichip
synchronization for most applications.
Low power architecture improves power efficiency.
FUNCTIONAL BLOCK DIAGRAM
DLL
13-TAP
DCIP/DCIN
AD9139
16
HB1
2×
DACOUTP
DACOUTN
DAC_CLK
GAIN 1
INTERP
MODE CTRL
FIFO CTRL
SED CTRL
INTERFACE CTRL
FRAMEP/PARITYP
FRAMEN/PARITYN
DAC 1
16-BIT
DC OFFSET
CONTROL
GAIN CONTROL
INV SINC
FIFO
8-SAMPLE
SED
D0P/D0N
LVDS DATA
RECEIVER
D15P/D15N
10
REF
AND
BIAS
VREF
FSADJ
INTERNAL CLOCK TIMING AND CONTROL LOGIC
PROGRAMMING
REGISTERS
SERIAL
INPUT/OUTPUT
PORT
POWER-ON
RESET
MULTICHIP
SYNCHRONIZATION
DAC_CLK
CLOCK
MULTIPLIER
DACCLKP
DACCLKN
REF
RCVR
REFP/SYNCP
REFN/SYNCN
11744-001
IRQ2
RESET
TXEN
IRQ1
CS
SCLK
SDIO
SYNC
CLK
RCVR
Figure 1.
Rev. A
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AD9139
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Multidevice Synchronization and Fixed Latency ....................... 29
Applications ....................................................................................... 1
Very Small Inherent Latency Variation ................................... 29
General Description ......................................................................... 1
Further Reducing the Latency Variation................................. 29
Product Highlights ........................................................................... 1
Synchronization Implementation ............................................ 29
Functional Block Diagram .............................................................. 1
Synchronization Procedures ..................................................... 30
Revision History ............................................................................... 3
Interrupt Request Operation ........................................................ 32
Specifications..................................................................................... 4
Interrupt Working Mechanism ................................................ 32
DC Specifications ......................................................................... 4
Interrupt Service Routine .......................................................... 32
Digital Specifications ................................................................... 5
Temperature Sensor ....................................................................... 33
Latency Variation Specifications ................................................ 6
DAC Input Clock Configurations ................................................ 34
AC Specifications.......................................................................... 6
Driving the DACCLK and REFCLK Inputs ........................... 34
Operating Speed Specifications .................................................. 6
Direct Clocking .......................................................................... 34
Absolute Maximum Ratings ....................................................... 7
Clock Multiplication .................................................................. 34
Thermal Resistance ...................................................................... 7
PLL Settings ................................................................................ 35
ESD Caution .................................................................................. 7
Configuring the VCO Tuning Band ........................................ 35
Pin Configuration and Function Descriptions ............................. 8
Automatic VCO Band Select .................................................... 35
Typical Performance Characteristics ........................................... 11
Manual VCO Band Select ......................................................... 35
Terminology .................................................................................... 15
PLL Enable Sequence ................................................................. 35
Serial Port Operation ..................................................................... 16
Analog Outputs............................................................................... 36
Data Format ................................................................................ 16
Transmit DAC Operation.......................................................... 36
Serial Port Pin Descriptions ...................................................... 16
Interfacing to Modulators ......................................................... 37
Serial Port Options ..................................................................... 16
Reducing LO Leakage and Unwanted Sidebands .................. 38
Data Interface .................................................................................. 18
Start-Up Routine ............................................................................ 39
LVDS Input Data Ports .............................................................. 18
Device Configuration Register Map and Description ............... 40
Word Interface Mode ................................................................. 18
SPI Configure Register .............................................................. 42
Byte Interface Mode ................................................................... 18
Power-Down Control Register ................................................. 42
Data Interface Configuration Options .................................... 18
Interrupt Enable 0 Register ....................................................... 42
DLL Interface Mode ................................................................... 18
Interrupt Enable 1 Register ....................................................... 42
Parity ............................................................................................ 21
Interrupt Flag 0 Register............................................................ 43
SED Operation ............................................................................ 21
Interrupt Flag 1 Register............................................................ 43
SED Example ............................................................................... 22
Interrupt Select 0 Register ......................................................... 43
Delay Line Interface Mode ........................................................ 22
Interrupt Select 1 Register ......................................................... 44
FIFO Operation .............................................................................. 24
Frame Mode Register ................................................................. 44
Resetting the FIFO ..................................................................... 25
Data Control 0 Register ............................................................. 44
Serial Port Initiated FIFO Reset ............................................... 25
Data Control 1 Register ............................................................. 44
Frame Initiated FIFO Reset ....................................................... 25
Data Control 2 Register ............................................................. 45
Digital Datapath.............................................................................. 27
Data Control 3 Register ............................................................. 45
Interpolation Filters ................................................................... 27
Data Status 0 Register ................................................................ 45
Inverse Sinc Filter ....................................................................... 28
DAC Clock Receiver Control Register .................................... 46
Digital Function Configuration................................................ 28
Reference Clock Receiver Control Register ............................ 46
Rev. A | Page 2 of 56
Data Sheet
AD9139
PLL Control Register ..................................................................46
Gain Step Control0 Register ...................................................... 52
PLL Control Register ..................................................................47
Gain Step Control1 Register ...................................................... 52
PLL Control Register ..................................................................47
TX Enable Control Register ...................................................... 52
PLL Status Register .....................................................................47
DAC Output Control Register .................................................. 53
PLL Status Register .....................................................................48
DLL Cell Enable 0 Register ........................................................ 53
DAC FS Adjust LSB Register .....................................................48
DLL Cell Enable 1 Register ........................................................ 53
DAC FS Adjust MSB Register ....................................................48
SED Control Register ................................................................. 53
Die Temperature Sensor Control Register ...............................48
SED Pattern S0 Low Bits Register ............................................. 54
Die Temperature LSB Register ..................................................48
SED Pattern S0 High Bits Register ............................................ 54
Die Temperature MSB Register .................................................49
SED Pattern S1 Low Bits Register ............................................. 54
Chip ID Register..........................................................................49
SED Pattern S1 High Bits Register ............................................ 54
Interrupt Configuration Register ..............................................49
SED Pattern S2 Low Bits Register ............................................. 54
Sync CTRL Register ....................................................................49
SED Pattern S2 High Bits Register ............................................ 54
Frame Reset CTRL Register .......................................................49
SED Pattern S3 Low Bits Register ............................................. 54
FIFO Level Configuration Register ..........................................50
SED Pattern S3 High Bits Register ............................................ 55
FIFO Level Readback Register ..................................................50
Parity Control Register ............................................................... 55
FIFO CTRL Register ...................................................................50
Parity Error Rising Edge Register ............................................. 55
Data Format Select Register.......................................................51
Parity Error Falling Edge Register ............................................ 55
Datapath Control Register .........................................................51
Version Register .......................................................................... 55
Interpolation Control Register ..................................................51
Packaging and Ordering Information .......................................... 56
Power-Down Data Input 0 Register..........................................51
Outline Dimensions ................................................................... 56
DAC_DC_OFFSET0 Register ...................................................51
Ordering Guide ........................................................................... 56
DAC_DC_OFFSET1 Register ...................................................51
DAC_GAIN_ADJ Register ........................................................52
REVISION HISTORY
3/14—Rev. 0 to Rev. A
Change to Register 0x7F, Table 21.................................................41
Change to Table 80 ..........................................................................55
10/13—Revision 0: Initial Version
Rev. A | Page 3 of 56
AD9139
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUT
Offset Error
Gain Error
Full-Scale Output Current
Output Compliance Range
Output Resistance
Gain DAC Monotonicity
Settling Time to Within ±0.5 LSB
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD18
DVDD18 Variation over Operating
Conditions 1
POWER CONSUMPTION
1× Mode
2× Mode
Phase-Locked Loop
Inverse Sinc
Reduced Power Mode (Power-Down)
AVDD33 Current
CVDD18 Current
DVDD18 Current
OPERATING RANGE
1
Test Conditions/Comments
Min
Typ
16
Max
±2.1
±3.7
With internal reference
10 kΩ external resistor between FSADJ and AVSS
−0.001
−3.2
19.06
−1.0
0
+2
19.8
LSB
LSB
+0.001
+4.7
20.6
+1.0
10
Guaranteed
20
% FSR
% FSR
mA
V
MΩ
ns
0.04
100
30
1.17
Unit
Bits
ppm/°C
ppm/°C
ppm/°C
1.19
V
kΩ
5
3.13
1.7
3.3
1.8
3.47
1.9
V
V
1.7
−2.5%
1.8
1.9
+2.5%
V
V
57.3
0.4
26.6
4.5
+85
mW
mW
mW
mW
mW
mW
mW
mA
mA
mA
°C
fDAC = 614 MSPS
fDAC = 1230 MSPS
fDAC = 800 MSPS
fDAC = 1600 MSPS
440
700
670
1150
70
60
fDAC = 1230 MSPS
−40
+25
This parameter specifies the maximum allowable variation of DVDD18 over operating conditions compared with the DVDD18 presented to the device at the time the
data interface DLL is enabled.
Rev. A | Page 4 of 56
Data Sheet
AD9139
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 2.
Parameter
CMOS INPUT LOGIC LEVEL
Input
Logic High
Logic Low
CMOS OUTPUT LOGIC LEVEL
Output
Logic High
Logic Low
LVDS RECEIVER INPUTS
Input Voltage Range
Input Differential Threshold
Input Differential Hysteresis
Receiver Differential Input Impedance
DLL SPEED RANGE
DAC UPDATE RATE
DAC Adjusted Update Rate
DAC CLOCK INPUT (DACCLKP, DACCLKN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
REFCLK/SYNCCLK INPUT (REFP/SYNCP,
REFN/SYNCN)
Differential Peak-to-Peak Voltage
Common-Mode Voltage
Input Clock Frequency
SERIAL PORT INTERFACE
Maximum Clock Rate
Minimum Pulse Width
High
Low
SDIO to SCLK Setup Time
SDIO to SCLK Hold Time
CS to SCLK Setup Time
CS to SCLK Hold Time
SDIO to SCLK Delay
Symbol
Min
DVDD18 = 1.8 V
DVDD18 = 1.8 V
1.2
DVDD18 = 1.8 V
DVDD18 = 1.8 V
Data and frame inputs
1.4
VIA or VIB
VIDTH
VIDTHH to VIDTHL
RIN
Typ
825
−175
0.6
V
V
0.4
V
V
575
1600
1150
800
500
1.25
2000
mV
V
100
500
1.25
2000
mV
V
MHz
1.03 GHz ≤ fVCO ≤ 2.07 GHz
SCLK
450
40
MHz
12.5
12.5
Wait time for valid output from
SDIO
Time for SDIO to relinquish the
output bus
1.5
0.68
2.38
9.6
11
Rev. A | Page 5 of 56
1.4
8.5
1.2
With 2 mA loading
With 2 mA loading
mV
mV
mV
Ω
MHz
MSPS
MSPS
MSPS
100
Self biased input, ac-coupled
VIH
VIL
IIH
IIL
Unit
20
100
1× interpolation
2× interpolation
tPWH
tPWL
tDS
tDH
tDCSB
tDCSB
tDV
Max
1675
+175
250
SDIO High-Z to CS
SDIO LOGIC LEVEL
Voltage Input High
Voltage Input Low
Voltage Output High
Voltage Output Low
Test Conditions/Comments
1.36
0
ns
ns
ns
ns
ns
ns
ns
ns
1.8
0
0.5
2
0.45
V
V
V
V
AD9139
Data Sheet
LATENCY VARIATION SPECIFICATIONS
Table 3.
Parameter
DAC LATENCY 1 VARIATION
SYNC Off
SYNC On
1
Min
Typ
Max
Unit
1
0
2
1
DAC clock cycles
DAC clock cycles
DAC latency is defined as the elapsed time from a data sample clocked at the input to the device until the analog output begins to change.
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted.
Table 4.
Parameter
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fDAC = 737.28 MSPS
Bandwidth (BW) = 125 MHz
BW = 270 MHz
fDAC = 983.04 MSPS
BW = 360 MHz
fDAC = 1228.8 MSPS
BW = 200 MHz
BW = 500 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 737.28 MSPS
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
NOISE SPECTRAL DENSITY (NSD)
fDAC = 737.28 MSPS
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR)
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
W-CDMA SECOND (ACLR)
fDAC = 983.04 MSPS
fDAC = 1228.8 MSPS
Test Conditions/Comments
−14 dBFS single tone
fOUT = 200 MHz
Min
Typ
Max
Unit
85
80
dBc
dBc
85
dBc
85
75
dBc
dBc
80
82
80
dBc
dBc
dBc
−160
−161.5
−164.5
dBm/Hz
dBm/Hz
dBm/Hz
81
83
80
dBc
dBc
dBc
85
86
86
dBc
dBc
dBc
fOUT = 200 MHz
fOUT = 280 MHz
−12 dBFS each tone
fOUT = 200 MHz
fOUT = 200 MHz
fOUT = 280 MHz
Eight-tone, 500 kHz tone spacing
fOUT = 200 MHz
fOUT = 200 MHz
fOUT = 280 MHz
Single carrier
fOUT = 200 MHz
fOUT = 20 MHz
fOUT = 280 MHz
Single carrier
fOUT = 200 MHz
fOUT = 20 MHz
fOUT = 280 MHz
OPERATING SPEED SPECIFICATIONS
Table 5.
Interpolation
Factor
1×
2×
DVDD18, CVDD18 = 1.8 V ± 5%
fDCI (MSPS) Max
fDAC (MSPS) Max
575
1150
350
1400
DVDD18, CVDD18 = 1.9 V ± 5% or 1.8 V ± 2%
fDCI (MSPS) Max
fDAC (MSPS) Max
575
1150
375
1500
Rev. A | Page 6 of 56
DVDD18, CVDD18 = 1.9 V ± 2%
fDCI (MSPS) Max
fDAC (MSPS) Max
575
1150
400
1600
Data Sheet
AD9139
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
Parameter
AVDD33 to GND
DVDD18, CVDD18 to GND
FSADJ, VREF, DACOUTP/DACOUTN, to
GND
D15P to D0P/D15N to D0N,
FRAMEP/FRAMEN, DCIP/DCIN to
GND
DACCLKP/DACCLKN,
REFP/SYNCP/REFN/SYNCN to GND
RESET, IRQ1, IRQ2, CS, SCLK, SDIO
to GND
Junction Temperature
Storage Temperature Range
Rating
−0.3 V to +3.6 V
−0.3 V to +2.1 V
−0.3 V to AVDD33 + 0.3 V
−0.3 V to DVDD18 + 0.3 V
−0.3 V to CVDD18 + 0.3 V
The exposed pad (EPAD) must be soldered to the ground plane
(AVSS) for the 72-lead LFCSP. The EPAD provides an electrical,
thermal, and mechanical connection to the board.
Typical θJA, θJB, and θJC values are specified for a 4-layer board in
still air. Airflow increases heat dissipation, effectively reducing
θJA and θJB.
Table 7. Thermal Resistance
−0.3 V to DVDD18 + 0.3 V
Package
72-Lead LFCSP
125°C
−65°C to +150°C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 7 of 56
θJA
20.7
θJB
10.9
θJC
1.1
Unit
°C/W
Conditions
EPAD soldered
to ground plane
AD9139
Data Sheet
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
CVDD18
CVDD18
VREF
FSADJ
AVDD33
DACOUTP
DACOUTN
AVDD33
CVDD18
CVDD18
DACCLKP
DACCLKN
CVDD18
CVDD18
AVDD33
DNC
DNC
AVDD33
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
AD9139
TOP VIEW
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
CS
SCLK
SDIO
IRQ1
IRQ2
DVDD18
DVDD18
D0N
D0P
D1N
D1P
DVDD18
D2N
D2P
D3N
D3P
D4N
D4P
11744-002
DVDD18
D11P
D11N
D10P
D10N
D9P
D9N
D8P
D8N
DCIP
DCIN
D7P
D7N
D6P
D6N
D5P
D5N
DVDD18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CVDD18
REFP/SYNCP
REFN/SYNCN
CVDD18
RESET
TXEN
DVDD18
FRAMEP/PARITYP
FRAMEN/PARITYN
D15P
D15N
DVDD18
D14P
D14N
D13P
D13N
D12P
D12N
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE (AVSS, DVSS, CVSS).
THE EPAD PROVIDES AN ELECTRICAL, THERMAL, AND MECHANICAL CONNECTION TO THE BOARD.
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
Mnemonic
CVDD18
REFP/SYNCP
REFN/SYNCN
CVDD18
RESET
TXEN
7
DVDD18
8
9
10
11
12
FRAMEP/PARITYP
FRAMEN/PARITYN
D15P
D15N
DVDD18
13
14
15
16
17
18
19
D14P
D14N
D13P
D13N
D12P
D12N
DVDD18
20
21
22
23
D11P
D11N
D10P
D10N
Description
1.8 V PLL Supply. CVDD18 supplies the power to the clock receivers, clock multiplier, and clock distribution.
PLL Reference Clock/Synchronization Clock Input, Positive.
PLL Reference Clock/Synchronization Clock Input, Negative.
1.8 V PLL Supply. CVDD18 supplies the power to the clock receivers, clock multiplier, and clock distribution.
Reset, Active Low. CMOS levels with respect to DVDD18. Recommended reset pulse length is 1 µs.
Active High Transmit Path Enable. CMOS levels with respect to DVDD18. A low level on this pin triggers two
selectable actions in the DAC. See Register 0x43 in Table 64 for details.
1.8 V Digital Supply. Pin 7 supplies power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Frame/Parity Input, Positive.
Frame/Parity Input, Negative.
Data Bit 15 (MSB), Positive.
Data Bit 15 (MSB), Negative.
1.8 V Digital Supply. Pin 12 supplies the power to the digital core and digital data ports, serial port
input/output pins, RESET, IRQ1, and IRQ2.
Data Bit 14, Positive.
Data Bit 14, Negative.
Data Bit 13, Positive.
Data Bit 13, Negative.
Data Bit 12, Positive.
Data Bit 12, Negative.
1.8 V Digital Supply. Pin 19 supplies power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Data Bit 11, Positive.
Data Bit 11, Negative.
Data Bit 10, Positive.
Data Bit 10, Negative.
Rev. A | Page 8 of 56
Data Sheet
Pin No.
24
25
26
27
28
29
30
31
32
33
34
35
36
Mnemonic
D9P
D9N
D8P
D8N
DCIP
DCIN
D7P
D7N
D6P
D6N
D5P
D5N
DVDD18
37
38
39
40
41
42
43
D4P
D4N
D3P
D3N
D2P
D2N
DVDD18
44
45
46
47
48
D1P
D1N
D0P
D0N
DVDD18
49
DVDD18
50
IRQ2
51
IRQ1
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
SDIO
SCLK
CS
AVDD33
DNC
DNC
AVDD33
CVDD18
CVDD18
DACCLKN
DACCLKP
CVDD18
CVDD18
AVDD33
DACOUTN
DACOUTP
AVDD33
FSADJ
VREF
CVDD18
AD9139
Description
Data Bit 9, Positive.
Data Bit 9, Negative.
Data Bit 8, Positive.
Data Bit 8, Negative.
Data Clock Input, Positive.
Data Clock Input, Negative.
Data Bit 7, Positive.
Data Bit 7, Negative.
Data Bit 6, Positive.
Data Bit 6, Negative.
Data Bit 5, Positive.
Data Bit 5, Negative.
1.8 V Digital Supply. Pin 36 supplies the power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Data Bit 4, Positive.
Data Bit 4, Negative.
Data Bit 3, Positive.
Data Bit 3, Negative.
Data Bit 2, Positive.
Data Bit 2, Negative.
1.8 V Digital Supply. Pin 43 supplies the power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Data Bit 1, Positive.
Data Bit 1, Negative.
Data Bit 0, Positive.
Data Bit 0, Negative.
1.8 V Digital Supply. Pin 48 supplies the power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
1.8 V Digital Supply. Pin 49 supplies the power to the digital core, digital data ports, serial port input/output
pins, RESET, IRQ1, and IRQ2.
Second Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through a
10 kΩ resistor.
First Interrupt Request. Open-drain, active low output. Connect an external pull-up to DVDD18 through a
10 kΩ resistor.
Serial Port Data Input/Output. CMOS levels with respect to DVDD18.
Serial Port Clock Input. CMOS levels with respect to DVDD18.
Serial Port Chip Select. Active low (CMOS levels with respect to DVDD18).
3.3 V Analog Supply.
Do No Connect. Leave this pin floating.
Do No Connect. Leave this pin floating.
3.3 V Analog Supply.
1.8 V Clock Supply. CVDD18 supplies the power to the clock receivers and clock distribution.
1.8 V Clock Supply. CVDD18 supplies the power to the clock receivers and clock distribution.
DAC Clock Input, Negative.
DAC Clock Input, Positive.
1.8 V Clock Supply. CVDD18 supplies the power to the clock receivers and clock distribution.
1.8 V Clock Supply. CVDD18 supplies the power to the clock receivers and clock distribution.
3.3 V Analog Supply.
DAC Current Output, Negative.
DAC Current Output, Positive.
3.3 V Analog Supply.
Full-Scale Current Output Adjust. Place a 10 kΩ resistor from this pin to AVSS.
Voltage Reference. Nominally 1.2 V output. Decouple VREF to AVSS.
1.8 V Clock Supply. Pin 71 supplies power to the clock receivers, clock multiplier, and clock distribution.
Rev. A | Page 9 of 56
AD9139
Pin No.
72
Mnemonic
CVDD18
EPAD
Data Sheet
Description
1.8 V Clock Supply. Pin 72 supplies power to the clock receivers, clock multiplier, and clock distribution.
Exposed Pad. The exposed pad (EPAD) must be soldered to the ground plane (AVSS, DVSS, CVSS). The EPAD
provides an electrical, thermal, and mechanical connection to the board.
Rev. A | Page 10 of 56
Data Sheet
AD9139
TYPICAL PERFORMANCE CHARACTERISTICS
–40
–40
fDAC = 737.28MHz
fDAC = 983.04MHz
fDAC = 1228.8MHz
–50
–70
–80
–80
–90
–90
–100
0
100
200
300
400
500
600
700
fOUT (MHz)
–100
Figure 3. Single-Tone (0 dBFS) SFDR vs. fOUT in the First Nyquist Zone over fDAC
0
100
150
200
250
300
350
400
fOUT (MHz)
Figure 6. Single-Tone SFDR Excluding 2nd and 3rd Harmonics vs. fOUT in the
First Nyquist Zone over fDAC and Digital Back Off
–40
–40
0dBFS
–6dBFS
–12dBFS
–16dBFS
–50
fDAC = 737.28MHz
fDAC = 983.04MHz
fDAC = 1228.8MHz
–50
–60
–70
–70
–80
–80
–90
–90
100
200
300
400
500
600
700
fOUT (MHz)
–100
11744-004
0
0
100
200
300
400
500
600
700
fOUT (MHz)
Figure 4. Single-Tone Second Harmonic vs. fOUT in the First Nyquist Zone
over Digital Back Off, fDAC = 1228.8 MHz
11744-008
IMD (dBc)
–60
–100
Figure 7. Two-Tone Third IMD vs. fOUT over fDAC
–40
–40
0dBFS
–6dBFS
–12dBFS
–16dBFS
–50
0dBFS
–6dBFS
–12dBFS
–16dBFS
–50
–60
–70
–70
–80
–80
–90
–90
–100
0
100
200
300
400
fOUT (MHz)
500
600
700
Figure 5. Single-Tone Third Harmonic vs. fOUT in the First Nyquist Zone
over Digital Back Off, fDAC = 1228.8 MHz
Rev. A | Page 11 of 56
–100
0
100
200
300
400
500
600
fOUT (MHz)
Figure 8. Two-Tone Third IMD vs. fOUT over Digital Back Off,
fDAC = 1228.8 MHz
700
11744-009
IMD (dBc)
–60
11744-005
THIRD HARMONIC (dBc)
50
11744-006
SFDR (dBc)
–70
11744-003
SFDR (dBc)
0dBFS
–12dBFS
–60
–60
SECOND HARMONIC (dBc)
fDAC = 800MHz
fDAC = 1600MHz
–50
AD9139
Data Sheet
–40
–150
PLL OFF
PLL ON
0dBFS
–12 dBFS
PLL OFF
PLL ON
–50
–155
NSD (dBm/Hz)
IMD (dBc)
–60
–70
–160
–80
–165
0
100
200
300
400
500
600
700
fOUT (MHz)
Figure 9. Two-Tone Third IMD vs. fOUT over PLL on and off,
fDAC = 1228.8 MHz
–145
–170
11744-010
–100
0
100
200
400
300
500
600
700
fOUT (MHz)
11744-013
–90
Figure 12. Single-Tone NSD vs. fOUT, over Digital Back Off, PLL on and off
–60
fDAC = 737.28MHz
fDAC = 983.04MHz
fDAC = 1228.8MHz
fDAC = 1228.8MHz
fDAC = 983.04MHz
–65
–150
PLL OFF
PLL ON
ACLR (dBc)
NSD (dBm/Hz)
–70
–155
–160
–75
–80
–165
0
100
200
300
400
500
600
700
fOUT (MHz)
–90
11744-011
–170
0
100
200
300
400
500
600
fOUT (MHz)
11744-014
–85
Figure 13. 1-Carrier WCDMA 1st Adjacent ACLR vs. fOUT over fDAC
PLL on and off
Figure 10. Single-Tone (0 dBFS) NSD vs. fOUT over fDAC
–150
0dBFS
–6dBFS
–12dBFS
–16dBFS
–60
PLL OFF
PLL ON
–70
ACLR (dBc)
NSD (dBm/Hz)
fDAC = 1228.8MHz
fDAC = 983.04MHz
–65
–155
–160
–75
–80
–165
100
200
300
400
fOUT (MHz)
500
600
700
–90
0
100
200
300
400
500
600
fOUT (MHz)
Figure 11. Single-Tone NSD vs. fOUT, over Digital Back Off, fDAC = 1228.8 MHz
Rev. A | Page 12 of 56
Figure 14. 1-Carrier WCDMA 2nd Adjacent ACLR vs. fOUT over fDAC
PLL on and off
11744-015
0
11744-012
–85
–170
AD9139
11744-017
11744-023
Data Sheet
Figure 15. Two-Tone Third IMD Performance, IF = 200 MHz,
fDAC = 1228.8 MHz, −9 dBFS
Figure 18. 4-Carrier WCDMA ACLR Performance, IF = 200 MHz,
fDAC = 1228.8 MHz
1.0
1× INTERPOLATION
2× INTERPOLATION
0.9
POWER (W)
0.8
0.7
0.6
0.5
0.4
0.2
200
400
600
11744-019
0
800
1000
1200
1400
fDAC (MHz)
11744-024
0.3
Figure 19. Total Power Consumption vs. fDAC over Interpolation
Figure 16. 1-Carrier WCDMA ACLR Performance, IF = 200 MHz,
fDAC = 1228.8 MHz
350
1× INTERPOLATION
2× INTERPOLATION
DVDD18 CURRENT (mA)
300
250
200
150
100
0
11744-021
0
Figure 17. Single-Tone Performance, IF = 200 MH, fDAC = 1228.8 MHz
Rev. A | Page 13 of 56
200
400
600
800
1000
1200
fDAC (MHz)
Figure 20. DVDD18 Current vs. fDAC over Interpolation
1400
11744-025
50
AD9139
Data Sheet
35
250
AVDD33 (mA)
CVDD18 (mA), PLL OFF
CVDD18 (mA), PLL ON
DIGITAL GAIN AND OFFSET
INVERSE SINC
30
SUPPLY CURRENT (mA)
25
20
15
10
150
100
50
0
0
200
400
600
800
1000
1200
1400
fDAC (MHz)
Figure 21. DVDD18 Current vs. fDAC over Digital Functions
0
0
200
400
600
800
1000
1200
fDAC (MHz)
Figure 22. CVDD18 and AVDD18 Current vs. fDAC
Rev. A | Page 14 of 56
1400
11744-027
5
11744-026
DVDD18 CURRENT (mA)
200
Data Sheet
AD9139
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation of the actual analog output from
the ideal output, determined by a straight line drawn from zero
scale to full scale.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Spurious Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the peak amplitude
of the output signal and the peak spurious signal within the dc
to Nyquist frequency of the DAC. Typically, the interpolation
filters reject energy in this band. This specification, therefore,
defines how well the interpolation filters work and the effect of
other parasitic coupling paths on the DAC output.
Offset Error
Offset error is the deviation of the output current from the ideal
of 0 mA. For DACOUTP, 0 mA output is expected when all
inputs are set to 0. For DACOUTN, 0 mA output is expected
when all inputs are set to 1.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the difference between
the output when all inputs are set to 1 and the output when all
inputs are set to 0.
Output Compliance Range
The output compliance range is the range of allowable voltage
at the output of a current output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from
the ambient (25°C) value to the value at either TMIN or TMAX.
For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the
drift is reported in ppm per degree Celsius.
Power Supply Rejection (PSR)
PSR is the maximum change in the full-scale output as the
supplies are varied from minimum to maximum specified
voltages.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
fDATA (interpolation rate), a digital filter can be constructed that
has a sharp transition band near fDATA/2. Images that typically
appear around fDAC (output data rate) can be greatly suppressed.
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in decibels relative to the carrier (dBc) between
the measured power within a channel relative to its adjacent
channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images have the effect
of wasting transmitter power and system bandwidth. By placing
the real part of a second complex modulator in series with the
first complex modulator, either the upper or lower frequency
image near the second IF can be rejected.
Rev. A | Page 15 of 56
AD9139
Data Sheet
SERIAL PORT OPERATION
54 CS
SPI
PORT 53 SCLK
52 SDIO
11744-028
The serial port is a flexible, synchronous serial communications
port that allows easy interfacing to many industry standard microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola SPI and Intel® SSR protocols. The interface allows
read/write access to all registers that configure the AD9139.
MSB first or LSB first transfer formats are supported. The serial
port interface is a 3-wire only interface. The input and output
share a single input/output (SDIO) pin.
SERIAL PORT PIN DESCRIPTIONS
Serial Clock (SCLK)
The serial clock pin, SCLK, synchronizes data to and from the
device and runs the internal state machines. The maximum
frequency of SCLK is 40 MHz. All data input is read on the rising
edge of SCLK. All data is driven out on the falling edge of SCLK.
Chip Select (CS)
Figure 23. Serial Port Interface Pins
There are two phases to a communication cycle with the AD9139.
Phase 1 is the instruction cycle (the writing of an instruction
byte into the device), coincident with the first 16 SCLK rising
edges. The instruction word provides the serial port controller
with information regarding the data transfer cycle, Phase 2, of
the communication cycle. The Phase 1 instruction word defines
whether the upcoming data transfer is a read or write, together
with the starting register address for the following data transfer.
A logic high on the CS pin, followed by a logic low, resets the
serial port timing to the initial state of the instruction cycle.
From this state, the next 16 rising SCLK edges represent the
instruction bits of the current I/O operation.
The remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the device and
the system controller. Phase 2 of the communication cycle is a
transfer of one data byte. Registers change immediately upon
writing to the last bit of each transfer byte.
DATA FORMAT
The instruction byte contains the information shown in Table 9.
Table 9. Serial Port Instruction Word
I15 (MSB)
R/W
A14 to A0 (Bit 14 to Bit 0 of the instruction word) determine
the register that is accessed during the data transfer portion of
the communication cycle. For multibyte transfers, A14 is the
starting address; the device generates the remaining register
addresses based on the SPI_LSB_FIRST bit.
I[14:0]
A[14:0]
R/W (Bit 15 of the instruction word) determines whether a read
or a write data transfer occurs after the instruction word write.
Logic 1 indicates a read operation, and Logic 0 indicates a write
operation.
CS is an active low input that starts and gates a communication
cycle. It allows the use of multiple devices on the same serial
communications line. The SDIO pin enters a high impedance
state when the CS input is high. During the communication
cycle, CS remains low.
Serial Data I/O (SDIO)
The SDIO pin is a bidirectional data line.
SERIAL PORT OPTIONS
The serial port supports both MSB first and LSB first data
formats; the SPI_LSB_FIRST bit (Register 0x00, Bit 6) controls
this functionality. The default is MSB first (SPI_LSB_FIRST = 0).
When SPI_LSB_FIRST = 0 (MSB first), the instruction and data
bits must be written from MSB to LSB. Multibyte data transfers
in MSB first format start with an instruction word that includes the
register address of the most significant data byte. Subsequent data
bytes must follow from high address to low address. In MSB first
mode, the serial port internal word address generator decrements
for each data byte of the multibyte communication cycle.
When SPI_LSB_FIRST = 1 (LSB first), the instruction and data
bits must be written from LSB to MSB. Multibyte data transfers
in LSB first format start with an instruction word that includes the
register address of the least significant data byte. Subsequent data
bytes must follow from low address to high address. In LSB first
mode, the serial port internal word address generator increments
for each data byte of the multibyte communication cycle.
When the MSB first mode is active, the serial port controller
data address decrements from the data address written toward
0x00 for multibyte I/O operations. If the LSB first mode is
active, the serial port controller data address increments from
the data address written toward 0xFF for multibyte I/O
operations.
Rev. A | Page 16 of 56
Data Sheet
AD9139
tDCSB
INSTRUCTION CYCLE
tSCLK
DATA TRANSFER CYCLE
CS
CS
tPWH
SCLK
R/W A14 A13
A3
A2 A1
A0 D7N D6N D5N
D30 D20 D10 D00
tDS
SDIO
Figure 24. Serial Register Interface Timing, MSB First
INSTRUCTION CYCLE
tDH
INSTRUCTION BIT 15
INSTRUCTION BIT 14
11744-031
SCLK
11744-029
SDIO
tPWL
Figure 26. Timing Diagram for Serial Port Register Write
CS
DATA TRANSFER CYCLE
CS
SCLK
A0
A1
A2
A12 A13 A14 R/W D00 D10 D20
D4N D5N D6N D7N
tDV
SDIO
Figure 25. Serial Register Interface Timing, LSB First
DATA BIT n
DATA BIT n – 1
Figure 27. Timing Diagram for Serial Port Register Read
Rev. A | Page 17 of 56
11744-032
SDIO
11744-030
SCLK
AD9139
Data Sheet
DATA INTERFACE
LVDS INPUT DATA PORTS
DATA INTERFACE CONFIGURATION OPTIONS
The AD9139 has a 16-bit LVDS bus that accepts 16-bit data
either in word wide (16-bit) or byte wide (8-bit) formats. In the
word wide interface mode, the data is sent over the entire 16-bit
data bus. In the byte wide interface mode, the data is sent over
the lower 8-bit (D7 to D0) LVDS bus. Table 10 lists the pin
assignment of the bus and the SPI register configuration for
each mode.
To provide more flexibility for the data interface, additional
options are listed in Table 11.
Table 11. Data Interface Configuration Options
Register 0x26, Bit 7
DATA_FORMAT
Table 10. LVDS Input Data Modes
Interface Mode
Word
Byte
Input Data
Width
D15 to D0
D7 to D0
DLL INTERFACE MODE
A source synchronous LVDS interface is used between the data
host and the AD9139 to achieve high data rates while simplifying
the interface. The FPGA or ASIC feeds the AD9139 with 16-bit
input data. Together with the input data, the FPGA or ASIC
provides a DDR DCI.
SPI Register Configuration
Register 0x26, Bit 0 = 0
Register 0x26, Bit 0 = 1
WORD INTERFACE MODE
In word mode, the digital clock input (DCI) signal is a reference
bit that generates a double data rate (DDR) data sampling clock.
Time align the DCI signal with the data.
A delay locked loop (DLL) circuit, designed to operate with
DCI clock rates between 250 MHz and 575 MHz, generates a
phase shifted version of the DCI signal, called a data sampling
clock (DSC), to register the input data on both the rising and
falling edges.
AD9139 WORD MODE
INPUT DATA[15:0]
S1
S2
S3
11744-033
S0
DCI
Figure 28. AD9139 Timing Diagram for Word Mode
BYTE INTERFACE MODE
In byte mode, the required sequence of the input data stream is
S0[15:8], S0[7:0], S1[15:8], S1[7:0], and so forth. A frame signal
is required to align the order of input data bytes properly. Time
align both the DCI signal and frame signal with the data. The
rising edge of the frame indicates the start of the sequence. The
frame can be either a one shot or periodical signal as long as its
first rising edge is correctly captured by the device. For a one
shot frame, the frame pulse must be held at high for at least one
DCI cycle. For a periodical frame, the frequency must be
fDCI/(2 × n)
Figure 29 is an example of signal timing in byte mode.
AD9139 WORD MODE
S0[15:8]
S0[7:0]
S1[15:8]
As shown in Figure 31, the DCI clock edges must be coincident
with the data bit transitions with minimum skew and jitter. The
nominal sampling point of the input data occurs in the middle
of the DCI clock edges because this point corresponds to the
center of the data eye. This is also equivalent to a nominal phase
shift of 90°of the DCI clock.
The data timing requirements are defined by a data valid
window (DVW) that is dependent on the data clock input skew,
input data jitter, and the variations of the DLL delay line across
delay settings. The DVW is defined as
DVW = tDATA PERIOD − tDATA SKEW − tDATA JITTER
The available margin for data interface timing is given by
tMARGIN = DVW − (tS + tH)
The difference of the setup and hold times, which is also called
the keep out window, or KOW, is the area where data transitions
are prohibited. The timing margin allows the user to set the
DLL delay, as shown in Figure 30.
where n is a positive integer, that is, 1, 2, 3, …
INPUT DATA[7:0]
Description
Select between binary and twos
complement formats.
S1[7:0]
11744-034
DCI
FRAME
Figure 29. Timing Diagram for Byte Mode
Rev. A | Page 18 of 56
Data Sheet
AD9139
tH
tDATA JITTER
tS
INPUT DATA
DATA EYE
tDATA PERIOD
DCI
DATA SAMPLE CLOCK
tH + tS
tDCI SKEW
DLL
PHASE
DELAY
tDATA JITTER
DATA EYE
INPUT DATA
tDATA PERIOD
11744-035
DCI
DATA SAMPLE CLOCK
Figure 30. LVDS Data Port Timing Requirements
Figure 30 shows that the ideal location for the DSC signal is 90°
out of phase from the DCI input; however, due to skew of the
DCI relative to the data, it may be necessary to change the DSC
phase offset to sample the data at the center of its eye diagram.
Vary the sampling instance in discrete increments by offsetting the
nominal DLL phase shift value of 90° via Register 0x0A, Bits[3:0].
This register is a signed value. The MSB is the sign and the LSBs
are the magnitude. The following equation defines the phase
offset relationship:
Phase Offset = 90° + n × 11.25°, |n| < 7
where n is the DLL phase offset setting.
Figure 31 shows the DSC setup and hold times with respect to
the DCI signal and data signals.
Table 12 lists the guaranteed values across the operating conditions. These values were obtained using a 50% duty cycle and a
DCI swing of 450 mV p-p. For best performance, maintain a
duty cycle variation below ±5% and set the DCI input as high as
possible, up to 1200 mV p-p.
Table 12. DLL Phase Setup and Hold Times (Guaranteed)
Frequency,
fDCI (MHz)
307
368
491
DATA
614
DCI
tS
tH
11744-036
DSC
Figure 31. LVDS Data Port Setup and Hold Times
Rev. A | Page 19 of 56
Time (ps)
tS
tH
tS
tH
tS
tH
tS
tH
Data Port Setup and Hold Times (ps)
at DLL Phase
−3
0
+3
−125
−385
−695
834
1120
1417
−70
−305
−534
753
967
1207
−81
−245
−402
601
762
928
−54.0
−167
−277
497
603
721
AD9139
Data Sheet
Table 13. DLL Phase Setup and Hold Times (Typical)
Frequency,
fDCI 1
(MHz)
250
275
300
325
350
375
400
425
450
475
500
525
550
575
1
Time
(ps)
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
tS
tH
Data Port Setup and Hold Times (ps) at DLL Phase
−6
−93
468
−87
451
−82
422
−46
405
−23
383
−7
401
−46
385
4
358
11
354
−15
355
9
313
−7
311
−5
300
8
312
−5
−196
579
−172
537
−166
500
−114
483
−92
451
−82
466
−98
445
−52
408
−34
406
−51
399
−28
354
−52
356
−39
340
−28
348
−4
−312
707
−264
646
−256
598
−190
563
−180
524
−150
504
−161
503
−110
465
−92
457
−95
451
−77
399
−100
395
−74
378
−66
379
−3
−416
825
−364
757
−341
703
−271
647
−252
607
−225
569
−243
546
−170
524
−147
516
−147
499
−128
445
−147
438
−107
423
−102
414
−2
−530
947
−464
878
−426
803
−358
740
−328
682
−315
641
−303
604
−229
595
−209
573
−198
556
−183
500
−187
489
−147
468
−143
453
−1
−658
1067
−556
977
−515
897
−447
832
−409
762
−391
718
−384
674
−297
625
−269
637
−255
613
−233
555
−237
537
−192
510
−181
496
0
−770
1188
−653
1092
−622
1000
−538
914
−491
844
−461
783
−448
748
−394
692
−324
693
−313
675
−288
615
−285
592
−249
560
−245
544
+1
−878
1315
−756
1218
−715
1105
−612
1000
−574
930
−526
863
−513
826
−449
762
−386
731
−366
727
−333
668
−335
645
−302
610
−280
599
+2
−983
1442
−859
1311
−809
1203
−706
1100
−654
1011
−595
941
−578
890
−517
829
−446
792
−425
779
−390
726
−387
692
−352
659
−336
654
+3
−1093
1570
−956
1423
−900
1303
−806
1200
−731
1097
−661
1025
−643
965
−579
900
−509
852
−480
815
−438
783
−436
746
−397
710
−366
708
+4
−1193
1697
−1053
1537
−1001
1411
−891
1292
−819
1186
−726
1106
−713
1039
−641
966
−564
917
−530
873
−495
825
−483
799
−440
756
−406
759
+5
−1289
1777
−1151
1653
−1097
1522
−966
1380
−889
1277
−786
1187
−771
1110
−704
1032
−622
983
−585
930
−545
881
−530
850
−486
810
−443
806
+6
−1412
1876
−1251
1728
−1184
1612
−1044
1476
−959
1358
−853
1264
−833
1178
−752
1097
−672
1042
−640
988
−594
934
−581
909
−529
865
−488
847
Table 13 shows characterization data for selected fDCI frequencies. Other frequencies are possible; use Table 13 to estimate performance.
Table 13 shows the typical times for various DCI clock frequencies
that are required to calculate the data valid margin. Use Table 13 to
determine the amount of margin that is available for tuning of
the DSC sampling point.
Maximizing the opening of the eye in both the DCI and data
signals improves the reliability of the data port interface. Use
differential controlled impedance traces of equal length (that is,
delay) between the host processor and the AD9139 input. To
ensure coincident transitions with the data bits, implement the
DCI signal as an additional data line with an alternating
(010101…) bit sequence from the same output drivers that are
used for the data.
The DCI signal is ac-coupled by default; thus, removing the
DCI signal may cause DAC output chatter due to randomness
on the DCI input. To avoid this, disable the DAC output
whenever the DCI signal is not present by setting the DAC output
current power-down bit in Register 0x01[7] to 1. When the DCI
signal is again present, enable the DAC output by programming
Register 0x01[7] to 0.
Register 0x0D optimizes the DLL stability over the operating
frequency range. Table 14 shows the recommended settings.
Table 14. DLL Configuration Options
DCI Speed
≥350 MHz
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