Octal, 10-Bit, 40 MSPS/65 MSPS,
Serial LVDS, 1.8 V ADC
AD9212
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
8 analog-to-digital converters (ADCs) integrated into 1 package
100 mW ADC power per channel at 65 MSPS
SNR = 60.8 dB (to Nyquist)
ENOB = 9.8 bits
SFDR = 80 dBc (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical); INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
325 MHz, full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
DRVDD
AD9212
DRGND
10
VIN + A
VIN – A
ADC
VIN + B
VIN – B
ADC
VIN + C
VIN – C
ADC
VIN + D
VIN – D
ADC
VIN + E
VIN – E
ADC
VIN + F
VIN – F
ADC
VIN + G
VIN – G
ADC
VIN + H
VIN – H
ADC
SERIAL
LVDS
D+A
D–A
SERIAL
LVDS
D+B
D–B
SERIAL
LVDS
D+C
D–C
SERIAL
LVDS
D+D
D–D
SERIAL
LVDS
D+E
D–E
SERIAL
LVDS
D+F
D–F
SERIAL
LVDS
D+G
D–G
SERIAL
LVDS
D+H
D–H
10
10
10
10
10
10
10
VREF
SENSE
APPLICATIONS
FCO+
0.5V
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9212 is an octal, 10-bit, 40 MSPS/65 MSPS ADC with an
on-chip sample-and-hold circuit designed for low cost, low power,
small size, and ease of use. Operating at a conversion rate of up to
65 MSPS, it is optimized for outstanding dynamic performance
and low power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO)
for capturing data on the output and a frame clock (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
Rev. F
PDWN
AVDD
REFT
REFB
REF
SELECT
RBIAS
SERIAL PORT
INTERFACE
AGND CSB
SDIO/
ODM
SCLK/
DTP
DATA RATE
MULTIPLIER
CLK+
CLK–
FCO–
DCO+
DCO–
05968-001
FEATURES
Figure 1.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI).
The AD9212 is available in a RoHS-compliant, 64-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Small Footprint. Eight ADCs are contained in a small package.
Low Power of 100 mW per Channel at 65 MSPS.
Ease of Use. A data clock output (DCO) operates up to
300 MHz and supports double data rate (DDR) operation.
User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
Pin-Compatible Family. This includes the AD9222 (12-bit)
and AD9252 (14-bit).
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700 ©2006–2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9212
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Clock Input Considerations ...................................................... 23
Applications ....................................................................................... 1
Serial Port Interface (SPI) .............................................................. 31
General Description ......................................................................... 1
Hardware Interface..................................................................... 31
Functional Block Diagram .............................................................. 1
Memory Map .................................................................................. 33
Product Highlights ........................................................................... 1
Reading the Memory Map Table .............................................. 33
Revision History ............................................................................... 3
Reserved Locations .................................................................... 33
Specifications..................................................................................... 4
Default Values ............................................................................. 33
AC Specifications.......................................................................... 5
Logic Levels ................................................................................. 33
Digital Specifications ................................................................... 6
Applications Information .............................................................. 36
Switching Specifications .............................................................. 7
Design Guidelines ...................................................................... 36
Timing Diagrams.......................................................................... 8
Evaluation Board ............................................................................ 37
Absolute Maximum Ratings.......................................................... 10
Power Supplies ............................................................................ 37
Thermal Impedance ................................................................... 10
Input Signals................................................................................ 37
ESD Caution ................................................................................ 10
Output Signals ............................................................................ 37
Pin Configuration and Function Descriptions ........................... 11
Default Operation and Jumper Selection Settings ................. 38
Equivalent Circuits ......................................................................... 13
Alternative Analog Input Drive Configuration...................... 39
Typical Performance Characteristics ........................................... 15
Outline Dimensions ....................................................................... 56
Theory of Operation ...................................................................... 20
Ordering Guide .......................................................................... 56
Analog Input Considerations.................................................... 20
Rev. F | Page 2 of 56
Data Sheet
AD9212
REVISION HISTORY
9/2018—Rev. E to Rev. F
Changes to Digital Outputs and Timing Section ........................28
Updated Outline Dimensions ........................................................56
Changes to Ordering Guide ...........................................................56
12/2011—Rev. D to Rev. E
Changes to Output Signals Section and Figure 70......................37
Changed Default Operation and Jumper Selection Settings
Section ..............................................................................................38
Added Endnote 2 in Ordering Guide ...........................................56
5/2010—Rev. C to Rev. D
Deleted LFCSP CP-64-3 Package ..................................... Universal
Changes to output_phase Register, Table 16 ...............................33
Deleted Figure 85; Renumbered Sequentially .............................55
Updated Outline Dimensions ........................................................55
Changes to Ordering Guide ...........................................................55
12/2009—Rev. B to Rev. C
Updated Outline Dimensions ........................................................55
Changes to Ordering Guide ...........................................................56
7/2009—Rev. A to Rev. B
Changes to Figure 5.........................................................................10
Changes to Figure 49 and Figure 50 .............................................21
Changes to Figure 63 and Figure 64 .............................................28
Updated Outline Dimensions ........................................................55
12/07—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Changes to Figure 1........................................................................... 1
Changes to Crosstalk Parameter ..................................................... 3
Changes to Logic Output (SDIO/ODM)........................................ 5
Changes to Figure 2 to Figure 4 ...................................................... 7
Changes to Figure 59 ...................................................................... 24
Changes to Table 9 Endnote .......................................................... 26
Changes to Digital Outputs and Timing Section ........................ 27
Added Table 10 ................................................................................ 27
Changes to Table 11 and Table 12 ................................................. 27
Changes to RBIAS Pin Section ...................................................... 28
Deleted Figure 63 to Figure 66 ...................................................... 28
Moved Figure 65 .............................................................................. 28
Changes to Serial Port Interface (SPI) Section ............................ 30
Changes to Hardware Interface Section ....................................... 30
Changes to Table 15 ........................................................................ 31
Changes to Reading the Memory Map Table Section ................ 32
Added Applications Information and Design Guidelines
Sections ............................................................................................. 35
Changes to Input Signals Section .................................................. 36
Changes to Output Signals Section............................................... 36
Changes to Figure 70 ...................................................................... 36
Changes to Default Operation and Jumper Selection Settings
Section .............................................................................................. 37
Changes to Alternative Analog Input Drive Configuration
Section .............................................................................................. 38
Changes to Figure 73 ...................................................................... 38
Change to Figure 75 ........................................................................ 40
Changes to Figure 76 ...................................................................... 41
Changes to Figure 80 ...................................................................... 45
Changes to Table 17 ........................................................................ 52
Updated Outline Dimensions........................................................ 55
Changes to Ordering Guide ........................................................... 55
10/2006—Revision 0: Initial Version
Rev. F | Page 3 of 56
AD9212
Data Sheet
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1.
Parameter1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Voltage (1 V Mode)
REFERENCE
Output Voltage Error (VREF = 1 V)
Load Regulation at 1.0 mA (VREF = 1 V)
Input Resistance
ANALOG INPUTS
Differential Input Voltage Range (VREF = 1 V)
Common-Mode Voltage
Differential Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
AVDD
DRVDD
IAVDD
IDRVDD
Total Power Dissipation (Including Output Drivers)
Power-Down Dissipation
Standby Dissipation 2
CROSSTALK
AIN = −0.5 dBFS
Overrange 3
Temperature
Min
10
Full
Full
Full
Full
Full
Full
Full
AD9212-40
Typ
Max
Guaranteed
±1.5
±3
±0.4
±0.3
±0.1
±0.15
Full
Full
Full
±2
±17
±21
Full
Full
Full
±2
3
6
Full
Full
Full
Full
2
AVDD/2
7
325
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
Full
Full
1.8
1.8
252
49.5
542
3
83
−90
−90
Min
10
AD9212-65
Typ
Max
Guaranteed
±1.5
±3
±3.2
±0.4
±0.3
±0.4
±8
±8
±1.2
±0.7
±0.4
±0.5
±8
±8
±4.3
±0.9
±0.65
±1
±2
±17
±21
±30
±2
3
6
1.7
1.7
1.8
1.8
390
54
800
3
95
−90
−90
mV
mV
% FS
% FS
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
±30
2
AVDD/2
7
325
1.9
1.9
260
53
560
11
Unit
Bits
mV
mV
kΩ
V p-p
V
pF
MHz
1.9
1.9
405
58
833
11
V
V
mA
mA
mW
mW
mW
dB
dB
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Can be controlled via the SPI.
3
Overrange condition is specific with 6 dB of the full-scale input range.
1
2
Rev. F | Page 4 of 56
Data Sheet
AD9212
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 35 MHz
fIN = 70 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 35 MHz
fIN = 70 MHz
WORST OTHER (EXCLUDING SECOND OR THIRD)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—
AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 15 MHz, fIN2 = 16 MHz
fIN1 = 70 MHz, fIN2 = 71 MHz
1
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
AD9212-40
Min Typ Max
AD9212-65
Min Typ Max
61.2
61.2
61.2
61.0
60.8
60.8
60.8
60.7
dB
dB
dB
dB
60.7
60.6
60.5
60.4
dB
dB
dB
dB
9.81
9.81
9.81
9.79
Bits
Bits
Bits
Bits
81
79
77
77
72
dBc
dBc
dBc
dBc
dBc
−81
−79
−77
−77
−72
dBc
dBc
dBc
dBc
dBc
60.2
60.0
9.71
72
58.5
61.2
61.0
61.0
60.8
57.0
9.87
9.87
9.87
9.84
9.43
87
85
79
62
69
74
Full
Full
Full
25°C
Full
−87
−85
−79
Full
Full
Full
Full
−90
−85
−85
−85
25°C
25°C
80.0
77.0
−72
−74
−72
−86
−86
−85
−85
−62
−69
−70
77.0
77.0
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. F | Page 5 of 56
Unit
dBc
dBc
dBc
dBc
dBc
dBc
AD9212
Data Sheet
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage 2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM) 3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D + x, D − x),
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
1
2
3
AD9212-40
Typ
Max
Temperature
Min
Full
Full
25°C
25°C
250
Full
Full
25°C
25°C
1.2
0
Full
Full
25°C
25°C
1.2
0
Full
Full
25°C
25°C
1.2
0
Full
Full
1.79
Full
Full
247
1.125
Full
Full
150
1.10
AD9212-65
Typ
Max
Min
CMOS/LVDS/LVPECL
CMOS/LVDS/LVPECL
250
1.2
20
1.5
mV p-p
V
kΩ
pF
1.2
20
1.5
3.6
0.3
1.2
30
0.5
3.6
0.3
V
V
kΩ
pF
3.6
0.3
V
V
kΩ
pF
DRVDD + 0.3
0.3
V
V
kΩ
pF
30
0.5
3.6
0.3
1.2
70
0.5
70
0.5
DRVDD + 0.3
0.3
1.2
0
30
2
30
2
1.79
0.05
0.05
LVDS
454
1.375
Offset binary
V
V
LVDS
247
1.125
LVDS
250
1.30
Offset binary
Unit
454
1.375
Offset binary
mV
V
LVDS
150
1.10
250
1.30
Offset binary
mV
V
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
This is specified for LVDS and LVPECL only.
This is specified for 13 SDIO pins sharing the same connection.
Rev. F | Page 6 of 56
Data Sheet
AD9212
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
AD9212-40
Parameter1
CLOCK 2
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
Temp
Min
Full
Full
Full
Full
40
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD) 4
Full
Full
Full
Full
Full
1.5
Typ
AD9212-65
Max
Min
Typ
Max
65
10
10
12.5
12.5
7.7
7.7
DCO to Data Delay (tDATA)4
Full
(tSAMPLE/20) − 300
(tSAMPLE/20) + 300
(tSAMPLE/20) − 300
2.3
300
300
2.3
tFCO +
(tSAMPLE/20)
(tSAMPLE/20)
(tSAMPLE/20) + 300
ps
DCO to FCO Delay (tFRAME)4
Data-to-Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
Full
(tSAMPLE/20) − 300
(tSAMPLE/20)
(tSAMPLE/20) + 300
(tSAMPLE/20) − 300
(tSAMPLE/20)
(tSAMPLE/20) + 300
ps
Full
±50
±200
±50
±200
ps
25°C
25°C
Full
600
375
8
600
375
8
ns
μs
CLK
cycles
25°C
25°C
25°C
750